From gerrit at coreboot.org  Sun Jan  1 03:30:55 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Sun, 1 Jan 2012 03:30:55 +0100
Subject: [coreboot] New patch to review for coreboot: 5e0f452 geos:
	Explicitly set console baud rate
References: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+0@gerrit.coreboot.org>
Message-ID: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/513

-gerrit

commit 5e0f452ec5454d96dbef1f01f557e90306aa96ce
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 31 19:29:21 2011 -0700

    geos: Explicitly set console baud rate
    
    If the default baud rate changes, we should remain compatible with
    earlier published coreboot images.
    
    Change-Id: I4e6b5515395a9de237ad8f758f6f66fb825262eb
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..b455f60 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_1024
 	select POWER_BUTTON_DEFAULT_DISABLE
+	select CONSOLE_SERIAL_115200
 
 config MAINBOARD_DIR
 	string


From hagigatali at gmail.com  Sun Jan  1 09:15:19 2012
From: hagigatali at gmail.com (ali hagigat)
Date: Sun, 1 Jan 2012 11:45:19 +0330
Subject: [coreboot] xgcc folder is not made!
In-Reply-To: <4EFF5906.3080700@coreboot.org>
References: <CAKKWdtftxKJ80VZbiSY+ySCU3v8d5Df3+jwWGRNa-T1DYbvowg@mail.gmail.com>
	<4EFF5906.3080700@coreboot.org>
Message-ID: <CAKKWdte_FhRQw03GcJQ_RqY=Ophhq+VZyBaaq8votPnRZCoNxg@mail.gmail.com>

Thank you for the reply. First please consider the specifications of my machine:

root at sky-desktop:~/coreboot/util/crossgcc# uname -r
2.6.32-36-generic-pae


root at sky-desktop:~/coreboot/util/crossgcc# uname -m
i686


root at sky-desktop:~/coreboot/util/crossgcc# uname -a
Linux sky-desktop 2.6.32-36-generic-pae #79-Ubuntu SMP Tue Nov 8
23:25:26 UTC 2011 i686 GNU/Linux

root at sky-desktop:~# head -n1 /etc/issue
Ubuntu 10.04.3 LTS \n \l

and then the error:

root at sky-desktop:~/coreboot/util/crossgcc# make build-without-gdb
bash ./buildgcc
Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011)

Will skip GDB ... ok
Downloading tar balls ...
 * gmp-5.0.2.tar.bz2 (cached)
 * mpfr-3.1.0.tar.bz2 (cached)
 * mpc-0.9.tar.gz (cached)
 * libelf-0.8.13.tar.gz (cached)
 * gcc-core-4.6.2.tar.bz2 (cached)
 * binutils-2.21.1.tar.bz2 (cached)
 * acpica-unix-20110922.tar.gz (cached)
Downloaded tar balls ... ok
Unpacking and patching ...
Unpacked and patched ... ok
Skipping GMP as it is already built
grep: /root/coreboot/util/crossgcc/xgcc/include/gmp.h: No such file or directory
Skipping MPFR as it is already built
Skipping MPC as it is already built
Skipping libelf as it is already built
Skipping binutils as it is already built
Skipping GCC as it is already built
Skipping Expat (Python scripting not enabled)
Skipping Python (Python scripting not enabled)
Skipping GDB (GDB support not enabled)
Building IASL 20110922 ... failed
make: *** [build-without-gdb] Error 1


and the second scenario:

root at sky-desktop:~/coreboot/util/crossgcc# make
bash ./buildgcc -G
Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011)

Downloading tar balls ...
 * gmp-5.0.2.tar.bz2 (cached)
 * mpfr-3.1.0.tar.bz2 (cached)
 * mpc-0.9.tar.gz (cached)
 * libelf-0.8.13.tar.gz (cached)
 * gcc-core-4.6.2.tar.bz2 (cached)
 * binutils-2.21.1.tar.bz2 (cached)
 * gdb-7.3.1.tar.bz2 (cached)
 * acpica-unix-20110922.tar.gz (cached)
Downloaded tar balls ... ok
Unpacking and patching ...
Unpacked and patched ... ok
Skipping GMP as it is already built
grep: /root/coreboot/util/crossgcc/xgcc/include/gmp.h: No such file or directory
Skipping MPFR as it is already built
Skipping MPC as it is already built
Skipping libelf as it is already built
Skipping binutils as it is already built
Skipping GCC as it is already built
Skipping Expat (Python scripting not enabled)
Skipping Python (Python scripting not enabled)
Building GDB 7.3.1 ... failed
make: *** [build] Error 1



Regards


On Sat, Dec 31, 2011 at 10:18 PM, Stefan Reinauer
<stefan.reinauer at coreboot.org> wrote:
> On 12/31/11 5:00 AM, ali hagigat wrote:
>>
>> I downloaded the coreboot version 4 for a Ubuntu system. When i want to
>> execute
>> util/crossgcc/make
>>
>> It stops complaining that there is an error building GDB!
>> If i want to make without GDB like by buildgcc, it stops , the error
>> is that it can not find one h file in xgcc and iasl can not be made!
>>
>> xgcc folder is not filled! What is the problem?
>>
>> Regards
>>
>> (PS. Besides when i want to compile the source code of coreboot by its
>> makefile, it stops and complains that one symbol has two contradict
>> types.
>
> An error log would be helpful.
>
>
>> Should i run `buildgcc` ?before making the Coreboot source
>> code? )
>
> yes.
>>
>>
> Please update your coreboot checkout to the latest version. GDB is no longer
> built per default due to problems with some Linux distributions.
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


From svn at coreboot.org  Mon Jan  2 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 02 Jan 2012 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RhjMn-0002m2-V9@ra.coresystems.de>

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From martinbarrowcliff at gmail.com  Mon Jan  2 16:35:07 2012
From: martinbarrowcliff at gmail.com (marty)
Date: Mon, 02 Jan 2012 10:35:07 -0500
Subject: [coreboot] please suggest
Message-ID: <4F01CEAB.3040003@gmail.com>

I wish to use coreboot for a firewall design.
I need to have iptables/modules/and drop policy all loaded before 
networking is enabled. I can do the rest from disk.
I will need 2 slots for Ethernet cards.
I need 2G RAM capability.
I prefer a 3.x version Linux kernel.

 From what I see, most BIOS chips seem a bit small for this.
I don't need high-end hardware; domestic stuff is preferred.
Definately no Realtec 8169 however... Gaa...

Can someone please suggest a board(s) that might suit my needs,
and is well supported by coreboot?


Thank you,

Marty B.


From gerrit at coreboot.org  Mon Jan  2 23:10:06 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 2 Jan 2012 23:10:06 +0100
Subject: [coreboot] Patch merged into coreboot/master: 42bde27 F14
	mainboard: update acpi interrupt routing in pic and apic mode
References: <I4b6e0fce8d34637c03de8ebfdadea008c98e193b+0@gerrit.coreboot.org>
Message-ID: <E1Rhq50-00058L-UI@ra.coresystems.de>

the following patch was just integrated into master:
commit 42bde27e1474bd45ef0d727ef7a874f1eebfd3ab
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Dec 22 12:18:37 2011 +0800

    F14 mainboard: update acpi interrupt routing in pic and apic mode
    
    Add interrupt routing for APU GNB internal Graphic and HD audio device, and
    other pcie bridge device in GNB.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>

Build-Tested: build bot (Jenkins) at Thu Dec 22 04:46:42 2011, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Mon Jan  2 23:10:04 2012, giving +2
See http://review.coreboot.org/452 for details.

-gerrit


From gerrit at coreboot.org  Mon Jan  2 23:14:49 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 2 Jan 2012 23:14:49 +0100
Subject: [coreboot] Patch merged into coreboot/master: 1ba80c2 F14
	mainboard: mptable update
References: <Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59+0@gerrit.coreboot.org>
Message-ID: <E1Rhq9Z-0007lr-PT@ra.coresystems.de>

the following patch was just integrated into master:
commit 1ba80c2a084e3403fc7ce06c487e0a97316b668e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Dec 22 12:18:26 2011 +0800

    F14 mainboard: mptable update
    
    Add GNB internal graphic interrupt,
    correct southbridge hd audio device interrupt. and remove the
    dead code already commented out.
    
    south_station, union_station, inagua, persimmon and e350m1 mainboard
    are included herein.
    
    Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>

Build-Tested: build bot (Jenkins) at Thu Dec 22 04:56:30 2011, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Mon Jan  2 23:12:57 2012, giving +2
See http://review.coreboot.org/451 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan  3 02:16:41 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Tue, 3 Jan 2012 02:16:41 +0100
Subject: [coreboot] New patch to review for coreboot: 39a4861 Fix omission
	of EOT maker from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
References: <Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3+0@gerrit.coreboot.org>
Message-ID: <Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3+1@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/514

-gerrit

commit 39a4861b8725618182c5e1f662d56c55ba6cb9b8
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Mon Jan 2 19:11:49 2012 -0600

    Fix omission of EOT maker from commit
    3d1d6bb4ecb15a12f48f871c623882bee9c0c576
    
    Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
---
 util/superiotool/superiotool.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 5583ec5..94918b8 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -247,7 +247,7 @@ static const struct {
 	{probe_idregs_amd,	{0xaa, EOT}},
 #endif
 	{probe_idregs_serverengines,	{0x2e, EOT}},
-	{probe_idregs_infineon,	{0x2e, 0x4e}},
+	{probe_idregs_infineon,	{0x2e, 0x4e, EOT}},
 };
 
 /** Table of functions to print out supported Super I/O chips. */


From gerrit at coreboot.org  Tue Jan  3 02:36:37 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Tue, 3 Jan 2012 02:36:37 +0100
Subject: [coreboot] Patch set updated for coreboot: 098c3a7 Add missing EOT
	marker.
References: <Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3+0@gerrit.coreboot.org>
Message-ID: <Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3+2@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/514

-gerrit

commit 098c3a7c8881934249624d28a6e1889c061d9c35
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Mon Jan 2 19:11:49 2012 -0600

    Add missing EOT marker.
    
    Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
    
    Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
---
 util/superiotool/superiotool.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h
index 5583ec5..94918b8 100644
--- a/util/superiotool/superiotool.h
+++ b/util/superiotool/superiotool.h
@@ -247,7 +247,7 @@ static const struct {
 	{probe_idregs_amd,	{0xaa, EOT}},
 #endif
 	{probe_idregs_serverengines,	{0x2e, EOT}},
-	{probe_idregs_infineon,	{0x2e, 0x4e}},
+	{probe_idregs_infineon,	{0x2e, 0x4e, EOT}},
 };
 
 /** Table of functions to print out supported Super I/O chips. */


From gerrit at coreboot.org  Tue Jan  3 05:26:17 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 3 Jan 2012 05:26:17 +0100
Subject: [coreboot] Patch merged into coreboot/master: 098c3a7 Add missing
	EOT marker.
References: <Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3+0@gerrit.coreboot.org>
Message-ID: <E1Rhvx3-0003rR-LN@ra.coresystems.de>

the following patch was just integrated into master:
commit 098c3a7c8881934249624d28a6e1889c061d9c35
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Mon Jan 2 19:11:49 2012 -0600

    Add missing EOT marker.
    
    Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576
    
    Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
    Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Build-Tested: build bot (Jenkins) at Tue Jan  3 02:47:29 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Tue Jan  3 02:38:27 2012, giving +2
See http://review.coreboot.org/514 for details.

-gerrit


From ahardyx at yahoo.in  Tue Jan  3 12:47:14 2012
From: ahardyx at yahoo.in (Abhinav Hardikar)
Date: Tue, 3 Jan 2012 17:17:14 +0530 (IST)
Subject: [coreboot] I/O ports don't work
Message-ID: <1325591234.63516.YahooMailNeo@web95401.mail.in2.yahoo.com>

Hi there.?

I finally got coreboot working with my mobo in September and now I am back to resolve more issues.?
None of my I/O ports, PCI/ISA slots work. I some how got output from the serial ports. To get the output, I flashed my mobo with coreboot and restarted the PC without losing power. I think because of this the serial ports remained initialized and I got output on minicom on another computer. But when I powered down my PC and started it up again I had no response on minicom.
Is there a solution to this:

http://pastebin.com/r5E2Qnuq?is the output on minicom.


Abhinav
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From ahardyx at yahoo.in  Tue Jan  3 15:21:51 2012
From: ahardyx at yahoo.in (Abhinav Hardikar)
Date: Tue, 3 Jan 2012 19:51:51 +0530 (IST)
Subject: [coreboot] I/O ports don't work
In-Reply-To: <1325591234.63516.YahooMailNeo@web95401.mail.in2.yahoo.com>
References: <1325591234.63516.YahooMailNeo@web95401.mail.in2.yahoo.com>
Message-ID: <1325600511.58911.YahooMailNeo@web95401.mail.in2.yahoo.com>

Ok I forgot to attach my mobo details

Company: Jetway
Model: J7BXAN
NB: 440BX
SB: 82371EB
Super I/O: Winbond W83977EF
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From gerrit at coreboot.org  Wed Jan  4 04:52:17 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 4 Jan 2012 04:52:17 +0100
Subject: [coreboot] New patch to review for coreboot: a2f4c41 Fix Fam14
	mainboard whitespace
References: <I6d63d428dde0a5d9748027e603b03de25d3be472+0@gerrit.coreboot.org>
Message-ID: <I6d63d428dde0a5d9748027e603b03de25d3be472+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/515

-gerrit

commit a2f4c419f0526c66cfc51217baf64729f60affca
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 3 16:02:07 2012 -0700

    Fix Fam14 mainboard whitespace
    
    Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
    changes
    
    Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/acpi_tables.c         |  334 +++++-----
 src/mainboard/amd/inagua/agesawrapper.c        |  855 ++++++++++++------------
 src/mainboard/amd/persimmon/acpi_tables.c      |   44 +-
 src/mainboard/amd/persimmon/agesawrapper.c     |  159 +++---
 src/mainboard/amd/south_station/acpi_tables.c  |  352 +++++-----
 src/mainboard/amd/south_station/agesawrapper.c |  862 ++++++++++++------------
 src/mainboard/amd/union_station/acpi_tables.c  |  352 +++++-----
 src/mainboard/amd/union_station/agesawrapper.c |  862 ++++++++++++------------
 src/mainboard/asrock/e350m1/acpi_tables.c      |  355 +++++-----
 src/mainboard/asrock/e350m1/agesawrapper.c     |  839 ++++++++++++------------
 10 files changed, 2505 insertions(+), 2509 deletions(-)

diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index cc37ed2..6450f35 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -38,15 +38,15 @@ extern u32 apicid_sb800;
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -56,197 +56,197 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
 
-  /* create all subtables for processors */
-  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
-  current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
+	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
 
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
-             IO_APIC_ADDR, 0);
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
+			 IO_APIC_ADDR, 0);
 
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 0, 2, 0);
 
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
 
-  /* create all subtables for processors */
-  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-  current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
-  /* 1: LINT1 connect to NMI */
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+	/* 1: LINT1 connect to NMI */
 
-  return current;
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
 #if 0 // Don't need HPET table.
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
 #endif
 
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy(current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy(current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy(current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+		memcpy(current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+		memcpy(current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy(current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	}
+	else {
+		ssdt = (acpi_header_t *) current;
+		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+		current += ssdt->length;
+		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+		 /* recalculate checksum */
+		ssdt->checksum = 0;
+		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index df5cd1e..727436c 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -39,503 +39,498 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
+VOID *DmiTable		= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
 
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
 
 
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /* Enable MMIO on AMD CPU Address Map Controller */
-
-  /* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00000B00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = 0x00000A03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Set TOM-DFFFFFFF to Node0 Link0. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00DFFF00;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-  PciData = 0x00FFFF00 | 0x80;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-  PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  /* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000013;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/* Enable MMIO on AMD CPU Address Map Controller */
+
+	/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00000B00;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = 0x00000A03;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Set TOM-DFFFFFFF to Node0 Link0. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00DFFF00;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
+	PciData = 0x00FFFF00 | 0x80;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
+	PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000013;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-
-  /* Set ROM cache onto WP to decrease post time */
-  MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-  LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-  MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-  LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/*
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
+	*/
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+
+	/* Set ROM cache onto WP to decrease post time */
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+
+	LibAmdMemFill (&AmdResetParams,
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32					*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+		 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-
-    case PICK_PSTATE:
-      return AcpiPstate;
-
-    case PICK_SRAT:
-      return AcpiSrat;
-
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Data,
-  VOID *ConfigPtr
-  )
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdLateRunApTask (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable       = AmdLateParams.DmiTable;
-  AcpiPstate     = AmdLateParams.AcpiPState;
-  AcpiSrat       = AmdLateParams.AcpiSrat;
-  AcpiSlit       = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib       = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdLateRunApTask (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }
diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c
index 637a304..99a6e88 100644
--- a/src/mainboard/amd/persimmon/acpi_tables.c
+++ b/src/mainboard/amd/persimmon/acpi_tables.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,  MA 02110-1301 USA
  */
 
 #include <console/console.h>
@@ -130,23 +130,23 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* DSDT */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	* DSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
 	dsdt = (acpi_header_t *)current; // it will used by fadt
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:	* DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
 
 	/* FACS */ // it needs 64 bit alignment
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
 	facs = (acpi_facs_t *) current; // it will be used by fadt
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
 	/* FDAT */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	* FADT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
 	current += sizeof(acpi_fadt_t);
 
@@ -157,7 +157,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	 * We explicitly add these tables later on:
 	 */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	* HPET at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
@@ -165,7 +165,7 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* If we want to use HPET Timers Linux wants an MADT */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	* MADT at %lx\n",current);
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
@@ -173,31 +173,31 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SRAT */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	* SRAT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
 	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
 	if (srat != NULL) {
-	memcpy((void *)current, srat, srat->header.length);
-	srat = (acpi_srat_t *) current;
-	//acpi_create_srat(srat);
-	current += srat->header.length;
-	acpi_add_table(rsdp, srat);
+		memcpy((void *)current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
 	}
 
 	/* SLIT */
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:	 * SLIT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
 	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
 	if (slit != NULL) {
-	memcpy((void *)current, slit, slit->header.length);
-	slit = (acpi_slit_t *) current;
-	//acpi_create_slit(slit);
-	current += slit->header.length;
-	acpi_add_table(rsdp, slit);
+		memcpy((void *)current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
 	}
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:	* SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
 		memcpy((void *)current, ssdt, ssdt->length);
@@ -215,7 +215,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:	* SSDT for PState at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 89f171b..55e8488 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -9,17 +9,17 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *							 M O D U L E S	U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -40,52 +40,52 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *					 D E F I N I T I O N S	A N D	M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable	= NULL;
+VOID *DmiTable		= NULL;
 VOID *AcpiPstate	= NULL;
-VOID *AcpiSrat	= NULL;
-VOID *AcpiSlit	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
 
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib	= NULL;
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
 
-/*----------------------------------------------------------------------------------------
- *					T Y P E D E F S	 A N D	 S T R U C T U	R E S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *			 P R O T O T Y P E S	 O F	 L O C A L	 F U	N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *							E X P O R T E D	F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *							L O C A L	F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
 	VOID
 	)
 {
-	AGESA_STATUS				Status;
-	UINT64						MsrReg;
-	UINT32						PciData;
-	PCI_ADDR					PciAddress;
-	AMD_CONFIG_PARAMS			StdHeader;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
@@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio (
 	 */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-	PciData |= 1 << 7;	// set NP (non-posted) bit
+	PciData |= 1 << 7;		// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
 	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
@@ -130,15 +130,15 @@ agesawrapper_amdinitmmio (
 	VOID
 	)
 {
-	AGESA_STATUS				Status;
-	UINT64						MsrReg;
-	UINT32						PciData;
-	PCI_ADDR					PciAddress;
-	AMD_CONFIG_PARAMS			StdHeader;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
 
-	UINT8						BusRangeVal = 0;
-	UINT8						BusNum;
-	UINT8						Index;
+	UINT8				BusRangeVal = 0;
+	UINT8				BusNum;
+	UINT8				Index;
 
 	/*
 	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
@@ -185,14 +185,14 @@ agesawrapper_amdinitreset (
 	AMD_RESET_PARAMS AmdResetParams;
 
 	LibAmdMemFill (&AmdParamStruct,
-				 0,
-				 sizeof (AMD_INTERFACE_PARAMS),
-				 &(AmdParamStruct.StdHeader));
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
 	LibAmdMemFill (&AmdResetParams,
-				 0,
-				 sizeof (AMD_RESET_PARAMS),
-				 &(AmdResetParams.StdHeader));
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
 	AmdParamStruct.AllocationMethod = ByHost;
@@ -218,12 +218,12 @@ agesawrapper_amdinitearly (
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
+	AMD_EARLY_PARAMS		 *AmdEarlyParamsPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-				 0,
-				 sizeof (AMD_INTERFACE_PARAMS),
-				 &(AmdParamStruct.StdHeader));
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -250,14 +250,14 @@ agesawrapper_amdinitpost (
 {
 	AGESA_STATUS status;
 	UINT16					i;
-	UINT32			*HeadPtr;
+	UINT32					*HeadPtr;
 	AMD_INTERFACE_PARAMS	AmdParamStruct;
-	BIOS_HEAP_MANAGER	*BiosManagerPtr;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-				 0,
-				 sizeof (AMD_INTERFACE_PARAMS),
-				 &(AmdParamStruct.StdHeader));
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -275,7 +275,8 @@ agesawrapper_amdinitpost (
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
 		*HeadPtr = 0x00000000;
 		HeadPtr++;
 	}
@@ -296,9 +297,9 @@ agesawrapper_amdinitenv (
 	UINT32				 PciValue;
 
 	LibAmdMemFill (&AmdParamStruct,
-				 0,
-				 sizeof (AMD_INTERFACE_PARAMS),
-				 &(AmdParamStruct.StdHeader));
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -311,7 +312,7 @@ agesawrapper_amdinitenv (
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
-	 Modify D1F0x18
+		 Modify D1F0x18
 	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
@@ -423,9 +424,9 @@ agesawrapper_amdinitmid (
 	agesawrapper_amdinitcpuio ();
 
 	LibAmdMemFill (&AmdParamStruct,
-				 0,
-				 sizeof (AMD_INTERFACE_PARAMS),
-				 &(AmdParamStruct.StdHeader));
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -452,9 +453,9 @@ agesawrapper_amdinitlate (
 	AMD_LATE_PARAMS AmdLateParams;
 
 	LibAmdMemFill (&AmdLateParams,
-				 0,
-				 sizeof (AMD_LATE_PARAMS),
-				 &(AmdLateParams.StdHeader));
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
 
 	AmdLateParams.StdHeader.AltImageBasePtr = 0;
 	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -467,14 +468,14 @@ agesawrapper_amdinitlate (
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable	= AmdLateParams.DmiTable;
-	AcpiPstate	= AmdLateParams.AcpiPState;
-	AcpiSrat	= AmdLateParams.AcpiSrat;
-	AcpiSlit	= AmdLateParams.AcpiSlit;
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
 
-	AcpiWheaMce = AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
-	AcpiAlib	= AmdLateParams.AcpiAlib;
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
 
 	return (UINT32)Status;
 }
@@ -490,9 +491,9 @@ agesawrapper_amdlaterunaptask (
 	AP_EXE_PARAMS ApExeParams;
 
 	LibAmdMemFill (&ApExeParams,
-				 0,
-				 sizeof (AP_EXE_PARAMS),
-				 &(ApExeParams.StdHeader));
+					0,
+					sizeof (AP_EXE_PARAMS),
+					&(ApExeParams.StdHeader));
 
 	ApExeParams.StdHeader.AltImageBasePtr = 0;
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -520,9 +521,9 @@ agesawrapper_amdreadeventlog (
 	EVENT_PARAMS AmdEventParams;
 
 	LibAmdMemFill (&AmdEventParams,
-				 0,
-				 sizeof (EVENT_PARAMS),
-				 &(AmdEventParams.StdHeader));
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
 
 	AmdEventParams.StdHeader.AltImageBasePtr = 0;
 	AmdEventParams.StdHeader.CalloutPtr = NULL;
diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c
index 2a299d8..ae058d6 100644
--- a/src/mainboard/amd/south_station/acpi_tables.c
+++ b/src/mainboard/amd/south_station/acpi_tables.c
@@ -35,15 +35,15 @@
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  /* create all subtables for processors */
-  current = acpi_create_madt_lapics(current);
-
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-             IO_APIC_ADDR, 0);
-
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 9, 9, 0xF);
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
-
-  /* create all subtables for processors */
-  /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-  /* 1: LINT1 connect to NMI */
-
-  return current;
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+						 IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FDAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
-
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy((void *)current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy((void *)current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy((void *)current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-    char *position = ssdt;
-    if (memcmp(position + 50, "TOM1", 4) == 0)
-        *(u32 *)(position + 55) = __readmsr(0xc001001a);
-
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+		memcpy((void *)current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+		memcpy((void *)current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	}
+	else {
+		ssdt = (acpi_header_t *) current;
+		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+		current += ssdt->length;
+		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+		char *position = ssdt;
+		if (memcmp(position + 50, "TOM1", 4) == 0)
+				*(u32 *)(position + 55) = __readmsr(0xc001001a);
+
+	 /* recalculate checksum */
+		ssdt->checksum = 0;
+		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c
index 74aa73d..55e8488 100644
--- a/src/mainboard/amd/south_station/agesawrapper.c
+++ b/src/mainboard/amd/south_station/agesawrapper.c
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -40,502 +40,502 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
-
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
+VOID *DmiTable		= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
+
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
+
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-  
-  /* Enable legacy video routing: D18F1xF4 VGA Enable */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
-  PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-
-  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-   * set to non-posted regions.
-   */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-  PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
-  /* Map the remaining PCI hole as posted MMIO */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
-  /* Send all IO (0000-FFFF) to southbridge. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000003;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/* Enable legacy video routing: D18F1xF4 VGA Enable */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciData = 1;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+	 * set to non-posted regions.
+	 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+	PciData |= 1 << 7;		// set NP (non-posted) bit
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Map the remaining PCI hole as posted MMIO */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00FECF00; // last address before non-posted range
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Send all IO (0000-FFFF) to southbridge. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000003;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-  
-  UINT8                         BusRangeVal = 0;
-  UINT8                         BusNum;
-  UINT8                         Index;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-
-  for (Index = 0; Index < 8; Index++) {
-    BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
-    if (BusNum == 1) {
-      BusRangeVal = Index;
-      break;
-    }
-  }
-
-  MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000ull;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	UINT8				BusRangeVal = 0;
+	UINT8				BusNum;
+	UINT8				Index;
+
+	/*
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
+	*/
+
+	for (Index = 0; Index < 8; Index++) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1) {
+			BusRangeVal = Index;
+			break;
+		}
+	}
+
+	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000ull;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	LibAmdMemFill (&AmdResetParams,
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS		 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32					*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */  
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+		 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-    case PICK_PSTATE:
-      return AcpiPstate;
-    case PICK_SRAT:
-      return AcpiSrat;
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams.DmiTable;
-  AcpiPstate  = AmdLateParams.AcpiPState;
-  AcpiSrat    = AmdLateParams.AcpiSrat;
-  AcpiSlit    = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func, 
-  UINT32 Data, 
-  VOID *ConfigPtr
-  )
+	UINT32 Func,
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AP_EXE_PARAMS ApExeParams;
-
-  LibAmdMemFill (&ApExeParams,
-                 0,
-                 sizeof (AP_EXE_PARAMS),
-                 &(ApExeParams.StdHeader));
-
-  ApExeParams.StdHeader.AltImageBasePtr = 0;
-  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  ApExeParams.StdHeader.Func = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.FunctionNumber = Func;
-  ApExeParams.RelatedDataBlock = ConfigPtr;
-
-  Status = AmdLateRunApTask (&ApExeParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AP_EXE_PARAMS ApExeParams;
+
+	LibAmdMemFill (&ApExeParams,
+					0,
+					sizeof (AP_EXE_PARAMS),
+					&(ApExeParams.StdHeader));
+
+	ApExeParams.StdHeader.AltImageBasePtr = 0;
+	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	ApExeParams.StdHeader.Func = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.FunctionNumber = Func;
+	ApExeParams.RelatedDataBlock = ConfigPtr;
+
+	Status = AmdLateRunApTask (&ApExeParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }
diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c
index 2a299d8..ae058d6 100644
--- a/src/mainboard/amd/union_station/acpi_tables.c
+++ b/src/mainboard/amd/union_station/acpi_tables.c
@@ -35,15 +35,15 @@
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -52,197 +52,197 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  /* create all subtables for processors */
-  current = acpi_create_madt_lapics(current);
-
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-             IO_APIC_ADDR, 0);
-
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 9, 9, 0xF);
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
-
-  /* create all subtables for processors */
-  /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-  /* 1: LINT1 connect to NMI */
-
-  return current;
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+						 IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FDAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
-
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy((void *)current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy((void *)current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy((void *)current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-    char *position = ssdt;
-    if (memcmp(position + 50, "TOM1", 4) == 0)
-        *(u32 *)(position + 55) = __readmsr(0xc001001a);
-
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+		memcpy((void *)current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+		memcpy((void *)current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	}
+	else {
+		ssdt = (acpi_header_t *) current;
+		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+		current += ssdt->length;
+		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+		char *position = ssdt;
+		if (memcmp(position + 50, "TOM1", 4) == 0)
+				*(u32 *)(position + 55) = __readmsr(0xc001001a);
+
+	 /* recalculate checksum */
+		ssdt->checksum = 0;
+		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c
index 74aa73d..55e8488 100644
--- a/src/mainboard/amd/union_station/agesawrapper.c
+++ b/src/mainboard/amd/union_station/agesawrapper.c
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -40,502 +40,502 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
 #define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
-
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
+VOID *DmiTable		= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
+
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
+
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-  
-  /* Enable legacy video routing: D18F1xF4 VGA Enable */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
-  PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-
-  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-   * set to non-posted regions.
-   */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-  PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
-  /* Map the remaining PCI hole as posted MMIO */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-   
-  /* Send all IO (0000-FFFF) to southbridge. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000003;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/* Enable legacy video routing: D18F1xF4 VGA Enable */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciData = 1;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+	 * set to non-posted regions.
+	 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+	PciData |= 1 << 7;		// set NP (non-posted) bit
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Map the remaining PCI hole as posted MMIO */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00FECF00; // last address before non-posted range
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Send all IO (0000-FFFF) to southbridge. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000003;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-  
-  UINT8                         BusRangeVal = 0;
-  UINT8                         BusNum;
-  UINT8                         Index;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-
-  for (Index = 0; Index < 8; Index++) {
-    BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
-    if (BusNum == 1) {
-      BusRangeVal = Index;
-      break;
-    }
-  }
-
-  MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000ull;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); 
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	UINT8				BusRangeVal = 0;
+	UINT8				BusNum;
+	UINT8				Index;
+
+	/*
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
+	*/
+
+	for (Index = 0; Index < 8; Index++) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1) {
+			BusRangeVal = Index;
+			break;
+		}
+	}
+
+	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000ull;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	LibAmdMemFill (&AmdResetParams,
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS		 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32					*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */  
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+		 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-    case PICK_PSTATE:
-      return AcpiPstate;
-    case PICK_SRAT:
-      return AcpiSrat;
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams.DmiTable;
-  AcpiPstate  = AmdLateParams.AcpiPState;
-  AcpiSrat    = AmdLateParams.AcpiSrat;
-  AcpiSlit    = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
-UINT32 
+UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func, 
-  UINT32 Data, 
-  VOID *ConfigPtr
-  )
+	UINT32 Func,
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AP_EXE_PARAMS ApExeParams;
-
-  LibAmdMemFill (&ApExeParams,
-                 0,
-                 sizeof (AP_EXE_PARAMS),
-                 &(ApExeParams.StdHeader));
-
-  ApExeParams.StdHeader.AltImageBasePtr = 0;
-  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  ApExeParams.StdHeader.Func = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.FunctionNumber = Func;
-  ApExeParams.RelatedDataBlock = ConfigPtr;
-
-  Status = AmdLateRunApTask (&ApExeParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AP_EXE_PARAMS ApExeParams;
+
+	LibAmdMemFill (&ApExeParams,
+					0,
+					sizeof (AP_EXE_PARAMS),
+					&(ApExeParams.StdHeader));
+
+	ApExeParams.StdHeader.AltImageBasePtr = 0;
+	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	ApExeParams.StdHeader.Func = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.FunctionNumber = Func;
+	ApExeParams.RelatedDataBlock = ConfigPtr;
+
+	Status = AmdLateRunApTask (&ApExeParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }
diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c
index cd0a996..593ec46 100644
--- a/src/mainboard/asrock/e350m1/acpi_tables.c
+++ b/src/mainboard/asrock/e350m1/acpi_tables.c
@@ -37,15 +37,15 @@
 static void dump_mem(u32 start, u32 end)
 {
 
-  u32 i;
-  print_debug("dump_mem:");
-  for (i = start; i < end; i++) {
-    if ((i & 0xf) == 0) {
-      printk(BIOS_DEBUG, "\n%08x:", i);
-    }
-    printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
-  }
-  print_debug("\n");
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
 }
 #endif
 
@@ -54,198 +54,199 @@ extern const unsigned char AmlCode_ssdt[];
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
-  /* Just a dummy */
-  return current;
+	/* Just a dummy */
+	return current;
 }
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-  /* create all subtables for processors */
-  current = acpi_create_madt_lapics(current);
-
-  /* Write SB800 IOAPIC, only one */
-  current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-             IO_APIC_ADDR, 0);
-
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 0, 2, 0);
-  current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-            current, 0, 9, 9, 0xF);
-  /* 0: mean bus 0--->ISA */
-  /* 0: PIC 0 */
-  /* 2: APIC 2 */
-  /* 5 mean: 0101 --> Edige-triggered, Active high */
-
-  /* create all subtables for processors */
-  /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
-  /* 1: LINT1 connect to NMI */
-
-  return current;
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB800 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 9, 9, 0xF);
+
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
 }
 
 unsigned long acpi_fill_slit(unsigned long current)
 {
-  // Not implemented
-  return current;
+	// Not implemented
+	return current;
 }
 
 unsigned long acpi_fill_srat(unsigned long current)
 {
-  /* No NUMA, no SRAT */
-  return current;
+	/* No NUMA, no SRAT */
+	return current;
 }
 
 unsigned long write_acpi_tables(unsigned long start)
 {
-  unsigned long current;
-  acpi_rsdp_t *rsdp;
-  acpi_rsdt_t *rsdt;
-  acpi_hpet_t *hpet;
-  acpi_madt_t *madt;
-  acpi_srat_t *srat;
-  acpi_slit_t *slit;
-  acpi_fadt_t *fadt;
-  acpi_facs_t *facs;
-  acpi_header_t *dsdt;
-  acpi_header_t *ssdt;
-
-  get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
-
-  /* Align ACPI tables to 16 bytes */
-  start = (start + 0x0f) & -0x10;
-  current = start;
-
-  printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
-
-  /* We need at least an RSDP and an RSDT Table */
-  rsdp = (acpi_rsdp_t *) current;
-  current += sizeof(acpi_rsdp_t);
-  rsdt = (acpi_rsdt_t *) current;
-  current += sizeof(acpi_rsdt_t);
-
-  /* clear all table memory */
-  memset((void *)start, 0, current - start);
-
-  acpi_write_rsdp(rsdp, rsdt, NULL);
-  acpi_write_rsdt(rsdt);
-
-  /*
-   * We explicitly add these tables later on:
-   */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
-  hpet = (acpi_hpet_t *) current;
-  current += sizeof(acpi_hpet_t);
-  acpi_create_hpet(hpet);
-  acpi_add_table(rsdp, hpet);
-
-  /* If we want to use HPET Timers Linux wants an MADT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
-  madt = (acpi_madt_t *) current;
-  acpi_create_madt(madt);
-  current += madt->header.length;
-  acpi_add_table(rsdp, madt);
-
-  /* SRAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-  srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-  if (srat != NULL) {
-    memcpy(current, srat, srat->header.length);
-    srat = (acpi_srat_t *) current;
-    //acpi_create_srat(srat);
-    current += srat->header.length;
-    acpi_add_table(rsdp, srat);
-  }
-
-  /* SLIT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-  slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-  if (slit != NULL) {
-    memcpy(current, slit, slit->header.length);
-    slit = (acpi_slit_t *) current;
-    //acpi_create_slit(slit);
-    current += slit->header.length;
-    acpi_add_table(rsdp, slit);
-  }
-
-  /* SSDT */
-  current   = ( current + 0x0f) & -0x10;
-  printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-  ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-  if (ssdt != NULL) {
-    memcpy(current, ssdt, ssdt->length);
-    ssdt = (acpi_header_t *) current;
-    current += ssdt->length;
-  }
-  else {
-    ssdt = (acpi_header_t *) current;
-    memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-    current += ssdt->length;
-    memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-
-    char *position = ssdt;
-    if (memcmp (position + 50, "TOM1", 4) == 0)
-        *(u32 *) (position + 55) = __readmsr (0xc001001a);
-
-   /* recalculate checksum */
-    ssdt->checksum = 0;
-    ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
-  }
-  acpi_add_table(rsdp,ssdt);
-
-  printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
-
-  /* DSDT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-  dsdt = (acpi_header_t *)current; // it will used by fadt
-  memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-  current += dsdt->length;
-  memcpy(dsdt, &AmlCode, dsdt->length);
-  printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-  /* FACS */ // it needs 64 bit alignment
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-  facs = (acpi_facs_t *) current; // it will be used by fadt
-  current += sizeof(acpi_facs_t);
-  acpi_create_facs(facs);
-
-  /* FDAT */
-  current   = ( current + 0x07) & -0x08;
-  printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-  fadt = (acpi_fadt_t *) current;
-  current += sizeof(acpi_fadt_t);
-
-  acpi_create_fadt(fadt, facs, dsdt);
-  acpi_add_table(rsdp, fadt);
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	* We explicitly add these tables later on:
+	*/
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+	memcpy(current, srat, srat->header.length);
+	srat = (acpi_srat_t *) current;
+	//acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+	memcpy(current, slit, slit->header.length);
+	slit = (acpi_slit_t *) current;
+	//acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current   = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+	memcpy(current, ssdt, ssdt->length);
+	ssdt = (acpi_header_t *) current;
+	current += ssdt->length;
+	}
+	else {
+	ssdt = (acpi_header_t *) current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+
+	char *position = ssdt;
+	if (memcmp (position + 50, "TOM1", 4) == 0)
+	*(u32 *) (position + 55) = __readmsr (0xc001001a);
+
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	}
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+
+	/* DSDT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FDAT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
 
 #if DUMP_ACPI_TABLES == 1
-  printk(BIOS_DEBUG, "rsdp\n");
-  dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
 
-  printk(BIOS_DEBUG, "rsdt\n");
-  dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
 
-  printk(BIOS_DEBUG, "madt\n");
-  dump_mem(madt, ((void *)madt) + madt->header.length);
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
 
-  printk(BIOS_DEBUG, "srat\n");
-  dump_mem(srat, ((void *)srat) + srat->header.length);
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
 
-  printk(BIOS_DEBUG, "slit\n");
-  dump_mem(slit, ((void *)slit) + slit->header.length);
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
 
-  printk(BIOS_DEBUG, "ssdt\n");
-  dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
-  printk(BIOS_DEBUG, "fadt\n");
-  dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
 
-  printk(BIOS_INFO, "ACPI: done.\n");
-  return current;
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
 }
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 7fc2fd6..8ecc885 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -17,9 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-/*----------------------------------------------------------------------------------------
- *                             M O D U L E S    U S E D
- *----------------------------------------------------------------------------------------
+/*-----------------------------------------------------------------------------
+ *						M O D U L E S		U S E D
+ *-----------------------------------------------------------------------------
  */
 
 #include <stdint.h>
@@ -39,490 +39,489 @@
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
-/*----------------------------------------------------------------------------------------
- *                   D E F I N I T I O N S    A N D    M A C R O S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *					D E F I N I T I O N S		A N D		M A C R O S
+ *------------------------------------------------------------------------------
  */
 
-/* ACPI table pointers returned by AmdInitLate */
-VOID *DmiTable    = NULL;
-VOID *AcpiPstate  = NULL;
-VOID *AcpiSrat    = NULL;
-VOID *AcpiSlit    = NULL;
-
-VOID *AcpiWheaMce = NULL;
-VOID *AcpiWheaCmc = NULL;
-VOID *AcpiAlib    = NULL;
 
-
-/*----------------------------------------------------------------------------------------
- *                  T Y P E D E F S     A N D     S T R U C T U  R E S
- *----------------------------------------------------------------------------------------
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable		= NULL;
+VOID *AcpiPstate	= NULL;
+VOID *AcpiSrat		= NULL;
+VOID *AcpiSlit		= NULL;
+
+VOID *AcpiWheaMce	= NULL;
+VOID *AcpiWheaCmc	= NULL;
+VOID *AcpiAlib		= NULL;
+
+/*------------------------------------------------------------------------------
+ *				T Y P E D E F S		 A N D		 S T R U C T U R E S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *	P R O T O T Y P E S		 O F		 L O C A L		 F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*----------------------------------------------------------------------------------------
- *                          E X P O R T E D    F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						E X P O R T E D		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 
-/*---------------------------------------------------------------------------------------
- *                          L O C A L    F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/*------------------------------------------------------------------------------
+ *						L O C A L		F U N C T I O N S
+ *------------------------------------------------------------------------------
  */
 UINT32
 agesawrapper_amdinitcpuio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /* Enable legacy video routing: D18F1xF4 VGA Enable */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
-  PciData = 1;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
-   * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
-   * set to non-posted regions.
-   */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-  PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-  PciData |= 1 << 7;    // set NP (non-posted) bit
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-  PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Map the remaining PCI hole as posted MMIO */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-  PciData = 0x00FECF00; // last address before non-posted range
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
-  MsrReg = (MsrReg >> 8) | 3;
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
-  PciData = (UINT32)MsrReg;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  /* Send all IO (0000-FFFF) to southbridge. */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
-  PciData = 0x0000F000;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-  PciData = 0x00000003;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/* Enable legacy video routing: D18F1xF4 VGA Enable */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciData = 1;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+	 * set to non-posted regions.
+	 */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+	PciData |= 1 << 7;		// set NP (non-posted) bit
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Map the remaining PCI hole as posted MMIO */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciData = 0x00FECF00; // last address before non-posted range
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+	MsrReg = (MsrReg >> 8) | 3;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciData = (UINT32)MsrReg;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Send all IO (0000-FFFF) to southbridge. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciData = 0x0000F000;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciData = 0x00000003;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitmmio (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS                  Status;
-  UINT64                        MsrReg;
-  UINT32                        PciData;
-  PCI_ADDR                      PciAddress;
-  AMD_CONFIG_PARAMS             StdHeader;
-
-  /*
-   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-   Address MSR register.
-  */
-
-  MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-  LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
-
-  /*
-   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-  */
-  LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-  MsrReg = MsrReg | 0x0000400000000000;
-  LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
-
-  /* Set Ontario Link Data */
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
-  PciData = 0x01308002;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-  PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
-  PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
-  LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-  Status = AGESA_SUCCESS;
-  return (UINT32)Status;
+	AGESA_STATUS		Status;
+	UINT64				MsrReg;
+	UINT32				PciData;
+	PCI_ADDR			PciAddress;
+	AMD_CONFIG_PARAMS	StdHeader;
+
+	/*
+	Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	Address MSR register.
+	*/
+
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	*/
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | 0x0000400000000000;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set Ontario Link Data */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE0);
+	PciData = 0x01308002;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0xE4);
+	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdinitreset (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_RESET_PARAMS AmdResetParams;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-
-  LibAmdMemFill (&AmdResetParams,
-                 0,
-                 sizeof (AMD_RESET_PARAMS),
-                 &(AmdResetParams.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-  AmdParamStruct.AllocationMethod = ByHost;
-  AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-  AmdParamStruct.NewStructPtr = &AmdResetParams;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = NULL;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  AmdResetParams.HtConfig.Depth = 0;
-
-  status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	LibAmdMemFill (&AmdResetParams,
+					0,
+					sizeof (AMD_RESET_PARAMS),
+					&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
  }
 
 UINT32
 agesawrapper_amdinitearly (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-
-  AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
-  OemCustomizeInitEarly (AmdEarlyParamsPtr);
-
-  status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS		 *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitpost (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  UINT16                  i;
-  UINT32          *HeadPtr;
-  AMD_INTERFACE_PARAMS  AmdParamStruct;
-  BIOS_HEAP_MANAGER    *BiosManagerPtr;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-  AmdParamStruct.AllocationMethod = PreMemHeap;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
-  /* Initialize heap space */
-  BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
-
-  HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-  for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-  {
-    *HeadPtr = 0x00000000;
-    HeadPtr++;
-  }
-  BiosManagerPtr->StartOfAllocatedNodes = 0;
-  BiosManagerPtr->StartOfFreedNodes = 0;
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	UINT16					i;
+	UINT32					*HeadPtr;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	BIOS_HEAP_MANAGER		*BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+	*HeadPtr = 0x00000000;
+	HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitenv (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
-  PCI_ADDR             PciAddress;
-  UINT32               PciValue;
-
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
-
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
-  AmdCreateStruct (&AmdParamStruct);
-  status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  /* Initialize Subordinate Bus Number and Secondary Bus Number
-   * In platform BIOS this address is allocated by PCI enumeration code
-     Modify D1F0x18
-   */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-  /* Write to D1F0x18 */
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x00010100;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Legacy Bridge Mode
-  *  Modify B1D5F0x18
-  */
-  PciAddress.Address.Bus = 1;
-  PciAddress.Address.Device = 5;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Legacy Bridge Mode
-  * Modify B1D5F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize GMM Base Address for Pcie Mode
-  *  Modify B0D1F0x18
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x18;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize FB Base Address for Pcie Mode
-  *  Modify B0D1F0x10
-  */
-  PciAddress.Address.Register = 0x10;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x80000000;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-
-  /* Initialize MMIO Base and Limit Address
-  *  Modify B0D1F0x20
-  */
-  PciAddress.Address.Bus = 0;
-  PciAddress.Address.Device = 1;
-  PciAddress.Address.Function = 0;
-  PciAddress.Address.Register = 0x20;
-
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x96009600;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-
-  /* Initialize MMIO Prefetchable Memory Limit and Base
-  *  Modify B0D1F0x24
-  */
-  PciAddress.Address.Register = 0x24;
-  LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  PciValue |= 0x8FF18001;
-  LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
-  AmdReleaseStruct (&AmdParamStruct);
-
-  return (UINT32)status;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR			 PciAddress;
+	UINT32				 PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	/* Initialize Subordinate Bus Number and Secondary Bus Number
+	 * In platform BIOS this address is allocated by PCI enumeration code
+		 Modify D1F0x18
+	 */
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+	/* Write to D1F0x18 */
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x00010100;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Legacy Bridge Mode
+	*	Modify B1D5F0x18
+	*/
+	PciAddress.Address.Bus = 1;
+	PciAddress.Address.Device = 5;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Legacy Bridge Mode
+	* Modify B1D5F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize GMM Base Address for Pcie Mode
+	*	Modify B0D1F0x18
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x18;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize FB Base Address for Pcie Mode
+	*	Modify B0D1F0x10
+	*/
+	PciAddress.Address.Register = 0x10;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x80000000;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Base and Limit Address
+	*	Modify B0D1F0x20
+	*/
+	PciAddress.Address.Bus = 0;
+	PciAddress.Address.Device = 1;
+	PciAddress.Address.Function = 0;
+	PciAddress.Address.Register = 0x20;
+
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x96009600;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+
+	/* Initialize MMIO Prefetchable Memory Limit and Base
+	*	Modify B0D1F0x24
+	*/
+	PciAddress.Address.Register = 0x24;
+	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	PciValue |= 0x8FF18001;
+	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
 }
 
 VOID *
 agesawrapper_getlateinitptr (
-  int pick
-  )
+	int pick
+	)
 {
-  switch (pick) {
-    case PICK_DMI:
-      return DmiTable;
-    case PICK_PSTATE:
-      return AcpiPstate;
-    case PICK_SRAT:
-      return AcpiSrat;
-    case PICK_SLIT:
-      return AcpiSlit;
-    case PICK_WHEA_MCE:
-      return AcpiWheaMce;
-    case PICK_WHEA_CMC:
-      return AcpiWheaCmc;
-    case PICK_ALIB:
-      return AcpiAlib;
-    default:
-      return NULL;
-  }
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+		case PICK_PSTATE:
+			return AcpiPstate;
+		case PICK_SRAT:
+			return AcpiSrat;
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
 }
 
 UINT32
 agesawrapper_amdinitmid (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS status;
-  AMD_INTERFACE_PARAMS AmdParamStruct;
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
 
-  /* Enable MMIO on AMD CPU Address Map Controller */
-  agesawrapper_amdinitcpuio ();
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
 
-  LibAmdMemFill (&AmdParamStruct,
-                 0,
-                 sizeof (AMD_INTERFACE_PARAMS),
-                 &(AmdParamStruct.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+					0,
+					sizeof (AMD_INTERFACE_PARAMS),
+					&(AmdParamStruct.StdHeader));
 
-  AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-  AmdParamStruct.AllocationMethod = PostMemDram;
-  AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-  AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdParamStruct.StdHeader.Func = 0;
-  AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-  AmdCreateStruct (&AmdParamStruct);
+	AmdCreateStruct (&AmdParamStruct);
 
-  status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
-  if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
-  AmdReleaseStruct (&AmdParamStruct);
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
 
-  return (UINT32)status;
+	return (UINT32)status;
 }
 
 UINT32
 agesawrapper_amdinitlate (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  AMD_LATE_PARAMS AmdLateParams;
-
-  LibAmdMemFill (&AmdLateParams,
-                 0,
-                 sizeof (AMD_LATE_PARAMS),
-                 &(AmdLateParams.StdHeader));
-
-  AmdLateParams.StdHeader.AltImageBasePtr = 0;
-  AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  AmdLateParams.StdHeader.Func = 0;
-  AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-  Status = AmdInitLate (&AmdLateParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  DmiTable    = AmdLateParams.DmiTable;
-  AcpiPstate  = AmdLateParams.AcpiPState;
-  AcpiSrat    = AmdLateParams.AcpiSrat;
-  AcpiSlit    = AmdLateParams.AcpiSlit;
-
-  AcpiWheaMce = AmdLateParams.AcpiWheaMce;
-  AcpiWheaCmc = AmdLateParams.AcpiWheaCmc;
-  AcpiAlib    = AmdLateParams.AcpiAlib;
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+					0,
+					sizeof (AMD_LATE_PARAMS),
+					&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdInitLate (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	DmiTable		= AmdLateParams.DmiTable;
+	AcpiPstate		= AmdLateParams.AcpiPState;
+	AcpiSrat		= AmdLateParams.AcpiSrat;
+	AcpiSlit		= AmdLateParams.AcpiSlit;
+
+	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
+	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
+	AcpiAlib		= AmdLateParams.AcpiAlib;
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdlaterunaptask (
-  UINT32 Func,
-  UINT32 Data,
-  VOID *ConfigPtr
-  )
+	UINT32 Func,
+	UINT32 Data,
+	VOID *ConfigPtr
+	)
 {
-  AGESA_STATUS Status;
-  AP_EXE_PARAMS ApExeParams;
-
-  LibAmdMemFill (&ApExeParams,
-                 0,
-                 sizeof (AP_EXE_PARAMS),
-                 &(ApExeParams.StdHeader));
-
-  ApExeParams.StdHeader.AltImageBasePtr = 0;
-  ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-  ApExeParams.StdHeader.Func = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.StdHeader.ImageBasePtr = 0;
-  ApExeParams.FunctionNumber = Func;
-  ApExeParams.RelatedDataBlock = ConfigPtr;
-
-  Status = AmdLateRunApTask (&ApExeParams);
-  if (Status != AGESA_SUCCESS) {
-    agesawrapper_amdreadeventlog();
-    ASSERT(Status == AGESA_SUCCESS);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	AP_EXE_PARAMS ApExeParams;
+
+	LibAmdMemFill (&ApExeParams,
+					0,
+					sizeof (AP_EXE_PARAMS),
+					&(ApExeParams.StdHeader));
+
+	ApExeParams.StdHeader.AltImageBasePtr = 0;
+	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	ApExeParams.StdHeader.Func = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.FunctionNumber = Func;
+	ApExeParams.RelatedDataBlock = ConfigPtr;
+
+	Status = AmdLateRunApTask (&ApExeParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdreadeventlog (
-  VOID
-  )
+	VOID
+	)
 {
-  AGESA_STATUS Status;
-  EVENT_PARAMS AmdEventParams;
-
-  LibAmdMemFill (&AmdEventParams,
-                 0,
-                 sizeof (EVENT_PARAMS),
-                 &(AmdEventParams.StdHeader));
-
-  AmdEventParams.StdHeader.AltImageBasePtr = 0;
-  AmdEventParams.StdHeader.CalloutPtr = NULL;
-  AmdEventParams.StdHeader.Func = 0;
-  AmdEventParams.StdHeader.ImageBasePtr = 0;
-  Status = AmdReadEventLog (&AmdEventParams);
-  while (AmdEventParams.EventClass != 0) {
-    printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-    printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-    printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-    Status = AmdReadEventLog (&AmdEventParams);
-  }
-
-  return (UINT32)Status;
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+					0,
+					sizeof (EVENT_PARAMS),
+					&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+	printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+	printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+	printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+	Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
 }


From gerrit at coreboot.org  Wed Jan  4 04:52:18 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 4 Jan 2012 04:52:18 +0100
Subject: [coreboot] New patch to review for coreboot: a750360 Clean up AMD
	Fam14 SSDT
References: <I808c863597e024e3e8aeec0821e8618d96cc96a6+0@gerrit.coreboot.org>
Message-ID: <I808c863597e024e3e8aeec0821e8618d96cc96a6+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/516

-gerrit

commit a750360f845cebbd5a798d79b567b9ebd5d00003
Author: Marc Jones <marcj303 at gmail.com>
Date:   Mon Dec 12 21:12:43 2011 -0700

    Clean up AMD Fam14 SSDT
    
    The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
    include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
    for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
    fixes some ACPI errors in Linux and Windows bluescreens.
    
    The Persimmon acpi_tables.c is where the main changes were made and then
    replicated in the other Fam14 boards. Please test the other mainbords if you
    have one.
    
    Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/acpi_tables.c          |   84 ++++--
 src/mainboard/amd/persimmon/acpi/ssdt2.asl      |   84 ------
 src/mainboard/amd/persimmon/acpi/ssdt3.asl      |   84 ------
 src/mainboard/amd/persimmon/acpi/ssdt4.asl      |   84 ------
 src/mainboard/amd/persimmon/acpi/ssdt5.asl      |   85 ------
 src/mainboard/amd/persimmon/acpi_tables.c       |   59 +++-
 src/mainboard/amd/south_station/acpi_tables.c   |   74 ++++--
 src/mainboard/amd/union_station/acpi_tables.c   |   74 ++++--
 src/mainboard/asrock/e350m1/acpi_tables.c       |  158 ++++++-----
 src/northbridge/amd/agesa/family14/Makefile.inc |    2 -
 src/northbridge/amd/agesa/family14/ssdt.asl     |  346 -----------------------
 11 files changed, 287 insertions(+), 847 deletions(-)

diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 6450f35..74df922 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -21,17 +21,14 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
-#include <arch/io.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-
 #include "agesawrapper.h"
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam14.h>
 
 #define DUMP_ACPI_TABLES 0
-extern u32 apicid_sb800;
-
 
 #if DUMP_ACPI_TABLES == 1
 
@@ -51,8 +48,29 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
 
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -62,17 +80,17 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
-
 	/* create all subtables for processors */
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
-	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 1);
+	current = acpi_create_madt_lapics(current);
 
 	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, apicid_sb800,
-			 IO_APIC_ADDR, 0);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 			current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+			current, 0, 9, 9, 0xF);
 
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */
@@ -80,8 +98,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	/* 5 mean: 0101 --> Edige-triggered, Active high */
 
 	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
 	/* 1: LINT1 connect to NMI */
 
 	return current;
@@ -112,6 +129,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -136,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* DSDT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
+	dsdt = (acpi_header_t *)current;
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
@@ -145,7 +163,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* FACS */ // it needs 64 bit alignment
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
-	facs = (acpi_facs_t *) current; // it will be used by fadt
+	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
@@ -161,14 +179,12 @@ unsigned long write_acpi_tables(unsigned long start)
 	/*
 	 * We explicitly add these tables later on:
 	 */
-#if 0 // Don't need HPET table.
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
-#endif
 
 	/* If we want to use HPET Timers Linux wants an MADT */
 	current	 = ( current + 0x07) & -0x08;
@@ -183,46 +199,49 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
 	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
 	if (srat != NULL) {
-		memcpy(current, srat, srat->header.length);
+		memcpy((void *)current, srat, srat->header.length);
 		srat = (acpi_srat_t *) current;
-		//acpi_create_srat(srat);
 		current += srat->header.length;
 		acpi_add_table(rsdp, srat);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
+	}
 
 	/* SLIT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
 	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
 	if (slit != NULL) {
-		memcpy(current, slit, slit->header.length);
+		memcpy((void *)current, slit, slit->header.length);
 		slit = (acpi_slit_t *) current;
-		//acpi_create_slit(slit);
 		current += slit->header.length;
 		acpi_add_table(rsdp, slit);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
+	}
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
-		memcpy(current, ssdt, ssdt->length);
+		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
 	}
 	else {
-		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		 /* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
@@ -243,6 +262,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
+	printk(BIOS_DEBUG, "ssdt2\n");
+	dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
 	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
diff --git a/src/mainboard/amd/persimmon/acpi/ssdt2.asl b/src/mainboard/amd/persimmon/acpi/ssdt2.asl
deleted file mode 100644
index ef1a4bf..0000000
--- a/src/mainboard/amd/persimmon/acpi/ssdt2.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-		// BUS ? Second HT Chain
-		Name (HCIN, 0xcc)  // HC2 0x01
-
-		Name (_UID,	 0xdd)	// HC 0x03
-
-		Name (_HID, "PNP0A03")
-
-		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-		{
-			Return (DADD(GHCN(HCIN), 0x00000000))
-		}
-
-		Method (_BBN, 0, NotSerialized)
-		{
-			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-		}
-
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (\_SB.GHCE(HCIN))
-		}
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Name (BUF0, ResourceTemplate () { })
-			Store( GHCN(HCIN), Local4)
-			Store( GHCL(HCIN), Local5)
-
-			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-			Return (Local3)
-		}
-
-			#include "acpi/pci2_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/persimmon/acpi/ssdt3.asl b/src/mainboard/amd/persimmon/acpi/ssdt3.asl
deleted file mode 100644
index 68a4b95..0000000
--- a/src/mainboard/amd/persimmon/acpi/ssdt3.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci3_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/persimmon/acpi/ssdt4.asl b/src/mainboard/amd/persimmon/acpi/ssdt4.asl
deleted file mode 100644
index e06fe8a..0000000
--- a/src/mainboard/amd/persimmon/acpi/ssdt4.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci4_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/persimmon/acpi/ssdt5.asl b/src/mainboard/amd/persimmon/acpi/ssdt5.asl
deleted file mode 100644
index a141a37..0000000
--- a/src/mainboard/amd/persimmon/acpi/ssdt5.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-	External (DADD, MethodObj)
-	External (GHCE, MethodObj)
-	External (GHCN, MethodObj)
-	External (GHCL, MethodObj)
-	External (GHCD, MethodObj)
-	External (GNUS, MethodObj)
-	External (GIOR, MethodObj)
-	External (GMEM, MethodObj)
-	External (GWBN, MethodObj)
-	External (GBUS, MethodObj)
-
-	External (PICF)
-
-	External (\_SB.PCI0.LNKA, DeviceObj)
-	External (\_SB.PCI0.LNKB, DeviceObj)
-	External (\_SB.PCI0.LNKC, DeviceObj)
-	External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci5_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c
index 99a6e88..47e35af 100644
--- a/src/mainboard/amd/persimmon/acpi_tables.c
+++ b/src/mainboard/amd/persimmon/acpi_tables.c
@@ -48,7 +48,29 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -107,6 +129,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -131,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* DSDT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
+	dsdt = (acpi_header_t *)current;
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
@@ -140,11 +163,11 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* FACS */ // it needs 64 bit alignment
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
-	facs = (acpi_facs_t *) current; // it will be used by fadt
+	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
@@ -178,10 +201,12 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (srat != NULL) {
 		memcpy((void *)current, srat, srat->header.length);
 		srat = (acpi_srat_t *) current;
-		//acpi_create_srat(srat);
 		current += srat->header.length;
 		acpi_add_table(rsdp, srat);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
+	}
 
 	/* SLIT */
 	current	 = ( current + 0x07) & -0x08;
@@ -190,14 +215,16 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (slit != NULL) {
 		memcpy((void *)current, slit, slit->header.length);
 		slit = (acpi_slit_t *) current;
-		//acpi_create_slit(slit);
 		current += slit->header.length;
 		acpi_add_table(rsdp, slit);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
+	}
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
 		memcpy((void *)current, ssdt, ssdt->length);
@@ -205,17 +232,16 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += ssdt->length;
 	}
 	else {
-		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		 /* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
@@ -236,6 +262,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
+	printk(BIOS_DEBUG, "ssdt2\n");
+	dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
 	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c
index ae058d6..74df922 100644
--- a/src/mainboard/amd/south_station/acpi_tables.c
+++ b/src/mainboard/amd/south_station/acpi_tables.c
@@ -48,7 +48,29 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -62,13 +84,14 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics(current);
 
 	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-						 IO_APIC_ADDR, 0);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
+			current, 0, 0, 2, 0);
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
+			current, 0, 9, 9, 0xF);
+
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */
 	/* 2: APIC 2 */
@@ -106,6 +129,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -130,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* DSDT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
+	dsdt = (acpi_header_t *)current;
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
@@ -138,12 +162,12 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* FACS */ // it needs 64 bit alignment
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-	facs = (acpi_facs_t *) current; // it will be used by fadt
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
@@ -177,10 +201,12 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (srat != NULL) {
 		memcpy((void *)current, srat, srat->header.length);
 		srat = (acpi_srat_t *) current;
-		//acpi_create_srat(srat);
 		current += srat->header.length;
 		acpi_add_table(rsdp, srat);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
+	}
 
 	/* SLIT */
 	current	 = ( current + 0x07) & -0x08;
@@ -189,14 +215,16 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (slit != NULL) {
 		memcpy((void *)current, slit, slit->header.length);
 		slit = (acpi_slit_t *) current;
-		//acpi_create_slit(slit);
 		current += slit->header.length;
 		acpi_add_table(rsdp, slit);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
+	}
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
 		memcpy((void *)current, ssdt, ssdt->length);
@@ -204,21 +232,16 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += ssdt->length;
 	}
 	else {
-		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		char *position = ssdt;
-		if (memcmp(position + 50, "TOM1", 4) == 0)
-				*(u32 *)(position + 55) = __readmsr(0xc001001a);
-
-	 /* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
@@ -239,6 +262,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
+	printk(BIOS_DEBUG, "ssdt2\n");
+	dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
 	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c
index ae058d6..74df922 100644
--- a/src/mainboard/amd/union_station/acpi_tables.c
+++ b/src/mainboard/amd/union_station/acpi_tables.c
@@ -48,7 +48,29 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -62,13 +84,14 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics(current);
 
 	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-						 IO_APIC_ADDR, 0);
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
+			current, 0, 0, 2, 0);
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
+			current, 0, 9, 9, 0xF);
+
 	/* 0: mean bus 0--->ISA */
 	/* 0: PIC 0 */
 	/* 2: APIC 2 */
@@ -106,6 +129,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -130,7 +154,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* DSDT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
+	dsdt = (acpi_header_t *)current;
 	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
 	current += dsdt->length;
 	memcpy(dsdt, &AmlCode, dsdt->length);
@@ -138,12 +162,12 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* FACS */ // it needs 64 bit alignment
 	current	 = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-	facs = (acpi_facs_t *) current; // it will be used by fadt
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	acpi_create_facs(facs);
 
-	/* FDAT */
+	/* FADT */
 	current	 = ( current + 0x07) & -0x08;
 	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
@@ -177,10 +201,12 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (srat != NULL) {
 		memcpy((void *)current, srat, srat->header.length);
 		srat = (acpi_srat_t *) current;
-		//acpi_create_srat(srat);
 		current += srat->header.length;
 		acpi_add_table(rsdp, srat);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
+	}
 
 	/* SLIT */
 	current	 = ( current + 0x07) & -0x08;
@@ -189,14 +215,16 @@ unsigned long write_acpi_tables(unsigned long start)
 	if (slit != NULL) {
 		memcpy((void *)current, slit, slit->header.length);
 		slit = (acpi_slit_t *) current;
-		//acpi_create_slit(slit);
 		current += slit->header.length;
 		acpi_add_table(rsdp, slit);
 	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
+	}
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:  * SSDT at %lx\n", current);
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
 		memcpy((void *)current, ssdt, ssdt->length);
@@ -204,21 +232,16 @@ unsigned long write_acpi_tables(unsigned long start)
 		current += ssdt->length;
 	}
 	else {
-		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		char *position = ssdt;
-		if (memcmp(position + 50, "TOM1", 4) == 0)
-				*(u32 *)(position + 55) = __readmsr(0xc001001a);
-
-	 /* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:  * SSDT for PState at %lx\n", current);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
@@ -239,6 +262,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
+	printk(BIOS_DEBUG, "ssdt2\n");
+	dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
 	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c
index 593ec46..74df922 100644
--- a/src/mainboard/asrock/e350m1/acpi_tables.c
+++ b/src/mainboard/asrock/e350m1/acpi_tables.c
@@ -24,11 +24,9 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-//#include <cpu/amd/amdfam10_sysconf.h>
-
-//#include "mb_sysconf.h"
 #include "agesawrapper.h"
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam14.h>
 
 #define DUMP_ACPI_TABLES 0
 
@@ -50,7 +48,29 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
 
 unsigned long acpi_fill_mcfg(unsigned long current)
 {
@@ -109,6 +129,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -130,99 +151,97 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_write_rsdp(rsdp, rsdt, NULL);
 	acpi_write_rsdt(rsdt);
 
+	/* DSDT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:  * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FADT */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
 	/*
-	* We explicitly add these tables later on:
-	*/
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	 * We explicitly add these tables later on:
+	 */
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * HPET at %lx\n", current);
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
 	/* If we want to use HPET Timers Linux wants an MADT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * MADT at %lx\n",current);
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
 	current += madt->header.length;
 	acpi_add_table(rsdp, madt);
 
 	/* SRAT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SRAT at %lx\n", current);
 	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
 	if (srat != NULL) {
-	memcpy(current, srat, srat->header.length);
-	srat = (acpi_srat_t *) current;
-	//acpi_create_srat(srat);
-	current += srat->header.length;
-	acpi_add_table(rsdp, srat);
+		memcpy((void *)current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SRAT table NULL. Skipping.\n");
 	}
 
 	/* SLIT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	current	 = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:  * SLIT at %lx\n", current);
 	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
 	if (slit != NULL) {
-	memcpy(current, slit, slit->header.length);
-	slit = (acpi_slit_t *) current;
-	//acpi_create_slit(slit);
-	current += slit->header.length;
-	acpi_add_table(rsdp, slit);
+		memcpy((void *)current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+	else {
+		printk(BIOS_DEBUG, "  AGESA SLIT table NULL. Skipping.\n");
 	}
 
 	/* SSDT */
-	current   = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
-	memcpy(current, ssdt, ssdt->length);
-	ssdt = (acpi_header_t *) current;
-	current += ssdt->length;
+		memcpy((void *)current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
 	}
 	else {
-	ssdt = (acpi_header_t *) current;
-	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
-	current += ssdt->length;
-	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-
-	char *position = ssdt;
-	if (memcmp (position + 50, "TOM1", 4) == 0)
-	*(u32 *) (position + 55) = __readmsr (0xc001001a);
-
-	/* recalculate checksum */
-	ssdt->checksum = 0;
-	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 
-	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
-
-	/* DSDT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
-
-	/* FACS */ // it needs 64 bit alignment
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI: * FACS at %lx\n", current);
-	facs = (acpi_facs_t *) current; // it will be used by fadt
-	current += sizeof(acpi_facs_t);
-	acpi_create_facs(facs);
-
-	/* FDAT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
-	fadt = (acpi_fadt_t *) current;
-	current += sizeof(acpi_fadt_t);
-
-	acpi_create_fadt(fadt, facs, dsdt);
-	acpi_add_table(rsdp, fadt);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
@@ -243,6 +262,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
+	printk(BIOS_DEBUG, "ssdt2\n");
+	dump_mem(ssdt2, ((void *)ssdt2) + ssdt2->length);
+
 	printk(BIOS_DEBUG, "fadt\n");
 	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
 #endif
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 3bda8d5..899d517 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -18,5 +18,3 @@
 #
  
 driver-y += northbridge.c
-
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
\ No newline at end of file
diff --git a/src/northbridge/amd/agesa/family14/ssdt.asl b/src/northbridge/amd/agesa/family14/ssdt.asl
deleted file mode 100644
index 1e694db..0000000
--- a/src/northbridge/amd/agesa/family14/ssdt.asl
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-/*
- * Make sure HC_NUMS and HC_POSSIBLE_NUM setting is consistent to this file
- */
-
-DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-FAM14H", "AMD-ACPI", 0x1000)
-{
-	/*
-	 * These objects were referenced but not defined in this table
-	 */
-	External (\_SB_.PCI0, DeviceObj)
-
-	Scope (\_SB.PCI0)
-	{
-		Name (TOM1, 0xaaaaaaaa)
-		Name (BUSN, Package (0x20) /* HC_NUMS */
-		{
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x10101010,
-			0x11111111,
-			0x12121212,
-			0x13131313,
-			0x14141414,
-			0x15151515,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc
-		})
-		Name (MMIO, Package (0x80) /* HC_NUMS * 4 */
-		{
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x11111111,
-			0x22222222,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x11111111,
-			0x22222222,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x11111111,
-			0x22222222,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x11111111,
-			0x22222222,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x11111111,
-			0x22222222,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888
-		})
-		Name (PCIO, Package (0x40) /* HC_NUMS * 2 */
-		{
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0xaaaaaaaa,
-			0xbbbbbbbb,
-			0xcccccccc,
-			0xdddddddd,
-			0xeeeeeeee,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x99999999,
-			0xaaaaaaaa,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444
-		})
-		Name (SBLK, 0x11)
-		Name (SBDN, 0xbbbbbbbb)
-		Name (HCLK, Package (0x20) /* HC_POSSIBLE_NUM */
-		{
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888
-		})
-		Name (HCDN, Package (0x20) /* HC_POSSIBLE_NUM */
-		{
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888,
-			0x11111111,
-			0x22222222,
-			0x33333333,
-			0x44444444,
-			0x55555555,
-			0x66666666,
-			0x77777777,
-			0x88888888
-		})
-		Name (CBB, 0x99)
-		Name (CBST, 0x88)
-		Name (CBB2, 0x77)
-		Name (CBS2, 0x66)
-
-	}
-}
-


From gerrit at coreboot.org  Wed Jan  4 04:52:18 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 4 Jan 2012 04:52:18 +0100
Subject: [coreboot] New patch to review for coreboot: 898b606 Fix Fam14
	AGESA ACPI table generation
References: <I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd+0@gerrit.coreboot.org>
Message-ID: <I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/517

-gerrit

commit 898b6065fdc2b26bf8cd4a8f0bf48ff8647e086b
Author: Marc Jones <marcj303 at gmail.com>
Date:   Mon Dec 12 22:04:25 2011 -0700

    Fix Fam14 AGESA ACPI table generation
    
    The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
    call was failing without heap space allocated causing the ASSERT messages in
    the output. I think are there may still be other issues in integrating the
    SSDT table with the DSDT, but now it is there to debug.
    
    The changes were made in Persimmon and copied to the other Fam14 mainboards.
    Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/acpi_tables.c         |   16 ++
 src/mainboard/amd/inagua/agesawrapper.c        |  175 +++++++++++++-----------
 src/mainboard/amd/persimmon/acpi_tables.c      |   23 +++-
 src/mainboard/amd/persimmon/agesawrapper.c     |   56 +++++---
 src/mainboard/amd/persimmon/buildOpts.c        |    6 +-
 src/mainboard/amd/south_station/acpi_tables.c  |   16 ++
 src/mainboard/amd/south_station/agesawrapper.c |   51 ++++---
 src/mainboard/amd/union_station/acpi_tables.c  |   16 ++
 src/mainboard/amd/union_station/agesawrapper.c |   51 ++++---
 src/mainboard/asrock/e350m1/acpi_tables.c      |   16 ++
 src/mainboard/asrock/e350m1/agesawrapper.c     |   97 ++++++++-----
 11 files changed, 344 insertions(+), 179 deletions(-)

diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 74df922..2e6e50f 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	}
+	else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
@@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
+#endif
 
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index 727436c..c33d20f 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -36,6 +36,7 @@
 #include "amdlib.h"
 #include "PlatformGnbPcieComplex.h"
 #include "Filecode.h"
+#include <arch/io.h>
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
@@ -44,6 +45,8 @@
  *------------------------------------------------------------------------------
  */
 
+#define MMCONF_ENABLE 1
+
 /* ACPI table pointers returned by AmdInitLate */
 VOID *DmiTable		= NULL;
 VOID *AcpiPstate	= NULL;
@@ -79,44 +82,45 @@ agesawrapper_amdinitcpuio (
 	VOID
 	)
 {
-	AGESA_STATUS		Status;
-	UINT64				MsrReg;
-	UINT32				PciData;
-	PCI_ADDR			PciAddress;
-	AMD_CONFIG_PARAMS	StdHeader;
-
-	/* Enable MMIO on AMD CPU Address Map Controller */
+	AGESA_STATUS				Status;
+	UINT64						MsrReg;
+	UINT32						PciData;
+	PCI_ADDR					PciAddress;
+	AMD_CONFIG_PARAMS			StdHeader;
+
+	/* Enable legacy video routing: D18F1xF4 VGA Enable */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciData = 1;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-	/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
+	/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
+	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
+	 * set to non-posted regions.
+	 */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
-	PciData = 0x00000B00;
+	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
+	PciData |= 1 << 7;	// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
-	PciData = 0x00000A03;
+	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-	/* Set TOM-DFFFFFFF to Node0 Link0. */
+	/* Map the remaining PCI hole as posted MMIO */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00DFFF00;
+	PciData = 0x00FECF00; // last address before non-posted range
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
 	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xBC);
-	PciData = 0x00FFFF00 | 0x80;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xB8);
-	PciData = (PCIE_BASE_ADDRESS >> 8) | 03;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
+
+	/* Send all IO (0000-FFFF) to southbridge. */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
 	PciData = 0x0000F000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000013;
+	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	Status = AGESA_SUCCESS;
 	return (UINT32)Status;
@@ -127,24 +131,37 @@ agesawrapper_amdinitmmio (
 	VOID
 	)
 {
-	AGESA_STATUS		Status;
-	UINT64				MsrReg;
-	UINT32				PciData;
-	PCI_ADDR			PciAddress;
-	AMD_CONFIG_PARAMS	StdHeader;
+	AGESA_STATUS				Status;
+	UINT64						MsrReg;
+	UINT32						PciData;
+	PCI_ADDR					PciAddress;
+	AMD_CONFIG_PARAMS			StdHeader;
+
+	UINT8						BusRangeVal = 0;
+	UINT8						BusNum;
+	UINT8						Index;
 
 	/*
 	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
 	 Address MSR register.
 	*/
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (8 << 2) | 1;
+
+	for (Index = 0; Index < 8; Index++) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1) {
+			BusRangeVal = Index;
+			break;
+		}
+	}
+
+	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
 	/*
 	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
 	*/
 	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
+	MsrReg = MsrReg | 0x0000400000000000ull;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set Ontario Link Data */
@@ -155,13 +172,6 @@ agesawrapper_amdinitmmio (
 	PciData = (AMD_APU_SSID<<0x10)|AMD_APU_SVID;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
-	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
-	LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
-
 	Status = AGESA_SUCCESS;
 	return (UINT32)Status;
 }
@@ -262,12 +272,12 @@ agesawrapper_amdinitpost (
 	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	AmdReleaseStruct (&AmdParamStruct);
+
 	/* Initialize heap space */
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-	{
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
 		*HeadPtr = 0x00000000;
 		HeadPtr++;
 	}
@@ -354,7 +364,6 @@ agesawrapper_amdinitenv (
 	PciValue |= 0x80000000;
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
-
 	/* Initialize MMIO Base and Limit Address
 	*	Modify B0D1F0x20
 	*/
@@ -442,68 +451,76 @@ agesawrapper_amdinitlate (
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 
-	Status = AmdInitLate (&AmdLateParams);
+	printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate (AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
 
 UINT32
 agesawrapper_amdlaterunaptask (
+	UINT32 Func,
 	UINT32 Data,
 	VOID *ConfigPtr
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
-
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
-
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
-
-	Status = AmdLateRunApTask (&AmdLateParams);
+	AP_EXE_PARAMS ApExeParams;
+
+	LibAmdMemFill (&ApExeParams,
+				 0,
+				 sizeof (AP_EXE_PARAMS),
+				 &(ApExeParams.StdHeader));
+
+	ApExeParams.StdHeader.AltImageBasePtr = 0;
+	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	ApExeParams.StdHeader.Func = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.StdHeader.ImageBasePtr = 0;
+	ApExeParams.FunctionNumber = Func;
+	ApExeParams.RelatedDataBlock = ConfigPtr;
+
+	Status = AmdLateRunApTask (&ApExeParams);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
-
 	return (UINT32)Status;
 }
 
@@ -526,9 +543,9 @@ agesawrapper_amdreadeventlog (
 	AmdEventParams.StdHeader.ImageBasePtr = 0;
 	Status = AmdReadEventLog (&AmdEventParams);
 	while (AmdEventParams.EventClass != 0) {
-		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-		printk(BIOS_DEBUG,"	Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-		printk(BIOS_DEBUG,"	Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
 		Status = AmdReadEventLog (&AmdEventParams);
 	}
 
diff --git a/src/mainboard/amd/persimmon/acpi_tables.c b/src/mainboard/amd/persimmon/acpi_tables.c
index 47e35af..9526fea 100644
--- a/src/mainboard/amd/persimmon/acpi_tables.c
+++ b/src/mainboard/amd/persimmon/acpi_tables.c
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -130,6 +131,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -224,17 +226,33 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	}
+	else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
+		acpi_add_table(rsdp,ssdt);
 	}
 	else {
-		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
+		printk(BIOS_DEBUG, "  AGESA SSDT Pstate table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
+#endif
 
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
@@ -259,6 +277,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
+	printk(BIOS_DEBUG, "alib\n");
+	dump_mem(ssdt, ((void *)alib) + alib->length);
+
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index 55e8488..f9847c2 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -275,8 +275,7 @@ agesawrapper_amdinitpost (
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-	{
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
 		*HeadPtr = 0x00000000;
 		HeadPtr++;
 	}
@@ -450,32 +449,49 @@ agesawrapper_amdinitlate (
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 
-	Status = AmdInitLate (&AmdLateParams);
+	printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate (AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
-
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c
index 368eed2..3e5b14e 100644
--- a/src/mainboard/amd/persimmon/buildOpts.c
+++ b/src/mainboard/amd/persimmon/buildOpts.c
@@ -95,9 +95,9 @@
 	#define BLDCFG_REMOVE_ACPI_PSTATES_PSS			FALSE
 	#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS			FALSE
 	#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT		FALSE
-#define BLDOPT_REMOVE_SRAT						TRUE
-#define BLDOPT_REMOVE_SLIT						TRUE
-#define BLDOPT_REMOVE_WHEA						TRUE
+#define BLDOPT_REMOVE_SRAT						FALSE
+#define BLDOPT_REMOVE_SLIT						FALSE
+#define BLDOPT_REMOVE_WHEA						FALSE
 #define BLDOPT_REMOVE_DMI						TRUE
 #define BLDOPT_REMOVE_HT_ASSIST					TRUE
 #define BLDOPT_REMOVE_ATM_MODE					TRUE
diff --git a/src/mainboard/amd/south_station/acpi_tables.c b/src/mainboard/amd/south_station/acpi_tables.c
index 74df922..2e6e50f 100644
--- a/src/mainboard/amd/south_station/acpi_tables.c
+++ b/src/mainboard/amd/south_station/acpi_tables.c
@@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	}
+	else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
@@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
+#endif
 
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c
index 55e8488..0fbb3e4 100644
--- a/src/mainboard/amd/south_station/agesawrapper.c
+++ b/src/mainboard/amd/south_station/agesawrapper.c
@@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio (
 	 */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-	PciData |= 1 << 7;		// set NP (non-posted) bit
+	PciData |= 1 << 7;	// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
 	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
@@ -275,8 +275,7 @@ agesawrapper_amdinitpost (
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-	{
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
 		*HeadPtr = 0x00000000;
 		HeadPtr++;
 	}
@@ -450,32 +449,44 @@ agesawrapper_amdinitlate (
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 
-	Status = AmdInitLate (&AmdLateParams);
+	printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate (AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
diff --git a/src/mainboard/amd/union_station/acpi_tables.c b/src/mainboard/amd/union_station/acpi_tables.c
index 74df922..2e6e50f 100644
--- a/src/mainboard/amd/union_station/acpi_tables.c
+++ b/src/mainboard/amd/union_station/acpi_tables.c
@@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	}
+	else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
@@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
+#endif
 
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c
index 55e8488..0fbb3e4 100644
--- a/src/mainboard/amd/union_station/agesawrapper.c
+++ b/src/mainboard/amd/union_station/agesawrapper.c
@@ -98,7 +98,7 @@ agesawrapper_amdinitcpuio (
 	 */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-	PciData |= 1 << 7;		// set NP (non-posted) bit
+	PciData |= 1 << 7;	// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
 	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
@@ -275,8 +275,7 @@ agesawrapper_amdinitpost (
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-	{
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
 		*HeadPtr = 0x00000000;
 		HeadPtr++;
 	}
@@ -450,32 +449,44 @@ agesawrapper_amdinitlate (
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
 
-	Status = AmdInitLate (&AmdLateParams);
+	printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate (AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
diff --git a/src/mainboard/asrock/e350m1/acpi_tables.c b/src/mainboard/asrock/e350m1/acpi_tables.c
index 74df922..2e6e50f 100644
--- a/src/mainboard/asrock/e350m1/acpi_tables.c
+++ b/src/mainboard/asrock/e350m1/acpi_tables.c
@@ -130,6 +130,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_header_t *dsdt;
 	acpi_header_t *ssdt;
 	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -224,6 +225,20 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* SSDT */
 	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	}
+	else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
 	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
 	if (ssdt != NULL) {
@@ -235,6 +250,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
+#endif
 
 	current	 = ( current + 0x0f) & -0x10;
 	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index 8ecc885..fc87029 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -36,6 +36,7 @@
 #include "amdlib.h"
 #include "PlatformGnbPcieComplex.h"
 #include "Filecode.h"
+#include <arch/io.h>
 
 #define FILECODE UNASSIGNED_FILE_FILECODE
 
@@ -44,6 +45,7 @@
  *------------------------------------------------------------------------------
  */
 
+#define MMCONF_ENABLE 1
 
 /* ACPI table pointers returned by AmdInitLate */
 VOID *DmiTable		= NULL;
@@ -96,7 +98,7 @@ agesawrapper_amdinitcpuio (
 	 */
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000
-	PciData |= 1 << 7;		// set NP (non-posted) bit
+	PciData |= 1 << 7;	// set NP (non-posted) bit
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
 	PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000
@@ -128,25 +130,37 @@ agesawrapper_amdinitmmio (
 	VOID
 	)
 {
-	AGESA_STATUS		Status;
-	UINT64				MsrReg;
-	UINT32				PciData;
-	PCI_ADDR			PciAddress;
-	AMD_CONFIG_PARAMS	StdHeader;
+	AGESA_STATUS				Status;
+	UINT64						MsrReg;
+	UINT32						PciData;
+	PCI_ADDR					PciAddress;
+	AMD_CONFIG_PARAMS			StdHeader;
+
+	UINT8						BusRangeVal = 0;
+	UINT8						BusNum;
+	UINT8						Index;
 
 	/*
-	Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	Address MSR register.
+	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	 Address MSR register.
 	*/
 
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
+	for (Index = 0; Index < 8; Index++) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1) {
+			BusRangeVal = Index;
+			break;
+		}
+	}
+
+	MsrReg = (CONFIG_MMCONF_BASE_ADDRESS | (UINT64)(BusRangeVal << 2) | MMCONF_ENABLE);
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
 	/*
-	Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
 	*/
 	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
-	MsrReg = MsrReg | 0x0000400000000000;
+	MsrReg = MsrReg | 0x0000400000000000ull;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set Ontario Link Data */
@@ -261,10 +275,9 @@ agesawrapper_amdinitpost (
 	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
 
 	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
-	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
-	{
-	*HeadPtr = 0x00000000;
-	HeadPtr++;
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++) {
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
 	}
 	BiosManagerPtr->StartOfAllocatedNodes = 0;
 	BiosManagerPtr->StartOfFreedNodes = 0;
@@ -436,32 +449,44 @@ agesawrapper_amdinitlate (
 	)
 {
 	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
-	LibAmdMemFill (&AmdLateParams,
-					0,
-					sizeof (AMD_LATE_PARAMS),
-					&(AmdLateParams.StdHeader));
+	LibAmdMemFill (&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	Status = AmdInitLate (&AmdLateParams);
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+	printk (BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate (AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
 		agesawrapper_amdreadeventlog();
 		ASSERT(Status == AGESA_SUCCESS);
 	}
 
-	DmiTable		= AmdLateParams.DmiTable;
-	AcpiPstate		= AmdLateParams.AcpiPState;
-	AcpiSrat		= AmdLateParams.AcpiSrat;
-	AcpiSlit		= AmdLateParams.AcpiSlit;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
 
-	AcpiWheaMce		= AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc		= AmdLateParams.AcpiWheaCmc;
-	AcpiAlib		= AmdLateParams.AcpiAlib;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
@@ -517,10 +542,10 @@ agesawrapper_amdreadeventlog (
 	AmdEventParams.StdHeader.ImageBasePtr = 0;
 	Status = AmdReadEventLog (&AmdEventParams);
 	while (AmdEventParams.EventClass != 0) {
-	printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
-	printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
-	printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
-	Status = AmdReadEventLog (&AmdEventParams);
+		printk(BIOS_DEBUG,"\nEventLog:	EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"	Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"	Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
 	}
 
 	return (UINT32)Status;


From gerrit at coreboot.org  Wed Jan  4 13:06:40 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 4 Jan 2012 13:06:40 +0100
Subject: [coreboot] Patch set updated for coreboot: b7929ad Fix multipleVGA
	cards resource conflict on Windows
References: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+0@gerrit.coreboot.org>
Message-ID: <I0de5e3761b51e2723d9c1dc0c39fff692e3a779d+5@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/489

-gerrit

commit b7929add7bf1b40795e0a16ab08fc47858971ccc
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 4 20:51:47 2012 +0800

    Fix multipleVGA cards resource conflict on Windows
    
    If multiple VGA-compatible legacy graphic cards decode the IO range
    3B0-3BB, 3C0-3DF and MEM range A00000-BFFFF.
    Windows 7 complain a resource conflict, so only one VGA card can
    works at the same time.
    
    There is a discussion in coreboot mail list before,
    please reference thread: "how to prevent legacy resource conflictwith   multipleVGA cards"
    http://www.coreboot.org/pipermail/coreboot/2010-October/061508.html
    
    Linux using VGA Arbiter module(vgaarb) to resolve this resource conflict,
    Please see the following linux dmesg log, more information can be found in
    Linux source dir Documentation/vgaarbiter.txt.
    But it seems that windows don't dealwith this conflict.
    ~# dmesg | grep -i vgaarb
    [    0.774076] vgaarb: device added: PCI:0000:00:01.0,decodes=io+mem,owns=io+mem
    [    0.776065] vgaarb: device added: PCI:0000:01:00.0,decodes=io+mem,owns=none,l
    [    0.780051] vgaarb: loaded
    [    0.784049] vgaarb: bridge control possible 0000:01:00.0
    [    0.788050] vgaarb: bridge control possible 0000:00:01.0
    
    For the second legacy graphic device, coreboot already disabled the
    IO and MEM decode in function set_vga_bridge_bits().
    But it will be enabled again in function pci_set_resource(),
    if the second legacy vga-compatible graphic device take any IO/MEM resources.
    
    Following log printed by enable_resources() shows the problem:
    ...snip...
    PCI: 00:00.0 cmd <- 06
    PCI: 00:01.0 subsystem <- 1022/1410
    PCI: 00:01.0 cmd <- 07                <== The first graphic device
    PCI: 00:01.1 subsystem <- 1022/1410
    PCI: 00:01.1 cmd <- 02
    PCI: 00:02.0 bridge ctrl <- 0003
    PCI: 00:02.0 cmd <- 07
    ...snip...
    PCI: 01:00.0 cmd <- 03                <== The second graphic device
    PCI: 01:00.1 cmd <- 02
    PCI: 02:00.0 cmd <- 02
    PCI: 03:00.0 cmd <- 03
    done.
    ...snip...
    
    
    The IO & MEM decoding on the second vga graphic device should be disabled.
    Please reference PCI spec. section 3.10 in detail.
    set_vga_bridge_bits() would do this work for us, it did the right thing,
    but was put to the wrong place, the setting would be overwritten by
    assign_resources() later.
    
    In order to make sure the set_vga_bridge_bits() setting not be
    overwritten by others, moving the call of set_vga_bridge_bits()
    to the end of dev_configure(), instead of at the beginning.
    
    This patch resolved the dual graphic cards resource conflict in windows7,
    multiple vga-compatible graphic cards can work together in windows7.
    
    
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Change-Id: I0de5e3761b51e2723d9c1dc0c39fff692e3a779d
---
 src/devices/device.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/devices/device.c b/src/devices/device.c
index a2619bf..8ad9787 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -932,10 +932,6 @@ void dev_configure(void)
 	struct device *root;
 	struct device *child;
 
-#if CONFIG_VGA_BRIDGE_SETUP == 1
-	set_vga_bridge_bits();
-#endif
-
 	printk(BIOS_INFO, "Allocating resources...\n");
 
 	root = &dev_root;
@@ -1028,6 +1024,10 @@ void dev_configure(void)
 	printk(BIOS_INFO, "Done setting resources.\n");
 	print_resource_tree(root, BIOS_SPEW, "After assigning values.");
 
+#if CONFIG_VGA_BRIDGE_SETUP == 1
+	set_vga_bridge_bits();
+#endif
+
 	printk(BIOS_INFO, "Done allocating resources.\n");
 }
 


From echelon at free.fr  Wed Jan  4 22:10:14 2012
From: echelon at free.fr (echelon at free.fr)
Date: Wed, 04 Jan 2012 22:10:14 +0100 (CET)
Subject: [coreboot] hackaton proposal in Paris
Message-ID: <a5ceb900-551b-4240-8297-eaa4f5d69054@zimbra6-e1.priv.proxad.net>

Hello,

First of all, let me wish you, all the people involved in the Coreboot project hackers and enthusiasts, a great and happy New Year!

Next, following some discussions I've had at the 28c3 event in Berlin, I would like to propose a coreboot hackaton at the 12,13 and 14 april in Paris. If all goes OK, we could take profit from the organisation of the event "Hackito Ergo Sum", wich takes place at the same dates in Paris. Hopefully there will be some kind of "hack area" like the "hackcenter" of the CCC Congress, where we could install our stuff. The guy I have meet told me that providing space for 6-7 people will be no problem. Regarding the accomodation and other logistical details, unfortunately I can not give you more info yet.
Now I would like to know if there are some coreboot people which are intersted by this ideea, and if enough persons are interested I will proceed with further organizatoric actions.

By the way, Rudolph, do you plan to organize in 2012 a new hackaton in Prague? (For my part, I see no problem if there are 2 coreboot hackatons in 2012.. ;-))

Florentin Demetrescu



From gerrit at coreboot.org  Thu Jan  5 02:39:33 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Thu, 5 Jan 2012 02:39:33 +0100
Subject: [coreboot] New patch to review for coreboot: e74bd22 rs780: use
	bitwise rather than boolean not
References: <Ie3872c57990f9784aafda14f8c7fc842b3a65260+0@gerrit.coreboot.org>
Message-ID: <Ie3872c57990f9784aafda14f8c7fc842b3a65260+1@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/518

-gerrit

commit e74bd229bfc01533d9547b519b0ed1afdbc776c5
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jan 4 19:37:48 2012 -0600

    rs780: use bitwise rather than boolean not
    
    Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/amd/rs780/pcie.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 5e2d985..b55da89 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -72,7 +72,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 	state = ~state;
 	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
 	state_save = state << 17;
-	state &= !(AtiPcieCfg.PortHp);
+	state &= ~(AtiPcieCfg.PortHp);
 	reg = nbmisc_read_index(nb_dev, 0x0c);
 	reg |= state;
 	nbmisc_write_index(nb_dev, 0x0c, reg);


From gerrit at coreboot.org  Thu Jan  5 02:47:09 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Thu, 5 Jan 2012 02:47:09 +0100
Subject: [coreboot] New patch to review for coreboot: b21ed15 rs780: power
	down GPPSB SB lane pads in correct PCIe core
References: <I059d5b155cae051f31cc2495f8a47d53e01af808+0@gerrit.coreboot.org>
Message-ID: <I059d5b155cae051f31cc2495f8a47d53e01af808+1@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/519

-gerrit

commit b21ed1585ff2c6889678c83e66651d83b5e277e3
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jan 4 19:43:49 2012 -0600

    rs780: power down GPPSB SB lane pads in correct PCIe core
    
    Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/amd/rs780/pcie.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 5e2d985..efa2e58 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -86,15 +86,21 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 		 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
 			   PCIE_GFX_COMPLIANCE))) {
 	}
+
 	/* step 3 Power Down Control for Southbridge */
+	if (port != 8)
+		return;
+
 	reg = nbpcie_p_read_index(dev, 0xa2);
 
 	switch ((reg >> 4) & 0x7) {	/* get bit 4-6, LC_LINK_WIDTH_RD */
 	case 1:
-		nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+		set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+				     0x0f0f, 0x0e0e);
 		break;
 	case 2:
-		nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+		set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+				     0x0f0f, 0x0c0c);
 		break;
 	default:
 		break;


From gerrit at coreboot.org  Thu Jan  5 04:25:11 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 04:25:11 +0100
Subject: [coreboot] Patch merged into coreboot/master: b21ed15 rs780: power
	down GPPSB SB lane pads in correct PCIe core
References: <I059d5b155cae051f31cc2495f8a47d53e01af808+0@gerrit.coreboot.org>
Message-ID: <E1Ridx1-0000P4-AQ@ra.coresystems.de>

the following patch was just integrated into master:
commit b21ed1585ff2c6889678c83e66651d83b5e277e3
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jan 4 19:43:49 2012 -0600

    rs780: power down GPPSB SB lane pads in correct PCIe core
    
    Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>

Build-Tested: build bot (Jenkins) at Thu Jan  5 03:12:41 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Thu Jan  5 04:25:09 2012, giving +2
See http://review.coreboot.org/519 for details.

-gerrit


From philipp_subx at redfish-solutions.com  Thu Jan  5 06:22:18 2012
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Wed, 04 Jan 2012 22:22:18 -0700
Subject: [coreboot] MSR discrepancies
Message-ID: <4F05338A.2070308@redfish-solutions.com>

I was looking at the devicetree.cb values for the alix2 versus what I see on my alix6:

root at OpenWrt:/# rdmsr 0x51400025
1002
root at OpenWrt:/# rdmsr 0x5140004e
effd00c0
root at OpenWrt:/#

I'm not sure how significant these differences are:

chip northbridge/amd/lx
        device pci_domain 0 on
                device pci 1.0 on end
                device pci 1.1 on end
                chip southbridge/amd/cs5536
                        # IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
                        # SIRQ Mode = Active(Quiet) mode. Save power....
                        # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
                        # How to get these? Boot linux and do this:
                        # rdmsr 0x51400025
                        register "lpc_serirq_enable" = "0x00001002"
                        # rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
                        register "lpc_serirq_polarity" = "0x0000EFFD"
                        # mode is high 10 bits (determined from code)
                        register "lpc_serirq_mode" = "1"
                        # Don't yet know how to find this.
                        register "enable_gpio_int_route" = "0x0D0C0700"
                        register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
                        register "enable_USBP4_device" = "0"    #0: host, 1:device


From rminnich at gmail.com  Thu Jan  5 07:47:34 2012
From: rminnich at gmail.com (ron minnich)
Date: Wed, 4 Jan 2012 22:47:34 -0800
Subject: [coreboot] MSR discrepancies
In-Reply-To: <4F05338A.2070308@redfish-solutions.com>
References: <4F05338A.2070308@redfish-solutions.com>
Message-ID: <CAP6exYKnu2FvDZFbnoaB3g0mMY-v=LOEuZJ079hsAe+OWTsOZQ@mail.gmail.com>

They're going to differ because the values of those registers depend
on how things are wired up.

I'd be careful about changing that sort of thing. It drove me crazy.

ron


From gerrit at coreboot.org  Thu Jan  5 17:28:21 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 17:28:21 +0100
Subject: [coreboot] Patch merged into coreboot/master: a2f4c41 Fix Fam14
	mainboard whitespace
References: <I6d63d428dde0a5d9748027e603b03de25d3be472+0@gerrit.coreboot.org>
Message-ID: <E1RiqAv-0002Dw-FP@ra.coresystems.de>

the following patch was just integrated into master:
commit a2f4c419f0526c66cfc51217baf64729f60affca
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 3 16:02:07 2012 -0700

    Fix Fam14 mainboard whitespace
    
    Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
    changes
    
    Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan  4 05:19:57 2012, giving +1
Reviewed-By: Kerry Sheh <shekairui at gmail.com> at Wed Jan  4 12:15:44 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Thu Jan  5 17:28:19 2012, giving +2
See http://review.coreboot.org/515 for details.

-gerrit


From gerrit at coreboot.org  Thu Jan  5 17:29:12 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 17:29:12 +0100
Subject: [coreboot] Patch merged into coreboot/master: a750360 Clean up AMD
	Fam14 SSDT
References: <I808c863597e024e3e8aeec0821e8618d96cc96a6+0@gerrit.coreboot.org>
Message-ID: <E1RiqBk-0002Q3-A5@ra.coresystems.de>

the following patch was just integrated into master:
commit a750360f845cebbd5a798d79b567b9ebd5d00003
Author: Marc Jones <marcj303 at gmail.com>
Date:   Mon Dec 12 21:12:43 2011 -0700

    Clean up AMD Fam14 SSDT
    
    The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
    include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
    for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
    fixes some ACPI errors in Linux and Windows bluescreens.
    
    The Persimmon acpi_tables.c is where the main changes were made and then
    replicated in the other Fam14 boards. Please test the other mainbords if you
    have one.
    
    Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan  4 05:31:14 2012, giving +1
Reviewed-By: Kerry Sheh <shekairui at gmail.com> at Wed Jan  4 12:30:20 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Thu Jan  5 17:29:10 2012, giving +2
See http://review.coreboot.org/516 for details.

-gerrit


From gerrit at coreboot.org  Thu Jan  5 17:29:46 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 17:29:46 +0100
Subject: [coreboot] Patch merged into coreboot/master: 898b606 Fix Fam14
	AGESA ACPI table generation
References: <I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd+0@gerrit.coreboot.org>
Message-ID: <E1RiqCI-0002b0-RQ@ra.coresystems.de>

the following patch was just integrated into master:
commit 898b6065fdc2b26bf8cd4a8f0bf48ff8647e086b
Author: Marc Jones <marcj303 at gmail.com>
Date:   Mon Dec 12 22:04:25 2011 -0700

    Fix Fam14 AGESA ACPI table generation
    
    The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
    call was failing without heap space allocated causing the ASSERT messages in
    the output. I think are there may still be other issues in integrating the
    SSDT table with the DSDT, but now it is there to debug.
    
    The changes were made in Persimmon and copied to the other Fam14 mainboards.
    Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan  4 05:41:56 2012, giving +1
Reviewed-By: Kerry Sheh <shekairui at gmail.com> at Wed Jan  4 12:28:40 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Thu Jan  5 17:29:44 2012, giving +2
See http://review.coreboot.org/517 for details.

-gerrit


From gerrit at coreboot.org  Thu Jan  5 17:34:54 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 17:34:54 +0100
Subject: [coreboot] Patch merged into coreboot/master: e267d74 Indentation:
	Various indentation fixes
References: <I5b396e5753544aff13ac5d16afc59e193a6b1da1+0@gerrit.coreboot.org>
Message-ID: <E1RiqHG-0003fA-Dz@ra.coresystems.de>

the following patch was just integrated into master:
commit e267d74eb35f6df29e9463faf6c75b3f7989af07
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 22:52:01 2011 +0530

    Indentation: Various indentation fixes
    
    Fixed indentation using indent tool in the src/drivers/i2c tree
    
    Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>

Build-Tested: build bot (Jenkins) at Mon Dec 26 18:42:54 2011, giving +1
Reviewed-By: Kerry Sheh <shekairui at gmail.com> at Wed Jan  4 13:09:26 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Thu Jan  5 17:34:50 2012, giving +2
See http://review.coreboot.org/506 for details.

-gerrit


From gerrit at coreboot.org  Thu Jan  5 17:38:19 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Thu, 5 Jan 2012 17:38:19 +0100
Subject: [coreboot] Patch set updated for coreboot: 4bfe8f6 rs780: use
	bitwise rather than boolean not
References: <Ie3872c57990f9784aafda14f8c7fc842b3a65260+0@gerrit.coreboot.org>
Message-ID: <Ie3872c57990f9784aafda14f8c7fc842b3a65260+2@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/518

-gerrit

commit 4bfe8f667b7d237cdbed73c61fbe09442acc4d97
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jan 4 19:37:48 2012 -0600

    rs780: use bitwise rather than boolean not
    
    Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/amd/rs780/pcie.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index efa2e58..be80ed3 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -72,7 +72,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 	state = ~state;
 	state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
 	state_save = state << 17;
-	state &= !(AtiPcieCfg.PortHp);
+	state &= ~(AtiPcieCfg.PortHp);
 	reg = nbmisc_read_index(nb_dev, 0x0c);
 	reg |= state;
 	nbmisc_write_index(nb_dev, 0x0c, reg);


From GNUtoo at no-log.org  Thu Jan  5 17:19:00 2012
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Thu, 5 Jan 2012 17:19:00 +0100
Subject: [coreboot] TOM2 and M4A785T-M
Message-ID: <201201051719.01192.GNUtoo@no-log.org>

Hi, is it normal that TOM2 is 0 on the M4A785T-M mainboard?

Here are the logs from coreboot:
--------------------------------------------
Sysmem TOM = 0_80000000
Sysmem TOM2 = 0_0
[...]
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base:    0MB, range: 2048MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 1792MB, range:  256MB, type UC
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled


And from the linux kernel:
-----------------------------------
[    0.312294] mtrr: your CPUs had inconsistent variable MTRR settings
[    0.312295] mtrr: probably your BIOS does not setup all CPUs.
[    0.312296] mtrr: corrected configuration.
[...]
[    0.317404] ACPI: Executed 2 blocks of module-level executable AML code
[    0.383560] ACPI: Interpreter enabled
[    0.384025] ACPI: (supports S0 S1 S2 S3 S4 S5)
[    0.392816] ACPI: BIOS offers _BFS
[    0.396026] ACPI: If "acpi.bfs=1" improves resume, please notify linux-
acpi at vger.kernel.org
[    0.400025] ACPI: Using IOAPIC for interrupt routing
[    0.432761] ACPI: Power Resource [PFN0] (on)
[    0.444081] ACPI: No dock devices found.
[    0.448028] HEST: Table not found.
[    0.451490] PCI: Ignoring host bridge windows from ACPI; if necessary, use 
"pci=use_crs" and report a bug
[    0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND 
(20110112/psargs-359)
[    0.460029] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] 
(Node f4426e70), AE_NOT_FOUND (20110112/psparse-536)
[    0.472033] [Firmware Bug]: ACPI: no secondary bus range in _CRS
[    0.476035] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.480086] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND 
(20110112/psargs-359)
[    0.492031] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS] 
(Node f4426e70), AE_NOT_FOUND (20110112/psparse-536)

Denis.


From gerrit at coreboot.org  Thu Jan  5 18:08:08 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 5 Jan 2012 18:08:08 +0100
Subject: [coreboot] Patch merged into coreboot/master: 4bfe8f6 rs780: use
	bitwise rather than boolean not
References: <Ie3872c57990f9784aafda14f8c7fc842b3a65260+0@gerrit.coreboot.org>
Message-ID: <E1RiqnQ-00019m-P5@ra.coresystems.de>

the following patch was just integrated into master:
commit 4bfe8f667b7d237cdbed73c61fbe09442acc4d97
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Wed Jan 4 19:37:48 2012 -0600

    rs780: use bitwise rather than boolean not
    
    Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>

Build-Tested: build bot (Jenkins) at Thu Jan  5 17:57:08 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Thu Jan  5 18:08:06 2012, giving +2
See http://review.coreboot.org/518 for details.

-gerrit


From marcj303 at gmail.com  Thu Jan  5 19:11:51 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 5 Jan 2012 11:11:51 -0700
Subject: [coreboot] TOM2 and M4A785T-M
In-Reply-To: <201201051719.01192.GNUtoo@no-log.org>
References: <201201051719.01192.GNUtoo@no-log.org>
Message-ID: <CALrs_3ia=C1OzHWJLwgUO7bspYXxw4CFYJuWJm5BUNj9yxLKXQ@mail.gmail.com>

On Thu, Jan 5, 2012 at 9:19 AM, Denis 'GNUtoo' Carikli
<GNUtoo at no-log.org> wrote:
> Hi, is it normal that TOM2 is 0 on the M4A785T-M mainboard?
>
> Here are the logs from coreboot:
> --------------------------------------------
> Sysmem TOM = 0_80000000
> Sysmem TOM2 = 0_0
> [...]
> Setting fixed MTRRs(0-88) type: UC
> Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
> Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
> DONE fixed MTRRs
> Setting variable MTRR 0, base: ? ?0MB, range: 2048MB, type WB
> ADDRESS_MASK_HIGH=0xffff
> Setting variable MTRR 1, base: 1792MB, range: ?256MB, type UC
> ADDRESS_MASK_HIGH=0xffff
> DONE variable MTRRs
> Clear out the extra MTRR's
> call enable_var_mtrr()
> Leave x86_setup_var_mtrrs
>
> MTRR check
> Fixed MTRRs ? : Enabled
> Variable MTRRs: Enabled
>
>
> And from the linux kernel:
> -----------------------------------
> [ ? ?0.312294] mtrr: your CPUs had inconsistent variable MTRR settings
> [ ? ?0.312295] mtrr: probably your BIOS does not setup all CPUs.
> [ ? ?0.312296] mtrr: corrected configuration.
> [...]
> [ ? ?0.317404] ACPI: Executed 2 blocks of module-level executable AML code
> [ ? ?0.383560] ACPI: Interpreter enabled
> [ ? ?0.384025] ACPI: (supports S0 S1 S2 S3 S4 S5)
> [ ? ?0.392816] ACPI: BIOS offers _BFS
> [ ? ?0.396026] ACPI: If "acpi.bfs=1" improves resume, please notify linux-
> acpi at vger.kernel.org
> [ ? ?0.400025] ACPI: Using IOAPIC for interrupt routing
> [ ? ?0.432761] ACPI: Power Resource [PFN0] (on)
> [ ? ?0.444081] ACPI: No dock devices found.
> [ ? ?0.448028] HEST: Table not found.
> [ ? ?0.451490] PCI: Ignoring host bridge windows from ACPI; if necessary, use
> "pci=use_crs" and report a bug
> [ ? ?0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
> (20110112/psargs-359)
> [ ? ?0.460029] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS]
> (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536)
> [ ? ?0.472033] [Firmware Bug]: ACPI: no secondary bus range in _CRS
> [ ? ?0.476035] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
> [ ? ?0.480086] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND
> (20110112/psargs-359)
> [ ? ?0.492031] ACPI Error: Method parse/execution failed [\_SB_.PCI0._CRS]
> (Node f4426e70), AE_NOT_FOUND (20110112/psparse-536)
>
> Denis.
>

Hi Denis,

This is probably a failure in the mainboard ssdt. The dsdt has the
variable for TOM and TOM2 that are in an ssdt. You probably want to
add some debug code to acpi_tables.c to see what is getting loaded. It
looks like the method used in this mainboard is to copy a compile time
ssdt in. A better way is to generate the ssdt. The amd/mahogany or the
amd/persimmon acpi_tables.c have examples that generate the ssdt
table. You may want to start there.

Marc

-- 
http://se-eng.com


From patrick at georgi-clan.de  Thu Jan  5 21:43:37 2012
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Thu, 05 Jan 2012 21:43:37 +0100
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <1325024460.2022.13.camel@Debian.lan>
References: <1325024460.2022.13.camel@Debian.lan>
Message-ID: <4F060B79.6000101@georgi-clan.de>

Am 27.12.2011 23:21, schrieb Nils:
> Is that a caching problem introduced by tiny bootblock?
> What is needed to get it right?
Probably MTRRs. With tinybootblock, these are set at slightly different 
times.
GX2 uses Cache-As-RAM, right? That affects MTRRs, too (as CAR is a 
"special" MTRR setup)


Patrick


From philipp_subx at redfish-solutions.com  Fri Jan  6 03:56:51 2012
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Thu, 05 Jan 2012 19:56:51 -0700
Subject: [coreboot] tiny bootblock problem
Message-ID: <4F0662F3.6050908@redfish-solutions.com>

When I boot coreboot (the alix2 image) on a 6F2 I get the following spew.

==========

Changing serial settings was 13/5 now 3/0
In resume (status=0)
In 32bit resume
Attempting a hard reboot
WARNING - Timeout at i8042_wait_write:51!


coreboot-4.0-1936-g33dd7a8-dirty Wed Jan  4 12:20:50 MST 2012 starting...
MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e
Configuring PLL.


coreboot-4.0-1936-g33dd7a8-dirty Wed Jan  4 12:20:50 MST 2012 starting...
MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e
PLL configured.
Castle 2.0 BTM periodic sync period.
Enable Quack for fewer re-RAS on the MC
 GLIU port active enable
Set the Delay Control in GLCP
spd_read_byte dev 50 addr 0d returns 08
spd_read_byte dev 50 addr 05 returns 01
spd_read_byte dev 51 returns 0xff
Enable RSDC
FPU imprecise exceptions bit
Enable Suspend on HLT & PAUSE instructions
Enable SUSP and allow TSC to run in Suspend
Setup throttling delays to proper mode
Done cpuRegInit
Ram1.00
Ram2.00
 * sdram_set_spd_register
spd_read_byte dev 50 addr 15 returns ff
 * Check DIMM 0
 * Check DIMM 1
spd_read_byte dev 51 returns 0xff
 * Check DDR MAX
spd_read_byte dev 50 addr 09 returns 0a
spd_read_byte dev 51 returns 0xff
 * AUTOSIZE DIMM 0
 * Check present
spd_read_byte dev 50 addr 02 returns 07
 * MODBANKS
spd_read_byte dev 50 addr 05 returns 01
 * FIELDBANKS
spd_read_byte dev 50 addr 11 returns 04
 * SPDNUMROWS
spd_read_byte dev 50 addr 03 returns 03
spd_read_byte dev 50 addr 04 returns 0a
 * SPDBANKDENSITY
spd_read_byte dev 50 addr 1f returns 40
 * DIMMSIZE
 * BEFORT CTZ
 * TEST DIMM SIZE>8
 * PAGESIZE
spd_read_byte dev 50 addr 04 returns 0a
 * MAXCOLADDR
 * >12address test
 * RDMSR CF07
 * WRMSR CF07
 * ALL DONE
 * AUTOSIZE DIMM 1
 * Check present
spd_read_byte dev 51 returns 0xff
 * set cas latency
spd_read_byte dev 50 addr 12 returns 10
spd_read_byte dev 50 addr 17 returns 3c
spd_read_byte dev 50 addr 19 returns 4b
spd_read_byte dev 51 returns 0xff
 * set all latency
spd_read_byte dev 50 addr 1e returns 28
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1b returns 0f
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1d returns 0f
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 1c returns 0a
spd_read_byte dev 51 returns 0xff
spd_read_byte dev 50 addr 2a returns 46
spd_read_byte dev 51 returns 0xff
 * set emrs
spd_read_byte dev 50 addr 16 returns ff
spd_read_byte dev 51 returns 0xff
 * set ref rate
spd_read_byte dev 50 addr 0c returns 3a
spd_read_byte dev 51 returns 0xff
Ram3
 * DRAM controller init done.

RAM DLL lock
Ram4
POST 02
Past wbinvd
Loading image.
Searching for fallback/coreboot_ram
Check fallback/romstage
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000
Stage: done loading.
Jumping to image.
coreboot-4.0-1936-g33dd7a8-dirty Wed Jan  4 12:20:50 MST 2012 booting...
clocks_per_usec: 499
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 1
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
Compare with tree...
Root Device: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:0f.0: enabled 1
  PCI: 00:0f.1: enabled 1
  PCI: 00:0f.2: enabled 1
  PCI: 00:0f.4: enabled 1
  PCI: 00:0f.5: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
scan_static_bus for Root Device
>> Entering northbridge.c: enable_dev with path 6
>> Entering northbridge.c: pci_domain_enable
Enter northbridge_init_early
writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SMMGL0Init: 268304384 bytes
SMMGL0Init: offset is 0x80400000
SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
sizeram: sizem 0x100MB
SysmemInit: enable for 256MBytes
usable RAM: 268304383 bytes
SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
SMMGL1Init:
SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
L2 cache enabled
Enabling cache
GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
Exit northbridge_init_early
Done cpubug fixes
Not Doing ChipsetFlashSetup()
Preparing for VSA...
VSA: Real mode stub @00000600: 862 bytes
Searching for vsa
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Stage: loading vsa @ 0x60000 (57504 bytes), entry @ 0x60020
Stage: done loading.
VSA: Buffer @00060000 *[0k]=ba
VSA: Signature *[0x20-0x23] is b0:10:e6:80
Calling VSA module...
... VSA module returned.
VSM: VSA2 VR signature verified.
Graphics init...
VRC_VG value: 0x2808
Finding PCI configuration type.
PCI: Using configuration type 1
PCI_DOMAIN: 0000 enabled
>> Entering northbridge.c: enable_dev with path 7
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
>> Entering northbridge.c: enable_dev with path 2
PCI: 00:01.0 [1022/2080] ops
PCI: 00:01.0 [1022/2080] enabled
>> Entering northbridge.c: enable_dev with path 2
PCI: 00:01.1 [1022/2081] enabled
PCI: 00:01.2 [1022/2082] enabled
PCI: 00:09.0 [1106/3053] enabled
PCI: 00:0a.0 [1106/3053] enabled
PCI: 00:0c.0 [168c/0013] enabled
cs5536: southbridge_enable: dev is 00112660
PCI: 00:0f.0 [1022/2090] bus ops
PCI: 00:0f.0 [1022/2090] enabled
cs5536: southbridge_enable: dev is 001126a8
PCI: Static device PCI: 00:0f.1 not found, disabling it.
cs5536: southbridge_enable: dev is 001126f0
PCI: 00:0f.2 [1022/209a] ops
PCI: 00:0f.2 [1022/209a] enabled
PCI: 00:0f.3 [1022/2093] enabled
cs5536: southbridge_enable: dev is 00112738
PCI: 00:0f.4 [1022/2094] enabled
cs5536: southbridge_enable: dev is 00112780
PCI: 00:0f.5 [1022/2095] enabled
PCI: 00:0f.6 [1022/2096] enabled
PCI: 00:0f.7 [1022/2097] enabled
scan_static_bus for PCI: 00:0f.0
scan_static_bus for PCI: 00:0f.0 done
PCI: pci_scan_bus returning with max=000
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 00:01.1
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10
   PCI: 00:01.1
   PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
   PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
   PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
   PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
   PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20
   PCI: 00:01.2
   PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
   PCI: 00:09.0
   PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
   PCI: 00:0a.0
   PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
   PCI: 00:0a.0 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 14
   PCI: 00:0c.0
   PCI: 00:0c.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10
   PCI: 00:0f.0
   PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
   PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18
   PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c
   PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20
   PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
   PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:0f.1
   PCI: 00:0f.2
   PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:0f.3
   PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
   PCI: 00:0f.4
   PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:0f.5
   PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:0f.6
   PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
   PCI: 00:0f.7
   PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:09.0 10 *  [0x0 - 0xff] io
PCI: 00:0a.0 10 *  [0x400 - 0x4ff] io
PCI: 00:0f.0 14 *  [0x800 - 0x8ff] io
PCI: 00:0f.0 20 *  [0xc00 - 0xc7f] io
PCI: 00:0f.3 10 *  [0xc80 - 0xcff] io
PCI: 00:0f.0 18 *  [0x1000 - 0x103f] io
PCI: 00:0f.0 24 *  [0x1040 - 0x107f] io
PCI: 00:0f.0 1c *  [0x1080 - 0x109f] io
PCI: 00:0f.2 20 *  [0x10a0 - 0x10af] io
PCI: 00:0f.0 10 *  [0x10b0 - 0x10b7] io
PCI: 00:01.0 10 *  [0x10b8 - 0x10bb] io
PCI_DOMAIN: 0000 compute_resources_io: base: 10bc size: 10bc align: 8 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:01.1 10 *  [0x0 - 0xffffff] mem
PCI: 00:0c.0 10 *  [0x1000000 - 0x100ffff] mem
PCI: 00:01.1 14 *  [0x1010000 - 0x1013fff] mem
PCI: 00:01.1 18 *  [0x1014000 - 0x1017fff] mem
PCI: 00:01.1 1c *  [0x1018000 - 0x101bfff] mem
PCI: 00:01.1 20 *  [0x101c000 - 0x101ffff] mem
PCI: 00:01.2 10 *  [0x1020000 - 0x1023fff] mem
PCI: 00:0f.6 10 *  [0x1024000 - 0x1025fff] mem
PCI: 00:0f.4 10 *  [0x1026000 - 0x1026fff] mem
PCI: 00:0f.5 10 *  [0x1027000 - 0x1027fff] mem
PCI: 00:0f.7 10 *  [0x1028000 - 0x1028fff] mem
PCI: 00:09.0 14 *  [0x1029000 - 0x10290ff] mem
PCI: 00:0a.0 14 *  [0x1029100 - 0x10291ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 1029200 size: 1029200 align: 24 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:01.1
constrain_resources: PCI: 00:01.2
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 00:0c.0
constrain_resources: PCI: 00:0f.0
constrain_resources: PCI: 00:0f.2
constrain_resources: PCI: 00:0f.3
constrain_resources: PCI: 00:0f.4
constrain_resources: PCI: 00:0f.5
constrain_resources: PCI: 00:0f.6
constrain_resources: PCI: 00:0f.7
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
        lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
        lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:10bc align:8 gran:0 limit:ffff
Assigned: PCI: 00:09.0 10 *  [0x1000 - 0x10ff] io
Assigned: PCI: 00:0a.0 10 *  [0x1400 - 0x14ff] io
Assigned: PCI: 00:0f.0 14 *  [0x1800 - 0x18ff] io
Assigned: PCI: 00:0f.0 20 *  [0x1c00 - 0x1c7f] io
Assigned: PCI: 00:0f.3 10 *  [0x1c80 - 0x1cff] io
Assigned: PCI: 00:0f.0 18 *  [0x2000 - 0x203f] io
Assigned: PCI: 00:0f.0 24 *  [0x2040 - 0x207f] io
Assigned: PCI: 00:0f.0 1c *  [0x2080 - 0x209f] io
Assigned: PCI: 00:0f.2 20 *  [0x20a0 - 0x20af] io
Assigned: PCI: 00:0f.0 10 *  [0x20b0 - 0x20b7] io
Assigned: PCI: 00:01.0 10 *  [0x20b8 - 0x20bb] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 20bc size: 10bc align: 8 gran: 0 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:fd000000 size:1029200 align:24 gran:0 limit:febfffff
Assigned: PCI: 00:01.1 10 *  [0xfd000000 - 0xfdffffff] mem
Assigned: PCI: 00:0c.0 10 *  [0xfe000000 - 0xfe00ffff] mem
Assigned: PCI: 00:01.1 14 *  [0xfe010000 - 0xfe013fff] mem
Assigned: PCI: 00:01.1 18 *  [0xfe014000 - 0xfe017fff] mem
Assigned: PCI: 00:01.1 1c *  [0xfe018000 - 0xfe01bfff] mem
Assigned: PCI: 00:01.1 20 *  [0xfe01c000 - 0xfe01ffff] mem
Assigned: PCI: 00:01.2 10 *  [0xfe020000 - 0xfe023fff] mem
Assigned: PCI: 00:0f.6 10 *  [0xfe024000 - 0xfe025fff] mem
Assigned: PCI: 00:0f.4 10 *  [0xfe026000 - 0xfe026fff] mem
Assigned: PCI: 00:0f.5 10 *  [0xfe027000 - 0xfe027fff] mem
Assigned: PCI: 00:0f.7 10 *  [0xfe028000 - 0xfe028fff] mem
Assigned: PCI: 00:09.0 14 *  [0xfe029000 - 0xfe0290ff] mem
Assigned: PCI: 00:0a.0 14 *  [0xfe029100 - 0xfe0291ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe029200 size: 1029200 align: 24 gran: 0 done
Root Device assign_resources, bus 0 link: 0
>> Entering northbridge.c: pci_domain_set_resources
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem
PCI: 00:01.1 14 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 18 <- [0x00fe014000 - 0x00fe017fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 1c <- [0x00fe018000 - 0x00fe01bfff] size 0x00004000 gran 0x0e mem
PCI: 00:01.1 20 <- [0x00fe01c000 - 0x00fe01ffff] size 0x00004000 gran 0x0e mem
PCI: 00:01.2 10 <- [0x00fe020000 - 0x00fe023fff] size 0x00004000 gran 0x0e mem
PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 00:09.0 14 <- [0x00fe029000 - 0x00fe0290ff] size 0x00000100 gran 0x08 mem
PCI: 00:0a.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
PCI: 00:0a.0 14 <- [0x00fe029100 - 0x00fe0291ff] size 0x00000100 gran 0x08 mem
PCI: 00:0c.0 10 <- [0x00fe000000 - 0x00fe00ffff] size 0x00010000 gran 0x10 mem
PCI: 00:0f.0 10 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io
PCI: 00:0f.0 14 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
PCI: 00:0f.0 18 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
PCI: 00:0f.0 1c <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io
PCI: 00:0f.0 20 <- [0x0000001c00 - 0x0000001c7f] size 0x00000080 gran 0x07 io
PCI: 00:0f.0 24 <- [0x0000002040 - 0x000000207f] size 0x00000040 gran 0x06 io
PCI: 00:0f.2 20 <- [0x00000020a0 - 0x00000020af] size 0x00000010 gran 0x04 io
PCI: 00:0f.3 10 <- [0x0000001c80 - 0x0000001cff] size 0x00000080 gran 0x07 io
PCI: 00:0f.4 10 <- [0x00fe026000 - 0x00fe026fff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.5 10 <- [0x00fe027000 - 0x00fe027fff] size 0x00001000 gran 0x0c mem
PCI: 00:0f.6 10 <- [0x00fe024000 - 0x00fe025fff] size 0x00002000 gran 0x0d mem
PCI: 00:0f.7 10 <- [0x00fe028000 - 0x00fe028fff] size 0x00001000 gran 0x0c mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:01.0
  PCI_DOMAIN: 0000 resource base 1000 size 10bc align 8 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base fd000000 size 1029200 align 24 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  PCI_DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b
   PCI: 00:01.0
   PCI: 00:01.0 resource base 20b8 size 4 align 2 gran 2 limit ffff flags 40000100 index 10
   PCI: 00:01.1
   PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
   PCI: 00:01.1 resource base fe010000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14
   PCI: 00:01.1 resource base fe014000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18
   PCI: 00:01.1 resource base fe018000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 1c
   PCI: 00:01.1 resource base fe01c000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 20
   PCI: 00:01.2
   PCI: 00:01.2 resource base fe020000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10
   PCI: 00:09.0
   PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
   PCI: 00:09.0 resource base fe029000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
   PCI: 00:0a.0
   PCI: 00:0a.0 resource base 1400 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
   PCI: 00:0a.0 resource base fe029100 size 100 align 8 gran 8 limit febfffff flags 60000200 index 14
   PCI: 00:0c.0
   PCI: 00:0c.0 resource base fe000000 size 10000 align 16 gran 16 limit febfffff flags 60000200 index 10
   PCI: 00:0f.0
   PCI: 00:0f.0 resource base 20b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
   PCI: 00:0f.0 resource base 2000 size 40 align 6 gran 6 limit ffff flags 60000100 index 18
   PCI: 00:0f.0 resource base 2080 size 20 align 5 gran 5 limit ffff flags 60000100 index 1c
   PCI: 00:0f.0 resource base 1c00 size 80 align 7 gran 7 limit ffff flags 60000100 index 20
   PCI: 00:0f.0 resource base 2040 size 40 align 6 gran 6 limit ffff flags 60000100 index 24
   PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
   PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:0f.1
   PCI: 00:0f.2
   PCI: 00:0f.2 resource base 20a0 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:0f.3
   PCI: 00:0f.3 resource base 1c80 size 80 align 7 gran 7 limit ffff flags 60000100 index 10
   PCI: 00:0f.4
   PCI: 00:0f.4 resource base fe026000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:0f.5
   PCI: 00:0f.5 resource base fe027000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:0f.6
   PCI: 00:0f.6 resource base fe024000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10
   PCI: 00:0f.7
   PCI: 00:0f.7 resource base fe028000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
  APIC_CLUSTER: 0 child on link 0 APIC: 00
   APIC: 00
Done allocating resources.
Enabling resources...
PCI: 00:01.0 cmd <- 05
PCI: 00:01.1 subsystem <- 0000/0000
PCI: 00:01.1 cmd <- 03
PCI: 00:01.2 cmd <- 02
PCI: 00:09.0 cmd <- 83
PCI: 00:0a.0 cmd <- 83
PCI: 00:0c.0 cmd <- 02
PCI: 00:0f.0 cmd <- 09
PCI: 00:0f.2 cmd <- 01
PCI: 00:0f.3 cmd <- 01
PCI: 00:0f.4 subsystem <- 0000/0000
PCI: 00:0f.4 cmd <- 02
PCI: 00:0f.5 subsystem <- 0000/0000
PCI: 00:0f.5 cmd <- 02
PCI: 00:0f.6 cmd <- 02
PCI: 00:0f.7 cmd <- 02
done.
Initializing devices...
Root Device init
ALIX.2D ENTER init
ALIX.2D EXIT init
APIC_CLUSTER: 0 init
>> Entering northbridge.c: cpu_bus_init
Initializing CPU #0
CPU: vendor AMD device 5a2
CPU: family 05, model 0a, stepping 02
model_lx_init
Enabling cache
A20 (0x92): 2
A20 (0x92): 2
CPU model_lx_init DONE
CPU #0 initialized
PCI: 00:01.0 init
>> Entering northbridge.c: northbridge_init
PCI: 00:01.1 init
Searching for pci1022,2081.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2081.rom'.
PCI: 00:01.2 init
Searching for pci1022,2082.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2082.rom'.
PCI: 00:09.0 init
Searching for pci1106,3053.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1106,3053.rom'.
PCI: 00:0a.0 init
Searching for pci1106,3053.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1106,3053.rom'.
PCI: 00:0c.0 init
Searching for pci168c,0013.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci168c,0013.rom'.
PCI: 00:0f.0 init
cs5536: southbridge_init
RTC Init
GPIO_ADDR: 00001800
uarts_init: enable COM1
uarts_init: enable COM2
uarts_init: wrote COM2 address 0x2f8
uarts_init: set COM2 irq
uarts_init: set output enable
uarts_init: set OUTAUX1
uarts_init: set pullup COM2
uarts_init: COM2 enabled
cs5536: southbridge_init: enable_ide_nand_flash is 0
Disabling VPCI device: 0x80000900
Disabling VPCI device: 0x80007B00
PCI: 00:0f.2 init
cs5536_ide: ide_init
PCI: 00:0f.3 init
Searching for pci1022,2093.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2093.rom'.
PCI: 00:0f.4 init
Searching for pci1022,2094.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2094.rom'.
PCI: 00:0f.5 init
Searching for pci1022,2095.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2095.rom'.
PCI: 00:0f.6 init
Searching for pci1022,2096.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2096.rom'.
PCI: 00:0f.7 init
Searching for pci1022,2097.rom
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Check vsa
Check config
Check
ERROR: No file header found at fffffd40, attempting to recover by searching for header
Could not find file 'pci1022,2097.rom'.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:0f.0: enabled 1
PCI: 00:0f.1: enabled 0
PCI: 00:0f.2: enabled 1
PCI: 00:0f.4: enabled 1
PCI: 00:0f.5: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI: 00:01.2: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:0c.0: enabled 1
PCI: 00:0f.3: enabled 1
PCI: 00:0f.6: enabled 1
PCI: 00:0f.7: enabled 1
CPU: 00: enabled 1
Initializing CBMEM area to 0xf7d0000 (65536 bytes)
Adding CBMEM entry as no. 1
Moving GDT to 0f7d0200...ok
High Tables Base is f7d0000.
Copying Interrupt Routing Table to 0x000f0000... done.
PIRQ Entry 0 Dev/Fn: 1 Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:1.2
i8259_configure_irq_trigger: current interrupts are 0x0
i8259_configure_irq_trigger: try to set interrupts 0x800
PIRQ Entry 1 Dev/Fn: 9 Slot: 0
INT: A link: 2 bitmap: 400  IRQ: 10
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 10 to 0:9.0
i8259_configure_irq_trigger: current interrupts are 0x800
i8259_configure_irq_trigger: try to set interrupts 0xc00
PIRQ Entry 2 Dev/Fn: A Slot: 0
INT: A link: 3 bitmap: 800  IRQ: 11
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:a.0
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xc00
PIRQ Entry 3 Dev/Fn: B Slot: 0
INT: A link: 4 bitmap: 200  IRQ: 9
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
PIRQ Entry 4 Dev/Fn: C Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 2 bitmap: 400  IRQ: 10
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:c.0
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xc00
PIRQ Entry 5 Dev/Fn: E Slot: 0
INT: A link: 3 bitmap: 800  IRQ: 11
INT: B link: 4 bitmap: 200  IRQ: 9
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
PIRQ Entry 6 Dev/Fn: F Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 2 bitmap: 400  IRQ: 10
INT: C link: 3 bitmap: 800  IRQ: 11
INT: D link: 4 bitmap: 200  IRQ: 9
Assigning IRQ 9 to 0:f.4
i8259_configure_irq_trigger: current interrupts are 0xc00
i8259_configure_irq_trigger: try to set interrupts 0xe00
Assigning IRQ 9 to 0:f.5
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ1: 11
PIRQ2: 10
PIRQ3: 11
PIRQ4: 9
Adding CBMEM entry as no. 2
Copying Interrupt Routing Table to 0x0f7d0400... done.
PIRQ Entry 0 Dev/Fn: 1 Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:1.2
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ Entry 1 Dev/Fn: 9 Slot: 0
INT: A link: 2 bitmap: 400  IRQ: 10
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 10 to 0:9.0
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ Entry 2 Dev/Fn: A Slot: 0
INT: A link: 3 bitmap: 800  IRQ: 11
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:a.0
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ Entry 3 Dev/Fn: B Slot: 0
INT: A link: 4 bitmap: 200  IRQ: 9
INT: B link: 0 bitmap: 0  not routed
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
PIRQ Entry 4 Dev/Fn: C Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 2 bitmap: 400  IRQ: 10
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
Assigning IRQ 11 to 0:c.0
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ Entry 5 Dev/Fn: E Slot: 0
INT: A link: 3 bitmap: 800  IRQ: 11
INT: B link: 4 bitmap: 200  IRQ: 9
INT: C link: 0 bitmap: 0  not routed
INT: D link: 0 bitmap: 0  not routed
PIRQ Entry 6 Dev/Fn: F Slot: 0
INT: A link: 1 bitmap: 800  IRQ: 11
INT: B link: 2 bitmap: 400  IRQ: 10
INT: C link: 3 bitmap: 800  IRQ: 11
INT: D link: 4 bitmap: 200  IRQ: 9
Assigning IRQ 9 to 0:f.4
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
Assigning IRQ 9 to 0:f.5
i8259_configure_irq_trigger: current interrupts are 0xe00
i8259_configure_irq_trigger: try to set interrupts 0xe00
PIRQ1: 11
PIRQ2: 10
PIRQ3: 11
PIRQ4: 9
PIRQ table: 144 bytes.
Adding CBMEM entry as no. 3
smbios_write_tables: 0f7d1400
Root Device (PC Engines ALIX.2D Mainboard)
PCI_DOMAIN: 0000 (AMD LX Northbridge)
PCI: 00:01.0 (AMD LX Northbridge)
PCI: 00:01.1 (AMD LX Northbridge)
PCI: 00:0f.0 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.1 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.2 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.4 (AMD Geode CS5536 Southbridge)
PCI: 00:0f.5 (AMD Geode CS5536 Southbridge)
APIC_CLUSTER: 0 (AMD LX Northbridge)
APIC: 00 ()
PCI: 00:01.2 ()
PCI: 00:09.0 ()
PCI: 00:0a.0 ()
PCI: 00:0c.0 ()
PCI: 00:0f.3 ()
PCI: 00:0f.6 ()
PCI: 00:0f.7 ()
CPU: 00 ()
SMBIOS tables: 297 bytes.
Adding CBMEM entry as no. 4
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum d461
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x0f7d1c00
rom_table_end = 0x0f7d1c00
Adjust low_table_end from 0x00000518 to 0x00001000
Adjust rom_table_end from 0x0f7d1c00 to 0x0f7e0000
Adding high table area
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000000f7cffff: RAM
 3. 000000000f7d0000-000000000f7dffff: CONFIGURATION TABLES
Wrote coreboot table at: 0f7d1c00 - 0f7d1dcc  checksum b828
coreboot table: 460 bytes.
Multiboot Information structure has been written.
 0. FREE SPACE 0f7d3c00 0000c400
 1. GDT        0f7d0200 00000200
 2. IRQ TABLE  0f7d0400 00001000
 3. SMBIOS     0f7d1400 00000800
 4. COREBOOT   0f7d1c00 00002000
Searching for fallback/payload
Check fallback/romstage
Check fallback/coreboot_ram
Check fallback/payload
Got a payload
Loading segment from rom address 0xfff8bcb8
  data (compression=1)
  New segment dstaddr 0xe7e04 memsize 0x181fc srcaddr 0xfff8bcf0 filesize 0xc20b
  (cleaned up) New segment addr 0xe7e04 size 0x181fc offset 0xfff8bcf0 filesize 0xc20b
Loading segment from rom address 0xfff8bcd4
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b
lb: [0x0000000000100000, 0x0000000000124000)
Post relocation: addr: 0x00000000000e7e04 memsz: 0x00000000000181fc filesz: 0x000000000000c20b
using LZMA
[ 0x000e7e04, 00100000, 0x00100000) <- fff8bcf0
dest 000e7e04, end 00100000, bouncebuffer f788000
Loaded segments
Jumping to boot code at fc8c0
entry    = 0x000fc8c0
lb_start = 0x00100000
lb_size  = 0x00024000
adjust   = 0x0f6ac000
buffer   = 0x0f788000
     elf_boot_notes = 0x001127c8
adjusted_boot_notes = 0x0f7be7c8
Start bios (version 1.6.3-20120104_122101-builder)
Found mainboard PC Engines ALIX.6
Found CBFS header at 0xfffffd30
Ram Size=0x0f7d0000 (0x0000000000000000 high)
Relocating init from 0x000e8450 to 0x0f7b57a0 (size 42812)
CPU Mhz=498
Found 9 PCI devices (max PCI bus is 00)
No apic - only the main cpu is present.
Copying SMBIOS entry point from 0x0f7d1400 to 0x000fdbd0
Scan for VGA option rom
EHCI init on dev 00:0f.5 (regs=0xfe027010)
WARNING - Timeout at i8042_flush:69!
Found 0 lpt ports
Found 2 serial ports
ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a)
ATA controller 2 at 170/374/0 (irq 15 dev 7a)
ata0-0: SanDisk SDCFH-002G ATA-4 Hard-Disk (1907 MiBytes)
Searching bootorder for: /pci at i0cf8/*@f,2/drive at 0/disk at 0
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fdb80: PCHS=3875/16/63 translation=large LCHS=968/64/63 s=3906560
Returned 65536 bytes of ZoneHigh
e820 map has 5 items:
  0: 0000000000000000 - 000000000009fc00 = 1 RAM
  1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000000f7d0000 = 1 RAM
  4: 000000000f7d0000 - 000000000f7e0000 = 2 RESERVED
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
Press any key to continue.
Press any key to continue.

==========


And then the linux early-printk logging begins.

Peter suggests it's an issue with the MTRR not being set up correctly (for caching), and is the same problem.

I'm seeing a 27-second pause after this line:

Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ 0x100000

Also, the Alix 6F2 doesn't have a keyboard controller... is there a way to turn off the i8042 stuff?

Thanks,

-Philip



From rminnich at gmail.com  Fri Jan  6 06:40:58 2012
From: rminnich at gmail.com (ron minnich)
Date: Thu, 5 Jan 2012 21:40:58 -0800
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <4F0662F3.6050908@redfish-solutions.com>
References: <4F0662F3.6050908@redfish-solutions.com>
Message-ID: <CAP6exYJXrAmTHA4OuBaehzsih_3_qeL4_TGE7wT=QWVERR53CQ@mail.gmail.com>

On Thu, Jan 5, 2012 at 6:56 PM, Philip Prindeville
<philipp_subx at redfish-solutions.com> wrote:

> Also, the Alix 6F2 doesn't have a keyboard controller... is there a way to turn off the i8042 stuff?

it used to be as simple as not putting pc80/keyboard or some such in
the mainboard Config. I'll look tomorrow if I get time.

ron


From gerrit at coreboot.org  Fri Jan  6 19:53:34 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:53:34 +0100
Subject: [coreboot] Patch set updated for coreboot: ba5be28
	cb_parse_header() should not assume table in 4K of contiguous memory
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
Message-ID: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+4@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501

-gerrit

commit ba5be2861e5adcc3cb990cc219e4207947beefde
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:09:25 2011 -0700

    cb_parse_header() should not assume table in 4K of contiguous memory
    
    If we have the CB table in E820 memory, we might not have an entire 4K
    (0x1000) bytes of memory to scan through. Instead, a better strategy
    is to pass in a pointer to the end of the region or the start + 4K
    (which ever is lower). This change prepares the cb_parse_header()
    calling convention for that change.
    
    Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..135c59c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = addr;
+	unsigned char *ptr;
 	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (ptr = addr; (void *)ptr < end; ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
@@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
-			return cb_parse_header(forward, len, info);
+			return cb_parse_header(forward, forward + 0x1000, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
@@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }


From gerrit at coreboot.org  Fri Jan  6 19:53:35 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:53:35 +0100
Subject: [coreboot] Patch set updated for coreboot: dd391db Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+5@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit dd391db0f9c89c83ff8e57950765430d89cd8feb
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 135c59c..7fe286e 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Fri Jan  6 19:56:18 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:18 +0100
Subject: [coreboot] New patch to review for coreboot: c3dc279 geos: missing
	Vendor information
References: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+0@gerrit.coreboot.org>
Message-ID: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520

-gerrit

commit c3dc279f497fe87af38b1efb4cc1ebf878264d9b
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:52:25 2012 -0700

    geos: missing Vendor information
    
    The DMI information isn't being generated correctly because of the
    mainboard vendor value not being set.
    
    Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index b455f60..5f00230 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -17,6 +17,10 @@ config MAINBOARD_DIR
 	string
 	default traverse/geos
 
+config MAINBOARD_VENDOR
+	string
+	default "PC Engines"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Geos"


From gerrit at coreboot.org  Fri Jan  6 19:56:19 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:19 +0100
Subject: [coreboot] New patch to review for coreboot: 7f5fb24 alix2: add
	support for alix6
References: <I19e4e756966e60bb0310c19286654d3d579b8850+0@gerrit.coreboot.org>
Message-ID: <I19e4e756966e60bb0310c19286654d3d579b8850+1@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/521

-gerrit

commit 7f5fb249802c8b4f7f26e9ef3869f14e83bba68b
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:54:23 2012 -0700

    alix2: add support for alix6
    
    The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
    slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
    SIM sockets.
    
    Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/Kconfig        |    2 ++
 src/mainboard/pcengines/alix2d/Kconfig |    9 ++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index d5d7008..d8a0201 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -7,6 +7,8 @@ config BOARD_PCENGINES_ALIX1C
 	bool "ALIX.1C"
 config BOARD_PCENGINES_ALIX2D
 	bool "ALIX.2D2 or 2D3"
+config BOARD_PCENGINES_ALIX6
+	bool "ALIX.6"
 
 endchoice
 
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index ea02adf..5036dcb 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_PCENGINES_ALIX2D
+if BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
 	select CONSOLE_SERIAL_38400
+	select GEODE_VSA
+	select GEODE_VSA_FILE
 
 config MAINBOARD_DIR
 	string
@@ -19,10 +21,11 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "ALIX.2D"
+	default "ALIX.2D" if BOARD_PCENGINES_ALIX2D
+	default "ALIX.6" if BOARD_PCENGINES_ALIX6
 
 config IRQ_SLOT_COUNT
 	int
 	default 7
 
-endif # BOARD_PCENGINES_ALIX2D
+endif # BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6


From gerrit at coreboot.org  Fri Jan  6 19:56:19 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:19 +0100
Subject: [coreboot] Patch set updated for coreboot: b731758 Set default
	baudrate on Alix2d to be compatible with factory default
References: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+0@gerrit.coreboot.org>
Message-ID: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508

-gerrit

commit b731758d195f1e0174afb77d6a310ebd91768fc5
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 28 16:32:44 2011 -0700

    Set default baudrate on Alix2d to be compatible with factory default
    
    Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99)
    boot up at 38400. In keeping with the principle of least astonishment,
    boards reflashed with SeaBIOS should probably try to keep compatible
    with this setting.
    
    Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/alix2d/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..ea02adf 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select CONSOLE_SERIAL_38400
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Fri Jan  6 19:56:20 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:20 +0100
Subject: [coreboot] Patch set updated for coreboot: 2ba6d09 Add rules to
	pull down and uncompress gpl_vsa_lx_102.bin
References: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+0@gerrit.coreboot.org>
Message-ID: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509

-gerrit

commit 2ba6d099f1f808c4592ff273d14c0de414fe1d61
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Thu Dec 29 12:21:39 2011 -0700

    Add rules to pull down and uncompress gpl_vsa_lx_102.bin
    
    These steps are in the Wiki, but they should be automated.
    
    Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/arch/x86/Makefile.inc |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..a95fd62 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -396,3 +396,8 @@ filo:
 			CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \
 			CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE)
 
+gpl_vsa_lx_102.bin.gz:
+	@wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz
+
+gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz
+	@gunzip $^


From gerrit at coreboot.org  Fri Jan  6 19:56:21 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:21 +0100
Subject: [coreboot] Patch set updated for coreboot: 33dd7a8 geos: Explicitly
	set console baud rate
References: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+0@gerrit.coreboot.org>
Message-ID: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/513

-gerrit

commit 33dd7a89e6c3214947ed8cc879819e6c89b0f6e3
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 31 19:29:21 2011 -0700

    geos: Explicitly set console baud rate
    
    If the default baud rate changes, we should remain compatible with
    earlier published coreboot images.
    
    Change-Id: I4e6b5515395a9de237ad8f758f6f66fb825262eb
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..b455f60 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_1024
 	select POWER_BUTTON_DEFAULT_DISABLE
+	select CONSOLE_SERIAL_115200
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Fri Jan  6 19:56:46 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:46 +0100
Subject: [coreboot] Patch set updated for coreboot: c3a4a42
	cb_parse_header() should not assume table in 4K of contiguous memory
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
Message-ID: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+5@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501

-gerrit

commit c3a4a4242a4c9d428638f271e95ed6d6d8cde2d4
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:09:25 2011 -0700

    cb_parse_header() should not assume table in 4K of contiguous memory
    
    If we have the CB table in E820 memory, we might not have an entire 4K
    (0x1000) bytes of memory to scan through. Instead, a better strategy
    is to pass in a pointer to the end of the region or the start + 4K
    (which ever is lower). This change prepares the cb_parse_header()
    calling convention for that change.
    
    Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
 1 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..135c59c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
+static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 {
 	struct cb_header *header;
-	unsigned char *ptr = addr;
+	unsigned char *ptr;
 	void *forward;
 	int i;
 
-	for (i = 0; i < len; i += 16, ptr += 16) {
+	for (ptr = addr; (void *)ptr < end; ptr += 16) {
 		header = (struct cb_header *)ptr;
 		if (!strncmp((const char *)header->signature, "LBIO", 4))
 			break;
 	}
 
 	/* We walked the entire space and didn't find anything. */
-	if (i >= len)
+	if ((void *)ptr >= end)
 		return -1;
 
 	if (!header->table_bytes)
@@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		switch (rec->tag) {
 		case CB_TAG_FORWARD:
 			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
-			return cb_parse_header(forward, len, info);
+			return cb_parse_header(forward, forward + 0x1000, info);
 			continue;
 		case CB_TAG_MEMORY:
 			cb_parse_memory(ptr, info);
@@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		}
 
 		ptr += rec->size;
+
+		if ((void *)ptr >= end)
+			return -1;
 	}
 
 	return 1;
@@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 
 int get_coreboot_info(struct sysinfo_t *info)
 {
-	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
+	void *base = phys_to_virt(0x00000000);
+	int ret = cb_parse_header(base, base + 0x1000, info);
 
-	if (ret != 1)
-		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
+	if (ret != 1) {
+		base = phys_to_virt(0x000f0000);
+		ret = cb_parse_header(base, base + 0x1000, info);
+	}
 
 	return (ret == 1) ? 0 : -1;
 }


From gerrit at coreboot.org  Fri Jan  6 19:56:48 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 19:56:48 +0100
Subject: [coreboot] Patch set updated for coreboot: c12bc24 Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+6@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit c12bc24e681e14e75699c65d3aa6575a76b89f62
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 135c59c..7fe286e 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From philipp_subx at redfish-solutions.com  Fri Jan  6 20:12:17 2012
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Fri, 06 Jan 2012 12:12:17 -0700
Subject: [coreboot] Patch set updated for coreboot: ba5be28
 cb_parse_header() should not assume table in 4K of contiguous memory
In-Reply-To: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+4@gerrit.coreboot.org>
References: <I9257726c6a7065b5596d4c32ab451edd0a3cdc10+0@gerrit.coreboot.org>
	<I9257726c6a7065b5596d4c32ab451edd0a3cdc10+4@gerrit.coreboot.org>
Message-ID: <4F074791.3080107@redfish-solutions.com>

Ok, didn't know that was still in my "git commit" list waiting for a "git push"...

Should have checked.

On 1/6/12 11:53 AM, Philip Prindeville (pprindeville at gmail.com) wrote:
> Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/501
> 
> -gerrit
> 
> commit ba5be2861e5adcc3cb990cc219e4207947beefde
> Author: Philip Prindeville <philipp at redfish-solutions.com>
> Date:   Fri Dec 23 18:09:25 2011 -0700
> 
>     cb_parse_header() should not assume table in 4K of contiguous memory
>     
>     If we have the CB table in E820 memory, we might not have an entire 4K
>     (0x1000) bytes of memory to scan through. Instead, a better strategy
>     is to pass in a pointer to the end of the region or the start + 4K
>     (which ever is lower). This change prepares the cb_parse_header()
>     calling convention for that change.
>     
>     Change-Id: I9257726c6a7065b5596d4c32ab451edd0a3cdc10
>     Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
> ---
>  payloads/libpayload/arch/i386/coreboot.c |   22 ++++++++++++++--------
>  1 files changed, 14 insertions(+), 8 deletions(-)
> 
> diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
> index 709f8ae..135c59c 100644
> --- a/payloads/libpayload/arch/i386/coreboot.c
> +++ b/payloads/libpayload/arch/i386/coreboot.c
> @@ -109,21 +109,21 @@ static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
>  }
>  #endif
>  
> -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
> +static int cb_parse_header(void *addr, void *end, struct sysinfo_t *info)
>  {
>  	struct cb_header *header;
> -	unsigned char *ptr = addr;
> +	unsigned char *ptr;
>  	void *forward;
>  	int i;
>  
> -	for (i = 0; i < len; i += 16, ptr += 16) {
> +	for (ptr = addr; (void *)ptr < end; ptr += 16) {
>  		header = (struct cb_header *)ptr;
>  		if (!strncmp((const char *)header->signature, "LBIO", 4))
>  			break;
>  	}
>  
>  	/* We walked the entire space and didn't find anything. */
> -	if (i >= len)
> +	if ((void *)ptr >= end)
>  		return -1;
>  
>  	if (!header->table_bytes)
> @@ -147,7 +147,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
>  		switch (rec->tag) {
>  		case CB_TAG_FORWARD:
>  			forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward);
> -			return cb_parse_header(forward, len, info);
> +			return cb_parse_header(forward, forward + 0x1000, info);
>  			continue;
>  		case CB_TAG_MEMORY:
>  			cb_parse_memory(ptr, info);
> @@ -176,6 +176,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
>  		}
>  
>  		ptr += rec->size;
> +
> +		if ((void *)ptr >= end)
> +			return -1;
>  	}
>  
>  	return 1;
> @@ -186,10 +189,13 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
>  
>  int get_coreboot_info(struct sysinfo_t *info)
>  {
> -	int ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
> +	void *base = phys_to_virt(0x00000000);
> +	int ret = cb_parse_header(base, base + 0x1000, info);
>  
> -	if (ret != 1)
> -		ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
> +	if (ret != 1) {
> +		base = phys_to_virt(0x000f0000);
> +		ret = cb_parse_header(base, base + 0x1000, info);
> +	}
>  
>  	return (ret == 1) ? 0 : -1;
>  }
> 



From svn at coreboot.org  Fri Jan  6 20:12:45 2012
From: svn at coreboot.org (coreboot)
Date: Fri, 06 Jan 2012 19:12:45 -0000
Subject: [coreboot]  #184: Asus p2b with aty128 fails
Message-ID: <064.bbc3fb0bf69d2039d2b6c9a5bc500cb1@coreboot.org>

#184: Asus p2b with aty128 fails
--------------------------------+------------------------------------------
    Reporter:                   |         Owner:  stepan@?
  jeroenkrabbendam@?            |        Status:  new
        Type:  defect           |     Milestone:
    Priority:  minor            |      Keywords:  Asus p2b & aty128 failure
   Component:  coreboot         |  Patch Status:  there is no patch
Dependencies:                   |
--------------------------------+------------------------------------------
 both Asus P2B mobo's (core)boot fine with several AGP and PCI video cards.
 However, equipped with a ATY128, nothing happens, not even debug output by
 the NE2K nic. With the original BIOS, everything is OK, so I assume it's a
 coreboot problem.

 Tested with several S3 PCI cards (all ok), several AGP cards (i.e. Sis,
 S3, MGA), all went fine. Except for the ATY128. (Note however my next
 ticket, addressing netboot failure.)

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/184>
coreboot <http://www.coreboot.org/>


From njacobs8 at adsltotaal.nl  Fri Jan  6 19:43:18 2012
From: njacobs8 at adsltotaal.nl (Nils)
Date: Fri, 06 Jan 2012 19:43:18 +0100
Subject: [coreboot] tiny bootblock problem
Message-ID: <1325875398.2692.20.camel@Debian.lan>

Patrick Georgi:
>> Is that a caching problem introduced by tiny bootblock?
>> What is needed to get it right?
>Probably MTRRs. With tinybootblock, these are set at slightly
>different times.
>GX2 uses Cache-As-RAM, right? That affects MTRRs, too (as CAR is a 
>"special" MTRR setup)

Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
Cache is setup via MSR registers.
So all that MTRR stuf in tiny bootblok/coreboot is useless to Geode.
Which regions are used for tiny bootblock that need caching?
If no one beets me i will investigate this further after SeaBIOS Geode
VGA is ready. 

Philip Prindeville wrote:
>Also, the Alix 6F2 doesn't have a keyboard controller... is there a way
>to turn off the i8042 stuff?

Those i8042 warning at the beginning before warm reset comes from
SeaBIOS.
There is a SeaBIOS kconfig option to turn off the ps2 controller.

Greetings, Nils.



From svn at coreboot.org  Fri Jan  6 20:13:17 2012
From: svn at coreboot.org (coreboot)
Date: Fri, 06 Jan 2012 19:13:17 -0000
Subject: [coreboot]  #185: Vtech partial success
Message-ID: <064.025b5d79093c4bfac2e2511c7060918d@coreboot.org>

#185: Vtech partial success
-----------------------------------+----------------------------------
    Reporter:  jeroenkrabbendam@?  |         Owner:  stepan@?
        Type:  enhancement         |        Status:  new
    Priority:  trivial             |     Milestone:
   Component:  coreboot            |      Keywords:  VTech success
Dependencies:                      |  Patch Status:  there is no patch
-----------------------------------+----------------------------------
 Picked up an oldfashioned VTech mobo (bios id: ite8671-2A69KV3IC-00), i.e.
 VTech, intel 440BX northbridge, intel 82371 southbridge, IT8671F superio.

 Gigabyte GA-6BX{CE} are close cousins, both run fine, that is, they boot
 from harddisk (I have no floppy anymore, why??)

 Soyo should be a close cousin too, but nothing happens, not even debug
 output on a (Atlantic) NE2K nic.

 However, the Gigabyte coreboot images both refuse to complete a netboot,
 as already noted for my Asus P2B. See next ticket.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/185>
coreboot <http://www.coreboot.org/>


From svn at coreboot.org  Fri Jan  6 20:13:51 2012
From: svn at coreboot.org (coreboot)
Date: Fri, 06 Jan 2012 19:13:51 -0000
Subject: [coreboot]  #186: 3com 3c905tx / gpxe boot problem
Message-ID: <064.5e47ef04816cb0047b4e755a20c55935@coreboot.org>

#186: 3com 3c905tx / gpxe boot problem
-----------------------------------+----------------------------------
    Reporter:  jeroenkrabbendam@?  |         Owner:  stepan@?
        Type:  defect              |        Status:  new
    Priority:  minor               |     Milestone:
   Component:  coreboot            |      Keywords:  gpxe
Dependencies:                      |  Patch Status:  there is no patch
-----------------------------------+----------------------------------
 Although (or: just because) novice in the field, I encountered some
 problems with netbooting with coreboot.

 Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All
 mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE}
 respectively.

 NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy
 slow! Although loading, the kernel is never able to start itself. Same
 kernel on HDU is no problem at all (GRUB2)

 Note: the gpxe-image is on the nic, coreboot payload is seabios.

-- 
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186>
coreboot <http://www.coreboot.org/>


From gerrit at coreboot.org  Fri Jan  6 20:14:20 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 20:14:20 +0100
Subject: [coreboot] Patch set updated for coreboot: 5616f71 Set default
	baudrate on Alix2d to be compatible with factory default
References: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+0@gerrit.coreboot.org>
Message-ID: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+3@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508

-gerrit

commit 5616f71e404771477770ca2ce098bbf36446ed35
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 28 16:32:44 2011 -0700

    Set default baudrate on Alix2d to be compatible with factory default
    
    Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99)
    boot up at 38400. In keeping with the principle of least astonishment,
    boards reflashed with SeaBIOS should probably try to keep compatible
    with this setting.
    
    Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/alix2d/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..ea02adf 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select CONSOLE_SERIAL_38400
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Fri Jan  6 20:14:21 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 20:14:21 +0100
Subject: [coreboot] Patch set updated for coreboot: 903a1d1 Add rules to
	pull down and uncompress gpl_vsa_lx_102.bin
References: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+0@gerrit.coreboot.org>
Message-ID: <I81528dddb47b0cfe4acd33456680f8d3211fabd7+3@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/509

-gerrit

commit 903a1d1c29527e024281d0bb3596c5e817f910b5
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Thu Dec 29 12:21:39 2011 -0700

    Add rules to pull down and uncompress gpl_vsa_lx_102.bin
    
    These steps are in the Wiki, but they should be automated.
    
    Change-Id: I81528dddb47b0cfe4acd33456680f8d3211fabd7
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/arch/x86/Makefile.inc |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..a95fd62 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -396,3 +396,8 @@ filo:
 			CONFIG_FILO_MASTER=$(CONFIG_FILO_MASTER) \
 			CONFIG_FILO_STABLE=$(CONFIG_FILO_STABLE)
 
+gpl_vsa_lx_102.bin.gz:
+	@wget -q http://marcjonesconsulting.com/gplvsa/gpl_vsa_lx_102.bin.gz
+
+gpl_vsa_lx_102.bin: gpl_vsa_lx_102.bin.gz
+	@gunzip $^


From gerrit at coreboot.org  Fri Jan  6 20:14:22 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 20:14:22 +0100
Subject: [coreboot] Patch set updated for coreboot: 54b9674 geos: Explicitly
	set console baud rate
References: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+0@gerrit.coreboot.org>
Message-ID: <I4e6b5515395a9de237ad8f758f6f66fb825262eb+3@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/513

-gerrit

commit 54b96744aeb672bb432ad0144e8a23b2a4afead4
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 31 19:29:21 2011 -0700

    geos: Explicitly set console baud rate
    
    If the default baud rate changes, we should remain compatible with
    earlier published coreboot images.
    
    Change-Id: I4e6b5515395a9de237ad8f758f6f66fb825262eb
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..b455f60 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_1024
 	select POWER_BUTTON_DEFAULT_DISABLE
+	select CONSOLE_SERIAL_115200
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Fri Jan  6 20:14:27 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 20:14:27 +0100
Subject: [coreboot] Patch set updated for coreboot: d0c03b5 geos: missing
	Vendor information
References: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+0@gerrit.coreboot.org>
Message-ID: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520

-gerrit

commit d0c03b53a060c24adc172d60072b0d45be530b38
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:52:25 2012 -0700

    geos: missing Vendor information
    
    The DMI information isn't being generated correctly because of the
    mainboard vendor value not being set.
    
    Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index b455f60..5f00230 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -17,6 +17,10 @@ config MAINBOARD_DIR
 	string
 	default traverse/geos
 
+config MAINBOARD_VENDOR
+	string
+	default "PC Engines"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Geos"


From gerrit at coreboot.org  Fri Jan  6 20:14:27 2012
From: gerrit at coreboot.org (Philip Prindeville (pprindeville@gmail.com))
Date: Fri, 6 Jan 2012 20:14:27 +0100
Subject: [coreboot] Patch set updated for coreboot: f922ea5 alix2: add
	support for alix6
References: <I19e4e756966e60bb0310c19286654d3d579b8850+0@gerrit.coreboot.org>
Message-ID: <I19e4e756966e60bb0310c19286654d3d579b8850+2@gerrit.coreboot.org>

Philip Prindeville (pprindeville at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/521

-gerrit

commit f922ea58e916be60c163a1d83616314d4acfea56
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:54:23 2012 -0700

    alix2: add support for alix6
    
    The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
    slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
    SIM sockets.
    
    Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/Kconfig        |    2 ++
 src/mainboard/pcengines/alix2d/Kconfig |    9 ++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index d5d7008..d8a0201 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -7,6 +7,8 @@ config BOARD_PCENGINES_ALIX1C
 	bool "ALIX.1C"
 config BOARD_PCENGINES_ALIX2D
 	bool "ALIX.2D2 or 2D3"
+config BOARD_PCENGINES_ALIX6
+	bool "ALIX.6"
 
 endchoice
 
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index ea02adf..5036dcb 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_PCENGINES_ALIX2D
+if BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
 	select CONSOLE_SERIAL_38400
+	select GEODE_VSA
+	select GEODE_VSA_FILE
 
 config MAINBOARD_DIR
 	string
@@ -19,10 +21,11 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "ALIX.2D"
+	default "ALIX.2D" if BOARD_PCENGINES_ALIX2D
+	default "ALIX.6" if BOARD_PCENGINES_ALIX6
 
 config IRQ_SLOT_COUNT
 	int
 	default 7
 
-endif # BOARD_PCENGINES_ALIX2D
+endif # BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6


From peter at stuge.se  Fri Jan  6 20:36:43 2012
From: peter at stuge.se (Peter Stuge)
Date: Fri, 6 Jan 2012 20:36:43 +0100
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <1325875398.2692.20.camel@Debian.lan>
References: <1325875398.2692.20.camel@Debian.lan>
Message-ID: <20120106193644.5604.qmail@stuge.se>

Nils wrote:
> >> Is that a caching problem introduced by tiny bootblock?
> >> What is needed to get it right?
> >Probably MTRRs. With tinybootblock, these are set at slightly
> >different times.
> >GX2 uses Cache-As-RAM, right? That affects MTRRs, too (as CAR is a 
> >"special" MTRR setup)
> 
> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
> Cache is setup via MSR registers.
> So all that MTRR stuf in tiny bootblok/coreboot is useless to Geode.
> Which regions are used for tiny bootblock that need caching?

The flash chip, most importantly.


//Peter


From patrick at georgi-clan.de  Fri Jan  6 21:31:10 2012
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 06 Jan 2012 21:31:10 +0100
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <1325875398.2692.20.camel@Debian.lan>
References: <1325875398.2692.20.camel@Debian.lan>
Message-ID: <4F075A0E.1000403@georgi-clan.de>

Am 06.01.2012 19:43, schrieb Nils:
> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
> Cache is setup via MSR registers.
MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
sure if Geode does it the same way, but MSR doesn't mean "no MTRR".


Patrick


From philipp_subx at redfish-solutions.com  Fri Jan  6 21:53:20 2012
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Fri, 06 Jan 2012 13:53:20 -0700
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <4F075A0E.1000403@georgi-clan.de>
References: <1325875398.2692.20.camel@Debian.lan>
	<4F075A0E.1000403@georgi-clan.de>
Message-ID: <4F075F40.3060403@redfish-solutions.com>

On 1/6/12 1:31 PM, Patrick Georgi wrote:
> Am 06.01.2012 19:43, schrieb Nils:
>> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
>> Cache is setup via MSR registers.
> MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
> sure if Geode does it the same way, but MSR doesn't mean "no MTRR".
> 
> 
> Patrick
> 

Caching is bits 30:29 of CR0.

-Philip



From philipp_subx at redfish-solutions.com  Fri Jan  6 23:59:05 2012
From: philipp_subx at redfish-solutions.com (Philip Prindeville)
Date: Fri, 06 Jan 2012 15:59:05 -0700
Subject: [coreboot] tiny bootblock problem
In-Reply-To: <1325890406.2692.29.camel@Debian.lan>
References: <1325890406.2692.29.camel@Debian.lan>
Message-ID: <4F077CB9.6020100@redfish-solutions.com>

On 1/6/12 3:53 PM, Nils wrote:
> Patrick Georgi wrote:
>>> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
>>> Cache is setup via MSR registers.
>> MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
>> sure if Geode does it the same way, but MSR doesn't mean "no MTRR".
> See attachment for part of page 494 of the GX2 databook.:)
>
> Philip Prindeville wrote:
>> Caching is bits 30:29 of CR0.
> There are actually a lot more MSR registers for defining cache regions.
>
> Thanks, Nils. 

I think we have a disconnect on what "Not supported" means. :-)



From njacobs8 at adsltotaal.nl  Fri Jan  6 23:53:26 2012
From: njacobs8 at adsltotaal.nl (Nils)
Date: Fri, 06 Jan 2012 23:53:26 +0100
Subject: [coreboot] tiny bootblock problem
Message-ID: <1325890406.2692.29.camel@Debian.lan>

Patrick Georgi wrote:
>> Correct me if i'm wrong but Geode GX2/LX doesn't have MTRRs.
>> Cache is setup via MSR registers.
>MTRR is usually configured via MSR (0x200 to 0x210, specifically). Not 
>sure if Geode does it the same way, but MSR doesn't mean "no MTRR".

See attachment for part of page 494 of the GX2 databook.:)

Philip Prindeville wrote:
>Caching is bits 30:29 of CR0.

There are actually a lot more MSR registers for defining cache regions.

Thanks, Nils. 
-------------- next part --------------
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From gerrit at coreboot.org  Sat Jan  7 11:25:16 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 7 Jan 2012 11:25:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 08f0b18 Eliminate magic
	numbers
References: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+0@gerrit.coreboot.org>
Message-ID: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/504

-gerrit

commit 08f0b180fe0d7a29a9f4608d536dcc2ce268a7f1
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:45:33 2011 -0700

    Eliminate magic numbers
    
    Use sizeof() on vendor and part# rather than explicit memory length.
    
    Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index d33ea9e..77a4bb2 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
-	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), sizeof(cb_info.vendor) - 1);
+	strncpy(cb_info.part, cb_mb_part_string(mb), sizeof(cb_info.part) - 1);
 }
 
 static void parse_strings(unsigned char *ptr)


From gerrit at coreboot.org  Sat Jan  7 11:25:16 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 7 Jan 2012 11:25:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 9f1890a Cleanup access
	to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+7@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/502

-gerrit

commit 9f1890a5a3ee76dee75f5c356166c0c6b513b7a3
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 payloads/coreinfo/coreboot_module.c           |    4 ++--
 payloads/libpayload/arch/i386/coreboot.c      |    5 +++++
 payloads/libpayload/include/coreboot_tables.h |   16 ++++++++++------
 payloads/libpayload/include/sysinfo.h         |    3 +++
 4 files changed, 20 insertions(+), 8 deletions(-)

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
index 7289366..d33ea9e 100644
--- a/payloads/coreinfo/coreboot_module.c
+++ b/payloads/coreinfo/coreboot_module.c
@@ -142,8 +142,8 @@ static void parse_mainboard(unsigned char *ptr)
 {
 	struct cb_mainboard *mb = (struct cb_mainboard *)ptr;
 
-	strncpy(cb_info.vendor, (const char *)MB_VENDOR_STRING(mb), 31);
-	strncpy(cb_info.part, (const char *)MB_PART_STRING(mb), 31);
+	strncpy(cb_info.vendor, cb_mb_vendor_part(mb), 31);
+	strncpy(cb_info.part, cb_mb_part_string(mb), 31);
 }
 
 static void parse_strings(unsigned char *ptr)
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 709f8ae..06acc17 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -137,6 +137,8 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		     header->table_bytes) != header->table_checksum)
 		return -1;
 
+	info->header = header;
+
 	/* Now, walk the tables. */
 	ptr += header->header_bytes;
 
@@ -173,6 +175,9 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 			cb_parse_framebuffer(ptr, info);
 			break;
 #endif
+		case CB_TAG_MAINBOARD:
+			info->mainboard = (struct cb_mainboard *)ptr;
+			break;
 		}
 
 		ptr += rec->size;
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index e362d06..c68ccc9 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -228,6 +228,16 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	return ipchksum(ptr, len);
 }
 
+static inline const char *cb_mb_vendor_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->vendor_idx);
+}
+
+static inline const char *cb_mb_part_string(const struct cb_mainboard *cbm)
+{
+	return (char *)(cbm->strings + cbm->part_number_idx);
+}
+
 /* Helpful macros */
 
 #define MEM_RANGE_COUNT(_rec) \
@@ -237,10 +247,4 @@ static inline u16 cb_checksum(const void *ptr, unsigned len)
 	(void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \
 		+ (sizeof((_rec)->map[0]) * (_idx)))
 
-#define MB_VENDOR_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
-
-#define MB_PART_STRING(_mb) \
-	(((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
-
 #endif
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index c1d2002..778dfe9 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -56,6 +56,9 @@ struct sysinfo_t {
 	struct cb_framebuffer *framebuffer;
 
 	unsigned long *mbtable; /** Pointer to the multiboot table */
+
+	struct cb_header *header;
+	struct cb_mainboard *mainboard;
 };
 
 extern struct sysinfo_t lib_sysinfo;


From gerrit at coreboot.org  Sat Jan  7 11:44:05 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 7 Jan 2012 11:44:05 +0100
Subject: [coreboot] New patch to review for coreboot: 9faab44 adm1027: add
	return statement
References: <I53741f1136b396e9493ce959b54efc00c9b09764+0@gerrit.coreboot.org>
Message-ID: <I53741f1136b396e9493ce959b54efc00c9b09764+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/522

-gerrit

commit 9faab4477efb6d0102c9854dcc1ecd3f1cac6421
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 7 16:04:46 2012 +0530

    adm1027: add return statement
    
    Adds a missing return statment which will stop misleading the users
    
    Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/drivers/i2c/adm1027/adm1027.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/drivers/i2c/adm1027/adm1027.c b/src/drivers/i2c/adm1027/adm1027.c
index 516a889..e97ec69 100644
--- a/src/drivers/i2c/adm1027/adm1027.c
+++ b/src/drivers/i2c/adm1027/adm1027.c
@@ -35,6 +35,7 @@ static void adm1027_enable_monitoring(device_t dev)
 	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
 	if (!(result & CFG1_STRT)) {
 		printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n");
+		return;
 	}
 	printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n");
 }


From gerrit at coreboot.org  Sat Jan  7 11:46:54 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 7 Jan 2012 11:46:54 +0100
Subject: [coreboot] Patch merged into coreboot/master: a96e8b2 Update geode
	GX2 tree to match LX.
References: <I5b99c531e44ea09990b9da0b97213fb7945f34ee+0@gerrit.coreboot.org>
Message-ID: <E1RjTna-00049p-1J@ra.coresystems.de>

the following patch was just integrated into master:
commit a96e8b2fffb58aa393ad0455f29df8737e2adbcf
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Fri Dec 30 23:00:11 2011 +0100

    Update geode GX2 tree to match LX.
    
    Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jan  7 11:46:49 2012, giving +2
See http://review.coreboot.org/512 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan  7 11:49:58 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 7 Jan 2012 11:49:58 +0100
Subject: [coreboot] Patch merged into coreboot/master: 9f1890a Cleanup
	access to vendor/part # info
References: <I074e3a0df7d25726cbd942538bfdc5a63dd17e12+0@gerrit.coreboot.org>
Message-ID: <E1RjTqY-0000Km-Dq@ra.coresystems.de>

the following patch was just integrated into master:
commit 9f1890a5a3ee76dee75f5c356166c0c6b513b7a3
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sat Dec 24 22:12:37 2011 -0700

    Cleanup access to vendor/part # info
    
    Instead of macros to access MAINBOARD record, use convenience functions.
    
    Store pointers to MAINBOARD and HEADER for use outside of CB code.
    
    Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jan  7 11:49:56 2012, giving +2
See http://review.coreboot.org/502 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan  7 11:50:18 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 7 Jan 2012 11:50:18 +0100
Subject: [coreboot] Patch merged into coreboot/master: 08f0b18 Eliminate
	magic numbers
References: <I2b7e0e4a8df6448d027cc61867382f161eb990d3+0@gerrit.coreboot.org>
Message-ID: <E1RjTqs-0000bg-QJ@ra.coresystems.de>

the following patch was just integrated into master:
commit 08f0b180fe0d7a29a9f4608d536dcc2ce268a7f1
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Dec 23 18:45:33 2011 -0700

    Eliminate magic numbers
    
    Use sizeof() on vendor and part# rather than explicit memory length.
    
    Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jan  7 11:50:15 2012, giving +2
See http://review.coreboot.org/504 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan  7 12:05:54 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 7 Jan 2012 12:05:54 +0100
Subject: [coreboot] Patch set updated for coreboot: 7c356b3 ACPI: mark empty
	get_cst_entries() weak
References: <I4bc0168aee110171faeaa081f217dfd1536bb821+0@gerrit.coreboot.org>
Message-ID: <I4bc0168aee110171faeaa081f217dfd1536bb821+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/496

-gerrit

commit 7c356b38ef762b2187f7f81e7c990d8409fadd14
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 23 10:29:09 2011 +0100

    ACPI: mark empty get_cst_entries() weak
    
    This function prevents the linker from choosing the right
    get_cst_entries(), preventing writing the _CST tables.
    
    Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/cpu/intel/speedstep/acpi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 8f32e4f..00c4ae9 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,7 +62,7 @@ static int get_fsb(void)
 	return 200;
 }
 
-int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+int __attribute__((weak)) get_cst_entries(struct cst_entry **entries __attribute__((unused)))
 {
 	return 0;
 }


From gerrit at coreboot.org  Sat Jan  7 15:01:59 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 7 Jan 2012 15:01:59 +0100
Subject: [coreboot] Patch set updated for coreboot: d864203 .gitignore
	ectool, inteltool, msrtool, nvramtool and superiotool
References: <I06e69d97ef3646f79104ec316ce932cc53894c92+0@gerrit.coreboot.org>
Message-ID: <I06e69d97ef3646f79104ec316ce932cc53894c92+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/485

-gerrit

commit d864203c152312aa8369377943312bb0fe232156
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:39:57 2011 +0100

    .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
    
    Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
    Signed-off-by: Peter Stuge <peter at stuge.se>
---
 .gitignore |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/.gitignore b/.gitignore
index a4bbacd..a08cb12 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,3 +35,12 @@ util/crossgcc/w32api-*/
 *.\#
 *.swp
 *.bin
+util/ectool/ectool
+util/inteltool/.dependencies
+util/inteltool/inteltool
+util/msrtool/Makefile
+util/msrtool/Makefile.deps
+util/msrtool/msrtool
+util/nvramtool/.dependencies
+util/nvramtool/nvramtool
+util/superiotool/superiotool


From gerrit at coreboot.org  Sat Jan  7 15:19:08 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 7 Jan 2012 15:19:08 +0100
Subject: [coreboot] New patch to review for coreboot: 80f420e Add subsystem
	callbacks for VT8237x and VT890 family of chipsets
References: <Id34615f0c229d276d72cdf984cf82ea8cc1a85bb+0@gerrit.coreboot.org>
Message-ID: <Id34615f0c229d276d72cdf984cf82ea8cc1a85bb+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/523

-gerrit

commit 80f420e5d626dc84c98196c2b9dd9d58cd3ad1d5
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Apr 22 20:48:21 2011 +0200

    Add subsystem callbacks for VT8237x and VT890 family of chipsets
    
    Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/southbridge/via/k8t890/ctrl.c      |    6 +++++-
 src/southbridge/via/k8t890/dram.c      |    8 ++++++--
 src/southbridge/via/k8t890/error.c     |    6 +++++-
 src/southbridge/via/k8t890/host.c      |    8 ++++++--
 src/southbridge/via/k8t890/host_ctrl.c |    8 ++++++--
 src/southbridge/via/vt8237r/lpc.c      |   14 ++++++++++++++
 src/southbridge/via/vt8237r/sata.c     |   15 +++++++++++++--
 src/southbridge/via/vt8237r/usb.c      |   16 ++++++++++++++--
 8 files changed, 69 insertions(+), 12 deletions(-)

diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index 6e5dbf7..1ff0b74 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -181,12 +181,16 @@ static void ctrl_init(struct device *dev)
 
 }
 
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
 static const struct device_operations ctrl_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= ctrl_init,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 294e387..7e450cc 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -153,12 +153,16 @@ static void dram_init_fb(struct device *dev)
 #endif
 }
 
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
 static const struct device_operations dram_ops_t = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= dram_enable,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations dram_ops_m = {
@@ -167,7 +171,7 @@ static const struct device_operations dram_ops_m = {
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= dram_enable_k8m890,
 	.init			= dram_init_fb,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
index f2cab10..1f6979a 100644
--- a/src/southbridge/via/k8t890/error.c
+++ b/src/southbridge/via/k8t890/error.c
@@ -41,12 +41,16 @@ static void error_enable(struct device *dev)
 	dump_south(dev);
 }
 
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
 static const struct device_operations error_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= error_enable,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c
index 700a637..54d79b4 100644
--- a/src/southbridge/via/k8t890/host.c
+++ b/src/southbridge/via/k8t890/host.c
@@ -95,12 +95,16 @@ static const struct device_operations host_ops_old = {
 	.ops_pci		= 0,
 };
 
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
 static const struct device_operations host_ops_t = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= host_enable,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations host_ops_m = {
@@ -109,7 +113,7 @@ static const struct device_operations host_ops_m = {
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= host_enable,
 	.init			= host_init,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_t800_old __pci_driver = {
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 5d46a00..c5d751e 100644
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -122,12 +122,16 @@ void set_cbmem_toc(struct cbmem_entry *toc) {
 		outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC);
 }
 
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
 static const struct device_operations host_ctrl_ops_t = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= host_ctrl_enable_k8t8xx,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations host_ctrl_ops_m = {
@@ -135,7 +139,7 @@ static const struct device_operations host_ctrl_ops_m = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.enable			= host_ctrl_enable_k8m8xx,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_t800 __pci_driver = {
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index cd1064f..d57d471 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -639,12 +639,24 @@ static void southbridge_init_common(struct device *dev)
 	init_keyboard(dev);
 }
 
+
+static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config16(dev, 0x70, vendor);
+	pci_write_config16(dev, 0x72, device);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = vt8237_set_subsystem,
+};
+
 static const struct device_operations vt8237r_lpc_ops_s = {
 	.read_resources		= vt8237r_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= vt8237s_init,
 	.scan_bus		= scan_static_bus,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations vt8237r_lpc_ops_r = {
@@ -653,6 +665,7 @@ static const struct device_operations vt8237r_lpc_ops_r = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= vt8237r_init,
 	.scan_bus		= scan_static_bus,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations vt8237r_lpc_ops_a = {
@@ -661,6 +674,7 @@ static const struct device_operations vt8237r_lpc_ops_a = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= vt8237a_init,
 	.scan_bus		= scan_static_bus,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver lpc_driver_r __pci_driver = {
diff --git a/src/southbridge/via/vt8237r/sata.c b/src/southbridge/via/vt8237r/sata.c
index 777d605..2f07e69 100644
--- a/src/southbridge/via/vt8237r/sata.c
+++ b/src/southbridge/via/vt8237r/sata.c
@@ -95,13 +95,24 @@ static void sata_ii_init(struct device *dev)
 	}
 }
 
+
+static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config16(dev, 0xd4, vendor);
+	pci_write_config16(dev, 0xd6, device);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = vt8237_set_subsystem,
+};
+
 static const struct device_operations sata_i_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= sata_i_init,
 	.enable			= 0,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct device_operations sata_ii_ops = {
@@ -110,7 +121,7 @@ static const struct device_operations sata_ii_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= sata_ii_init,
 	.enable			= 0,
-	.ops_pci		= 0,
+	.ops_pci		= &lops_pci,
 };
 
 static const struct pci_driver northbridge_driver_ii __pci_driver = {
diff --git a/src/southbridge/via/vt8237r/usb.c b/src/southbridge/via/vt8237r/usb.c
index 2bdcf9d..ac27f43 100644
--- a/src/southbridge/via/vt8237r/usb.c
+++ b/src/southbridge/via/vt8237r/usb.c
@@ -158,13 +158,25 @@ static void vt8237_usb_ii_read_resources(struct device *dev)
 	return;
 }
 
+static void vt8237_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) | 0x10);
+	pci_write_config16(dev, 0x2c, vendor);
+	pci_write_config16(dev, 0x2e, device);
+	pci_write_config32(dev, 0x42, pci_read_config32(dev, 0x42) & ~0x10);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = vt8237_set_subsystem,
+};
+
 static const struct device_operations usb_i_ops = {
 	.read_resources		= vt8237_usb_i_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init				= usb_i_init,
 	.enable				= 0,
-	.ops_pci			= 0,
+	.ops_pci			= &lops_pci,
 };
 
 static const struct device_operations usb_ii_ops = {
@@ -173,7 +185,7 @@ static const struct device_operations usb_ii_ops = {
 	.enable_resources	= pci_dev_enable_resources,
 	.init				= usb_ii_init,
 	.enable				= 0,
-	.ops_pci			= 0,
+	.ops_pci			= &lops_pci,
 };
 
 static const struct pci_driver vt8237r_driver_usbii __pci_driver = {


From gerrit at coreboot.org  Sat Jan  7 15:19:47 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 7 Jan 2012 15:19:47 +0100
Subject: [coreboot] Patch merged into coreboot/master: d864203 .gitignore
	ectool, inteltool, msrtool, nvramtool and superiotool
References: <I06e69d97ef3646f79104ec316ce932cc53894c92+0@gerrit.coreboot.org>
Message-ID: <E1RjX7b-0005sw-5R@ra.coresystems.de>

the following patch was just integrated into master:
commit d864203c152312aa8369377943312bb0fe232156
Author: Peter Stuge <peter at stuge.se>
Date:   Wed Dec 14 07:39:57 2011 +0100

    .gitignore ectool, inteltool, msrtool, nvramtool and superiotool
    
    Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
    Signed-off-by: Peter Stuge <peter at stuge.se>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jan  7 15:19:30 2012, giving +2
See http://review.coreboot.org/485 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan  7 17:18:18 2012
From: gerrit at coreboot.org (Jonathan A. Kollasch (jakllsch@kollasch.net))
Date: Sat, 7 Jan 2012 17:18:18 +0100
Subject: [coreboot] New patch to review for coreboot: 396b232 rs780: correct
	comment in switching_gpp_configurations()
References: <I6417a92523eea7307d080669fbc4e16ee28c8a6c+0@gerrit.coreboot.org>
Message-ID: <I6417a92523eea7307d080669fbc4e16ee28c8a6c+1@gerrit.coreboot.org>

Jonathan A. Kollasch (jakllsch at kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/524

-gerrit

commit 396b2325b1bf5d5986a6377052f00b9cb7d2ecec
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Sat Jan 7 10:17:50 2012 -0600

    rs780: correct comment in switching_gpp_configurations()
    
    Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>
---
 src/southbridge/amd/rs780/pcie.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index be80ed3..527a710 100644
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -191,7 +191,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev)
 	reg = nbmisc_read_index(nb_dev, 0x22);
 	reg |= 1 << 14;
 	nbmisc_write_index(nb_dev, 0x22, reg);
-	/* 5.6.2.2. sets desired GPPSB configurations, bit4-7 */
+	/* 5.6.2.2. sets desired GPP configurations, bit7-10 */
 	reg = nbmisc_read_index(nb_dev, 0x2D);
 	reg &= ~(0xF << 7);		/* clean */
 	reg |= cfg->gpp_configuration << 7;


From gerrit at coreboot.org  Sun Jan  8 15:44:51 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 8 Jan 2012 15:44:51 +0100
Subject: [coreboot] New patch to review for coreboot: 2ae66cb inteltool: Add
	support for dumping AMB registers
References: <I98615725afdb315caa67b2226224e3eb2a0e4393+0@gerrit.coreboot.org>
Message-ID: <I98615725afdb315caa67b2226224e3eb2a0e4393+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/525

-gerrit

commit 2ae66cb092deb642a0d22ed80f73d3411a51c696
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jan 8 15:27:18 2012 +0100

    inteltool: Add support for dumping AMB registers
    
    Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 util/inteltool/Makefile    |    2 +-
 util/inteltool/amb.c       |  469 ++++++++++++++++++++++++++++++++++++++++++++
 util/inteltool/inteltool.c |   16 ++-
 util/inteltool/inteltool.h |    6 +
 4 files changed, 490 insertions(+), 3 deletions(-)

diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile
index db7fca0..6a01173 100644
--- a/util/inteltool/Makefile
+++ b/util/inteltool/Makefile
@@ -27,7 +27,7 @@ PREFIX  = /usr/local
 CFLAGS  = -O2 -g -Wall -W
 LDFLAGS = -lpci -lz
 
-OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o
+OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o
 
 OS_ARCH	= $(shell uname)
 ifeq ($(OS_ARCH), Darwin)
diff --git a/util/inteltool/amb.c b/util/inteltool/amb.c
new file mode 100644
index 0000000..a3ee01d
--- /dev/null
+++ b/util/inteltool/amb.c
@@ -0,0 +1,469 @@
+/*
+ * inteltool - dump all registers on an Intel CPU + chipset based system.
+ *
+ * Copyright (C) 2012 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "inteltool.h"
+
+#define AMB_CONFIG_SPACE_SIZE 0x20000
+
+#define AMB_ADDR(base, fn, reg) (base | ((fn & 7) << 8) | ((reg & 0xff)))
+
+static uint32_t amb_read_config32(volatile void *base, int fn, int reg)
+{
+	return *(uint32_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg32(volatile void *base, int fn, int reg,
+			   const char *name, int printzero)
+{
+	uint32_t val = amb_read_config32(base, fn, reg);
+	if (!val && !printzero)
+		return;
+	printf("%d:%2.2x %-16.16s: 0x%08x\n", fn, reg, name, val);
+}
+
+static uint16_t amb_read_config16(volatile void *base, int fn, int reg)
+{
+	return *(uint16_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg16(volatile void *base, int fn, int reg,
+			   const char *name, int printzero)
+{
+	uint16_t val = amb_read_config16(base, fn, reg);
+	if (!val && !printzero)
+		return;
+	printf("%d:%2.2x %-16.16s: 0x%04x\n", fn, reg, name, val);
+
+}
+
+static uint8_t amb_read_config8(volatile void *base, int fn, int reg)
+{
+	return *(uint8_t *)(AMB_ADDR((uint64_t)base, fn, reg));
+}
+
+static void amb_printreg8(volatile void *base, int fn, int reg,
+			  const char *name, int printzero)
+{
+	uint8_t val = amb_read_config8(base, fn, reg);
+	if (!val && !printzero)
+		return;
+	printf("%d:%2.2x %-16.16s: 0x%02x\n", fn, reg, name, val);
+
+}
+
+static void amb_printreg24(volatile void *base, int fn, int reg,
+			   const char *name, int printzero)
+{
+	uint32_t val;
+
+	if (reg & 1) {
+		val = amb_read_config8(base, fn, reg) |
+			(amb_read_config16(base, fn, reg + 1) << 8);
+	} else {
+		val = amb_read_config16(base, fn, reg) |
+			(amb_read_config8(base, fn, reg + 2) << 16);
+	}
+
+	if (!val && !printzero)
+		return;
+
+	printf("%d:%2.2x %-16.16s: 0x%06x\n", fn, reg, name, val);
+}
+
+
+struct amb_register {
+	int fn;
+	int offset;
+	const char *name;
+	void (*printfunc)(volatile void *, int, int, const char *, int);
+	int width;
+} amb_registers[] = {
+	{ 0, 0x00, "VID", NULL, 2 },
+	{ 0, 0x02, "DID", NULL, 2 },
+	{ 0, 0x08, "RID", NULL, 1 },
+	{ 0, 0x09, "CCR", NULL, 3 },
+	{ 0, 0x0e, "HDR", NULL, 1 },
+	{ 1, 0x40, "FBDS0", NULL, 1 },
+	{ 1, 0x41, "FBDS1", NULL, 1 },
+	{ 1, 0x42, "FBDS2", NULL, 1 },
+	{ 1, 0x43, "FBDS3", NULL, 1 },
+	{ 1, 0x50, "FBDSBCFGCUR", NULL, 1 },
+	{ 1, 0x51, "FBDNBCFGCUR", NULL, 1 },
+	{ 1, 0x52, "LINKPARCUR", NULL, 2 },
+	{ 1, 0x54, "FBDSBCFGNXT", NULL, 1 },
+	{ 1, 0x55, "FBDNBCFGNXT", NULL, 1 },
+	{ 1, 0x56, "LINKPARNXT", NULL, 2 },
+	{ 1, 0x5a, "SBRXMAR", NULL, 1 },
+	{ 1, 0x5b, "NBRXMAR", NULL, 1 },
+	{ 1, 0x5c, "MODES", NULL, 1 },
+	{ 1, 0x60, "FEATURES", NULL, 2 },
+	{ 1, 0x64, "FBDLIS", NULL, 3 },
+	{ 1, 0x68, "FBDLOCKTO", NULL, 2 },
+	{ 1, 0x6c, "FBDHAC", NULL, 1 },
+	{ 1, 0x6e, "FBDLS", NULL, 1 },
+	{ 1, 0x70, "RECALDUR", NULL, 1 },
+	{ 1, 0x74, "LOSDUR", NULL, 1 },
+	{ 1, 0x78, "SYNCTRAININT", NULL, 1 },
+	{ 1, 0x7c, "SBCALSTATUS", NULL, 2 },
+	{ 1, 0x7e, "NBCALSTATUS", NULL, 2 },
+	{ 1, 0x88, "CBC", NULL, 1 },
+	{ 1, 0x8c, "EMASK", NULL, 1 },
+	{ 1, 0x90, "FERR", NULL, 1 },
+	{ 1, 0x94, "NERR", NULL, 1 },
+	{ 1, 0x98, "RECCFG", NULL, 2 },
+	{ 1, 0x9c, "RECFBD0", NULL, 2 },
+	{ 1, 0x9e, "RECFBD1", NULL, 2 },
+	{ 1, 0xa0, "RECFBD2", NULL, 2 },
+	{ 1, 0xa2, "RECFBD3", NULL, 2 },
+	{ 1, 0xa4, "RECFBD4", NULL, 2 },
+	{ 1, 0xa6, "RECFBD5", NULL, 2 },
+	{ 1, 0xa8, "RECFBD6", NULL, 2 },
+	{ 1, 0xaa, "RECFBD7", NULL, 2 },
+	{ 1, 0xac, "RECFBD8", NULL, 2 },
+	{ 1, 0xae, "RECFBD9", NULL, 2 },
+	{ 1, 0xb0, "PERSBYTE0NXT", NULL, 1 },
+	{ 1, 0xb1, "PERSBYTE1NXT", NULL, 1 },
+	{ 1, 0xb2, "PERSBYTE2NXT", NULL, 1 },
+	{ 1, 0xb3, "PERSBYTE3NXT", NULL, 1 },
+	{ 1, 0xb4, "PERSBYTE4NXT", NULL, 1 },
+	{ 1, 0xb5, "PERSBYTE5NXT", NULL, 1 },
+	{ 1, 0xb6, "PERSBYTE6NXT", NULL, 1 },
+	{ 1, 0xb7, "PERSBYTE7NXT", NULL, 1 },
+	{ 1, 0xb8, "PERSBYTE8NXT", NULL, 1 },
+	{ 1, 0xb9, "PERSBYTE9NXT", NULL, 1 },
+	{ 1, 0xba, "PERSBYTE10NXT", NULL, 1 },
+	{ 1, 0xbb, "PERSBYTE11NXT", NULL, 1 },
+	{ 1, 0xbc, "PERSBYTE12NXT", NULL, 1 },
+	{ 1, 0xbd, "PERSBYTE13NXT", NULL, 1 },
+	{ 1, 0xc0, "PERSBYTE0CUR", NULL, 1 },
+	{ 1, 0xc1, "PERSBYTE1CUR", NULL, 1 },
+	{ 1, 0xc2, "PERSBYTE2CUR", NULL, 1 },
+	{ 1, 0xc3, "PERSBYTE3CUR", NULL, 1 },
+	{ 1, 0xc4, "PERSBYTE4CUR", NULL, 1 },
+	{ 1, 0xc5, "PERSBYTE5CUR", NULL, 1 },
+	{ 1, 0xc6, "PERSBYTE6CUR", NULL, 1 },
+	{ 1, 0xc7, "PERSBYTE7CUR", NULL, 1 },
+	{ 1, 0xc8, "PERSBYTE8CUR", NULL, 1 },
+	{ 1, 0xc9, "PERSBYTE9CUR", NULL, 1 },
+	{ 1, 0xca, "PERSBYTE10CUR", NULL, 1 },
+	{ 1, 0xcb, "PERSBYTE11CUR", NULL, 1 },
+	{ 1, 0xcc, "PERSBYTE12CUR", NULL, 1 },
+	{ 1, 0xcd, "PERSBYTE13CUR", NULL, 1 },
+	{ 1, 0xe8, "CMD2DATANXT", NULL, 1 },
+	{ 1, 0xe9, "CMD2DATACUR", NULL, 1 },
+	{ 1, 0xea, "C2DINCRNXT", NULL, 1 },
+	{ 1, 0xeb, "C2DINCRCUR", NULL, 1 },
+	{ 1, 0xec, "C2DDECRNXT", NULL, 1 },
+	{ 1, 0xed, "C2DDECRCUR", NULL, 1 },
+	{ 2, 0x40, "SBDRVCFG", NULL, 1 },
+	{ 2, 0x41, "NBDRVCFG", NULL, 1 },
+	{ 2, 0x42, "FBDPDCFG", NULL, 1 },
+	{ 2, 0x44, "RTERMCFG", NULL, 3 },
+	{ 2, 0x47, "IDTCTRLCFG", NULL, 1 },
+	{ 2, 0x48, "FBDBUFCFG", NULL, 1 },
+	{ 2, 0x50, "SBRQOFFS0", NULL, 1 },
+	{ 2, 0x51, "SBRQOFFS1", NULL, 1 },
+	{ 2, 0x52, "SBRQOFFS2", NULL, 1 },
+	{ 2, 0x53, "SBRQOFFS3", NULL, 1 },
+	{ 2, 0x54, "SBRQOFFS4", NULL, 1 },
+	{ 2, 0x55, "SBRQOFFS5", NULL, 1 },
+	{ 2, 0x56, "SBRQOFFS6", NULL, 1 },
+	{ 2, 0x57, "SBRQOFFS7", NULL, 1 },
+	{ 2, 0x58, "SBRQOFFS8", NULL, 1 },
+	{ 2, 0x59, "SBRQOFFS9", NULL, 1 },
+
+	{ 2, 0x60, "NBRQOFFS0", NULL, 1 },
+	{ 2, 0x61, "NBRQOFFS1", NULL, 1 },
+	{ 2, 0x62, "NBRQOFFS2", NULL, 1 },
+	{ 2, 0x63, "NBRQOFFS3", NULL, 1 },
+	{ 2, 0x64, "NBRQOFFS4", NULL, 1 },
+	{ 2, 0x65, "NBRQOFFS5", NULL, 1 },
+	{ 2, 0x66, "NBRQOFFS6", NULL, 1 },
+	{ 2, 0x67, "NBRQOFFS7", NULL, 1 },
+	{ 2, 0x68, "NBRQOFFS8", NULL, 1 },
+	{ 2, 0x69, "NBRQOFFS9", NULL, 1 },
+	{ 2, 0x6a, "NBRQOFFS10", NULL, 1 },
+	{ 2, 0x6b, "NBRQOFFS11", NULL, 1 },
+	{ 2, 0x6c, "NBRQOFFS12", NULL, 1 },
+	{ 2, 0x6d, "NBRQOFFS13", NULL, 1 },
+	{ 2, 0x90, "TESTCFG", NULL, 1 },
+	{ 2, 0x94, "SBTXENCFG", NULL, 2 },
+	{ 2, 0x96, "NBTXENCFG", NULL, 2 },
+	{ 2, 0x98, "IDLEDETCFG", NULL, 2 },
+	{ 2, 0xa4, "SBRXSTATUS", NULL, 4 },
+	{ 2, 0xa8, "SBRXSTATUS", NULL, 1 },
+	{ 3, 0x3c, "MBIDT", NULL, 1 },
+	{ 3, 0x40, "MBCSR", NULL, 4 },
+	{ 3, 0x44, "MBADDR", NULL, 4 },
+	{ 3, 0x40, "MBDATA0", NULL, 4 },
+	{ 3, 0x41, "MBDATA1", NULL, 4 },
+	{ 3, 0x42, "MBDATA2", NULL, 4 },
+	{ 3, 0x43, "MBDATA3", NULL, 4 },
+	{ 3, 0x44, "MBDATA4", NULL, 4 },
+	{ 3, 0x45, "MBDATA5", NULL, 4 },
+	{ 3, 0x46, "MBDATA6", NULL, 4 },
+	{ 3, 0x47, "MBDATA7", NULL, 4 },
+	{ 3, 0x48, "MBDATA8", NULL, 4 },
+	{ 3, 0x49, "MBDATA9", NULL, 4 },
+	{ 3, 0x70, "DAREFTC", NULL, 4 },
+	{ 3, 0x74, "DSREFTC", NULL, 3 },
+	{ 3, 0x77, "MTR", NULL, 1 },
+	{ 3, 0x78, "DRT", NULL, 4 },
+	{ 3, 0x7c, "DRC", NULL, 4 },
+	{ 3, 0x80, "TEMPLO", NULL, 1 },
+	{ 3, 0x81, "TEMPMID", NULL, 1 },
+	{ 3, 0x82, "TEMPHI", NULL, 1 },
+	{ 3, 0x83, "UPDATED", NULL, 1 },
+	{ 3, 0x84, "TEMPSTAT", NULL, 1 },
+	{ 3, 0x85, "TEMP", NULL, 1 },
+	{ 3, 0x86, "TEMPOFFSET", NULL, 1 },
+	{ 3, 0x9c, "MB_START_ADDR", NULL, 4 },
+	{ 3, 0xa0, "MB_END_ADDR", NULL, 4 },
+	{ 3, 0xa4, "MBLFSRSEED", NULL, 4 },
+	{ 3, 0xa8, "MBFADDRPTR", NULL, 4 },
+	{ 3, 0xb0, "MB_ERR_DATA00", NULL, 4 },
+	{ 3, 0xb4, "MB_ERR_DATA01", NULL, 4 },
+	{ 3, 0xb8, "MB_ERR_DATA02", NULL, 4 },
+	{ 3, 0xbc, "MB_ERR_DATA03", NULL, 4 },
+	{ 3, 0xc0, "MB_ERR_DATA04", NULL, 2 },
+	{ 3, 0xc4, "MB_ERR_DATA10", NULL, 4 },
+	{ 3, 0xc8, "MB_ERR_DATA11", NULL, 4 },
+	{ 3, 0xcc, "MB_ERR_DATA12", NULL, 4 },
+	{ 3, 0xd0, "MB_ERR_DATA13", NULL, 4 },
+	{ 3, 0xd4, "MB_ERR_DATA14", NULL, 2 },
+
+	{ 4, 0x40, "DCALCSR", NULL, 4 },
+	{ 4, 0x44, "DCALADDR", NULL, 4 },
+	{ 4, 0x98, "DSRETC", NULL, 4 },
+	{ 4, 0xa4, "S3RESTORE0", NULL, 4 },
+	{ 4, 0xa8, "S3RESTORE1", NULL, 4 },
+	{ 4, 0xac, "S3RESTORE2", NULL, 4 },
+	{ 4, 0xb0, "S3RESTORE3", NULL, 4 },
+	{ 4, 0xb4, "S3RESTORE4", NULL, 4 },
+	{ 4, 0xb8, "S3RESTORE5", NULL, 4 },
+	{ 4, 0xbc, "S3RESTORE6", NULL, 4 },
+	{ 4, 0xc0, "S3RESTORE7", NULL, 4 },
+	{ 4, 0xc4, "S3RESTORE8", NULL, 4 },
+	{ 4, 0xc8, "S3RESTORE9", NULL, 4 },
+	{ 4, 0xcc, "S3RESTORE10", NULL, 4 },
+	{ 4, 0xe8, "FIVESREG", NULL, 4 },
+	{ 4, 0xea, "AAAAREG", NULL, 4 },
+
+	{ 5, 0x3c, "TRANSCFG", NULL, 4 },
+	{ 5, 0x40, "TRANDERR0", NULL, 2 },
+	{ 5, 0x42, "TRANDERR1", NULL, 2 },
+	{ 5, 0x44, "TRANDERR2", NULL, 2 },
+	{ 5, 0x46, "TRANDERR3", NULL, 2 },
+	{ 5, 0x48, "TRANDERR4", NULL, 2 },
+	{ 5, 0x4a, "TRANDERR5", NULL, 2 },
+	{ 5, 0x4c, "TRANDERR6", NULL, 2 },
+	{ 5, 0x4e, "TRANDERR7", NULL, 2 },
+	{ 5, 0x50, "TRANDERR8", NULL, 2 },
+	{ 5, 0x80, "TRANSCTRL", NULL, 1 },
+	{ 5, 0xbc, "SBMATCHU", NULL, 3 },
+	{ 5, 0xc0, "SBMATCHL0", NULL, 4 },
+	{ 5, 0xcc, "SBMASKU", NULL, 3 },
+	{ 5, 0xd0, "SBMASKL0", NULL, 4 },
+	{ 5, 0xe0, "EVENTSEL0", NULL, 3 },
+	{ 5, 0xfc, "EICNTL", NULL, 1 },
+	{ 5, 0xfe, "STUCKL", NULL, 1 },
+
+	{ 6, 0x50, "NBRXSTATUS", NULL, 4 },
+	{ 6, 0x7c, "SPAD0", NULL, 4 },
+	{ 6, 0x80, "SBFIBPORTCTL", NULL, 4 },
+	{ 6, 0x84, "SBFIBPGCTL", NULL, 4 },
+	{ 6, 0x88, "SBFIBPATTBUF1", NULL, 3 },
+	{ 6, 0x8c, "SBFIBTXMSK", NULL, 2 },
+	{ 6, 0x90, "SBFIBRXMSK", NULL, 2 },
+	{ 6, 0x94, "SBFIBTXSHFT", NULL, 2 },
+	{ 6, 0x98, "SBFIBRXSHFT", NULL, 2 },
+	{ 6, 0x9c, "SBFIBRXLNERR", NULL, 2 },
+	{ 6, 0xa0, "SBFIBPATTBUF2", NULL, 3 },
+	{ 6, 0xa4, "SBFIBPATT2EN", NULL, 2 },
+	{ 6, 0xb0, "SBFIBINIT", NULL, 4 },
+	{ 6, 0xb4, "SBIBISTMISC", NULL, 3 },
+	{ 6, 0xc0, "NBFIBPORTCTL", NULL, 4 },
+	{ 6, 0xc4, "NBFIBPGCTL", NULL, 4 },
+	{ 6, 0xc8, "NBFIBPATTBUF1", NULL, 3 },
+	{ 6, 0xcc, "NBFIBTXMSK", NULL, 2 },
+	{ 6, 0xd0, "NBFIBRXMSK", NULL, 2 },
+	{ 6, 0xd4, "NBFIBTXSHFT", NULL, 2 },
+	{ 6, 0xd8, "NBFIBRXSHFT", NULL, 2 },
+	{ 6, 0xdc, "NBFIBRXLNERR", NULL, 2 },
+	{ 6, 0xe0, "NBFIBPATTBUF2", NULL, 3 },
+	{ 6, 0xe4, "NBFIBPATT2EN", NULL, 2 },
+	{ 6, 0xf0, "NBFIBINIT", NULL, 4 },
+	{ 6, 0xf4, "NBIBISTMISC", NULL, 3 },
+
+	{ 7, 0x40, "ODRV_ADJ_ADDR_A", NULL, 3 },
+	{ 7, 0x43, "ODRV_ADJ_CAS_A", NULL, 3 },
+	{ 7, 0x46, "ODRV_ADJ_CKE_A", NULL, 3 },
+	{ 7, 0x49, "ODRV_ADJ_ODT_A", NULL, 3 },
+	{ 7, 0x4c, "ODRV_ADJ_ADDR_B", NULL, 3 },
+	{ 7, 0x4f, "ODRV_ADJ_CAS_B", NULL, 3 },
+	{ 7, 0x52, "ODRV_ADJ_CKE_B", NULL, 3 },
+	{ 7, 0x55, "ODRV_ADJ_ODT_B", NULL, 3 },
+	{ 7, 0x58, "ODRV_ADJ_CLK0", NULL, 3 },
+	{ 7, 0x5b, "ODRV_ADJ_CLK1", NULL, 3 },
+	{ 7, 0x5e, "ODRV_ADJ_CLK2", NULL, 3 },
+	{ 7, 0x61, "ODRV_ADJ_CLK3", NULL, 3 },
+	{ 7, 0x64, "ODRV_ADJ_DQ_DQS", NULL, 3 },
+	{ 7, 0x67, "DDR_ODTCTL", NULL, 1 },
+	{ 7, 0x69, "DDR_ZCAL", NULL, 2 },
+	{ 7, 0x6c, "DDR_ZCTL", NULL, 4 },
+	{ 7, 0x78, "VHOSTCNTL", NULL, 1 },
+	{ 7, 0x79, "DQSDLY_SMBUSCTL", NULL, 1 },
+	{ 7, 0x7c, "SPAD1", NULL, 4 },
+	{ 7, 0x80, "CTL_ADDR_A", NULL, 1 },
+	{ 7, 0x81, "CTL_CAS_A", NULL, 1 },
+	{ 7, 0x82, "CTL_CKE_A", NULL, 1 },
+	{ 7, 0x83, "CTL_ODT_A", NULL, 1 },
+	{ 7, 0x84, "CTL_ADDR_B", NULL, 1 },
+	{ 7, 0x85, "CTL_CAS_B", NULL, 1 },
+	{ 7, 0x86, "CTL_CKE_B", NULL, 1 },
+	{ 7, 0x87, "CTL_ODT_B", NULL, 1 },
+	{ 7, 0x88, "CTL_CLK0", NULL, 1 },
+	{ 7, 0x89, "CTL_CLK1", NULL, 1 },
+	{ 7, 0x8a, "CTL_CLK2", NULL, 1 },
+	{ 7, 0x8b, "CTL_CLK3", NULL, 1 },
+	{ 7, 0x8c, "CTL_DQ", NULL, 1 },
+	{ 7, 0x8d, "CTL_DQS", NULL, 1 },
+	{ 0, 0x00, NULL, NULL, 0 },
+};
+
+static void dump_amb(volatile void *ambconfig, int branch, int channel, int amb)
+{
+	struct amb_register *reg;
+	static int lastreg, lastfn;
+	int bytes;
+
+	volatile void *base = ambconfig + \
+		((branch << 16) | (channel << 15) | (amb << 11));
+
+	if ((amb_read_config32(base, 0, 0) == 0xffffffff) |
+	    (amb_read_config32(base, 0, 0) == 0x00000000))
+		return;
+
+	printf("AMB %d, branch %d, channel %d register dump:\n"
+	       "============================================\n",
+	       amb, branch, channel);
+
+	for(reg = amb_registers; reg->name; reg++) {
+		if (reg->fn == lastfn && reg->offset > 0 && reg->offset - lastreg) {
+			bytes = reg->offset - lastreg;
+
+			do {
+				if (!(lastreg & 3) && bytes >= 4) {
+					amb_printreg32(base, reg->fn, lastreg, "RESERVED", 0);
+					bytes -= 4;
+					lastreg += 4;
+				} else if (!(lastreg & 1) && bytes >= 2) {
+					amb_printreg16(base, reg->fn, lastreg, "RESERVED", 0);
+					bytes -= 2;
+					lastreg += 2;
+				} else {
+					amb_printreg8(base, reg->fn, lastreg, "RESERVED", 0);
+					bytes -= 1;
+					lastreg += 1;
+				}
+			} while(bytes > 0);
+		}
+
+		switch(reg->width) {
+		case 1:
+			amb_printreg8(base, reg->fn, reg->offset, reg->name, 1);
+			break;
+		case 2:
+			amb_printreg16(base, reg->fn, reg->offset, reg->name, 1);
+			break;
+
+		case 3:
+			amb_printreg24(base, reg->fn, reg->offset, reg->name, 1);
+			break;
+
+		case 4:
+			amb_printreg32(base, reg->fn, reg->offset, reg->name, 1);
+			break;
+
+		default:
+			break;
+		}
+
+		if (reg->printfunc)
+			reg->printfunc(base, reg->fn, reg->offset, reg->name, 1);
+		lastreg = reg->offset + reg->width;
+		lastfn = reg->fn;
+	}
+	printf("\n\n");
+}
+
+int print_ambs(struct pci_dev *dev, struct pci_access *pacc)
+{
+	struct pci_dev *dev16;
+	int branch, channel, amb;
+	int max_branch, max_channel, max_amb;
+	volatile void *ambconfig;
+	uint64_t ambconfig_phys;
+
+	printf("\n============= AMBs ============\n\n");
+
+	switch (dev->device_id) {
+	case PCI_DEVICE_ID_INTEL_I5000P:
+	case PCI_DEVICE_ID_INTEL_I5000X:
+	case PCI_DEVICE_ID_INTEL_I5000Z:
+
+		max_branch = 2;
+
+		if (!(dev16 = pci_get_dev(pacc, 0, 0, 0x10, 0))) {
+			perror("Error: no device 0:16.0\n");
+			return 1;
+		}
+
+		ambconfig_phys = ((u64)pci_read_long(dev16, 0x4c) << 32) |
+			pci_read_long(dev16, 0x48);
+
+		max_channel = pci_read_byte(dev16, 0x56)/max_branch;
+		max_amb = pci_read_byte(dev16, 0x57);
+		break;
+
+	default:
+		fprintf(stderr, "Error: Dumping AMBs on this MCH is not (yet) supported.\n");
+		return 1;
+	}
+
+	if (!(ambconfig = map_physical(ambconfig_phys, AMB_CONFIG_SPACE_SIZE))) {
+		fprintf(stderr, "Error mapping AMB config space\n");
+		return 1;
+	}
+
+	for(branch = 0; branch < max_branch; branch++) {
+		for(channel = 0; channel < max_channel; channel++) {
+			for(amb = 0; amb < max_amb; amb++) {
+				dump_amb(ambconfig, branch, channel, amb);
+			}
+		}
+	}
+	unmap_physical((void *)ambconfig, AMB_CONFIG_SPACE_SIZE);
+	return 0;
+}
+
+
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 488d9f5..6b99605 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -83,6 +83,9 @@ static const struct {
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
 };
 
 #ifndef __DARWIN__
@@ -139,6 +142,7 @@ void print_usage(const char *name)
 	     "   -d | --dmibar:                    dump northbridge DMIBAR registers\n"
 	     "   -P | --pciexpress:                dump northbridge PCIEXBAR registers\n\n"
 	     "   -M | --msrs:                      dump CPU MSRs\n"
+	     "   -A | --ambs:                      dump AMB registers\n"
 	     "   -a | --all:                       dump all known registers\n"
 	     "\n");
 	exit(1);
@@ -155,7 +159,7 @@ int main(int argc, char *argv[])
 
 	int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
 	int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
-	int dump_pciexbar = 0, dump_coremsrs = 0;
+	int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0;
 
 	static struct option long_options[] = {
 		{"version", 0, 0, 'v'},
@@ -168,11 +172,12 @@ int main(int argc, char *argv[])
 		{"dmibar", 0, 0, 'd'},
 		{"pciexpress", 0, 0, 'P'},
 		{"msrs", 0, 0, 'M'},
+		{"ambs", 0, 0, 'A'},
 		{"all", 0, 0, 'a'},
 		{0, 0, 0, 0}
 	};
 
-	while ((opt = getopt_long(argc, argv, "vh?grpmedPMa",
+	while ((opt = getopt_long(argc, argv, "vh?grpmedPMaA",
                                   long_options, &option_index)) != EOF) {
 		switch (opt) {
 		case 'v':
@@ -212,6 +217,10 @@ int main(int argc, char *argv[])
 			dump_dmibar = 1;
 			dump_pciexbar = 1;
 			dump_coremsrs = 1;
+			dump_ambs = 1;
+			break;
+		case 'A':
+			dump_ambs = 1;
 			break;
 		case 'h':
 		case '?':
@@ -356,6 +365,9 @@ int main(int argc, char *argv[])
 		printf("\n\n");
 	}
 
+	if (dump_ambs) {
+		print_ambs(nb, pacc);
+	}
 	/* Clean up */
 	pci_free_dev(nb);
 	// pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 1bfb3d1..c3fa365 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -85,6 +85,11 @@
 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO		0x8100
 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX		0xa000
 #define PCI_DEVICE_ID_INTEL_I63XX		0x2670
+
+#define PCI_DEVICE_ID_INTEL_I5000X		0x25d0
+#define PCI_DEVICE_ID_INTEL_I5000Z		0x25d4
+#define PCI_DEVICE_ID_INTEL_I5000P		0x25d8
+
 /* untested, but almost identical to D-series */
 #define PCI_DEVICE_ID_INTEL_ATOM_NXXX		0xa010
 
@@ -125,3 +130,4 @@ int print_gpios(struct pci_dev *sb);
 int print_epbar(struct pci_dev *nb);
 int print_dmibar(struct pci_dev *nb);
 int print_pciexbar(struct pci_dev *nb);
+int print_ambs(struct pci_dev *nb, struct pci_access *pacc);


From gerrit at coreboot.org  Sun Jan  8 20:41:10 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 8 Jan 2012 20:41:10 +0100
Subject: [coreboot] Patch merged into coreboot/master: 2ae66cb inteltool:
	Add support for dumping AMB registers
References: <I98615725afdb315caa67b2226224e3eb2a0e4393+0@gerrit.coreboot.org>
Message-ID: <E1RjycA-0001Md-H8@ra.coresystems.de>

the following patch was just integrated into master:
commit 2ae66cb092deb642a0d22ed80f73d3411a51c696
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jan 8 15:27:18 2012 +0100

    inteltool: Add support for dumping AMB registers
    
    Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Sun Jan  8 16:08:24 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sun Jan  8 20:41:08 2012, giving +2
See http://review.coreboot.org/525 for details.

-gerrit


From gerrit at coreboot.org  Sun Jan  8 20:42:10 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 8 Jan 2012 20:42:10 +0100
Subject: [coreboot] Patch merged into coreboot/master: 9faab44 adm1027: add
	return statement
References: <I53741f1136b396e9493ce959b54efc00c9b09764+0@gerrit.coreboot.org>
Message-ID: <E1Rjyd8-0001Zv-36@ra.coresystems.de>

the following patch was just integrated into master:
commit 9faab4477efb6d0102c9854dcc1ecd3f1cac6421
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 7 16:04:46 2012 +0530

    adm1027: add return statement
    
    Adds a missing return statment which will stop misleading the users
    
    Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jan  7 18:45:32 2012, giving +1
Build-Tested: build bot (Jenkins) at Sat Jan  7 12:31:23 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sun Jan  8 20:42:07 2012, giving +2
See http://review.coreboot.org/522 for details.

-gerrit


From gerrit at coreboot.org  Sun Jan  8 20:43:04 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sun, 8 Jan 2012 20:43:04 +0100
Subject: [coreboot] Patch merged into coreboot/master: 396b232 rs780:
	correct comment in switching_gpp_configurations()
References: <I6417a92523eea7307d080669fbc4e16ee28c8a6c+0@gerrit.coreboot.org>
Message-ID: <E1Rjye0-0001m9-9s@ra.coresystems.de>

the following patch was just integrated into master:
commit 396b2325b1bf5d5986a6377052f00b9cb7d2ecec
Author: Jonathan A. Kollasch <jakllsch at kollasch.net>
Date:   Sat Jan 7 10:17:50 2012 -0600

    rs780: correct comment in switching_gpp_configurations()
    
    Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
    Signed-off-by: Jonathan A. Kollasch <jakllsch at kollasch.net>

Build-Tested: build bot (Jenkins) at Sat Jan  7 17:28:51 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sun Jan  8 20:42:55 2012, giving +2
See http://review.coreboot.org/524 for details.

-gerrit


From gerrit at coreboot.org  Sun Jan  8 21:06:35 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Sun, 8 Jan 2012 21:06:35 +0100
Subject: [coreboot] Patch set updated for coreboot: cc32bd5 Set default
	baudrate on Alix2d to be compatible with factory default
References: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+0@gerrit.coreboot.org>
Message-ID: <Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0+4@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/508

-gerrit

commit cc32bd53cd174d32726186b107436edc699bd842
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Dec 28 16:32:44 2011 -0700

    Set default baudrate on Alix2d to be compatible with factory default
    
    Boards shipping from PC Engines with the factory BIOS (tinyBios 0.99)
    boot up at 38400. In keeping with the principle of least astonishment,
    boards reflashed with SeaBIOS should probably try to keep compatible
    with this setting.
    
    Change-Id: Ieda47016c78e673ce2f6aec8b270c2b511ebfcf0
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/alix2d/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..ea02adf 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select CONSOLE_SERIAL_38400
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Sun Jan  8 21:12:04 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Sun, 8 Jan 2012 21:12:04 +0100
Subject: [coreboot] Patch set updated for coreboot: 8718691 geos: missing
	Vendor information
References: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+0@gerrit.coreboot.org>
Message-ID: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+3@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520

-gerrit

commit 87186912502c19bec6f24febed5dc64f905bb08f
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:52:25 2012 -0700

    geos: missing Vendor information
    
    The DMI information isn't being generated correctly because of the
    mainboard vendor value not being set.
    
    Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..184beee 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -16,6 +16,10 @@ config MAINBOARD_DIR
 	string
 	default traverse/geos
 
+config MAINBOARD_VENDOR
+	string
+	default "PC Engines"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Geos"


From gerrit at coreboot.org  Sun Jan  8 21:54:13 2012
From: gerrit at coreboot.org (Alec Ari (neotheuser@ymail.com))
Date: Sun, 8 Jan 2012 21:54:13 +0100
Subject: [coreboot] Patch set updated for coreboot: bbedf7e Add support for
	MA785GM-US2H
References: <I58a7083a023ebf7373b6ded2e9f0adda7ab76dea+0@gerrit.coreboot.org>
Message-ID: <I58a7083a023ebf7373b6ded2e9f0adda7ab76dea+2@gerrit.coreboot.org>

Alec Ari (neotheuser at ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/476

-gerrit

commit bbedf7e55f845e022e0149e9b7bf005f4c559cb1
Author: Alec Ari <neotheuser at ymail.com>
Date:   Sun Jan 8 14:49:44 2012 -0600

    Add support for MA785GM-US2H
    
    This patch adds coreboot support for the
    GIGABYTE MA785GM-US2H board.
    
    This port now removes all dead code in
    the previous patch set, and also boots Fedora 16
    on x86_64 (Phenom II X4 955 BE)
    
    On-board audio causes spurious interrupts and
    the kernel gets stuck in an infinite loop.
    
    AtomBIOS on RadeonHD video cards does not function
    and causes another infinite loop. radeon.modeset=0
    must be set. acpi=off must also be set.
    
    With those kernel command line options set,
    Fedora 16 makes it to the login screen. USB
    mouse and keyboard don't work though. several
    USB error codes on boot-up. PS/2 should.
    
    Change-Id: I58a7083a023ebf7373b6ded2e9f0adda7ab76dea
    Signed-off-by: Alec Ari <neotheuser at ymail.com>
---
 src/mainboard/gigabyte/ma785gm/Kconfig          |   86 ++
 src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl |   75 +
 src/mainboard/gigabyte/ma785gm/acpi/ide.asl     |  244 +++
 src/mainboard/gigabyte/ma785gm/acpi/routing.asl |  300 ++++
 src/mainboard/gigabyte/ma785gm/acpi/sata.asl    |  149 ++
 src/mainboard/gigabyte/ma785gm/acpi/usb.asl     |  161 ++
 src/mainboard/gigabyte/ma785gm/acpi_tables.c    |  272 ++++
 src/mainboard/gigabyte/ma785gm/chip.h           |   23 +
 src/mainboard/gigabyte/ma785gm/cmos.layout      |   98 ++
 src/mainboard/gigabyte/ma785gm/devicetree.cb    |  115 ++
 src/mainboard/gigabyte/ma785gm/dsdt.asl         | 1850 +++++++++++++++++++++++
 src/mainboard/gigabyte/ma785gm/get_bus_conf.c   |  116 ++
 src/mainboard/gigabyte/ma785gm/irq_tables.c     |  112 ++
 src/mainboard/gigabyte/ma785gm/mainboard.c      |  206 +++
 src/mainboard/gigabyte/ma785gm/mb_sysconf.h     |   45 +
 src/mainboard/gigabyte/ma785gm/mptable.c        |  171 +++
 src/mainboard/gigabyte/ma785gm/resourcemap.c    |  281 ++++
 src/mainboard/gigabyte/ma785gm/romstage.c       |  256 ++++
 18 files changed, 4560 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig
new file mode 100644
index 0000000..1357104
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/Kconfig
@@ -0,0 +1,86 @@
+if BOARD_GIGABYTE_MA785GM
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_SOCKET_AM3
+	select DIMM_DDR2
+	select DIMM_REGISTERED
+	select NORTHBRIDGE_AMD_AMDFAM10
+	select SOUTHBRIDGE_AMD_RS780
+	select SOUTHBRIDGE_AMD_SB700
+	select SUPERIO_ITE_IT8718F
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_1024
+	select ENABLE_APIC_EXT_ID
+	select GFXUMA
+	select RAMINIT_SYSINFO
+	select QRANK_DIMM_SUPPORT
+
+config MAINBOARD_DIR
+	string
+	default gigabyte/ma785gm
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "GA-MA785GM-US2H"
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config MEM_TRAIN_SEQ
+	int
+	default 2
+
+config SB_HT_CHAIN_ON_BUS0
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	hex
+	default 0x1
+
+config HT_CHAIN_UNITID_BASE
+	hex
+	default 0x0
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config AMD_UCODE_PATCH_FILE
+	string
+	default "mc_patch_010000b6.h"
+
+config RAMTOP
+	hex
+	default 0x2000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config RAMBASE
+	hex
+	default 0x200000
+
+endif # BOARD_GIGABYTE_MA785GM
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl
new file mode 100644
index 0000000..6a1b002
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/ide.asl b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl
new file mode 100644
index 0000000..6ea2b09
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/routing.asl b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl
new file mode 100644
index 0000000..ad51815
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/routing.asl
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, INTB, 0 }, */
+		/* Package(){0x0005FFFF, 1, INTC, 0 }, */
+		/* Package(){0x0005FFFF, 2, INTD, 0 }, */
+		/* Package(){0x0005FFFF, 3, INTA, 0 }, */
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 1, INTA, 0 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0012FFFF, 0, INTA, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 0, INTA, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTA, 0 },
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:AC97 Audio;F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		/* Package(){0x0001FFFF, 0, 0, 18 }, */
+		/* package(){0x0001FFFF, 1, 0, 19 }, */
+
+		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		/* Package(){0x0002FFFF, 1, 0, 19 }, */
+		/* Package(){0x0002FFFF, 2, 0, 16 }, */
+		/* Package(){0x0002FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+		Package(){0x0003FFFF, 0, 0, 19 },
+
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		/* Package(){0x0004FFFF, 1, 0, 17 }, */
+		/* Package(){0x0004FFFF, 2, 0, 18 }, */
+		/* Package(){0x0004FFFF, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		/* Package(){0x0005FFFF, 0, 0, 17 }, */
+		/* Package(){0x0005FFFF, 1, 0, 18 }, */
+		/* Package(){0x0005FFFF, 2, 0, 19 }, */
+		/* Package(){0x0005FFFF, 3, 0, 16 }, */
+
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		/* Package(){0x0006FFFF, 0, 0, 18 }, */
+		/* Package(){0x0006FFFF, 1, 0, 19 }, */
+		/* Package(){0x0006FFFF, 2, 0, 16 }, */
+		/* Package(){0x0006FFFF, 3, 0, 17 }, */
+
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		/* Package(){0x0007FFFF, 0, 0, 19 }, */
+		/* Package(){0x0007FFFF, 1, 0, 16 }, */
+		/* Package(){0x0007FFFF, 2, 0, 17 }, */
+		/* Package(){0x0007FFFF, 3, 0, 18 }, */
+
+		/* Bus 0, Dev 9 - PCIe Bridge for network card */
+		Package(){0x0009FFFF, 0, 0, 17 },
+		/* Package(){0x0009FFFF, 1, 0, 16 }, */
+		/* Package(){0x0009FFFF, 2, 0, 17 }, */
+		/* Package(){0x0009FFFF, 3, 0, 18 }, */
+		/* Bus 0, Dev A - PCIe Bridge for network card */
+		Package(){0x000AFFFF, 0, 0, 18 },
+		/* Package(){0x000AFFFF, 1, 0, 16 }, */
+		/* Package(){0x000AFFFF, 2, 0, 17 }, */
+		/* Package(){0x000AFFFF, 3, 0, 18 }, */
+		/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		/* Bus 0, Dev 18 - SATA controller #1 */
+		Package(){0x0011FFFF, 0, 0, 22 },
+
+		/* Bus 0, Dev 19 - USB: OHCI, funct 0-4; EHCI, funct 5 */
+		Package(){0x0012FFFF, 0, 0, 16 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 19 },
+		Package(){0x0014FFFF, 0, 0, 16 },
+		/* Package(){0x00130004, 2, 0, 18 }, */
+		/* Package(){0x00130005, 3, 0, 19 }, */
+
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Package(){0x00140004, 2, 0, 18 }, */
+		/* Package(){0x00140004, 3, 0, 19 }, */
+		/* Package(){0x00140005, 1, 0, 17 }, */
+		/* Package(){0x00140006, 1, 0, 17 }, */
+	})
+
+	Name(PR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, INTA, 0 },
+		Package(){0x0005FFFF, 1, INTB, 0 },
+		Package(){0x0005FFFF, 2, INTC, 0 },
+		Package(){0x0005FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR1, Package(){
+		/* Internal graphics - RS780 VGA, Bus1, Dev5 */
+		Package(){0x0005FFFF, 0, 0, 18 },
+		Package(){0x0005FFFF, 1, 0, 19 },
+		/* Package(){0x0005FFFF, 2, 0, 20 }, */
+		/* Package(){0x0005FFFF, 3, 0, 17 }, */
+	})
+
+	Name(PS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* The external GFX - Hooked to PCIe slot 2 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* PCIe slot - Hooked to PCIe slot 4 */
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* PCIe slot - Hooked to PCIe slot 5 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* PCIe slot - Hooked to PCIe slot 6 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+	Name(PS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS9, Package(){
+		/* PCIe slot - Hooked to PCIe slot 9 */
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+	Name(PSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APSa, Package(){
+		/* PCIe slot - Hooked to PCIe slot 10 */
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PCIB, Package(){
+		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
+		Package(){0x0005FFFF, 0, 0, 0x14 },
+		Package(){0x0005FFFF, 1, 0, 0x15 },
+		Package(){0x0005FFFF, 2, 0, 0x16 },
+		Package(){0x0005FFFF, 3, 0, 0x17 },
+		Package(){0x0006FFFF, 0, 0, 0x15 },
+		Package(){0x0006FFFF, 1, 0, 0x16 },
+		Package(){0x0006FFFF, 2, 0, 0x17 },
+		Package(){0x0006FFFF, 3, 0, 0x14 },
+		Package(){0x0007FFFF, 0, 0, 0x16 },
+		Package(){0x0007FFFF, 1, 0, 0x17 },
+		Package(){0x0007FFFF, 2, 0, 0x14 },
+		Package(){0x0007FFFF, 3, 0, 0x15 },
+	})
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/sata.asl b/src/mainboard/gigabyte/ma785gm/acpi/sata.asl
new file mode 100644
index 0000000..b5e6fc5
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi/usb.asl b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl
new file mode 100644
index 0000000..203e0ad
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi/usb.asl
@@ -0,0 +1,161 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "usb.asl"
+	}
+*/
+Method(UCOC, 0) {
+	Sleep(20)
+    	Store(0x13,CMTI)
+	Store(0,GPSL)
+}
+
+/* USB Port 0 overcurrent uses Gpm 0 */
+If(LLessEqual(UOM0,9)) {
+	Scope (\_GPE) {
+		Method (_L13) {
+			UCOC()
+			if(LEqual(GPB0,PLC0)) {
+				Not(PLC0,PLC0)
+				Store(PLC0, \_SB.PT0D)
+			}
+		}
+	}
+}
+
+/* USB Port 1 overcurrent uses Gpm 1 */
+If (LLessEqual(UOM1,9)) {
+	Scope (\_GPE) {
+		Method (_L14) {
+			UCOC()
+			if (LEqual(GPB1,PLC1)) {
+				Not(PLC1,PLC1)
+				Store(PLC1, \_SB.PT1D)
+			}
+		}
+	}
+}
+
+/* USB Port 2 overcurrent uses Gpm 2 */
+If (LLessEqual(UOM2,9)) {
+	Scope (\_GPE) {
+		Method (_L15) {
+			UCOC()
+			if (LEqual(GPB2,PLC2)) {
+				Not(PLC2,PLC2)
+				Store(PLC2, \_SB.PT2D)
+			}
+		}
+	}
+}
+
+/* USB Port 3 overcurrent uses Gpm 3 */
+If (LLessEqual(UOM3,9)) {
+	Scope (\_GPE) {
+		Method (_L16) {
+			UCOC()
+			if (LEqual(GPB3,PLC3)) {
+				Not(PLC3,PLC3)
+				Store(PLC3, \_SB.PT3D)
+			}
+		}
+	}
+}
+
+/* USB Port 4 overcurrent uses Gpm 4 */
+If (LLessEqual(UOM4,9)) {
+	Scope (\_GPE) {
+		Method (_L19) {
+			UCOC()
+			if (LEqual(GPB4,PLC4)) {
+				Not(PLC4,PLC4)
+				Store(PLC4, \_SB.PT4D)
+			}
+		}
+	}
+}
+
+/* USB Port 5 overcurrent uses Gpm 5 */
+If (LLessEqual(UOM5,9)) {
+	Scope (\_GPE) {
+		Method (_L1A) {
+			UCOC()
+			if (LEqual(GPB5,PLC5)) {
+				Not(PLC5,PLC5)
+				Store(PLC5, \_SB.PT5D)
+			}
+		}
+	}
+}
+
+/* USB Port 6 overcurrent uses Gpm 6 */
+If (LLessEqual(UOM6,9)) {
+	Scope (\_GPE) {
+		/* Method (_L1C) { */
+		Method (_L06) {
+			UCOC()
+			if (LEqual(GPB6,PLC6)) {
+				Not(PLC6,PLC6)
+				Store(PLC6, \_SB.PT6D)
+			}
+		}
+	}
+}
+
+/* USB Port 7 overcurrent uses Gpm 7 */
+If (LLessEqual(UOM7,9)) {
+ 	Scope (\_GPE) {
+		/* Method (_L1D) { */
+		Method (_L07) {
+			UCOC()
+			if (LEqual(GPB7,PLC7)) {
+				Not(PLC7,PLC7)
+				Store(PLC7, \_SB.PT7D)
+			}
+		}
+	}
+}
+
+/* USB Port 8 overcurrent uses Gpm 8 */
+If (LLessEqual(UOM8,9)) {
+	Scope (\_GPE) {
+		Method (_L17) {
+			if (LEqual(G8IS,PLC8)) {
+				Not(PLC8,PLC8)
+				Store(PLC8, \_SB.PT8D)
+			}
+		}
+	}
+}
+
+/* USB Port 9 overcurrent uses Gpm 9 */
+If (LLessEqual(UOM9,9)) {
+	Scope (\_GPE) {
+		Method (_L0E) {
+			if (LEqual(G9IS,0)) {
+			Store(1,\_SB.PT9D)
+			}
+		}
+	}
+}
diff --git a/src/mainboard/gigabyte/ma785gm/acpi_tables.c b/src/mainboard/gigabyte/ma785gm/acpi_tables.c
new file mode 100644
index 0000000..1b2ea6e
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/acpi_tables.c
@@ -0,0 +1,272 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+extern const unsigned char AmlCode_ssdt[];
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+extern const unsigned char AmlCode_ssdt2[];
+extern const unsigned char AmlCode_ssdt3[];
+extern const unsigned char AmlCode_ssdt4[];
+extern const unsigned char AmlCode_ssdt5[];
+#endif
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB700 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
+					   IO_APIC_ADDR, 0);
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+	acpi_header_t *ssdtx;
+	void *p;
+	int i;
+#endif
+
+	get_bus_conf();	/* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdp, srat);
+
+	/* SLIT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current += slit->header.length;
+	acpi_add_table(rsdp, slit);
+
+	/* SSDT */
+	current	  = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
+	ssdt = (acpi_header_t *)current;
+	memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
+	current += ssdt->length;
+	memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
+	//Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+	update_ssdt((void*)ssdt);
+	/* recalculate checksum */
+	ssdt->checksum = 0;
+	ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	acpi_add_table(rsdp,ssdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
+	current = acpi_add_ssdt_pstates(rsdp, current);
+
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+
+	/* same htio, but different position? We may have to copy,
+	change HCIN, and recalculate the checknum and add_table */
+
+	for(i=1;i<sysconf.hc_possible_num;i++) {  // 0: is hc sblink
+		if((sysconf.pci1234[i] & 1) != 1 ) continue;
+		u8 c;
+		if (i < 7) {
+			c = (u8) ('4' + i - 1);
+		} else {
+			c = (u8) ('A' + i - 1 - 6);
+		}
+		current	  = ( current + 0x07) & -0x08;
+		printk(BIOS_DEBUG, "ACPI:    * SSDT for PCI%c at %lx\n", c, current); //pci0 and pci1 are in dsdt
+		ssdtx = (acpi_header_t *)current;
+		switch (sysconf.hcid[i]) {
+		case 1:
+			p = &AmlCode_ssdt2;
+			break;
+		case 2:
+			p = &AmlCode_ssdt3;
+			break;
+		case 3:	/* 8131 */
+			p = &AmlCode_ssdt4;
+			break;
+		default:
+			/* HTX no io apic */
+			p = &AmlCode_ssdt5;
+			break;
+		}
+		memcpy(ssdtx, p, sizeof(acpi_header_t));
+		current += ssdtx->length;
+		memcpy(ssdtx, p, ssdtx->length);
+		update_ssdtx((void *)ssdtx, i);
+		ssdtx->checksum = 0;
+		ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length);
+		acpi_add_table(rsdp, ssdtx);
+	}
+#endif
+
+	/* DSDT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
+	dsdt = (acpi_header_t *)current; // it will used by fadt
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+
+	/* FACS */ // it needs 64 bit alignment
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:	* FACS at %lx\n", current);
+	facs = (acpi_facs_t *) current; // it will be used by fadt
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* FADT */
+	current	  = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/chip.h b/src/mainboard/gigabyte/ma785gm/chip.h
new file mode 100644
index 0000000..70102aa
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout
new file mode 100644
index 0000000..53fdef5
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/cmos.layout
@@ -0,0 +1,98 @@
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb
new file mode 100644
index 0000000..47add73
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb
@@ -0,0 +1,115 @@
+# sample config for gigabyte/ma785gm
+chip northbridge/amd/amdfam10/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/socket_AM3  #L1 and DDR2
+			 device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x3060 inherit
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				chip southbridge/amd/rs780
+					device pci 0.0 on end # HT  	0x9601
+					device pci 1.0 on end # Internal Graphics P2P bridge 0x9602
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
+					device pci 3.0 off end # PCIE P2P bridge	0x960b
+					device pci 4.0 off end # PCIE P2P bridge 0x9604
+					device pci 5.0 off end # PCIE P2P bridge 0x9605
+					device pci 6.0 off end # PCIE P2P bridge 0x9606
+					device pci 7.0 off end # PCIE P2P bridge 0x9607
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					device pci 9.0 off end #
+					device pci a.0 on end #	PCIE P2P bridge 0x9609
+					register "gppsb_configuration" = "1"   # Configuration B
+					register "gpp_configuration" = "3"   # Configuration D default
+					register "port_enable" = "0x6fc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "2"
+
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.1 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.1 on end # USB
+					device pci 13.2 on end # USB
+	 				device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x439d
+						chip superio/ite/it8718f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8718f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # USB 2
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+				end	#southbridge/amd/sb700
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end
+	end #pci_domain
+	#for node 32 to node 63
+end
diff --git a/src/mainboard/gigabyte/ma785gm/dsdt.asl b/src/mainboard/gigabyte/ma785gm/dsdt.asl
new file mode 100644
index 0000000..58352a8
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/dsdt.asl
@@ -0,0 +1,1850 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+	"DSDT.AML",           /* Output filename */
+	"DSDT",                 /* Signature */
+	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
+	"GIGA  ",               /* OEMID */
+	"MA785GM ",	     /* TABLE ID */
+	0x00010001	/* OEM Revision */
+	)
+{	/* Start of ASL file */
+	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+
+	/* Data to be patched by the BIOS during POST */
+	/* FIXME the patching is not done yet! */
+	/* Memory related values */
+	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+	Name(PBLN, 0x0)	/* Length of BIOS area */
+
+	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+	/* USB overcurrent mapping pins.   */
+	Name(UOM0, 0)
+	Name(UOM1, 2)
+	Name(UOM2, 0)
+	Name(UOM3, 7)
+	Name(UOM4, 2)
+	Name(UOM5, 2)
+	Name(UOM6, 6)
+	Name(UOM7, 2)
+	Name(UOM8, 6)
+	Name(UOM9, 6)
+
+	/* Some global data */
+	Name(OSTP, 3)		/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+	Name(OSV, Ones)	/* Assume nothing */
+	Name(PMOD, One)	/* Assume APIC */
+
+	/*
+	 * Processor Object
+	 *
+	 */
+	Scope (\_PR) {		/* define processor scope */
+		Processor(
+			CPU0,		/* name space name */
+			0,		/* Unique number for this processor */
+			0x808,		/* PBLK system I/O address !hardcoded! */
+			0x06		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU1,		/* name space name */
+			1,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU2,		/* name space name */
+			2,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+
+		Processor(
+			CPU3,		/* name space name */
+			3,		/* Unique number for this processor */
+			0x0000,		/* PBLK system I/O address !hardcoded! */
+			0x00		/* PBLKLEN for boot processor */
+			) {
+			#include "acpi/cpstate.asl"
+		}
+	} /* End _PR scope */
+
+	/* PIC IRQ mapping registers, C00h-C01h */
+	OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
+		Field(PRQM, ByteAcc, NoLock, Preserve) {
+		PRQI, 0x00000008,
+		PRQD, 0x00000008,  /* Offset: 1h */
+	}
+	IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+		PINA, 0x00000008,	/* Index 0  */
+		PINB, 0x00000008,	/* Index 1 */
+		PINC, 0x00000008,	/* Index 2 */
+		PIND, 0x00000008,	/* Index 3 */
+		AINT, 0x00000008,	/* Index 4 */
+		SINT, 0x00000008,	/*  Index 5 */
+		, 0x00000008,	             /* Index 6 */
+		AAUD, 0x00000008,	/* Index 7 */
+		AMOD, 0x00000008,	/* Index 8 */
+		PINE, 0x00000008,	/* Index 9 */
+		PINF, 0x00000008,	/* Index A */
+		PING, 0x00000008,	/* Index B */
+		PINH, 0x00000008,	/* Index C */
+	}
+
+	/* PCI Error control register */
+	OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+		Field(PERC, ByteAcc, NoLock, Preserve) {
+		SENS, 0x00000001,
+		PENS, 0x00000001,
+		SENE, 0x00000001,
+		PENE, 0x00000001,
+	}
+
+	/* Client Management index/data registers */
+	OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+		Field(CMT, ByteAcc, NoLock, Preserve) {
+		CMTI,      8,
+		/* Client Management Data register */
+		G64E,   1,
+		G64O,      1,
+		G32O,      2,
+		,       2,
+		GPSL,     2,
+	}
+
+	/* GPM Port register */
+	OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+		Field(GPT, ByteAcc, NoLock, Preserve) {
+		GPB0,1,
+		GPB1,1,
+		GPB2,1,
+		GPB3,1,
+		GPB4,1,
+		GPB5,1,
+		GPB6,1,
+		GPB7,1,
+	}
+
+	/* Flash ROM program enable register */
+	OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+		Field(FRE, ByteAcc, NoLock, Preserve) {
+		,     0x00000006,
+		FLRE, 0x00000001,
+	}
+
+	/* PM2 index/data registers */
+	OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+		Field(PM2R, ByteAcc, NoLock, Preserve) {
+		PM2I, 0x00000008,
+		PM2D, 0x00000008,
+	}
+
+	/* Power Management I/O registers */
+	OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
+		Field(PIOR, ByteAcc, NoLock, Preserve) {
+		PIOI, 0x00000008,
+		PIOD, 0x00000008,
+	}
+	IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
+		Offset(0x00),	/* MiscControl */
+		, 1,
+		T1EE, 1,
+		T2EE, 1,
+		Offset(0x01),	/* MiscStatus */
+		, 1,
+		T1E, 1,
+		T2E, 1,
+		Offset(0x04),	/* SmiWakeUpEventEnable3 */
+		, 7,
+		SSEN, 1,
+		Offset(0x07),	/* SmiWakeUpEventStatus3 */
+		, 7,
+		CSSM, 1,
+		Offset(0x10),	/* AcpiEnable */
+		, 6,
+		PWDE, 1,
+		Offset(0x1C),	/* ProgramIoEnable */
+		, 3,
+		MKME, 1,
+		IO3E, 1,
+		IO2E, 1,
+		IO1E, 1,
+		IO0E, 1,
+		Offset(0x1D),	/* IOMonitorStatus */
+		, 3,
+		MKMS, 1,
+		IO3S, 1,
+		IO2S, 1,
+		IO1S, 1,
+		IO0S,1,
+		Offset(0x20),	/* AcpiPmEvtBlk */
+		APEB, 16,
+		Offset(0x36),	/* GEvtLevelConfig */
+		, 6,
+		ELC6, 1,
+		ELC7, 1,
+		Offset(0x37),	/* GPMLevelConfig0 */
+		, 3,
+		PLC0, 1,
+		PLC1, 1,
+		PLC2, 1,
+		PLC3, 1,
+		PLC8, 1,
+		Offset(0x38),	/* GPMLevelConfig1 */
+		, 1,
+		 PLC4, 1,
+		 PLC5, 1,
+		, 1,
+		 PLC6, 1,
+		 PLC7, 1,
+		Offset(0x3B),	/* PMEStatus1 */
+		GP0S, 1,
+		GM4S, 1,
+		GM5S, 1,
+		APS, 1,
+		GM6S, 1,
+		GM7S, 1,
+		GP2S, 1,
+		STSS, 1,
+		Offset(0x55),	/* SoftPciRst */
+		SPRE, 1,
+		, 1,
+		, 1,
+		PNAT, 1,
+		PWMK, 1,
+		PWNS, 1,
+
+		/* 	Offset(0x61), */	/*  Options_1 */
+		/* 		,7,  */
+		/* 		R617,1, */
+
+		Offset(0x65),	/* UsbPMControl */
+		, 4,
+		URRE, 1,
+		Offset(0x68),	/* MiscEnable68 */
+		, 3,
+		TMTE, 1,
+		, 1,
+		Offset(0x92),	/* GEVENTIN */
+		, 7,
+		E7IS, 1,
+		Offset(0x96),	/* GPM98IN */
+		G8IS, 1,
+		G9IS, 1,
+		Offset(0x9A),	/* EnhanceControl */
+		,7,
+		HPDE, 1,
+		Offset(0xA8),	/* PIO7654Enable */
+		IO4E, 1,
+		IO5E, 1,
+		IO6E, 1,
+		IO7E, 1,
+		Offset(0xA9),	/* PIO7654Status */
+		IO4S, 1,
+		IO5S, 1,
+		IO6S, 1,
+		IO7S, 1,
+	}
+
+	/* PM1 Event Block
+	* First word is PM1_Status, Second word is PM1_Enable
+	*/
+	OperationRegion(P1EB, SystemIO, APEB, 0x04)
+		Field(P1EB, ByteAcc, NoLock, Preserve) {
+		TMST, 1,
+		,    3,
+		BMST,    1,
+		GBST,   1,
+		Offset(0x01),
+		PBST, 1,
+		, 1,
+		RTST, 1,
+		, 3,
+		PWST, 1,
+		SPWS, 1,
+		Offset(0x02),
+		TMEN, 1,
+		, 4,
+		GBEN, 1,
+		Offset(0x03),
+		PBEN, 1,
+		, 1,
+		RTEN, 1,
+		, 3,
+		PWDA, 1,
+	}
+
+	Scope(\_SB) {
+		/* PCIe Configuration Space for 16 busses */
+		OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+			Field(PCFG, ByteAcc, NoLock, Preserve) {
+			/* Byte offsets are computed using the following technique:
+			 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+			 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+			*/
+			Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+			STB5, 32,
+			Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+			PT0D, 1,
+			PT1D, 1,
+			PT2D, 1,
+			PT3D, 1,
+			PT4D, 1,
+			PT5D, 1,
+			PT6D, 1,
+			PT7D, 1,
+			PT8D, 1,
+			PT9D, 1,
+			Offset(0x000A0004),	/* Byte offset to SMBUS	register 4h - Bus 0, Device 20, Function 0 */
+			SBIE, 1,
+			SBME, 1,
+			Offset(0x000A0008),	/* Byte offset to SMBUS	register 8h - Bus 0, Device 20, Function 0 */
+			SBRI, 8,
+			Offset(0x000A0014),	/* Byte offset to SMBUS	register 14h - Bus 0, Device 20, Function 0 */
+			SBB1, 32,
+			Offset(0x000A0078),	/* Byte offset to SMBUS	register 78h - Bus 0, Device 20, Function 0 */
+			,14,
+			P92E, 1,		/* Port92 decode enable */
+		}
+
+		OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+			Field(SB5, AnyAcc, NoLock, Preserve){
+			/* Port 0 */
+			Offset(0x120),		/* Port 0 Task file status */
+			P0ER, 1,
+			, 2,
+			P0DQ, 1,
+			, 3,
+			P0BY, 1,
+			Offset(0x128),		/* Port 0 Serial ATA status */
+			P0DD, 4,
+			, 4,
+			P0IS, 4,
+			Offset(0x12C),		/* Port 0 Serial ATA control */
+			P0DI, 4,
+			Offset(0x130),		/* Port 0 Serial ATA error */
+			, 16,
+			P0PR, 1,
+
+			/* Port 1 */
+			offset(0x1A0),		/* Port 1 Task file status */
+			P1ER, 1,
+			, 2,
+			P1DQ, 1,
+			, 3,
+			P1BY, 1,
+			Offset(0x1A8),		/* Port 1 Serial ATA status */
+			P1DD, 4,
+			, 4,
+			P1IS, 4,
+			Offset(0x1AC),		/* Port 1 Serial ATA control */
+			P1DI, 4,
+			Offset(0x1B0),		/* Port 1 Serial ATA error */
+			, 16,
+			P1PR, 1,
+
+			/* Port 2 */
+			Offset(0x220),		/* Port 2 Task file status */
+			P2ER, 1,
+			, 2,
+			P2DQ, 1,
+			, 3,
+			P2BY, 1,
+			Offset(0x228),		/* Port 2 Serial ATA status */
+			P2DD, 4,
+			, 4,
+			P2IS, 4,
+			Offset(0x22C),		/* Port 2 Serial ATA control */
+			P2DI, 4,
+			Offset(0x230),		/* Port 2 Serial ATA error */
+			, 16,
+			P2PR, 1,
+
+			/* Port 3 */
+			Offset(0x2A0),		/* Port 3 Task file status */
+			P3ER, 1,
+			, 2,
+			P3DQ, 1,
+			, 3,
+			P3BY, 1,
+			Offset(0x2A8),		/* Port 3 Serial ATA status */
+			P3DD, 4,
+			, 4,
+			P3IS, 4,
+			Offset(0x2AC),		/* Port 3 Serial ATA control */
+			P3DI, 4,
+			Offset(0x2B0),		/* Port 3 Serial ATA error */
+			, 16,
+			P3PR, 1,
+		}
+	}
+
+
+	#include "acpi/routing.asl"
+
+	Scope(\_SB) {
+
+		Method(CkOT, 0){
+
+			if(LNotEqual(OSTP, Ones)) {Return(OSTP)}	/* OS version was already detected */
+
+			if(CondRefOf(\_OSI,Local1))
+			{
+				Store(1, OSTP)                /* Assume some form of XP */
+				if (\_OSI("Windows 2006"))      /* Vista */
+				{
+					Store(2, OSTP)
+				}
+			} else {
+				If(WCMP(\_OS,"Linux")) {
+					Store(3, OSTP)            /* Linux */
+				} Else {
+					Store(4, OSTP)            /* Gotta be WinCE */
+				}
+			}
+			Return(OSTP)
+		}
+
+		Method(_PIC, 0x01, NotSerialized)
+		{
+			If (Arg0)
+			{
+				\_SB.CIRQ()
+			}
+			Store(Arg0, PMOD)
+		}
+		Method(CIRQ, 0x00, NotSerialized){
+			Store(0, PINA)
+			Store(0, PINB)
+			Store(0, PINC)
+			Store(0, PIND)
+			Store(0, PINE)
+			Store(0, PINF)
+			Store(0, PING)
+			Store(0, PINH)
+		}
+
+		Name(IRQB, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Shared){15}
+		})
+
+		Name(IRQP, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
+		})
+
+		Name(PITF, ResourceTemplate(){
+			IRQ(Level,ActiveLow,Exclusive){9}
+		})
+
+		Device(INTA) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 1)
+
+			Method(_STA, 0) {
+				if (PINA) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTA._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_DIS\n") */
+				Store(0, PINA)
+			} /* End Method(_SB.INTA._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTA._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINA, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTA._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKA\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINA)
+			} /* End Method(_SB.INTA._SRS) */
+		} /* End Device(INTA) */
+
+		Device(INTB) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 2)
+
+			Method(_STA, 0) {
+				if (PINB) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTB._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_DIS\n") */
+				Store(0, PINB)
+			} /* End Method(_SB.INTB._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTB._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINB, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTB._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKB\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINB)
+			} /* End Method(_SB.INTB._SRS) */
+		} /* End Device(INTB)  */
+
+		Device(INTC) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 3)
+
+			Method(_STA, 0) {
+				if (PINC) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTC._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_DIS\n") */
+				Store(0, PINC)
+			} /* End Method(_SB.INTC._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTC._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINC, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTC._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKC\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINC)
+			} /* End Method(_SB.INTC._SRS) */
+		} /* End Device(INTC)  */
+
+		Device(INTD) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 4)
+
+			Method(_STA, 0) {
+				if (PIND) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTD._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_DIS\n") */
+				Store(0, PIND)
+			} /* End Method(_SB.INTD._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTD._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PIND, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTD._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKD\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PIND)
+			} /* End Method(_SB.INTD._SRS) */
+		} /* End Device(INTD)  */
+
+		Device(INTE) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 5)
+
+			Method(_STA, 0) {
+				if (PINE) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTE._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_DIS\n") */
+				Store(0, PINE)
+			} /* End Method(_SB.INTE._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTE._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINE, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTE._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKE\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINE)
+			} /* End Method(_SB.INTE._SRS) */
+		} /* End Device(INTE)  */
+
+		Device(INTF) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 6)
+
+			Method(_STA, 0) {
+				if (PINF) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTF._STA) */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_DIS\n") */
+				Store(0, PINF)
+			} /* End Method(_SB.INTF._DIS) */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_PRS\n") */
+				Return(PITF)
+			} /* Method(_SB.INTF._PRS) */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINF, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTF._CRS) */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKF\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINF)
+			} /*  End Method(_SB.INTF._SRS) */
+		} /* End Device(INTF)  */
+
+		Device(INTG) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 7)
+
+			Method(_STA, 0) {
+				if (PING) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTG._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_DIS\n") */
+				Store(0, PING)
+			} /* End Method(_SB.INTG._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PING, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTG._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKG\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PING)
+			} /* End Method(_SB.INTG._SRS)  */
+		} /* End Device(INTG)  */
+
+		Device(INTH) {
+			Name(_HID, EISAID("PNP0C0F"))
+			Name(_UID, 8)
+
+			Method(_STA, 0) {
+				if (PINH) {
+					Return(0x0B) /* sata is invisible */
+				} else {
+					Return(0x09) /* sata is disabled */
+				}
+			} /* End Method(_SB.INTH._STA)  */
+
+			Method(_DIS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_DIS\n") */
+				Store(0, PINH)
+			} /* End Method(_SB.INTH._DIS)  */
+
+			Method(_PRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_PRS\n") */
+				Return(IRQP)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_CRS ,0) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(IRQB, 0x1, IRQN)
+				ShiftLeft(1, PINH, IRQN)
+				Return(IRQB)
+			} /* Method(_SB.INTH._CRS)  */
+
+			Method(_SRS, 1) {
+				/* DBGO("\\_SB\\LNKH\\_CRS\n") */
+				CreateWordField(ARG0, 1, IRQM)
+
+				/* Use lowest available IRQ */
+				FindSetRightBit(IRQM, Local0)
+				if (Local0) {
+					Decrement(Local0)
+				}
+				Store(Local0, PINH)
+			} /* End Method(_SB.INTH._SRS)  */
+		} /* End Device(INTH)   */
+
+	}   /* End Scope(_SB)  */
+
+
+	/* Supported sleep states: */
+	Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
+
+	If (LAnd(SSFG, 0x01)) {
+		Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
+	}
+	If (LAnd(SSFG, 0x02)) {
+		Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x04)) {
+		Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */
+	}
+	If (LAnd(SSFG, 0x08)) {
+		Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )	/* (S4) - Suspend to Disk */
+	}
+
+	Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )	/* (S5) - Soft Off */
+
+	Name(\_SB.CSPS ,0)				/* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+	Name(CSMS, 0)			/* Current System State */
+
+	/* Wake status package */
+	Name(WKST,Package(){Zero, Zero})
+
+	/*
+	* \_PTS - Prepare to Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+	*
+	* Exit:
+	*		-none-
+	*
+	* The _PTS control method is executed at the beginning of the sleep process
+	* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+	* control method may be executed a relatively long time before entering the
+	* sleep state and the OS may abort	the operation without notification to
+	* the ACPI driver.  This method cannot modify the configuration or power
+	* state of any device in the system.
+	*/
+	Method(\_PTS, 1) {
+		/* DBGO("\\_PTS\n") */
+		/* DBGO("From S0 to S") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+
+		/* Don't allow PCIRST# to reset USB */
+		if (LEqual(Arg0,3)){
+			Store(0,URRE)
+		}
+
+		/* Clear sleep SMI status flag and enable sleep SMI trap. */
+		/*Store(One, CSSM)
+		Store(One, SSEN)*/
+
+		/* On older chips, clear PciExpWakeDisEn */
+		/*if (LLessEqual(\_SB.SBRI, 0x13)) {
+		*    	Store(0,\_SB.PWDE)
+		*}
+		*/
+
+		/* Clear wake status structure. */
+		Store(0, Index(WKST,0))
+		Store(0, Index(WKST,1))
+		\_SB.PCI0.SIOS (Arg0)
+	} /* End Method(\_PTS) */
+
+	/*
+	*  The following method results in a "not a valid reserved NameSeg"
+	*  warning so I have commented it out for the duration.  It isn't
+	*  used, so it could be removed.
+	*
+	*
+	*  	\_GTS OEM Going To Sleep method
+	*
+	*  	Entry:
+	*  		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*  	Exit:
+	*  		-none-
+	*
+	*  Method(\_GTS, 1) {
+	*  DBGO("\\_GTS\n")
+	*  DBGO("From S0 to S")
+	*  DBGO(Arg0)
+	*  DBGO("\n")
+	*  }
+	*/
+
+	/*
+	*	\_BFS OEM Back From Sleep method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		-none-
+	*/
+	Method(\_BFS, 1) {
+		/* DBGO("\\_BFS\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+	}
+
+	/*
+	*  \_WAK System Wake method
+	*
+	*	Entry:
+	*		Arg0=The value of the sleeping state S1=1, S2=2
+	*
+	*	Exit:
+	*		Return package of 2 DWords
+	*		Dword 1 - Status
+	*			0x00000000	wake succeeded
+	*			0x00000001	Wake was signaled but failed due to lack of power
+	*			0x00000002	Wake was signaled but failed due to thermal condition
+	*		Dword 2 - Power Supply state
+	*			if non-zero the effective S-state the power supply entered
+	*/
+	Method(\_WAK, 1) {
+		/* DBGO("\\_WAK\n") */
+		/* DBGO("From S") */
+		/* DBGO(Arg0) */
+		/* DBGO(" to S0\n") */
+
+		/* Re-enable HPET */
+		Store(1,HPDE)
+
+		/* Restore PCIRST# so it resets USB */
+		if (LEqual(Arg0,3)){
+			Store(1,URRE)
+		}
+
+		/* Arbitrarily clear PciExpWakeStatus */
+		Store(PWST, PWST)
+
+		/* if(DeRefOf(Index(WKST,0))) {
+		*	Store(0, Index(WKST,1))
+		* } else {
+		*	Store(Arg0, Index(WKST,1))
+		* }
+		*/
+		\_SB.PCI0.SIOW (Arg0)
+		Return(WKST)
+	} /* End Method(\_WAK) */
+
+	Scope(\_GPE) {	/* Start Scope GPE */
+		/*  General event 0  */
+		/* Method(_L00) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 1  */
+		/* Method(_L01) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 2  */
+		/* Method(_L02) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 3  */
+		Method(_L03) {
+			/* DBGO("\\_GPE\\_L00\n") */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  General event 4  */
+		/* Method(_L04) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 5  */
+		/* Method(_L05) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 6 - Used for GPM6, moved to USB.asl */
+		/* Method(_L06) {
+		*	DBGO("\\_GPE\\_L00\n")
+		* }
+		*/
+
+		/*  General event 7 - Used for GPM7, moved to USB.asl */
+		/* Method(_L07) {
+		*	DBGO("\\_GPE\\_L07\n")
+		* }
+		*/
+
+		/*  Legacy PM event  */
+		Method(_L08) {
+			/* DBGO("\\_GPE\\_L08\n") */
+		}
+
+		/*  Temp warning (TWarn) event  */
+		Method(_L09) {
+			/* DBGO("\\_GPE\\_L09\n") */
+			Notify (\_TZ.TZ00, 0x80)
+		}
+
+		/*  Reserved  */
+		/* Method(_L0A) {
+		*	DBGO("\\_GPE\\_L0A\n")
+		* }
+		*/
+
+		/*  USB controller PME#  */
+		Method(_L0B) {
+			/* DBGO("\\_GPE\\_L0B\n") */
+			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  AC97 controller PME#  */
+		/* Method(_L0C) {
+		*	DBGO("\\_GPE\\_L0C\n")
+		* }
+		*/
+
+		/*  OtherTherm PME#  */
+		/* Method(_L0D) {
+		*	DBGO("\\_GPE\\_L0D\n")
+		* }
+		*/
+
+		/*  GPM9 SCI event - Moved to USB.asl */
+		/* Method(_L0E) {
+		*	DBGO("\\_GPE\\_L0E\n")
+		* }
+		*/
+
+		/*  PCIe HotPlug event  */
+		/* Method(_L0F) {
+		* 	DBGO("\\_GPE\\_L0F\n")
+		* }
+		*/
+
+		/*  ExtEvent0 SCI event  */
+		Method(_L10) {
+			/* DBGO("\\_GPE\\_L10\n") */
+		}
+
+
+		/*  ExtEvent1 SCI event  */
+		Method(_L11) {
+			/* DBGO("\\_GPE\\_L11\n") */
+		}
+
+		/*  PCIe PME# event  */
+		/* Method(_L12) {
+		*	DBGO("\\_GPE\\_L12\n")
+		* }
+		*/
+
+		/*  GPM0 SCI event - Moved to USB.asl */
+		/* Method(_L13) {
+		* 	DBGO("\\_GPE\\_L13\n")
+		* }
+		*/
+
+		/*  GPM1 SCI event - Moved to USB.asl */
+		/* Method(_L14) {
+		* 	DBGO("\\_GPE\\_L14\n")
+		* }
+		*/
+
+		/*  GPM2 SCI event - Moved to USB.asl */
+		/* Method(_L15) {
+		* 	DBGO("\\_GPE\\_L15\n")
+		* }
+		*/
+
+		/*  GPM3 SCI event - Moved to USB.asl */
+		/* Method(_L16) {
+		*	DBGO("\\_GPE\\_L16\n")
+		* }
+		*/
+
+		/*  GPM8 SCI event - Moved to USB.asl */
+		/* Method(_L17) {
+		* 	DBGO("\\_GPE\\_L17\n")
+		* }
+		*/
+
+		/*  GPIO0 or GEvent8 event  */
+		Method(_L18) {
+			/* DBGO("\\_GPE\\_L18\n") */
+			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM4 SCI event - Moved to USB.asl */
+		/* Method(_L19) {
+		* 	DBGO("\\_GPE\\_L19\n")
+		* }
+		*/
+
+		/*  GPM5 SCI event - Moved to USB.asl */
+		/* Method(_L1A) {
+		*	DBGO("\\_GPE\\_L1A\n")
+		* }
+		*/
+
+		/*  Azalia SCI event  */
+		Method(_L1B) {
+			/* DBGO("\\_GPE\\_L1B\n") */
+			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+		}
+
+		/*  GPM6 SCI event - Reassigned to _L06 */
+		/* Method(_L1C) {
+		*	DBGO("\\_GPE\\_L1C\n")
+		* }
+		*/
+
+		/*  GPM7 SCI event - Reassigned to _L07 */
+		/* Method(_L1D) {
+		*	DBGO("\\_GPE\\_L1D\n")
+		* }
+		*/
+
+		/*  GPIO2 or GPIO66 SCI event  */
+		/* Method(_L1E) {
+		* 	DBGO("\\_GPE\\_L1E\n")
+		* }
+		*/
+
+		/*  SATA SCI event - Moved to sata.asl */
+		/* Method(_L1F) {
+		*	 DBGO("\\_GPE\\_L1F\n")
+		* }
+		*/
+
+	} 	/* End Scope GPE */
+
+	#include "acpi/usb.asl"
+
+	/* South Bridge */
+	Scope(\_SB) { /* Start \_SB scope */
+		#include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+		/*  _SB.PCI0 */
+		/* Note: Only need HID on Primary Bus */
+		Device(PCI0) {
+			External (TOM1)
+			External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
+			Name(_HID, EISAID("PNP0A03"))
+			Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+			Method(_BBN, 0) { /* Bus number = 0 */
+				Return(0)
+			}
+			Method(_STA, 0) {
+				/* DBGO("\\_SB\\PCI0\\_STA\n") */
+				Return(0x0B)     /* Status is visible */
+			}
+
+			Method(_PRT,0) {
+				If(PMOD){ Return(APR0) }   /* APIC mode */
+				Return (PR0)                  /* PIC Mode */
+			} /* end _PRT */
+
+			/* Describe the Northbridge devices */
+			Device(AMRT) {
+				Name(_ADR, 0x00000000)
+			} /* end AMRT */
+
+			/* The internal GFX bridge */
+			Device(AGPB) {
+				Name(_ADR, 0x00010000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					Return (APR1)
+				}
+			}  /* end AGPB */
+
+			/* The external GFX bridge */
+			Device(PBR2) {
+				Name(_ADR, 0x00020000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS2) }   /* APIC mode */
+					Return (PS2)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR2 */
+
+			/* Dev3 is also an external GFX bridge, not used in Herring */
+
+			Device(PBR4) {
+				Name(_ADR, 0x00040000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS4) }   /* APIC mode */
+					Return (PS4)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR4 */
+
+			Device(PBR5) {
+				Name(_ADR, 0x00050000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS5) }   /* APIC mode */
+					Return (PS5)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR5 */
+
+			Device(PBR6) {
+				Name(_ADR, 0x00060000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS6) }   /* APIC mode */
+					Return (PS6)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR6 */
+
+			/* The onboard EtherNet chip */
+			Device(PBR7) {
+				Name(_ADR, 0x00070000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS7) }   /* APIC mode */
+					Return (PS7)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR7 */
+
+			/* GPP */
+			Device(PBR9) {
+				Name(_ADR, 0x00090000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APS9) }   /* APIC mode */
+					Return (PS9)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBR9 */
+
+			Device(PBRa) {
+				Name(_ADR, 0x000A0000)
+				Name(_PRW, Package() {0x18, 4})
+				Method(_PRT,0) {
+					If(PMOD){ Return(APSa) }   /* APIC mode */
+					Return (PSa)                  /* PIC Mode */
+				} /* end _PRT */
+			} /* end PBRa */
+
+
+			/* PCI slot 1, 2, 3 */
+			Device(PIBR) {
+				Name(_ADR, 0x00140004)
+				Name(_PRW, Package() {0x18, 4})
+
+				Method(_PRT, 0) {
+					Return (PCIB)
+				}
+			}
+
+			/* Describe the Southbridge devices */
+			Device(STCR) {
+				Name(_ADR, 0x00110000)
+				#include "acpi/sata.asl"
+			} /* end STCR */
+
+			Device(UOH1) {
+				Name(_ADR, 0x00130000)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH1 */
+
+			Device(UOH2) {
+				Name(_ADR, 0x00130001)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH2 */
+
+			Device(UOH3) {
+				Name(_ADR, 0x00130002)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH3 */
+
+			Device(UOH4) {
+				Name(_ADR, 0x00130003)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH4 */
+
+			Device(UOH5) {
+				Name(_ADR, 0x00130004)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UOH5 */
+
+			Device(UEH1) {
+				Name(_ADR, 0x00130005)
+				Name(_PRW, Package() {0x0B, 3})
+			} /* end UEH1 */
+
+			Device(SBUS) {
+				Name(_ADR, 0x00140000)
+			} /* end SBUS */
+
+			/* Primary (and only) IDE channel */
+			Device(IDEC) {
+				Name(_ADR, 0x00140001)
+				#include "acpi/ide.asl"
+			} /* end IDEC */
+
+			Device(AZHD) {
+				Name(_ADR, 0x00140002)
+				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+					Field(AZPD, AnyAcc, NoLock, Preserve) {
+					offset (0x42),
+					NSDI, 1,
+					NSDO, 1,
+					NSEN, 1,
+					offset (0x44),
+					IPCR, 4,
+					offset (0x54),
+					PWST, 2,
+					, 6,
+					PMEB, 1,
+					, 6,
+					PMST, 1,
+					offset (0x62),
+					MMCR, 1,
+					offset (0x64),
+					MMLA, 32,
+					offset (0x68),
+					MMHA, 32,
+					offset (0x6C),
+					MMDT, 16,
+				}
+
+				Method(_INI) {
+					If(LEqual(OSTP,3)){   /* If we are running Linux */
+						Store(zero, NSEN)
+						Store(one, NSDO)
+						Store(one, NSDI)
+					}
+				}
+			} /* end AZHD */
+
+			Device(LIBR) {
+				Name(_ADR, 0x00140003)
+				/* Method(_INI) {
+				*	DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
+				} */ /* End Method(_SB.SBRDG._INI) */
+
+				/* Real Time Clock Device */
+				Device(RTC0) {
+					Name(_HID, EISAID("PNP0B00"))	/* AT Real Time Clock (not PIIX4 compatible) */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){8}
+						IO(Decode16,0x0070, 0x0070, 0, 2)
+						/* IO(Decode16,0x0070, 0x0070, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+				Device(TMR) {	/* Timer */
+					Name(_HID,EISAID("PNP0100"))	/* System Timer */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){0}
+						IO(Decode16, 0x0040, 0x0040, 0, 4)
+						/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+				Device(SPKR) {	/* Speaker */
+					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x0061, 0x0061, 0, 1)
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+				Device(PIC) {
+					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
+					Name(_CRS, ResourceTemplate() {
+						IRQNoFlags(){2}
+						IO(Decode16,0x0020, 0x0020, 0, 2)
+						IO(Decode16,0x00A0, 0x00A0, 0, 2)
+						/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+						/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+				Device(MAD) { /* 8257 DMA */
+					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
+					Name(_CRS, ResourceTemplate() {
+						DMA(Compatibility,BusMaster,Transfer8){4}
+						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+				Device(COPR) {
+					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
+					Name(_CRS, ResourceTemplate() {
+						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+						IRQNoFlags(){13}
+					})
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+				Device(HPTM) {
+					Name(_HID,EISAID("PNP0103"))
+					Name(CRS,ResourceTemplate()	{
+						Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)	/* 1kb reserved space */
+					})
+					Method(_STA, 0) {
+						Return(0x0F) /* sata is visible */
+					}
+					Method(_CRS, 0)	{
+						CreateDwordField(CRS, ^HPT._BAS, HPBA)
+						Store(HPBA, HPBA)
+						Return(CRS)
+					}
+				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+			} /* end LIBR */
+
+			Device(HPBR) {
+				Name(_ADR, 0x00140004)
+			} /* end HostPciBr */
+
+			Device(ACAD) {
+				Name(_ADR, 0x00140005)
+			} /* end Ac97audio */
+
+			Device(ACMD) {
+				Name(_ADR, 0x00140006)
+			} /* end Ac97modem */
+
+			/* ITE8718 Support */
+			OperationRegion (IOID, SystemIO, 0x2E, 0x02)	/* sometimes it is 0x4E */
+				Field (IOID, ByteAcc, NoLock, Preserve)
+				{
+					SIOI,   8,    SIOD,   8		/* 0x2E and 0x2F */
+				}
+
+			IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
+			{
+					Offset (0x07),
+				LDN,	8,	/* Logical Device Number */
+					Offset (0x20),
+				CID1,	8,	/* Chip ID Byte 1, 0x87 */
+				CID2,	8,	/* Chip ID Byte 2, 0x12 */
+					Offset (0x30),
+				ACTR,	8,	/* Function activate */
+					Offset (0xF0),
+				APC0,	8,	/* APC/PME Event Enable Register */
+				APC1,	8,	/* APC/PME Status Register */
+				APC2,	8,	/* APC/PME Control Register 1 */
+				APC3,	8,	/* Environment Controller Special Configuration Register */
+				APC4,	8	/* APC/PME Control Register 2 */
+			}
+
+			/* Enter the 8718 MB PnP Mode */
+			Method (EPNP)
+			{
+				Store(0x87, SIOI)
+				Store(0x01, SIOI)
+				Store(0x55, SIOI)
+				Store(0x55, SIOI) /* 8718 magic number */
+			}
+			/* Exit the 8718 MB PnP Mode */
+			Method (XPNP)
+			{
+				Store (0x02, SIOI)
+				Store (0x02, SIOD)
+			}
+			/*
+			 * Keyboard PME is routed to SB700 Gevent3. We can wake
+			 * up the system by pressing the key.
+			 */
+			Method (SIOS, 1)
+			{
+				/* We only enable KBD PME for S5. */
+				If (LLess (Arg0, 0x05))
+				{
+					EPNP()
+					/* DBGO("8718F\n") */
+
+					Store (0x4, LDN)
+					Store (One, ACTR)  /* Enable EC */
+					/*
+					Store (0x4, LDN)
+					Store (0x04, APC4)
+					*/  /* falling edge. which mode? Not sure. */
+
+					Store (0x4, LDN)
+					Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
+					Store (0x4, LDN)
+					Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
+
+					XPNP()
+				}
+			}
+			Method (SIOW, 1)
+			{
+				EPNP()
+				Store (0x4, LDN)
+				Store (Zero, APC0) /* disable keyboard PME */
+				Store (0x4, LDN)
+				Store (0xFF, APC1) /* clear keyboard PME status */
+				XPNP()
+			}
+
+			Name(CRES, ResourceTemplate() {
+				IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0000,			/* range minimum */
+					0x0CF7,			/* range maximum */
+					0x0000,			/* translation */
+					0x0CF8			/* length */
+				)
+
+				WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,			/* address granularity */
+					0x0D00,			/* range minimum */
+					0xFFFF,			/* range maximum */
+					0x0000,			/* translation */
+					0xF300			/* length */
+				)
+
+				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
+				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
+				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
+
+				/* DRAM Memory from 1MB to TopMem */
+				Memory32Fixed(READWRITE, 0x00100000, 0, DMLO)	/* 1MB to TopMem */
+
+				/* BIOS space just below 4GB */
+				DWORDMemory(
+					ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00,			/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PCBM
+				)
+
+				/* DRAM memory from 4GB to TopMem2 */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					DMHI
+				)
+
+				/* BIOS space just below 16EB */
+				QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+					0x00000000,		/* Granularity */
+					0x00000000,		/* Min */
+					0x00000000,		/* Max */
+					0x00000000,		/* Translation */
+					0x00000001,		/* Max-Min, RLEN */
+					,,
+					PEBM
+				)
+
+			}) /* End Name(_SB.PCI0.CRES) */
+
+			Method(_CRS, 0) {
+				/* DBGO("\\_SB\\PCI0\\_CRS\n") */
+
+				CreateDWordField(CRES, ^EMM1._BAS, EM1B)
+				CreateDWordField(CRES, ^EMM1._LEN, EM1L)
+				CreateDWordField(CRES, ^DMLO._BAS, DMLB)
+				CreateDWordField(CRES, ^DMLO._LEN, DMLL)
+				CreateDWordField(CRES, ^PCBM._MIN, PBMB)
+				CreateDWordField(CRES, ^PCBM._LEN, PBML)
+
+				CreateQWordField(CRES, ^DMHI._MIN, DMHB)
+				CreateQWordField(CRES, ^DMHI._LEN, DMHL)
+				CreateQWordField(CRES, ^PEBM._MIN, EBMB)
+				CreateQWordField(CRES, ^PEBM._LEN, EBML)
+
+				If(LGreater(LOMH, 0xC0000)){
+					Store(0xC0000, EM1B)	/* Hole above C0000 and below E0000 */
+					Subtract(LOMH, 0xC0000, EM1L)	/* subtract start, assumes allocation from C0000 going up */
+				}
+
+				/* Set size of memory from 1MB to TopMem */
+				Subtract(TOM1, 0x100000, DMLL)
+
+				/*
+				* If(LNotEqual(TOM2, 0x00000000)){
+				*	Store(0x100000000,DMHB)			DRAM from 4GB to TopMem2
+				*	ShiftLeft(TOM2, 20, Local0)
+				*	Subtract(Local0, 0x100000000, DMHL)
+				* }
+				*/
+
+				/* If there is no memory above 4GB, put the BIOS just below 4GB */
+				If(LEqual(TOM2, 0x00000000)){
+					Store(PBAD,PBMB)			/* Reserve the "BIOS" space */
+					Store(PBLN,PBML)
+				}
+				Else {  /* Otherwise, put the BIOS just below 16EB */
+					ShiftLeft(PBAD,16,EBMB)		/* Reserve the "BIOS" space */
+					Store(PBLN,EBML)
+				}
+
+				Return(CRES) /* note to change the Name buffer */
+			}  /* end of Method(_SB.PCI0._CRS) */
+
+			/*
+			*
+			*               FIRST METHOD CALLED UPON BOOT
+			*
+			*  1. If debugging, print current OS and ACPI interpreter.
+			*  2. Get PCI Interrupt routing from ACPI VSM, this
+			*     value is based on user choice in BIOS setup.
+			*/
+			Method(_INI, 0) {
+				/* DBGO("\\_SB\\_INI\n") */
+				/* DBGO("   DSDT.ASL code from ") */
+				/* DBGO(__DATE__) */
+				/* DBGO(" ") */
+				/* DBGO(__TIME__) */
+				/* DBGO("\n   Sleep states supported: ") */
+				/* DBGO("\n") */
+				/* DBGO("   \\_OS=") */
+				/* DBGO(\_OS) */
+				/* DBGO("\n   \\_REV=") */
+				/* DBGO(\_REV) */
+				/* DBGO("\n") */
+
+				/* Determine the OS we're running on */
+				CkOT()
+
+				/* On older chips, clear PciExpWakeDisEn */
+				/*if (LLessEqual(\SBRI, 0x13)) {
+				*    	Store(0,\PWDE)
+				* }
+				*/
+			} /* End Method(_SB._INI) */
+		} /* End Device(PCI0)  */
+
+		Device(PWRB) {	/* Start Power button device */
+			Name(_HID, EISAID("PNP0C0C"))
+			Name(_UID, 0xAA)
+			Name(_PRW, Package () {3, 0x04})	/* wake from S1-S4 */
+			Name(_STA, 0x0B) /* sata is invisible */
+		}
+	} /* End \_SB scope */
+
+	Scope(\_SI) {
+		Method(_SST, 1) {
+			/* DBGO("\\_SI\\_SST\n") */
+			/* DBGO("   New Indicator state: ") */
+			/* DBGO(Arg0) */
+			/* DBGO("\n") */
+		}
+	} /* End Scope SI */
+
+	/* SMBUS Support */
+	Mutex (SBX0, 0x00)
+	OperationRegion (SMB0, SystemIO, 0xB00, 0x0C)
+		Field (SMB0, ByteAcc, NoLock, Preserve) {
+			HSTS,   8, /* SMBUS status */
+			SSTS,   8,  /* SMBUS slave status */
+			HCNT,   8,  /* SMBUS control */
+			HCMD,   8,  /* SMBUS host cmd */
+			HADD,   8,  /* SMBUS address */
+			DAT0,   8,  /* SMBUS data0 */
+			DAT1,   8,  /* SMBUS data1 */
+			BLKD,   8,  /* SMBUS block data */
+			SCNT,   8,  /* SMBUS slave control */
+			SCMD,   8,  /* SMBUS shaow cmd */
+			SEVT,   8,  /* SMBUS slave event */
+			SDAT,   8  /* SMBUS slave data */
+	}
+
+	Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
+		Store (0x1E, HSTS)
+		Store (0xFA, Local0)
+		While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
+			Stall (0x64)
+			Decrement (Local0)
+		}
+
+		Return (Local0)
+	}
+
+	Method (SWTC, 1, NotSerialized) {
+		Store (Arg0, Local0)
+		Store (0x07, Local2)
+		Store (One, Local1)
+		While (LEqual (Local1, One)) {
+			Store (And (HSTS, 0x1E), Local3)
+			If (LNotEqual (Local3, Zero)) { /* read sucess */
+				If (LEqual (Local3, 0x02)) {
+					Store (Zero, Local2)
+				}
+
+				Store (Zero, Local1)
+			}
+			Else {
+				If (LLess (Local0, 0x0A)) { /* read failure */
+					Store (0x10, Local2)
+					Store (Zero, Local1)
+				}
+				Else {
+					Sleep (0x0A) /* 10 ms, try again */
+					Subtract (Local0, 0x0A, Local0)
+				}
+			}
+		}
+
+		Return (Local2)
+	}
+
+	Method (SMBR, 3, NotSerialized) {
+		Store (0x07, Local0)
+		If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
+			Store (WCLR (), Local0) /* clear SMBUS status register before read data */
+			If (LEqual (Local0, Zero)) {
+				Release (SBX0)
+				Return (0x0)
+			}
+
+			Store (0x1F, HSTS)
+			Store (Or (ShiftLeft (Arg1, One), One), HADD)
+			Store (Arg2, HCMD)
+			If (LEqual (Arg0, 0x07)) {
+				Store (0x48, HCNT) /* read byte */
+			}
+
+			Store (SWTC (0x03E8), Local1) /* 1000 ms */
+			If (LEqual (Local1, Zero)) {
+				If (LEqual (Arg0, 0x07)) {
+					Store (DAT0, Local0)
+				}
+			}
+			Else {
+				Store (Local1, Local0)
+			}
+
+			Release (SBX0)
+		}
+
+		/* DBGO("the value of SMBusData0 register ") */
+		/* DBGO(Arg2) */
+		/* DBGO(" is ") */
+		/* DBGO(Local0) */
+		/* DBGO("\n") */
+
+		Return (Local0)
+	}
+
+	/* THERMAL */
+	Scope(\_TZ) {
+		Name (KELV, 2732)
+		Name (THOT, 800)
+		Name (TCRT, 850)
+
+		ThermalZone(TZ00) {
+			Method(_AC0,0) {	/* Active Cooling 0 (0=highest fan speed) */
+				/* DBGO("\\_TZ\\TZ00\\_AC0\n") */
+				Return(Add(0, 2730))
+			}
+			Method(_AL0,0) {	/* Returns package of cooling device to turn on */
+				/* DBGO("\\_TZ\\TZ00\\_AL0\n") */
+				Return(Package() {\_TZ.TZ00.FAN0})
+			}
+			Device (FAN0) {
+				Name(_HID, EISAID("PNP0C0B"))
+				Name(_PR0, Package() {PFN0})
+			}
+
+			PowerResource(PFN0,0,0) {
+				Method(_STA) {
+					Store(0xF,Local0)
+					Return(Local0)
+				}
+				Method(_ON) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
+				}
+				Method(_OFF) {
+					/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
+				}
+			}
+
+			Method(_HOT,0) {	/* return hot temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
+				Return (Add (THOT, KELV))
+			}
+			Method(_CRT,0) {	/* return critical temp in tenths degree Kelvin */
+				/* DBGO("\\_TZ\\TZ00\\_CRT\n") */
+				Return (Add (TCRT, KELV))
+			}
+			Method(_TMP,0) {	/* return current temp of this zone */
+				Store (SMBR (0x07, 0x4C,, 0x00), Local0)
+				If (LGreater (Local0, 0x10)) {
+					Store (Local0, Local1)
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400, KELV))
+				}
+
+				Store (SMBR (0x07, 0x4C, 0x01), Local0)
+				/* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
+				/* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
+				If (LGreater (Local0, 0x10)) {
+					If (LGreater (Local0, Local1)) {
+						Store (Local0, Local1)
+					}
+
+					Multiply (Local1, 10, Local1)
+					Return (Add (Local1, KELV))
+				}
+				Else {
+					Add (Local0, THOT, Local0)
+					Return (Add (400 , KELV))
+				}
+			} /* end of _TMP */
+		} /* end of TZ00 */
+	}
+}
+/* End of ASL file */
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
new file mode 100644
index 0000000..b169775
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -0,0 +1,116 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/multicore.h>
+#endif
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+* and acpi_tables busnum is default.
+*/
+u8 bus_rs780[11];
+u8 bus_sb700[2];
+u32 apicid_sb700;
+
+/*
+* Here you only need to set value in pci1234 for HT-IO that could be installed or not
+* You may need to preset pci1234 for HTIO board,
+* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+*/
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+* HT Chain device num, actually it is unit id base of every ht device in chain,
+* assume every chain only have 4 ht device at most
+*/
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 sbdn_rs780;
+u32 sbdn_sb700;
+
+extern void get_pci1234(void);
+
+static u32 get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+	u32 apicid_base;
+	device_t dev;
+	int i;
+
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
+	get_bus_conf_done = 1;
+
+	sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
+	for (i = 0; i < sysconf.hc_possible_num; i++) {
+		sysconf.pci1234[i] = pci1234x[i];
+		sysconf.hcdn[i] = hcdnx[i];
+	}
+
+	get_pci1234();
+
+	sysconf.sbdn = (sysconf.hcdn[0] & 0xff);
+	sbdn_rs780 = sysconf.sbdn;
+	sbdn_sb700 = 0;
+
+	for (i = 0; i < 2; i++) {
+		bus_sb700[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) {
+		bus_rs780[i] = 0;
+	}
+
+	bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb700[0] = bus_rs780[0];
+
+	/* sb700 */
+	dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
+	if (dev) {
+		bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	}
+
+	/* rs780 */
+	for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) {
+		dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
+		if (dev) {
+			bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+		}
+	}
+
+	/* I/O APICs:   APIC ID Version State   Address */
+#if CONFIG_LOGICAL_CPUS==1
+	apicid_base = get_apicid_base(1);
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+	apicid_sb700 = apicid_base + 0;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/irq_tables.c b/src/mainboard/gigabyte/ma785gm/irq_tables.c
new file mode 100644
index 0000000..fc9e42c
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/irq_tables.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+#include <cpu/amd/amdfam10_sysconf.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+			    u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_rs780[8];
+extern u8 bus_sb700[2];
+extern unsigned long sbdn_sb700;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb700[0];
+	pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+	slot_num++;
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
new file mode 100644
index 0000000..97a86f6
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -0,0 +1,206 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Alec Ari <neotheuser at ymail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "chip.h"
+
+uint64_t uma_memory_base, uma_memory_size;
+
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+int is_dev3_present(void);
+
+void set_pcie_dereset()
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
+	byte = pm_ioread(0x8d);
+	byte &= ~((1 << 1) | (1 << 2));
+	pm_iowrite(0x8d, byte);
+
+	/* set the GPM8 and GPM9 output enable and the value to 1 */
+	byte = pm_ioread(0x94);
+	byte &= ~((1 << 2) | (1 << 3));
+	byte |=  ((1 << 0) | (1 << 1));
+	pm_iowrite(0x94, byte);
+
+	/* set the GPIO65 output enable and the value is 1 */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word = pci_read_config16(sm_dev, 0x7e);
+	word |= (1 << 0);
+	word &= ~(1 << 4);
+	pci_write_config16(sm_dev, 0x7e, word);
+}
+
+void set_pcie_reset()
+{
+	u8 byte;
+	u16 word;
+	device_t sm_dev;
+
+	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
+	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
+	byte = pm_ioread(0x8d);
+	byte &= ~((1 << 1) | (1 << 2));
+	pm_iowrite(0x8d, byte);
+
+	/* set the GPM8 and GPM9 output enable and the value to 0 */
+	byte = pm_ioread(0x94);
+	byte &= ~((1 << 2) | (1 << 3));
+	byte &= ~((1 << 0) | (1 << 1));
+	pm_iowrite(0x94, byte);
+
+	/* set the GPIO65 output enable and the value is 0 */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+	word = pci_read_config16(sm_dev, 0x7e);
+	word &= ~(1 << 0);
+	word &= ~(1 << 4);
+	pci_write_config16(sm_dev, 0x7e, word);
+}
+
+/*
+ * dev3 does not exist on ma785gm
+ */
+int is_dev3_present(void)
+{
+		return 0;
+}
+
+/*
+ * set gpio40 gfx
+ */
+static void set_gpio40_gfx(void)
+{
+	u8 byte;
+//	u16 word;
+	u32 dword;
+	device_t sm_dev;
+	/* disable the GPIO40 as CLKREQ2# function */
+	byte = pm_ioread(0xd3);
+	byte &= ~(1 << 7);
+	pm_iowrite(0xd3, byte);
+
+	/* disable the GPIO40 as CLKREQ3# function */
+	byte = pm_ioread(0xd4);
+	byte &= ~(1 << 0);
+	pm_iowrite(0xd4, byte);
+
+	/* enable pull up for GPIO68 */
+	byte = pm2_ioread(0xf1);
+	byte &=	~(1 << 4);
+	pm2_iowrite(0xf1, byte);
+
+	/* access the smbus extended register */
+	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+
+	/* set the gfx to 1x16 lanes */
+		printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
+		/* when the gpio40 is configured as GPIO, this will enable the output */
+		pci_write_config32(sm_dev, 0xf8, 0x4);
+		dword = pci_read_config32(sm_dev, 0xfc);
+		dword &= ~(1 << 10);
+
+        	/* When the gpio40 is configured as GPIO, this will represent the output value*/
+		/* 1 :enable two x8  , 0 : master slot enable only */
+		dword &=  ~(1 << 26);
+		pci_write_config32(sm_dev, 0xfc, dword);
+}
+
+/*************************************************
+* enable the dedicated function in ma785gm board.
+* This function called early than rs780_enable.
+*************************************************/
+static void ma785gm_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
+
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+	     __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk(BIOS_INFO,
+	    "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+	     __func__, msr2.lo, msr2.hi);
+
+	switch (msr.lo) {
+	case 0x10000000:	/* 256M system memory */
+		uma_memory_size = 0x4000000;	/* 64M recommended UMA */
+		break;
+
+	case 0x20000000:	/* 512M system memory */
+		uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+		break;
+
+	default:		/* 1GB and above system memory */
+		uma_memory_size = 0x10000000;	/* 256M recommended UMA */
+		break;
+	}
+
+	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+		    __func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 0x8000000;	/* 128M recommended UMA */
+	uma_memory_base = 0x38000000;	/* 1GB  system memory supposed */
+#endif
+
+	set_pcie_dereset();
+	/* get_ide_dma66(); */
+	set_gpio40_gfx();
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+ 	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+		    uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			    uma_memory_size);
+#endif
+	return 0;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("GIGABYTE MA785GM-US2H   Mainboard")
+	.enable_dev = ma785gm_enable,
+};
diff --git a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h
new file mode 100644
index 0000000..8827fb6
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+	u8 bus_isa;
+	u8 bus_8132_0;
+	u8 bus_8132_1;
+	u8 bus_8132_2;
+	u8 bus_8111_0;
+	u8 bus_8111_1;
+	u8 bus_8132a[31][3];
+	u8 bus_8151[31][2];
+
+	u32 apicid_8111;
+	u32 apicid_8132_1;
+	u32 apicid_8132_2;
+	u32 apicid_8132a[31][2];
+	u32 sbdn3;
+	u32 sbdn3a[31];
+	u32 sbdn5[31];
+ 	u32 bus_type[256];
+};
+
+#endif
+
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
new file mode 100644
index 0000000..4bf3480
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <cpu/amd/amdfam10_sysconf.h>
+
+extern u8 bus_rs780[11];
+extern u8 bus_sb700[2];
+
+extern u32 apicid_sb700;
+
+extern u32 sbdn_rs780;
+extern u32 sbdn_sb700;
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+
+	get_bus_conf();
+
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	{
+		device_t dev;
+		u32 dword;
+		u8 byte;
+
+		dev =
+		    dev_find_slot(bus_sb700[0],
+				  PCI_DEVFN(sbdn_sb700 + 0x14, 0));
+		if (dev) {
+			dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_sb700, 0x11, dword);
+
+			/* Initialize interrupt mapping */
+			/* aza */
+			byte = pci_read_config8(dev, 0x63);
+			byte &= 0xf8;
+			byte |= 0;	/* 0: INTA, ...., 7: INTH */
+			pci_write_config8(dev, 0x63, byte);
+
+			/* SATA */
+			dword = pci_read_config32(dev, 0xac);
+			dword &= ~(7 << 26);
+			dword |= 6 << 26;	/* 0: INTA, ...., 7: INTH */
+			/* dword |= 1<<22; PIC and APIC co exists */
+			pci_write_config32(dev, 0xac, dword);
+
+			/*
+			 * 00:12.0: PROG SATA : INT F
+			 * 00:13.0: INTA USB_0
+			 * 00:13.1: INTB USB_1
+			 * 00:13.2: INTC USB_2
+			 * 00:13.3: INTD USB_3
+			 * 00:13.4: INTC USB_4
+			 * 00:13.5: INTD USB2
+			 * 00:14.1: INTA IDE
+			 * 00:14.2: Prog HDA : INT E
+			 * 00:14.5: INTB ACI
+			 * 00:14.6: INTB MCI
+			 */
+		}
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
+
+	/* usb */
+	PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */
+	PCI_INT(0x0, 0x12, 0x1, 0x11);
+	PCI_INT(0x0, 0x13, 0x0, 0x12);
+	PCI_INT(0x0, 0x13, 0x1, 0x13);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, 0x16);
+
+	/* HD Audio: b0:d20:f1:reg63 should be 0. */
+	/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
+
+	/* on board NIC & Slot PCIE.  */
+	/* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */
+/* 	PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */
+	PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */
+	/* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */
+	PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10);
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13);
+	 */
+	PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11);
+	PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c
new file mode 100644
index 0000000..7a3631b
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c
@@ -0,0 +1,281 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+
+static void setup_mb_resource_map(void)
+{
+	static const unsigned int register_values[] = {
+		/* Careful set limit registers before base registers which contain the enables */
+		/* DRAM Limit i Registers
+		 * F1:0x44 i = 0
+		 * F1:0x4C i = 1
+		 * F1:0x54 i = 2
+		 * F1:0x5C i = 3
+		 * F1:0x64 i = 4
+		 * F1:0x6C i = 5
+		 * F1:0x74 i = 6
+		 * F1:0x7C i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 3] Reserved
+		 * [10: 8] Interleave select
+		 *	   specifies the values of A[14:12] to use with interleave enable.
+		 * [15:11] Reserved
+		 * [31:16] DRAM Limit Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40 bit  address
+		 *	   that define the end of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		/* DRAM Base i Registers
+		 * F1:0x40 i = 0
+		 * F1:0x48 i = 1
+		 * F1:0x50 i = 2
+		 * F1:0x58 i = 3
+		 * F1:0x60 i = 4
+		 * F1:0x68 i = 5
+		 * F1:0x70 i = 6
+		 * F1:0x78 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 7: 2] Reserved
+		 * [10: 8] Interleave Enable
+		 *	   000 = No interleave
+		 *	   001 = Interleave on A[12] (2 nodes)
+		 *	   010 = reserved
+		 *	   011 = Interleave on A[12] and A[14] (4 nodes)
+		 *	   100 = reserved
+		 *	   101 = reserved
+		 *	   110 = reserved
+		 *	   111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+		 * [15:11] Reserved
+		 * [13:16] DRAM Base Address i Bits 39-24
+		 *	   This field defines the upper address bits of a 40-bit address
+		 *	   that define the start of the DRAM region.
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+		/* Memory-Mapped I/O Limit i Registers
+		 * F1:0x84 i = 0
+		 * F1:0x8C i = 1
+		 * F1:0x94 i = 2
+		 * F1:0x9C i = 3
+		 * F1:0xA4 i = 4
+		 * F1:0xAC i = 5
+		 * F1:0xB4 i = 6
+		 * F1:0xBC i = 7
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = Reserved
+		 * [ 6: 6] Reserved
+		 * [ 7: 7] Non-Posted
+		 *	   0 = CPU writes may be posted
+		 *	   1 = CPU writes must be non-posted
+		 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+		 *	   This field defines the upp adddress bits of a 40-bit address that
+		 *	   defines the end of a memory-mapped I/O region n
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+
+		/* Memory-Mapped I/O Base i Registers
+		 * F1:0x80 i = 0
+		 * F1:0x88 i = 1
+		 * F1:0x90 i = 2
+		 * F1:0x98 i = 3
+		 * F1:0xA0 i = 4
+		 * F1:0xA8 i = 5
+		 * F1:0xB0 i = 6
+		 * F1:0xB8 i = 7
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Cpu Disable
+		 *	   0 = Cpu can use this I/O range
+		 *	   1 = Cpu requests do not use this I/O range
+		 * [ 3: 3] Lock
+		 *	   0 = base/limit registers i are read/write
+		 *	   1 = base/limit registers i are read-only
+		 * [ 7: 4] Reserved
+		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+		 *	   This field defines the upper address bits of a 40bit address
+		 *	   that defines the start of memory-mapped I/O region i
+		 */
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+		/* PCI I/O Limit i Registers
+		 * F1:0xC4 i = 0
+		 * F1:0xCC i = 1
+		 * F1:0xD4 i = 2
+		 * F1:0xDC i = 3
+		 * [ 2: 0] Destination Node ID
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 3: 3] Reserved
+		 * [ 5: 4] Destination Link ID
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 = reserved
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Limit Address i
+		 *	   This field defines the end of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+		/* PCI I/O Base i Registers
+		 * F1:0xC0 i = 0
+		 * F1:0xC8 i = 1
+		 * F1:0xD0 i = 2
+		 * F1:0xD8 i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 3: 2] Reserved
+		 * [ 4: 4] VGA Enable
+		 *	   0 = VGA matches Disabled
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
+		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+		 * [ 5: 5] ISA Enable
+		 *	   0 = ISA matches Disabled
+		 *	   1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+		 *	       from matching agains this base/limit pair
+		 * [11: 6] Reserved
+		 * [24:12] PCI I/O Base i
+		 *	   This field defines the start of PCI I/O region n
+		 * [31:25] Reserved
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+		/* Config Base and Limit i Registers
+		 * F1:0xE0 i = 0
+		 * F1:0xE4 i = 1
+		 * F1:0xE8 i = 2
+		 * F1:0xEC i = 3
+		 * [ 0: 0] Read Enable
+		 *	   0 = Reads Disabled
+		 *	   1 = Reads Enabled
+		 * [ 1: 1] Write Enable
+		 *	   0 = Writes Disabled
+		 *	   1 = Writes Enabled
+		 * [ 2: 2] Device Number Compare Enable
+		 *	   0 = The ranges are based on bus number
+		 *	   1 = The ranges are ranges of devices on bus 0
+		 * [ 3: 3] Reserved
+		 * [ 6: 4] Destination Node
+		 *	   000 = Node 0
+		 *	   001 = Node 1
+		 *	   010 = Node 2
+		 *	   011 = Node 3
+		 *	   100 = Node 4
+		 *	   101 = Node 5
+		 *	   110 = Node 6
+		 *	   111 = Node 7
+		 * [ 7: 7] Reserved
+		 * [ 9: 8] Destination Link
+		 *	   00 = Link 0
+		 *	   01 = Link 1
+		 *	   10 = Link 2
+		 *	   11 - Reserved
+		 * [15:10] Reserved
+		 * [23:16] Bus Number Base i
+		 *	   This field defines the lowest bus number in configuration region i
+		 * [31:24] Bus Number Limit i
+		 *	   This field defines the highest bus number in configuration regin i
+		 */
+//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
+		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+	};
+
+	int max;
+	max = ARRAY_SIZE(register_values);
+	setup_resource_map(register_values, max);
+}
+
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
new file mode 100644
index 0000000..4572169
--- /dev/null
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -0,0 +1,256 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Wang Qing Pei <wangqingpei at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* DESKTOP */
+//#define SYSTEM_TYPE 2	/* MOBILE */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include <lib.h>
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/ite/it8718f/early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include <cpu/amd/mtrr.h>
+#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/rs780/early_setup.c"
+#include "southbridge/amd/sb700/sb700.h"
+#include "southbridge/amd/sb700/smbus.h"
+#include "northbridge/amd/amdfam10/debug.c"
+
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
+
+static int spd_read_byte(u32 device, u32 address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+#include "northbridge/amd/amdfam10/amdfam10.h"
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/microcode/microcode.c"
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#endif
+
+#include "cpu/amd/model_10xxx/init_cpus.c"
+#include "northbridge/amd/amdfam10/early_ht.c"
+#include <spd.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
+	u32 bsp_apicid = 0, val;
+	msr_t msr;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		/* Nothing special needs to be done to find bus 0 */
+		/* Allow the HT devices to be found */
+		/* mov bsp to bus 0xff when > 8 nodes */
+		set_bsp_node_CHtExtNodeCfgEn();
+		enumerate_ht_chain();
+		sb7xx_51xx_pci_port80();
+	}
+
+	post_code(0x30);
+
+	if (bist == 0) {
+		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
+		/* All cores run this but the BSP(node0,core0) is the only core that returns. */
+	}
+
+	post_code(0x32);
+
+	enable_rs780_dev8();
+	sb7xx_51xx_lpc_init();
+
+	it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
+	it8718f_disable_reboot();
+	console_init();
+
+//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+	printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	/* Setup sysinfo defaults */
+	set_sysinfo_in_ram(0);
+
+#if CONFIG_UPDATE_CPU_MICROCODE
+	update_microcode(val);
+#endif
+	post_code(0x33);
+
+	cpuSetAMDMSR();
+	post_code(0x34);
+
+	amd_ht_init(sysinfo);
+	post_code(0x35);
+
+	/* Setup nodes PCI space and start core 0 AP init. */
+	finalize_node_setup(sysinfo);
+
+	/* Setup any mainboard PCI settings etc. */
+	setup_mb_resource_map();
+	post_code(0x36);
+
+	/* wait for all the APs core0 started by finalize_node_setup. */
+	/* FIXME: A bunch of cores are going to start output to serial at once.
+	   It would be nice to fixup prink spinlocks for ROM XIP mode.
+	   I think it could be done by putting the spinlock flag in the cache
+	   of the BSP located right after sysinfo.
+	 */
+	wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+	/* Core0 on each node is configured. Now setup any additional cores. */
+	printk(BIOS_DEBUG, "start_other_cores()\n");
+	start_other_cores();
+	post_code(0x37);
+	wait_all_other_cores_started(bsp_apicid);
+#endif
+
+	post_code(0x38);
+
+	/* run _early_setup before soft-reset. */
+	rs780_early_setup();
+	sb7xx_51xx_early_setup();
+
+#if CONFIG_SET_FIDVID
+	msr = rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+
+	/* FIXME: The sb fid change may survive the warm reset and only
+	   need to be done once.*/
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+	post_code(0x39);
+
+	if (!warm_reset_detect(0)) {			// BSP is node 0
+		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+	} else {
+		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+	}
+
+	post_code(0x3A);
+
+	/* show final fid and vid */
+	msr=rdmsr(0xc0010071);
+	printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
+#endif
+
+	rs780_htinit();
+
+	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	if (!warm_reset_detect(0)) {
+		print_info("...WARM RESET...\n\n\n");
+		soft_reset();
+		die("After soft_reset_x - shouldn't see this message!!!\n");
+	}
+
+	post_code(0x3B);
+
+	/* It's the time to set ctrl in sysinfo now; */
+	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
+	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+	post_code(0x40);
+
+//	die("Die Before MCT init.");
+
+	printk(BIOS_DEBUG, "raminit_amdmct()\n");
+	raminit_amdmct(sysinfo);
+	post_code(0x41);
+
+/*
+	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
+	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
+*/
+
+//	die("After MCT init before CAR disabled.");
+
+	rs780_before_pci_init();
+	sb7xx_51xx_before_pci_init();
+
+	post_code(0x42);
+	printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_code(0x43);	// Should never see this post code.
+}
+
+/**
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ *	This routine is called every time a non-coherent chain is processed.
+ *	BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ *	swap list. The first part of the list controls the BUID assignment and the
+ *	second part of the list provides the device to device linking.  Device orientation
+ *	can be detected automatically, or explicitly.  See documentation for more details.
+ *
+ *	Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ *	based on each device's unit count.
+ *
+ * Parameters:
+ *	@param[in]  u8  node    = The node on which this chain is located
+ *	@param[in]  u8  link    = The link on the host for this chain
+ *	@param[out] u8** list   = supply a pointer to a list
+ *	@param[out] BOOL result = true to use a manual list
+ *				  false to initialize the link automatically
+ */
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+	/* If the BUID was adjusted in early_ht we need to do the manual override */
+	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
+		printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
+		if ((node == 0) && (link == 0)) {	/* BSP SB link */
+			*List = swaplist;
+			return 1;
+		}
+	}
+
+	return 0;
+}


From gerrit at coreboot.org  Mon Jan  9 00:26:53 2012
From: gerrit at coreboot.org (Nils Jacobs (njacobs8@adsltotaal.nl))
Date: Mon, 9 Jan 2012 00:26:53 +0100
Subject: [coreboot] New patch to review for coreboot: 047d2e8 Add MSR
	register writes for VGA Add missing license Add bit explanation
References: <Ibf0ee569b1addcad575f20fcfdd6ffc28322ca12+0@gerrit.coreboot.org>
Message-ID: <Ibf0ee569b1addcad575f20fcfdd6ffc28322ca12+1@gerrit.coreboot.org>

Nils Jacobs (njacobs8 at adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/526

-gerrit

commit 047d2e80c1b8aafb29bfa4c5f0db0497860c8fdc
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Mon Jan 9 00:19:33 2012 +0100

    Add MSR register writes for VGA
    Add missing license
    Add bit explanation
    
    Change-Id: Ibf0ee569b1addcad575f20fcfdd6ffc28322ca12
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>
---
 src/northbridge/amd/gx2/grphinit.c |   95 ++++++++++++++++++++++++++++++++++--
 1 files changed, 90 insertions(+), 5 deletions(-)

diff --git a/src/northbridge/amd/gx2/grphinit.c b/src/northbridge/amd/gx2/grphinit.c
index fce1190..d6955a2 100644
--- a/src/northbridge/amd/gx2/grphinit.c
+++ b/src/northbridge/amd/gx2/grphinit.c
@@ -1,18 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
 #include <arch/io.h>
 #include <stdint.h>
 #include <cpu/amd/vr.h>
-#include <device/device.h>
-#include "chip.h"
-#include "northbridge.h"
+#include <console/console.h>
+#include <cpu/amd/gx2def.h>
+#include <cpu/x86/msr.h>
+#include <stdlib.h>
+
+void geodegx2_vga_msr_init(void);
+void graphics_init(void);
+
+struct msrinit {
+	u32 msrnum;
+	msr_t msr;
+};
+
+static const struct msrinit geodegx2_vga_msr[] = {
+	/* Enable the GLIU Memory routing to the hardware
+	* PDID1 : Port 4, GLIU0
+	* PBASE : 0x000A0
+	* PMASK : 0xFFFE0
+	*/
+	{.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
+	/* Enable the GLIU IO Routing
+	* IDID  : Port 4, GLIU0
+	* IBASE : 0x003c0
+	* IMASK : 0xffff0
+	*/
+	{.msrnum = GLIU0_IOD_BM_0,  {.lo = 0x3c0ffff0, .hi = 0x80000000}},
+	/* Enable the GLIU IO Routing
+	* IDID  : Port 4, GLIU0
+	* IBASE : 0x003d0
+	* IMASK : 0xffff0
+	*/
+	{.msrnum = GLIU0_IOD_BM_1,  {.lo = 0x3d0ffff0, .hi = 0x80000000}},
+};
+
+void geodegx2_vga_msr_init(void)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++)
+		wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr);
+}
+
 
 /* This function mirrors the Graphics_Init routine in GeodeROM. */
 void graphics_init(void)
 {
+	uint16_t wClassIndex, wData, res;
+
 	/* SoftVG initialization */
+	printk(BIOS_DEBUG, "Graphics init...\n");
+
+	geodegx2_vga_msr_init();
 
 	/* Call SoftVG with the main configuration parameters. */
-	/* NOTE: SoftVG expects the memory size to be given in 512 KB pages */
-	vrWrite((VRC_VG <<  8) + VG_MEM_SIZE, 0x0100 | (CONFIG_VIDEO_MB * 2));
+	/* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */
+
+	wClassIndex = (VRC_VG << 8) + VG_CONFIG;
+
+	/*
+	 * Graphics Driver Enabled (13)				0, NO (lets BIOS controls the GP)
+	 * External Monochrome Card Support(12)			0, NO
+	 * Controller Priority Select(11)			1, Primary
+	 * Display Select(10:8)					0x0, CRT
+	 * Graphics Memory Size(7:1)				CONFIG_VIDEO_MB >> 1,
+	 *							defined in devicetree.cb
+	 * PLL Reference Clock Bypass(0)			0, Default
+	 */
+
+	/* Video RAM has to be given in 512KB chunks
+	 *   the value is read @ 7:1 (value in 7:0 looks like /2)
+	 *   so we can add the real value in megabytes
+	 */
+
+	wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK);
+	vrWrite(wClassIndex, wData);
+
+	res = vrRead(wClassIndex);
+	printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
 }
 
 


From gerrit at coreboot.org  Mon Jan  9 04:05:16 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Mon, 9 Jan 2012 04:05:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 973b589 geos: missing
	Vendor information
References: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+0@gerrit.coreboot.org>
Message-ID: <I07a6620bc6938292fecd50dc3ff0cb926d9c5f97+4@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/520

-gerrit

commit 973b589e6002d48e4184904d4be7afc3c2317c10
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sun Jan 8 20:00:45 2012 -0700

    geos: missing Vendor information
    
    The DMI information isn't being generated correctly because of the
    mainboard vendor value not being set.
    
    Change-Id: I07a6620bc6938292fecd50dc3ff0cb926d9c5f97
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/traverse/geos/Kconfig |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..6b7813b 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -16,6 +16,10 @@ config MAINBOARD_DIR
 	string
 	default traverse/geos
 
+config MAINBOARD_VENDOR
+	string
+	default "Traverse Technologies"
+
 config MAINBOARD_PART_NUMBER
 	string
 	default "Geos"


From gerrit at coreboot.org  Mon Jan  9 04:28:47 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Mon, 9 Jan 2012 04:28:47 +0100
Subject: [coreboot] New patch to review for coreboot: f11e0ec geode: need
	VSA files to initialize h/w properly
References: <Ieb71958f788084b587a3192343445bca4fb40f37+0@gerrit.coreboot.org>
Message-ID: <Ieb71958f788084b587a3192343445bca4fb40f37+1@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/527

-gerrit

commit f11e0ec621c2b1dde12c4532b3d9873c953c6b59
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Sun Jan 8 20:28:17 2012 -0700

    geode: need VSA files to initialize h/w properly
    
    SeaBIOS and other payloads will likely hang if the VSA hasn't been
    initialized properly beforehand.
    
    Change-Id: Ieb71958f788084b587a3192343445bca4fb40f37
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/alix2d/Kconfig |    2 ++
 src/mainboard/traverse/geos/Kconfig    |    2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..23766c7 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_512
 	select POWER_BUTTON_FORCE_DISABLE
+	select GEODE_VSA
+	select GEODE_VSA_FILE
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
index dd6c8dd..5e435fa 100644
--- a/src/mainboard/traverse/geos/Kconfig
+++ b/src/mainboard/traverse/geos/Kconfig
@@ -11,6 +11,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select BOARD_ROMSIZE_KB_1024
 	select POWER_BUTTON_DEFAULT_DISABLE
+	select GEODE_VSA
+	select GEODE_VSA_FILE
 
 config MAINBOARD_DIR
 	string


From gerrit at coreboot.org  Mon Jan  9 04:42:01 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Mon, 9 Jan 2012 04:42:01 +0100
Subject: [coreboot] Patch set updated for coreboot: 56d8552 alix2: add
	support for alix6
References: <I19e4e756966e60bb0310c19286654d3d579b8850+0@gerrit.coreboot.org>
Message-ID: <I19e4e756966e60bb0310c19286654d3d579b8850+3@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/521

-gerrit

commit 56d8552a1bb3cd9aca669899e4d2e8a18534d006
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Fri Jan 6 11:54:23 2012 -0700

    alix2: add support for alix6
    
    The Alix6 is very similar to the alix2, differing in having 1 mini-PCIe
    slot (USB 2.0 only), an RFKILL GPIO line going to that slot, and 1 or 2
    SIM sockets.
    
    Change-Id: I19e4e756966e60bb0310c19286654d3d579b8850
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/pcengines/Kconfig        |    2 ++
 src/mainboard/pcengines/alix2d/Kconfig |    7 ++++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index d5d7008..d8a0201 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -7,6 +7,8 @@ config BOARD_PCENGINES_ALIX1C
 	bool "ALIX.1C"
 config BOARD_PCENGINES_ALIX2D
 	bool "ALIX.2D2 or 2D3"
+config BOARD_PCENGINES_ALIX6
+	bool "ALIX.6"
 
 endchoice
 
diff --git a/src/mainboard/pcengines/alix2d/Kconfig b/src/mainboard/pcengines/alix2d/Kconfig
index 264f5d9..0182e52 100644
--- a/src/mainboard/pcengines/alix2d/Kconfig
+++ b/src/mainboard/pcengines/alix2d/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_PCENGINES_ALIX2D
+if BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
@@ -18,10 +18,11 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "ALIX.2D"
+	default "ALIX.2D" if BOARD_PCENGINES_ALIX2D
+	default "ALIX.6" if BOARD_PCENGINES_ALIX6
 
 config IRQ_SLOT_COUNT
 	int
 	default 7
 
-endif # BOARD_PCENGINES_ALIX2D
+endif # BOARD_PCENGINES_ALIX2D || BOARD_PCENGINES_ALIX6


From gerrit at coreboot.org  Mon Jan  9 10:55:48 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Mon, 9 Jan 2012 10:55:48 +0100
Subject: [coreboot] Patch set updated for coreboot: 0b00a17 ACPI: mark empty
	get_cst_entries() weak
References: <I4bc0168aee110171faeaa081f217dfd1536bb821+0@gerrit.coreboot.org>
Message-ID: <I4bc0168aee110171faeaa081f217dfd1536bb821+3@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/496

-gerrit

commit 0b00a17cc8276a4ebfbe645d5e66888460b75327
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 23 10:29:09 2011 +0100

    ACPI: mark empty get_cst_entries() weak
    
    This function prevents the linker from choosing the right
    get_cst_entries(), preventing writing the _CST tables.
    
    Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/include/arch/acpigen.h |    2 +-
 src/cpu/intel/speedstep/acpi.c      |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index 0833371..9dc9675 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -66,6 +66,6 @@ int acpigen_write_resourcetemplate_footer(int len);
 int acpigen_write_mainboard_resource_template(void);
 int acpigen_write_mainboard_resources(const char *scope, const char *name);
 
-int get_cst_entries(struct cst_entry **) __attribute__((weak));
+int get_cst_entries(struct cst_entry **);
 
 #endif
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 8f32e4f..00c4ae9 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -62,7 +62,7 @@ static int get_fsb(void)
 	return 200;
 }
 
-int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
+int __attribute__((weak)) get_cst_entries(struct cst_entry **entries __attribute__((unused)))
 {
 	return 0;
 }


From gerrit at coreboot.org  Mon Jan  9 11:07:19 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 9 Jan 2012 11:07:19 +0100
Subject: [coreboot] Patch merged into coreboot/master: 0b00a17 ACPI: mark
	empty get_cst_entries() weak
References: <I4bc0168aee110171faeaa081f217dfd1536bb821+0@gerrit.coreboot.org>
Message-ID: <E1RkC8N-0007VT-S4@ra.coresystems.de>

the following patch was just integrated into master:
commit 0b00a17cc8276a4ebfbe645d5e66888460b75327
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 23 10:29:09 2011 +0100

    ACPI: mark empty get_cst_entries() weak
    
    This function prevents the linker from choosing the right
    get_cst_entries(), preventing writing the _CST tables.
    
    Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Jan  9 11:07:17 2012, giving +2
See http://review.coreboot.org/496 for details.

-gerrit


From svante.ekholm at crosscontrol.com  Mon Jan  9 11:12:24 2012
From: svante.ekholm at crosscontrol.com (Svante Ekholm)
Date: Mon, 9 Jan 2012 10:12:24 +0000
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
Message-ID: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>

Hello, community!

Over the last six months I've been working on my M.Sc. thesis: Controlling the Bootstrap Process: Firmware Alternatives for an x86 Embedded Platform. The thesis is now complete and is available from http://uu.diva-portal.org/smash/record.jsf?searchId=1&pid=diva2:469328 . The text explores the feasibility of firmware engineering on a lower-tier OEM level with the aims of achieving control of the firmware and boot time optimization. It evaluates the current state of x86 firmware engineering and market, including the legacy BIOS, the UEFI standard, and most importantly: the coreboot project. It also looks (briefly) at commercial products such as the Intel Boot Loader Development Kit and the Congatec BIOS Utility. A prototype bootloader using coreboot+SeaBIOS is constructed and tested for a rugged, embedded, Core 2 Duo-based computer using a Kontron ETX module.

On another note: There has long been a lack of good introductory material into x86 firmware engineering. In the thesis there is a rather large theory section, covering PCI interrupt handling, ACPI, legacy BIOS, UEFI and coreboot. I've decided to release this portion under a Creative Commons by-nc-sa license to the community. I hope that this text can act as a ramp for introducing new people into the subject and you are welcome to help expand it. Peter Stuge will be setting up a git repository for the source of this introduction. The material is until then available at http://xerent.lokalen.org/files/firmware.pdf and http://xerent.lokalen.org/files/firmware-source.zip .

Best regards,

Svante Ekholm Lindahl
Embedded Software Developer

dir:          +46 271 75 76 27
sms:        +46 730 73 33 42

CrossControl AB
Norra ?sav?gen 11B
822 22 Alfta, Sweden
www.crosscontrol.com<http://www.crosscontrol.com/>

CrossControl - Humans in control

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From svn at coreboot.org  Mon Jan  9 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 09 Jan 2012 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1RkGhd-0000mz-Qr@ra.coresystems.de>

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From GNUtoo at no-log.org  Mon Jan  9 20:11:33 2012
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Mon, 9 Jan 2012 20:11:33 +0100
Subject: [coreboot] TOM2 and M4A785T-M
In-Reply-To: <CALrs_3ia=C1OzHWJLwgUO7bspYXxw4CFYJuWJm5BUNj9yxLKXQ@mail.gmail.com>
References: <201201051719.01192.GNUtoo@no-log.org>
	<CALrs_3ia=C1OzHWJLwgUO7bspYXxw4CFYJuWJm5BUNj9yxLKXQ@mail.gmail.com>
Message-ID: <201201092011.33741.GNUtoo@no-log.org>

Thanks a lot, I will try to port my mainboard to AGESA.

I guess that mixing AGESA and non-AGESA won't work and that I should fully 
port it to AGESA to get something working...(for me it resulted in many many 
compilation errors)

The supermicro h8qgi mainboard has AGESA for the 10h Family(and that compiles 
unlike what I tried to do, so I'll start from there)...

I will also read the "A short introduction to firmware on the x86 platform"

Denis.


From gerrit at coreboot.org  Mon Jan  9 20:33:13 2012
From: gerrit at coreboot.org (Nils Jacobs (njacobs8@adsltotaal.nl))
Date: Mon, 9 Jan 2012 20:33:13 +0100
Subject: [coreboot] New patch to review for coreboot: bf764d6 Fix Geode GX2
	+ LX caching for tiny bootblock.
References: <If681a33deb7df752b37c6a8a20482d3c374af936+0@gerrit.coreboot.org>
Message-ID: <If681a33deb7df752b37c6a8a20482d3c374af936+1@gerrit.coreboot.org>

Nils Jacobs (njacobs8 at adsltotaal.nl) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/528

-gerrit

commit bf764d6ac76f1bca9da890af81ff5783d27c8c41
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Mon Jan 9 20:27:07 2012 +0100

    Fix Geode GX2 + LX caching for tiny bootblock.
    
    Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>
---
 src/cpu/amd/model_lx/msrinit.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 9c6e98e..1118250 100644
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -22,10 +22,10 @@
 
 static const msrinit_t msr_table[] =
 {
-	{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
+	{CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
 								   * Rom Properties: Write Serialize, WriteProtect.
 								   * RomBase: 0xFFFC0
-								   * SysTop to RomBase Properties: Write Serialize, Cache Disable.
+								   * SysTop to RomBase Properties: Write Back.
 								   * SysTop: 0x000A0
 								   * System Memory Properties:  (Write Back) */
 	{CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */


From bluckau at sgi.com  Mon Jan  9 21:33:49 2012
From: bluckau at sgi.com (Brian Luckau)
Date: Mon, 9 Jan 2012 20:33:49 +0000
Subject: [coreboot] Extracting an image created with mkelfImage
Message-ID: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C3FE@P-EXMB1-DC21.corp.sgi.com>

Hello,

I have an elf netowrk bootable image for linux that was created with mkelfImage.  How can I extract the file to view its contents (which kernel modules were included in the file, etc. )

Thanks,
Brian Luckau


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From peter at stuge.se  Mon Jan  9 22:30:05 2012
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 Jan 2012 22:30:05 +0100
Subject: [coreboot] Extracting an image created with mkelfImage
In-Reply-To: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C3FE@P-EXMB1-DC21.corp.sgi.com>
References: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C3FE@P-EXMB1-DC21.corp.sgi.com>
Message-ID: <20120109213005.3503.qmail@stuge.se>

Hi Brian,

Brian Luckau wrote:
> I have an elf netowrk bootable image for linux that was created
> with mkelfImage.  How can I extract the file to view its contents
> (which kernel modules were included in the file, etc. )

The image may or may not include initrd, if yes it will quite likely
be compressed. What does readelf and/or objdump say about the file?

There's no pre-made tool for taking apart those ELF images. You can
of course always peruse the mkelfImage source code to find out all
details.

http://www.coreboot.org/Mkelfimage
svn co svn://coreboot.org/coreboot/trunk/util/mkelfImage


//Peter


From peter at stuge.se  Mon Jan  9 23:15:00 2012
From: peter at stuge.se (Peter Stuge)
Date: Mon, 9 Jan 2012 23:15:00 +0100
Subject: [coreboot] Extracting an image created with mkelfImage
In-Reply-To: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C472@P-EXMB1-DC21.corp.sgi.com>
References: <20120109213005.3503.qmail@stuge.se>
	<B4EE0490205BD44F8BD3F7BE2E8E0D760613C472@P-EXMB1-DC21.corp.sgi.com>
Message-ID: <20120109221500.9510.qmail@stuge.se>

Brian Luckau wrote:
> root at admin cache]# readelf -a Compute.ebi 
..
> Program Headers:
>   Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
>   NOTE           0x0000d4 0x00000000 0x00000000 0x000a4 0x000a4 RWE 0
>   LOAD           0x000178 0x00010000 0x00010000 0x01288 0x05524 RWE 0
>   LOAD           0x001400 0x00020000 0x00020000 0x00000 0x01070 RWE 0
>   LOAD           0x001400 0x00100000 0x00100000 0x20029c 0x700000 RWE 0

The above looks like the kernel.


>   LOAD           0x20169c 0x02800000 0x02800000 0x7dbdc6 0x7dbdc6 RWE 0

And this would be the initrd.

Could perhaps extract as such:

dd if=Compute.ebi of=Compute-kernel bs=1 skip=$[0x1400] count=$[0x20029c]
dd if=Compute.ebi of=Compute-initrd bs=1 skip=$[0x20169c] count=$[0x7dbdc6]

Run file on the initrd to find out if it is compressed, but since
it's 8 MB I guess it might be uncompressed.

Depending on the format of the initrd you would proceed perhaps by
mounting it through the loopback device, or if it's a more modern
kernel and actually initramfs instead of initrd then you would use
cpio to unpack.


//Peter


From bluckau at sgi.com  Mon Jan  9 23:00:42 2012
From: bluckau at sgi.com (Brian Luckau)
Date: Mon, 9 Jan 2012 22:00:42 +0000
Subject: [coreboot] Extracting an image created with mkelfImage
In-Reply-To: <20120109213005.3503.qmail@stuge.se>
References: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C3FE@P-EXMB1-DC21.corp.sgi.com>,
	<20120109213005.3503.qmail@stuge.se>
Message-ID: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C472@P-EXMB1-DC21.corp.sgi.com>

Hi,

I'm not sure if I'm using the correct paramters but here is some of the information you requested.

# objdump -x -s -D Compute.ebi 

Compute.ebi:     file format elf32-i386
Compute.ebi
architecture: i386, flags 0x00000102:
EXEC_P, D_PAGED
start address 0x00010000

Program Header:
    NOTE off    0x000000d4 vaddr 0x00000000 paddr 0x00000000 align 2**0
         filesz 0x000000a4 memsz 0x000000a4 flags rwx
    LOAD off    0x00000178 vaddr 0x00010000 paddr 0x00010000 align 2**0
         filesz 0x00001288 memsz 0x00005524 flags rwx
    LOAD off    0x00001400 vaddr 0x00020000 paddr 0x00020000 align 2**0
         filesz 0x00000000 memsz 0x00001070 flags rwx
    LOAD off    0x00001400 vaddr 0x00100000 paddr 0x00100000 align 2**0
         filesz 0x0020029c memsz 0x00700000 flags rwx
    LOAD off    0x0020169c vaddr 0x02800000 paddr 0x02800000 align 2**0
         filesz 0x007dbdc6 memsz 0x007dbdc6 flags rwx

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
SYMBOL TABLE:
no symbols

root at admin cache]# readelf -a Compute.ebi 
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00 
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              EXEC (Executable file)
  Machine:                           Intel 80386
  Version:                           0x1
  Entry point address:               0x10000
  Start of program headers:          52 (bytes into file)
  Start of section headers:          0 (bytes into file)
  Flags:                             0x0
  Size of this header:               52 (bytes)
  Size of program headers:           32 (bytes)
  Number of program headers:         5
  Size of section headers:           0 (bytes)
  Number of section headers:         0
  Section header string table index: 0

There are no sections in this file.

There are no sections in this file.

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  NOTE           0x0000d4 0x00000000 0x00000000 0x000a4 0x000a4 RWE 0
  LOAD           0x000178 0x00010000 0x00010000 0x01288 0x05524 RWE 0
  LOAD           0x001400 0x00020000 0x00020000 0x00000 0x01070 RWE 0
  LOAD           0x001400 0x00100000 0x00100000 0x20029c 0x700000 RWE 0
  LOAD           0x20169c 0x02800000 0x02800000 0x7dbdc6 0x7dbdc6 RWE 0

There is no dynamic section in this file.

There are no relocations in this file.

There are no unwind sections in this file.

No version information found in this file.
__________________________
From: coreboot-bounces at coreboot.org [coreboot-bounces at coreboot.org] on behalf of Peter Stuge [peter at stuge.se]
Sent: Monday, January 09, 2012 2:30 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] Extracting an image created with mkelfImage

Hi Brian,

Brian Luckau wrote:
> I have an elf netowrk bootable image for linux that was created
> with mkelfImage.  How can I extract the file to view its contents
> (which kernel modules were included in the file, etc. )

The image may or may not include initrd, if yes it will quite likely
be compressed. What does readelf and/or objdump say about the file?

There's no pre-made tool for taking apart those ELF images. You can
of course always peruse the mkelfImage source code to find out all
details.

http://www.coreboot.org/Mkelfimage
svn co svn://coreboot.org/coreboot/trunk/util/mkelfImage


//Peter

--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot


From ybernd at googlemail.com  Mon Jan  9 23:20:27 2012
From: ybernd at googlemail.com (Bernd Dreyer Gmail)
Date: Mon, 9 Jan 2012 23:20:27 +0100
Subject: [coreboot] Replace the BIOS of a Acer laptop with the coreboot
	software
Message-ID: <53074CBB4672450696184C91B05AF0DB@xpp>

Ladies and Gentlemen!

Attached to this message you find a listing from the hardware of my Laptop.
Please let me know something about the possibility to replace the BIOS of the laptop with the coreboot software.

Best Regards

  
     
            CPU-Z   
                
            Binaries   
            CPU-Z version 1.59 
                
            Processors   
            Number of processors 1 
            Number of threads 2 
                
            APICs   
            Processor 0  
                 -- Core 0  
                     -- Thread 0 0 
                     -- Thread 1 1 
                
            Processors Information   
            Processor 1 ID = 0 
                 Number of cores 1 (max 1) 
                 Number of threads 2 (max 2) 
                 Name Intel Pentium 4 
                 Codename Northwood 
                 Specification Intel(R) Pentium(R) 4 CPU 3.00GHz 
                 Package (platform ID) Socket 478 mPGA (0x2) 
                 CPUID F.2.9 
                 Extended CPUID F.2 
                 Brand ID 9 
                 Core Stepping D1 
                 Technology 0.13 um 
                 Core Speed 3000.0 MHz 
                 Multiplier x FSB 15.0 x 200.0 MHz 
                 Rated Bus speed 800.0 MHz 
                 Stock frequency 3000 MHz 
                 Instructions sets MMX, SSE, SSE2 
                 L1 Data cache 8 KBytes, 4-way set associative, 64-byte line size 
                 Trace cache 12 Kuops, 8-way set associative 
                 L2 cache 512 KBytes, 8-way set associative, 64-byte line size 
                 FID/VID Control no 
                
                
                
            Thread dumps   
            CPU Thread 0  
                 APIC ID 0 
                 Topology Processor ID 0, Core ID 0, Thread ID 0 
                 Type 01001003h 
                 Max CPUID level 00000002h 
                 Max CPUID ext. level 80000004h 
                 Cache descriptor Level 2, U, 512 KB, 2 thread(s) 
                 Cache descriptor Level 1, T, 12 KB, 2 thread(s) 
                 Cache descriptor Level 1, D, 8 KB, 2 thread(s) 
                
                 CPUID  
                 0x00000000 0x00000002 0x756E6547 0x6C65746E 0x49656E69 
                 0x00000001 0x00000F29 0x00020809 0x00004400 0xBFEBFBFF 
                 0x00000002 0x665B5001 0x00000000 0x00000000 0x007B7040 
                 0x80000000 0x80000004 0x00000000 0x00000000 0x00000000 
                 0x80000001 0x00000000 0x00000000 0x00000000 0x00000000 
                 0x80000002 0x20202020 0x20202020 0x20202020 0x6E492020 
                 0x80000003 0x286C6574 0x50202952 0x69746E65 0x52286D75 
                 0x80000004 0x20342029 0x20555043 0x30302E33 0x007A4847 
                
                 MSR 0x0000001B 0x00000000 0xFEE00900 
                 MSR 0x00000017 0x000A0000 0x00000000 
                 MSR 0x0000002C 0x00000000 0x0F12000F 
                 MSR 0x000001A0 0x00000000 0x000004C9 
                
            CPU Thread 1  
                 APIC ID 1 
                 Topology Processor ID 0, Core ID 0, Thread ID 1 
                 Type 01001003h 
                 Max CPUID level 00000002h 
                 Max CPUID ext. level 80000004h 
                 Cache descriptor Level 2, U, 512 KB, 2 thread(s) 
                 Cache descriptor Level 1, T, 12 KB, 2 thread(s) 
                 Cache descriptor Level 1, D, 8 KB, 2 thread(s) 
                
                 CPUID  
                 0x00000000 0x00000002 0x756E6547 0x6C65746E 0x49656E69 
                 0x00000001 0x00000F29 0x01020809 0x00004400 0xBFEBFBFF 
                 0x00000002 0x665B5001 0x00000000 0x00000000 0x007B7040 
                 0x80000000 0x80000004 0x00000000 0x00000000 0x00000000 
                 0x80000001 0x00000000 0x00000000 0x00000000 0x00000000 
                 0x80000002 0x20202020 0x20202020 0x20202020 0x6E492020 
                 0x80000003 0x286C6574 0x50202952 0x69746E65 0x52286D75 
                 0x80000004 0x20342029 0x20555043 0x30302E33 0x007A4847 
                
                 MSR 0x0000001B 0x00000000 0xFEE00800 
                 MSR 0x00000017 0x000A0000 0x00000000 
                 MSR 0x0000002C 0x00000000 0x0F12000F 
                 MSR 0x000001A0 0x00000000 0x000004C9 
                
                
                
            Chipset   
            Northbridge ATI ID5833 rev. 02 
            Southbridge ATI SB200 rev. 00 
            Graphic Interface AGP 
            AGP Revision 3.0 
            AGP Transfer Rate 8x 
            AGP SBA supported, enabled 
            Memory Type  
            Memory Size 1536 MBytes 
                
            Memory SPD   
            DIMM # 1 
                 SMBus address 0x50 
                 Memory type DDR 
                 Manufacturer (ID) MOSEL (4000000000000000) 
                 Size 512 MBytes 
                 Max bandwidth PC2700 (166 MHz) 
                 Part number V826764B24SBIW-C0 
                 Serial number 4F222000 
                 Manufacturing date Week 32/Year 06 
                 Number of banks 2 
                 Data width 64 bits 
                 Correction None 
                 Registered no 
                 Buffered no 
                 Nominal Voltage 2.50 Volts 
                 EPP no 
                 XMP no 
            JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency 
                 JEDEC #1 2.5-3-3-7-n.a. @ 166 MHz 
                
            DIMM # 2 
                 SMBus address 0x51 
                 Memory type DDR 
                 Manufacturer (ID) (7F7F7F7F7F5D0000) 
                 Size 1024 MBytes 
                 Max bandwidth PC2700 (166 MHz) 
                 Part number  
                 Manufacturing date Week 82/Year 07 
                 Number of banks 2 
                 Data width 64 bits 
                 Correction None 
                 Registered no 
                 Buffered no 
                 Nominal Voltage 2.50 Volts 
                 EPP no 
                 XMP no 
            JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency 
                 JEDEC #1 2.0-3-3-6-n.a. @ 133 MHz 
                 JEDEC #2 2.5-3-3-7-n.a. @ 166 MHz 
                
            DIMM # 1 
            SPD registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 80 08 07 0D 0A 02 40 00 04 60 70 00 82 10 00 01  
                 10 0E 04 08 01 02 20 C0 00 00 00 00 48 30 48 2A 40  
                 20 75 75 45 45 00 00 00 00 00 3C 48 30 2D 55 00 01  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 31  
                 40 40 00 00 00 00 00 00 00 02 56 38 32 36 37 36 34  
                 50 42 32 34 53 42 49 57 2D 43 30 00 00 00 06 20 4F  
                 60 22 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 50 34 53 38 30 30 2D 31 35 31 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 05 00 00 00 00 00 00 00  
                
            DIMM # 2 
            SPD registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 01  
                 10 0E 04 0C 01 02 20 00 75 75 00 00 48 30 48 2A 80  
                 20 75 75 45 45 00 00 00 00 00 3C 48 30 28 55 00 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 82  
                 40 7F 7F 7F 7F 7F 5D 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 07 52 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
                
            Monitoring   
            Mainboard Model Aspire 1660 (0x00000351 - 0xF6044E00) 
                
            LPCIO   
            LPCIO Vendor NS 
            LPCIO Vendor ID 0xFF02 
            LPCIO Chip ID 0xEA 
            LPCIO Revision ID 0x3 
            Config Mode I/O address 0x2E 
            Config Mode LDN 0x9 
            Config Mode registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 00 00 00 00 00 00 00 09 00 00 00 00 00 00 00 00  
                 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 EA 11 00 00 29 80 04 03 00 1C 37 00 00 00 00 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 04 04 00 00 00 00 00 00 00 00 00 00  
                
            Hardware Monitors   
            Hardware monitor ACPI 
                 Temperature 0 62?C (143?F) [0xD18] (THRC) 
                 Temperature 1 58?C (136?F) [0xCF0] (THRS) 
                
            Hardware monitor Battery 
                
                
            PCI Devices   
            Description Host Bridge 
            Location bus 0 (0x00), device 0 (0x00), function 0 (0x00) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x5833 
                 Revision ID 0x02 
                 PI 0x00 
                 SubClass 0x00 
                 BaseClass 0x06 
                 Cache Line 0x00 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (memory) 0xDC000000 
                 Address 1 (memory) 0xD8000000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x00 
                 Int. Pin 0x00 
            PCI capability  
                 Caps class AGP 
                 Caps offset 0xA0 
                 Caps version 3.0 
                 Caps status enabled 
                 Transfer rate 8x (max 8x) 
                 Queue length 1 (max 32) 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 33 58 06 01 30 22 02 00 00 06 00 40 00 00  
                 10 08 00 00 DC 00 00 00 D8 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 A0 00 00 00 00 00 00 00 00 00 00 00  
                 40 00 00 11 64 08 02 00 00 00 00 00 00 04 2D 00 00  
                 50 25 10 52 00 81 35 00 C0 00 10 11 11 00 30 11 11  
                 60 AD 0C 00 00 2D 26 E2 7E 00 0A 25 00 27 00 09 06  
                 70 E1 09 60 30 84 84 84 84 18 18 05 2E 80 07 30 C0  
                 80 00 00 00 00 92 10 83 00 30 00 00 00 01 24 00 D0  
                 90 00 00 00 60 10 0F 10 0F 00 00 08 00 00 00 00 00  
                 A0 02 00 30 00 1B 02 00 1F 12 03 00 00 00 00 00 00  
                 B0 00 00 00 00 30 0F 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 02 FF 0F 00 2B FF 4F 00 6A 00 60 50 00 00 00 00  
                 E0 00 00 00 00 00 00 40 00 18 00 00 00 00 14 07 52  
                 F0 1F 00 09 00 00 00 00 00 03 00 00 00 00 00 02 00  
                
            Description PCI to PCI Bridge 
            Location bus 0 (0x00), device 1 (0x01), function 0 (0x00) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x5838 
                 Revision ID 0x00 
                 PI 0x00 
                 SubClass 0x04 
                 BaseClass 0x06 
                 Cache Line 0x00 
                 Latency 0x63 
                 Header 0x01 
            PCI header  
                 Primary bus 0x00 
                 Secondary bus 0x01 
                 Int. Line 0xFF 
                 Int. Pin 0x00 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 38 58 07 00 20 02 00 00 04 06 00 63 01 00  
                 10 00 00 00 00 00 00 00 00 00 01 01 44 91 91 20 22  
                 20 10 D8 10 D8 00 E0 F0 E7 00 00 00 00 25 10 38 58  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 FF 00 0C 00  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 25 10 38 58  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 80 00 C7 FF FF 00 00 00 FF FF FF DF FF FF FF FF  
                 70 00 00 00 00 11 0E 10 0F 16 06 18 08 7D 03 06 60  
                 80 FF F0 00 00 FF 00 00 00 00 00 00 00 FF FF 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 10 36 16 00 3C 0F 04 3E 00 00 00 00 20 0A B1 16  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description USB Controller (OHCI) 
            Location bus 0 (0x00), device 19 (0x13), function 0 (0x00) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4347 
                 Revision ID 0x01 
                 PI 0x10 
                 SubClass 0x03 
                 BaseClass 0x0C 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x80 
            PCI header  
                 Address 0 (memory) 0xD8001000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x13 
                 Int. Pin 0x01 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 47 43 17 00 A0 02 01 10 03 0C 08 40 80 00  
                 10 00 10 00 D8 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 13 01 00 00  
                 40 80 FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 08  
                 E0 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description USB Controller (OHCI) 
            Location bus 0 (0x00), device 19 (0x13), function 1 (0x01) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4348 
                 Revision ID 0x01 
                 PI 0x10 
                 SubClass 0x03 
                 BaseClass 0x0C 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (memory) 0xD8002000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x13 
                 Int. Pin 0x01 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 48 43 17 00 A0 02 01 10 03 0C 08 40 00 00  
                 10 00 20 00 D8 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 13 01 00 00  
                 40 80 FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 08  
                 E0 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description USB 2.0 Controller (EHCI) 
            Location bus 0 (0x00), device 19 (0x13), function 2 (0x02) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4345 
                 Revision ID 0x01 
                 PI 0x20 
                 SubClass 0x03 
                 BaseClass 0x0C 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (memory) 0xD8003000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x13 
                 Int. Pin 0x01 
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0xDC 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 45 43 17 00 B0 02 01 20 03 0C 08 40 00 00  
                 10 00 30 00 D8 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 DC 00 00 00 00 00 00 00 13 01 00 00  
                 40 80 FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 20 20 00 00 00 20 00 00 00 20 00 00 00 20 00 00  
                 70 00 20 00 00 00 20 00 00 00 20 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 01 00 00 00 00 00 00 C0 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 7E  
                 E0 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description SMBus Controller 
            Location bus 0 (0x00), device 20 (0x14), function 0 (0x00) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4353 
                 Revision ID 0x18 
                 PI 0x00 
                 SubClass 0x05 
                 BaseClass 0x0C 
                 Cache Line 0x00 
                 Latency 0x00 
                 Header 0x80 
            PCI header  
                 Address 0 (port) 0x00008060 
                 Address 1 (memory) 0xD8004000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x00 
                 Int. Pin 0x00 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 53 43 03 00 20 02 18 00 05 0C 00 00 80 00  
                 10 61 80 00 00 00 40 00 D8 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 40 D4 33 00 00 00 00 00 00 0F FF 46 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 01 00 00 00 9F BB 9E 82 00 90 00 00 00 00 00 00  
                 70 00 00 00 00 08 00 C0 FE FF 4E 00 00 00 00 00 00  
                 80 0F 0E 00 00 00 00 00 00 00 00 00 00 8C 00 00 80  
                 90 61 80 00 00 42 10 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 FF FF FF FF 00 00 10 3F 3F 00 C0 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description IDE Controller 
            Location bus 0 (0x00), device 20 (0x14), function 1 (0x01) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4349 
                 Revision ID 0x00 
                 PI 0x8A 
                 SubClass 0x01 
                 BaseClass 0x01 
                 Cache Line 0x00 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (port) 0x000001F0 
                 Address 1 (port) 0x000003F4 
                 Address 2 (port) 0x00000170 
                 Address 3 (port) 0x00000374 
                 Address 4 (port) 0x00008070 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0xFF 
                 Int. Pin 0x01 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 49 43 05 00 00 0A 00 8A 01 01 00 40 00 00  
                 10 F1 01 00 00 F5 03 00 00 71 01 00 00 75 03 00 00  
                 20 71 80 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 FF 01 00 00  
                 40 99 20 99 20 FF FF FF FF 00 00 04 04 00 00 00 00  
                 50 00 00 00 00 05 00 05 02 00 00 00 00 00 00 00 00  
                 60 00 00 03 00 00 6C 1E 6C 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description PCI to ISA Bridge 
            Location bus 0 (0x00), device 20 (0x14), function 3 (0x03) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x434C 
                 Revision ID 0x00 
                 PI 0x00 
                 SubClass 0x01 
                 BaseClass 0x06 
                 Cache Line 0x00 
                 Latency 0x00 
                 Header 0x80 
            PCI header  
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x00 
                 Int. Pin 0x00 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 4C 43 0F 00 20 02 00 00 01 06 00 00 80 00  
                 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 40 04 00 00 00 FF FF 40 FF 87 FF 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 06 00 00 0E 00 0F 00 B8 FF FF FF  
                 70 67 45 23 01 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description PCI to PCI Bridge 
            Location bus 0 (0x00), device 20 (0x14), function 4 (0x04) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4342 
                 Revision ID 0x00 
                 PI 0x01 
                 SubClass 0x04 
                 BaseClass 0x06 
                 Cache Line 0x00 
                 Latency 0x40 
                 Header 0x81 
            PCI header  
                 Primary bus 0x00 
                 Secondary bus 0x02 
                 Int. Line 0x00 
                 Int. Pin 0x00 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 42 43 07 00 A0 02 00 01 04 06 00 40 81 00  
                 10 00 00 00 00 00 00 00 00 00 02 04 44 A1 A1 80 22  
                 20 20 D8 20 D8 F0 FF 00 00 00 00 00 00 00 00 00 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 40 24 00 3C FF 00 00 00 00 00 03 0F E0 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 06  
                 E0 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description Audio device 
            Location bus 0 (0x00), device 20 (0x14), function 5 (0x05) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4341 
                 Revision ID 0x00 
                 PI 0x00 
                 SubClass 0x01 
                 BaseClass 0x04 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x80 
            PCI header  
                 Address 0 (memory) 0xD8004400 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x11 
                 Int. Pin 0x02 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 41 43 17 00 20 04 00 00 01 04 08 40 80 00  
                 10 00 44 00 D8 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 11 02 02 00  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description Modem 
            Location bus 0 (0x00), device 20 (0x14), function 6 (0x06) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x434D 
                 Revision ID 0x01 
                 PI 0x00 
                 SubClass 0x03 
                 BaseClass 0x07 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x80 
            PCI header  
                 Address 0 (memory) 0xD8004800 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x11 
                 Int. Pin 0x02 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 4D 43 17 00 20 04 01 00 03 07 08 40 80 00  
                 10 00 48 00 D8 00 00 00 00 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 00 00 00 00 00 00 00 00 11 02 02 00  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description VGA Controller 
            Location bus 1 (0x01), device 5 (0x05), function 0 (0x00) 
            Common header  
                 Vendor ID 0x1002 
                 Model ID 0x4E50 
                 Revision ID 0x00 
                 PI 0x00 
                 SubClass 0x00 
                 BaseClass 0x03 
                 Cache Line 0x08 
                 Latency 0xFF 
                 Header 0x00 
            PCI header  
                 Address 0 (memory) 0xE0000000 
                 Address 1 (port) 0x00009000 
                 Address 2 (memory) 0xD8100000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0053 
                 Int. Line 0x13 
                 Int. Pin 0x01 
            PCI capability  
                 Caps class AGP 
                 Caps offset 0x58 
                 Caps version 3.0 
                 Caps status enabled 
                 Transfer rate 8x (max 8x) 
                 Queue length 1 (max 256) 
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0x50 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 02 10 50 4E 07 02 B0 02 00 00 00 03 08 FF 00 00  
                 10 08 00 00 E0 01 90 00 00 00 00 10 D8 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 53 00  
                 30 00 00 00 00 58 00 00 00 00 00 00 00 13 01 08 00  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 25 10 53 00  
                 50 01 00 02 06 00 00 00 00 02 50 30 00 1B 02 00 FF  
                 60 12 03 00 1F 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description OHCI FireWire Controller 
            Location bus 2 (0x02), device 3 (0x03), function 0 (0x00) 
            Common header  
                 Vendor ID 0x104C 
                 Model ID 0x8023 
                 Revision ID 0x00 
                 PI 0x10 
                 SubClass 0x00 
                 BaseClass 0x0C 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (memory) 0xD8204000 
                 Address 1 (memory) 0xD8200000 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x10 
                 Int. Pin 0x01 
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0x44 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 4C 10 23 80 16 00 10 02 00 10 00 0C 08 40 00 00  
                 10 00 40 20 D8 00 00 20 D8 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 44 00 00 00 00 00 00 00 10 01 02 04  
                 40 00 00 00 00 01 00 02 7E 00 80 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00  
                 F0 00 00 00 00 00 10 00 00 25 10 52 00 00 00 00 00  
                
            Description PCI to CardBus Bridge 
            Location bus 2 (0x02), device 4 (0x04), function 0 (0x00) 
            Common header  
                 Vendor ID 0x104C 
                 Model ID 0xAC55 
                 Revision ID 0x01 
                 PI 0x00 
                 SubClass 0x07 
                 BaseClass 0x06 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x82 
            PCI header  
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0xA0 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 4C 10 55 AC 07 00 10 02 01 00 07 06 08 40 82 00  
                 10 00 F0 BF FE A0 00 00 02 02 03 03 40 00 E0 BF FE  
                 20 00 E0 BF FE 00 E0 BF FA 00 D0 BF FE 00 FE 00 00  
                 30 FC FE 00 00 00 FD 00 00 FC FD 00 00 10 01 C0 00  
                 40 25 10 52 00 01 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 61 90 44 28 00 00 00 00 00 00 00 00 22 10 00 01  
                 90 C0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 01 00 12 FE 00 00 C0 00 01 00 00 00 1F 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description PCI to CardBus Bridge 
            Location bus 2 (0x02), device 4 (0x04), function 1 (0x01) 
            Common header  
                 Vendor ID 0x104C 
                 Model ID 0xAC55 
                 Revision ID 0x01 
                 PI 0x00 
                 SubClass 0x07 
                 BaseClass 0x06 
                 Cache Line 0x08 
                 Latency 0x40 
                 Header 0x82 
            PCI header  
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0xA0 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 4C 10 55 AC 07 00 10 02 01 00 07 06 08 40 82 00  
                 10 00 D0 BF FA A0 00 00 02 02 04 04 40 00 C0 BF FA  
                 20 00 C0 BF FA 00 C0 BF F6 00 B0 BF FA 00 FC 00 00  
                 30 FC FC 00 00 00 FA 00 00 FC FA 00 00 10 01 C0 00  
                 40 25 10 52 00 01 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 61 90 44 28 00 00 00 00 00 00 00 00 22 10 00 01  
                 90 C0 22 64 60 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 01 00 12 FE 00 00 C0 00 01 00 00 00 1F 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description Ethernet Controller 
            Location bus 2 (0x02), device 5 (0x05), function 0 (0x00) 
            Common header  
                 Vendor ID 0x17FE 
                 Model ID 0x2220 
                 Revision ID 0x00 
                 PI 0x00 
                 SubClass 0x00 
                 BaseClass 0x02 
                 Cache Line 0x00 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (port) 0x0000A400 
                 Address 1 (memory) 0xD8205000 
                 Address 2 (memory) 0xD8204800 
                 Subvendor ID 0x1468 
                 Subsystem ID 0x0305 
                 Int. Line 0x12 
                 Int. Pin 0x01 
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0x40 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 FE 17 20 22 1F 00 90 82 00 00 00 02 00 40 00 00  
                 10 01 A4 00 00 00 50 20 D8 00 48 20 D8 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 03 06 00 00 68 14 05 03  
                 30 00 00 00 00 40 00 00 00 00 00 00 00 12 01 20 20  
                 40 01 00 22 04 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
            Description Ethernet Controller 
            Location bus 2 (0x02), device 10 (0x0A), function 0 (0x00) 
            Common header  
                 Vendor ID 0x10EC 
                 Model ID 0x8139 
                 Revision ID 0x10 
                 PI 0x00 
                 SubClass 0x00 
                 BaseClass 0x02 
                 Cache Line 0x00 
                 Latency 0x40 
                 Header 0x00 
            PCI header  
                 Address 0 (port) 0x0000A000 
                 Address 1 (memory) 0xD8205400 
                 Subvendor ID 0x1025 
                 Subsystem ID 0x0052 
                 Int. Line 0x10 
                 Int. Pin 0x01 
            PCI capability  
                 Caps class Power Management 
                 Caps offset 0x50 
                 Caps version 1.1 
            PCI registers  
                  00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F  
                 00 EC 10 39 81 05 00 90 02 10 00 00 02 00 40 00 00  
                 10 01 A0 00 00 00 54 20 D8 00 00 00 00 00 00 00 00  
                 20 00 00 00 00 00 00 00 00 00 00 00 00 25 10 52 00  
                 30 00 00 00 00 50 00 00 00 00 00 00 00 10 01 20 40  
                 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 50 01 00 C2 F7 00 00 00 00 00 00 00 00 00 00 00 00  
                 60 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 A0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 B0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 C0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 D0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 E0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                 F0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  
                
                
            DMI   
            DMI BIOS  
                 vendor Phoenix Technologies LTD 
                 version V1.11 
                 date 05/27/04 
                
            DMI System Information  
                 manufacturer Acer 
                 product Aspire 1660 
                 version 0100 
                 serial LXA300505742700B17M000 
                 UUID {60C56C3C-00CA-D811-B4F7-D768E9E8C320} 
                
            DMI Baseboard  
                 vendor Acer 
                 model Aspire 1660 
                 revision Rev 
                 serial LXA300505742700B17M000 
                
            DMI System Enclosure  
                 manufacturer Acer 
                 chassis type 1X 
                 chassis serial None 
                
            DMI Processor  
                 manufacturer GenuineIntel 
                 model Intel(R) Pentium(R) 4 CPU 3.00GHz 
                 clock speed 3000.0 MHz 
                
            DMI Memory Controller  
                 correction unknown 
                 Max module size 128 MBytes 
                
            DMI Memory Module  
                 designation M4 
                
            DMI Memory Module  
                 designation M3 
                
            DMI Memory Module  
                 designation M1 
                 size 512 MBytes (single bank) 
                
            DMI Memory Module  
                 designation M2 
                 size 1024 MBytes (single bank) 
                
            DMI Extension Slot  
                 designation PCI Slot J11 
                 type PCI 
                 width 32 bits 
                
            DMI Extension Slot  
                 designation PCI Slot J12 
                 type PCI 
                 width 32 bits 
                
            DMI OEM Strings  
                 string[0] 1 
                 string[1] 1234567890 
                
            DMI Physical Memory Array  
                 location Motherboard 
                 usage System Memory 
                 correction None 
                 max capacity 1024 MBytes 
                 max# of devices 2 
                
            DMI Memory Device  
                 designation U5 
                 format DIMM 
                 type DRAM 
                
            DMI Memory Device  
                 designation U6 
                 format DIMM 
                 type DRAM 
                
            DMI Memory Device  
                 designation U5 
                 format DIMM 
                 type DRAM 
                 total width 32 bits 
                 data width 32 bits 
                 size 512 MBytes 
                
            DMI Memory Device  
                 designation U6 
                 format DIMM 
                 type DRAM 
                 total width 32 bits 
                 data width 32 bits 
                 size 1024 MBytes 
                
                
            Graphics   
            Number of adapters 1 
                
            Graphic APIs   
            API ATI I/O 
                
            Display Adapters   
            Display adapter 0  
                 Name ATI MOBILITY RADEON 9700 Series 
                 Codename RV350 
                 Technology 0.11 um 
                 Memory size 64 MB 
                 GPU ref clock 27000 
                 PCI device bus 1 (0x1), device 5 (0x5), function 0 (0x0) 
                 Vendor ID 0x1002 (0x1025) 
                 Model ID 0x4E50 (0x0053) 
                 Performance Level 0 
                
                
            Software   
            Windows Version Microsoft Windows XP Home Edition Service Pack 3 (Build 2600)  
            DirectX Version 9.0c 
                
            ACPI   
            ACPI Tree  
           _GPE 
           _L01 
           _L06 
           _PR_ 
           CPU0 
           HI0_ 
           HC0_ 
           _PDC 
           CSTR 
           _CST 
           CPU1 
           HI1_ 
           HC1_ 
           _PDC 
           CSTR 
           _CST 
           _SB_ 
           OSTB 
           OSTY 
           [ ] 
           TPOS 
           OSTP 
           SEQL 
           AC__ 
           _HID 
           _PCL 
           _STA 
           ACFG 
           ACP_ 
           _PSR 
           BAT0 
           _HID 
           _PCL 
           BP__ 
           IBP_ 
           PSTA 
           CHAR 
           VTOB 
           BTOV 
           MKWD 
           GBFE 
           PBFE 
           ITOS 
           PBIF 
           PBST 
           UBIF 
           SMBF 
           _STA 
           _BIF 
           _BST 
           IVBI 
           IVBS 
           UPBI 
           UPBS 
           LID0 
           _HID 
           _LID 
           _PRW 
           SLPB 
           _HID 
           _PRW 
           PCI0 
           _HID 
           _ADR 
           _UID 
           _BBN 
           _INI 
           MREG 
           [ ] 
           TOML 
           TOMH 
           TOM_ 
           REGS 
           [ ] 
           SR59 
           SR5A 
           SR5B 
           SR5C 
           SR5D 
           SR5E 
           SR5F 
           RSRC 
           _CRS 
           _PRT 
           BAR1 
           [ ] 
           Z009 
           LPC0 
           _ADR 
           PSMX 
           PIRQ 
           [ ] 
           PIID 
           PIDA 
           [ ] 
           PIR0 
           PIR1 
           PIR2 
           PIR3 
           PIRS 
           IPRS 
           DSPI 
           LNK0 
           _HID 
           _UID 
           _STA 
           _PRS 
           _DIS 
           _CRS 
           _SRS 
           LNK1 
           _HID 
           _UID 
           _STA 
           _PRS 
           _DIS 
           _CRS 
           _SRS 
           LNK2 
           _HID 
           _UID 
           _STA 
           _PRS 
           _DIS 
           _CRS 
           _SRS 
           LNK3 
           _HID 
           _UID 
           _STA 
           _PRS 
           _DIS 
           _CRS 
           _SRS 
           LPCR 
           [ ] 
           CMA0 
           CMA1 
           CMA2 
           CMA3 
           CMA4 
           CMA5 
           CMA6 
           CMA7 
           CMB0 
           CMB1 
           CMB2 
           CMB3 
           CMB4 
           CMB5 
           CMB6 
           CMB7 
           [ ] 
           [ ] 
           [ ] 
           FDD1 
           FDD2 
           [ ] 
           [ ] 
           [ ] 
           [ ] 
           DMAC 
           _HID 
           _CRS 
           MATH 
           _HID 
           _CRS 
           PIC_ 
           _HID 
           _CRS 
           RTC_ 
           _HID 
           _CRS 
           SPKR 
           _HID 
           _CRS 
           TIME 
           _HID 
           _CRS 
           PS2K 
           _HID 
           _CRS 
           PS2M 
           _HID 
           _CID 
           _CRS 
           SYSR 
           _HID 
           _CRS 
           MEM_ 
           _HID 
           MSRC 
           _CRS 
           _STA 
           SMI0 
           [ ] 
           SMIC 
           SMI1 
           [ ] 
           BCMD 
           DID_ 
           INFO 
           [ ] 
           [ ] 
           INF_ 
           EC0_ 
           _HID 
           _GPE 
           NRTY 
           _STA 
           _CRS 
           RAM_ 
           [ ] 
           [ ] 
           SCIC 
           [ ] 
           CMCD 
           DAT1 
           DAT2 
           DAT3 
           [ ] 
           SMPR 
           SMST 
           SMAD 
           SMCM 
           SMD0 
           SMAA 
           [ ] 
           P50_ 
           [ ] 
           P43_ 
           P54_ 
           P55_ 
           [ ] 
           [ ] 
           P54S 
           P55S 
           P50S 
           P43S 
           P54T 
           P55T 
           P50T 
           P43T 
           P60S 
           P61S 
           P62S 
           P63S 
           P64S 
           [ ] 
           P67S 
           P60T 
           [ ] 
           P67T 
           [ ] 
           [ ] 
           P63_ 
           P64_ 
           [ ] 
           P67_ 
           [ ] 
           CTMP 
           [ ] 
           STMP 
           [ ] 
           CTT4 
           CTT5 
           CTT6 
           [ ] 
           STT4 
           STT5 
           STT6 
           [ ] 
           [ ] 
           SMW0 
           [ ] 
           [ ] 
           SMB0 
           ECO1 
           [ ] 
           PX62 
           ECO2 
           [ ] 
           PX66 
           _REG 
           RAMR 
           RAMW 
           COMD 
           SMRD 
           SMWR 
           _Q0A 
           _Q0B 
           _Q0C 
           _Q0D 
           _Q0E 
           _Q10 
           _Q11 
           _Q12 
           _Q50 
           _Q35 
           _Q36 
           _Q51 
           _Q33 
           _Q34 
           _Q2E 
           _Q31 
           _Q32 
           _Q77 
           _Q78 
           _Q79 
           _Q7F 
           SGIO 
           [ ] 
           GDO0 
           GDI0 
           GEE0 
           GES0 
           GDO1 
           GDI1 
           GEE1 
           GES1 
           GDO2 
           GDI2 
           GDO3 
           GDI3 
           N393 
           [ ] 
           INDX 
           DATA 
           MTIO 
           SETD 
           READ 
           WRIT 
           STAT 
           DFIN 
           SLPC 
           FDSK 
           _HID 
           FDMM 
           [ ] 
           [ ] 
           FDCD 
           FDIO 
           [ ] 
           [ ] 
           FDTP 
           [ ] 
           _STA 
           _DIS 
           _CRS 
           _PRS 
           _SRS 
           _PS0 
           _PS3 
           LPT_ 
           _UID 
           FLAG 
           ISNO 
           MECP 
           MLPT 
           MODE 
           _HID 
           _STA 
           _DIS 
           CRSA 
           CRSB 
           _CRS 
           PRSA 
           PRSB 
           _PRS 
           _SRS 
           COMB 
           _UID 
           FLAG 
           MODE 
           _HID 
           _STA 
           _DIS 
           CRSA 
           CRSB 
           _CRS 
           PRSA 
           PRSB 
           _PRS 
           _SRS 
           _PS0 
           _PS3 
           P2P_ 
           _ADR 
           _PRT 
           LANC 
           _ADR 
           _PRW 
           MPCI 
           _ADR 
           CBS0 
           _ADR 
           _STA 
           _S3D 
           _S4D 
           CBS1 
           _ADR 
           _STA 
           _S3D 
           _S4D 
           OHC1 
           _ADR 
           OHC2 
           _ADR 
           EHCI 
           _ADR 
           AUDO 
           _ADR 
           _PRW 
           MODM 
           _ADR 
           _PRW 
           IDE_ 
           _ADR 
           UDMT 
           PIOT 
           PITR 
           MDMT 
           MDTR 
           IDE_ 
           [ ] 
           PPIT 
           SPIT 
           PMDT 
           SMDT 
           PPIC 
           SPIC 
           PPIM 
           SPIM 
           [ ] 
           PUDC 
           SUDC 
           [ ] 
           PUDM 
           SUDM 
           ATPI 
           GETT 
           GTM_ 
           STM_ 
           GTF_ 
           PRID 
           _ADR 
           _GTM 
           _STM 
           P_D0 
           _ADR 
           _GTF 
           P_D1 
           _ADR 
           _GTF 
           SECD 
           _ADR 
           _GTM 
           _STM 
           S_D0 
           _ADR 
           _GTF 
           S_D1 
           _ADR 
           _GTF 
           AGP_ 
           _ADR 
           _PRT 
           VGA_ 
           _ADR 
           SWIT 
           CRTA 
           LCDA 
           TVAF 
           TOGF 
           OSF_ 
           _INI 
           _DOS 
           _DOD 
           CRT_ 
           _ADR 
           _DCS 
           _DGS 
           _DSS 
           LCD_ 
           _ADR 
           _DCS 
           _DGS 
           _DSS 
           TVO_ 
           _ADR 
           _DCS 
           _DSS 
           _DDC 
           DDC0 
           DDC3 
           DDC4 
           DDC5 
           _SI_ 
           _SST 
           _TZ_ 
           T4TH 
           T4FG 
           SBFG 
           CBFG 
           TBSE 
           THRC 
           _TMP 
           _CRT 
           _PSL 
           _PSV 
           _TC1 
           _TC2 
           _TSP 
           THRS 
           _TMP 
           _CRT 
           _PSL 
           _PSV 
           _TC1 
           _TC2 
           _TSP 
           _REV 
           _OS_ 
           _OSI 
           _GL_ 
           Z000 
           Z001 
           Z002 
           Z003 
           Z004 
           Z005 
           Z006 
           Z007 
           Z008 
           DEBG 
           [ ] 
           DBGP 
           HTTX 
           ECON 
           LIDF 
           LIDS 
           MUTX 
           MIOT 
           MSMI 
           PHSR 
           _S0_ 
           _S3_ 
           _S4_ 
           _S5_ 
           _PTS 
           _WAK 
           FWSO 
           _PSC 
           _PS0 
           _PS3 
           GPIC 
           _PIC 
           SSDT 
           CFGD 
           PWRS 
           PDC0 
           PDC1 
     
 

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From gerrit at coreboot.org  Mon Jan  9 23:50:28 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 9 Jan 2012 23:50:28 +0100
Subject: [coreboot] Patch merged into coreboot/master: bf764d6 Fix Geode GX2
	+ LX caching for tiny bootblock.
References: <If681a33deb7df752b37c6a8a20482d3c374af936+0@gerrit.coreboot.org>
Message-ID: <E1RkO2u-00061v-5t@ra.coresystems.de>

the following patch was just integrated into master:
commit bf764d6ac76f1bca9da890af81ff5783d27c8c41
Author: Nils Jacobs <njacobs8 at adsltotaal.nl>
Date:   Mon Jan 9 20:27:07 2012 +0100

    Fix Geode GX2 + LX caching for tiny bootblock.
    
    Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
    Signed-off-by: Nils Jacobs <njacobs8 at adsltotaal.nl>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Jan  9 21:05:27 2012, giving +2
Build-Tested: build bot (Jenkins) at Mon Jan  9 20:57:54 2012, giving +1
See http://review.coreboot.org/528 for details.

-gerrit


From gerrit at coreboot.org  Mon Jan  9 23:55:27 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 9 Jan 2012 23:55:27 +0100
Subject: [coreboot] Patch merged into coreboot/master: c7d7cdb Un-perl
	commit-msg hook
References: <I67adfe1ec43c898735d4bae4819ceb53e83c303b+0@gerrit.coreboot.org>
Message-ID: <E1RkO7j-0005Mq-ST@ra.coresystems.de>

the following patch was just integrated into master:
commit c7d7cdb0bd994c887cab6f617497b20069be8a2d
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Jul 2 00:35:02 2011 +0200

    Un-perl commit-msg hook
    
    To simplify installation on mingw a bit (even though git remains a pain),
    drop the perl dependency the commit-msg hook introduced to the coreboot
    development environment.
    It's replaced by awk which we use elsewhere already (and is a more lightweight
    utility in any case)
    
    Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Build-Tested: build bot (Jenkins) at Sun Jul 17 13:04:37 2011, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Mon Jan  9 23:55:13 2012, giving +2
See http://review.coreboot.org/78 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan 10 00:02:48 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 00:02:48 +0100
Subject: [coreboot] Patch merged into coreboot/master: 8f5c7b3 libpayload:
	Remove bitfield use from OHCI data structures
References: <Ic04f151091c359912835b8b3db488d2d41bd4bbb+0@gerrit.coreboot.org>
Message-ID: <E1RkOEq-0005pD-CM@ra.coresystems.de>

the following patch was just integrated into master:
commit 8f5c7b3a920532a36375705092ad1edd27599326
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 09:12:11 2011 +0100

    libpayload: Remove bitfield use from OHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: Ic04f151091c359912835b8b3db488d2d41bd4bbb
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Thu Dec  8 16:20:54 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  9 21:44:56 2011, giving +2
Reviewed-By: Peter Stuge <peter at stuge.se> at Tue Jan 10 00:02:40 2012, giving +2
See http://review.coreboot.org/479 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan 10 00:02:57 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 00:02:57 +0100
Subject: [coreboot] Patch merged into coreboot/master: c10f527 libpayload:
	Remove bitfield use from UHCI data structures
References: <I1b2bcda28c52ad10bbe9429e04d126b555f7828a+0@gerrit.coreboot.org>
Message-ID: <E1RkOEz-000624-Kb@ra.coresystems.de>

the following patch was just integrated into master:
commit c10f52730fcfd22693cea27d6cc0fbf66000d8e2
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 11:55:46 2011 +0100

    libpayload: Remove bitfield use from UHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Thu Dec  8 16:09:28 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  9 21:45:12 2011, giving +2
Reviewed-By: Peter Stuge <peter at stuge.se> at Tue Jan 10 00:02:53 2012, giving +2
See http://review.coreboot.org/478 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan 10 00:04:34 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 00:04:34 +0100
Subject: [coreboot] Patch merged into coreboot/master: 340d640 libpayload:
	Remove bitfield use from EHCI data structures
References: <If4c4cb748af340e2721b89fea8e035da0632971f+0@gerrit.coreboot.org>
Message-ID: <E1RkOGY-0006sg-Hi@ra.coresystems.de>

the following patch was just integrated into master:
commit 340d64045cf4798d301d28664d24bc9ef78050e6
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Thu Nov 24 13:19:57 2011 +0100

    libpayload: Remove bitfield use from EHCI data structures
    
    We agreed that bitfields are a Bad Idea[tm].
    
    Change-Id: If4c4cb748af340e2721b89fea8e035da0632971f
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Thu Dec  8 16:32:03 2011, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Dec  9 21:44:44 2011, giving +2
Reviewed-By: Peter Stuge <peter at stuge.se> at Tue Jan 10 00:04:23 2012, giving +2
See http://review.coreboot.org/480 for details.

-gerrit


From bluckau at sgi.com  Tue Jan 10 00:12:17 2012
From: bluckau at sgi.com (Brian Luckau)
Date: Mon, 9 Jan 2012 23:12:17 +0000
Subject: [coreboot] Extracting an image created with mkelfImage
In-Reply-To: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C472@P-EXMB1-DC21.corp.sgi.com>
References: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C3FE@P-EXMB1-DC21.corp.sgi.com>,
	<20120109213005.3503.qmail@stuge.se>,
	<B4EE0490205BD44F8BD3F7BE2E8E0D760613C472@P-EXMB1-DC21.corp.sgi.com>
Message-ID: <B4EE0490205BD44F8BD3F7BE2E8E0D760613C76B@P-EXMB1-DC21.corp.sgi.com>

Thanks!    

It is an initramfs but it was compressed (must just be very large in relative terms.)  After using your strategy to determine what to put into dd, I was able to use cpio and gzip to do the rest.

--Brian
________________________________________
From: coreboot-bounces at coreboot.org [coreboot-bounces at coreboot.org] on behalf of Brian Luckau [bluckau at sgi.com]
Sent: Monday, January 09, 2012 3:00 PM
To: Peter Stuge; coreboot at coreboot.org
Subject: Re: [coreboot] Extracting an image created with mkelfImage

Hi,

I'm not sure if I'm using the correct paramters but here is some of the information you requested.

# objdump -x -s -D Compute.ebi

Compute.ebi:     file format elf32-i386
Compute.ebi
architecture: i386, flags 0x00000102:
EXEC_P, D_PAGED
start address 0x00010000

Program Header:
    NOTE off    0x000000d4 vaddr 0x00000000 paddr 0x00000000 align 2**0
         filesz 0x000000a4 memsz 0x000000a4 flags rwx
    LOAD off    0x00000178 vaddr 0x00010000 paddr 0x00010000 align 2**0
         filesz 0x00001288 memsz 0x00005524 flags rwx
    LOAD off    0x00001400 vaddr 0x00020000 paddr 0x00020000 align 2**0
         filesz 0x00000000 memsz 0x00001070 flags rwx
    LOAD off    0x00001400 vaddr 0x00100000 paddr 0x00100000 align 2**0
         filesz 0x0020029c memsz 0x00700000 flags rwx
    LOAD off    0x0020169c vaddr 0x02800000 paddr 0x02800000 align 2**0
         filesz 0x007dbdc6 memsz 0x007dbdc6 flags rwx

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
SYMBOL TABLE:
no symbols

root at admin cache]# readelf -a Compute.ebi
ELF Header:
  Magic:   7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
  Class:                             ELF32
  Data:                              2's complement, little endian
  Version:                           1 (current)
  OS/ABI:                            UNIX - System V
  ABI Version:                       0
  Type:                              EXEC (Executable file)
  Machine:                           Intel 80386
  Version:                           0x1
  Entry point address:               0x10000
  Start of program headers:          52 (bytes into file)
  Start of section headers:          0 (bytes into file)
  Flags:                             0x0
  Size of this header:               52 (bytes)
  Size of program headers:           32 (bytes)
  Number of program headers:         5
  Size of section headers:           0 (bytes)
  Number of section headers:         0
  Section header string table index: 0

There are no sections in this file.

There are no sections in this file.

Program Headers:
  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  NOTE           0x0000d4 0x00000000 0x00000000 0x000a4 0x000a4 RWE 0
  LOAD           0x000178 0x00010000 0x00010000 0x01288 0x05524 RWE 0
  LOAD           0x001400 0x00020000 0x00020000 0x00000 0x01070 RWE 0
  LOAD           0x001400 0x00100000 0x00100000 0x20029c 0x700000 RWE 0
  LOAD           0x20169c 0x02800000 0x02800000 0x7dbdc6 0x7dbdc6 RWE 0

There is no dynamic section in this file.

There are no relocations in this file.

There are no unwind sections in this file.

No version information found in this file.
__________________________
From: coreboot-bounces at coreboot.org [coreboot-bounces at coreboot.org] on behalf of Peter Stuge [peter at stuge.se]
Sent: Monday, January 09, 2012 2:30 PM
To: coreboot at coreboot.org
Subject: Re: [coreboot] Extracting an image created with mkelfImage

Hi Brian,

Brian Luckau wrote:
> I have an elf netowrk bootable image for linux that was created
> with mkelfImage.  How can I extract the file to view its contents
> (which kernel modules were included in the file, etc. )

The image may or may not include initrd, if yes it will quite likely
be compressed. What does readelf and/or objdump say about the file?

There's no pre-made tool for taking apart those ELF images. You can
of course always peruse the mkelfImage source code to find out all
details.

http://www.coreboot.org/Mkelfimage
svn co svn://coreboot.org/coreboot/trunk/util/mkelfImage


//Peter

--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

--
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot


From daniel-coreboot at lindenaar.eu  Tue Jan 10 08:40:30 2012
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Tue, 10 Jan 2012 08:40:30 +0100
Subject: [coreboot] i965 and ICH-8
Message-ID: <4F0BEB6E.9010102@lindenaar.eu>

Hi all,
I know it has come up a number of times on the mailing list, but here we 
go again...

I own a few nice motherboards which have an intel chipset with the 965 
northbridge and ICH-8 southbridge. I'd really like to use coreboot on 
them as I have a DIY application where boot time is quite critical.

Has anyone has any luck or progress porting coreboot to this chipset? 
Does anyone have access to the required documentation?

Best regards,
Daniel


From gerrit at coreboot.org  Tue Jan 10 12:02:25 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 12:02:25 +0100
Subject: [coreboot] New patch to review for coreboot: 1ab750f MTRR: get
	physical address size from CPUID
References: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+0@gerrit.coreboot.org>
Message-ID: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/529

-gerrit

commit 1ab750f693375752956642bfc7615954e2942d11
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/intel/ep80579/ep80579_init.c         |    2 +-
 src/cpu/intel/model_1067x/model_1067x_init.c |    2 +-
 src/cpu/intel/model_106cx/model_106cx_init.c |    2 +-
 src/cpu/intel/model_65x/model_65x_init.c     |    2 +-
 src/cpu/intel/model_67x/model_67x_init.c     |    2 +-
 src/cpu/intel/model_68x/model_68x_init.c     |    2 +-
 src/cpu/intel/model_69x/model_69x_init.c     |    2 +-
 src/cpu/intel/model_6bx/model_6bx_init.c     |    2 +-
 src/cpu/intel/model_6dx/model_6dx_init.c     |    2 +-
 src/cpu/intel/model_6ex/model_6ex_init.c     |    2 +-
 src/cpu/intel/model_6fx/model_6fx_init.c     |    2 +-
 src/cpu/intel/model_6xx/model_6xx_init.c     |    2 +-
 src/cpu/intel/model_f0x/model_f0x_init.c     |    2 +-
 src/cpu/intel/model_f1x/model_f1x_init.c     |    2 +-
 src/cpu/intel/model_f2x/model_f2x_init.c     |    2 +-
 src/cpu/intel/model_f3x/model_f3x_init.c     |    2 +-
 src/cpu/intel/model_f4x/model_f4x_init.c     |    2 +-
 src/cpu/via/model_c3/model_c3_init.c         |    2 +-
 src/cpu/via/model_c7/model_c7_init.c         |    2 +-
 src/cpu/x86/mtrr/mtrr.c                      |    8 ++++++--
 src/include/cpu/x86/mtrr.h                   |    2 +-
 21 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(32);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 0c9b3d2..d34e4da 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -54,7 +54,7 @@ static void model_67x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index 7244693..fa35e55 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -85,7 +85,7 @@ static void model_68x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index db8e661..cb805ae 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -25,7 +25,7 @@ static void model_69x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index a8883ec..a06d7fb 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -71,7 +71,7 @@ static void model_6bx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 820597d..19b351d 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -23,7 +23,7 @@ static void model_6dx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index abd9cf4..1c8c72b 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -184,7 +184,7 @@ static void model_6ex_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 5cb1cae..033dfe6 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -211,7 +211,7 @@ static void model_6fx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Setup Page Attribute Tables (PAT) */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 34599e9..5724add 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -47,7 +47,7 @@ static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 11e0c7c..ed12b6e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -28,7 +28,7 @@ static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 1069687..feb8410 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -31,7 +31,7 @@ static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index c1c2b7c..ec78672 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -48,7 +48,7 @@ static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index f04ddcc..580c98b 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index d4c1634..54edf2e 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -39,7 +39,7 @@ static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c
index 2fd2be4..0c5315b 100644
--- a/src/cpu/via/model_c3/model_c3_init.c
+++ b/src/cpu/via/model_c3/model_c3_init.c
@@ -29,7 +29,7 @@
 static void model_c3_init(device_t dev)
 {
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
index bc32616..585f749 100644
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ b/src/cpu/via/model_c7/model_c7_init.c
@@ -202,7 +202,7 @@ static void model_c7_init(device_t dev)
 	x86_enable_cache();
 
 	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..46d8e2d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -462,10 +463,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 }
 
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
+	int address_size;
 	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(address_bits, 1);
+	address_size = cpu_phys_address_size();
+	printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
+	x86_setup_var_mtrrs(address_size, 1);
 }
 
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index c3b3e22..62cb8b7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -39,7 +39,7 @@
 #include <device/device.h>
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
-void x86_setup_mtrrs(unsigned address_bits);
+void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);


From gerrit at coreboot.org  Tue Jan 10 12:08:21 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 12:08:21 +0100
Subject: [coreboot] Patch set updated for coreboot: 8d9a8bc MTRR: get
	physical address size from CPUID
References: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+0@gerrit.coreboot.org>
Message-ID: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+2@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/529

-gerrit

commit 8d9a8bc05374b79360ec627df203306e21ae5c1e
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/arch/x86/include/arch/cpu.h              |    2 ++
 src/arch/x86/lib/cpu.c                       |   20 ++++++++++++++++++++
 src/cpu/intel/ep80579/ep80579_init.c         |    2 +-
 src/cpu/intel/model_1067x/model_1067x_init.c |    2 +-
 src/cpu/intel/model_106cx/model_106cx_init.c |    2 +-
 src/cpu/intel/model_65x/model_65x_init.c     |    2 +-
 src/cpu/intel/model_67x/model_67x_init.c     |    2 +-
 src/cpu/intel/model_68x/model_68x_init.c     |    2 +-
 src/cpu/intel/model_69x/model_69x_init.c     |    2 +-
 src/cpu/intel/model_6bx/model_6bx_init.c     |    2 +-
 src/cpu/intel/model_6dx/model_6dx_init.c     |    2 +-
 src/cpu/intel/model_6ex/model_6ex_init.c     |    2 +-
 src/cpu/intel/model_6fx/model_6fx_init.c     |    2 +-
 src/cpu/intel/model_6xx/model_6xx_init.c     |    2 +-
 src/cpu/intel/model_f0x/model_f0x_init.c     |    2 +-
 src/cpu/intel/model_f1x/model_f1x_init.c     |    2 +-
 src/cpu/intel/model_f2x/model_f2x_init.c     |    2 +-
 src/cpu/intel/model_f3x/model_f3x_init.c     |    2 +-
 src/cpu/intel/model_f4x/model_f4x_init.c     |    2 +-
 src/cpu/via/model_c3/model_c3_init.c         |    2 +-
 src/cpu/via/model_c7/model_c7_init.c         |    2 +-
 src/cpu/x86/mtrr/mtrr.c                      |    8 ++++++--
 src/include/cpu/x86/mtrr.h                   |    2 +-
 23 files changed, 48 insertions(+), 22 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..8089dd5 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -22,6 +22,8 @@
 #define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
 #define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
 
+int cpu_phys_address_size(void);
+
 struct cpuid_result {
 	uint32_t eax;
 	uint32_t ebx;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
 	return name;
 }
 
+static int cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+	if (!(have_cpuid_p()))
+		return 32;
+
+	if (cpu_cpuid_extended_level() > 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+	return 32;
+}
 static void identify_cpu(struct device *cpu)
 {
 	char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(32);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 0c9b3d2..d34e4da 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -54,7 +54,7 @@ static void model_67x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index 7244693..fa35e55 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -85,7 +85,7 @@ static void model_68x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index db8e661..cb805ae 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -25,7 +25,7 @@ static void model_69x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index a8883ec..a06d7fb 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -71,7 +71,7 @@ static void model_6bx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 820597d..19b351d 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -23,7 +23,7 @@ static void model_6dx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index abd9cf4..1c8c72b 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -184,7 +184,7 @@ static void model_6ex_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 5cb1cae..033dfe6 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -211,7 +211,7 @@ static void model_6fx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Setup Page Attribute Tables (PAT) */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 34599e9..5724add 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -47,7 +47,7 @@ static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 11e0c7c..ed12b6e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -28,7 +28,7 @@ static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 1069687..feb8410 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -31,7 +31,7 @@ static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index c1c2b7c..ec78672 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -48,7 +48,7 @@ static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index f04ddcc..580c98b 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index d4c1634..54edf2e 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -39,7 +39,7 @@ static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c
index 2fd2be4..0c5315b 100644
--- a/src/cpu/via/model_c3/model_c3_init.c
+++ b/src/cpu/via/model_c3/model_c3_init.c
@@ -29,7 +29,7 @@
 static void model_c3_init(device_t dev)
 {
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
index bc32616..585f749 100644
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ b/src/cpu/via/model_c7/model_c7_init.c
@@ -202,7 +202,7 @@ static void model_c7_init(device_t dev)
 	x86_enable_cache();
 
 	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..46d8e2d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -462,10 +463,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 }
 
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
+	int address_size;
 	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(address_bits, 1);
+	address_size = cpu_phys_address_size();
+	printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
+	x86_setup_var_mtrrs(address_size, 1);
 }
 
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index c3b3e22..62cb8b7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -39,7 +39,7 @@
 #include <device/device.h>
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
-void x86_setup_mtrrs(unsigned address_bits);
+void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);


From gerrit at coreboot.org  Tue Jan 10 12:18:23 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 12:18:23 +0100
Subject: [coreboot] New patch to review for coreboot: 6b3747f i945: fix tsc
	udelay()
References: <I75de74ef750b5a45be0156efaf10d7239a0b1136+0@gerrit.coreboot.org>
Message-ID: <I75de74ef750b5a45be0156efaf10d7239a0b1136+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/530

-gerrit

commit 6b3747fcc1a57223a25b60e391dc9c1db9ddbbdd
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:16:38 2012 +0100

    i945: fix tsc udelay()
    
    The comparision is the wrong way round: as long as tsc
    is below tsc1, the timeout is not reached
    
    Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/i945/udelay.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index 6b3882b..9170335 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -78,7 +78,7 @@ void udelay(u32 us)
 
 	do {
 		tsc = rdtsc();
-	} while ((tsc.hi > tsc1.hi)
-		 || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
 
 }


From gerrit at coreboot.org  Tue Jan 10 12:54:10 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 12:54:10 +0100
Subject: [coreboot] Patch merged into coreboot/master: 6b3747f i945: fix tsc
	udelay()
References: <I75de74ef750b5a45be0156efaf10d7239a0b1136+0@gerrit.coreboot.org>
Message-ID: <E1RkaHK-00031t-HD@ra.coresystems.de>

the following patch was just integrated into master:
commit 6b3747fcc1a57223a25b60e391dc9c1db9ddbbdd
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:16:38 2012 +0100

    i945: fix tsc udelay()
    
    The comparision is the wrong way round: as long as tsc
    is below tsc1, the timeout is not reached
    
    Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Tue Jan 10 12:54:08 2012, giving +2
See http://review.coreboot.org/530 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan 10 14:12:07 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:12:07 +0100
Subject: [coreboot] Patch set updated for coreboot: a311aff MTRR: get
	physical address size from CPUID
References: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+0@gerrit.coreboot.org>
Message-ID: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+3@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/529

-gerrit

commit a311aff916acb0ee221b599f2cc3a707c9b6761f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/arch/x86/include/arch/cpu.h              |    3 +++
 src/arch/x86/lib/cpu.c                       |   20 ++++++++++++++++++++
 src/cpu/intel/ep80579/ep80579_init.c         |    2 +-
 src/cpu/intel/model_1067x/model_1067x_init.c |    2 +-
 src/cpu/intel/model_106cx/model_106cx_init.c |    2 +-
 src/cpu/intel/model_65x/model_65x_init.c     |    2 +-
 src/cpu/intel/model_67x/model_67x_init.c     |    2 +-
 src/cpu/intel/model_68x/model_68x_init.c     |    2 +-
 src/cpu/intel/model_69x/model_69x_init.c     |    2 +-
 src/cpu/intel/model_6bx/model_6bx_init.c     |    2 +-
 src/cpu/intel/model_6dx/model_6dx_init.c     |    2 +-
 src/cpu/intel/model_6ex/model_6ex_init.c     |    2 +-
 src/cpu/intel/model_6fx/model_6fx_init.c     |    2 +-
 src/cpu/intel/model_6xx/model_6xx_init.c     |    2 +-
 src/cpu/intel/model_f0x/model_f0x_init.c     |    2 +-
 src/cpu/intel/model_f1x/model_f1x_init.c     |    2 +-
 src/cpu/intel/model_f2x/model_f2x_init.c     |    2 +-
 src/cpu/intel/model_f3x/model_f3x_init.c     |    2 +-
 src/cpu/intel/model_f4x/model_f4x_init.c     |    2 +-
 src/cpu/via/model_c3/model_c3_init.c         |    2 +-
 src/cpu/via/model_c7/model_c7_init.c         |    2 +-
 src/cpu/x86/mtrr/mtrr.c                      |    8 ++++++--
 src/include/cpu/x86/mtrr.h                   |    2 +-
 23 files changed, 49 insertions(+), 22 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..79f9113 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -22,6 +22,7 @@
 #define X86_EFLAGS_VIP	0x00100000 /* Virtual Interrupt Pending */
 #define X86_EFLAGS_ID	0x00200000 /* CPUID detection flag */
 
+
 struct cpuid_result {
 	uint32_t eax;
 	uint32_t ebx;
@@ -108,6 +109,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #if !defined(__PRE_RAM__)
 #include <device/device.h>
 
+int cpu_phys_address_size(void);
+
 struct cpu_device_id {
 	unsigned vendor;
 	unsigned device;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
 	return name;
 }
 
+static int cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+	if (!(have_cpuid_p()))
+		return 32;
+
+	if (cpu_cpuid_extended_level() > 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+	return 32;
+}
 static void identify_cpu(struct device *cpu)
 {
 	char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(32);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 0c9b3d2..d34e4da 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -54,7 +54,7 @@ static void model_67x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index 7244693..fa35e55 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -85,7 +85,7 @@ static void model_68x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index db8e661..cb805ae 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -25,7 +25,7 @@ static void model_69x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index a8883ec..a06d7fb 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -71,7 +71,7 @@ static void model_6bx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 820597d..19b351d 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -23,7 +23,7 @@ static void model_6dx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index abd9cf4..1c8c72b 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -184,7 +184,7 @@ static void model_6ex_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 5cb1cae..033dfe6 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -211,7 +211,7 @@ static void model_6fx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Setup Page Attribute Tables (PAT) */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 34599e9..5724add 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -47,7 +47,7 @@ static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 11e0c7c..ed12b6e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -28,7 +28,7 @@ static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 1069687..feb8410 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -31,7 +31,7 @@ static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index c1c2b7c..ec78672 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -48,7 +48,7 @@ static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index f04ddcc..580c98b 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index d4c1634..54edf2e 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -39,7 +39,7 @@ static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c
index 2fd2be4..0c5315b 100644
--- a/src/cpu/via/model_c3/model_c3_init.c
+++ b/src/cpu/via/model_c3/model_c3_init.c
@@ -29,7 +29,7 @@
 static void model_c3_init(device_t dev)
 {
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
index bc32616..585f749 100644
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ b/src/cpu/via/model_c7/model_c7_init.c
@@ -202,7 +202,7 @@ static void model_c7_init(device_t dev)
 	x86_enable_cache();
 
 	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..46d8e2d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -462,10 +463,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 }
 
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
+	int address_size;
 	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(address_bits, 1);
+	address_size = cpu_phys_address_size();
+	printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
+	x86_setup_var_mtrrs(address_size, 1);
 }
 
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index c3b3e22..62cb8b7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -39,7 +39,7 @@
 #include <device/device.h>
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
-void x86_setup_mtrrs(unsigned address_bits);
+void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);


From gerrit at coreboot.org  Tue Jan 10 14:13:27 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:13:27 +0100
Subject: [coreboot] Patch set updated for coreboot: 734bdc3 MTRR: get
	physical address size from CPUID
References: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+0@gerrit.coreboot.org>
Message-ID: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+4@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/529

-gerrit

commit 734bdc32fadc41f4e023868495fbc5b2bef562b3
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/arch/x86/include/arch/cpu.h              |    2 ++
 src/arch/x86/lib/cpu.c                       |   20 ++++++++++++++++++++
 src/cpu/intel/ep80579/ep80579_init.c         |    2 +-
 src/cpu/intel/model_1067x/model_1067x_init.c |    2 +-
 src/cpu/intel/model_106cx/model_106cx_init.c |    2 +-
 src/cpu/intel/model_65x/model_65x_init.c     |    2 +-
 src/cpu/intel/model_67x/model_67x_init.c     |    2 +-
 src/cpu/intel/model_68x/model_68x_init.c     |    2 +-
 src/cpu/intel/model_69x/model_69x_init.c     |    2 +-
 src/cpu/intel/model_6bx/model_6bx_init.c     |    2 +-
 src/cpu/intel/model_6dx/model_6dx_init.c     |    2 +-
 src/cpu/intel/model_6ex/model_6ex_init.c     |    2 +-
 src/cpu/intel/model_6fx/model_6fx_init.c     |    2 +-
 src/cpu/intel/model_6xx/model_6xx_init.c     |    2 +-
 src/cpu/intel/model_f0x/model_f0x_init.c     |    2 +-
 src/cpu/intel/model_f1x/model_f1x_init.c     |    2 +-
 src/cpu/intel/model_f2x/model_f2x_init.c     |    2 +-
 src/cpu/intel/model_f3x/model_f3x_init.c     |    2 +-
 src/cpu/intel/model_f4x/model_f4x_init.c     |    2 +-
 src/cpu/via/model_c3/model_c3_init.c         |    2 +-
 src/cpu/via/model_c7/model_c7_init.c         |    2 +-
 src/cpu/x86/mtrr/mtrr.c                      |    8 ++++++--
 src/include/cpu/x86/mtrr.h                   |    2 +-
 23 files changed, 48 insertions(+), 22 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..85357d7 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -108,6 +108,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #if !defined(__PRE_RAM__)
 #include <device/device.h>
 
+int cpu_phys_address_size(void);
+
 struct cpu_device_id {
 	unsigned vendor;
 	unsigned device;
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..aaa0a16 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -131,6 +131,26 @@ static const char *cpu_vendor_name(int vendor)
 	return name;
 }
 
+static int cpu_cpuid_extended_level(void)
+{
+	return cpuid_eax(0x80000000);
+}
+
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_phys_address_size(void)
+{
+	if (!(have_cpuid_p()))
+		return 32;
+
+	if (cpu_cpuid_extended_level() > 0x80000008)
+		return cpuid_eax(0x80000008) & 0xff;
+
+	if (cpuid_eax(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36))
+		return 36;
+	return 32;
+}
 static void identify_cpu(struct device *cpu)
 {
 	char vendor_name[16];
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c
index 2f47158..8b7dba0 100644
--- a/src/cpu/intel/ep80579/ep80579_init.c
+++ b/src/cpu/intel/ep80579/ep80579_init.c
@@ -41,7 +41,7 @@ static void ep80579_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca2b960..c6d716d 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -197,7 +197,7 @@ static void model_1067x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..4bf2924 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -158,7 +158,7 @@ static void model_106cx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(32);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
index ef97597..285bacd 100644
--- a/src/cpu/intel/model_65x/model_65x_init.c
+++ b/src/cpu/intel/model_65x/model_65x_init.c
@@ -65,7 +65,7 @@ static void model_65x_init(device_t dev)
 
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
index 0c9b3d2..d34e4da 100644
--- a/src/cpu/intel/model_67x/model_67x_init.c
+++ b/src/cpu/intel/model_67x/model_67x_init.c
@@ -54,7 +54,7 @@ static void model_67x_init(device_t cpu)
 	x86_enable_cache();
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
index 7244693..fa35e55 100644
--- a/src/cpu/intel/model_68x/model_68x_init.c
+++ b/src/cpu/intel/model_68x/model_68x_init.c
@@ -85,7 +85,7 @@ static void model_68x_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c
index db8e661..cb805ae 100644
--- a/src/cpu/intel/model_69x/model_69x_init.c
+++ b/src/cpu/intel/model_69x/model_69x_init.c
@@ -25,7 +25,7 @@ static void model_69x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
index a8883ec..a06d7fb 100644
--- a/src/cpu/intel/model_6bx/model_6bx_init.c
+++ b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -71,7 +71,7 @@ static void model_6bx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c
index 820597d..19b351d 100644
--- a/src/cpu/intel/model_6dx/model_6dx_init.c
+++ b/src/cpu/intel/model_6dx/model_6dx_init.c
@@ -23,7 +23,7 @@ static void model_6dx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index abd9cf4..1c8c72b 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -184,7 +184,7 @@ static void model_6ex_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 #if CONFIG_USBDEBUG
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 5cb1cae..033dfe6 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -211,7 +211,7 @@ static void model_6fx_init(device_t cpu)
 #endif
 
 	/* Setup MTRRs */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Setup Page Attribute Tables (PAT) */
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index 34599e9..5724add 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -47,7 +47,7 @@ static void model_6xx_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c
index 11e0c7c..ed12b6e 100644
--- a/src/cpu/intel/model_f0x/model_f0x_init.c
+++ b/src/cpu/intel/model_f0x/model_f0x_init.c
@@ -28,7 +28,7 @@ static void model_f0x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c
index 1069687..feb8410 100644
--- a/src/cpu/intel/model_f1x/model_f1x_init.c
+++ b/src/cpu/intel/model_f1x/model_f1x_init.c
@@ -31,7 +31,7 @@ static void model_f1x_init(device_t dev)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
index c1c2b7c..ec78672 100644
--- a/src/cpu/intel/model_f2x/model_f2x_init.c
+++ b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -48,7 +48,7 @@ static void model_f2x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
index f04ddcc..580c98b 100644
--- a/src/cpu/intel/model_f3x/model_f3x_init.c
+++ b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -31,7 +31,7 @@ static void model_f3x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
index d4c1634..54edf2e 100644
--- a/src/cpu/intel/model_f4x/model_f4x_init.c
+++ b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -39,7 +39,7 @@ static void model_f4x_init(device_t cpu)
 {
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Update the microcode */
diff --git a/src/cpu/via/model_c3/model_c3_init.c b/src/cpu/via/model_c3/model_c3_init.c
index 2fd2be4..0c5315b 100644
--- a/src/cpu/via/model_c3/model_c3_init.c
+++ b/src/cpu/via/model_c3/model_c3_init.c
@@ -29,7 +29,7 @@
 static void model_c3_init(device_t dev)
 {
 	x86_enable_cache();
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
index bc32616..585f749 100644
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ b/src/cpu/via/model_c7/model_c7_init.c
@@ -202,7 +202,7 @@ static void model_c7_init(device_t dev)
 	x86_enable_cache();
 
 	/* Set up Memory Type Range Registers */
-	x86_setup_mtrrs(36);
+	x86_setup_mtrrs();
 	x86_mtrr_check();
 
 	/* Enable the local cpu apics */
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..46d8e2d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <arch/cpu.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -462,10 +463,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 }
 
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
+	int address_size;
 	x86_setup_fixed_mtrrs();
-	x86_setup_var_mtrrs(address_bits, 1);
+	address_size = cpu_phys_address_size();
+	printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
+	x86_setup_var_mtrrs(address_size, 1);
 }
 
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index c3b3e22..62cb8b7 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -39,7 +39,7 @@
 #include <device/device.h>
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
-void x86_setup_mtrrs(unsigned address_bits);
+void x86_setup_mtrrs(void);
 int x86_mtrr_check(void);
 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res);
 void x86_setup_fixed_mtrrs(void);


From gerrit at coreboot.org  Tue Jan 10 14:21:24 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:21:24 +0100
Subject: [coreboot] New patch to review for coreboot: d5dad6a Add missing
	HAVE_HARD_RESET
References: <I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c+0@gerrit.coreboot.org>
Message-ID: <I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/531

-gerrit

commit d5dad6a629c2cbe3a5a3d36bb9596ad4e86bc3ed
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:26:02 2011 +0100

    Add missing HAVE_HARD_RESET
    
    Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/southbridge/intel/esb6300/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/esb6300/Kconfig b/src/southbridge/intel/esb6300/Kconfig
index 0ef9db5..01f719e 100644
--- a/src/southbridge/intel/esb6300/Kconfig
+++ b/src/southbridge/intel/esb6300/Kconfig
@@ -1,3 +1,4 @@
 config SOUTHBRIDGE_INTEL_ESB6300
 	bool
 	select IOAPIC
+	select HAVE_HARD_RESET


From gerrit at coreboot.org  Tue Jan 10 14:21:24 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:21:24 +0100
Subject: [coreboot] New patch to review for coreboot: 616b146 lib: add
	ram_check_nodie
References: <Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2+0@gerrit.coreboot.org>
Message-ID: <Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/532

-gerrit

commit 616b146ce9c61753407b061c18a687807e4ba238
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:23:06 2011 +0100

    lib: add ram_check_nodie
    
    The current implementation calls die() if memory checking fails.
    This isn't always what we want: one might want to print error registers,
    or do some other error handling. Introduce ram_check_nodie() for that
    reason. It returns 0 if ram check succeeded, otherwise 1.
    
    Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/include/lib.h |    1 +
 src/lib/ramtest.c |   40 +++++++++++++++++++++++++++++++++++++---
 2 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/src/include/lib.h b/src/include/lib.h
index ba9684a..bbe735f 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -37,6 +37,7 @@ void move_gdt(void);
 
 /* Defined in src/lib/ramtest.c */
 void ram_check(unsigned long start, unsigned long stop);
+int ram_check_nodie(unsigned long start, unsigned long stop);
 void quick_ram_check(void);
 
 /* Defined in romstage.c */
diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c
index b35c36d..e118062 100644
--- a/src/lib/ramtest.c
+++ b/src/lib/ramtest.c
@@ -83,7 +83,7 @@ static void ram_fill(unsigned long start, unsigned long stop)
 #endif
 }
 
-static void ram_verify(unsigned long start, unsigned long stop)
+static int ram_verify_nodie(unsigned long start, unsigned long stop)
 {
 	unsigned long addr;
 	int i = 0;
@@ -146,15 +146,17 @@ static void ram_verify(unsigned long start, unsigned long stop)
 #else
 		print_debug("\nDRAM did _NOT_ verify!\n");
 #endif
-		die("DRAM ERROR");
+		return 1;
 	}
 	else {
 #if !defined(__ROMCC__)
 		printk(BIOS_DEBUG, "\nDRAM range verified.\n");
 #else
 		print_debug("\nDRAM range verified.\n");
+		return 0;
 #endif
 	}
+	return 0;
 }
 
 
@@ -177,12 +179,44 @@ void ram_check(unsigned long start, unsigned long stop)
 	ram_fill(start, stop);
 	/* Make sure we don't read before we wrote */
 	phys_memory_barrier();
-	ram_verify(start, stop);
+	if (ram_verify_nodie(start, stop))
+		die("DRAM ERROR");
+#if !defined(__ROMCC__)
+	printk(BIOS_DEBUG, "Done.\n");
+#else
+	print_debug("Done.\n");
+#endif
+}
+
+
+int ram_check_nodie(unsigned long start, unsigned long stop)
+{
+	int ret;
+	/*
+	 * This is much more of a "Is my DRAM properly configured?"
+	 * test than a "Is my DRAM faulty?" test.  Not all bits
+	 * are tested.   -Tyson
+	 */
+#if !defined(__ROMCC__)
+	printk(BIOS_DEBUG, "Testing DRAM : %08lx - %08lx\n", start, stop);
+#else
+	print_debug("Testing DRAM : ");
+	print_debug_hex32(start);
+	print_debug("-");
+	print_debug_hex32(stop);
+	print_debug("\n");
+#endif
+	ram_fill(start, stop);
+	/* Make sure we don't read before we wrote */
+	phys_memory_barrier();
+	ret = ram_verify_nodie(start, stop);
+
 #if !defined(__ROMCC__)
 	printk(BIOS_DEBUG, "Done.\n");
 #else
 	print_debug("Done.\n");
 #endif
+	return ret;
 }
 
 void quick_ram_check(void)


From gerrit at coreboot.org  Tue Jan 10 14:21:24 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:21:24 +0100
Subject: [coreboot] Patch set updated for coreboot: 5aaa1a5 Add Intel i5000
	Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+2@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 5aaa1a5ec647b15b141f6d175032653c8d27af77
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig                      |    1 +
 src/northbridge/intel/Makefile.inc                 |    1 +
 src/northbridge/intel/i5000/Kconfig                |   38 +
 src/northbridge/intel/i5000/Makefile.inc           |   21 +
 src/northbridge/intel/i5000/chip.h                 |   23 +
 src/northbridge/intel/i5000/i5000.new/Kconfig      |   38 +
 src/northbridge/intel/i5000/i5000.new/Makefile.inc |   21 +
 src/northbridge/intel/i5000/i5000.new/chip.h       |   23 +
 .../intel/i5000/i5000.new/northbridge.c            |  202 +++
 src/northbridge/intel/i5000/i5000.new/raminit.c    | 1553 ++++++++++++++++++++
 src/northbridge/intel/i5000/i5000.new/raminit.h    |  330 +++++
 src/northbridge/intel/i5000/i5000.new/udelay.c     |   85 ++
 src/northbridge/intel/i5000/northbridge.c          |  189 +++
 src/northbridge/intel/i5000/raminit.c              | 1510 +++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h              |  326 ++++
 src/northbridge/intel/i5000/udelay.c               |   85 ++
 16 files changed, 4446 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..2b25ac4 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
\ No newline at end of file
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..db59cf0 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
\ No newline at end of file
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..41c523d
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on Northbridge
+		setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/i5000.new/Kconfig b/src/northbridge/intel/i5000/i5000.new/Kconfig
new file mode 100644
index 0000000..41c523d
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on Northbridge
+		setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/i5000.new/Makefile.inc b/src/northbridge/intel/i5000/i5000.new/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/i5000.new/chip.h b/src/northbridge/intel/i5000/i5000.new/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/i5000.new/northbridge.c b/src/northbridge/intel/i5000/i5000.new/northbridge.c
new file mode 100644
index 0000000..85ae79e
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/northbridge.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t hecbase, amsize, tolm;
+	uint64_t ambase, memsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+
+	memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
+		      pci_read_config16(dev16_1, 0x84) & ~3);
+	memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
+
+	memsize <<= 24;
+	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
+	if (memsize > 0xe0000000) {
+		memsize -= 0xe0000000;
+		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
+		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
+	}
+
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfeexxxxx range. This range is used for LAPIC */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfee00000;
+	resource->size = (resource_t)0x00001000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfe6xxxxx range. This range is used for IOAPICs */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfec00000;
+	resource->size = (resource_t)0x00010000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/i5000.new/raminit.c b/src/northbridge/intel/i5000/i5000.new/raminit.c
new file mode 100644
index 0000000..a625770
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/raminit.c
@@ -0,0 +1,1553 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		for(;;) {
+			status = pci_read_config16(dev,	stsreg);
+
+			if (status & I5000_SPD_SBE)
+				return -1;
+
+			if (status & I5000_SPD_BUSY)
+				continue;
+
+			if (status & I5000_SPD_RDO) {
+				*out = status & 0xff;
+				out++;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static const int fsbdivs[] = {
+	[DDR_400MHZ] = 500,
+	[DDR_533MHZ] = 375,
+	[DDR_667MHZ] = 300,
+	[DDR_800MHZ] = 250,
+};
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 100) / fsbdivs[d->setup->ddr_speed];
+	return ret;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * fsbdivs[d->setup->ddr_speed]);
+	if ((ret % 10) > 0)
+		ret += 10;
+	ret /= 10;
+	return ret;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	case DDR_800MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_800;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_800, 1, &d->cmd2datanxt[DDR_800MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 250)
+		d->speed = DDR_800MHZ;
+	else if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else if (t_ck_min <= 500)
+		d->speed = DDR_400MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+				 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+				 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, ((bb >> 2) & 3));
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_WOD)
+			return 0;
+	}
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	return -1;
+
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	} else {
+		printk(BIOS_SPEW, "done\n");
+	}
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
+	       d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
+				      d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x, ", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state);
+	printk(BIOS_DEBUG, "done\n");
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	printk(BIOS_DEBUG, "Round trip latency: %d\n",
+	       pci_mmio_read_config8(branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_INFO, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, d->num ? 0x21b1b : 0x20b1b);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+	s->t_ref = tref;
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		tref = 15;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d\n", d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = MIN(s->t_ref, tref);
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_INFO, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	default:
+		break;
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	}
+
+	printk(BIOS_INFO, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+#endif
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
+{
+	i5000_amb_write_config32(d, 1, AMB_FERR,
+				 i5000_amb_read_config32(d, 1, AMB_FERR));
+	i5000_amb_write_config32(d, 1, AMB_NERR,
+				 i5000_amb_read_config32(d, 1, AMB_NERR));
+
+	i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	struct i5000_fbd_branch *b;
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	device_t dev;
+	u32 tolm, mir, drta, drtb, mc, mca, dmir;
+	char ethrot;
+	int t_wrc, bl2, branch;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	switch(setup->ddr_speed) {
+	case DDR_400MHZ:
+	case DDR_533MHZ:
+		ethrot = 0;
+		break;
+	case DDR_667MHZ:
+		ethrot = 1;
+		break;
+	case DDR_800MHZ:
+		ethrot = 2;
+		break;
+	default:
+		ethrot = 3;
+		break;
+	}
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		(ethrot << 18) | /* Electrical throttling: 20 clocks */
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	/* branch participation */
+	mir = (setup->totalmem >> 4) & 0xfff;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		if (setup->branch[branch].used) {
+			b = setup->branch + branch;
+			dev = b->branchdev;
+			mir |= 1 << branch;
+			dmir = b->totalmem << 8;
+
+			/* DMIR interleaves with vendor BIOS:
+			 * 2x dual ranked (0x8b):
+			 * Way 0 = Rank 3
+			 * Way 1 = Rank 1
+			 * Way 2 = Rank 2
+			 * Way 3 = Rank 0
+			 *
+			 * 2x single ranked (0x41):
+			 * Way 0 = Rank 1
+			 * Way 1 = Rank 0
+			 * Way 2 = Rank 1
+			 * Way 3 = Rank 0
+			 *
+			 *
+			 */
+
+			dmir |= 0x8b; /* FIXME: rank interleave */
+
+			printk(BIOS_DEBUG, "DMIR: %08x\n", dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR0, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR1, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR2, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR3, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR4, dmir);
+
+		}
+	}
+
+	printk(BIOS_DEBUG, "MIR: 0x%08x\n", mir);
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir);
+
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir & ~0x03);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir & ~0x03);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting */
+	setup->ddr_speed = DDR_800MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_die(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+	outb(0x06, 0xcf9);
+	asm volatile("hlt");
+}
+
+static void i5000_pam_setup(void)
+{
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(10000);
+	memset(&setup, 0, sizeof(setup));
+
+	pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		i5000_die("Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_die("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_die("failed to enable auto refresh\n");
+
+	if (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		i5000_die("Channel training failed\n");
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+	i5000_pam_setup();
+
+	if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
+		i5000_die("failed to clear error status\n");
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_die("RAM verification failed");
+	}
+#endif
+}
diff --git a/src/northbridge/intel/i5000/i5000.new/raminit.h b/src/northbridge/intel/i5000/i5000.new/raminit.h
new file mode 100644
index 0000000..1632f0e
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/raminit.h
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x54
+#define AMB_FBDLOCKTO 0x68
+#define AMB_EMASK 0x8c
+#define AMB_FERR 0x90
+#define AMB_NERR 0x94
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_400MHZ,
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_800MHZ,
+	DDR_MAX,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt[DDR_MAX];
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/i5000.new/udelay.c b/src/northbridge/intel/i5000/i5000.new/udelay.c
new file mode 100644
index 0000000..26b3c49
--- /dev/null
+++ b/src/northbridge/intel/i5000/i5000.new/udelay.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+
+}
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..4f20f78
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t tolm;
+	uint32_t hecbase;
+	uint64_t ambase;
+//	uint64_t val;
+	uint32_t amsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+//	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+#if 0
+	if (tolm == 0xe0000000 && (val = pci_read_config16(dev16_1, 0x80)) > 0) {
+		val &= 0xfff0;
+		val <<= 34;
+		if (val > 4 * 1048576) {
+			val -= 4 * 1048576;
+			printk(BIOS_INFO, "memory above 4GB: %lldMB\n", val / 1024);
+			ram_resource(dev, idx++, 4096 * 1024, val);
+		}
+	}
+#endif
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28 ;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..d833563
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1510 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		for(;;) {
+			status = pci_read_config16(dev,	stsreg);
+
+			if (status & I5000_SPD_SBE)
+				return -1;
+
+			if (status & I5000_SPD_BUSY)
+				continue;
+
+			if (status & I5000_SPD_RDO) {
+				*out = status & 0xff;
+				out++;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static const int fsbdivs[] = {
+	[DDR_400MHZ] = 500,
+	[DDR_533MHZ] = 375,
+	[DDR_667MHZ] = 300,
+	[DDR_800MHZ] = 250,
+};
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 100) / fsbdivs[d->setup->ddr_speed];
+	return ret;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * fsbdivs[d->setup->ddr_speed]);
+	if ((ret % 10) > 0)
+		ret += 10;
+	ret /= 10;
+	return ret;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	case DDR_800MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_800;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, cmd2data_addr, 1, &d->cmd2datanxt) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 250)
+		d->speed = DDR_800MHZ;
+	else if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else if (t_ck_min <= 500)
+		d->speed = DDR_400MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+				 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+				 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, ((bb >> 2) & 3));
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_WOD)
+			return 0;
+	}
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	return -1;
+
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	} else {
+		printk(BIOS_SPEW, "done\n");
+	}
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc, d->cmd2datanxt);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT, d->cmd2datanxt);
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x, ", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state);
+	printk(BIOS_DEBUG, "done\n");
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	printk(BIOS_DEBUG, "Round trip latency: %d\n",
+	       pci_mmio_read_config8(branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_INFO, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 4, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 4, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 4, 0xbc, p16[6]);
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, d->num ? 0x21b1b : 0x20b1b);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+	s->t_ref = tref;
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		tref = 15;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d\n", d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = MIN(s->t_ref, tref);
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_INFO, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	default:
+		break;
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	}
+
+	printk(BIOS_INFO, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	device_t dev;
+	u32 tolm, mir, drta, drtb, mc, mca;
+	char ethrot;
+	int t_wrc, bl2, branch;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	switch(setup->ddr_speed) {
+	case DDR_400MHZ:
+	case DDR_533MHZ:
+		ethrot = 0;
+		break;
+	case DDR_667MHZ:
+		ethrot = 1;
+		break;
+	case DDR_800MHZ:
+		ethrot = 2;
+		break;
+	default:
+		ethrot = 3;
+		break;
+	}
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		(ethrot << 18) | /* Electrical throttling: 20 clocks */
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	/* branch participation */
+	mir = (setup->totalmem >> 4) & 0xfff;
+
+	/* Rank2 = 2
+	 * Rank1 = 1
+	 * Rank0 = 3
+	 */
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		if (setup->branch[branch].used) {
+			dev = setup->branch[branch].branchdev;
+			mir |= 1 << branch;
+			pci_mmio_write_config32(dev, I5000_DMIR0, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR1, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR2, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR3, 0x20000);
+			pci_mmio_write_config32(dev, I5000_DMIR4, 0x20000);
+
+		}
+	}
+
+	printk(BIOS_DEBUG, "MIR: 0x%08x\n", mir);
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir);
+
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir & ~0x03);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir & ~0x03);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting */
+	setup->ddr_speed = DDR_800MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_die(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+//	outb(0x06, 0xcf9);
+	asm volatile("hlt");
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(10000);
+	memset(&setup, 0, sizeof(setup));
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	while (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		printk(BIOS_INFO, "Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_die("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_die("failed to enable auto refresh\n");
+
+	while (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		printk(BIOS_INFO, "Channel training failed\n");
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_die("RAM verification failed");
+	}
+#endif
+
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..60fbaec
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,326 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x58
+#define AMB_FBDLOCKTO 0x68
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_400MHZ,
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_800MHZ,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt;
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..26b3c49
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+
+}


From gerrit at coreboot.org  Tue Jan 10 14:29:38 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 14:29:38 +0100
Subject: [coreboot] Patch set updated for coreboot: 8e3f9ad Add Intel i5000
	Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+3@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 8e3f9add34e7a1a23cb2edc0cb1649e63db8d940
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig             |    1 +
 src/northbridge/intel/Makefile.inc        |    1 +
 src/northbridge/intel/i5000/Kconfig       |   38 +
 src/northbridge/intel/i5000/Makefile.inc  |   21 +
 src/northbridge/intel/i5000/chip.h        |   23 +
 src/northbridge/intel/i5000/northbridge.c |  202 ++++
 src/northbridge/intel/i5000/raminit.c     | 1553 +++++++++++++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h     |  330 ++++++
 src/northbridge/intel/i5000/udelay.c      |   85 ++
 9 files changed, 2254 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..2b25ac4 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
\ No newline at end of file
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..db59cf0 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
\ No newline at end of file
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..41c523d
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on Northbridge
+		setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..85ae79e
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t hecbase, amsize, tolm;
+	uint64_t ambase, memsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+
+	memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
+		      pci_read_config16(dev16_1, 0x84) & ~3);
+	memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
+
+	memsize <<= 24;
+	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
+	if (memsize > 0xe0000000) {
+		memsize -= 0xe0000000;
+		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
+		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
+	}
+
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfeexxxxx range. This range is used for LAPIC */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfee00000;
+	resource->size = (resource_t)0x00001000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfe6xxxxx range. This range is used for IOAPICs */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfec00000;
+	resource->size = (resource_t)0x00010000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..a625770
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1553 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		for(;;) {
+			status = pci_read_config16(dev,	stsreg);
+
+			if (status & I5000_SPD_SBE)
+				return -1;
+
+			if (status & I5000_SPD_BUSY)
+				continue;
+
+			if (status & I5000_SPD_RDO) {
+				*out = status & 0xff;
+				out++;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static const int fsbdivs[] = {
+	[DDR_400MHZ] = 500,
+	[DDR_533MHZ] = 375,
+	[DDR_667MHZ] = 300,
+	[DDR_800MHZ] = 250,
+};
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 100) / fsbdivs[d->setup->ddr_speed];
+	return ret;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * fsbdivs[d->setup->ddr_speed]);
+	if ((ret % 10) > 0)
+		ret += 10;
+	ret /= 10;
+	return ret;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	case DDR_800MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_800;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_800, 1, &d->cmd2datanxt[DDR_800MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 250)
+		d->speed = DDR_800MHZ;
+	else if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else if (t_ck_min <= 500)
+		d->speed = DDR_400MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+				 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+				 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, ((bb >> 2) & 3));
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_WOD)
+			return 0;
+	}
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	return -1;
+
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	} else {
+		printk(BIOS_SPEW, "done\n");
+	}
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
+	       d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
+				      d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x, ", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state);
+	printk(BIOS_DEBUG, "done\n");
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	printk(BIOS_DEBUG, "Round trip latency: %d\n",
+	       pci_mmio_read_config8(branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_INFO, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, d->num ? 0x21b1b : 0x20b1b);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+	s->t_ref = tref;
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		tref = 15;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d\n", d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = MIN(s->t_ref, tref);
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_INFO, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	default:
+		break;
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	}
+
+	printk(BIOS_INFO, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+#endif
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
+{
+	i5000_amb_write_config32(d, 1, AMB_FERR,
+				 i5000_amb_read_config32(d, 1, AMB_FERR));
+	i5000_amb_write_config32(d, 1, AMB_NERR,
+				 i5000_amb_read_config32(d, 1, AMB_NERR));
+
+	i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	struct i5000_fbd_branch *b;
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	device_t dev;
+	u32 tolm, mir, drta, drtb, mc, mca, dmir;
+	char ethrot;
+	int t_wrc, bl2, branch;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	switch(setup->ddr_speed) {
+	case DDR_400MHZ:
+	case DDR_533MHZ:
+		ethrot = 0;
+		break;
+	case DDR_667MHZ:
+		ethrot = 1;
+		break;
+	case DDR_800MHZ:
+		ethrot = 2;
+		break;
+	default:
+		ethrot = 3;
+		break;
+	}
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		(ethrot << 18) | /* Electrical throttling: 20 clocks */
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	/* branch participation */
+	mir = (setup->totalmem >> 4) & 0xfff;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		if (setup->branch[branch].used) {
+			b = setup->branch + branch;
+			dev = b->branchdev;
+			mir |= 1 << branch;
+			dmir = b->totalmem << 8;
+
+			/* DMIR interleaves with vendor BIOS:
+			 * 2x dual ranked (0x8b):
+			 * Way 0 = Rank 3
+			 * Way 1 = Rank 1
+			 * Way 2 = Rank 2
+			 * Way 3 = Rank 0
+			 *
+			 * 2x single ranked (0x41):
+			 * Way 0 = Rank 1
+			 * Way 1 = Rank 0
+			 * Way 2 = Rank 1
+			 * Way 3 = Rank 0
+			 *
+			 *
+			 */
+
+			dmir |= 0x8b; /* FIXME: rank interleave */
+
+			printk(BIOS_DEBUG, "DMIR: %08x\n", dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR0, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR1, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR2, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR3, dmir);
+			pci_mmio_write_config32(dev, I5000_DMIR4, dmir);
+
+		}
+	}
+
+	printk(BIOS_DEBUG, "MIR: 0x%08x\n", mir);
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir);
+
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir & ~0x03);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir & ~0x03);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting */
+	setup->ddr_speed = DDR_800MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_die(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+	outb(0x06, 0xcf9);
+	asm volatile("hlt");
+}
+
+static void i5000_pam_setup(void)
+{
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(10000);
+	memset(&setup, 0, sizeof(setup));
+
+	pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		i5000_die("Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_die("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_die("failed to enable auto refresh\n");
+
+	if (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		i5000_die("Channel training failed\n");
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+	i5000_pam_setup();
+
+	if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
+		i5000_die("failed to clear error status\n");
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_die("RAM verification failed");
+	}
+#endif
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..1632f0e
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x54
+#define AMB_FBDLOCKTO 0x68
+#define AMB_EMASK 0x8c
+#define AMB_FERR 0x90
+#define AMB_NERR 0x94
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_400MHZ,
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_800MHZ,
+	DDR_MAX,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt[DDR_MAX];
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..26b3c49
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+
+}


From gerrit at coreboot.org  Tue Jan 10 15:03:48 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 15:03:48 +0100
Subject: [coreboot] Patch merged into coreboot/master: d5dad6a Add missing
	HAVE_HARD_RESET
References: <I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c+0@gerrit.coreboot.org>
Message-ID: <E1RkcIm-0001uP-1g@ra.coresystems.de>

the following patch was just integrated into master:
commit d5dad6a629c2cbe3a5a3d36bb9596ad4e86bc3ed
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:26:02 2011 +0100

    Add missing HAVE_HARD_RESET
    
    Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Tue Jan 10 15:00:38 2012, giving +2
See http://review.coreboot.org/531 for details.

-gerrit


From r.marek at assembler.cz  Tue Jan 10 16:19:30 2012
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 10 Jan 2012 16:19:30 +0100
Subject: [coreboot] Fwd: FOSDEM 2012 stand confirmation: coreboot
Message-ID: <4F0C5702.7090003@assembler.cz>

Hi all

We do have a stand confirmation on FOSDEM. I will take most likely AM2 M2V-MX SE 
plus maybe the the A8V-E SE. Board.

What are your plans to display there?


Thanks
Rudolf

-------- Original Message --------
Subject: FOSDEM 2012 stand confirmation: coreboot
Date: Thu, 5 Jan 2012 16:05:29 +0100 (CET)
From: FOSDEM Stands Team <stands at fosdem.org>
Reply-To: stands at fosdem.org
Organization: FOSDEM - http://fosdem.org
To: Rudolf Marek <r.marek at assembler.cz>
CC: stands at fosdem.org


Hi Rudolf Marek

We have the pleasure to inform you that your request for a stand
at FOSDEM 2012 has been accepted.

* amount of tables: 1
* in building.....: AW
* build-up........: from 09:00 on, on Saturday
* teardown........: closing is at 18:00 on Sunday

We can provide you with secure space where you may deposit
hardware during the night from Saturday to Sunday. It is closed
and security staff is on the campus all the time, but we do not
provide insurance nor take responsibility in case of damage or
theft.

Please try to have everything torn down by 18:00 on Sunday, as
we have to clean everything up on Sunday night.

We put a certain amount of tables at your disposal (see above),
each having a size of about 2m by 1m:
https://fosdem.org/2012/files/stands-table.jpg

Note that we do not provide any clothing but you are more than
welcome to provide any on your own, especially if you have
something like a banner for your project.

We will provide you with power sockets (*) but if you have a
couple of extension cables, we recommend you do bring them along
if possible.

(*) note that Belgium uses type E sockets:
http://users.telenet.be/worldstandards/electricity.htm#plugs_e
If you need any adapters, make sure to bring them along as we
cannot provide you with any ourselves.

High-speed Internet uplink will be provided by means of WiFi
everywhere. If you have a device that requires a wired ethernet
connection, please do take a bridge device with you.

If you have any further questions, please do contact us at
stands at fosdem.org

Thank you for your participation and see you in Brussels soon :)

cheers,
The FOSDEM Team



From r.marek at assembler.cz  Tue Jan 10 16:25:37 2012
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 10 Jan 2012 16:25:37 +0100
Subject: [coreboot] hackaton proposal in Paris
In-Reply-To: <a5ceb900-551b-4240-8297-eaa4f5d69054@zimbra6-e1.priv.proxad.net>
References: <a5ceb900-551b-4240-8297-eaa4f5d69054@zimbra6-e1.priv.proxad.net>
Message-ID: <4F0C5871.50302@assembler.cz>

Hi Florentin

> First of all, let me wish you, all the people involved in the Coreboot
> project hackers and enthusiasts, a great and happy New Year!

-j MIRROR

> Next, following some discussions I've had at the 28c3 event in Berlin, I
> would like to propose a coreboot hackaton at the 12,13 and 14 april in Paris.
> If all goes OK, we could take profit from the organisation of the event
> "Hackito Ergo Sum", wich takes place at the same dates in Paris. Hopefully
> there will be some kind of "hack area" like the "hackcenter" of the CCC
> Congress, where we could install our stuff. The guy I have meet told me that
> providing space for 6-7 people will be no problem.

Sounds good to me!

> Regarding the accomodation
> and other logistical details, unfortunately I can not give you more info
> yet. Now I would like to know if there are some coreboot people which are
> intersted by this ideea, and if enough persons are interested I will proceed
> with further organizatoric actions.

Yes maybe doing a doodle survey?

> By the way, Rudolph, do you plan to organize in 2012 a new hackaton in
> Prague? (For my part, I see no problem if there are 2 coreboot hackatons in
> 2012.. ;-))

Well not decided yet ;) Maybe again in October/September?
Lets concentrate on the Paris right now!

Thanks
Rudolf



From GNUtoo at no-log.org  Tue Jan 10 19:50:10 2012
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Tue, 10 Jan 2012 19:50:10 +0100
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
In-Reply-To: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
References: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
Message-ID: <201201101950.10839.GNUtoo@no-log.org>

Thanks a lot!!!!

I'm comming from the embedded world( that means ARM devices running GNU/Linux 
or Android ) and I find this paper very usefull....
I've already started to read it but I didn't finish yet.

Denis.


From gerrit at coreboot.org  Tue Jan 10 21:51:41 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 10 Jan 2012 21:51:41 +0100
Subject: [coreboot] Patch merged into coreboot/master: 734bdc3 MTRR: get
	physical address size from CPUID
References: <If019c3d9147c3b86357f0ef0d9fda94d49d811ca+0@gerrit.coreboot.org>
Message-ID: <E1RkifV-0005Ar-KW@ra.coresystems.de>

the following patch was just integrated into master:
commit 734bdc32fadc41f4e023868495fbc5b2bef562b3
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 12:01:43 2012 +0100

    MTRR: get physical address size from CPUID
    
    The current code uses static values for the physical address size
    supported by a CPU. This isn't always the right value: I.e. on
    model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
    Xeons from the same family have 38 bits, which results in invalid
    MTRR setup. Fix this by getting the right number from CPUID.
    
    Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Tue Jan 10 14:43:20 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue Jan 10 21:32:38 2012, giving +2
See http://review.coreboot.org/529 for details.

-gerrit


From gerrit at coreboot.org  Tue Jan 10 22:34:18 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Tue, 10 Jan 2012 22:34:18 +0100
Subject: [coreboot] New patch to review for coreboot: 20a412d W83627HF:
	remove unused function
References: <I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff+0@gerrit.coreboot.org>
Message-ID: <I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/533

-gerrit

commit 20a412d99c1a2f2c95a7c5db997c4f6a570a4d1c
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 22:33:01 2012 +0100

    W83627HF: remove unused function
    
    When CONFIG_EXPERT is set, compilation fails with:
    
    src/superio/winbond/w83627hf/superio.c:61:13: error: ?w83627hf_16_bit_addr_qual? defined but not used [-Werror=unused-function]
    cc1: all warnings being treated as errors
    
    This function isn't used in the code, so just remove it.
    
    Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/superio/winbond/w83627hf/superio.c |   14 --------------
 1 files changed, 0 insertions(+), 14 deletions(-)

diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c
index 8ecec62..1d1b169 100644
--- a/src/superio/winbond/w83627hf/superio.c
+++ b/src/superio/winbond/w83627hf/superio.c
@@ -57,20 +57,6 @@ static u8 pnp_read_index(u16 port, u8 reg)
 	return inb(port + 1);
 }
 
-#if CONFIG_EXPERT
-static void w83627hf_16_bit_addr_qual(device_t dev)
-{
-	u8 reg8;
-
-	/* Enable 16 bit address qualification. */
-	pnp_enter_ext_func_mode(dev);
-	reg8 = pnp_read_config(dev, 0x24);
-	reg8 |= (1 << 7);
-	pnp_write_config(dev, 0x24, reg8);
-	pnp_exit_ext_func_mode(dev);
-}
-#endif
-
 static void enable_hwm_smbus(device_t dev)
 {
 	u8 reg8;


From paulepanter at users.sourceforge.net  Tue Jan 10 22:41:49 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 10 Jan 2012 22:41:49 +0100
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
In-Reply-To: <201201101950.10839.GNUtoo@no-log.org>
References: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
	<201201101950.10839.GNUtoo@no-log.org>
Message-ID: <1326231709.15840.94.camel@mattotaupa>

Am Dienstag, den 10.01.2012, 19:50 +0100 schrieb Denis 'GNUtoo' Carikli:
> Thanks a lot!!!!

I second that! Thank you very much and congrats for finishing your
thesis.

> I'm comming from the embedded world( that means ARM devices running GNU/Linux 
> or Android ) and I find this paper very usefull....
> I've already started to read it but I didn't finish yet.

Peter, have you had time to set up the Git repository yet? Denis could
then already correct some errors, if he finds them. Should it be hosted
by the coreboot infrastructure?


Thanks,

Paul
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From r.marek at assembler.cz  Wed Jan 11 00:15:04 2012
From: r.marek at assembler.cz (Rudolf Marek)
Date: Wed, 11 Jan 2012 00:15:04 +0100
Subject: [coreboot] will order flash chips
Message-ID: <4F0CC678.1090405@assembler.cz>

Hi all,

I will buy some SPI flashchips and some of us will meet on FOSDEM:

http://cz.farnell.com/amic/a25l016-f/memory-flash-spi-16m-8dip/dp/1907083?in_merch=New%20Products

http://cz.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085?in_merch=New%20Products

http://cz.farnell.com/amic/a25l080-f/memory-flash-spi-8m-8dip/dp/1907080

http://cz.farnell.com/amic/a25l40pu-f/ic-flash-4mb-spi-bottom-boot/dp/1566004

All are in DIP casing. In case you are there we can share bit of shipping costs. 
I can order through some other company and it will cost about 4EUR (shipping to me).

Thanks
Rudolf


From gerrit at coreboot.org  Wed Jan 11 09:13:17 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 11 Jan 2012 09:13:17 +0100
Subject: [coreboot] Patch merged into coreboot/master: 20a412d W83627HF:
	remove unused function
References: <I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff+0@gerrit.coreboot.org>
Message-ID: <E1RktJ7-0004jL-Mn@ra.coresystems.de>

the following patch was just integrated into master:
commit 20a412d99c1a2f2c95a7c5db997c4f6a570a4d1c
Author: Sven Schnelle <svens at stackframe.org>
Date:   Tue Jan 10 22:33:01 2012 +0100

    W83627HF: remove unused function
    
    When CONFIG_EXPERT is set, compilation fails with:
    
    src/superio/winbond/w83627hf/superio.c:61:13: error: ?w83627hf_16_bit_addr_qual? defined but not used [-Werror=unused-function]
    cc1: all warnings being treated as errors
    
    This function isn't used in the code, so just remove it.
    
    Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Tue Jan 10 22:48:50 2012, giving +1
Reviewed-By: Sven Schnelle <svens at stackframe.org> at Wed Jan 11 09:13:16 2012, giving +2
See http://review.coreboot.org/533 for details.

-gerrit


From daniel-coreboot at lindenaar.eu  Wed Jan 11 15:13:13 2012
From: daniel-coreboot at lindenaar.eu (Daniel Lindenaar)
Date: Wed, 11 Jan 2012 15:13:13 +0100
Subject: [coreboot] i965 and ICH-8
In-Reply-To: <CAP6exY+4p8f3uJ7vSvDhTMrck+39n1mL=D-CvQF-0CTkxQUQHQ@mail.gmail.com>
References: <4F0BEB6E.9010102@lindenaar.eu>
	<CAP6exY+4p8f3uJ7vSvDhTMrck+39n1mL=D-CvQF-0CTkxQUQHQ@mail.gmail.com>
Message-ID: <4F0D98F9.2040906@lindenaar.eu>

Op 01/10/2012 5:05 PM, ron minnich schreef:
> I think if you are in need of
> what coreboot can offer you should change the question: what kind of
> chipsets do you want that coreboot supports?
Hi,
I understand what you're saying, yet I've gotten my hands on two boards 
with the aforementioned chipsets and a lot of goodies on them, so I 
thought to give it a go before spending ??? for an already supported 
board (which would obviously be much easier)
So I'm looking for any kind of support in getting this thing to work. 
Also I might have a go at reverse engineering the original BIOS and 
seeing if the difference between the 945 and the 965 is small enough to 
adapt the code here and there.

Anyone?

Best regards,
Daniel


From gerrit at coreboot.org  Wed Jan 11 15:45:27 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Wed, 11 Jan 2012 15:45:27 +0100
Subject: [coreboot] Patch set updated for coreboot: 2301c36 Add Intel i5000
	Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+4@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 2301c3600ce3e76f8cb526f28c62d02ea7de4022
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig             |    1 +
 src/northbridge/intel/Makefile.inc        |    1 +
 src/northbridge/intel/i5000/Kconfig       |   38 +
 src/northbridge/intel/i5000/Makefile.inc  |   21 +
 src/northbridge/intel/i5000/chip.h        |   23 +
 src/northbridge/intel/i5000/northbridge.c |  202 ++++
 src/northbridge/intel/i5000/raminit.c     | 1639 +++++++++++++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h     |  330 ++++++
 src/northbridge/intel/i5000/udelay.c      |   85 ++
 9 files changed, 2340 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..2b25ac4 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
\ No newline at end of file
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..db59cf0 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
\ No newline at end of file
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..41c523d
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on Northbridge
+		setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..85ae79e
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,202 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t hecbase, amsize, tolm;
+	uint64_t ambase, memsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+
+	memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
+		      pci_read_config16(dev16_1, 0x84) & ~3);
+	memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
+
+	memsize <<= 24;
+	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
+	if (memsize > 0xe0000000) {
+		memsize -= 0xe0000000;
+		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
+		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
+	}
+
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfeexxxxx range. This range is used for LAPIC */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfee00000;
+	resource->size = (resource_t)0x00001000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* add resource for 0xfe6xxxxx range. This range is used for IOAPICs */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfec00000;
+	resource->size = (resource_t)0x00010000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..04a2335
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1639 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		for(;;) {
+			status = pci_read_config16(dev,	stsreg);
+
+			if (status & I5000_SPD_SBE)
+				return -1;
+
+			if (status & I5000_SPD_BUSY)
+				continue;
+
+			if (status & I5000_SPD_RDO) {
+				*out = status & 0xff;
+				out++;
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static const int fsbdivs[] = {
+	[DDR_400MHZ] = 500,
+	[DDR_533MHZ] = 375,
+	[DDR_667MHZ] = 300,
+	[DDR_800MHZ] = 250,
+};
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 100) / fsbdivs[d->setup->ddr_speed];
+	return ret;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int ret = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * fsbdivs[d->setup->ddr_speed]);
+	if ((ret % 10) > 0)
+		ret += 10;
+	ret /= 10;
+	return ret;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	case DDR_800MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_800;
+		break;
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_800, 1, &d->cmd2datanxt[DDR_800MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 250)
+		d->speed = DDR_800MHZ;
+	else if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else if (t_ck_min <= 500)
+		d->speed = DDR_400MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+				 t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+				 t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, ((bb >> 2) & 3));
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_WOD)
+			return 0;
+	}
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	return -1;
+
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	for(;;) {
+		status = pci_read_config16(dev,	stsreg);
+
+		if (status & I5000_SPD_SBE)
+			break;
+
+		if (status & I5000_SPD_BUSY)
+			continue;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			return 0;
+		}
+	}
+	return -1;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	} else {
+		printk(BIOS_SPEW, "done\n");
+	}
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
+	       d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
+				      d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x, ", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state);
+	printk(BIOS_DEBUG, "done\n");
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	printk(BIOS_DEBUG, "Round trip latency: %d\n",
+	       pci_mmio_read_config8(branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	int i;
+	pci_mmio_write_config8(c->branch->branchdev,
+			       c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	for(i = 0; i < 4; i++) {
+		if (c->dimm[i].present)
+			i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? 0x21b1b : 0x20b1b);
+	}
+
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_INFO, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+	s->t_ref = tref;
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		tref = 15;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d\n", d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = MIN(s->t_ref, tref);
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_INFO, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	default:
+		break;
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	}
+
+	printk(BIOS_INFO, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+#endif
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
+{
+	i5000_amb_write_config32(d, 1, AMB_FERR,
+				 i5000_amb_read_config32(d, 1, AMB_FERR));
+	i5000_amb_write_config32(d, 1, AMB_NERR,
+				 i5000_amb_read_config32(d, 1, AMB_NERR));
+
+	i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int i5000_setup_dmir(struct i5000_fbd_branch *b)
+{
+	struct i5000_fbdimm *d;
+	device_t dev = b->branchdev;
+	u8 rankmap = 0, dmir = 0;
+	u32 dmirval = 0;
+	int i, set, rankoffset = 0, ranksize = 0, ranks = 0;
+
+	if (!b->used)
+		return 0;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		rankmap >>= 2;
+
+		d = b->channel[0].dimm + i;
+		if (!d->present)
+			continue;
+
+		if (d->ranks == 2) {
+			rankmap |= 0xc0;
+			ranks += 2;
+		} else {
+			rankmap |= 0x40;
+			ranks++;
+		}
+	}
+
+	printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);
+
+	dmir = I5000_DMIR0;
+
+	ranksize = b->channel[0].dimm[0].size << 7;
+
+	if (b->channel[0].dimm[0].ranks == 2)
+		ranksize <<= 1;
+
+	if (b->setup->single_channel)
+		ranksize >>= 1;
+
+	while(ranks) {
+		dmirval = 0;
+		set = 0;
+		if (ranks >= 4) {
+			for(i = 7; set < 4 && i >= 0; i--) {
+				if (rankmap & (1 << i)) {
+					rankmap &= ~(1 << i);
+					ranks--;
+					dmirval |= (i << (set * 3));
+					set++;
+				}
+			}
+		} else if (ranks >= 2) {
+			printk(BIOS_DEBUG, "ranks2\n");
+			for(i = 7; set < 2 && i >= 0; i--) {
+				if (rankmap & (1 << i)) {
+				printk(BIOS_DEBUG, "%d set\n", i);
+					rankmap &= ~(1 << i);
+					ranks--;
+					dmirval |= (i << (set * 3)) | (i << (6 + (set * 3)));
+					set++;
+				}
+			}
+		} else {
+			for(i = 7; set < 1 && i >= 0; i--) {
+				if (rankmap & (1 << i)) {
+					rankmap &= ~(1 << i);
+					ranks--;
+					dmirval |= i;
+					set++;
+				}
+			}
+		}
+		dmirval |= rankoffset + (set * ranksize);
+		rankoffset += (set * ranksize);
+		printk(BIOS_DEBUG, "a ranks %d DMIR%d: %08x\n", ranks, (dmir - I5000_DMIR0) >> 2,
+		       dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+		dmir += 4;
+	}
+
+	for(; dmir <= I5000_DMIR4; dmir += 4) {
+		printk(BIOS_DEBUG, "b DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2, dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+	}
+	return rankoffset;
+}
+
+static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
+
+	size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;
+	size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;
+
+        minsize = MIN(size0, size1);
+
+        if (size0 > size1) {
+                tmp = size1;
+                size1 = size0;
+                size0 = tmp;
+        }
+
+        if (size0 == size1) {
+                mir0 = (size0 << 1) | 3;
+                mir1 = (size0 << 1);
+                mir2 = (size0 << 1);
+        } else if (!size0) {
+                mir0 = size1 | 1;
+                mir1 = size1;
+                mir2 = size1;
+        } else {
+                mir0 = (size0 << 1) | 3;
+                mir1 = (size1 + size0) | 1;
+                mir2 = size1 + size0;
+        }
+
+        printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
+        printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
+        printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
+
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir0);
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir1);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir2);
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 tolm, drta, drtb, mc, mca;
+	char ethrot;
+	int t_wrc, bl2;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	switch(setup->ddr_speed) {
+	case DDR_400MHZ:
+	case DDR_533MHZ:
+		ethrot = 0;
+		break;
+	case DDR_667MHZ:
+		ethrot = 1;
+		break;
+	case DDR_800MHZ:
+		ethrot = 2;
+		break;
+	default:
+		ethrot = 3;
+		break;
+	}
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		(ethrot << 18) | /* Electrical throttling: 20 clocks */
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	i5000_setup_interleave(setup);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting */
+	setup->ddr_speed = DDR_800MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_die(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+	outb(0x06, 0xcf9);
+	asm volatile("hlt");
+}
+
+static void i5000_pam_setup(void)
+{
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(10000);
+	memset(&setup, 0, sizeof(setup));
+
+	pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		i5000_die("Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_die("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_die("failed to enable auto refresh\n");
+
+	if (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		i5000_die("Channel training failed\n");
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+	i5000_pam_setup();
+
+	if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
+		i5000_die("failed to clear error status\n");
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_die("RAM verification failed");
+	}
+#endif
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..1632f0e
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x54
+#define AMB_FBDLOCKTO 0x68
+#define AMB_EMASK 0x8c
+#define AMB_FERR 0x90
+#define AMB_NERR 0x94
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_400MHZ,
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_800MHZ,
+	DDR_MAX,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt[DDR_MAX];
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..26b3c49
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+
+}


From GNUtoo at no-log.org  Wed Jan 11 19:14:30 2012
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Wed, 11 Jan 2012 19:14:30 +0100
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
In-Reply-To: <1326231709.15840.94.camel@mattotaupa>
References: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
	<201201101950.10839.GNUtoo@no-log.org>
	<1326231709.15840.94.camel@mattotaupa>
Message-ID: <201201111914.31127.GNUtoo@no-log.org>

>Denis could
>then already correct some errors, if he finds them.
I've found an error:
Page 4 there is:
The standard [insert 'which' here] does not just cover a communications 
protocol, is a widely used untire I/O signaling bus and describes the various 
physical and electrical characteristics of the PCI hardware.

Denis.


From xdrudis at tinet.cat  Wed Jan 11 20:56:20 2012
From: xdrudis at tinet.cat (xdrudis)
Date: Wed, 11 Jan 2012 20:56:20 +0100
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
In-Reply-To: <1326231709.15840.94.camel@mattotaupa>
References: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
	<201201101950.10839.GNUtoo@no-log.org>
	<1326231709.15840.94.camel@mattotaupa>
Message-ID: <20120111195620.GA3866@ideafix.casa.ct>

On Tue, Jan 10, 2012 at 10:41:49PM +0100, Paul Menzel wrote:
> Am Dienstag, den 10.01.2012, 19:50 +0100 schrieb Denis 'GNUtoo' Carikli:
> > Thanks a lot!!!!
> 
> I second that! Thank you very much and congrats for finishing your
> thesis.
>

+1




From stefan.reinauer at coreboot.org  Wed Jan 11 23:23:41 2012
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 11 Jan 2012 23:23:41 +0100
Subject: [coreboot] i965 and ICH-8
In-Reply-To: <4F0D98F9.2040906@lindenaar.eu>
References: <4F0BEB6E.9010102@lindenaar.eu>
	<CAP6exY+4p8f3uJ7vSvDhTMrck+39n1mL=D-CvQF-0CTkxQUQHQ@mail.gmail.com>
	<4F0D98F9.2040906@lindenaar.eu>
Message-ID: <20120111222339.GA1361@coreboot.org>

* Daniel Lindenaar <daniel-coreboot at lindenaar.eu> [120111 15:13]:
> I understand what you're saying, yet I've gotten my hands on two
> boards with the aforementioned chipsets and a lot of goodies on
> them, so I thought to give it a go before spending ??? for an
> already supported board (which would obviously be much easier)
> So I'm looking for any kind of support in getting this thing to
> work. Also I might have a go at reverse engineering the original
> BIOS and seeing if the difference between the 945 and the 965 is
> small enough to adapt the code here and there.

The effort of porting coreboot to 965 will take many weeks.
If you wish to do that, the coreboot community would highly
appreciate that and help whenever possible.

Stefan



From peter at stuge.se  Thu Jan 12 04:31:56 2012
From: peter at stuge.se (Peter Stuge)
Date: Thu, 12 Jan 2012 04:31:56 +0100
Subject: [coreboot] i965 and ICH-8
In-Reply-To: <20120111222339.GA1361@coreboot.org>
References: <4F0BEB6E.9010102@lindenaar.eu>
	<CAP6exY+4p8f3uJ7vSvDhTMrck+39n1mL=D-CvQF-0CTkxQUQHQ@mail.gmail.com>
	<4F0D98F9.2040906@lindenaar.eu>
	<20120111222339.GA1361@coreboot.org>
Message-ID: <20120112033156.13457.qmail@stuge.se>

Stefan Reinauer wrote:
> > I understand what you're saying, yet I've gotten my hands on two
> > boards with the aforementioned chipsets and a lot of goodies on
> > them, so I thought to give it a go before spending ??? for an
> > already supported board (which would obviously be much easier)
> 
> The effort of porting coreboot to 965 will take many weeks.

I see your weeks and raise with many months.

Daniel, buy a supported board if all you want to do is use coreboot.


//Peter


From russ at ashlandhome.net  Thu Jan 12 05:26:40 2012
From: russ at ashlandhome.net (Russell Whitaker)
Date: Wed, 11 Jan 2012 20:26:40 -0800 (PST)
Subject: [coreboot] M.Sc. thesis on x86 firmware alternatives
In-Reply-To: <201201111914.31127.GNUtoo@no-log.org>
References: <BE6707C8ED77C542A5697148F6B406E9094306@Mail-AA.ccs.local>
	<201201101950.10839.GNUtoo@no-log.org>
	<1326231709.15840.94.camel@mattotaupa>
	<201201111914.31127.GNUtoo@no-log.org>
Message-ID: <alpine.LNX.2.00.1201112018490.1640@bigred.russwhit.org>



On Wed, 11 Jan 2012, Denis 'GNUtoo' Carikli wrote:

>> Denis could
>> then already correct some errors, if he finds them.
> I've found an error:
> Page 4 there is:
> The standard [insert 'which' here] does not just cover a communications
> protocol, is a widely used untire I/O signaling bus and describes the various
> physical and electrical characteristics of the PCI hardware.
>

Sounds awkward. try:

The standard does not just cover a communications protocol, it is a widely
used entire ...
      ^                                                      ^^

   Russ

> Denis.
>
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>


From echelon at free.fr  Thu Jan 12 09:24:14 2012
From: echelon at free.fr (echelon at free.fr)
Date: Thu, 12 Jan 2012 09:24:14 +0100 (CET)
Subject: [coreboot] hackaton proposal in Paris
In-Reply-To: <4F0C5871.50302@assembler.cz>
Message-ID: <8fbaba9a-ce20-4a7e-9d68-d12406c0a3cc@zimbra6-e1.priv.proxad.net>

OK,
I have to check first some logistical details with the people who organize the "Hackito Ergo Sum" event and then I will open the doodle survey asap this WE.
BR,
 Florentin

----- Mail d'origine -----
De: Rudolf Marek <r.marek at assembler.cz>
?: coreboot at coreboot.org
Envoy?: Tue, 10 Jan 2012 16:25:37 +0100 (CET)
Objet: Re: [coreboot] hackaton proposal in Paris

Hi Florentin

> First of all, let me wish you, all the people involved in the Coreboot
> project hackers and enthusiasts, a great and happy New Year!

-j MIRROR

> Next, following some discussions I've had at the 28c3 event in Berlin, I
> would like to propose a coreboot hackaton at the 12,13 and 14 april in Paris.
> If all goes OK, we could take profit from the organisation of the event
> "Hackito Ergo Sum", wich takes place at the same dates in Paris. Hopefully
> there will be some kind of "hack area" like the "hackcenter" of the CCC
> Congress, where we could install our stuff. The guy I have meet told me that
> providing space for 6-7 people will be no problem.

Sounds good to me!

> Regarding the accomodation
> and other logistical details, unfortunately I can not give you more info
> yet. Now I would like to know if there are some coreboot people which are
> intersted by this ideea, and if enough persons are interested I will proceed
> with further organizatoric actions.

Yes maybe doing a doodle survey?

> By the way, Rudolph, do you plan to organize in 2012 a new hackaton in
> Prague? (For my part, I see no problem if there are 2 coreboot hackatons in
> 2012.. ;-))

Well not decided yet ;) Maybe again in October/September?
Lets concentrate on the Paris right now!

Thanks
Rudolf


-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot



From gerrit at coreboot.org  Thu Jan 12 13:26:30 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 12 Jan 2012 13:26:30 +0100
Subject: [coreboot] Patch merged into coreboot/master: 616b146 lib: add
	ram_check_nodie
References: <Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2+0@gerrit.coreboot.org>
Message-ID: <E1RlJjj-0005do-0Z@ra.coresystems.de>

the following patch was just integrated into master:
commit 616b146ce9c61753407b061c18a687807e4ba238
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:23:06 2011 +0100

    lib: add ram_check_nodie
    
    The current implementation calls die() if memory checking fails.
    This isn't always what we want: one might want to print error registers,
    or do some other error handling. Introduce ram_check_nodie() for that
    reason. It returns 0 if ram check succeeded, otherwise 1.
    
    Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Tue Jan 10 15:18:20 2012, giving +1
Reviewed-By: Sven Schnelle <svens at stackframe.org> at Thu Jan 12 13:26:29 2012, giving +2
See http://review.coreboot.org/532 for details.

-gerrit


From gerrit at coreboot.org  Thu Jan 12 19:47:54 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Thu, 12 Jan 2012 19:47:54 +0100
Subject: [coreboot] Patch set updated for coreboot: 756e343 Add Intel i5000
	Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+5@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 756e3431a04a62e2a205e5da56edc8eb5586023f
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig             |    1 +
 src/northbridge/intel/Makefile.inc        |    1 +
 src/northbridge/intel/i5000/Kconfig       |   38 +
 src/northbridge/intel/i5000/Makefile.inc  |   21 +
 src/northbridge/intel/i5000/chip.h        |   23 +
 src/northbridge/intel/i5000/northbridge.c |  188 ++++
 src/northbridge/intel/i5000/raminit.c     | 1660 +++++++++++++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h     |  328 ++++++
 src/northbridge/intel/i5000/udelay.c      |   84 ++
 9 files changed, 2344 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..31afe6a 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..c599dab 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..f1c87af
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on
+		Northbridge setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..3db755c
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t hecbase, amsize, tolm;
+	uint64_t ambase, memsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+
+	memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
+		      pci_read_config16(dev16_1, 0x84) & ~3);
+	memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
+
+	memsize <<= 24;
+	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
+	if (memsize > 0xe0000000) {
+		memsize -= 0xe0000000;
+		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
+		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
+	}
+
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..db732c6
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1660 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		int timeout = 1000;
+		do {
+			status = pci_read_config16(dev,	stsreg);
+			udelay(100);
+		} while(status & I5000_SPD_BUSY && timeout--);
+
+		if (status & I5000_SPD_SBE || !timeout)
+			return -1;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			out++;
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int div;
+
+	switch (d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		div = 375;
+		break;
+
+	default:
+		printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
+			d->setup->ddr_speed);
+
+	case DDR_667MHZ:
+		div = 300;
+		break;
+	}
+
+	return (del * 100) / div;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int val, div;
+
+	switch (d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		div = 375;
+		break;
+	default:
+		printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
+			d->setup->ddr_speed);
+
+	case DDR_667MHZ:
+		div = 300;
+		break;
+	}
+
+	val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div);
+	if ((val % 10) > 0)
+		val += 10;
+	return val / 10;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_INFO, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+			t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+			t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3);
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+	int timeout = 1000;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	do {
+		status = pci_read_config16(dev,	stsreg);
+		udelay(100);
+	} while((status & I5000_SPD_BUSY) && timeout--);
+
+	if (status & I5000_SPD_WOD && timeout)
+		return 0;
+
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+		d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	for(;;);
+	return -1;
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+	int timeout = 1000;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	do {
+		status = pci_read_config16(dev,	stsreg);
+		udelay(100);
+	} while((status & I5000_SPD_BUSY) && timeout--);
+
+	if ((status & I5000_SPD_RDO) && timeout)
+		*out = status & 0xff;
+
+	if (status & I5000_SPD_SBE || !timeout) {
+		printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n",
+			d->branch->num, d->channel->num, d->num, byte1, status);
+		for(;;);
+		return -1;
+	}
+	return 0;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+		d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	}
+
+	printk(BIOS_SPEW, "done\n");
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
+	       d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
+				      d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config8(d, 1, 0xea, 0);
+
+
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	int timeout = 10000;
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x,", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--)
+		udelay(10);
+
+	if (timeout) {
+		printk(BIOS_DEBUG, "done\n");
+		return;
+	}
+
+	printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n",
+		state, b->num);
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	printk(BIOS_INFO, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,
+	       pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	int i;
+	pci_mmio_write_config8(c->branch->branchdev,
+			       c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	for(i = 0; i < 4; i++) {
+		if (c->dimm[i].present)
+			i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? 0x21b1b : 0x20b1b);
+	}
+
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n",
+			d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = tref;
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	default:
+		break;
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+#endif
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
+{
+	i5000_amb_write_config32(d, 1, AMB_FERR,
+				 i5000_amb_read_config32(d, 1, AMB_FERR));
+	i5000_amb_write_config32(d, 1, AMB_NERR,
+				 i5000_amb_read_config32(d, 1, AMB_NERR));
+
+	i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int get_dmir(u8 *rankmap, int *_set, int limit)
+{
+        int i, dmir = 0, set = 0;
+
+        for(i = 7; set < limit && i >= 0; i--) {
+                if (!(*rankmap & (1 << i)))
+                        continue;
+
+                *rankmap &= ~(1 << i);
+
+                switch(limit) {
+                case 1:
+                        dmir |= (i |
+				 (i << 3) |
+				 (i << 6) |
+				 (i << 9));
+                        break;
+                case 2:
+                        dmir |= (i << (set * 3)) |
+                                (i << (6 + set * 3));
+                        break;
+                case 4:
+                        dmir |= (i << (set * 3));
+                        break;
+
+                default:
+                        break;
+                }
+                set++;
+        }
+        *_set = set;
+        return dmir;
+}
+
+static int i5000_setup_dmir(struct i5000_fbd_branch *b)
+{
+	struct i5000_fbdimm *d;
+	device_t dev = b->branchdev;
+	u8 rankmap = 0, dmir = 0;
+	u32 dmirval = 0;
+	int i, set, rankoffset = 0, ranksize = 0, ranks = 0;
+
+	if (!b->used)
+		return 0;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		rankmap >>= 2;
+		d = b->channel[0].dimm + i;
+
+		if (!d->present)
+			continue;
+
+		if (d->ranks == 2) {
+			rankmap |= 0xc0;
+			ranks += 2;
+		} else {
+			rankmap |= 0x40;
+			ranks++;
+		}
+	}
+
+	printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);
+
+	dmir = I5000_DMIR0;
+
+	ranksize = b->channel[0].dimm[0].size << 7;
+
+	if (b->channel[0].dimm[0].ranks == 2)
+		ranksize <<= 1;
+
+	if (b->setup->single_channel)
+		ranksize >>= 1;
+
+	while(ranks) {
+
+		if (ranks >= 4)
+			dmirval = get_dmir(&rankmap, &set, 4);
+		else if (ranks >= 2)
+			dmirval = get_dmir(&rankmap, &set, 2);
+		else
+			dmirval = get_dmir(&rankmap, &set, 1);
+
+		ranks -= set;
+
+		dmirval |= rankoffset + (set * ranksize);
+
+		rankoffset += (set * ranksize);
+		printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
+		       dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+		dmir += 4;
+	}
+
+	for(; dmir <= I5000_DMIR4; dmir += 4) {
+		printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
+		       dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+	}
+	return rankoffset;
+}
+
+static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
+
+	size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;
+	size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;
+
+        minsize = MIN(size0, size1);
+
+        if (size0 > size1) {
+                tmp = size1;
+                size1 = size0;
+                size0 = tmp;
+        }
+
+        if (size0 == size1) {
+                mir0 = (size0 << 1) | 3;
+                mir1 = (size0 << 1);
+                mir2 = (size0 << 1);
+        } else if (!size0) {
+                mir0 = size1 | 1;
+                mir1 = size1;
+                mir2 = size1;
+        } else {
+                mir0 = (size0 << 1) | 3;
+                mir1 = (size1 + size0) | 1;
+                mir2 = size1 + size0;
+        }
+
+        printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
+        printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
+        printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
+
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir0);
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir1);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir2);
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 tolm, drta, drtb, mc, mca;
+	int t_wrc, bl2;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		 setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		 (((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		/* Electrical throttling: 20 clocks */
+		((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	i5000_setup_interleave(setup);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting in spd_read */
+	setup->ddr_speed = DDR_667MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_try_restart(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+	outb(0x06, 0xcf9);
+	for(;;) asm volatile("hlt");
+}
+
+static void i5000_pam_setup(void)
+{
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(1000);
+	memset(&setup, 0, sizeof(setup));
+
+	pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		i5000_try_restart("Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_try_restart("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_try_restart("failed to enable auto refresh\n");
+
+	if (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		i5000_try_restart("Channel training failed\n");
+
+	i5000_clear_fbd_errors();
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+	i5000_pam_setup();
+
+	if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
+		i5000_try_restart("failed to clear error status\n");
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_try_restart("RAM verification failed");
+	}
+#endif
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..2e48238
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,328 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x54
+#define AMB_FBDLOCKTO 0x68
+#define AMB_EMASK 0x8c
+#define AMB_FERR 0x90
+#define AMB_NERR 0x94
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_MAX,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt[DDR_MAX];
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..6462fe0
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}


From gerrit at coreboot.org  Thu Jan 12 19:56:47 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Thu, 12 Jan 2012 19:56:47 +0100
Subject: [coreboot] Patch set updated for coreboot: 3ac759d Add Intel i5000
	Memory Controller Hub
References: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+0@gerrit.coreboot.org>
Message-ID: <Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb+6@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/491

-gerrit

commit 3ac759d09e7f4b3a7c877db6707ea1aa64ffc059
Author: Sven Schnelle <svens at stackframe.org>
Date:   Fri Dec 2 16:21:01 2011 +0100

    Add Intel i5000 Memory Controller Hub
    
    Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/Kconfig             |    1 +
 src/northbridge/intel/Makefile.inc        |    1 +
 src/northbridge/intel/i5000/Kconfig       |   38 +
 src/northbridge/intel/i5000/Makefile.inc  |   21 +
 src/northbridge/intel/i5000/chip.h        |   23 +
 src/northbridge/intel/i5000/northbridge.c |  188 ++++
 src/northbridge/intel/i5000/raminit.c     | 1660 +++++++++++++++++++++++++++++
 src/northbridge/intel/i5000/raminit.h     |  328 ++++++
 src/northbridge/intel/i5000/udelay.c      |   84 ++
 9 files changed, 2344 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 1809d11..31afe6a 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -10,3 +10,4 @@ source src/northbridge/intel/i82830/Kconfig
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/i5000/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 0d116d0..c599dab 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -11,3 +11,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig
new file mode 100644
index 0000000..f1c87af
--- /dev/null
+++ b/src/northbridge/intel/i5000/Kconfig
@@ -0,0 +1,38 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_I5000
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+
+config NORTHBRIDGE_INTEL_I5000_MEMBIST
+	bool
+	prompt "Run Memory selfcheck (MEMBIST) during initialization"
+	default y
+	help
+		FBDIMM memory modules have a controller called 'Advanced Memory
+		Buffer' which allows to test the Memories used on that module.
+		Select yes to do a quick memory check after AMBs have been
+		initialized. This option can be used to check if the Memory
+		module has been correctly initialized, without depending on
+		Northbridge setup.
+
+config NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	bool
+	prompt "Run ramcheck after RAM initialization"
diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc
new file mode 100644
index 0000000..a5623c0
--- /dev/null
+++ b/src/northbridge/intel/i5000/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+romstage-y += raminit.c udelay.c
diff --git a/src/northbridge/intel/i5000/chip.h b/src/northbridge/intel/i5000/chip.h
new file mode 100644
index 0000000..a23be90
--- /dev/null
+++ b/src/northbridge/intel/i5000/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_intel_i5000_config {
+};
+
+extern struct chip_operations northbridge_intel_i5000_ops;
diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c
new file mode 100644
index 0000000..3db755c
--- /dev/null
+++ b/src/northbridge/intel/i5000/northbridge.c
@@ -0,0 +1,188 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include "chip.h"
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x25d8,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+#if CONFIG_WRITE_HIGH_TABLES
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	struct resource *resource;
+	uint32_t hecbase, amsize, tolm;
+	uint64_t ambase, memsize;
+	int idx = 0;
+	device_t dev16_0 = dev_find_slot(0, PCI_DEVFN(16, 0));
+	device_t dev16_1 = dev_find_slot(0, PCI_DEVFN(16, 1));
+
+	tolm = pci_read_config16(dev_find_slot(0, PCI_DEVFN(16, 1)), 0x6c) << 16;
+	hecbase = pci_read_config16(dev16_0, 0x64) >> 12;
+	hecbase &= 0xffff;
+
+	ambase = ((u64)pci_read_config32(dev16_0, 0x48) |
+		  (u64)pci_read_config32(dev16_0, 0x4c) << 32);
+
+	amsize = pci_read_config32(dev16_0, 0x50);
+	ambase &= 0x000000ffffff0000;
+
+	printk(BIOS_DEBUG, "TOLM: 0x%08x AMBASE: 0x%016llx\n", tolm, ambase);
+
+	/* Report the memory regions */
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, ((tolm >> 10) - 768));
+
+	memsize = MAX(pci_read_config16(dev16_1, 0x80) & ~3,
+		      pci_read_config16(dev16_1, 0x84) & ~3);
+	memsize = MAX(memsize, pci_read_config16(dev16_1, 0x88) & ~3);
+
+	memsize <<= 24;
+	printk(BIOS_INFO, "MEMSIZE: %08llx\n", memsize);
+	if (memsize > 0xe0000000) {
+		memsize -= 0xe0000000;
+		printk(BIOS_INFO, "high memory: %lldMB\n", memsize / 1048576);
+		ram_resource(dev, idx++, 4096 * 1024, memsize / 1024);
+	}
+
+	if (hecbase) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar at 0x%016llx\n", (u64)hecbase << 28);
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)(uint64_t)hecbase << 28;
+		resource->size = (resource_t)256 * 1024 * 1024;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)(uint64_t)0xffe00000;
+	resource->size = (resource_t)0x200000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (ambase && amsize) {
+		resource = new_resource(dev, idx++);
+		resource->base = (resource_t)ambase;
+		resource->size = (resource_t)amsize;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+
+	/* add resource for 0xfe6xxxxx range. This range is used by i5000 for
+	   various fixed address registers (BOFL, SPAD, SPADS */
+	resource = new_resource(dev, idx++);
+	resource->base = (resource_t)0xfe600000;
+	resource->size = (resource_t)0x00100000;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = tolm - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size);
+#endif
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_i5000_ops = {
+	CHIP_NAME("Intel i5000 Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
new file mode 100644
index 0000000..9148d37
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -0,0 +1,1660 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "raminit.h"
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <spd.h>
+#include <types.h>
+#include <southbridge/intel/i63xx/early_smbus.c>
+#include <string.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <lib.h>
+#include <delay.h>
+
+static int i5000_for_each_channel(struct i5000_fbd_branch *branch,
+				  int (*cb)(struct i5000_fbd_channel *))
+{
+	struct i5000_fbd_channel *c;
+	int ret;
+
+	for(c = branch->channel; c < branch->channel + I5000_MAX_CHANNEL; c++)
+		if (c->used && (ret = cb(c)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_branch(struct i5000_fbd_setup *setup,
+				 int (*cb)(struct i5000_fbd_branch *))
+{
+	struct i5000_fbd_branch *b;
+	int ret;
+
+	for(b = setup->branch; b < setup->branch + I5000_MAX_BRANCH; b++)
+		if (b->used && (ret = cb(b)))
+			return ret;
+	return 0;
+}
+
+static int i5000_for_each_dimm(struct i5000_fbd_setup *setup,
+			       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if ((ret = cb(d))) {
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int i5000_for_each_dimm_present(struct i5000_fbd_setup *setup,
+				       int (*cb)(struct i5000_fbdimm *))
+{
+	struct i5000_fbdimm *d;
+	int ret, i;
+
+	for(i = 0; i < I5000_MAX_DIMMS; i++) {
+		d = setup->dimms[i];
+		if (d->present && (ret = cb(d)))
+			return ret;
+	}
+	return 0;
+}
+
+static int spd_read_byte(struct i5000_fbdimm *d, u8 addr, int count, u8 *out)
+{
+	u16 status;
+	device_t dev = d->branch->branchdev;
+
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+
+	while(count-- > 0) {
+		pci_write_config32(dev, cmdreg, 0xa8000000 |	\
+				   (d->num & 0x03) << 24 | addr++ << 16);
+
+		int timeout = 1000;
+		do {
+			status = pci_read_config16(dev,	stsreg);
+			udelay(100);
+		} while(status & I5000_SPD_BUSY && timeout--);
+
+		if (status & I5000_SPD_SBE || !timeout)
+			return -1;
+
+		if (status & I5000_SPD_RDO) {
+			*out = status & 0xff;
+			out++;
+		}
+	}
+	return 0;
+}
+
+static void i5000_clear_fbd_errors(void)
+{
+	device_t dev16_1, dev16_2;
+
+	dev16_1 = PCI_ADDR(0, 16, 1, 0);
+	dev16_2 = PCI_ADDR(0, 16, 2, 0);
+
+	pci_mmio_write_config32(dev16_1, I5000_EMASK_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_EMASK_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_FAT_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_FAT_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_NERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_NERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_1, I5000_FERR_NF_FBD,
+				pci_mmio_read_config32(dev16_1, I5000_FERR_NF_FBD));
+
+	pci_mmio_write_config32(dev16_2, I5000_FERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_FERR_GLOBAL));
+
+	pci_mmio_write_config32(dev16_2, I5000_NERR_GLOBAL,
+				pci_mmio_read_config32(dev16_2, I5000_NERR_GLOBAL));
+}
+
+static int i5000_branch_reset(struct i5000_fbd_branch *b)
+{
+	device_t dev = b->branchdev;
+
+	pci_write_config8(dev, I5000_FBDRST, 0x00);
+
+	udelay(5000);
+
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	udelay(1);
+	pci_write_config8(dev, I5000_FBDRST, 0x04);
+	udelay(2);
+	pci_write_config8(dev, I5000_FBDRST, 0x05);
+	pci_write_config8(dev, I5000_FBDRST, 0x07);
+	return 0;
+}
+
+static int delay_ns_to_clocks(struct i5000_fbdimm *d, int del)
+{
+	int div;
+
+	switch (d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		div = 375;
+		break;
+
+	default:
+		printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
+		       d->setup->ddr_speed);
+
+	case DDR_667MHZ:
+		div = 300;
+		break;
+	}
+
+	return (del * 100) / div;
+}
+
+static int mtb2clks(struct i5000_fbdimm *d, int del)
+{
+	int val, div;
+
+	switch (d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		div = 375;
+		break;
+	default:
+		printk(BIOS_ERR, "Invalid clock: %d, using 667MHz\n",
+		       d->setup->ddr_speed);
+
+	case DDR_667MHZ:
+		div = 300;
+		break;
+	}
+
+	val = (del * 1000 * d->mtb_dividend) / (d->mtb_divisor * div);
+	if ((val % 10) > 0)
+		val += 10;
+	return val / 10;
+}
+
+static int i5000_read_spd_data(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u8 addr, val, org, ftb, cas, t_ras_rc_h, t_rtp, t_wtr;
+	u8 bb, bl, t_wr, t_rp, t_rcd, t_rc, t_ras, t_aa_min;
+	u8 cmd2data_addr;
+	int t_ck_min;
+
+	s = d->setup;
+	if (spd_read_byte(d, SPD_MEMORY_TYPE, 1, &val)) {
+		printk(BIOS_INFO, "DIMM %d/%d/%d not present\n",
+		       d->branch->num, d->channel->num, d->num);
+		return 0; // No FBDIMM present
+	}
+
+	if (val != 0x09)
+		return 0; // SDRAM type not FBDIMM
+
+	if (spd_read_byte(d, 0x65, 14, d->amb_personality_bytes))
+		return 0;
+
+	switch(d->setup->ddr_speed) {
+	case DDR_533MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_533;
+		break;
+
+	case DDR_667MHZ:
+		cmd2data_addr = FBDIMM_SPD_CMD2DATA_667;
+		break;
+
+	default:
+		printk(BIOS_ERR, "Unsupported FBDIMM clock\n");
+		return -1;
+	}
+
+	if (spd_read_byte(d, FBDIMM_SPD_SDRAM_ADDRESSING, 1, &addr) ||
+	    spd_read_byte(d, FBDIMM_SPD_MODULE_ORGANIZATION, 1, &org) ||
+	    spd_read_byte(d, FBDIMM_SPD_FTB, 1, &ftb) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVIDEND, 1, &d->mtb_dividend) ||
+	    spd_read_byte(d, FBDIMM_SPD_MTB_DIVISOR, 1, &d->mtb_divisor) ||
+	    spd_read_byte(d, FBDIMM_SPD_MIN_TCK, 1, &d->t_ck_min) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WR, 1, &t_wr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RCD, 1, &t_rcd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RRD, 1, &d->t_rrd) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RP, 1, &t_rp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS_RC_MSB, 1, &t_ras_rc_h) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RAS, 1, (u8 *)&t_ras) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RC, 1, (u8 *)&t_rc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RFC, 2, (u8 *)&d->t_rfc) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_WTR, 1, &t_wtr) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_RTP, 1, &t_rtp) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_BB, 1, &bb) ||
+	    spd_read_byte(d, FBDIMM_SPD_BURST_LENGTHS_SUPPORTED, 1, &bl) ||
+	    spd_read_byte(d, FBDIMM_SPD_ODT, 1, &d->odt) ||
+	    spd_read_byte(d, FBDIMM_SPD_T_REFI, 1, &d->t_refi) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_LATENCIES, 1, &cas) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_533, 1, &d->cmd2datanxt[DDR_533MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CMD2DATA_667, 1, &d->cmd2datanxt[DDR_667MHZ]) ||
+	    spd_read_byte(d, FBDIMM_SPD_CAS_MIN_LATENCY, 1, &t_aa_min)) {
+		printk(BIOS_ERR, "failed to read data from SPD\n");
+		return 0;
+	}
+
+
+	t_ck_min = (d->t_ck_min * 100) / d->mtb_divisor;
+	if (t_ck_min <= 300)
+		d->speed = DDR_667MHZ;
+	else if (t_ck_min <= 375)
+		d->speed = DDR_533MHZ;
+	else {
+		printk(BIOS_ERR, "Unsupported t_ck_min: %d\n", t_ck_min);
+		return -1;
+	}
+
+	d->sdram_width = org & 0x07;
+	if (d->sdram_width > 1) {
+		printk(BIOS_ERR, "SDRAM width %d not supported\n", d->sdram_width);
+		return 0;
+	}
+
+	s->ddr_speed = MIN(s->ddr_speed, d->speed);
+
+	d->banks = 4 << (addr & 0x03);
+	d->columns = 9 + ((addr >> 2) & 0x03);
+	d->rows = 12 + ((addr >> 5) & 0x03);
+	d->ranks = (org >> 3) & 0x03;
+	d->min_cas_latency = cas & 0x0f;
+
+	d->setup->bl &= bl;
+
+	if (!d->setup->bl) {
+		printk(BIOS_ERR, "no compatible burst length found\n");
+		return -1;
+	}
+
+	s->t_rc = MAX(s->t_rc, mtb2clks(d,
+					t_rc | ((t_ras_rc_h & 0xf0) << 4)));
+	s->t_rrd = MAX(s->t_rrd, mtb2clks(d, d->t_rrd));
+	s->t_rfc = MAX(s->t_rfc, mtb2clks(d, d->t_rfc));
+	s->t_rcd = MAX(s->t_rcd, mtb2clks(d, t_rcd));
+	s->t_cl = MAX(s->t_cl, mtb2clks(d, t_aa_min));
+	s->t_wr = MAX(s->t_wr, mtb2clks(d, t_wr));
+	s->t_rp = MAX(s->t_rp, mtb2clks(d, t_rp));
+	s->t_rtp = MAX(s->t_rtp, mtb2clks(d, t_rtp));
+	s->t_wtr = MAX(s->t_wtr, mtb2clks(d, t_wtr));
+	s->t_ras = MAX(s->t_ras, mtb2clks(d,
+					  t_ras | ((t_ras_rc_h & 0x0f) << 8)));
+	s->t_r2r = MAX(s->t_r2r, bb & 3);
+	s->t_r2w = MAX(s->t_r2w, (bb >> 4) & 3);
+	s->t_w2r = MAX(s->t_w2r, (bb >> 2) & 3);
+
+	d->size = (1 << (d->banks + d->columns + d->rows + d->ranks)) >> 20;
+	d->branch->totalmem += d->size;
+	s->totalmem += d->size;
+
+	d->channel->columns = d->columns;
+	d->channel->rows = d->rows;
+	d->channel->ranks = d->ranks;
+	d->channel->banks = d->banks;
+	d->channel->width = d->sdram_width;
+
+	printk(BIOS_INFO, "DIMM %d/%d/%d %dMB: %d banks, "
+	       "%d columns, %d rows, %d ranks\n",
+	       d->branch->num, d->channel->num, d->num, d->size,
+	       d->banks, d->columns, d->rows, d->ranks);
+
+	d->present = 1;
+	d->branch->used |= 1;
+	d->channel->used |= 1;
+	d->channel->highest_amb = d->num;
+	return 0;
+}
+
+static int i5000_amb_smbus_write(struct i5000_fbdimm *d,  int byte1, int byte2)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+	int timeout = 1000;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16) | (byte2 << 8) | 1);
+
+	do {
+		status = pci_read_config16(dev,	stsreg);
+		udelay(100);
+	} while((status & I5000_SPD_BUSY) && timeout--);
+
+	if (status & I5000_SPD_WOD && timeout)
+		return 0;
+
+	printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n",
+	       d->branch->num, d->channel->num, d->num, byte1, byte2, status);
+	for(;;);
+	return -1;
+}
+
+static int i5000_amb_smbus_read(struct i5000_fbdimm *d, int byte1, u8 *out)
+{
+	u16 status;
+	device_t dev = PCI_DEV(0, d->branch->num ? 22 : 21, 0);
+	int cmdreg = d->channel->num ? I5000_SPDCMD1 : I5000_SPDCMD0;
+	int stsreg = d->channel->num ? I5000_SPD1 : I5000_SPD0;
+	int timeout = 1000;
+
+	pci_write_config32(dev, cmdreg, 0xb8000000 | ((d->num & 0x03) << 24) |
+			   (byte1 << 16));
+
+	do {
+		status = pci_read_config16(dev,	stsreg);
+		udelay(100);
+	} while((status & I5000_SPD_BUSY) && timeout--);
+
+	if ((status & I5000_SPD_RDO) && timeout)
+		*out = status & 0xff;
+
+	if (status & I5000_SPD_SBE || !timeout) {
+		printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x status %04x\n",
+		       d->branch->num, d->channel->num, d->num, byte1, status);
+		for(;;);
+		return -1;
+	}
+	return 0;
+
+}
+
+static int i5000_amb_smbus_write_config8(struct i5000_fbdimm *d,
+					 int fn, int reg, u8 val)
+{
+	if (i5000_amb_smbus_write(d, 0x84, 00) ||
+	    i5000_amb_smbus_write(d, 0x04, fn) ||
+	    i5000_amb_smbus_write(d, 0x04, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x04, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x44, val)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config16(struct i5000_fbdimm *d,
+					  int fn, int reg, u16 val)
+{
+	if (i5000_amb_smbus_write(d, 0x88, 00) ||
+	    i5000_amb_smbus_write(d, 0x08, fn) ||
+	    i5000_amb_smbus_write(d, 0x08, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x08, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x48, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_write_config32(struct i5000_fbdimm *d,
+					  int fn, int reg, u32 val)
+{
+	if (i5000_amb_smbus_write(d, 0x8c, 00) ||
+	    i5000_amb_smbus_write(d, 0x0c, fn) ||
+	    i5000_amb_smbus_write(d, 0x0c, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, reg & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 24) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 16) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x0c, (val >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x4c, val & 0xff)) {
+		printk(BIOS_ERR, "AMB SMBUS write failed\n");
+		return 1;
+	}
+	return 0;
+}
+
+static int i5000_amb_smbus_read_config32(struct i5000_fbdimm *d,
+					 int fn, int reg, u32 *val)
+{
+	u8 byte3, byte2, byte1, byte0;
+
+	if (i5000_amb_smbus_write(d, 0x80, 00) ||
+	    i5000_amb_smbus_write(d, 0x00, fn) ||
+	    i5000_amb_smbus_write(d, 0x00, (reg >> 8) & 0xff) ||
+	    i5000_amb_smbus_write(d, 0x40, reg & 0xff) ||
+	    i5000_amb_smbus_read(d, 0x80, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte3) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte2) ||
+	    i5000_amb_smbus_read(d, 0x00, &byte1) ||
+	    i5000_amb_smbus_read(d, 0x40, &byte0)) {
+		printk(BIOS_ERR, "AMB SMBUS read failed\n");
+		return 1;
+	}
+	*val = (byte3 << 24) | (byte2 << 16) | (byte1 << 8) | byte0;
+	return 0;
+}
+
+static void i5000_amb_write_config8(struct i5000_fbdimm *d,
+				    int fn, int reg, u32 val)
+{
+	write8(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config16(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write16(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static void i5000_amb_write_config32(struct i5000_fbdimm *d,
+				     int fn, int reg, u32 val)
+{
+	write32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg), val);
+}
+
+static u32 i5000_amb_read_config32(struct i5000_fbdimm *d,
+				   int fn, int reg)
+{
+	return read32(DEFAULT_AMBASE + AMB_ADDR(d->ambase, fn, reg));
+}
+
+static int ddr_command(struct i5000_fbdimm *d, int rank, u32 addr, u32 command)
+{
+	u32 drc, status;
+
+	printk(BIOS_SPEW, "DIMM %d/%d/%d: rank %d: sending command %x (addr %08x)...",
+	       d->branch->num, d->channel->num, d->num, rank, command, addr);
+
+	drc = i5000_amb_read_config32(d, 3, AMB_DRC);
+	drc &= ~((3 << 9) | (1 << 12));
+	drc |= (rank << 9);
+
+	i5000_amb_write_config32(d, 3, AMB_DRC, drc);
+	i5000_amb_write_config32(d, 4, AMB_DCALADDR, addr);
+	i5000_amb_write_config32(d, 4, AMB_DCALCSR,
+				 (rank << 21) | (command & 0x0f) | AMB_DCALCSR_START);
+
+	udelay(1000);
+	while((status = (i5000_amb_read_config32(d, 4, AMB_DCALCSR)))
+	      & (1 << 31));
+
+	if (status & (1 << 30)) {
+		printk(BIOS_SPEW, "failed (status 0x%08x)\n", status);
+		return -1;
+	}
+
+	printk(BIOS_SPEW, "done\n");
+	return 0;
+}
+
+static int i5000_ddr_calibration(struct i5000_fbdimm *d)
+{
+	u32 status;
+
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80100050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x80200050);
+	while((status = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31));
+
+	if (ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL) ||
+	    ddr_command(d, 3, 0, AMB_DCALCSR_OPCODE_DQS_DELAY_CAL))
+		return -1;
+	return 0;
+}
+
+static int i5000_ddr_init(struct i5000_fbdimm *d)
+{
+
+	int rank;
+	u32 val;
+	u8 odt;
+
+	for(rank = 0; rank < d->ranks; rank++) {
+		printk(BIOS_DEBUG, "%s: %d/%d/%d rank %d\n", __func__,
+		       d->branch->num, d->channel->num, d->num, rank);
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_NOP))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		/* EMRS(2) */
+		if (ddr_command(d, 1 << rank,
+				2, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(3) */
+		if (ddr_command(d, 1 << rank,
+				3, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* EMRS(1) */
+		if (ddr_command(d, 1 << rank,
+				1, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* MRS: DLL reset */
+		if (ddr_command(d, 1 << rank,
+				0x1000000, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		udelay(200);
+
+		if (ddr_command(d, 1 << rank,
+				0x4000000, AMB_DCALCSR_OPCODE_PRECHARGE))
+			return -1;
+
+		if (ddr_command(d, 1 << rank,
+				0, AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		if (ddr_command(d, 1 << rank, 0,
+				AMB_DCALCSR_OPCODE_REFRESH))
+			return -1;
+
+		/* burst length + cas latency */
+		val = (((d->setup->bl & BL_BL8) ? 3 : 2) << 16) |
+			(1 << 19) /* interleaved burst */ |
+			(d->setup->t_cl << 20) |
+			(((d->setup->t_wr - 1) & 7) << 25);
+
+		printk(BIOS_DEBUG, "MRS: 0x%08x\n", val);
+		if (ddr_command(d, 1 << rank,
+				val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+		/* OCD calibration default */
+		if (ddr_command(d, 1 << rank, 0x03800001,
+				AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+
+
+		odt = d->odt;
+		if (rank)
+			odt >>= 4;
+
+		val = (d->setup->t_al << 19) |
+			((odt & 1) << 18) |
+		        ((odt & 2) << 21) | 1;
+
+		printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
+
+		/* ODT, OCD exit, additive latency */
+		if (ddr_command(d, 1 << rank, val, AMB_DCALCSR_OPCODE_MRS_EMRS))
+			return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_preinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+	u32 id, drc;
+
+	printk(BIOS_DEBUG, "%s: %d/%d/%d\n", __func__,
+	       d->branch->num, d->channel->num, d->num);
+
+	i5000_amb_smbus_write_config32(d, 1, 0xb0, p32[0]);
+	i5000_amb_smbus_write_config16(d, 1, 0xb4, p16[2]);
+
+	drc = (d->setup->t_al << 4) | (d->setup->t_cl);
+	printk(BIOS_SPEW, "DRC: %02X, CMD2DATANXT: %02x\n", drc,
+	       d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDSBCFGNXT, 0x20909);
+	i5000_amb_smbus_write_config32(d, 1, AMB_FBDLOCKTO, 0x1651);
+	i5000_amb_smbus_write_config8(d, 1, AMB_CMD2DATANXT,
+				      d->cmd2datanxt[d->setup->ddr_speed]);
+	i5000_amb_smbus_write_config8(d, 1, 0xea, 0);
+
+
+	i5000_amb_smbus_write_config8(d, 3, AMB_DRC, drc);
+
+	if (!i5000_amb_smbus_read_config32(d, 0, 0, &id)) {
+		d->vendor = id & 0xffff;
+		d->device = id >> 16;
+	}
+
+	pci_mmio_write_config8(d->branch->branchdev,
+			       d->channel->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x04);
+	return 0;
+}
+
+static void i5000_fbd_next_state(struct i5000_fbd_branch *b, int state)
+{
+	int timeout = 10000;
+	device_t dev = b->branchdev;
+
+	printk(BIOS_DEBUG, "  FBD state branch %d: %02x,", b->num, state);
+
+	pci_mmio_write_config8(dev, I5000_FBDHPC, state);
+
+	printk(BIOS_DEBUG, "waiting for new state...");
+
+	while(pci_mmio_read_config8(dev, I5000_FBDST) != state && timeout--)
+		udelay(10);
+
+	if (timeout) {
+		printk(BIOS_DEBUG, "done\n");
+		return;
+	}
+
+	printk(BIOS_ERR, "timeout while entering state %02x on branch %d\n",
+	       state, b->num);
+}
+
+static int i5000_wait_pattern_recognized(struct i5000_fbd_channel *c)
+{
+	int i = 10;
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDISTS1 : I5000_FBDISTS0);
+
+	printk(BIOS_DEBUG, "      waiting for pattern recognition...");
+	while(pci_mmio_read_config16(dev, 0) != 0x1fff && --i > 0)
+		udelay(5000);
+
+	printk(BIOS_DEBUG, i ?  "done\n" : "failed\n");
+	printk(BIOS_INFO, "%d/%d Round trip latency: %d\n", c->branch->num, c->num,
+	       pci_mmio_read_config8(c->branch->branchdev, c->num ? I5000_FBDLVL1 : I5000_FBDLVL0) & 0x3f);
+	return !i;
+}
+
+static const char *pattern_names[16] = {
+	"EI", "EI", "EI", "EI",
+	"EI", "EI", "EI", "EI",
+	"TS0", "TS1", "TS2", "TS3",
+	"RESERVED", "TS2 (merge disabled)", "TS2 (merge enabled)","All ones",
+};
+
+static int i5000_drive_pattern(struct i5000_fbd_channel *c, int pattern, int wait)
+{
+	device_t dev = PCI_ADDR(0, c->branch->num ? 22 : 21, 0,
+				c->num ? I5000_FBDICMD1 : I5000_FBDICMD0);
+
+	printk(BIOS_DEBUG, "    %d/%d  driving pattern %s to AMB%d (%02x)\n",
+	       c->branch->num, c->num,
+	       pattern_names[(pattern >> 4) & 0xf], pattern & 3, pattern);
+	pci_mmio_write_config8(dev, 0, pattern);
+
+	if (!wait)
+		return 0;
+
+	return i5000_wait_pattern_recognized(c);
+}
+
+static int i5000_set_ambpresent(struct i5000_fbd_channel *c)
+{
+	int i;
+	device_t branchdev = c->branch->branchdev;
+	u16 ambpresent = 0x8000;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		if (c->dimm[i].present)
+			ambpresent |= (1 << i);
+	}
+
+	printk(BIOS_DEBUG, "AMBPRESENT: %04x\n", ambpresent);
+	pci_write_config16(branchdev,
+			   c->num ?
+			   I5000_AMBPRESENT1 :		\
+			   I5000_AMBPRESENT0, ambpresent);
+
+	return 0;
+}
+
+
+static int i5000_drive_test_patterns(struct i5000_fbd_channel *c, int highest_amb, int mchpad)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->num ? 0x100 : 0;
+	u32 portctl;
+	int i, cnt = 1000;
+
+	portctl = pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off);
+	portctl &= ~0x01000020;
+	if (mchpad)
+		portctl |= 0x00800000;
+	else
+		portctl &= ~0x00800000;
+	portctl &= ~0x01000020;
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBPORTCTL + off, portctl);
+
+	/* drive calibration patterns */
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS0 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS1 | highest_amb, 1))
+		return -1;
+
+	while (!(pci_mmio_read_config32(branchdev, I5000_FBD0IBPORTCTL + off) & 4) && cnt--)
+		udelay(1000);
+
+	if (!cnt) {
+		printk(BIOS_ERR, "IBIST timeout\n");
+		return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	for(i = 0; i < highest_amb; i++) {
+		if ((i5000_drive_pattern(c, I5000_FBDICMD_TS2_NOMERGE | i, 1)))
+			return -1;
+	}
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS2 | highest_amb, 1))
+		return -1;
+
+	if (i5000_drive_pattern(c, I5000_FBDICMD_TS3 | highest_amb, 1))
+		return -1;
+
+	if (i5000_set_ambpresent(c))
+		return -1;
+	return 0;
+}
+
+static int i5000_train_channel_idle(struct i5000_fbd_channel *c)
+{
+	int i;
+	pci_mmio_write_config8(c->branch->branchdev,
+			       c->num ? I5000_FBDSBTXCFG1 : I5000_FBDSBTXCFG0, 0x05);
+
+	for(i = 0; i < 4; i++) {
+		if (c->dimm[i].present)
+			i5000_amb_smbus_write_config32(c->dimm + i, 1, AMB_FBDSBCFGNXT, i ? 0x21b1b : 0x20b1b);
+	}
+
+	return i5000_drive_pattern(c, I5000_FBDICMD_IDLE, 1);
+}
+
+static int i5000_drive_test_patterns0(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 0);
+}
+
+static int i5000_drive_test_patterns1(struct i5000_fbd_channel *c)
+{
+	if (i5000_train_channel_idle(c))
+		return -1;
+
+	return i5000_drive_test_patterns(c, c->highest_amb, 1);
+}
+
+static int i5000_setup_channel(struct i5000_fbd_channel *c)
+{
+	device_t branchdev = c->branch->branchdev;
+	int off = c->branch->num ? 0x100 : 0;
+	u32 val;
+
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXPAT2EN + off, 0);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBTXMSK + off, 0x3ff);
+	pci_mmio_write_config32(branchdev, I5000_FBD0IBRXMSK + off, 0x1fff);
+
+	pci_mmio_write_config16(branchdev, off + 0x0162, c->used ? 0x20db : 0x18db);
+
+	/* unknown */
+	val = pci_mmio_read_config32(branchdev, off + 0x0164);
+	val &= 0xfffbcffc;
+	val |= 0x4004;
+	pci_mmio_write_config32(branchdev, off + 0x164, val);
+
+	pci_mmio_write_config32(branchdev, off + 0x15c, 0xff);
+	i5000_drive_pattern(c, I5000_FBDICMD_ALL_ONES, 0);
+	return 0;
+}
+
+static int i5000_link_training0(struct i5000_fbd_branch *b)
+{
+	device_t branchdev = b->branchdev;
+
+	pci_mmio_write_config8(branchdev, I5000_FBDPLLCTRL, b->used ? 0 : 1);
+
+	if (i5000_for_each_channel(b, i5000_setup_channel))
+		return -1;
+
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns0))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+static int i5000_link_training1(struct i5000_fbd_branch *b)
+{
+	if (i5000_for_each_channel(b, i5000_train_channel_idle))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_INIT);
+
+	if (i5000_for_each_channel(b, i5000_drive_test_patterns1))
+		return -1;
+
+	i5000_fbd_next_state(b, I5000_FBDHPC_STATE_READY);
+	return 0;
+}
+
+
+static int i5000_amb_check(struct i5000_fbdimm *d)
+{
+	u32 id = i5000_amb_read_config32(d, 0, 0);
+	printk(BIOS_DEBUG, "AMB %d/%d/%d ID: %04x:%04x\n",
+	       d->branch->num, d->channel->num, d->num,
+	       id & 0xffff, id >> 16);
+
+	if ((id & 0xffff) != d->vendor || id >> 16 != d->device) {
+		printk(BIOS_ERR, "AMB mapping failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int i5000_amb_postinit(struct i5000_fbdimm *d)
+{
+	u32 *p32 = (u32 *)d->amb_personality_bytes;
+	u16 *p16 = (u16 *)d->amb_personality_bytes;
+
+	i5000_amb_write_config16(d, 1, 0xb6, p16[3]);
+	i5000_amb_write_config32(d, 1, 0xb8, p32[2]);
+	i5000_amb_write_config16(d, 1, 0xbc, p16[6]);
+	return 0;
+}
+
+static int i5000_amb_dram_timing_init(struct i5000_fbdimm *d)
+{
+	struct i5000_fbd_setup *s;
+	u32 val, tref;
+	int refi;
+
+	s = d->setup;
+
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d config:\n",
+	       d->branch->num, d->channel->num, d->num);
+
+	val = 0x44;
+	printk(BIOS_DEBUG, "\tDDR2ODTC: 0x%02x\n", val);
+	i5000_amb_write_config8(d, 4, AMB_DDR2ODTC, val);
+
+	val = (0x0c << 24) | /* CLK control */
+		(1 << 18) | /* ODTZ enabled */
+		(((d->setup->bl & BL_BL8) ? 1 : 0) << 8) | /* 8 byte burst length supported */
+		((d->setup->t_al & 0x0f) << 4) | /* additive latency */
+		(d->setup->t_cl & 0x0f); /* CAS latency */
+
+	if (d->ranks > 1) {
+		val |= (0x03 << 9);
+	} else {
+		val |= (0x01 << 9);
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRC, val);
+
+	val = (d->sdram_width << 30) |
+		((d->ranks == 2 ? 1 : 0) << 29) |
+		((d->banks == 8 ? 1 : 0) << 28) |
+		((d->rows - 13) << 26) |
+		((d->columns - 10) << 24) |
+		(1 << 16) | /* Auto refresh exit */
+		(0x27 << 8) | /* t_xsnr */
+		(d->setup->t_rp << 4) |
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor) & 0x0f);
+
+	printk(BIOS_DEBUG, "\tAMB_DSREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, val);
+
+	tref = 15;
+
+	switch(d->t_refi & 0x0f) {
+	case 0:
+		refi = 15625;
+		break;
+	case 1:
+		refi = 3900;
+		tref = 3;
+		break;
+	case 2:
+		refi = 7800;
+		tref = 7;
+		break;
+	case 3:
+		refi = 31250;
+		break;
+	case 4:
+		refi = 62500;
+		break;
+	case 5:
+		refi = 125000;
+		break;
+	default:
+		printk(BIOS_ERR, "unsupported t_refi value: %d, using 7.8us\n",
+		       d->t_refi & 0x0f);
+		refi = 7800;
+		break;
+	}
+
+	s->t_ref = tref;
+	val = delay_ns_to_clocks(d, refi) | (s->t_rfc << 16);
+	printk(BIOS_DEBUG, "\tAMB_DAREFTC: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC, val);
+
+	u8 t_r2w = ((s->bl & BL_BL8) ? 4 : 2) +
+		(((d->t_ck_min * d->mtb_dividend) / d->mtb_divisor));
+	u8 t_w2r = (s->t_cl - 1) + ((s->bl & BL_BL8) ? 4 : 2) + s->t_wtr;
+
+	val = ((6 - s->t_rp) << 8) | ((6 - s->t_rcd) << 10) |
+		((26 - s->t_rc) << 12) | ((9 - s->t_wr) << 16) |
+		((12 - t_w2r) << 20) | ((10 - t_r2w) << 24) |
+		((s->t_rtp - 2) << 27);
+
+	switch(s->t_ras) {
+	case 15:
+		val |= (1 << 29);
+		break;
+	case 12:
+		val |= (2 << 29);
+		break;
+	default:
+		break;
+	}
+
+	printk(BIOS_DEBUG, "\tAMB_DRT: %08x\n", val);
+	i5000_amb_write_config32(d, 3, AMB_DRT, val);
+	return 0;
+}
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+static int i5000_do_amb_membist_start(struct i5000_fbdimm *d, int rank, int pattern)
+{
+	printk(BIOS_DEBUG, "DIMM %d/%d/%d rank %d pattern %d\n",
+	       d->branch->num, d->channel->num, d->num, rank, pattern);
+
+	i5000_amb_write_config32(d, 3, AMB_DAREFTC,
+				 i5000_amb_read_config32(d, 3, AMB_DAREFTC) | 0x8000);
+
+	i5000_amb_write_config32(d, 3, AMB_MBLFSRSED, 0x12345678);
+	i5000_amb_write_config32(d, 3, AMB_MBADDR, 0);
+	i5000_amb_write_config32(d, 3, AMB_MBCSR, 0x800000f0 | (rank << 20) | ((pattern & 3) << 8));
+	return 0;
+}
+
+static int i5000_do_amb_membist_status(struct i5000_fbdimm *d, int rank)
+{
+	int cnt = 1000;
+	u32 res;
+
+	while((res = i5000_amb_read_config32(d, 3, AMB_MBCSR)) & (1 << 31) && cnt--)
+		udelay(1000);
+
+	if (cnt && !(res & (1 << 30)))
+		return 0;
+
+	printk(BIOS_ERR, "DIMM %d/%d/%d rank %d failed membist check\n",
+	       d->branch->num, d->channel->num, d->num, rank);
+	return -1;
+}
+
+static int i5000_amb_membist_random1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_random2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 3))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero1_start(struct i5000_fbdimm *d)
+{
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 1, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_zero2_start(struct i5000_fbdimm *d)
+{
+
+	if (d->ranks < 2)
+		return 0;
+	/* MEMBIST check with random seed */
+	if (i5000_do_amb_membist_start(d, 2, 0))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status1(struct i5000_fbdimm *d)
+{
+	if (i5000_do_amb_membist_status(d, 1))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_status2(struct i5000_fbdimm *d)
+{
+	if (d->ranks < 2)
+		return 0;
+
+	if (i5000_do_amb_membist_status(d, 2))
+		return -1;
+	return 0;
+}
+
+static int i5000_amb_membist_end(struct i5000_fbdimm *d)
+{
+	printk(BIOS_DEBUG, "AMB_DRC MEMBIST: %08x\n", i5000_amb_read_config32(d, 3, AMB_DRC));
+	return 0;
+}
+
+static int i5000_membist(struct i5000_fbd_setup *setup)
+{
+	return i5000_for_each_dimm_present(setup, i5000_amb_membist_random1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero1_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status1) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_random2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_zero2_start) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_status2) ||
+		i5000_for_each_dimm_present(setup, i5000_amb_membist_end);
+}
+#endif
+
+static int i5000_enable_mc_autorefresh(struct i5000_fbdimm *d)
+{
+	u32 tmp = i5000_amb_read_config32(d, 3, AMB_DSREFTC);
+	tmp &= ~(1 << 16);
+	printk(BIOS_DEBUG, "new AMB_DSREFTC: 0x%08x\n", tmp);
+	i5000_amb_write_config32(d, 3, AMB_DSREFTC, tmp);
+	return 0;
+}
+
+static int i5000_amb_clear_error_status(struct i5000_fbdimm *d)
+{
+	i5000_amb_write_config32(d, 1, AMB_FERR,
+				 i5000_amb_read_config32(d, 1, AMB_FERR));
+	i5000_amb_write_config32(d, 1, AMB_NERR,
+				 i5000_amb_read_config32(d, 1, AMB_NERR));
+
+	i5000_amb_write_config32(d, 1, AMB_EMASK, 0xf2);
+	return 0;
+}
+
+static void i5000_program_mtr(struct i5000_fbd_channel *c, int mtr)
+{
+	u32 val;
+
+	if (c->dimm[0].present || c->dimm[1].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 2) |
+		       (((c->ranks == 2) ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR0: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr, val);
+	}
+
+	if (c->dimm[2].present || c->dimm[3].present) {
+		val = (((c->columns - 10) & 3) |
+		       (((c->rows - 13) & 3) << 4) |
+		       ((c->ranks ? 1 : 0) << 4) |
+		       (((c->banks == 8) ? 1 : 0) << 5) |
+		       ((c->width ? 1 : 0) << 6) |
+		       (1 << 7) | /* Electrical Throttling enabled */
+		       (1 << 8)); /* DIMM present and compatible */
+		printk(BIOS_DEBUG, "MTR1: %04x\n", val);
+		pci_mmio_write_config16(c->branch->branchdev, mtr+2, val);
+	}
+}
+
+static int get_dmir(u8 *rankmap, int *_set, int limit)
+{
+	int i, dmir = 0, set = 0;
+
+	for(i = 7; set < limit && i >= 0; i--) {
+		if (!(*rankmap & (1 << i)))
+			continue;
+
+		*rankmap &= ~(1 << i);
+
+		switch(limit) {
+		case 1:
+			dmir |= (i |
+				 (i << 3) |
+				 (i << 6) |
+				 (i << 9));
+			break;
+		case 2:
+			dmir |= (i << (set * 3)) |
+				(i << (6 + set * 3));
+			break;
+		case 4:
+			dmir |= (i << (set * 3));
+			break;
+
+		default:
+			break;
+		}
+		set++;
+	}
+	*_set = set;
+	return dmir;
+}
+
+static int i5000_setup_dmir(struct i5000_fbd_branch *b)
+{
+	struct i5000_fbdimm *d;
+	device_t dev = b->branchdev;
+	u8 rankmap = 0, dmir = 0;
+	u32 dmirval = 0;
+	int i, set, rankoffset = 0, ranksize = 0, ranks = 0;
+
+	if (!b->used)
+		return 0;
+
+	for(i = 0; i < I5000_MAX_DIMM_PER_CHANNEL; i++) {
+		rankmap >>= 2;
+		d = b->channel[0].dimm + i;
+
+		if (!d->present)
+			continue;
+
+		if (d->ranks == 2) {
+			rankmap |= 0xc0;
+			ranks += 2;
+		} else {
+			rankmap |= 0x40;
+			ranks++;
+		}
+	}
+
+	printk(BIOS_DEBUG, "total ranks: %d, rankmap: %02x\n", ranks, rankmap);
+
+	dmir = I5000_DMIR0;
+
+	ranksize = b->channel[0].dimm[0].size << 7;
+
+	if (b->channel[0].dimm[0].ranks == 2)
+		ranksize <<= 1;
+
+	if (b->setup->single_channel)
+		ranksize >>= 1;
+
+	while(ranks) {
+
+		if (ranks >= 4)
+			dmirval = get_dmir(&rankmap, &set, 4);
+		else if (ranks >= 2)
+			dmirval = get_dmir(&rankmap, &set, 2);
+		else
+			dmirval = get_dmir(&rankmap, &set, 1);
+
+		ranks -= set;
+
+		dmirval |= rankoffset + (set * ranksize);
+
+		rankoffset += (set * ranksize);
+		printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
+		       dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+		dmir += 4;
+	}
+
+	for(; dmir <= I5000_DMIR4; dmir += 4) {
+		printk(BIOS_DEBUG, "DMIR%d: %08x\n", (dmir - I5000_DMIR0) >> 2,
+		       dmirval);
+		pci_mmio_write_config32(dev, dmir, dmirval);
+	}
+	return rankoffset;
+}
+
+static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 mir0, mir1, mir2, size0, size1, minsize, tmp;
+
+	size0 = i5000_setup_dmir(&setup->branch[1]) >> 12;
+	size1 = i5000_setup_dmir(&setup->branch[0]) >> 12;
+
+	minsize = MIN(size0, size1);
+
+	if (size0 > size1) {
+		tmp = size1;
+		size1 = size0;
+		size0 = tmp;
+	}
+
+	if (size0 == size1) {
+		mir0 = (size0 << 1) | 3;
+		mir1 = (size0 << 1);
+		mir2 = (size0 << 1);
+        } else if (!size0) {
+		mir0 = size1 | 1;
+		mir1 = size1;
+		mir2 = size1;
+	} else {
+		mir0 = (size0 << 1) | 3;
+		mir1 = (size1 + size0) | 1;
+		mir2 = size1 + size0;
+	}
+
+	printk(BIOS_DEBUG, "MIR0: %04x\n", mir0);
+	printk(BIOS_DEBUG, "MIR1: %04x\n", mir1);;
+	printk(BIOS_DEBUG, "MIR2: %04x\n", mir2);;
+
+	pci_mmio_write_config16(dev16, I5000_MIR0, mir0);
+	pci_mmio_write_config16(dev16, I5000_MIR1, mir1);
+	pci_mmio_write_config16(dev16, I5000_MIR2, mir2);
+}
+
+static int i5000_dram_timing_init(struct i5000_fbd_setup *setup)
+{
+	device_t dev16 = PCI_ADDR(0, 16, 1, 0);
+	u32 tolm, drta, drtb, mc, mca;
+	int t_wrc, bl2;
+
+	bl2 = (setup->bl & BL_BL8) ? 4 :2;
+	t_wrc = setup->t_rcd + (setup->t_cl - 1) + bl2 +
+		setup->t_wr + setup->t_rp;
+
+	drta = (setup->t_ref & 0x0f) |
+		((setup->t_rrd & 0x0f) << 4) |
+		((setup->t_rfc & 0xff) << 8) |
+		((setup->t_rc & 0x3f) << 16) |
+		((t_wrc & 0x3f) << 22) |
+		(setup->t_al & 0x07) << 28;
+
+	drtb = (bl2) |
+		(((1 + bl2 + setup->t_r2r) & 0x0f) << 4) |
+		(((setup->t_cl - 1 + bl2 + setup->t_wtr) & 0x0f) << 8) |
+		(((2 + bl2 + setup->t_r2w) & 0x0f) << 12) |
+		(((bl2 + setup->t_w2rdr) & 0x07) << 16);
+
+	mc = (1 << 30) | /* enable retry */
+		(3 << 25) | /* bad RAM threshold */
+		(1 << 21) | /* INITDONE */
+		(1 << 20) | /* FSB enable */
+		/* Electrical throttling: 20 clocks */
+		((setup->ddr_speed == DDR_667MHZ ? 1 : 0) << 18) |
+		(1 << 8) | /* enhanced scrub mode */
+		(1 << 7) | /* enable patrol scrub */
+		(1 << 6) | /* enable demand scrubing */
+		(1 << 5); /* enable northbound error detection */
+
+	printk(BIOS_DEBUG, "DRTA: 0x%08x DRTB: 0x%08x MC: 0x%08x\n", drta, drtb, mc);
+	pci_mmio_write_config32(dev16, I5000_DRTA, drta);
+	pci_mmio_write_config32(dev16, I5000_DRTB, drtb);
+	pci_mmio_write_config32(dev16, I5000_MC, mc);
+
+	mca = pci_mmio_read_config32(dev16, I5000_MCA);
+
+	mca |= (7 << 28);
+	if (setup->single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	printk(BIOS_DEBUG, "MCA: 0x%08x\n", mca);
+	pci_mmio_write_config32(dev16, I5000_MCA, mca);
+
+	pci_mmio_write_config32(dev16, I5000_ERRPERR, 0xffffffff);
+
+	i5000_program_mtr(&setup->branch[0].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[0].channel[1], I5000_MTR1);
+	i5000_program_mtr(&setup->branch[1].channel[0], I5000_MTR0);
+	i5000_program_mtr(&setup->branch[1].channel[1], I5000_MTR1);
+
+	i5000_setup_interleave(setup);
+
+	if ((tolm = MIN(setup->totalmem, 0xe00)) > 0xe00)
+		tolm = 0xe00;
+
+	tolm <<= 4;
+	printk(BIOS_DEBUG, "TOLM: 0x%04x\n", tolm);
+	pci_mmio_write_config16(dev16, I5000_TOLM, tolm);
+	return 0;
+}
+
+static void i5000_init_setup(struct i5000_fbd_setup *setup)
+{
+	int branch, channel, dimm, i = 0;
+	struct i5000_fbdimm *d;
+	struct i5000_fbd_channel *c;
+	struct i5000_fbd_branch *b;
+
+	setup->bl = 3;
+	/* default to highest memory frequency. If a module doesn't
+	   support it, it will decrease this setting in spd_read */
+	setup->ddr_speed = DDR_667MHZ;
+
+	for(branch = 0; branch < I5000_MAX_BRANCH; branch++) {
+		b = setup->branch + branch;
+		b->branchdev = PCI_ADDR(0, branch ? 22 : 21, 0, 0);
+		b->setup = setup;
+		b->num = branch;
+
+		for(channel = 0; channel < I5000_MAX_CHANNEL; channel++) {
+			c = b->channel + channel;
+			c->branch = b;
+			c->setup = setup;
+			c->num = channel;
+
+			for(dimm = 0; dimm < I5000_MAX_DIMM_PER_CHANNEL; dimm++) {
+				d = c->dimm + dimm;
+				setup->dimms[i++] = d;
+				d->channel = c;
+				d->branch = b;
+				d->setup = setup;
+				d->num = dimm;
+				d->ambase = (b->num << 16) | (c->num << 15) | (dimm << 11);
+			}
+		}
+	}
+}
+
+static void i5000_reserved_register_init(struct i5000_fbd_setup *setup)
+{
+	/* register write captured from vendor BIOS, but undocument by Intel */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), I5000_PROCENABLE, 0x487f7c);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xf4, 0x1588106);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0xfc, 0x80);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x5c, 0x08);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x70, 0xfe2c08d);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x78, 0xfe2c08d);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x140, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 0, 0), 0x440, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x18c, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x180, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x180, 0x87ffffff);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x200, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 0, 0, 0), 0x208, 0x18000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 4, 0, 0), 0x208, 0x18000000);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x184, 0x01249249);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x154, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x158, 0x02492492);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x15c, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x160, 0x00000000);
+
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0090, 0x00000007);
+	pci_mmio_write_config16(PCI_ADDR(0, 19, 0, 0), 0x0092, 0x0000000f);
+
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0154, 0x10);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x0454, 0x10);
+
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000001);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0108, 0x000003F0);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x010C, 0x00000042);
+	pci_mmio_write_config16(PCI_ADDR(0, 17, 0, 0), 0x0112, 0x0000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0114, 0x00A0494C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0118, 0x0002134C);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x013C, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0140, 0x0C008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0144, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 17, 0, 0), 0x0148, 0x00008000);
+	pci_mmio_write_config32(PCI_ADDR(0, 19, 0, 0), 0x007C, 0x00000002);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0x00000800);
+
+	if (setup->branch[0].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[0].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 21, 0, 0), 0x020C, 0x004C0C10);
+
+	if (setup->branch[1].channel[0].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x010C, 0x004C0C10);
+
+	if (setup->branch[1].channel[1].used)
+		pci_mmio_write_config32(PCI_ADDR(0, 22, 0, 0), 0x020C, 0x004C0C10);
+}
+static void i5000_dump_error_registers(void)
+{
+	device_t dev = PCI_ADDR(0, 16, 1, 0);
+
+	printk(BIOS_ERR, "Dump of FBD error registers:\n"
+	       "FERR_FAT_FBD: 0x%08x NERR_FAT_FBD: 0x%08x\n"
+	       "FERR_NF_FBD:  0x%08x NERR_NF_FBD:  0x%08x\n"
+	       "EMASK_FBD:    0x%08x\n"
+	       "ERR0_FBD:     0x%08x\n"
+	       "ERR1_FBD:     0x%08x\n"
+	       "ERR2_FBD:     0x%08x\n"
+	       "MC_ERR_FBD:   0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_FERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_FAT_FBD),
+	       pci_mmio_read_config32(dev, I5000_FERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_NERR_NF_FBD),
+	       pci_mmio_read_config32(dev, I5000_EMASK_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR0_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR1_FBD),
+	       pci_mmio_read_config32(dev, I5000_ERR2_FBD),
+	       pci_mmio_read_config32(dev, I5000_MCERR_FBD));
+
+	printk(BIOS_ERR, "Non recoverable error registers:\n"
+	       "NRECMEMA:     0x%08x NRECMEMB:    0x%08x\n"
+	       "NRECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECMEMA),
+	       pci_mmio_read_config32(dev, I5000_NRECMEMB),
+	       pci_mmio_read_config32(dev, I5000_NRECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "NRECFBDA: 0x%08x\n"
+	       "NRECFBDB: 0x%08x\n"
+	       "NRECFBDC: 0x%08x\n"
+	       "NRECFBDD: 0x%08x\n"
+	       "NRECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_NRECFBDA),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDB),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDC),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDD),
+	       pci_mmio_read_config32(dev, I5000_NRECFBDE));
+
+	printk(BIOS_ERR, "recoverable error registers:\n"
+	       "RECMEMA:     0x%08x RECMEMB:    0x%08x\n"
+	       "RECFGLOG:    0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECMEMA),
+	       pci_mmio_read_config32(dev, I5000_RECMEMB),
+	       pci_mmio_read_config32(dev, I5000_RECFGLOG));
+
+	printk(BIOS_ERR, "Packet data:\n"
+	       "RECFBDA: 0x%08x\n"
+	       "RECFBDB: 0x%08x\n"
+	       "RECFBDC: 0x%08x\n"
+	       "RECFBDD: 0x%08x\n"
+	       "RECFBDE: 0x%08x\n",
+	       pci_mmio_read_config32(dev, I5000_RECFBDA),
+	       pci_mmio_read_config32(dev, I5000_RECFBDB),
+	       pci_mmio_read_config32(dev, I5000_RECFBDC),
+	       pci_mmio_read_config32(dev, I5000_RECFBDD),
+	       pci_mmio_read_config32(dev, I5000_RECFBDE));
+
+}
+
+static void i5000_try_restart(const char *msg)
+{
+	printk(BIOS_INFO, msg);
+	i5000_dump_error_registers();
+	outb(0x06, 0xcf9);
+	for(;;) asm volatile("hlt");
+}
+
+static void i5000_pam_setup(void)
+{
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x59, 0x30);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5a, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5b, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5c, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5d, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5e, 0x33);
+	pci_mmio_write_config8(PCI_ADDR(0, 16, 0, 0), 0x5f, 0x33);
+}
+
+void i5000_fbdimm_init(void)
+{
+	struct i5000_fbd_setup setup;
+	u32 mca, mc;
+
+	udelay(1000);
+	memset(&setup, 0, sizeof(setup));
+
+	pci_mmio_write_config16(PCI_ADDR(0, 0, 0, 0), 0x4, 0x144);
+
+	i5000_init_setup(&setup);
+
+	pci_write_config32(PCI_DEV(0, 16, 0), 0xf0,
+			   pci_mmio_read_config32(PCI_ADDR(0, 16, 0, 0), 0xf0) | 0x8000);
+
+	i5000_clear_fbd_errors();
+
+	if (i5000_for_each_dimm(&setup, i5000_read_spd_data)) {
+		printk(BIOS_ERR, "%s: failed to read SPD data\n", __func__);
+		return;
+	}
+
+	/* posted CAS requires t_AL = t_RCD - 1 */
+	setup.t_al = setup.t_rcd - 1;
+
+	printk(BIOS_DEBUG, "global timing parameters:\n"
+	       "CL: %d RAS: %d WRC: %d RC: %d RFC: %d RRD: %d REF: %d W2RDR: %d\n"
+	       "R2W: %d W2R: %d R2R: %d W2W: %d WTR: %d RCD: %d RP %d WR: %d RTP: %d AL: %d\n",
+	       setup.t_cl, setup.t_ras, setup.t_wrc, setup.t_rc, setup.t_rfc,
+	       setup.t_rrd, setup.t_ref, setup.t_w2rdr, setup.t_r2w, setup.t_w2r,
+	       setup.t_r2r, setup.t_w2w, setup.t_wtr, setup.t_rcd,
+	       setup.t_rp, setup.t_wr, setup.t_rtp, setup.t_al);
+
+	/* TODO: motherboard callback to set FBD clock */
+
+	setup.single_channel = (!(setup.branch[0].channel[1].used ||
+				  setup.branch[1].channel[0].used ||
+				  setup.branch[1].channel[1].used));
+
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x019C, 0x8010c);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), 0x01F4, 0);
+
+	/* enable or disable single channel mode */
+	mca = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA);
+	if (setup.single_channel)
+		mca |= (1 << 14);
+	else
+		mca &= ~(1 << 14);
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MCA, mca);
+
+	/*
+	 * i5000 supports burst length 8 only in single channel mode
+	 * so strip BL_BL8 if we're operating in multichannel mode
+	 */
+
+	if (!setup.single_channel)
+		setup.bl &= ~BL_BL8;
+
+	if (!setup.bl)
+		die("No supported burst length found\n");
+
+	mc = pci_mmio_read_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC);
+	/* disable error checking for training */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc & ~0x20);
+
+	if (i5000_for_each_branch(&setup, i5000_branch_reset) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_preinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training0) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_check) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_postinit) ||
+	    i5000_for_each_branch(&setup, i5000_link_training1) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_amb_dram_timing_init) ||
+	    i5000_for_each_dimm_present(&setup, i5000_ddr_calibration)) {
+		i5000_try_restart("Memory initialization failed\n");
+	}
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_MEMBIST
+	if (i5000_membist(&setup))
+		i5000_try_restart("Memory selftest failed\n");
+#endif
+
+	if (i5000_for_each_dimm_present(&setup, i5000_enable_mc_autorefresh))
+		i5000_try_restart("failed to enable auto refresh\n");
+
+	if (i5000_for_each_channel(&setup.branch[0], i5000_drive_test_patterns0) ||
+	    i5000_for_each_channel(&setup.branch[1], i5000_drive_test_patterns0))
+		i5000_try_restart("Channel training failed\n");
+
+	i5000_clear_fbd_errors();
+
+	/* enable error checking */
+	pci_mmio_write_config32(PCI_ADDR(0, 16, 1, 0), I5000_MC, mc | 0x20);
+
+	i5000_dram_timing_init(&setup);
+
+	i5000_reserved_register_init(&setup);
+	i5000_pam_setup();
+
+	if (i5000_for_each_dimm_present(&setup, i5000_amb_clear_error_status))
+		i5000_try_restart("failed to clear error status\n");
+
+	if (setup.branch[0].used)
+		i5000_fbd_next_state(&setup.branch[0], I5000_FBDHPC_STATE_ACTIVE);
+
+	if (setup.branch[1].used)
+		i5000_fbd_next_state(&setup.branch[1], I5000_FBDHPC_STATE_ACTIVE);
+
+#if CONFIG_NORTHBRIDGE_INTEL_I5000_RAM_CHECK
+	if (ram_check_nodie(0x000000, 0x0a0000) ||
+	    ram_check_nodie(0x100000, MIN(setup.totalmem * 1048576, 0xe0000000))) {
+		i5000_try_restart("RAM verification failed");
+	}
+#endif
+}
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
new file mode 100644
index 0000000..2e48238
--- /dev/null
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -0,0 +1,328 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_I5000_RAMINIT_H
+#define NORTHBRIDGE_I5000_RAMINIT_H
+
+#include <types.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#define I5000_MAX_BRANCH 2
+#define I5000_MAX_CHANNEL 2
+#define I5000_MAX_DIMM_PER_CHANNEL 4
+#define I5000_MAX_DIMMS (I5000_MAX_BRANCH * I5000_MAX_CHANNEL * I5000_MAX_DIMM_PER_CHANNEL)
+
+#define I5000_FBDRST 0x53
+
+#define I5000_SPD_BUSY (1 << 12)
+#define I5000_SPD_SBE (1 << 13)
+#define I5000_SPD_WOD (1 << 14)
+#define I5000_SPD_RDO (1 << 15)
+
+#define I5000_SPD0 0x74
+#define I5000_SPD1 0x76
+
+#define I5000_SPDCMD0 0x78
+#define I5000_SPDCMD1 0x7c
+
+#define I5000_FBDHPC 0x4f
+#define I5000_FBDST  0x4b
+
+#define I5000_FBDHPC_STATE_RESET 0x00
+#define I5000_FBDHPC_STATE_INIT 0x10
+#define I5000_FBDHPC_STATE_READY 0x20
+#define I5000_FBDHPC_STATE_ACTIVE 0x30
+
+#define I5000_FBDISTS0 0x58
+#define I5000_FBDISTS1 0x5a
+
+#define I5000_FBDLVL0 0x44
+#define I5000_FBDLVL1 0x45
+
+#define I5000_FBDICMD0 0x46
+#define I5000_FBDICMD1 0x47
+
+#define I5000_FBDICMD_IDLE 0x00
+#define I5000_FBDICMD_TS0  0x80
+#define I5000_FBDICMD_TS1  0x90
+#define I5000_FBDICMD_TS2  0xa0
+#define I5000_FBDICMD_TS3  0xb0
+#define I5000_FBDICMD_TS2_MERGE 0xd0
+#define I5000_FBDICMD_TS2_NOMERGE 0xe0
+#define I5000_FBDICMD_ALL_ONES 0xf0
+
+#define I5000_AMBPRESENT0 0x64
+#define I5000_AMBPRESENT1 0x66
+
+#define I5000_FBDSBTXCFG0 0xc0
+#define I5000_FBDSBTXCFG1 0xc1
+
+#define I5000_PROCENABLE 0xf0
+#define I5000_FBD0IBPORTCTL 0x180
+#define I5000_FBD0IBTXPAT2EN 0x1a8
+#define I5000_FBD0IBRXPAT2EN 0x1ac
+
+#define I5000_FBD0IBTXMSK 0x18c
+#define I5000_FBD0IBRXMSK 0x190
+
+#define I5000_FBDPLLCTRL 0x1c0
+
+/* dev 16, function 1 registers */
+#define I5000_MC 0x40
+#define I5000_DRTA 0x48
+#define I5000_DRTB 0x4c
+#define I5000_ERRPERR 0x50
+#define I5000_MCA 0x58
+#define I5000_TOLM 0x6c
+#define I5000_MIR0 0x80
+#define I5000_MIR1 0x84
+#define I5000_MIR2 0x88
+#define I5000_AMIR0 0x8c
+#define I5000_AMIR1 0x90
+#define I5000_AMIR2 0x94
+
+#define I5000_FERR_FAT_FBD 0x98
+#define I5000_NERR_FAT_FBD 0x9c
+#define I5000_FERR_NF_FBD 0xa0
+#define I5000_NERR_NF_FBD 0xa4
+#define I5000_EMASK_FBD 0xa8
+#define I5000_ERR0_FBD 0xac
+#define I5000_ERR1_FBD 0xb0
+#define I5000_ERR2_FBD 0xb4
+#define I5000_MCERR_FBD 0xb8
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECMEMB 0xc0
+#define I5000_NRECFGLOG 0xc4
+#define I5000_NRECMEMA 0xbe
+#define I5000_NRECFBDA 0xc8
+#define I5000_NRECFBDB 0xcc
+#define I5000_NRECFBDC 0xd0
+#define I5000_NRECFBDD 0xd4
+#define I5000_NRECFBDE 0xd8
+
+#define I5000_REDMEMB 0x7c
+#define I5000_RECMEMA 0xe2
+#define I5000_RECMEMB 0xe4
+#define I5000_RECFGLOG 0xe8
+#define I5000_RECFBDA 0xec
+#define I5000_RECFBDB 0xf0
+#define I5000_RECFBDC 0xf4
+#define I5000_RECFBDD 0xf8
+#define I5000_RECFBDE 0xfc
+
+/* dev 16, function 2 registers */
+#define I5000_FERR_GLOBAL 0x40
+#define I5000_NERR_GLOBAL 0x44
+
+/* dev 21, function 0 registers */
+#define I5000_MTR0 0x80
+#define I5000_MTR1 0x84
+#define I5000_MTR2 0x88
+#define I5000_MTR3 0x8c
+#define I5000_DMIR0 0x90
+#define I5000_DMIR1 0x94
+#define I5000_DMIR2 0x98
+#define I5000_DMIR3 0x9c
+#define I5000_DMIR4 0xa0
+
+#define DEFAULT_AMBASE 0xfe000000
+
+/* AMB function 1 registers */
+#define AMB_FBDSBCFGNXT 0x54
+#define AMB_FBDLOCKTO 0x68
+#define AMB_EMASK 0x8c
+#define AMB_FERR 0x90
+#define AMB_NERR 0x94
+#define AMB_CMD2DATANXT 0xe8
+
+/* AMB function 3 registers */
+#define AMB_DAREFTC 0x70
+#define AMB_DSREFTC 0x74
+#define AMB_DRT 0x78
+#define AMB_DRC 0x7c
+
+#define AMB_MBCSR 0x40
+#define AMB_MBADDR 0x44
+#define AMB_MBLFSRSED 0xa4
+
+/* AMB function 4 registers */
+#define AMB_DCALCSR  0x40
+#define AMB_DCALADDR 0x44
+#define AMB_DCALCSR_START (1 << 31)
+
+#define AMB_DCALCSR_OPCODE_NOP                0x00
+#define AMB_DCALCSR_OPCODE_REFRESH            0x01
+#define AMB_DCALCSR_OPCODE_PRECHARGE          0x02
+#define AMB_DCALCSR_OPCODE_MRS_EMRS           0x03
+#define AMB_DCALCSR_OPCODE_DQS_DELAY_CAL      0x05
+#define AMB_DCALCSR_OPCODE_RECV_ENABLE_CAL    0x0c
+#define AMB_DCALCSR_OPCODE_SELF_REFRESH_ENTRY 0x0d
+
+#define AMB_DDR2ODTC 0xfc
+
+#define FBDIMM_SPD_SDRAM_ADDRESSING 0x04
+#define FBDIMM_SPD_MODULE_ORGANIZATION 0x07
+#define FBDIMM_SPD_FTB 0x08
+#define FBDIMM_SPD_MTB_DIVIDEND 0x09
+#define FBDIMM_SPD_MTB_DIVISOR 0x0a
+#define FBDIMM_SPD_MIN_TCK 0x0b
+#define FBDIMM_SPD_CAS_LATENCIES 0x0d
+#define FBDIMM_SPD_CAS_MIN_LATENCY 0x0e
+#define FBDIMM_SPD_T_WR 0x10
+#define FBDIMM_SPD_T_RCD 0x13
+#define FBDIMM_SPD_T_RRD 0x14
+#define FBDIMM_SPD_T_RP 0x15
+#define FBDIMM_SPD_T_RAS_RC_MSB 0x16
+#define FBDIMM_SPD_T_RAS 0x17
+#define FBDIMM_SPD_T_RC 0x18
+#define FBDIMM_SPD_T_RFC 0x19
+#define FBDIMM_SPD_T_WTR 0x1b
+#define FBDIMM_SPD_T_RTP 0x1c
+#define FBDIMM_SPD_BURST_LENGTHS_SUPPORTED 0x1d
+#define FBDIMM_SPD_ODT 0x4f
+#define FBDIMM_SPD_T_REFI 0x20
+#define FBDIMM_SPD_T_BB 0x83
+#define FBDIMM_SPD_CMD2DATA_800 0x54
+#define FBDIMM_SPD_CMD2DATA_667 0x55
+#define FBDIMM_SPD_CMD2DATA_533 0x56
+
+void i5000_fbdimm_init(void);
+
+#define I5000_BURST4 0x01
+#define I5000_BURST8 0x02
+#define I5000_BURST_CHOP 0x80
+
+#define I5000_ODT_50 4
+#define I5000_ODT_75 2
+#define I5000_ODT_150 1
+
+enum ddr_speeds {
+	DDR_533MHZ,
+	DDR_667MHZ,
+	DDR_MAX,
+};
+
+struct i5000_fbdimm {
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_channel *channel;
+	struct i5000_fbd_setup *setup;
+	enum ddr_speeds speed;
+	int num;
+	int present:1;
+	u32 ambase;
+
+	/* SPD data */
+	u8 amb_personality_bytes[14];
+	u8 banks;
+	u8 rows;
+	u8 columns;
+	u8 ranks;
+	u8 odt;
+	u8 sdram_width;
+	u8 mtb_divisor;
+	u8 mtb_dividend;
+	u8 t_ck_min;
+	u8 min_cas_latency;
+	u8 t_rrd;
+	u16 t_rfc;
+	u8 t_wtr;
+	u8 t_refi;
+	u8 cmd2datanxt[DDR_MAX];
+
+	u16 vendor;
+	u16 device;
+
+	/* memory size in MB */
+	int size;
+};
+
+struct i5000_fbd_channel {
+	struct i5000_fbdimm dimm[I5000_MAX_DIMM_PER_CHANNEL];
+	struct i5000_fbd_branch *branch;
+	struct i5000_fbd_setup *setup;
+	int num;
+	int used;
+	int highest_amb;
+	int columns;
+	int rows;
+	int ranks;
+	int banks;
+	int width;
+	/* memory size in MB on this channel */
+	int totalmem;
+};
+
+struct i5000_fbd_branch {
+	struct i5000_fbd_channel channel[I5000_MAX_CHANNEL];
+	struct i5000_fbd_setup *setup;
+	device_t branchdev;
+	int num;
+	int used;
+	/* memory size in MB on this branch */
+	int totalmem;
+};
+
+enum odt {
+	ODT_150OHM=1,
+	ODT_50OHM=4,
+	ODT_75OHM=2,
+};
+
+enum bl {
+	BL_BL4=1,
+	BL_BL8=2,
+};
+
+struct i5000_fbd_setup {
+	struct i5000_fbd_branch branch[I5000_MAX_BRANCH];
+	struct i5000_fbdimm *dimms[I5000_MAX_DIMMS];
+	enum bl bl;
+	enum ddr_speeds ddr_speed;
+
+	int single_channel:1;
+	u32 tolm;
+
+	/* global SDRAM timing parameters */
+	u8 t_al;
+	u8 t_cl;
+	u8 t_ras;
+	u8 t_wrc;
+	u8 t_rc;
+	u8 t_rfc;
+	u8 t_rrd;
+	u8 t_ref;
+	u8 t_w2rdr;
+	u8 t_r2w;
+	u8 t_w2r;
+	u8 t_r2r;
+	u8 t_w2w;
+	u8 t_wtr;
+	u8 t_rcd;
+	u8 t_rp;
+	u8 t_wr;
+	u8 t_rtp;
+	/* memory size in MB */
+	int totalmem;
+};
+
+#define AMB_ADDR(base, fn, reg)	(base | ((fn & 7) << 8) | ((reg & 0xff)))
+#endif
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
new file mode 100644
index 0000000..6462fe0
--- /dev/null
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 0, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xcd);
+	switch (msr.lo & 0x07) {
+	case 5:
+		fsb = 400;
+		break;
+	case 1:
+		fsb = 533;
+		break;
+	case 3:
+		fsb = 667;
+		break;
+	case 2:
+		fsb = 800;
+		break;
+	case 0:
+		fsb = 1067;
+		break;
+	case 4:
+		fsb = 1333;
+		break;
+	case 6:
+		fsb = 1600;
+		break;
+	}
+
+	msr = rdmsr(0x198);
+	divisor = (msr.hi >> 8) & 0x1f;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	tsc = rdtsc();
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi) || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}


From gerrit at coreboot.org  Thu Jan 12 23:40:42 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Thu, 12 Jan 2012 23:40:42 +0100
Subject: [coreboot] New patch to review for coreboot: aa4e002 Fix to allow
	one vbios rom to match multiple PCI device IDs
References: <Ic68af575fe73d6700b5575b55148feef529637ef+0@gerrit.coreboot.org>
Message-ID: <Ic68af575fe73d6700b5575b55148feef529637ef+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/534

-gerrit

commit aa4e002b797e11d2a6508153e9962faec0aa4e5c
Author: Martin L Roth <martin at se-eng.com>
Date:   Thu Jan 12 15:09:02 2012 -0700

    Fix to allow one vbios rom to match multiple PCI device IDs
    
    This change supplies an AND mask which is applied to the PCI device
    ID for VGA devices before comparison with the rom device ID.  The
    reason for the change is to support "generic" video bios roms which
    work with multiple different device IDs.
    
    Change-Id: Ic68af575fe73d6700b5575b55148feef529637ef
    Signed-off-by: Martin L Roth <martin at se-eng.com>
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/Kconfig           |   22 ++++++++++++++++++++++
 src/devices/pci_rom.c |   24 ++++++++++++++++++++++++
 2 files changed, 46 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 525d452..37fe861 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -2,6 +2,8 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009-2010 coresystems GmbH
+## Copyright (C) 2012 Sage Electronic Engineering, LLC
+## (Written by Martin Roth <martin at se-eng.com> for Sage)
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -497,6 +499,26 @@ config VGA_BIOS_ID
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
 	  video card (also in hex, without "0x" prefix).
 
+config VGA_BIOS_ID_MASKda02d261343849f764ddc5a41ce4b40acdb7027e
+	hex "VGA device PCI device ID mask"
+	depends on VGA_BIOS
+	default 0xffff
+	help
+	  This is an AND mask that is applied to the PCI device ID that
+	  would associate your VGA BIOS to your video card when deciding
+	  to apply the rom to the PCI device.
+
+	  Example: 0xFFF0
+
+	  In the above example, the lower nibble of the device ID would not
+	  be included when comparing the ROM's programmed device ID with
+	  the device ID of the actual PCI device.  This allows a rom with
+	  a device ID of 3230 to match against any PCI devices with ids
+	  in the range of 3230 to 323F
+
+	  Note: The device ID portion of the VGA_BIOS_ID should have any
+	  masked bits set to zero as well.
+
 config INTEL_MBI
 	bool "Add an MBI image"
 	depends on NORTHBRIDGE_INTEL_I82830
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 56712df..a5e1717 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -6,6 +6,8 @@
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005 Ronald G. Minnich <rminnich at gmail.com>
  * Copyright (C) 2005-2007 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2012 Sage Electronic Engineering, LLC
+ * (Written by Martin Roth <martin at se-eng.com> for Sage)
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,6 +37,14 @@ struct rom_header *pci_rom_probe(struct device *dev)
 	struct pci_data *rom_data;
 
 	/* If it's in FLASH, then don't check device for ROM. */
+
+#if CONFIG_VGA_BIOS
+	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
+		rom_header = cbfs_load_optionrom(dev->vendor,
+			(dev->device & CONFIG_VGA_BIOS_ID_MASK), NULL);
+	else
+#endif
+
 	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
 	if (rom_header) {
@@ -78,6 +88,20 @@ struct rom_header *pci_rom_probe(struct device *dev)
 
 	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
 	       rom_data->vendor, rom_data->device);
+
+#if CONFIG_VGA_BIOS
+	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+		if (dev->vendor != rom_data->vendor
+		    || ((dev->device & CONFIG_VGA_BIOS_ID_MASK) !=
+			(rom_data->device & CONFIG_VGA_BIOS_ID_MASK))) {
+			printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
+			       "device ID %04x\n", rom_data->vendor,
+			       rom_data->device);
+			return NULL;
+		}
+	} else
+#endif
+
 	if (dev->vendor != rom_data->vendor
 	    || dev->device != rom_data->device) {
 		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "


From sulmicki at gmail.com  Fri Jan 13 18:19:14 2012
From: sulmicki at gmail.com (Adam Sulmicki)
Date: Fri, 13 Jan 2012 18:19:14 +0100
Subject: [coreboot] Job at Norway
Message-ID: <CAGfBNB-8EZtXcM=o8vU0arxkhk5W03Y9ty6cqGB-XAjpaShvZg@mail.gmail.com>

Hello all,

Creator of the ADLO fame (http://www.coreboot.org/ADLO) is back from
sabbatical and is looking for a job.

Preferably something linuxbios^w coreboot related but I am open for other
options.

Preferred country to live at is Norway.

Sincerely,
Adam Sulmicki
-------------- next part --------------
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From gerrit at coreboot.org  Fri Jan 13 23:40:13 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Fri, 13 Jan 2012 23:40:13 +0100
Subject: [coreboot] Patch set updated for coreboot: 6deec7b Fix to allow one
	vbios ROM to match multiple PCI device IDs
References: <Ic68af575fe73d6700b5575b55148feef529637ef+0@gerrit.coreboot.org>
Message-ID: <Ic68af575fe73d6700b5575b55148feef529637ef+2@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/534

-gerrit

commit 6deec7b7e51981b15094427b9570eda4350d7177
Author: Martin Roth <Martin at se-eng.com>
Date:   Thu Jan 12 14:23:48 2012 -0700

    Fix to allow one vbios ROM to match multiple PCI device IDs
    
    This change allows a single option ROM to be decompressed from CBFS
    and loaded for PCI devices with different PCI device IDs.  This is
    needed to support "generic" video BIOS ROMs designed to work with
    multiple different device IDs.
    
    The method of doing this is with an AND mask which is applied to the PCI
    device ID for VGA devices both when selecting the ROM to decompress from
    CBFS and before comparison with the ROM device ID to initialize.
    
    The main problem with this method is that if there were two PCI devices
    with very similar Device IDs and both had ROMs stored in CBFS, a VGA
    device and another device, the wrong ROM could be accidentally applied.
    Because of this, it's important to keep the mask as narrow as possible.
    0xff00 shouldn't be used if 0xfff0 will work.
    
    Change-Id: Ic68af575fe73d6700b5575b55148feef529637ef
    Signed-off-by: Martin L Roth <martin at se-eng.com>
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/Kconfig           |   32 ++++++++++++++++++++++++++++++++
 src/devices/pci_rom.c |   21 ++++++++++++++++++---
 2 files changed, 50 insertions(+), 3 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 525d452..abdad83 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009-2010 coresystems GmbH
+## Copyright (C) 2012 Sage Electronic Engineering, LLC
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -465,6 +466,13 @@ config COMPRESSED_PAYLOAD_NRV2B
 
 endmenu
 
+# This options is here to avoid "undefined" warnings.
+# The actual selection and help texts are in the following menu.
+
+config VGA_BIOS_DEVICEID_MASK
+	hex
+	default 0xffff
+
 menu "VGA BIOS"
 
 config VGA_BIOS
@@ -497,6 +505,30 @@ config VGA_BIOS_ID
 	  the "0x" prefix) and 3230 specifies the PCI device ID of the
 	  video card (also in hex, without "0x" prefix).
 
+config VGA_BIOS_DEVICEID_MASK
+	hex "VGA device PCI device ID mask"
+	depends on VGA_BIOS
+	default 0xffff
+	help
+	  This is an AND mask that is applied to the PCI device ID that
+	  would associate your VGA BIOS to your video card when deciding
+	  to apply the rom to the PCI device.
+
+	  Example: 0xFFF8
+
+	  In the above example, the lowest 3 bits of the device ID would not
+	  be included when comparing the ROM's programmed device ID with
+	  the device ID of the actual PCI device.  This allows a rom with
+	  a device ID of 3230 to match against any PCI devices with ids
+	  in the range of 3230 to 3237
+
+	  WARNING: This mask should be kept as narrow as possible to avoid
+	  loading an incorrect rom for a device out of CBFS.  If you're
+	  using a mask of 0x0000, you're *probably* doing something wrong.
+
+	  Note: The device ID portion of the VGA_BIOS_ID should have any
+	  masked bits set to zero in the above entry.
+
 config INTEL_MBI
 	bool "Add an MBI image"
 	depends on NORTHBRIDGE_INTEL_I82830
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 56712df..b5dce97 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -6,6 +6,7 @@
  * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
  * Copyright (C) 2005 Ronald G. Minnich <rminnich at gmail.com>
  * Copyright (C) 2005-2007 Stefan Reinauer <stepan at openbios.org>
+ * Copyright (C) 2012 Sage Electronic Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -35,7 +36,11 @@ struct rom_header *pci_rom_probe(struct device *dev)
 	struct pci_data *rom_data;
 
 	/* If it's in FLASH, then don't check device for ROM. */
-	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
+	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
+		rom_header = cbfs_load_optionrom(dev->vendor,
+			(dev->device & CONFIG_VGA_BIOS_DEVICEID_MASK), NULL);
+	else
+		rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
 	if (rom_header) {
 		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
@@ -78,8 +83,18 @@ struct rom_header *pci_rom_probe(struct device *dev)
 
 	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
 	       rom_data->vendor, rom_data->device);
-	if (dev->vendor != rom_data->vendor
-	    || dev->device != rom_data->device) {
+
+	if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
+		if (dev->vendor != rom_data->vendor
+		    || ((dev->device & CONFIG_VGA_BIOS_DEVICEID_MASK) !=
+			(rom_data->device & CONFIG_VGA_BIOS_DEVICEID_MASK))) {
+			printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
+			       "device ID %04x\n", rom_data->vendor,
+			       rom_data->device);
+			return NULL;
+		}
+	} else if (dev->vendor != rom_data->vendor
+		   || dev->device != rom_data->device) {
 		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
 		       "device ID %04x\n", rom_data->vendor, rom_data->device);
 		return NULL;


From gerrit at coreboot.org  Sat Jan 14 10:07:46 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 14 Jan 2012 10:07:46 +0100
Subject: [coreboot] New patch to review for coreboot: bc99d22 APIC: Fixed
	reading MSR_FSB_FREQ register
References: <I53199f212a543c642c633adf783b6490c216fb61+0@gerrit.coreboot.org>
Message-ID: <I53199f212a543c642c633adf783b6490c216fb61+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/535

-gerrit

commit bc99d2285ab900489e6737ec7e315afa812ea178
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 14 14:36:51 2012 +0530

    APIC: Fixed reading MSR_FSB_FREQ register
    
    According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB
    frequency. But the code had a right shift of 4 which will always
    give 267 MHz, as the valid bits are shifted to right.
    
    Change-Id: I53199f212a543c642c633adf783b6490c216fb61
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/lapic/apic_timer.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 826f5b6..0b56fd5 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -28,6 +28,7 @@
  */
 
 #define FSB_CLOCK_STS 0xcd
+#define FSB_FREQ_MASK 0x07
 
 static u32 timer_fsb = 200; // default to 200MHz
 
@@ -46,7 +47,7 @@ void init_timer(void)
 
 	/* Set FSB frequency to a reasonable value */
 	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
+	switch (fsb_clock_sts.lo & FSB_FREQ_MASK) {
 	case 0: timer_fsb = 266; break;
 	case 1: timer_fsb = 133; break;
 	case 2: timer_fsb = 200; break;


From gerrit at coreboot.org  Sat Jan 14 10:12:55 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 14 Jan 2012 10:12:55 +0100
Subject: [coreboot] New patch to review for coreboot: ed3a3f3 APIC: Fixed
	reading MSR_FSB_FREQ register
References: <I6d24f68edb4fa3ee739d63461a17f4458c90481b+0@gerrit.coreboot.org>
Message-ID: <I6d24f68edb4fa3ee739d63461a17f4458c90481b+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/536

-gerrit

commit ed3a3f37393055b8a85929db43df46077c994320
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 14 14:31:23 2012 +0530

    APIC: Fixed reading MSR_FSB_FREQ register
    
    According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB
    frequency. But the code had a right shift of 4 which will always
    give 267 MHz, as the valid bits are shifted to right.
    
    Change-Id: I6d24f68edb4fa3ee739d63461a17f4458c90481b
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/lapic/apic_timer.c |   28 +++++++++-------------------
 1 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 312951a..0b56fd5 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -27,10 +27,10 @@
  * memory init.
  */
 
-#define FSB_CLOCK_STS 0xCD
+#define FSB_CLOCK_STS 0xcd
 #define FSB_FREQ_MASK 0x07
 
-static u32 timer_fsb = 200;	// default to 200MHz
+static u32 timer_fsb = 200; // default to 200MHz
 
 void init_timer(void)
 {
@@ -43,26 +43,16 @@ void init_timer(void)
 	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
 
 	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, ~0UL);
+	lapic_write(LAPIC_TMICT, 0xffffffff);
 
 	/* Set FSB frequency to a reasonable value */
 	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
 	switch (fsb_clock_sts.lo & FSB_FREQ_MASK) {
-	case 0:
-		timer_fsb = 266;
-		break;
-	case 1:
-		timer_fsb = 133;
-		break;
-	case 2:
-		timer_fsb = 200;
-		break;
-	case 3:
-		timer_fsb = 166;
-		break;
-	case 5:
-		timer_fsb = 100;
-		break;
+	case 0: timer_fsb = 266; break;
+	case 1: timer_fsb = 133; break;
+	case 2: timer_fsb = 200; break;
+	case 3: timer_fsb = 166; break;
+	case 5: timer_fsb = 100; break;
 	}
 }
 
@@ -74,5 +64,5 @@ void udelay(u32 usecs)
 	start = lapic_read(LAPIC_TMCCT);
 	do {
 		value = lapic_read(LAPIC_TMCCT);
-	} while ((start - value) < ticks);
+	} while((start - value) < ticks);
 }


From gerrit at coreboot.org  Sat Jan 14 10:13:08 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 14 Jan 2012 10:13:08 +0100
Subject: [coreboot] Patch set updated for coreboot: 419f496 APIC: Fixed
	reading MSR_FSB_FREQ register
References: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+0@gerrit.coreboot.org>
Message-ID: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+2@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507

-gerrit

commit 419f496ece1a83a0317d1fa2ec9015a6d9d32a83
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Dec 26 23:30:23 2011 +0530

    APIC: Fixed reading MSR_FSB_FREQ register
    
    According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB
    frequency. But the code had a right shift of 4 which will always
    give 267 MHz, as the valid bits are shifted to right.
    Also, fixed the indentations.
    
    Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/lapic/apic_timer.c |   31 +++++++++++++++++++++----------
 1 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 826f5b6..312951a 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -27,9 +27,10 @@
  * memory init.
  */
 
-#define FSB_CLOCK_STS 0xcd
+#define FSB_CLOCK_STS 0xCD
+#define FSB_FREQ_MASK 0x07
 
-static u32 timer_fsb = 200; // default to 200MHz
+static u32 timer_fsb = 200;	// default to 200MHz
 
 void init_timer(void)
 {
@@ -42,16 +43,26 @@ void init_timer(void)
 	lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
 
 	/* Set the initial counter to 0xffffffff */
-	lapic_write(LAPIC_TMICT, 0xffffffff);
+	lapic_write(LAPIC_TMICT, ~0UL);
 
 	/* Set FSB frequency to a reasonable value */
 	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
-	case 0: timer_fsb = 266; break;
-	case 1: timer_fsb = 133; break;
-	case 2: timer_fsb = 200; break;
-	case 3: timer_fsb = 166; break;
-	case 5: timer_fsb = 100; break;
+	switch (fsb_clock_sts.lo & FSB_FREQ_MASK) {
+	case 0:
+		timer_fsb = 266;
+		break;
+	case 1:
+		timer_fsb = 133;
+		break;
+	case 2:
+		timer_fsb = 200;
+		break;
+	case 3:
+		timer_fsb = 166;
+		break;
+	case 5:
+		timer_fsb = 100;
+		break;
 	}
 }
 
@@ -63,5 +74,5 @@ void udelay(u32 usecs)
 	start = lapic_read(LAPIC_TMCCT);
 	do {
 		value = lapic_read(LAPIC_TMCCT);
-	} while((start - value) < ticks);
+	} while ((start - value) < ticks);
 }


From gerrit at coreboot.org  Sat Jan 14 10:32:33 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 14 Jan 2012 10:32:33 +0100
Subject: [coreboot] Patch set updated for coreboot: c2a8f4b APIC: Fixed
	reading MSR_FSB_FREQ register
References: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+0@gerrit.coreboot.org>
Message-ID: <I6bf93bac1ee9123af78c003f5a0728f8f0801958+3@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/507

-gerrit

commit c2a8f4b71c767287ab34df8455fc5f3848dcf5c6
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 14 14:36:51 2012 +0530

    APIC: Fixed reading MSR_FSB_FREQ register
    
    According to Intel's manual, bits 0:2 of MSR 0xCDh gives the FSB
    frequency. But the code had a right shift of 4 which will always
    give 267 MHz, as the valid bits are shifted to right.
    
    Change-Id: I6bf93bac1ee9123af78c003f5a0728f8f0801958
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/lapic/apic_timer.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index 826f5b6..0b56fd5 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -28,6 +28,7 @@
  */
 
 #define FSB_CLOCK_STS 0xcd
+#define FSB_FREQ_MASK 0x07
 
 static u32 timer_fsb = 200; // default to 200MHz
 
@@ -46,7 +47,7 @@ void init_timer(void)
 
 	/* Set FSB frequency to a reasonable value */
 	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
+	switch (fsb_clock_sts.lo & FSB_FREQ_MASK) {
 	case 0: timer_fsb = 266; break;
 	case 1: timer_fsb = 133; break;
 	case 2: timer_fsb = 200; break;


From svn at coreboot.org  Mon Jan 16 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 16 Jan 2012 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Rmo2T-0003zv-I3@ra.coresystems.de>

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From regmeplease at gmail.com  Mon Jan 16 15:59:04 2012
From: regmeplease at gmail.com (Vincenzo Romano)
Date: Mon, 16 Jan 2012 15:59:04 +0100
Subject: [coreboot] Coreboot on P6X58D-E?
Message-ID: <CAHjZ2x6KShCWG+dLED4SCEj_eGZnodaPJWXj9=YOD+7GhoZ5bA@mail.gmail.com>

Hi all.
Is there anyone working on cioreboot for the ASUS P6X58D-E board?
TIA.


From wmkamp at datakamp.de  Mon Jan 16 18:18:32 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Mon, 16 Jan 2012 18:18:32 +0100
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>

Hello,

I found a problem with the PCI enumeration of the PCIe Ports in the CIMX/SB800 Southbridge for the INAGUA platform.
The .../southbridge/amd/cimx/sb800/late.c routine calls the function sb_Before_PCI_Init after
case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | 0 are probed in the routine ../devices/pci_device.c function
pci_probe_dev they are not yet initialized. The probing fails and also devices behind the bridge are not recognized.
Behind the PCIe bridge I have an Intel 82574 LAN chip.
But if I move the call to sb_Before_PCI_Init behind case  (0x15 <<3) | 0 the enumeration succeed but coreboot crashes later into nothing. The Sage Debugger fails.
I can't imagine why.

Marc have you any idea?

Regards

Wolfgang

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From marcj303 at gmail.com  Mon Jan 16 20:22:59 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Mon, 16 Jan 2012 12:22:59 -0700
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
Message-ID: <CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>

On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
<wmkamp at datakamp.de> wrote:
> Hello,
>
>
>
> I found a problem with the PCI enumeration of the PCIe Ports in the
> CIMX/SB800 Southbridge for the INAGUA platform.
>
> The ?/southbridge/amd/cimx/sb800/late.c routine calls the function
> sb_Before_PCI_Init after
>
> case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | 0
> are probed in the routine ../devices/pci_device.c function
>
> pci_probe_dev they are not yet initialized. The probing fails and also
> devices behind the bridge are not recognized.
>
> Behind the PCIe bridge I have an Intel 82574 LAN chip.
>
> But if I move the call to sb_Before_PCI_Init behind case ?(0x15 <<3) | 0 the
> enumeration succeed but coreboot crashes later into nothing. The Sage
> Debugger fails.
>
> I can?t imagine why.
>
>
>
> Marc have you any idea?

This looks like a problem in the sb800 cimx wrapper logic. Cimx
doesn't treat the devices separately. it lumps all the configuration
and enables together, making the coreboot chipset device enable
callback fail to enable the device, so it gets disabled. The sb900
wrapper appears to fix this issue with cimx setup in early init. You
may want to try porting those changes to the sb800.

I don't know why it fails later, but I assume it is due to the missing
config since you moved the call earlier in the process. You could try
calling it multiple times. I'm not sure how it handles that, though.

Kerry,
Do you have any comments?



Marc

-- 
http://se-eng.com


From Kerry.She at amd.com  Tue Jan 17 09:07:14 2012
From: Kerry.She at amd.com (She, Kerry)
Date: Tue, 17 Jan 2012 16:07:14 +0800
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
	<CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>

Hello Walfqang,

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Marc Jones
> Sent: Tuesday, January 17, 2012 3:23 AM
> To: Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
> <wmkamp at datakamp.de> wrote:
> > Hello,
> >
> >
> >
> > I found a problem with the PCI enumeration of the PCIe Ports in the
> > CIMX/SB800 Southbridge for the INAGUA platform.
> >
> > The .../southbridge/amd/cimx/sb800/late.c routine calls the function
> > sb_Before_PCI_Init after
> >
> > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) |
> 0
> > are probed in the routine ../devices/pci_device.c function
> >
> > pci_probe_dev they are not yet initialized. The probing fails and also
> > devices behind the bridge are not recognized.
> >
> > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> >
> > But if I move the call to sb_Before_PCI_Init behind case ?(0x15 <<3) |
> 0 the
> > enumeration succeed but coreboot crashes later into nothing. The Sage
> > Debugger fails.
> >
> > I can't imagine why.
> >
> >
> >
> > Marc have you any idea?
> 
> This looks like a problem in the sb800 cimx wrapper logic. Cimx
> doesn't treat the devices separately. it lumps all the configuration
> and enables together, making the coreboot chipset device enable
> callback fail to enable the device, so it gets disabled. The sb900
> wrapper appears to fix this issue with cimx setup in early init. You
> may want to try porting those changes to the sb800.
> 
> I don't know why it fails later, but I assume it is due to the missing
> config since you moved the call earlier in the process. You could try
> calling it multiple times. I'm not sure how it handles that, though.
> 
> Kerry,
> Do you have any comments?
If the enumeration fail, I suggest you should check the PCIE deassert GPIO setting.
Thanks

Kerry
> 
> 
> Marc
> 
> --
> http://se-eng.com
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From gerrit at coreboot.org  Tue Jan 17 13:39:31 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Tue, 17 Jan 2012 13:39:31 +0100
Subject: [coreboot] New patch to review for coreboot: 7e6b6db Add coreboot
	version to id area
References: <I325491a0c42911d9d6ecd59e21ee1b756c987693+0@gerrit.coreboot.org>
Message-ID: <I325491a0c42911d9d6ecd59e21ee1b756c987693+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/537

-gerrit

commit 7e6b6db4ab80ffb8103c6a6ab32f3b648976b7fe
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jan 17 13:13:59 2012 +0100

    Add coreboot version to id area
    
    There was no good way to extract the build version from an image.
    
    This change will be mostly backward compatible: The only assumption
    that could break is that the board name string end directly before
    the 3 dwords that represent .id's "header".
    
    Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/arch/x86/Makefile.inc |   12 ++++++------
 src/arch/x86/lib/id.inc   |    3 +++
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..54f0f82 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -321,15 +321,15 @@ $(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions
 $(obj)/bootblock/bootblock.S: $$(bootblock_inc)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	mkdir -p $(obj)/bootblock
-	printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@
+	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj)/config.h $(obj)/build.h
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
@@ -371,15 +371,15 @@ $(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions
 $(obj)/romstage/crt0.S: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	mkdir -p $(obj)/romstage
-	printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
 
 seabios:
 	$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
diff --git a/src/arch/x86/lib/id.inc b/src/arch/x86/lib/id.inc
index 443dbad..f8aba0b 100644
--- a/src/arch/x86/lib/id.inc
+++ b/src/arch/x86/lib/id.inc
@@ -2,10 +2,13 @@
 
 	.globl __id_start
 __id_start:
+ver:
+	.asciz COREBOOT_VERSION
 vendor:
 	.asciz CONFIG_MAINBOARD_VENDOR
 part:
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver  /* Reverse offset to the vendor id */
 .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor  /* Reverse offset to the vendor id */
 .long __id_end + CONFIG_ID_SECTION_OFFSET - part    /* Reverse offset to the part number */
 .long CONFIG_ROM_SIZE                               /* Size of this romimage */


From paulepanter at users.sourceforge.net  Tue Jan 17 15:16:18 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 17 Jan 2012 15:16:18 +0100
Subject: [coreboot] [RFC] Announce new posts in blogs.coreboot.org on list
Message-ID: <1326809778.11113.72.camel@mattotaupa>

Dear coreboot folks,


as hopefully everyone of you knows, coreboot has a blog [1].
Unfortunately not a lot of posts are written. So for people interested
in coreboot and subscribed to the list but not using RSS/Atom feeds
maybe an announcement could be sent to the list? (At least until ten
blog posts per day are written.)

If no subscriber objects during the next week, maybe Patrick could set
up a hook in Wordpress? That would be great.


Thanks,

Paul


[1] http://blogs.coreboot.org/
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From libv at skynet.be  Tue Jan 17 15:27:53 2012
From: libv at skynet.be (Luc Verhaegen)
Date: Tue, 17 Jan 2012 15:27:53 +0100
Subject: [coreboot] [RFC] Announce new posts in blogs.coreboot.org
	on	list
In-Reply-To: <1326809778.11113.72.camel@mattotaupa>
References: <1326809778.11113.72.camel@mattotaupa>
Message-ID: <20120117142753.GD3259@skynet.be>

On Tue, Jan 17, 2012 at 03:16:18PM +0100, Paul Menzel wrote:
> Dear coreboot folks,
> 
> 
> as hopefully everyone of you knows, coreboot has a blog [1].
> Unfortunately not a lot of posts are written. So for people interested
> in coreboot and subscribed to the list but not using RSS/Atom feeds
> maybe an announcement could be sent to the list? (At least until ten
> blog posts per day are written.)
> 
> If no subscriber objects during the next week, maybe Patrick could set
> up a hook in Wordpress? That would be great.
> 
> 
> Thanks,
> 
> Paul
> 
> 
> [1] http://blogs.coreboot.org/

Thanks, I never knew about this.

First off, a list of bloggers who are posting there might be a nice 
feature which other "planets" tend to have.

Secondly, feel free to add libv.livejournal.com, even though i am too 
deep in graphics driver development these days to actively do coreboot 
or flashrom work.

Luc Verhaegen.


From josh at pcinw.net  Fri Jan 13 18:03:06 2012
From: josh at pcinw.net (Josh Stump)
Date: Fri, 13 Jan 2012 09:03:06 -0800
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
Message-ID: <CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>

I have a Lenovo T60 Type 8743-GZU.  From experience I know that with the
stock BIOS if I put in 4Gb of RAM I can only utilze 3Gb even with a 64bit
OS installed.  Is this a limitation of the stock BIOS that coreboot can
overcome or is this simply a chipset limitation and even if I got coreboot
flashed I still would only have use of 4Gb of RAM.  Does anyone know for
certain?  If it will allow full usage of the 4Gb of RAM then I think it
would be worth figuring out what parts I might need to flash my rom over.
 Thank you.

Josh Stump
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From rminnich at gmail.com  Tue Jan 17 22:20:46 2012
From: rminnich at gmail.com (ron minnich)
Date: Tue, 17 Jan 2012 13:20:46 -0800
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
References: <CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
Message-ID: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>

It's almost certainly impossible to get coreboot going on your T60.

ron


From peter at stuge.se  Tue Jan 17 22:51:34 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 17 Jan 2012 22:51:34 +0100
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
References: <CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
Message-ID: <20120117215134.20488.qmail@stuge.se>

Josh Stump wrote:
> I have a Lenovo T60 Type 8743-GZU.  From experience I know that with the
> stock BIOS if I put in 4Gb of RAM I can only utilze 3Gb even with a 64bit
> OS installed.  Is this a limitation of the stock BIOS that coreboot can
> overcome or is this simply a chipset limitation and even if I got coreboot
> flashed I still would only have use of 4Gb of RAM.  Does anyone know for
> certain?

It is a limitation of the factory BIOS. For comparison, on an X60
with 4GB of RAM with coreboot there is immediately 3.2GB available
for OS use.

This is with the standard resource allocator in coreboot, ie. without
any intense optimizations. If you work on optimizing this, you may
get even more usable RAM.

The technical limit is that many of the hardware parts in the system
require that they be memory mapped into the CPU bus, and that is only
32 bits, so some of the 4GB of RAM will be "covered" by these
hardware memory regions, but with coreboot you have an opportunity to
work on reducing this to the bare minimum.


> what parts I might need to flash my rom over.

You need the flashrom source, a small patch, and my bucts utility
from http://git.stuge.se/?p=bucts.git

Patch flashrom to use RES1 SPI identification and spi_chip_write1 for
your flash chip, as well as change the flash chip model id to fit the
RES1 command.

then run flashrom -p internal:laptop=force_I_want_a_brick -r factory.bin
# this step is IMPORTANT since the factory BIOS in your machine is
# tied to your particular system board "planar in IBM FRU terms" with
# a unique ID not present in factory BIOS updates

then build coreboot.rom
# note that you must include the correct VGA BIOS for your machine in
# order to have any graphics working when you use coreboot

then run dd if=coreboot.rom of=top64k.bin bs=1 \
 skip=$[sizeof(coreboot.rom) - 0x10000] count=64k

then run dd if=top64k of=coreboot.rom bs=1 \
 seek=$[sizeof(coreboot.rom) - 0x20000] count=64k conv=notrunc

then run bucts 1

then run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom
# this will be slow, and shall generate an erase error at e.g. 0x1f0000
# when working with a 2 Mbyte flash chip.

then power cycle, now starting with coreboot

then undo the flashrom patch, so that you have a stock flashrom

then run bucts 0

then run flashrom -p internal:laptop=force_I_want_a_brick -w coreboot.rom
# his will successfully overwrite the entire flash chip, including
# the last 64k that were write protected with the factory BIOS.


Many thanks to Sven for figuring out this procedure! It has been
successfully performed on at least two X60 machines with factory
BIOS.


ron minnich wrote:
> It's almost certainly impossible to get coreboot going on your T60.

I believe Sven's port is working!


//Peter


From peter at stuge.se  Wed Jan 18 00:14:36 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 18 Jan 2012 00:14:36 +0100
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <20120117215134.20488.qmail@stuge.se>
References: <CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<20120117215134.20488.qmail@stuge.se>
Message-ID: <20120117231436.26256.qmail@stuge.se>

Peter Stuge wrote:
> then run dd if=coreboot.rom of=top64k.bin bs=1 \
>  skip=$[sizeof(coreboot.rom) - 0x10000] count=64k

Insert one step here:

then run dd if=coreboot.rom bs=1 \
 skip=$[sizeof(coreboot.rom) - 0x10000] count=64k | hexdump
# and verify that the complete range is filled with ff bytes before
# proceeding further. if this is not the case, the coreboot image
# needs to be recreated with the second-to-last 64kbyte block unused


> then run dd if=top64k of=coreboot.rom bs=1 \
>  seek=$[sizeof(coreboot.rom) - 0x20000] count=64k conv=notrunc

That should of course read:

then run dd if=top64k.bin of=coreboot.rom bs=1 \
 seek=$[sizeof(coreboot.rom) - 0x20000] count=64k conv=notrunc


//Peter


From rminnich at gmail.com  Wed Jan 18 00:25:53 2012
From: rminnich at gmail.com (ron minnich)
Date: Tue, 17 Jan 2012 15:25:53 -0800
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <20120117215134.20488.qmail@stuge.se>
References: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<20120117215134.20488.qmail@stuge.se>
Message-ID: <CAP6exYJzD0cuGtPRz6AopwyJGAhqcCyLw-sNCLXb3u4YZKHT4g@mail.gmail.com>

On Tue, Jan 17, 2012 at 1:51 PM, Peter Stuge <peter at stuge.se> wrote:

> ron minnich wrote:
>> It's almost certainly impossible to get coreboot going on your T60.
>
> I believe Sven's port is working!

on x60, good news. But T60?

ron


From peter at stuge.se  Wed Jan 18 01:22:33 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 18 Jan 2012 01:22:33 +0100
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <CAP6exYJzD0cuGtPRz6AopwyJGAhqcCyLw-sNCLXb3u4YZKHT4g@mail.gmail.com>
References: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<20120117215134.20488.qmail@stuge.se>
	<CAP6exYJzD0cuGtPRz6AopwyJGAhqcCyLw-sNCLXb3u4YZKHT4g@mail.gmail.com>
Message-ID: <20120118002233.30994.qmail@stuge.se>

ron minnich wrote:
> >> It's almost certainly impossible to get coreboot going on your T60.
> >
> > I believe Sven's port is working!
> 
> on x60, good news. But T60?

Yes, also. Sven is using it on his machine already. It needed some
more work besides the X60, but it works for him.


//Peter


From rminnich at gmail.com  Wed Jan 18 01:37:42 2012
From: rminnich at gmail.com (ron minnich)
Date: Tue, 17 Jan 2012 16:37:42 -0800
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <20120118002233.30994.qmail@stuge.se>
References: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<20120117215134.20488.qmail@stuge.se>
	<CAP6exYJzD0cuGtPRz6AopwyJGAhqcCyLw-sNCLXb3u4YZKHT4g@mail.gmail.com>
	<20120118002233.30994.qmail@stuge.se>
Message-ID: <CAP6exYJ8eKuJGWKA425t_URcAeV=PcUdS-_mEYLW=vxe6kh0aw@mail.gmail.com>

On Tue, Jan 17, 2012 at 4:22 PM, Peter Stuge <peter at stuge.se> wrote:

> Yes, also. Sven is using it on his machine already. It needed some
> more work besides the X60, but it works for him.

I am in awe of these accomplishments! Geez, I go away for just a
little while and these great things happen :-)

ron


From gerrit at coreboot.org  Wed Jan 18 01:43:44 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 01:43:44 +0100
Subject: [coreboot] New patch to review for coreboot: 44085b2 Clean up AMD
	romstage.c whitespace indent issues
References: <I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9+0@gerrit.coreboot.org>
Message-ID: <I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/538

-gerrit

commit 44085b2509c0422a43b2c5a88b93f81e2be3a9c7
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 15:41:03 2012 -0700

    Clean up AMD romstage.c whitespace indent issues
    
    Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/romstage.c      |  149 ++++++++++++++-------------
 src/mainboard/amd/torpedo/get_bus_conf.c |  118 ++++++++++-----------
 src/mainboard/amd/torpedo/romstage.c     |  167 +++++++++++++++---------------
 3 files changed, 219 insertions(+), 215 deletions(-)

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index c4e8b15..d5fa8c5 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -38,80 +38,83 @@
 #include <arch/cpu.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-u32 agesawrapper_amdinitmmio (void);
-u32 agesawrapper_amdinitreset (void);
-u32 agesawrapper_amdinitearly (void);
-u32 agesawrapper_amdinitenv (void);
-u32 agesawrapper_amdinitlate (void);
-u32 agesawrapper_amdinitpost (void);
-u32 agesawrapper_amdinitmid (void);
+u32 agesawrapper_amdinitmmio(void);
+u32 agesawrapper_amdinitreset(void);
+u32 agesawrapper_amdinitearly(void);
+u32 agesawrapper_amdinitenv(void);
+u32 agesawrapper_amdinitlate(void);
+u32 agesawrapper_amdinitpost(void);
+u32 agesawrapper_amdinitmid(void);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  u32 val;
-
-  if (!cpu_init_detectedx && boot_cpu()) {
-    post_code(0x30);
-    sb_Poweron_Init();
-
-    post_code(0x31);
-    kbc1100_early_init(CONFIG_SIO_PORT);
-    console_init();
-  }
-
-  /* Halt if there was a built in self test failure */
-  post_code(0x34);
-  report_bist_failure(bist);
-
-  // Load MPB
-  val = cpuid_eax(1);
-  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
-  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
-  post_code(0x35);
-  val = agesawrapper_amdinitmmio();
-
-  post_code(0x37);
-  val = agesawrapper_amdinitreset();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-  }
-
-  post_code(0x38);
-  printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
-  post_code(0x39);
-  val = agesawrapper_amdinitearly ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
-
-  post_code(0x40);
-  val = agesawrapper_amdinitpost ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
-
-  post_code(0x41);
-  val = agesawrapper_amdinitenv ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
-
-  /* Initialize i8259 pic */
-  post_code(0x41);
-  setup_i8259 ();
-
-  /* Initialize i8254 timers */
-  post_code(0x42);
-  setup_i8254 ();
-
-  post_code(0x50);
-  copy_and_run(0);
-
-  post_code(0x54);  // Should never see this post code.
+	u32 val;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x30);
+		sb_Poweron_Init();
+
+		post_code(0x31);
+		kbc1100_early_init(CONFIG_SIO_PORT);
+		console_init();
+	}
+
+	/* Halt if there was a built in self test failure */
+	post_code(0x34);
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	post_code(0x35);
+	val = agesawrapper_amdinitmmio();
+
+	post_code(0x37);
+	val = agesawrapper_amdinitreset();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
+		       val);
+	}
+
+	post_code(0x38);
+	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+	post_code(0x39);
+	val = agesawrapper_amdinitearly();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+	post_code(0x40);
+	val = agesawrapper_amdinitpost();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+	post_code(0x41);
+	val = agesawrapper_amdinitenv();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+	/* Initialize i8259 pic */
+	post_code(0x41);
+	setup_i8259();
+
+	/* Initialize i8254 timers */
+	post_code(0x42);
+	setup_i8254();
+
+	post_code(0x50);
+	copy_and_run(0);
+
+	post_code(0x54);	// Should never see this post code.
 }
-
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index 13019ff..7dbe9a5 100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -27,7 +27,6 @@
 #include "SbEarly.h"
 #include "agesawrapper.h"
 
-
 /* Global variables for MB layouts and these will be shared by irqtable mptable
 * and acpi_tables busnum is default.
 */
@@ -40,7 +39,7 @@ u8 bus_sb900[3];
 * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
 */
 u32 pci1234x[] = {
-  0x0000ff0,
+	0x0000ff0,
 };
 
 /*
@@ -48,7 +47,7 @@ u32 pci1234x[] = {
 * assume every chain only have 4 ht device at most
 */
 u32 hcdnx[] = {
-  0x20202020,
+	0x20202020,
 };
 
 u32 bus_type[256];
@@ -59,22 +58,20 @@ u32 sbdn_sb900;
 
 static u32 get_bus_conf_done = 0;
 
-
-
-
 void get_bus_conf(void)
 {
-  u32 status;
+	u32 status;
 
-  device_t dev;
-  int i, j;
+	device_t dev;
+	int i, j;
 
-  if (get_bus_conf_done == 1)
-    return;   /* do it only once */
+	if (get_bus_conf_done == 1)
+		return;		/* do it only once */
 
-  get_bus_conf_done = 1;
+	get_bus_conf_done = 1;
 
-  printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+	printk(BIOS_DEBUG,
+	       "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
 /*
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
@@ -90,57 +87,58 @@ void get_bus_conf(void)
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
-  status = agesawrapper_amdinitlate();
-  if(status) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
+	status = agesawrapper_amdinitlate();
+	if (status) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n",
+		       status);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
 
-  sbdn_sb900 = 0;
+	sbdn_sb900 = 0;
 
-  for (i = 0; i < 3; i++) {
-    bus_sb900[i] = 0;
-  }
+	for (i = 0; i < 3; i++) {
+		bus_sb900[i] = 0;
+	}
 
-  for (i = 0; i < 256; i++) {
-    bus_type[i] = 0; /* default ISA bus. */
-  }
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0;	/* default ISA bus. */
+	}
 
-
-  bus_type[0] = 1;  /* pci */
+	bus_type[0] = 1;	/* pci */
 
 //  bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-  bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
-
-  /* sb900 */
-  dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4));
-
-
-
-  if (dev) {
-    bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-    bus_isa++;
-    for (j = bus_sb900[1]; j < bus_isa; j++)
-      bus_type[j] = 1;
-  }
-
-  for (i = 0; i < 4; i++) {
-    dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, i));
-    if (dev) {
-      bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-      bus_isa++;
-    }
-  }
-  for (j = bus_sb900[2]; j < bus_isa; j++)
-    bus_type[j] = 1;
-
-
-  /* I/O APICs:   APIC ID Version State   Address */
-  bus_isa = 10;
-
-  sb_Late_Post();
-  printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+	bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
+
+	/* sb900 */
+	dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4));
+
+	if (dev) {
+		bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb900[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev =
+		    dev_find_slot(bus_sb900[0],
+				  PCI_DEVFN(sbdn_sb900 + 0x14, i));
+		if (dev) {
+			bus_sb900[2 + i] =
+			    pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+	for (j = bus_sb900[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+
+	sb_Late_Post();
+	printk(BIOS_DEBUG,
+	       "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
 }
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index 317f697..ea902d8 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -40,88 +40,91 @@
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  u32 val;
-
-  post_code(0x35);
-  val = agesawrapper_amdinitmmio();
-  if(val) {
-	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
-
-  if (!cpu_init_detectedx && boot_cpu()) {
-    post_code(0x30);
-	gpioEarlyInit();
-    sb_poweron_init();
-
-    post_code(0x31);
-
-    kbc1100_early_init(CONFIG_SIO_PORT);
-
-    post_code(0x32);
-    uart_init();
-    post_code(0x33);
-    console_init();
-  }
-
-  /* Halt if there was a built in self test failure */
-  post_code(0x34);
-  report_bist_failure(bist);
-
-  // Load MPB
-  val = cpuid_eax(1);
-  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
-  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
-  post_code(0x36);
-  val = agesawrapper_amdinitreset();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
-
-  post_code(0x37);
-  val = agesawrapper_amdinitearly ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
-
-  post_code(0x38);
-  val = agesawrapper_amdinitpost ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
-
-  post_code(0x39);
-  sb_before_pci_init ();
-  printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
-
-  post_code(0x40);
-  val = agesawrapper_amdinitenv ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
-
-  /* Initialize i8259 pic */
-  post_code(0x41);
-  setup_i8259 ();
-  printk(BIOS_DEBUG, "Got past setup_i8259\n");
-
-  /* Initialize i8254 timers */
-  post_code(0x42);
-  setup_i8254 ();
-  printk(BIOS_DEBUG, "Got past setup_i8254\n");
-
-  post_code(0x43);
-  copy_and_run(0);
-  printk(BIOS_DEBUG, "Got past copy_and_run\n");
-
-  post_code(0x44);  // Should never see this post code.
+	u32 val;
+
+	post_code(0x35);
+	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x30);
+		gpioEarlyInit();
+		sb_poweron_init();
+
+		post_code(0x31);
+
+		kbc1100_early_init(CONFIG_SIO_PORT);
+
+		post_code(0x32);
+		uart_init();
+		post_code(0x33);
+		console_init();
+	}
+
+	/* Halt if there was a built in self test failure */
+	post_code(0x34);
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	post_code(0x36);
+	val = agesawrapper_amdinitreset();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+
+	post_code(0x37);
+	val = agesawrapper_amdinitearly();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+	post_code(0x38);
+	val = agesawrapper_amdinitpost();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+	post_code(0x39);
+	sb_before_pci_init();
+	printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+
+	post_code(0x40);
+	val = agesawrapper_amdinitenv();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
+		       val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+	/* Initialize i8259 pic */
+	post_code(0x41);
+	setup_i8259();
+	printk(BIOS_DEBUG, "Got past setup_i8259\n");
+
+	/* Initialize i8254 timers */
+	post_code(0x42);
+	setup_i8254();
+	printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
+	post_code(0x43);
+	copy_and_run(0);
+	printk(BIOS_DEBUG, "Got past copy_and_run\n");
+
+	post_code(0x44);	// Should never see this post code.
 }
-


From gerrit at coreboot.org  Wed Jan 18 01:43:44 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 01:43:44 +0100
Subject: [coreboot] New patch to review for coreboot: c4d2e0f Clean up AMD
	romstage.c serial output
References: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+0@gerrit.coreboot.org>
Message-ID: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/539

-gerrit

commit c4d2e0ff1d49e706c68812b5afa54d5470f0a32d
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 16:51:24 2012 -0700

    Clean up AMD romstage.c serial output
    
    This cleans up the strings in romstage.c, removing the ugly "got past".
    Also, cleaned up comments and some spacing.
    
    Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/romstage.c        |   41 ++++++++++++--------
 src/mainboard/amd/persimmon/romstage.c     |   57 +++++++++++++++++----------
 src/mainboard/amd/south_station/romstage.c |   53 ++++++++++++++++---------
 src/mainboard/amd/torpedo/get_bus_conf.c   |   19 +++------
 src/mainboard/amd/torpedo/romstage.c       |   45 +++++++++++++---------
 src/mainboard/amd/union_station/romstage.c |   49 +++++++++++++++--------
 src/mainboard/asrock/e350m1/romstage.c     |   49 ++++++++++++++---------
 7 files changed, 190 insertions(+), 123 deletions(-)

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index d5fa8c5..fa442a5 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -63,47 +63,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index bf8535f..ea0fab0 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #include <stdint.h>
@@ -46,12 +46,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -67,43 +69,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 95f27bd..cfe6789 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -43,12 +43,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -64,47 +66,60 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);  // Should never see this post code.
+	post_code(0x54);  /* Should never see this post code. */
 }
 
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index 7dbe9a5..fb8c095 100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -54,7 +54,6 @@ u32 bus_type[256];
 
 u32 sbdn_sb900;
 
-//KZ [092110]extern void get_pci1234(void);
 
 static u32 get_bus_conf_done = 0;
 
@@ -70,8 +69,7 @@ void get_bus_conf(void)
 
 	get_bus_conf_done = 1;
 
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
 /*
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
@@ -87,12 +85,13 @@ void get_bus_conf(void)
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate ");
 	status = agesawrapper_amdinitlate();
 	if (status) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n",
-		       status);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
 
 	sbdn_sb900 = 0;
 
@@ -106,7 +105,6 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;	/* pci */
 
-//  bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
 
 	/* sb900 */
@@ -114,7 +112,6 @@ void get_bus_conf(void)
 
 	if (dev) {
 		bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
 		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_isa++;
 		for (j = bus_sb900[1]; j < bus_isa; j++)
@@ -122,8 +119,7 @@ void get_bus_conf(void)
 	}
 
 	for (i = 0; i < 4; i++) {
-		dev =
-		    dev_find_slot(bus_sb900[0],
+		dev = dev_find_slot(bus_sb900[0],
 				  PCI_DEVFN(sbdn_sb900 + 0x14, i));
 		if (dev) {
 			bus_sb900[2 + i] =
@@ -139,6 +135,5 @@ void get_bus_conf(void)
 	bus_isa = 10;
 
 	sb_Late_Post();
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__));
 }
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index ea902d8..164b7e0 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -45,12 +45,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -77,54 +78,60 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x36);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x38);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "sb_before_pci_init ");
 	sb_before_pci_init();
-	printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+	printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
+	printk(BIOS_DEBUG, "setup_i8259\n");
 	setup_i8259();
-	printk(BIOS_DEBUG, "Got past setup_i8259\n");
 
 	/* Initialize i8254 timers */
 	post_code(0x42);
+	printk(BIOS_DEBUG, "setup_i8254\n");
 	setup_i8254();
-	printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
 
 	post_code(0x43);
 	copy_and_run(0);
-	printk(BIOS_DEBUG, "Got past copy_and_run\n");
+	printk(BIOS_ERR, "Error: copy_and_run returned!\n");
 
 	post_code(0x44);	// Should never see this post code.
 }
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index e7f05e8..14d1958 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -43,8 +43,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
@@ -61,46 +63,59 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
 	post_code(0x54);  // Should never see this post code.
 }
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 133aca7..6e83a07 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,12 +47,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	u8 reg8;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr(0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -68,47 +70,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -120,6 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }


From gerrit at coreboot.org  Wed Jan 18 01:43:45 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 01:43:45 +0100
Subject: [coreboot] New patch to review for coreboot: 6c42105 Remove old AMD
	#define
References: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+0@gerrit.coreboot.org>
Message-ID: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/540

-gerrit

commit 6c421059d3a6ff83c443dd8693b0fa3e8d0f1159
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:30:31 2012 -0700

    Remove old AMD #define
    
    The #define REQUIRED_CALLOUTS is no longer used on these platforms.
    
    Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/persimmon/BiosCallOuts.h     |    1 -
 src/mainboard/amd/south_station/BiosCallOuts.h |    1 -
 src/mainboard/amd/union_station/BiosCallOuts.h |    1 -
 3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index e023e38..d9e4497 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS			12
 #define BIOS_HEAP_START_ADDRESS		0x00010000
 #define BIOS_HEAP_SIZE				0x20000		/* 64MB */
 
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.h
+++ b/src/mainboard/amd/south_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.h
+++ b/src/mainboard/amd/union_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 


From gerrit at coreboot.org  Wed Jan 18 01:43:45 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 01:43:45 +0100
Subject: [coreboot] New patch to review for coreboot: 95f1144 Remove
	duplicated line of code in AMD wrappers.
References: <I438da05c770ded0bd32256f1c157cabcc383667a+0@gerrit.coreboot.org>
Message-ID: <I438da05c770ded0bd32256f1c157cabcc383667a+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/541

-gerrit

commit 95f1144b8a9e8970d947780a40bff7344d21ebd6
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:34:03 2012 -0700

    Remove duplicated line of code in AMD wrappers.
    
    This line was unnecessary and was duplicated on several mainboards.
    
    Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/agesawrapper.c        |    1 -
 src/mainboard/amd/persimmon/agesawrapper.c     |    1 -
 src/mainboard/amd/south_station/agesawrapper.c |    1 -
 src/mainboard/amd/union_station/agesawrapper.c |    1 -
 src/mainboard/asrock/e350m1/agesawrapper.c     |    1 -
 5 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index c33d20f..715202a 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -511,7 +511,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index f9847c2..6e9997f 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -515,7 +515,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/south_station/agesawrapper.c
+++ b/src/mainboard/amd/south_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/union_station/agesawrapper.c
+++ b/src/mainboard/amd/union_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index fc87029..742344a 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 


From peter at stuge.se  Wed Jan 18 01:47:58 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 18 Jan 2012 01:47:58 +0100
Subject: [coreboot] Lenovo T60 Type 8743-GZU - RAM Support? 3Gb or 4Gb
In-Reply-To: <CAP6exYJ8eKuJGWKA425t_URcAeV=PcUdS-_mEYLW=vxe6kh0aw@mail.gmail.com>
References: <CAP6exYKABFGP6FjBLHU76zbb_Yk9T9rcofV3U7bHjCRankj+Nw@mail.gmail.com>
	<CADcGPUE3cq4SvvFgz3aGnSB+reqM7KFPa-AKd5cBfRDSbDWcKg@mail.gmail.com>
	<20120117215134.20488.qmail@stuge.se>
	<CAP6exYJzD0cuGtPRz6AopwyJGAhqcCyLw-sNCLXb3u4YZKHT4g@mail.gmail.com>
	<20120118002233.30994.qmail@stuge.se>
	<CAP6exYJ8eKuJGWKA425t_URcAeV=PcUdS-_mEYLW=vxe6kh0aw@mail.gmail.com>
Message-ID: <20120118004758.327.qmail@stuge.se>

ron minnich wrote:
> > Yes, also. Sven is using it on his machine already. It needed some
> > more work besides the X60, but it works for him.
> 
> I am in awe of these accomplishments! Geez, I go away for just a
> little while and these great things happen :-)

Sven is doing a great job with the ThinkPad ports! All credit to him.

During the weekend I believe the first person outside the project
flashed coreboot onto his X60, using the procedure I described in
the previous email. One or three issues were quickly discovered,
where the more annoying one, current coreboot git code not resuming
properly, should actually already have been known by me. I'm
researching this now, we need to fix it.

I tried a quick fix which turned out to be a bit too ambitious and
which bricked his machine, so I then spent the rest of the weekend on
soldering an external programming header into his laptop and getting
an SPI flasher set up. Meanwhile I lent him my machine so that he
wouldn't be too badly affected. I hope he'll join at least on IRC
now and then, and give some feedback from the user perspective.

He was very very pleased to be able to free his firmware! :)


//Peter


From gerrit at coreboot.org  Wed Jan 18 06:04:00 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 06:04:00 +0100
Subject: [coreboot] Patch set updated for coreboot: fb666e6 Remove
	duplicated line of code in AMD wrappers.
References: <I438da05c770ded0bd32256f1c157cabcc383667a+0@gerrit.coreboot.org>
Message-ID: <I438da05c770ded0bd32256f1c157cabcc383667a+2@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/541

-gerrit

commit fb666e6bc435f4550aabc76e2d73f6e595986c4c
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:34:03 2012 -0700

    Remove duplicated line of code in AMD wrappers.
    
    This line was unnecessary and was duplicated on several mainboards.
    
    Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/agesawrapper.c        |    1 -
 src/mainboard/amd/persimmon/agesawrapper.c     |    1 -
 src/mainboard/amd/south_station/agesawrapper.c |    1 -
 src/mainboard/amd/union_station/agesawrapper.c |    1 -
 src/mainboard/asrock/e350m1/agesawrapper.c     |    1 -
 5 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index c33d20f..715202a 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -511,7 +511,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index f9847c2..6e9997f 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -515,7 +515,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/south_station/agesawrapper.c
+++ b/src/mainboard/amd/south_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/union_station/agesawrapper.c
+++ b/src/mainboard/amd/union_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index fc87029..742344a 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 


From gerrit at coreboot.org  Wed Jan 18 06:04:00 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 06:04:00 +0100
Subject: [coreboot] Patch set updated for coreboot: 62b4e27 Remove old AMD
	#define
References: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+0@gerrit.coreboot.org>
Message-ID: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+2@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/540

-gerrit

commit 62b4e27122c5f8482acd813199ad3501e17210a8
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:30:31 2012 -0700

    Remove old AMD #define
    
    The #define REQUIRED_CALLOUTS is no longer used on these platforms.
    
    Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/persimmon/BiosCallOuts.h     |    1 -
 src/mainboard/amd/south_station/BiosCallOuts.h |    1 -
 src/mainboard/amd/union_station/BiosCallOuts.h |    1 -
 3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index e023e38..d9e4497 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS			12
 #define BIOS_HEAP_START_ADDRESS		0x00010000
 #define BIOS_HEAP_SIZE				0x20000		/* 64MB */
 
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.h
+++ b/src/mainboard/amd/south_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.h
+++ b/src/mainboard/amd/union_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 


From gerrit at coreboot.org  Wed Jan 18 06:04:00 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 06:04:00 +0100
Subject: [coreboot] Patch set updated for coreboot: edd8829 Clean up AMD
	romstage.c serial output
References: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+0@gerrit.coreboot.org>
Message-ID: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+2@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/539

-gerrit

commit edd8829a75357c5ca2ed66425887f9b86f542c3e
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 16:51:24 2012 -0700

    Clean up AMD romstage.c serial output
    
    This cleans up the strings in romstage.c, removing the ugly "got past".
    Also, cleaned up comments and some spacing.
    
    Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/romstage.c        |   41 ++++++++++++--------
 src/mainboard/amd/persimmon/romstage.c     |   57 +++++++++++++++++----------
 src/mainboard/amd/south_station/romstage.c |   53 ++++++++++++++++---------
 src/mainboard/amd/torpedo/get_bus_conf.c   |   19 +++------
 src/mainboard/amd/torpedo/romstage.c       |   45 +++++++++++++---------
 src/mainboard/amd/union_station/romstage.c |   49 +++++++++++++++--------
 src/mainboard/asrock/e350m1/romstage.c     |   49 ++++++++++++++---------
 7 files changed, 190 insertions(+), 123 deletions(-)

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index d5fa8c5..fa442a5 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -63,47 +63,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index bf8535f..ea0fab0 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #include <stdint.h>
@@ -46,12 +46,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -67,43 +69,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 95f27bd..cfe6789 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -43,12 +43,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -64,47 +66,60 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);  // Should never see this post code.
+	post_code(0x54);  /* Should never see this post code. */
 }
 
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index 7dbe9a5..1e04678 100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -54,7 +54,6 @@ u32 bus_type[256];
 
 u32 sbdn_sb900;
 
-//KZ [092110]extern void get_pci1234(void);
 
 static u32 get_bus_conf_done = 0;
 
@@ -70,8 +69,7 @@ void get_bus_conf(void)
 
 	get_bus_conf_done = 1;
 
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
 /*
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
@@ -87,12 +85,13 @@ void get_bus_conf(void)
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate ");
 	status = agesawrapper_amdinitlate();
 	if (status) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n",
-		       status);
+		printk(BIOS_DEBUG, "error level: %x \n", status);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
 
 	sbdn_sb900 = 0;
 
@@ -106,7 +105,6 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;	/* pci */
 
-//  bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
 
 	/* sb900 */
@@ -114,7 +112,6 @@ void get_bus_conf(void)
 
 	if (dev) {
 		bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
 		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_isa++;
 		for (j = bus_sb900[1]; j < bus_isa; j++)
@@ -122,8 +119,7 @@ void get_bus_conf(void)
 	}
 
 	for (i = 0; i < 4; i++) {
-		dev =
-		    dev_find_slot(bus_sb900[0],
+		dev = dev_find_slot(bus_sb900[0],
 				  PCI_DEVFN(sbdn_sb900 + 0x14, i));
 		if (dev) {
 			bus_sb900[2 + i] =
@@ -139,6 +135,5 @@ void get_bus_conf(void)
 	bus_isa = 10;
 
 	sb_Late_Post();
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__);
 }
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index ea902d8..164b7e0 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -45,12 +45,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -77,54 +78,60 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x36);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x38);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "sb_before_pci_init ");
 	sb_before_pci_init();
-	printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+	printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
+	printk(BIOS_DEBUG, "setup_i8259\n");
 	setup_i8259();
-	printk(BIOS_DEBUG, "Got past setup_i8259\n");
 
 	/* Initialize i8254 timers */
 	post_code(0x42);
+	printk(BIOS_DEBUG, "setup_i8254\n");
 	setup_i8254();
-	printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
 
 	post_code(0x43);
 	copy_and_run(0);
-	printk(BIOS_DEBUG, "Got past copy_and_run\n");
+	printk(BIOS_ERR, "Error: copy_and_run returned!\n");
 
 	post_code(0x44);	// Should never see this post code.
 }
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index e7f05e8..14d1958 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -43,8 +43,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
@@ -61,46 +63,59 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
 	post_code(0x54);  // Should never see this post code.
 }
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 133aca7..6e83a07 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,12 +47,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	u8 reg8;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr(0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -68,47 +70,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val) {
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
+	}
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
 
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
 	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "passed.\n");
 	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -120,6 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }


From gerrit at coreboot.org  Wed Jan 18 08:36:07 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:07 +0100
Subject: [coreboot] New patch to review for coreboot: 0455fd8 Inagua:
	Synchronize AMD/inagua mainboard.
References: <Ia038e5a2b9550fe81bb075f31e30b98354758e9e+0@gerrit.coreboot.org>
Message-ID: <Ia038e5a2b9550fe81bb075f31e30b98354758e9e+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/542

-gerrit

commit 0455fd8f405247a40aaf1710e2df9eda20b685a2
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:04:31 2012 +0800

    Inagua: Synchronize AMD/inagua mainboard.
    
    AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
    Persimmom update a lot in the last few month, sync these modification to inagua.
    
    Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/BiosCallOuts.c    |  122 ++++++-----------------
 src/mainboard/amd/inagua/BiosCallOuts.h    |    2 +
 src/mainboard/amd/inagua/Kconfig           |   25 +-----
 src/mainboard/amd/inagua/Makefile.inc      |    7 ++
 src/mainboard/amd/inagua/OptionsIds.h      |    6 +-
 src/mainboard/amd/inagua/PlatformGnbPcie.c |   58 ++++++------
 src/mainboard/amd/inagua/acpi/ssdt2.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt3.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt4.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt5.asl    |   85 ----------------
 src/mainboard/amd/inagua/acpi_tables.c     |    7 +-
 src/mainboard/amd/inagua/agesawrapper.c    |    8 +-
 src/mainboard/amd/inagua/agesawrapper.h    |    9 +-
 src/mainboard/amd/inagua/buildOpts.c       |  116 +++++++++++++---------
 src/mainboard/amd/inagua/devicetree.cb     |    8 +-
 src/mainboard/amd/inagua/dimmSpd.c         |   39 ++++----
 src/mainboard/amd/inagua/dsdt.asl          |    9 +-
 src/mainboard/amd/inagua/fadt.c            |    4 +-
 src/mainboard/amd/inagua/get_bus_conf.c    |   23 +---
 src/mainboard/amd/inagua/irq_tables.c      |    3 +-
 src/mainboard/amd/inagua/mainboard.c       |   14 ++-
 src/mainboard/amd/inagua/mptable.c         |  146 ++++++---------------------
 src/mainboard/amd/inagua/platform_cfg.h    |    2 +-
 src/mainboard/amd/inagua/romstage.c        |   23 +++--
 24 files changed, 250 insertions(+), 718 deletions(-)

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index a72f96b..434e83f 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -19,13 +19,12 @@
 
 #include "agesawrapper.h"
 #include "amdlib.h"
+#include "dimmSpd.h"
 #include "BiosCallOuts.h"
-#include "Ids.h"
-#include "OptionsIds.h"
 #include "heapManager.h"
 #include "SB800.h"
 
-STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
   {AGESA_ALLOCATE_BUFFER,
    BiosAllocateBuffer
@@ -55,102 +54,44 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
    BiosRunFuncOnAp
   },
 
-  {AGESA_GET_IDS_INIT_DATA,
-   BiosGetIdsInitData
+	{AGESA_GNB_PCIE_SLOT_RESET,
+	 BiosGnbPcieSlotReset
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT,
+	 BiosHookBeforeDramInit
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+	 BiosHookBeforeDramInitRecovery
   },
 
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
 
-  {AGESA_HOOKBEFORE_DRAM_INIT,
-   BiosHookBeforeDramInit
-  },
   {AGESA_HOOKBEFORE_EXIT_SELF_REF,
    BiosHookBeforeExitSelfRefresh
   },
-  {AGESA_GNB_PCIE_SLOT_RESET,
-   BiosGnbPcieSlotReset
-  },
 };
 
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   UINTN i;
   AGESA_STATUS CalloutStatus;
+	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
 
-  for (i = 0; i < REQUIRED_CALLOUTS; i++)
-  {
-    if (BiosCallouts[i].CalloutName == Func)
-    {
-      break;
-    }
-  }
-
-  if(i >= REQUIRED_CALLOUTS)
-  {
-    return AGESA_UNSUPPORTED;
-  }
+	CalloutStatus = AGESA_UNSUPPORTED;
 
+	for (i = 0; i < CallOutCount; i++) {
+		if (BiosCallouts[i].CalloutName == Func) {
   CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
-
   return CalloutStatus;
-}
-
-
-CONST IDS_NV_ITEM IdsData[] =
-{
-  /*{
-    AGESA_IDS_NV_MAIN_PLL_CON,
-    0x1
-  },
-  {
-    AGESA_IDS_NV_MAIN_PLL_FID_EN,
-    0x1
-  },
-  {
-    AGESA_IDS_NV_MAIN_PLL_FID,
-    0x8
-  },
-
-  {
-    AGESA_IDS_NV_CUSTOM_NB_PSTATE,
-  },
-  {
-    AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
-  },
-  {
-    AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
-  },
-  {
-    AGESA_IDS_NV_FORCE_NB_PSTATE,
-  },
-*/
-  {
-    0xFFFF,
-    0xFFFF
-  }
-};
-
-#define   NUM_IDS_ENTRIES    (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
-
-
-AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
-{
-  UINTN   i;
-  IDS_NV_ITEM *IdsPtr;
-
-  IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
-
-  if (Data == IDS_CALLOUT_INIT) {
-    for (i = 0; i < NUM_IDS_ENTRIES; i++) {
-      IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
-      IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
     }
   }
-  return AGESA_SUCCESS;
-}
 
+	return CalloutStatus;
+}
 
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
@@ -210,7 +151,6 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
-
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -343,7 +283,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* Clear the BufferSize and NextNodeOffset of the previous first node */
       FreedNodePtr->BufferSize = 0;
       FreedNodePtr->NextNodeOffset = 0;
-
     } else {
       /* Otherwise, add freed node to the start of the list
          Update NextNodeOffset and BufferSize to include the
@@ -390,7 +329,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     if (AllocNodeOffset == EndNodeOffset) {
       PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
       PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
-
       AllocNodePtr->BufferSize = 0;
       AllocNodePtr->NextNodeOffset = 0;
     } else {
@@ -438,7 +376,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS        Status;
 
-  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
   return Status;
 }
 
@@ -481,7 +419,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS Status;
-  Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
 
   return Status;
 }
@@ -511,7 +449,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   MemData = ConfigPtr;
 
   Status  = AGESA_SUCCESS;
-  /* Get SB800 MMIO Base (AcpiMmioAddr) */
+	/* Get SB MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Data8   = ReadIo8(0xCD7);
   Data16  = Data8<<8;
@@ -534,12 +472,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
@@ -575,6 +515,13 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   }
   return Status;
 }
+
+/*	Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
@@ -607,8 +554,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   switch (ResetInfo->ResetId)
   {
   case 4:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
         Data8 &= ~(UINT8)BIT6 ;
@@ -624,8 +570,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       }
       break;
   case 6:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
         Data8 &= ~(UINT8)BIT6 ;
@@ -641,8 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       }
       break;
   case 7:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
         Data8 &= ~(UINT8)BIT6 ;
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index 4efe15f..f7124b9 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -64,6 +64,8 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 4bb0d60..b0c5f1a 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -22,8 +22,6 @@ if BOARD_AMD_INAGUA
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_FAMILY14
@@ -81,18 +79,6 @@ config MEM_TRAIN_SEQ
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11
@@ -147,19 +133,10 @@ config VGA_BIOS_ID
         depends on VGA_BIOS
         default "1002,9802"
 
-config AHCI_ROM
+config SB800_AHCI_ROM
         bool
         default n
 
-#config AHCI_ROM_FILE
-#        string "AHCI ROM path and filename"
-#        depends on AHCI_ROM
-#        default "rom/ahci/sb800.bin"
-
-config AHCI_ROM_ID
-        string "AHCI device PCI IDs"
-        depends on AHCI_ROM
-        default "1002,4391"
 
 endif # BOARD_AMD_INAGUA
 
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index d9fc200..8a72727 100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -17,6 +17,13 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+ifeq ($(CONFIG_AHCI_BIOS),y)
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+endif
+
 romstage-y += buildOpts.c
 romstage-y += agesawrapper.c
 romstage-y += dimmSpd.c
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
index eb756df..028d58f 100644
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ b/src/mainboard/amd/inagua/OptionsIds.h
@@ -51,11 +51,9 @@
  **/
 
 #define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
 #define IDSOPT_ASSERT_ENABLED  TRUE
-//#undef IDSOPT_DEBUG_ENABLED
+
 //#define IDSOPT_DEBUG_ENABLED  FALSE
 //#undef IDSOPT_HOST_SIMNOW
 //#define IDSOPT_HOST_SIMNOW    FALSE
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index 4f00071..ea080a5 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -26,6 +26,34 @@
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
+/*---------------------------------------------------------------------------------------*/
+/**
+ *	OemCustomizeInitEarly
+ *
+ *	Description:
+ *	This is the stub function will call the host environment through the binary block
+ *	interface (call-out port) to provide a user hook opportunity
+ *
+ *	Parameters:
+ *	@param[in]		**PeiServices
+ *	@param[in]		*InitEarly
+ *
+ *	@retval		 VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+	IN	OUT AMD_EARLY_PARAMS	*InitEarly
+	)
+{
+	AGESA_STATUS		 Status;
+	VOID				 *BrazosPcieComplexListPtr;
+	VOID				 *BrazosPciePortPtr;
+	VOID				 *BrazosPcieDdiPtr;
+
+	ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
 PCIe_PORT_DESCRIPTOR PortList [] = {
         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
         {
@@ -83,34 +111,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
         &DdiList[0]
 };
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  )
-{
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
-
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
   // GNB PCIe topology Porting
 
   //
@@ -126,7 +126,7 @@ OemCustomizeInitEarly (
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
     ASSERT(FALSE);
-    return Status;
+	return;
   }
 
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
diff --git a/src/mainboard/amd/inagua/acpi/ssdt2.asl b/src/mainboard/amd/inagua/acpi/ssdt2.asl
deleted file mode 100644
index ef1a4bf..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt2.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-		// BUS ? Second HT Chain
-		Name (HCIN, 0xcc)  // HC2 0x01
-
-		Name (_UID,	 0xdd)	// HC 0x03
-
-		Name (_HID, "PNP0A03")
-
-		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-		{
-			Return (DADD(GHCN(HCIN), 0x00000000))
-		}
-
-		Method (_BBN, 0, NotSerialized)
-		{
-			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-		}
-
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (\_SB.GHCE(HCIN))
-		}
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Name (BUF0, ResourceTemplate () { })
-			Store( GHCN(HCIN), Local4)
-			Store( GHCL(HCIN), Local5)
-
-			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-			Return (Local3)
-		}
-
-			#include "acpi/pci2_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt3.asl b/src/mainboard/amd/inagua/acpi/ssdt3.asl
deleted file mode 100644
index 68a4b95..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt3.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci3_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt4.asl b/src/mainboard/amd/inagua/acpi/ssdt4.asl
deleted file mode 100644
index e06fe8a..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt4.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci4_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt5.asl b/src/mainboard/amd/inagua/acpi/ssdt5.asl
deleted file mode 100644
index a141a37..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt5.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-	External (DADD, MethodObj)
-	External (GHCE, MethodObj)
-	External (GHCN, MethodObj)
-	External (GHCL, MethodObj)
-	External (GHCD, MethodObj)
-	External (GNUS, MethodObj)
-	External (GIOR, MethodObj)
-	External (GMEM, MethodObj)
-	External (GWBN, MethodObj)
-	External (GBUS, MethodObj)
-
-	External (PICF)
-
-	External (\_SB.PCI0.LNKA, DeviceObj)
-	External (\_SB.PCI0.LNKB, DeviceObj)
-	External (\_SB.PCI0.LNKC, DeviceObj)
-	External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci5_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 2e6e50f..8ed7d4f 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -245,9 +246,10 @@ unsigned long write_acpi_tables(unsigned long start)
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
+		acpi_add_table(rsdp,ssdt);
 	}
 	else {
-		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
+		printk(BIOS_DEBUG, "  AGESA SSDT Pstate table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 #endif
@@ -275,6 +277,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
+	printk(BIOS_DEBUG, "alib\n");
+	dump_mem(ssdt, ((void *)alib) + alib->length);
+
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index c33d20f..83c68f0 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -57,7 +57,6 @@ VOID *AcpiWheaMce	= NULL;
 VOID *AcpiWheaCmc	= NULL;
 VOID *AcpiAlib		= NULL;
 
-
 /*------------------------------------------------------------------------------
  *				T Y P E D E F S		 A N D		 S T R U C T U R E S
  *------------------------------------------------------------------------------
@@ -190,7 +189,6 @@ agesawrapper_amdinitreset (
 					sizeof (AMD_INTERFACE_PARAMS),
 					&(AmdParamStruct.StdHeader));
 
-
 	LibAmdMemFill (&AmdResetParams,
 					0,
 					sizeof (AMD_RESET_PARAMS),
@@ -485,6 +483,12 @@ agesawrapper_amdinitlate (
 	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
 	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
 	/* Don't release the structure until coreboot has copied the ACPI tables.
 	 * AmdReleaseStruct (&AmdLateParams);
 	 */
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index f6e6dec..f8d924e 100644
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -22,7 +22,6 @@
  *----------------------------------------------------------------------------------------
  */
 
-
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -39,7 +38,6 @@
 #define AMD_APU_SSID    0x1234
 #define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
 
-
 enum {
   PICK_DMI,       /* DMI Interface */
   PICK_PSTATE,    /* Acpi Pstate SSDT Table */
@@ -50,8 +48,6 @@ enum {
   PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
 };
 
-
-
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
  *----------------------------------------------------------------------------------------
@@ -77,15 +73,18 @@ typedef struct {
  *---------------------------------------------------------------------------------------
  */
 
-//void brazos_platform_stage(void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);
 UINT32 agesawrapper_amdinitlate (void);
 UINT32 agesawrapper_amdinitpost (void);
 UINT32 agesawrapper_amdinitmid (void);
+
 UINT32 agesawrapper_amdreadeventlog (void);
+
+UINT32 agesawrapper_amdinitcpuio (void);
 UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 void *agesawrapper_getlateinitptr (int pick);
 
 #endif
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 919f6be..6506c2e 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -33,8 +33,6 @@
  * @e \$Revision: 23714 $   @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
  */
 
-#include "AGESA.h"
-#include "CommonReturns.h"
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
@@ -80,16 +78,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +95,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT						FALSE
+#define BLDOPT_REMOVE_SLIT						FALSE
+#define BLDOPT_REMOVE_WHEA						FALSE
+#define BLDOPT_REMOVE_DMI						TRUE
+#define BLDOPT_REMOVE_HT_ASSIST					TRUE
+#define BLDOPT_REMOVE_ATM_MODE					TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,30 +121,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
-
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
-  { CPU_LIST_TERMINAL }
-};
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES		FALSE
 
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
@@ -201,7 +176,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
 //#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-//#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
+#define BLDCFG_CFG_GNB_HD_AUDIO					TRUE
 //#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
@@ -244,7 +219,33 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 
+/*
+ * Agesa configuration values selection.
+ * Uncomment and specify the value for the configuration options
+ * needed by the system.
+ */
+#include "AGESA.h"
+#include "CommonReturns.h"
+
+/* The fixed MTRR values to be set after memory initialization. */
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ CPU_LIST_TERMINAL }
+};
+
 /*  Include the files that instantiate the configuration definitions.  */
+
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -253,7 +254,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
@@ -271,13 +271,37 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  * version string as appropriate for the release. The trunk copy of this file
  * should also be updated/incremented for the next expected version, + trailing 'X'
  ****************************************************************************/
-                  // This is the delivery package title, "BrazosPI"
-                  // This string MUST be exactly 8 characters long
+// This is the delivery package title, "BrazosPI"
+// This string MUST be exactly 8 characters long
 #define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+// This is the release version number of the AGESA component
+// This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING	{'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY				200 ///< DDR 400
+#define DDR533_FREQUENCY				266 ///< DDR 533
+#define DDR667_FREQUENCY				333 ///< DDR 667
+#define DDR800_FREQUENCY				400 ///< DDR 800
+#define DDR1066_FREQUENCY				533 ///< DDR 1066
+#define DDR1333_FREQUENCY				667 ///< DDR 1333
+#define DDR1600_FREQUENCY				800 ///< DDR 1600
+#define DDR1866_FREQUENCY				933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY		934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED				0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED				1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO				0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED				1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC			2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL			0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT		1 ///< Chip select power down mode
 
 // The following definitions specify the default values for various parameters in which there are
 // no clearly defined defaults to be used in the common file.  The values below are based on product
@@ -373,7 +397,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 #include "mn.h"
 
 //DA Customer table
-UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
+CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
 {
  // Hardcoded Memory Training Values
 
@@ -415,7 +439,7 @@ UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
  // TABLE END
   NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
 };
-UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
+CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
 
 /* ***************************************************************************
  *   Optional User code to be included into the AGESA build
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 32d9a26..62cf32d 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/amd/agesa/family14/root_complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge
+                                        device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
                                         device pci 1.1 on end # Internal Multimedia
                                         device pci 4.0 on end # PCIE P2P bridge 0x9604
                                         device pci 5.0 off end # PCIE P2P bridge 0x9605
@@ -65,14 +65,14 @@ chip northbridge/amd/agesa/family14/root_complex
                                                         end
                                                 end # kbc1100
 					end #LPC
-					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
 					device pci 15.0 on end # PCIe PortA
 					device pci 15.1 on end # PCIe PortB
 					device pci 15.2 on end # PCIe PortC
 					device pci 15.3 on end # PCIe PortD
-					device pci 16.0 off end # OHCI USB3
-					device pci 16.2 off end # EHCI USB3
+					device pci 16.0 on end # OHCI USB3
+					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index d82cb5d..3719112 100644
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -20,6 +20,7 @@
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
+#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
@@ -30,13 +31,12 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 * SPD address table - porting required
 */
 
-#define SMBUS_BASE_ADDR		0xB00
-static const UINT8 spdAddressLookup [1] [2] [1] =  // socket, channel, dimm
+static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
    {
    // socket 0
       {
-         {0xA0},  // channel 0 dimms
-         {0xA2},  // channel 1 dimms
+         {0xA0, 0xA2},  // channel 0 dimms
+         {0x00, 0x00},  // channel 1 dimms
       },
    };
 
@@ -46,7 +46,7 @@ static const UINT8 spdAddressLookup [1] [2] [1] =  // socket, channel, dimm
  */
 
 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
-   {
+{
    unsigned int status;
    UINT64 limit;
 
@@ -60,8 +60,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 
    // time limit to avoid hanging for unexpected error status (should never happen)
    limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
+	for (;;) {
       status = __inbyte (iobase);
       if (__rdtsc () > limit) break;
       if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
@@ -72,7 +71,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    buffer [0] = __inbyte (iobase + 5);
    if (status == 2) status = 0;                      // check for done with no errors
    return status;
-   }
+}
 
 /*-----------------------------------------------------------------------------
  *
@@ -81,7 +80,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
  */
 
 static int readSmbusByte (int iobase, int address, char *buffer)
-   {
+{
    unsigned int status;
    UINT64 limit;
 
@@ -90,8 +89,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
 
    // time limit to avoid hanging for unexpected error status
    limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
+	for (;;) {
       status = __inbyte (iobase);
       if (__rdtsc () > limit) break;
       if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
@@ -102,7 +100,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
    buffer [0] = __inbyte (iobase + 5);
    if (status == 2) status = 0;                      // check for done with no errors
    return status;
-   }
+}
 
 /*---------------------------------------------------------------------------
  *
@@ -114,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  */
 
 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
-   {
+{
    int index, error;
 
    /* read the first byte using offset zero */
@@ -122,14 +120,13 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
    if (error) return error;
 
    /* read the remaining bytes using auto-increment for speed */
-   for (index = 1; index < count; index++)
-      {
+	for (index = 1; index < count; index++) {
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
 
    return 0;
-   }
+}
 
 static void writePmReg (int reg, int data)
    {
@@ -138,16 +135,16 @@ static void writePmReg (int reg, int data)
    }
 
 static void setupFch (int ioBase)
-   {
+{
    writePmReg (0x2D, ioBase >> 8);
    writePmReg (0x2C, ioBase | 1);
    writePmReg (0x29, 0x80);
    writePmReg (0x28, 0x61);
    __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
-   }
+}
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
-   {
+{
    int spdAddress, ioBase;
 
    if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
@@ -156,7 +153,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 
    spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
-   ioBase = SMBUS_BASE_ADDR;
+	ioBase = SMBUS0_BASE_ADDRESS;
    setupFch (ioBase);
    return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
-   }
+}
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
index d7506c9..4a61328 100644
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ b/src/mainboard/amd/inagua/dsdt.asl
@@ -27,7 +27,7 @@ DefinitionBlock (
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */	/* Include global debug methods if needed */
+	/* #include "../../../arch/i386/acpi/debug.asl" */		/* Include global debug methods if needed */
 
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
@@ -36,7 +36,7 @@ DefinitionBlock (
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1379,7 +1379,7 @@ DefinitionBlock (
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
@@ -1483,9 +1483,8 @@ DefinitionBlock (
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
diff --git a/src/mainboard/amd/inagua/fadt.c b/src/mainboard/amd/inagua/fadt.c
index c84edfb..020d011 100644
--- a/src/mainboard/amd/inagua/fadt.c
+++ b/src/mainboard/amd/inagua/fadt.c
@@ -40,9 +40,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
-  memcpy(header->oem_table_id, "AMD     ", 8);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index ab58c99..13d198a 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <cpu/amd/amdfam14.h>
+#include "agesawrapper.h"
 #if CONFIG_AMD_SB_CIMX
 #include <sb_cimx.h>
 #endif
@@ -34,6 +35,7 @@
 */
 u8 bus_isa;
 u8 bus_sb800[3];
+u32 apicid_sb800;
 
 /*
 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@@ -44,27 +46,15 @@ u32 pci1234x[] = {
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
+	u32 apicid_base;
   u32 status;
 
   device_t dev;
@@ -105,7 +95,6 @@ void get_bus_conf(void)
     bus_type[i] = 0; /* default ISA bus. */
   }
 
-
   bus_type[0] = 1;  /* pci */
 
 //  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
@@ -114,8 +103,6 @@ void get_bus_conf(void)
   /* sb800 */
   dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
 
-
-
   if (dev) {
     bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
@@ -133,12 +120,14 @@ void get_bus_conf(void)
       bus_isa++;
     }
   }
+
   for (j = bus_sb800[2]; j < bus_isa; j++)
     bus_type[j] = 1;
 
-
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
+	apicid_base = CONFIG_MAX_CPUS;
+	apicid_sb800 = apicid_base;
 
 #if CONFIG_AMD_SB_CIMX
   sb_Late_Post();
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
index a8ea5aa..28432dd 100644
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ b/src/mainboard/amd/inagua/irq_tables.c
@@ -23,8 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
-//#include <cpu/amd/amdfam10_sysconf.h>
-
+#include <cpu/amd/amdfam14.h>
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index e5025b6..1fd5fae 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -28,7 +28,8 @@
 //#include <southbridge/amd/sb800/sb800.h>
 #include "chip.h"
 
-//#define SMBUS_IO_BASE 0x6000
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
 
 /**
  * TODO
@@ -49,11 +50,12 @@ void set_pcie_dereset(void)
 uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
-* enable the dedicated function in inagua board.
+* enable the dedicated function in INAGUA    board.
 *************************************************/
 static void inagua_enable(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard Inagua Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 	uint32_t sys_mem;
@@ -78,11 +80,11 @@ static void inagua_enable(device_t dev)
 	else {
 	  if (sys_mem >= 0x40000000) {
 		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
-	  }
-	  else {
+		} else {
 		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
 	  }
 	}
+
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
@@ -109,6 +111,6 @@ int add_mainboard_resources(struct lb_memory *mem)
 	return 0;
 }
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD INAGUA Mainboard")
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
 	.enable_dev = inagua_enable,
 };
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 73d946c..0a2096b 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -24,114 +24,55 @@
 #include <arch/io.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
+#include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-#define IO_APIC_ID    CONFIG_MAX_PHYSICAL_CPUS + 1
 extern u8 bus_sb800[2];
 
+extern u32 apicid_sb800;
 
 extern u32 bus_type[256];
 extern u32 sbdn_sb800;
-u32 apicid_sb800;
-
-u8 picr_data[] = {
-  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0A,0x0B,0x05
-};
+
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,
+	[0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
+	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x50] = 0x10,0x11,0x12,0x13
 };
 
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
-{
-  mc->mpc_length += length;
-  mc->mpc_entry_count++;
-}
-static void my_smp_write_bus(struct mp_config_table *mc,
-  unsigned char id, const char *bustype)
-{
-  struct mpc_config_bus *mpc;
-  mpc = smp_next_mpc_entry(mc);
-  memset(mpc, '\0', sizeof(*mpc));
-  mpc->mpc_type = MP_BUS;
-  mpc->mpc_busid = id;
-  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-  smp_add_mpc_entry(mc, sizeof(*mpc));
-}
 static void *smp_write_config_table(void *v)
 {
   struct mp_config_table *mc;
   int bus_isa;
-  int boot_apic_id;
-  unsigned apic_version;
-  unsigned cpu_features;
-  unsigned cpu_feature_flags;
-  struct cpuid_result result;
-  unsigned long cpu_flag;
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
   mptable_init(mc, LAPIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  /*Inagua used dure core cpu with one die */
-  boot_apic_id = lapicid();
-  apic_version = lapic_read(LAPIC_LVR) & 0xff;
-  result = cpuid(1);
-  cpu_features = result.eax;
-  cpu_feature_flags = result.edx;
-  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
-  smp_write_processor(mc,
-      0, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  cpu_flag = MPC_CPU_ENABLED;
-  smp_write_processor(mc,
-      1, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
+	smp_write_processors(mc);
 
   get_bus_conf();
 
-  //mptable_write_buses(mc, NULL, &bus_isa);
-  my_smp_write_bus(mc, 0, "PCI   ");
-  my_smp_write_bus(mc, 1, "PCI   ");
-  bus_isa = 0x02;
-  my_smp_write_bus(mc, bus_isa, "ISA   ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
 
-  device_t dev;
   u32 dword;
   u8 byte;
 
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
-  /* Set IO APIC ID onto IO_APIC_ID */
-  write32 (dword, 0x00);
-  write32 (dword + 0x10, IO_APIC_ID << 24);
-  apicid_sb800 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
-  /* PIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-    outb(byte, 0xC00);
-    outb(picr_data[byte], 0xC01);
-  }
-
-  /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
     outb(intr_data[byte], 0xC01);
@@ -141,55 +82,37 @@ static void *smp_write_config_table(void *v)
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
   smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
-  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb800, 0x0);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb800, 0x1);
-  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb800, 0x2);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb800, 0x3);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb800, 0x4);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb800, 0x11);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb800, 0x6);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb800, 0x7);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb800, 0x8);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb800, 0x9);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb800, 0xa);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb800, 0x13);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb800, 0xc);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb800, 0xd);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb800, 0xe);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb800, 0xf);
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
-#define PCI_INT(bus, dev, int_sign, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
 
   /* APU Internal Graphic Device*/
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
   PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-  /* SMBUS */
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
-  /* Southbridge HD Audio */
-  PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
-
-  /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
   PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
   PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-  PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
 
   /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */
@@ -215,21 +138,18 @@ static void *smp_write_config_table(void *v)
   PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
   PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
-  /* PCIe Lan*/
-  PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-  /* FCH PCIe PortA */
+	/* PCIe PortA */
   PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* FCH PCIe PortB */
+	/* PCIe PortB */
   PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* FCH PCIe PortC */
+	/* PCIe PortC */
   PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* FCH PCIe PortD */
+	/* PCIe PortD */
   PCI_INT(0x0, 0x15, 0x3, 0x13);
 
   /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
   /* There is no extension information... */
 
   /* Compute the checksums */
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index aa7cb5c..87b2893 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			NATIVE_IDE_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index c4e8b15..ad94353 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -25,9 +25,11 @@
 #include <arch/stages.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
+#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/kbc1100/kbc1100_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -35,27 +37,29 @@
 #include "pc80/i8259.c"
 #include "sb_cimx.h"
 #include "SBPLATFORM.h"
-#include <arch/cpu.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-u32 agesawrapper_amdinitmmio (void);
-u32 agesawrapper_amdinitreset (void);
-u32 agesawrapper_amdinitearly (void);
-u32 agesawrapper_amdinitenv (void);
-u32 agesawrapper_amdinitlate (void);
-u32 agesawrapper_amdinitpost (void);
-u32 agesawrapper_amdinitmid (void);
+
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
   u32 val;
 
+	// all cores: allow caching of flash chip code and data
+	// (there are no cache-as-ram reliability concerns with family 14h)
+	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	__writemsr (0xc0010062, 0);
+
   if (!cpu_init_detectedx && boot_cpu()) {
     post_code(0x30);
     sb_Poweron_Init();
 
     post_code(0x31);
-    kbc1100_early_init(CONFIG_SIO_PORT);
+	kbc1100_early_init(CONFIG_SIO_PORT);
+
     console_init();
   }
 
@@ -114,4 +118,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
   post_code(0x54);  // Should never see this post code.
 }
-


From gerrit at coreboot.org  Wed Jan 18 08:36:08 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:08 +0100
Subject: [coreboot] New patch to review for coreboot: b25d3f7 Inagua:
	mainboard specific GPIO setting
References: <I563b2e6354a958a28f5d0162e7a4d60aa437fb9b+0@gerrit.coreboot.org>
Message-ID: <I563b2e6354a958a28f5d0162e7a4d60aa437fb9b+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/543

-gerrit

commit b25d3f7d2c52345353f9c62eb89a0bf333e4b94b
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:10:45 2012 +0800

    Inagua: mainboard specific GPIO setting
    
    Pcie device connected to Hudson/sb800 southbridge GPP training can works,
    by applying this mainbaind specific GPIO PCIE De-Assert setting.
    
    Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/mainboard.c |   28 +++++++++++++++++++++++++++-
 1 files changed, 27 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 1fd5fae..89a3c6b 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -26,6 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 //#include <southbridge/amd/sb800/sb800.h>
+#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "chip.h"
 
 void set_pcie_reset(void);
@@ -40,11 +41,34 @@ void set_pcie_reset(void)
 }
 
 /**
- * TODO
  * mainboard specific SB CIMx callback
  */
 void set_pcie_dereset(void)
 {
+	/**
+	 * GPIO32 Pcie Device DeAssert for APU
+	 * GPIO25 Pcie LAN,       APU GPP2
+	 * GPIO02 MINIPCIE SLOT1, APU GPP3
+	 * GPIO50 Pcie Device DeAssert for Hudson Southbridge
+	 * GPIO05 Express Card,     SB  GPP0
+	 * GPIO26 NEC USB3.0GPPUSB, SB  GPP1
+	 * GPIO00 MINIPCIE SLOT2,   SB  GPP2
+	 * GPIO05 Pcie X1 Slot,     SB  GPP3
+	 */
+
+	/* Multi-function pins switch to GPIO0-35, these pins are shared with
+	 * PCI pins, make sure Husson PCI device is disabled.
+	 */
+	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+
+	/* select IOMux to function1/2, corresponds to GPIO */
+	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
+	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
+
+
+	/* output low */
+	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
+	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
 }
 
 uint64_t uma_memory_base, uma_memory_size;
@@ -95,6 +119,8 @@ static void inagua_enable(device_t dev)
 	uma_memory_base = 0x30000000;	/* 1GB  system memory supported */
 #endif
 
+	/* Inagua mainboard specific setting */
+	set_pcie_dereset();
 }
 
 int add_mainboard_resources(struct lb_memory *mem)


From gerrit at coreboot.org  Wed Jan 18 08:36:09 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:09 +0100
Subject: [coreboot] New patch to review for coreboot: 4beb2a0 Inagua: Inagua
	GNB ddi lanes and pcie lanes config update
References: <I40aaf28119b946b3a6383ceff7c734c9c3fd313e+0@gerrit.coreboot.org>
Message-ID: <I40aaf28119b946b3a6383ceff7c734c9c3fd313e+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/544

-gerrit

commit 4beb2a0432fd76bc6cdfe220ca765d910fdfb70b
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:13:35 2012 +0800

    Inagua: Inagua GNB ddi lanes and pcie lanes config update
    
    DDI lanes configuration update to make LVDS works.
    Pcie lanes configuration update to make MiniPcie slot 1 works.
    
    Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/PlatformGnbPcie.c |   24 ++++++++----------------
 1 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index ea080a5..f758006 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -55,25 +55,19 @@ OemCustomizeInitEarly (
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
 PCIe_PORT_DESCRIPTOR PortList [] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
         {
           0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
         },
-        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
         {
           0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
         },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
         {
           0,
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
@@ -88,19 +82,17 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
         {
           0,   //Descriptor flags
           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
-          {ConnectorTypeDP, Aux1, Hdp1}
+          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
         },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
         {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
-          {ConnectorTypeDP, Aux2, Hdp2}
+          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
         }
 };
 


From gerrit at coreboot.org  Wed Jan 18 08:36:09 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:09 +0100
Subject: [coreboot] New patch to review for coreboot: de69b11 Inagua:
	devicetree.cb update
References: <I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a+0@gerrit.coreboot.org>
Message-ID: <I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/545

-gerrit

commit de69b11dfedbfef2619f02af2ebb408e063f4d8e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:16:10 2012 +0800

    Inagua: devicetree.cb update
    
    Add the slots connection comments to devicetree.cb
    
    Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/devicetree.cb |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 62cf32d..60bb29b 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -30,10 +30,10 @@ chip northbridge/amd/agesa/family14/root_complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
                                         device pci 1.1 on end # Internal Multimedia
-                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
-                                        device pci 5.0 off end # PCIE P2P bridge 0x9605
-                                        device pci 6.0 on end # PCIE P2P bridge 0x9606
-                                        device pci 7.0 off end # PCIE P2P bridge 0x9607
+                                        device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
+                                        device pci 5.0 off end # PCIE P2P bridge MXM lane 1
+                                        device pci 6.0 on end # PCIE P2P bridge  LAN
+                                        device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
                                         device pci 8.0 off end # NB/SB Link P2P bridge
                                 end # agesa northbridge
 
@@ -67,10 +67,10 @@ chip northbridge/amd/agesa/family14/root_complex
 					end #LPC
 					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
+					device pci 15.0 on end # PCIe PortA  Express Card
+					device pci 15.1 on end # PCIe PortB  NEC USB3.0
+					device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
+					device pci 15.3 on end # PCIe PortD  PCIE X1 SLOT
 					device pci 16.0 on end # OHCI USB3
 					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1


From gerrit at coreboot.org  Wed Jan 18 08:36:10 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:10 +0100
Subject: [coreboot] New patch to review for coreboot: b1709fd SB800: add
	debug info
References: <Ie50f6ad44b60982dd52253a759eb4c004e0df001+0@gerrit.coreboot.org>
Message-ID: <Ie50f6ad44b60982dd52253a759eb4c004e0df001+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/546

-gerrit

commit b1709fdd0839d7e840062fcb2354276d0264dce1
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:19:17 2012 +0800

    SB800: add debug info
    
    Print out pcie gpp device training status at BIOS_DEBUG level in
    the SB800 GPP training process.
    
    Change-Id: Ie50f6ad44b60982dd52253a759eb4c004e0df001
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/vendorcode/amd/cimx/sb800/Gpp.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/cimx/sb800/Gpp.c b/src/vendorcode/amd/cimx/sb800/Gpp.c
index 72cb1cd..6b89589 100644
--- a/src/vendorcode/amd/cimx/sb800/Gpp.c
+++ b/src/vendorcode/amd/cimx/sb800/Gpp.c
@@ -396,6 +396,7 @@ CheckGppLinkStatus (
         SbStall (1000);                          // Delay 400us
         abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);
         Data32 = readAlink (abIndex) & 0x3F3F3F3F;
+	printk(BIOS_DEBUG, "SB800 GPP port 0x%x training status=0x%x\n", portId, Data32);
 
         if ( (UINT8) (Data32) == 0x10 ) {
           portCfg->PortDetected = TRUE;


From gerrit at coreboot.org  Wed Jan 18 08:36:10 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Wed, 18 Jan 2012 08:36:10 +0100
Subject: [coreboot] New patch to review for coreboot: bfc1917 Inagua: Indent
	and wihtespace cleanup
References: <Ie574e08f138c88084c8ce06d0d0acc489013e3d7+0@gerrit.coreboot.org>
Message-ID: <Ie574e08f138c88084c8ce06d0d0acc489013e3d7+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/547

-gerrit

commit bfc19175afda9c6b8a0de9ead3bb2e2eb4e3e1e2
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Wed Jan 18 16:23:17 2012 +0800

    Inagua: Indent and wihtespace cleanup
    
    Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/BiosCallOuts.c           |  980 ++++++++++----------
 src/mainboard/amd/inagua/BiosCallOuts.h           |   12 +-
 src/mainboard/amd/inagua/Kconfig                  |  135 ++--
 src/mainboard/amd/inagua/PlatformGnbPcie.c        |  204 +++---
 src/mainboard/amd/inagua/PlatformGnbPcieComplex.h |   15 +-
 src/mainboard/amd/inagua/acpi_tables.c            |    2 +-
 src/mainboard/amd/inagua/agesawrapper.c           |  148 ++--
 src/mainboard/amd/inagua/agesawrapper.h           |   18 +-
 src/mainboard/amd/inagua/buildOpts.c              |  208 +++---
 src/mainboard/amd/inagua/devicetree.cb            |  120 ++--
 src/mainboard/amd/inagua/dimmSpd.c                |  146 ++--
 src/mainboard/amd/inagua/get_bus_conf.c           |  158 ++--
 src/mainboard/amd/inagua/irq_tables.c             |    6 +-
 src/mainboard/amd/inagua/mainboard.c              |   30 +-
 src/mainboard/amd/inagua/mptable.c                |  140 ++--
 src/mainboard/amd/inagua/platform_cfg.h           |    8 +-
 src/mainboard/amd/inagua/romstage.c               |  130 ++--
 17 files changed, 1228 insertions(+), 1232 deletions(-)

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 434e83f..3c38239 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -26,494 +26,494 @@
 
 STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
-  {AGESA_ALLOCATE_BUFFER,
-   BiosAllocateBuffer
-  },
+	{AGESA_ALLOCATE_BUFFER,
+		BiosAllocateBuffer
+	},
 
-  {AGESA_DEALLOCATE_BUFFER,
-   BiosDeallocateBuffer
-  },
+	{AGESA_DEALLOCATE_BUFFER,
+		BiosDeallocateBuffer
+	},
 
-  {AGESA_DO_RESET,
-   BiosReset
-  },
+	{AGESA_DO_RESET,
+		BiosReset
+	},
 
-  {AGESA_LOCATE_BUFFER,
-   BiosLocateBuffer
-  },
+	{AGESA_LOCATE_BUFFER,
+		BiosLocateBuffer
+	},
 
-  {AGESA_READ_SPD,
-   BiosReadSpd
-  },
+	{AGESA_READ_SPD,
+		BiosReadSpd
+	},
 
-  {AGESA_READ_SPD_RECOVERY,
-   BiosDefaultRet
-  },
+	{AGESA_READ_SPD_RECOVERY,
+		BiosDefaultRet
+	},
 
-  {AGESA_RUNFUNC_ONAP,
-   BiosRunFuncOnAp
-  },
+	{AGESA_RUNFUNC_ONAP,
+		BiosRunFuncOnAp
+	},
 
 	{AGESA_GNB_PCIE_SLOT_RESET,
-	 BiosGnbPcieSlotReset
+		BiosGnbPcieSlotReset
 	},
 
 	{AGESA_HOOKBEFORE_DRAM_INIT,
-	 BiosHookBeforeDramInit
+		BiosHookBeforeDramInit
 	},
 
 	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
-	 BiosHookBeforeDramInitRecovery
-  },
+		BiosHookBeforeDramInitRecovery
+	},
 
-  {AGESA_HOOKBEFORE_DQS_TRAINING,
-   BiosHookBeforeDQSTraining
-  },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,
+		BiosHookBeforeDQSTraining
+	},
 
-  {AGESA_HOOKBEFORE_EXIT_SELF_REF,
-   BiosHookBeforeExitSelfRefresh
-  },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,
+		BiosHookBeforeExitSelfRefresh
+	},
 };
 
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINTN i;
-  AGESA_STATUS CalloutStatus;
+	UINTN i;
+	AGESA_STATUS CalloutStatus;
 	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
 
 	CalloutStatus = AGESA_UNSUPPORTED;
 
 	for (i = 0; i < CallOutCount; i++) {
 		if (BiosCallouts[i].CalloutName == Func) {
-  CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
-  return CalloutStatus;
-    }
-  }
+			CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+			return CalloutStatus;
+		}
+	}
 
 	return CalloutStatus;
 }
 
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AvailableHeapSize;
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              CurrNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              BestFitNodeOffset;
-  UINT32              BestFitPrevNodeOffset;
-  UINT32              NextFreeOffset;
-  BIOS_BUFFER_NODE   *CurrNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *BestFitNodePtr;
-  BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
-  BIOS_BUFFER_NODE   *NextFreePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
-  AllocParams->BufferPointer = NULL;
-
-  AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
-    /* First allocation */
-    CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-    CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
-    CurrNodePtr->BufferSize = AllocParams->BufferLength;
-    CurrNodePtr->NextNodeOffset = 0;
-    AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
-
-    /* Update the remaining free space */
-    FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
-    FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-    FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
-    FreedNodePtr->NextNodeOffset = 0;
-
-    /* Update the offsets for Allocated and Freed nodes */
-    BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
-    BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
-  } else {
-    /* Find out whether BufferHandle has been allocated on the heap. */
-    /* If it has, return AGESA_BOUNDS_CHK */
-    CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-
-    while (CurrNodeOffset != 0) {
-      CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-      if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
-        return AGESA_BOUNDS_CHK;
-      }
-      CurrNodeOffset = CurrNodePtr->NextNodeOffset;
-      /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
-       to the end of the allocated nodes list.
-      */
-    }
-    /* Find the node that best fits the requested buffer size */
-    FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-    PrevNodeOffset = FreedNodeOffset;
-    BestFitNodeOffset = 0;
-    BestFitPrevNodeOffset = 0;
-    while (FreedNodeOffset != 0) {
-      FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-      if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        if (BestFitNodeOffset == 0) {
-          /* First node that fits the requested buffer size */
-          BestFitNodeOffset = FreedNodeOffset;
-          BestFitPrevNodeOffset = PrevNodeOffset;
-        } else {
-          /* Find out whether current node is a better fit than the previous nodes */
-          BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-          if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
-            BestFitNodeOffset = FreedNodeOffset;
-            BestFitPrevNodeOffset = PrevNodeOffset;
-          }
-        }
-      }
-      PrevNodeOffset = FreedNodeOffset;
-      FreedNodeOffset = FreedNodePtr->NextNodeOffset;
-    } /* end of while loop */
-
-
-    if (BestFitNodeOffset == 0) {
-      /* If we could not find a node that fits the requested buffer */
-      /* size, return AGESA_BOUNDS_CHK */
-      return AGESA_BOUNDS_CHK;
-    } else {
-      BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-      BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
-
-      /* If BestFitNode is larger than the requested buffer, fragment the node further */
-      if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
-
-        NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
-        NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
-        NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
-      } else {
-        /* Otherwise, next free node is NextNodeOffset of BestFitNode */
-        NextFreeOffset = BestFitNodePtr->NextNodeOffset;
-      }
-
-      /* If BestFitNode is the first buffer in the list, then update
-         StartOfFreedNodes to reflect the new free node
-      */
-      if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
-        BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
-      } else {
-        BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
-      }
-
-      /* Add BestFitNode to the list of Allocated nodes */
-      CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
-      BestFitNodePtr->BufferSize = AllocParams->BufferLength;
-      BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
-      BestFitNodePtr->NextNodeOffset = 0;
-
-      /* Remove BestFitNode from list of Freed nodes */
-      AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
-    }
-  }
-
-  return AGESA_SUCCESS;
+	UINT32              AvailableHeapSize;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              CurrNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              BestFitNodeOffset;
+	UINT32              BestFitPrevNodeOffset;
+	UINT32              NextFreeOffset;
+	BIOS_BUFFER_NODE   *CurrNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *BestFitNodePtr;
+	BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+	BIOS_BUFFER_NODE   *NextFreePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+	AllocParams->BufferPointer = NULL;
+
+	AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+		/* First allocation */
+		CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+		CurrNodePtr->BufferSize = AllocParams->BufferLength;
+		CurrNodePtr->NextNodeOffset = 0;
+		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+		/* Update the remaining free space */
+		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+		FreedNodePtr->NextNodeOffset = 0;
+
+		/* Update the offsets for Allocated and Freed nodes */
+		BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+		BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+	} else {
+		/* Find out whether BufferHandle has been allocated on the heap. */
+		/* If it has, return AGESA_BOUNDS_CHK */
+		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+		while (CurrNodeOffset != 0) {
+			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+				return AGESA_BOUNDS_CHK;
+			}
+			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+			   to the end of the allocated nodes list.
+			   */
+		}
+		/* Find the node that best fits the requested buffer size */
+		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+		PrevNodeOffset = FreedNodeOffset;
+		BestFitNodeOffset = 0;
+		BestFitPrevNodeOffset = 0;
+		while (FreedNodeOffset != 0) {
+			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				if (BestFitNodeOffset == 0) {
+					/* First node that fits the requested buffer size */
+					BestFitNodeOffset = FreedNodeOffset;
+					BestFitPrevNodeOffset = PrevNodeOffset;
+				} else {
+					/* Find out whether current node is a better fit than the previous nodes */
+					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+						BestFitNodeOffset = FreedNodeOffset;
+						BestFitPrevNodeOffset = PrevNodeOffset;
+					}
+				}
+			}
+			PrevNodeOffset = FreedNodeOffset;
+			FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+		} /* end of while loop */
+
+
+		if (BestFitNodeOffset == 0) {
+			/* If we could not find a node that fits the requested buffer */
+			/* size, return AGESA_BOUNDS_CHK */
+			return AGESA_BOUNDS_CHK;
+		} else {
+			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+			/* If BestFitNode is larger than the requested buffer, fragment the node further */
+			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+			} else {
+				/* Otherwise, next free node is NextNodeOffset of BestFitNode */
+				NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+			}
+
+			/* If BestFitNode is the first buffer in the list, then update
+			   StartOfFreedNodes to reflect the new free node
+			   */
+			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+			} else {
+				BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+			}
+
+			/* Add BestFitNode to the list of Allocated nodes */
+			CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+			BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+			BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+			BestFitNodePtr->NextNodeOffset = 0;
+
+			/* Remove BestFitNode from list of Freed nodes */
+			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+		}
+	}
+
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              AllocNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              NextNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              EndNodeOffset;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_BUFFER_NODE   *PrevNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *NextNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
-
-  /* Find target node to deallocate in list of allocated nodes.
-     Return AGESA_BOUNDS_CHK if the BufferHandle is not found
-  */
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  PrevNodeOffset = AllocNodeOffset;
-
-  while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      return AGESA_BOUNDS_CHK;
-    }
-    PrevNodeOffset = AllocNodeOffset;
-    AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-    AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  }
-
-  /* Remove target node from list of allocated nodes */
-  PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-  PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-
-  /* Zero out the buffer, and clear the BufferHandle */
-  LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
-  AllocNodePtr->BufferHandle = 0;
-  AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
-
-  /* Add deallocated node in order to the list of freed nodes */
-  FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-  FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-
-  EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
-
-  if (AllocNodeOffset < FreedNodeOffset) {
-    /* Add to the start of the freed list */
-    if (EndNodeOffset == FreedNodeOffset) {
-      /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
-      AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
-
-      /* Clear the BufferSize and NextNodeOffset of the previous first node */
-      FreedNodePtr->BufferSize = 0;
-      FreedNodePtr->NextNodeOffset = 0;
-    } else {
-      /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the
-         size of BIOS_BUFFER_NODE
-      */
-      AllocNodePtr->NextNodeOffset = FreedNodeOffset;
-    }
-    /* Update StartOfFreedNodes to the new first node */
-    BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
-  } else {
-    /* Traverse list of freed nodes to find where the deallocated node
-       should be place
-    */
-    NextNodeOffset = FreedNodeOffset;
-    NextNodePtr = FreedNodePtr;
-    while (AllocNodeOffset > NextNodeOffset) {
-      PrevNodeOffset = NextNodeOffset;
-      if (NextNodePtr->NextNodeOffset == 0) {
-        break;
-      }
-      NextNodeOffset = NextNodePtr->NextNodeOffset;
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-    }
-
-    /* If deallocated node is adjacent to the next node,
-       concatenate both nodes
-    */
-    if (NextNodeOffset == EndNodeOffset) {
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-      AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
-
-      NextNodePtr->BufferSize = 0;
-      NextNodePtr->NextNodeOffset = 0;
-    } else {
-      /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
-      AllocNodePtr->NextNodeOffset = NextNodeOffset;
-    }
-    /* If deallocated node is adjacent to the previous node,
-       concatenate both nodes
-    */
-    PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-    EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
-    if (AllocNodeOffset == EndNodeOffset) {
-      PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-      PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
-      AllocNodePtr->BufferSize = 0;
-      AllocNodePtr->NextNodeOffset = 0;
-    } else {
-      PrevNodePtr->NextNodeOffset = AllocNodeOffset;
-    }
-  }
-  return AGESA_SUCCESS;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              AllocNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              NextNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              EndNodeOffset;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_BUFFER_NODE   *PrevNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *NextNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	/* Find target node to deallocate in list of allocated nodes.
+	   Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+	   */
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	PrevNodeOffset = AllocNodeOffset;
+
+	while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			return AGESA_BOUNDS_CHK;
+		}
+		PrevNodeOffset = AllocNodeOffset;
+		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	}
+
+	/* Remove target node from list of allocated nodes */
+	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+	/* Zero out the buffer, and clear the BufferHandle */
+	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	AllocNodePtr->BufferHandle = 0;
+	AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+	/* Add deallocated node in order to the list of freed nodes */
+	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+	if (AllocNodeOffset < FreedNodeOffset) {
+		/* Add to the start of the freed list */
+		if (EndNodeOffset == FreedNodeOffset) {
+			/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+			AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+			/* Clear the BufferSize and NextNodeOffset of the previous first node */
+			FreedNodePtr->BufferSize = 0;
+			FreedNodePtr->NextNodeOffset = 0;
+		} else {
+			/* Otherwise, add freed node to the start of the list
+			   Update NextNodeOffset and BufferSize to include the
+			   size of BIOS_BUFFER_NODE
+			   */
+			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+		}
+		/* Update StartOfFreedNodes to the new first node */
+		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+	} else {
+		/* Traverse list of freed nodes to find where the deallocated node
+		   should be place
+		   */
+		NextNodeOffset = FreedNodeOffset;
+		NextNodePtr = FreedNodePtr;
+		while (AllocNodeOffset > NextNodeOffset) {
+			PrevNodeOffset = NextNodeOffset;
+			if (NextNodePtr->NextNodeOffset == 0) {
+				break;
+			}
+			NextNodeOffset = NextNodePtr->NextNodeOffset;
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+		}
+
+		/* If deallocated node is adjacent to the next node,
+		   concatenate both nodes
+		   */
+		if (NextNodeOffset == EndNodeOffset) {
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+			NextNodePtr->BufferSize = 0;
+			NextNodePtr->NextNodeOffset = 0;
+		} else {
+			/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+			AllocNodePtr->NextNodeOffset = NextNodeOffset;
+		}
+		/* If deallocated node is adjacent to the previous node,
+		   concatenate both nodes
+		   */
+		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+		if (AllocNodeOffset == EndNodeOffset) {
+			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+			AllocNodePtr->BufferSize = 0;
+			AllocNodePtr->NextNodeOffset = 0;
+		} else {
+			PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+		}
+	}
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AllocNodeOffset;
-  UINT8               *BiosHeapBaseAddr;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
-
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	UINT32              AllocNodeOffset;
+	UINT8               *BiosHeapBaseAddr;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			AllocParams->BufferPointer = NULL;
+			AllocParams->BufferLength = 0;
+			return AGESA_BOUNDS_CHK;
+		} else {
+			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		}
+	}
+
+	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+	AllocParams->BufferLength = AllocNodePtr->BufferSize;
 
-  while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      AllocParams->BufferPointer = NULL;
-      AllocParams->BufferLength = 0;
-      return AGESA_BOUNDS_CHK;
-    } else {
-      AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-      AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-    }
-  }
-
-  AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
-  AllocParams->BufferLength = AllocNodePtr->BufferSize;
-
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 
 }
 
 AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
+	AGESA_STATUS        Status;
 
 	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
-  return Status;
+	return Status;
 }
 
 AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
-  UINT8                 Value;
-  UINTN               ResetType;
-  AMD_CONFIG_PARAMS   *StdHeader;
-
-  ResetType = Data;
-  StdHeader = ConfigPtr;
-
-  //
-  // Perform the RESET based upon the ResetType. In case of
-  // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
-  // AmdResetManager. During the critical condition, where reset is required
-  // immediately, the reset will be invoked directly by writing 0x04 to port
-  // 0xCF9 (Reset Port).
-  //
-  switch (ResetType) {
-  case WARM_RESET_WHENEVER:
-  case COLD_RESET_WHENEVER:
-    break;
-
-  case WARM_RESET_IMMEDIATELY:
-  case COLD_RESET_IMMEDIATELY:
-      Value = 0x06;
-      LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
-    break;
-
-  default:
-    break;
-  }
-
-  Status = 0;
-  return Status;
+	AGESA_STATUS        Status;
+	UINT8                 Value;
+	UINTN               ResetType;
+	AMD_CONFIG_PARAMS   *StdHeader;
+
+	ResetType = Data;
+	StdHeader = ConfigPtr;
+
+	//
+	// Perform the RESET based upon the ResetType. In case of
+	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+	// AmdResetManager. During the critical condition, where reset is required
+	// immediately, the reset will be invoked directly by writing 0x04 to port
+	// 0xCF9 (Reset Port).
+	//
+	switch (ResetType) {
+		case WARM_RESET_WHENEVER:
+		case COLD_RESET_WHENEVER:
+			break;
+
+		case WARM_RESET_IMMEDIATELY:
+		case COLD_RESET_IMMEDIATELY:
+			Value = 0x06;
+			LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+			break;
+
+		default:
+			break;
+	}
+
+	Status = 0;
+	return Status;
 }
 
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
+	AGESA_STATUS Status;
 	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
 
-  return Status;
+	return Status;
 }
 
 AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_UNSUPPORTED;
+	return AGESA_UNSUPPORTED;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
-
-  FcnData = Data;
-  MemData = ConfigPtr;
-
-  Status  = AGESA_SUCCESS;
+	AGESA_STATUS      Status;
+	UINTN             FcnData;
+	MEM_DATA_STRUCT   *MemData;
+	UINT32            AcpiMmioAddr;
+	UINT32            GpioMmioAddr;
+	UINT8             Data8;
+	UINT16            Data16;
+	UINT8             TempData8;
+
+	FcnData = Data;
+	MemData = ConfigPtr;
+
+	Status  = AGESA_SUCCESS;
 	/* Get SB MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  return Status;
+	WriteIo8 (0xCD6, 0x27);
+	Data8   = ReadIo8(0xCD7);
+	Data16  = Data8<<8;
+	WriteIo8 (0xCD6, 0x26);
+	Data8   = ReadIo8(0xCD7);
+	Data16  |= Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	switch(MemData->ParameterListPtr->DDR3Voltage){
+		case VOLT1_35:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 |= (UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+			break;
+		case VOLT1_25:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+			break;
+		case VOLT1_5:
+		default:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 |= (UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	return Status;
 }
 
 /*	Call the host environment interface to provide a user hook opportunity. */
@@ -525,82 +525,82 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  UINTN                 FcnData;
-  PCIe_SLOT_RESET_INFO  *ResetInfo;
-
-  UINT32  GpioMmioAddr;
-  UINT32  AcpiMmioAddr;
-  UINT8   Data8;
-  UINT16  Data16;
-
-  FcnData   = Data;
-  ResetInfo = ConfigPtr;
-  // Get SB800 MMIO Base (AcpiMmioAddr)
-  WriteIo8(0xCD6, 0x27);
-  Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
-  WriteIo8(0xCD6, 0x26);
-  Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  Status = AGESA_UNSUPPORTED;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  switch (ResetInfo->ResetId)
-  {
-  case 4:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 6:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 7:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  }
-  return  Status;
+	AGESA_STATUS Status;
+	UINTN                 FcnData;
+	PCIe_SLOT_RESET_INFO  *ResetInfo;
+
+	UINT32  GpioMmioAddr;
+	UINT32  AcpiMmioAddr;
+	UINT8   Data8;
+	UINT16  Data16;
+
+	FcnData   = Data;
+	ResetInfo = ConfigPtr;
+	// Get SB800 MMIO Base (AcpiMmioAddr)
+	WriteIo8(0xCD6, 0x27);
+	Data8 = ReadIo8(0xCD7);
+	Data16=Data8<<8;
+	WriteIo8(0xCD6, 0x26);
+	Data8 = ReadIo8(0xCD7);
+	Data16|=Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	Status = AGESA_UNSUPPORTED;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	switch (ResetInfo->ResetId)
+	{
+		case 4:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+		case 6:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+		case 7:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+	}
+	return  Status;
 }
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index f7124b9..e713ac3 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -28,15 +28,15 @@
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 
 typedef struct _BIOS_HEAP_MANAGER {
-  //UINT32 AvailableSize;
-  UINT32 StartOfAllocatedNodes;
-  UINT32 StartOfFreedNodes;
+	//UINT32 AvailableSize;
+	UINT32 StartOfAllocatedNodes;
+	UINT32 StartOfFreedNodes;
 } BIOS_HEAP_MANAGER;
 
 typedef struct _BIOS_BUFFER_NODE {
-  UINT32 BufferHandle;
-  UINT32 BufferSize;
-  UINT32 NextNodeOffset;
+	UINT32 BufferHandle;
+	UINT32 BufferSize;
+	UINT32 NextNodeOffset;
 } BIOS_BUFFER_NODE;
 /*
  * CALLOUTS
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index b0c5f1a..a5920af 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -20,108 +20,108 @@
 if BOARD_AMD_INAGUA
 
 config BOARD_SPECIFIC_OPTIONS # dummy
-        def_bool y
-  select ARCH_X86
-  select CPU_AMD_AGESA_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_SB800
-  select SUPERIO_SMSC_KBC1100
-  select BOARD_HAS_FADT
-        select HAVE_BUS_CONFIG
-        select HAVE_OPTION_TABLE
-        select HAVE_PIRQ_TABLE
-        select HAVE_MP_TABLE
-        select HAVE_MAINBOARD_RESOURCES
-        select HAVE_HARD_RESET
-        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        select LIFT_BSP_APIC_ID
-  select SERIAL_CPU_INIT
-  select AMDMCT
-        select HAVE_ACPI_TABLES
-  select BOARD_ROMSIZE_KB_2048
-  select ENABLE_APIC_EXT_ID
-        select GFXUMA
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_AGESA_FAMILY14
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14
+	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SUPERIO_SMSC_KBC1100
+	select BOARD_HAS_FADT
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_2048
+	select ENABLE_APIC_EXT_ID
+	select GFXUMA
 
 config AMD_AGESA
-        bool
-        default y
+	bool
+	default y
 
 config MAINBOARD_DIR
-        string
-        default amd/inagua
+	string
+	default amd/inagua
 
 config APIC_ID_OFFSET
-        hex
-        default 0x0
+	hex
+	default 0x0
 
 config MAINBOARD_PART_NUMBER
-        string
-        default "Inagua"
+	string
+	default "Inagua"
 
 config HW_MEM_HOLE_SIZEK
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config MAX_CPUS
-        int
-        default 2
+	int
+	default 2
 
 config MAX_PHYSICAL_CPUS
-        int
-        default 1
+	int
+	default 1
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-        bool
-        default n
+	bool
+	default n
 
 config MEM_TRAIN_SEQ
-        int
-        default 2
+	int
+	default 2
 
 config IRQ_SLOT_COUNT
-        int
-        default 11
+	int
+	default 11
 
 config RAMTOP
-        hex
-        default 0x1000000
+	hex
+	default 0x1000000
 
 config HEAP_SIZE
-        hex
-        default 0xc0000
+	hex
+	default 0xc0000
 
 config STACK_SIZE
-        hex
-        default 0x10000
+	hex
+	default 0x10000
 
 config ACPI_SSDTX_NUM
-        int
-        default 0
+	int
+	default 0
 
 config RAMBASE
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config SIO_PORT
-        hex
-        default 0x2e
+	hex
+	default 0x2e
 
 config DRIVERS_PS2_KEYBOARD
-        bool
-        default y
+	bool
+	default y
 
 config WARNINGS_ARE_ERRORS
-        bool
-        default n
+	bool
+	default n
 
 config ONBOARD_VGA_IS_PRIMARY
-        bool
-        default y
+	bool
+	default y
 
 config VGA_BIOS
-        bool
-        default n
+	bool
+	default n
 
 #config VGA_BIOS_FILE
 #        string "VGA BIOS path and filename"
@@ -129,14 +129,13 @@ config VGA_BIOS
 #        default "rom/video/OntarioGenericVBios.bin"
 
 config VGA_BIOS_ID
-        string "VGA device PCI IDs"
-        depends on VGA_BIOS
-        default "1002,9802"
+	string "VGA device PCI IDs"
+	depends on VGA_BIOS
+	default "1002,9802"
 
 config SB800_AHCI_ROM
-        bool
-        default n
-
+	bool
+	default n
 
 endif # BOARD_AMD_INAGUA
 
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index f758006..539ca48 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -44,8 +44,8 @@
 /*---------------------------------------------------------------------------------------*/
 VOID
 OemCustomizeInitEarly (
-	IN	OUT AMD_EARLY_PARAMS	*InitEarly
-	)
+		IN	OUT AMD_EARLY_PARAMS	*InitEarly
+		)
 {
 	AGESA_STATUS		 Status;
 	VOID				 *BrazosPcieComplexListPtr;
@@ -54,105 +54,105 @@ OemCustomizeInitEarly (
 
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
-PCIe_PORT_DESCRIPTOR PortList [] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }
-};
-
-PCIe_DDI_DESCRIPTOR DdiList [] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
-        {
-          0,   //Descriptor flags
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
-        },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
-        }
-};
-
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
-};
-
-  // GNB PCIe topology Porting
-
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
-                                         sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
-
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-  if ( Status!= AGESA_SUCCESS) {
-    // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE);
-	return;
-  }
-
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  LibAmdMemFill (BrazosPcieComplexListPtr,
-                   0,
-                   sizeof (PCIe_COMPLEX_DESCRIPTOR),
-                   &InitEarly->StdHeader);
-
-  LibAmdMemFill (BrazosPciePortPtr,
-                   0,
-                   sizeof (PCIe_PORT_DESCRIPTOR) * 5,
-                   &InitEarly->StdHeader);
-
-  LibAmdMemFill (BrazosPcieDdiPtr,
-                   0,
-                   sizeof (PCIe_DDI_DESCRIPTOR) * 2,
-                   &InitEarly->StdHeader);
-
-  LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
-
-
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
-
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+	PCIe_PORT_DESCRIPTOR PortList [] = {
+		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
+		{
+			0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
+		{
+			0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
+		{
+			0,
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+		}
+	};
+
+	PCIe_DDI_DESCRIPTOR DdiList [] = {
+		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
+		{
+			0,   //Descriptor flags
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+			PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
+		},
+		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+			PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
+		}
+	};
+
+	PCIe_COMPLEX_DESCRIPTOR Brazos = {
+		DESCRIPTOR_TERMINATE_LIST,
+		0,
+		&PortList[0],
+		&DdiList[0]
+	};
+
+	// GNB PCIe topology Porting
+
+	//
+	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	//
+	AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+			sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+			sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
+
+	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+	if ( Status!= AGESA_SUCCESS) {
+		// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+		ASSERT(FALSE);
+		return;
+	}
+
+	BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+	BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
+	BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	LibAmdMemFill (BrazosPcieComplexListPtr,
+			0,
+			sizeof (PCIe_COMPLEX_DESCRIPTOR),
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (BrazosPciePortPtr,
+			0,
+			sizeof (PCIe_PORT_DESCRIPTOR) * 5,
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (BrazosPcieDdiPtr,
+			0,
+			sizeof (PCIe_DDI_DESCRIPTOR) * 2,
+			&InitEarly->StdHeader);
+
+	LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+	LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
+	LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
+
+
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+
+	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+	InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index b51089f..6477892 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -29,7 +29,7 @@
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
@@ -37,7 +37,7 @@
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
@@ -45,7 +45,7 @@
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
@@ -53,7 +53,7 @@
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
@@ -61,12 +61,9 @@
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
-VOID
-OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  );
+VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS    *InitEarly);
 
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 8ed7d4f..8f47591 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	/* Write SB800 IOAPIC, only one */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+			CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 			current, 0, 0, 2, 0);
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index 83c68f0..5315683 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -78,8 +78,8 @@ VOID *AcpiAlib		= NULL;
  */
 UINT32
 agesawrapper_amdinitcpuio (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS				Status;
 	UINT64						MsrReg;
@@ -127,8 +127,8 @@ agesawrapper_amdinitcpuio (
 
 UINT32
 agesawrapper_amdinitmmio (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS				Status;
 	UINT64						MsrReg;
@@ -141,9 +141,9 @@ agesawrapper_amdinitmmio (
 	UINT8						Index;
 
 	/*
-	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	 Address MSR register.
-	*/
+	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	   Address MSR register.
+	   */
 
 	for (Index = 0; Index < 8; Index++) {
 		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
@@ -157,8 +157,8 @@ agesawrapper_amdinitmmio (
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
 	/*
-	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	*/
+	   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	   */
 	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
 	MsrReg = MsrReg | 0x0000400000000000ull;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
@@ -177,22 +177,22 @@ agesawrapper_amdinitmmio (
 
 UINT32
 agesawrapper_amdinitreset (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_RESET_PARAMS AmdResetParams;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	LibAmdMemFill (&AmdResetParams,
-					0,
-					sizeof (AMD_RESET_PARAMS),
-					&(AmdResetParams.StdHeader));
+			0,
+			sizeof (AMD_RESET_PARAMS),
+			&(AmdResetParams.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
 	AmdParamStruct.AllocationMethod = ByHost;
@@ -209,21 +209,21 @@ agesawrapper_amdinitreset (
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	AmdReleaseStruct (&AmdParamStruct);
 	return (UINT32)status;
- }
+}
 
 UINT32
 agesawrapper_amdinitearly (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -245,8 +245,8 @@ agesawrapper_amdinitearly (
 
 UINT32
 agesawrapper_amdinitpost (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	UINT16					i;
@@ -255,9 +255,9 @@ agesawrapper_amdinitpost (
 	BIOS_HEAP_MANAGER		*BiosManagerPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -287,8 +287,8 @@ agesawrapper_amdinitpost (
 
 UINT32
 agesawrapper_amdinitenv (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
@@ -296,9 +296,9 @@ agesawrapper_amdinitenv (
 	UINT32				 PciValue;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -311,7 +311,7 @@ agesawrapper_amdinitenv (
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
-		 Modify D1F0x18
+	 Modify D1F0x18
 	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
@@ -323,8 +323,8 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize GMM Base Address for Legacy Bridge Mode
-	*	Modify B1D5F0x18
-	*/
+	 *	Modify B1D5F0x18
+	 */
 	PciAddress.Address.Bus = 1;
 	PciAddress.Address.Device = 5;
 	PciAddress.Address.Function = 0;
@@ -335,16 +335,16 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize FB Base Address for Legacy Bridge Mode
-	* Modify B1D5F0x10
-	*/
+	 * Modify B1D5F0x10
+	 */
 	PciAddress.Address.Register = 0x10;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x80000000;
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize GMM Base Address for Pcie Mode
-	*	Modify B0D1F0x18
-	*/
+	 *	Modify B0D1F0x18
+	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
 	PciAddress.Address.Function = 0;
@@ -355,16 +355,16 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize FB Base Address for Pcie Mode
-	*	Modify B0D1F0x10
-	*/
+	 *	Modify B0D1F0x10
+	 */
 	PciAddress.Address.Register = 0x10;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x80000000;
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize MMIO Base and Limit Address
-	*	Modify B0D1F0x20
-	*/
+	 *	Modify B0D1F0x20
+	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
 	PciAddress.Address.Function = 0;
@@ -375,8 +375,8 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize MMIO Prefetchable Memory Limit and Base
-	*	Modify B0D1F0x24
-	*/
+	 *	Modify B0D1F0x24
+	 */
 	PciAddress.Address.Register = 0x24;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x8FF18001;
@@ -388,8 +388,8 @@ agesawrapper_amdinitenv (
 
 VOID *
 agesawrapper_getlateinitptr (
-	int pick
-	)
+		int pick
+		)
 {
 	switch (pick) {
 		case PICK_DMI:
@@ -413,8 +413,8 @@ agesawrapper_getlateinitptr (
 
 UINT32
 agesawrapper_amdinitmid (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
@@ -423,9 +423,9 @@ agesawrapper_amdinitmid (
 	agesawrapper_amdinitcpuio ();
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -445,17 +445,17 @@ agesawrapper_amdinitmid (
 
 UINT32
 agesawrapper_amdinitlate (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS Status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-		       0,
-		       sizeof (AMD_INTERFACE_PARAMS),
-		       &(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -484,10 +484,10 @@ agesawrapper_amdinitlate (
 	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
 	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
-		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
-		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
-		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
-		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+			"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+			"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+			__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+			AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
 
 	/* Don't release the structure until coreboot has copied the ACPI tables.
 	 * AmdReleaseStruct (&AmdLateParams);
@@ -498,18 +498,18 @@ agesawrapper_amdinitlate (
 
 UINT32
 agesawrapper_amdlaterunaptask (
-	UINT32 Func,
-	UINT32 Data,
-	VOID *ConfigPtr
-	)
+		UINT32 Func,
+		UINT32 Data,
+		VOID *ConfigPtr
+		)
 {
 	AGESA_STATUS Status;
 	AP_EXE_PARAMS ApExeParams;
 
 	LibAmdMemFill (&ApExeParams,
-				 0,
-				 sizeof (AP_EXE_PARAMS),
-				 &(ApExeParams.StdHeader));
+			0,
+			sizeof (AP_EXE_PARAMS),
+			&(ApExeParams.StdHeader));
 
 	ApExeParams.StdHeader.AltImageBasePtr = 0;
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -530,16 +530,16 @@ agesawrapper_amdlaterunaptask (
 
 UINT32
 agesawrapper_amdreadeventlog (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
 
 	LibAmdMemFill (&AmdEventParams,
-					0,
-					sizeof (EVENT_PARAMS),
-					&(AmdEventParams.StdHeader));
+			0,
+			sizeof (EVENT_PARAMS),
+			&(AmdEventParams.StdHeader));
 
 	AmdEventParams.StdHeader.AltImageBasePtr = 0;
 	AmdEventParams.StdHeader.CalloutPtr = NULL;
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index f8d924e..3e819b7 100644
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -39,13 +39,13 @@
 #define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
 
 enum {
-  PICK_DMI,       /* DMI Interface */
-  PICK_PSTATE,    /* Acpi Pstate SSDT Table */
-  PICK_SRAT,      /* SRAT Table */
-  PICK_SLIT,      /* SLIT Table */
-  PICK_WHEA_MCE,  /* WHEA MCE table */
-  PICK_WHEA_CMC,  /* WHEA CMV table */
-  PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+	PICK_DMI,       /* DMI Interface */
+	PICK_PSTATE,    /* Acpi Pstate SSDT Table */
+	PICK_SRAT,      /* SRAT Table */
+	PICK_SLIT,      /* SLIT Table */
+	PICK_WHEA_MCE,  /* WHEA MCE table */
+	PICK_WHEA_CMC,  /* WHEA CMV table */
+	PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
 };
 
 /*----------------------------------------------------------------------------------------
@@ -54,8 +54,8 @@ enum {
  */
 
 typedef struct {
-  UINT32 CalloutName;
-  AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+	UINT32 CalloutName;
+	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
 } BIOS_CALLOUT_STRUCT;
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 6506c2e..49eb7bf 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -89,12 +89,12 @@
 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
+#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
 #define BLDOPT_REMOVE_SRAT						FALSE
 #define BLDOPT_REMOVE_SLIT						FALSE
 #define BLDOPT_REMOVE_WHEA						FALSE
@@ -329,65 +329,65 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  *  use its default conservative settings.
  */
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-  //
-  // The following macros are supported (use comma to separate macros):
-  //
-  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-  //      AGESA will base on this value to disable unused MemClk to save power.
-  //      Example:
-  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-  //           Bit AM3/S1g3 pin name
-  //           0   M[B,A]_CLK_H/L[0]
-  //           1   M[B,A]_CLK_H/L[1]
-  //           2   M[B,A]_CLK_H/L[2]
-  //           3   M[B,A]_CLK_H/L[3]
-  //           4   M[B,A]_CLK_H/L[4]
-  //           5   M[B,A]_CLK_H/L[5]
-  //           6   M[B,A]_CLK_H/L[6]
-  //           7   M[B,A]_CLK_H/L[7]
-  //      And platform has the following routing:
-  //           CS0   M[B,A]_CLK_H/L[4]
-  //           CS1   M[B,A]_CLK_H/L[2]
-  //           CS2   M[B,A]_CLK_H/L[3]
-  //           CS3   M[B,A]_CLK_H/L[5]
-  //      Then platform can specify the following macro:
-  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-  //
-  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-  //      AGESA will base on this value to tristate unused CKE to save power.
-  //
-  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-  //      AGESA will base on this value to tristate unused ODT pins to save power.
-  //
-  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-  //      AGESA will base on this value to tristate unused Chip select to save power.
-  //
-  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-  //      Specifies the number of DIMM slots per channel.
-  //
-  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-  //      Specifies the number of Chip selects per channel.
-  //
-  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-  //      Specifies the number of channels per socket.
-  //
-  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-  //
-  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-  //
-  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-  //      Byte6Seed, Byte7Seed, ByteEccSeed)
-  //      Specifies the write leveling seed for a channel of a socket.
-  //
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
-  PSO_END
+	//
+	// The following macros are supported (use comma to separate macros):
+	//
+	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+	//      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+	//      AGESA will base on this value to disable unused MemClk to save power.
+	//      Example:
+	//      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+	//           Bit AM3/S1g3 pin name
+	//           0   M[B,A]_CLK_H/L[0]
+	//           1   M[B,A]_CLK_H/L[1]
+	//           2   M[B,A]_CLK_H/L[2]
+	//           3   M[B,A]_CLK_H/L[3]
+	//           4   M[B,A]_CLK_H/L[4]
+	//           5   M[B,A]_CLK_H/L[5]
+	//           6   M[B,A]_CLK_H/L[6]
+	//           7   M[B,A]_CLK_H/L[7]
+	//      And platform has the following routing:
+	//           CS0   M[B,A]_CLK_H/L[4]
+	//           CS1   M[B,A]_CLK_H/L[2]
+	//           CS2   M[B,A]_CLK_H/L[3]
+	//           CS3   M[B,A]_CLK_H/L[5]
+	//      Then platform can specify the following macro:
+	//      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+	//
+	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+	//      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+	//      AGESA will base on this value to tristate unused CKE to save power.
+	//
+	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+	//      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+	//      AGESA will base on this value to tristate unused ODT pins to save power.
+	//
+	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+	//      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+	//      AGESA will base on this value to tristate unused Chip select to save power.
+	//
+	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+	//      Specifies the number of DIMM slots per channel.
+	//
+	// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+	//      Specifies the number of Chip selects per channel.
+	//
+	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+	//      Specifies the number of channels per socket.
+	//
+	// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+	//      Specifies DDR bus speed of channel ChannelID on socket SocketID.
+	//
+	// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+	//      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+	//
+	// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+	//      Byte6Seed, Byte7Seed, ByteEccSeed)
+	//      Specifies the write leveling seed for a channel of a socket.
+	//
+	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+	PSO_END
 };
 
 /*
@@ -399,45 +399,45 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 //DA Customer table
 CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
 {
- // Hardcoded Memory Training Values
-
- // The following macro should be used to override training values for your platform
- //
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
- //
- //   NOTE:
- //   The following training hardcode values are example values that were taken from a tilapia motherboard
- //   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
- //   the table and replace the byte lane values with your own.
- //
- //                                                                               ------------------ BYTE LANES ----------------------
- //                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
- // Write Data Timing
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
-
- // DQS Receiver Enable
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
-
- // Write DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
-
- // Read DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
- //--------------------------------------------------------------------------------------------------------------------------------------------------
- // TABLE END
-  NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+	// Hardcoded Memory Training Values
+
+	// The following macro should be used to override training values for your platform
+	//
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+	//
+	//   NOTE:
+	//   The following training hardcode values are example values that were taken from a tilapia motherboard
+	//   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
+	//   the table and replace the byte lane values with your own.
+	//
+	//                                                                               ------------------ BYTE LANES ----------------------
+	//                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+	// Write Data Timing
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+	// DQS Receiver Enable
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+	// Write DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+	// Read DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+	//--------------------------------------------------------------------------------------------------------------------------------------------------
+	// TABLE END
+	NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
 };
 CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
 
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 60bb29b..100a5cc 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -17,56 +17,56 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 chip northbridge/amd/agesa/family14/root_complex
-        device lapic_cluster 0 on
-                chip cpu/amd/agesa/family14
-                  device lapic 0 on end
-                end
-        end
-        device pci_domain 0 on
-                subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-                                        device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
-                                        device pci 1.1 on end # Internal Multimedia
-                                        device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
-                                        device pci 5.0 off end # PCIE P2P bridge MXM lane 1
-                                        device pci 6.0 on end # PCIE P2P bridge  LAN
-                                        device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
-                                        device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa northbridge
+	device lapic_cluster 0 on
+		chip cpu/amd/agesa/family14
+			device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+		chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+#			device pci 18.0 on #  northbridge
+				chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+					device pci 0.0 on end # Root Complex
+					device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
+					device pci 1.1 on end # Internal Multimedia
+					device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
+					device pci 5.0 off end # PCIE P2P bridge MXM lane 1
+					device pci 6.0 on end # PCIE P2P bridge  LAN
+					device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
+					device pci 8.0 off end # NB/SB Link P2P bridge
+				end # agesa northbridge
 
-                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-                                        device pci 11.0 on end # SATA
-                                        device pci 12.0 on end # USB
-                                        device pci 12.1 on end # USB
-                                        device pci 12.2 on end # USB
-                                        device pci 13.0 on end # USB
-                                        device pci 13.1 on end # USB
-                                        device pci 13.2 on end # USB
-                                        device pci 14.0 on # SM
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end
-                                        end # SM
-                                        device pci 14.1 on end # IDE    0x439c
-                                        device pci 14.2 on end # HDA    0x4383
-                                        device pci 14.3 on # LPC        0x439d
-					        chip superio/smsc/kbc1100
-                                                        device pnp 2e.7 on #  Keyboard
-                                                                io 0x60 = 0x60
-                                                                io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                                irq 0x72 = 12
-                                                        end
-                                                end # kbc1100
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.1 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.1 on end # USB
+					device pci 13.2 on end # USB
+					device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x439d
+						chip superio/smsc/kbc1100
+							device pnp 2e.7 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+						end # kbc1100
 					end #LPC
 					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-	  				device pci 14.5 on end # USB 2
+					device pci 14.5 on end # USB 2
 					device pci 15.0 on end # PCIe PortA  Express Card
 					device pci 15.1 on end # PCIe PortB  NEC USB3.0
 					device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
@@ -74,20 +74,20 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 16.0 on end # OHCI USB3
 					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
-#                       end #  device pci 18.0
+#			end #  device pci 18.0
 # These seem unnecessary
-                        device pci 18.0 on end
-                        #device pci 18.0 on end
-                        device pci 18.1 on end
-                        device pci 18.2 on end
-                        device pci 18.3 on end
-                        device pci 18.4 on end
-                        device pci 18.5 on end
-                        device pci 18.6 on end
-                        device pci 18.7 on end
-                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-        end #pci_domain
+			device pci 18.0 on end
+			#device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+	end #pci_domain
 end #northbridge/amd/agesa/family14/root_complex
 
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index 3719112..7a8e82a 100644
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -26,19 +26,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
 
 /*#pragma optimize ("", off) // for source level debug
-*---------------------------------------------------------------------------
-*
-* SPD address table - porting required
-*/
+ *---------------------------------------------------------------------------
+ *
+ * SPD address table - porting required
+ */
 
 static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
-   {
-   // socket 0
-      {
-         {0xA0, 0xA2},  // channel 0 dimms
-         {0x00, 0x00},  // channel 1 dimms
-      },
-   };
+{
+	// socket 0
+	{
+		{0xA0, 0xA2},  // channel 0 dimms
+		{0x00, 0x00},  // channel 1 dimms
+	},
+};
 
 /*-----------------------------------------------------------------------------
  *
@@ -47,30 +47,30 @@ static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
 
 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 {
-   unsigned int status;
-   UINT64 limit;
+	unsigned int status;
+	UINT64 limit;
 
-   address |= 1; // set read bit
+	address |= 1; // set read bit
 
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 1, 0x1F);                // clear error status
-   __outbyte (iobase + 3, offset);              // offset in eeprom
-   __outbyte (iobase + 4, address);             // slave address and read bit
-   __outbyte (iobase + 2, 0x48);                // read byte command
+	__outbyte (iobase + 0, 0xFF);                // clear error status
+	__outbyte (iobase + 1, 0x1F);                // clear error status
+	__outbyte (iobase + 3, offset);              // offset in eeprom
+	__outbyte (iobase + 4, address);             // slave address and read bit
+	__outbyte (iobase + 2, 0x48);                // read byte command
 
-   // time limit to avoid hanging for unexpected error status (should never happen)
-   limit = __rdtsc () + 2000000000 / 10;
+	// time limit to avoid hanging for unexpected error status (should never happen)
+	limit = __rdtsc () + 2000000000 / 10;
 	for (;;) {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;                      // check for done with no errors
+	return status;
 }
 
 /*-----------------------------------------------------------------------------
@@ -81,25 +81,25 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 
 static int readSmbusByte (int iobase, int address, char *buffer)
 {
-   unsigned int status;
-   UINT64 limit;
+	unsigned int status;
+	UINT64 limit;
 
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 2, 0x44);                // read command
+	__outbyte (iobase + 0, 0xFF);                // clear error status
+	__outbyte (iobase + 2, 0x44);                // read command
 
-   // time limit to avoid hanging for unexpected error status
-   limit = __rdtsc () + 2000000000 / 10;
+	// time limit to avoid hanging for unexpected error status
+	limit = __rdtsc () + 2000000000 / 10;
 	for (;;) {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;                      // check for done with no errors
+	return status;
 }
 
 /*---------------------------------------------------------------------------
@@ -113,47 +113,47 @@ static int readSmbusByte (int iobase, int address, char *buffer)
 
 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
 {
-   int index, error;
+	int index, error;
 
-   /* read the first byte using offset zero */
-   error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
-   if (error) return error;
+	/* read the first byte using offset zero */
+	error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+	if (error) return error;
 
-   /* read the remaining bytes using auto-increment for speed */
+	/* read the remaining bytes using auto-increment for speed */
 	for (index = 1; index < count; index++) {
-      error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
-      if (error) return error;
-      }
+		error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+		if (error) return error;
+	}
 
-   return 0;
+	return 0;
 }
 
 static void writePmReg (int reg, int data)
-   {
-   __outbyte (0xCD6, reg);
-   __outbyte (0xCD7, data);
-   }
+{
+	__outbyte (0xCD6, reg);
+	__outbyte (0xCD7, data);
+}
 
 static void setupFch (int ioBase)
 {
-   writePmReg (0x2D, ioBase >> 8);
-   writePmReg (0x2C, ioBase | 1);
-   writePmReg (0x29, 0x80);
-   writePmReg (0x28, 0x61);
-   __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+	writePmReg (0x2D, ioBase >> 8);
+	writePmReg (0x2C, ioBase | 1);
+	writePmReg (0x29, 0x80);
+	writePmReg (0x28, 0x61);
+	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
 }
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
-   int spdAddress, ioBase;
+	int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
-   if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+	if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+	if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
+	if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
 
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
-   if (spdAddress == 0) return AGESA_ERROR;
+	spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+	if (spdAddress == 0) return AGESA_ERROR;
 	ioBase = SMBUS0_BASE_ADDRESS;
-   setupFch (ioBase);
-   return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+	setupFch (ioBase);
+	return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
 }
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index 13d198a..229477d 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,19 +31,19 @@
 
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
+ * and acpi_tables busnum is default.
+ */
 u8 bus_isa;
 u8 bus_sb800[3];
 u32 apicid_sb800;
 
 /*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
 u32 pci1234x[] = {
-  0x0000ff0,
+	0x0000ff0,
 };
 
 u32 bus_type[256];
@@ -55,81 +55,81 @@ static u32 get_bus_conf_done = 0;
 void get_bus_conf(void)
 {
 	u32 apicid_base;
-  u32 status;
-
-  device_t dev;
-  int i, j;
-
-  if (get_bus_conf_done == 1)
-    return;   /* do it only once */
-
-  get_bus_conf_done = 1;
-
-/*
- * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
- * but functionally within the coreboot model, this is the best place to make the
- * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions.  The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written.  This routine is called at the beginning
- * of each of the write functions called prior to the ACPI write functions, so this
- * becomes the best place for this call.
- */
-  status = agesawrapper_amdinitlate();
-  if(status) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-  }
-
-  sbdn_sb800 = 0;
-
-  for (i = 0; i < 3; i++) {
-    bus_sb800[i] = 0;
-  }
-
-  for (i = 0; i < 256; i++) {
-    bus_type[i] = 0; /* default ISA bus. */
-  }
-
-  bus_type[0] = 1;  /* pci */
-
-//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-  bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
-
-  /* sb800 */
-  dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
-
-  if (dev) {
-    bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-    bus_isa++;
-    for (j = bus_sb800[1]; j < bus_isa; j++)
-      bus_type[j] = 1;
-  }
-
-  for (i = 0; i < 4; i++) {
-    dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
-    if (dev) {
-      bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-      bus_isa++;
-    }
-  }
-
-  for (j = bus_sb800[2]; j < bus_isa; j++)
-    bus_type[j] = 1;
-
-  /* I/O APICs:   APIC ID Version State   Address */
-  bus_isa = 10;
+	u32 status;
+
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;   /* do it only once */
+
+	get_bus_conf_done = 1;
+
+	/*
+	 * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+	 * but functionally within the coreboot model, this is the best place to make the
+	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+	 * after the decision about S3 resume is made, and before the system tables are
+	 * written into RAM.  The routine that is responsible for writing the tables is
+	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * specific entry point between the S3 resume decision point and the call to
+	 * "write_tables", and the next platform specific entry points are the calls to
+	 * the ACPI table write functions.  The first of ose would seem to be the right
+	 * place, but other table write functions, e.g. the PIRQ table write function, are
+	 * called before the ACPI tables are written.  This routine is called at the beginning
+	 * of each of the write functions called prior to the ACPI write functions, so this
+	 * becomes the best place for this call.
+	 */
+	status = agesawrapper_amdinitlate();
+	if(status) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+	}
+
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;  /* pci */
+
+	//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
 	apicid_base = CONFIG_MAX_CPUS;
 	apicid_sb800 = apicid_base;
 
 #if CONFIG_AMD_SB_CIMX
-  sb_Late_Post();
+	sb_Late_Post();
 #endif
 }
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
index 28432dd..de25b48 100644
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ b/src/mainboard/amd/inagua/irq_tables.c
@@ -27,9 +27,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+		u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+		u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+		u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 89a3c6b..17c985d 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -74,8 +74,8 @@ void set_pcie_dereset(void)
 uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
-* enable the dedicated function in INAGUA    board.
-*************************************************/
+ * enable the dedicated function in INAGUA    board.
+ *************************************************/
 static void inagua_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -87,14 +87,14 @@ static void inagua_enable(device_t dev)
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr.lo, msr.hi);
+		(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+		 __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
-	     __func__, msr2.lo, msr2.hi);
+		(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+		 __func__, msr2.lo, msr2.hi);
 
 	/* refer to UMA Size Consideration in Family14h BKDG. */
 	sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
@@ -102,16 +102,16 @@ static void inagua_enable(device_t dev)
 		uma_memory_size = 0x18000000;	/* >= 2G memory, 384M recommended UMA */
 	}
 	else {
-	  if (sys_mem >= 0x40000000) {
-		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
+		if (sys_mem >= 0x40000000) {
+			uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
 		} else {
-		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
-	  }
+			uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
+		}
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
-		    __func__, uma_memory_size, uma_memory_base);
+			__func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
 #else
@@ -127,16 +127,16 @@ int add_mainboard_resources(struct lb_memory *mem)
 {
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
- 	 */
+	 */
 #if (CONFIG_GFXUMA == 1)
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
-		    uma_memory_base, uma_memory_size);
+			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
-			    uma_memory_size);
+			uma_memory_size);
 #endif
 	return 0;
 }
 struct chip_operations mainboard_ops = {
 	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
-	.enable_dev = inagua_enable,
+		.enable_dev = inagua_enable,
 };
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 0a2096b..b339348 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -50,115 +50,115 @@ u8 intr_data[] = {
 
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;
 
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LAPIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
 
 	smp_write_processors(mc);
 
-  get_bus_conf();
+	get_bus_conf();
 
 	mptable_write_buses(mc, NULL, &bus_isa);
 
-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:   APIC ID Version State   Address */
 
-  u32 dword;
-  u8 byte;
+	u32 dword;
+	u8 byte;
 
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword &= 0xFFFFFFF0;
-  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword &= 0xFFFFFFF0;
+	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
 
-    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #if CONFIG_GENERATE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
 	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
 	/* Southbridge HD Audio: */
 	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
 	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-  /* on board NIC & Slot PCIE.  */
-
-  /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
 	/* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
 	/* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
 	/* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
 	/* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
 
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
+	/* There is no extension information... */
 
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 87b2893..2a3342c 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -38,13 +38,13 @@
  */
 #ifndef BIOS_SIZE
 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
-  #define BIOS_SIZE BIOS_SIZE_1M
+#define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
-  #define BIOS_SIZE BIOS_SIZE_2M
+#define BIOS_SIZE BIOS_SIZE_2M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
-  #define BIOS_SIZE BIOS_SIZE_4M
+#define BIOS_SIZE BIOS_SIZE_4M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
-  #define BIOS_SIZE BIOS_SIZE_8M
+#define BIOS_SIZE BIOS_SIZE_8M
 #endif
 #endif
 
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index ad94353..60f2aba 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -43,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-  u32 val;
+	u32 val;
 
 	// all cores: allow caching of flash chip code and data
 	// (there are no cache-as-ram reliability concerns with family 14h)
@@ -53,68 +53,68 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
 	__writemsr (0xc0010062, 0);
 
-  if (!cpu_init_detectedx && boot_cpu()) {
-    post_code(0x30);
-    sb_Poweron_Init();
-
-    post_code(0x31);
-	kbc1100_early_init(CONFIG_SIO_PORT);
-
-    console_init();
-  }
-
-  /* Halt if there was a built in self test failure */
-  post_code(0x34);
-  report_bist_failure(bist);
-
-  // Load MPB
-  val = cpuid_eax(1);
-  printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
-  printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
-  post_code(0x35);
-  val = agesawrapper_amdinitmmio();
-
-  post_code(0x37);
-  val = agesawrapper_amdinitreset();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-  }
-
-  post_code(0x38);
-  printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
-
-  post_code(0x39);
-  val = agesawrapper_amdinitearly ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
-
-  post_code(0x40);
-  val = agesawrapper_amdinitpost ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
-
-  post_code(0x41);
-  val = agesawrapper_amdinitenv ();
-  if(val) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-  }
-  printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
-
-  /* Initialize i8259 pic */
-  post_code(0x41);
-  setup_i8259 ();
-
-  /* Initialize i8254 timers */
-  post_code(0x42);
-  setup_i8254 ();
-
-  post_code(0x50);
-  copy_and_run(0);
-
-  post_code(0x54);  // Should never see this post code.
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x30);
+		sb_Poweron_Init();
+
+		post_code(0x31);
+		kbc1100_early_init(CONFIG_SIO_PORT);
+
+		console_init();
+	}
+
+	/* Halt if there was a built in self test failure */
+	post_code(0x34);
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	post_code(0x35);
+	val = agesawrapper_amdinitmmio();
+
+	post_code(0x37);
+	val = agesawrapper_amdinitreset();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	}
+
+	post_code(0x38);
+	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+
+	post_code(0x39);
+	val = agesawrapper_amdinitearly ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+	post_code(0x40);
+	val = agesawrapper_amdinitpost ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+	post_code(0x41);
+	val = agesawrapper_amdinitenv ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+	/* Initialize i8259 pic */
+	post_code(0x41);
+	setup_i8259 ();
+
+	/* Initialize i8254 timers */
+	post_code(0x42);
+	setup_i8254 ();
+
+	post_code(0x50);
+	copy_and_run(0);
+
+	post_code(0x54);  // Should never see this post code.
 }


From gerrit at coreboot.org  Wed Jan 18 08:43:50 2012
From: gerrit at coreboot.org (Philip Prindeville (philipp@redfish-solutions.com))
Date: Wed, 18 Jan 2012 08:43:50 +0100
Subject: [coreboot] New patch to review for coreboot: 99b78c2 pcengines:
	align VENDOR_ and BOARD_ names for PC engines
References: <I44cf759dd3b2d02c525eb325dc9c5c989f172ac5+0@gerrit.coreboot.org>
Message-ID: <I44cf759dd3b2d02c525eb325dc9c5c989f172ac5+1@gerrit.coreboot.org>

Philip Prindeville (philipp at redfish-solutions.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/548

-gerrit

commit 99b78c2949cb8d61ffb5d2941dcfa7e12405f664
Author: Philip Prindeville <philipp at redfish-solutions.com>
Date:   Wed Jan 18 00:31:50 2012 -0700

    pcengines: align VENDOR_ and BOARD_ names for PC engines
    
    Coming changes to abuild require that VENDOR_ and BOARD_ names have
    common suffixes.
    
    Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5
    Signed-off-by: Philip Prindeville <philipp at redfish-solutions.com>
---
 src/mainboard/Kconfig           |    2 +-
 src/mainboard/pcengines/Kconfig |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 13032a6..cc4e14f 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -90,7 +90,7 @@ config VENDOR_NOKIA
 	bool "Nokia"
 config VENDOR_NVIDIA
 	bool "NVIDIA"
-config VENDOR_PC_ENGINES
+config VENDOR_PCENGINES
 	bool "PC Engines"
 config VENDOR_RCA
 	bool "RCA"
diff --git a/src/mainboard/pcengines/Kconfig b/src/mainboard/pcengines/Kconfig
index d5d7008..6c6646d 100644
--- a/src/mainboard/pcengines/Kconfig
+++ b/src/mainboard/pcengines/Kconfig
@@ -1,4 +1,4 @@
-if VENDOR_PC_ENGINES
+if VENDOR_PCENGINES
 
 choice
 	prompt "Mainboard model"
@@ -17,4 +17,4 @@ config MAINBOARD_VENDOR
 	string
 	default "PC Engines"
 
-endif # VENDOR_PC_ENGINES
+endif # VENDOR_PCENGINES


From Kerry.She at amd.com  Wed Jan 18 08:49:13 2012
From: Kerry.She at amd.com (She, Kerry)
Date: Wed, 18 Jan 2012 15:49:13 +0800
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local><CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
Message-ID: <F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>

Hello Marc and Wolfgang

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of She, Kerry
> Sent: Tuesday, January 17, 2012 4:07 PM
> To: Marc Jones; Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Walfqang,
> 
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> bounces at coreboot.org]
> > On Behalf Of Marc Jones
> > Sent: Tuesday, January 17, 2012 3:23 AM
> > To: Wolfgang Kamp - datakamp
> > Cc: coreboot at coreboot.org
> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> >
> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
> > <wmkamp at datakamp.de> wrote:
> > > Hello,
> > >
> > >
> > >
> > > I found a problem with the PCI enumeration of the PCIe Ports in the
> > > CIMX/SB800 Southbridge for the INAGUA platform.
> > >
> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the function
> > > sb_Before_PCI_Init after
> > >
> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3)
> |
> > 0
> > > are probed in the routine ../devices/pci_device.c function
> > >
> > > pci_probe_dev they are not yet initialized. The probing fails and
> also
> > > devices behind the bridge are not recognized.
> > >
> > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> > >
> > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15 <<3)
> |
> > 0 the
> > > enumeration succeed but coreboot crashes later into nothing. The Sage
> > > Debugger fails.
> > >
> > > I can't imagine why.
> > >
> > >
> > >
> > > Marc have you any idea?
> >
> > This looks like a problem in the sb800 cimx wrapper logic. Cimx
> > doesn't treat the devices separately. it lumps all the configuration
> > and enables together, making the coreboot chipset device enable
> > callback fail to enable the device, so it gets disabled. The sb900
> > wrapper appears to fix this issue with cimx setup in early init. You
> > may want to try porting those changes to the sb800.
> >
> > I don't know why it fails later, but I assume it is due to the missing
> > config since you moved the call earlier in the process. You could try
> > calling it multiple times. I'm not sure how it handles that, though.
> >
> > Kerry,
> > Do you have any comments?
> If the enumeration fail, I suggest you should check the PCIE deassert
> GPIO setting.
> Thanks

I found the recent amd/inagua code in the git tree is not boot on my platform and more.
I made an update to make my platform works now.
The missing mainboard specific GPIO setting also added back,
So the sb800 GPP enumeration works now.

Please reference following link and the attachment.
http://review.coreboot.org/#change,542
http://review.coreboot.org/#change,543
http://review.coreboot.org/#change,544
http://review.coreboot.org/#change,545
http://review.coreboot.org/#change,546

Thanks
Kerry  
 
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From gerrit at coreboot.org  Wed Jan 18 10:17:57 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 18 Jan 2012 10:17:57 +0100
Subject: [coreboot] New patch to review for coreboot: 585291e Unify
	ID_SECTION_OFFSET and mark it deprecated
References: <I6ce2d6e94e57717939bda070bfe0c9df80ca2a89+0@gerrit.coreboot.org>
Message-ID: <I6ce2d6e94e57717939bda070bfe0c9df80ca2a89+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/549

-gerrit

commit 585291e3659b86478f3054e240600a4a5d3fd443
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Wed Jan 18 09:43:52 2012 +0100

    Unify ID_SECTION_OFFSET and mark it deprecated
    
    We used to put the id section at -0x10, with some boards overriding
    this to avoid collisions with romstraps.
    Hardcode the location at -0x80, at the possible expense of some space
    (0x70 bytes).
    This also makes the section easier to find in a binary image.
    
    At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
    is moved to src/Kconfig.deprecated_options.
    
    Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/Kconfig                                       |    4 ----
 src/Kconfig.deprecated_options                    |    4 ++++
 src/mainboard/amd/serengeti_cheetah_fam10/Kconfig |    4 ----
 src/mainboard/msi/ms9652_fam10/Kconfig            |    4 ----
 src/southbridge/nvidia/ck804/Kconfig              |    4 ----
 src/southbridge/nvidia/mcp55/Kconfig              |    4 ----
 src/southbridge/sis/sis966/Kconfig                |    4 ----
 src/southbridge/via/k8t890/Kconfig                |    4 ----
 8 files changed, 4 insertions(+), 28 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 525d452..64c359e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -883,10 +883,6 @@ config WARNINGS_ARE_ERRORS
 	bool
 	default y
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x10
-
 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
 # mutually exclusive. One of these options must be selected in the
diff --git a/src/Kconfig.deprecated_options b/src/Kconfig.deprecated_options
index d83525e..3cfb5dd 100644
--- a/src/Kconfig.deprecated_options
+++ b/src/Kconfig.deprecated_options
@@ -61,4 +61,8 @@ config PCIE_TUNING
 	  This variable enables certain PCIe optimizations. Right now it's
 	  only ASPM and it's untested.
 
+config ID_SECTION_OFFSET
+	hex
+	default 0x80
+
 endmenu
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
index 0fc857b..feecdec 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
@@ -87,8 +87,4 @@ config RAMBASE
 	hex
 	default 0x200000
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80
-
 endif # BOARD_AMD_SERENGETI_CHEETAH_FAM10
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index 71568d7..17f0502 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -170,10 +170,6 @@ config AMD_UCODE_PATCH_FILE
 	string
 	default "mc_patch_01000096.h"
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80
-
 config HT3_SUPPORT
 	bool
 	default y
diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig
index 88ab7ff..97927d7 100644
--- a/src/southbridge/nvidia/ck804/Kconfig
+++ b/src/southbridge/nvidia/ck804/Kconfig
@@ -10,10 +10,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/nvidia/ck804/bootblock.c"
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80
-
 config EHCI_BAR
 	hex
 	default 0xfef00000
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index adca4bd..fc355cb 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -9,10 +9,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/nvidia/mcp55/bootblock.c"
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80
-
 config EHCI_BAR
 	hex
 	default 0xfef00000
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index 909a741..3cee5b3 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -7,10 +7,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 	default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80 if SOUTHBRIDGE_SIS_SIS966
-
 config EHCI_BAR
 	hex
 	default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966
diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig
index 94b62b0..b23b84a 100644
--- a/src/southbridge/via/k8t890/Kconfig
+++ b/src/southbridge/via/k8t890/Kconfig
@@ -50,7 +50,3 @@ config VIDEO_MB
 	default -1  if K8M890_VIDEO_MB_CMOS
 	depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN
 
-config ID_SECTION_OFFSET
-	hex
-	default 0x80 if SOUTHBRIDGE_VIA_K8M800 || SOUTHBRIDGE_VIA_K8T800_OLD || SOUTHBRIDGE_VIA_K8T800 || SOUTHBRIDGE_VIA_K8T800PRO || SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890
-


From gerrit at coreboot.org  Wed Jan 18 10:17:58 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 18 Jan 2012 10:17:58 +0100
Subject: [coreboot] Patch set updated for coreboot: fd8418f Add coreboot
	version to id area
References: <I325491a0c42911d9d6ecd59e21ee1b756c987693+0@gerrit.coreboot.org>
Message-ID: <I325491a0c42911d9d6ecd59e21ee1b756c987693+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/537

-gerrit

commit fd8418ff2850ac95024bd800f78e00d0efa99811
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jan 17 13:13:59 2012 +0100

    Add coreboot version to id area
    
    There was no good way to extract the build version from an image.
    
    This change will be mostly backward compatible: The only assumption
    that could break is that the board name string ends directly before
    the 3 dwords that represent .id's "header".
    
    Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 src/arch/x86/Makefile.inc |   12 ++++++------
 src/arch/x86/lib/id.inc   |    3 +++
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 7bba44e..54f0f82 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -321,15 +321,15 @@ $(obj)/bootblock/ldscript.ld: $$(bootblock_lds) $(obj)/ldoptions
 $(obj)/bootblock/bootblock.S: $$(bootblock_inc)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	mkdir -p $(obj)/bootblock
-	printf '$(foreach crt0,config.h $(bootblock_inc),#include "$(crt0)"\n)' > $@
+	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.o: $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
+$(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S $(obj)/config.h $(obj)/build.h
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
@@ -371,15 +371,15 @@ $(obj)/romstage/ldscript.ld: $$(ldscripts) $(obj)/ldoptions
 $(obj)/romstage/crt0.S: $$(crt0s)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	mkdir -p $(obj)/romstage
-	printf '$(foreach crt0,config.h $(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
+	printf '$(foreach crt0,$(crt0s),#include "$(crt0:$(obj)/%=%)"\n)' > $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/crt0.romstage.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
 
-$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S $(obj)/config.h $(obj)/build.h
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $< -o $@
 
 seabios:
 	$(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \
diff --git a/src/arch/x86/lib/id.inc b/src/arch/x86/lib/id.inc
index 443dbad..f8aba0b 100644
--- a/src/arch/x86/lib/id.inc
+++ b/src/arch/x86/lib/id.inc
@@ -2,10 +2,13 @@
 
 	.globl __id_start
 __id_start:
+ver:
+	.asciz COREBOOT_VERSION
 vendor:
 	.asciz CONFIG_MAINBOARD_VENDOR
 part:
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
+.long __id_end + CONFIG_ID_SECTION_OFFSET - ver  /* Reverse offset to the vendor id */
 .long __id_end + CONFIG_ID_SECTION_OFFSET - vendor  /* Reverse offset to the vendor id */
 .long __id_end + CONFIG_ID_SECTION_OFFSET - part    /* Reverse offset to the part number */
 .long CONFIG_ROM_SIZE                               /* Size of this romimage */


From kim.callis at gmail.com  Wed Jan 18 10:48:34 2012
From: kim.callis at gmail.com (Kim C. Callis)
Date: Wed, 18 Jan 2012 04:48:34 -0500
Subject: [coreboot] Finding motherboard specs
Message-ID: <CABVoSWq+0Jmkpb_40pCkx5XBfF1PwBZN-1aPYGM7yjFFri9qJA@mail.gmail.com>

A couple of days ago, I ended up with an old Sony PCV44G desktop system.
Once upon a time, it was used as a Windows MCE machine, but that was long
time ago. I wanted to throw a thumb drive on it and have it boot to
something else. Of course, the crap AMI bios, doesn't allow for booting off
of USB devices. Is there a way to check under knoppix the specs on the
motherboard to see if this machine is a viable candidate for coreboot
replacement?
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From peter at stuge.se  Wed Jan 18 11:20:46 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 18 Jan 2012 11:20:46 +0100
Subject: [coreboot] Finding motherboard specs
In-Reply-To: <CABVoSWq+0Jmkpb_40pCkx5XBfF1PwBZN-1aPYGM7yjFFri9qJA@mail.gmail.com>
References: <CABVoSWq+0Jmkpb_40pCkx5XBfF1PwBZN-1aPYGM7yjFFri9qJA@mail.gmail.com>
Message-ID: <20120118102046.14443.qmail@stuge.se>

Kim C. Callis wrote:
> Is there a way to check under knoppix the specs on the motherboard
> to see if this machine is a viable candidate for coreboot
> replacement?

Start with lspci


//Peter


From gerrit at coreboot.org  Wed Jan 18 11:21:41 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 11:21:41 +0100
Subject: [coreboot] Patch merged into coreboot/master: 585291e Unify
	ID_SECTION_OFFSET and mark it deprecated
References: <I6ce2d6e94e57717939bda070bfe0c9df80ca2a89+0@gerrit.coreboot.org>
Message-ID: <E1RnSeD-0002td-Ff@ra.coresystems.de>

the following patch was just integrated into master:
commit 585291e3659b86478f3054e240600a4a5d3fd443
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Wed Jan 18 09:43:52 2012 +0100

    Unify ID_SECTION_OFFSET and mark it deprecated
    
    We used to put the id section at -0x10, with some boards overriding
    this to avoid collisions with romstraps.
    Hardcode the location at -0x80, at the possible expense of some space
    (0x70 bytes).
    This also makes the section easier to find in a binary image.
    
    At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
    is moved to src/Kconfig.deprecated_options.
    
    Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 10:32:51 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Jan 18 11:21:39 2012, giving +2
See http://review.coreboot.org/549 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 11:22:07 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 11:22:07 +0100
Subject: [coreboot] Patch merged into coreboot/master: fd8418f Add coreboot
	version to id area
References: <I325491a0c42911d9d6ecd59e21ee1b756c987693+0@gerrit.coreboot.org>
Message-ID: <E1RnSed-00032h-JM@ra.coresystems.de>

the following patch was just integrated into master:
commit fd8418ff2850ac95024bd800f78e00d0efa99811
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jan 17 13:13:59 2012 +0100

    Add coreboot version to id area
    
    There was no good way to extract the build version from an image.
    
    This change will be mostly backward compatible: The only assumption
    that could break is that the board name string ends directly before
    the 3 dwords that represent .id's "header".
    
    Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 10:44:34 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Jan 18 10:30:16 2012, giving +2
See http://review.coreboot.org/537 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 13:33:18 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 18 Jan 2012 13:33:18 +0100
Subject: [coreboot] New patch to review for coreboot: 7c8cf66 libpayload:
	Allow using CBFS functions on images in RAM
References: <I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6+0@gerrit.coreboot.org>
Message-ID: <I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/550

-gerrit

commit 7c8cf667e1f1eb785d6bcf1a94b346c1a5cc00d5
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Tue Jan 17 15:52:05 2012 +0100

    libpayload: Allow using CBFS functions on images in RAM
    
    Two new functions allow switching the CBFS functions from using RAM
    or ROM, with ROM as default.
    
    Change-Id: I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/include/cbfs.h |    2 ++
 payloads/libpayload/libcbfs/cbfs.c |   31 +++++++++++++++++++++++++++----
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h
index 681caeb..8b8b024 100644
--- a/payloads/libpayload/include/cbfs.h
+++ b/payloads/libpayload/include/cbfs.h
@@ -1,2 +1,4 @@
 #include <arch/types.h>
 #include "cbfs_core.h"
+void setup_cbfs_from_ram(void* start, uint32_t size);
+void setup_cbfs_from_flash(void);
diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
index c7173e0..7da2d58 100644
--- a/payloads/libpayload/libcbfs/cbfs.c
+++ b/payloads/libpayload/libcbfs/cbfs.c
@@ -40,18 +40,18 @@
 #define ERROR(x...) printf(x)
 #define LOG(x...)
 
-uint32_t host_virt_to_phys(void *addr);
-void *host_phys_to_virt(uint32_t addr);
+static uint32_t host_virt_to_phys(void *addr);
+static void *host_phys_to_virt(uint32_t addr);
 
 uint32_t romstart(void);
 uint32_t romend(void);
 
 #include <arch/virtual.h>
-uint32_t host_virt_to_phys(void *addr) {
+static uint32_t host_virt_to_phys(void *addr) {
 	return virt_to_phys(addr);
 }
 
-void *host_phys_to_virt(uint32_t addr) {
+static void *host_phys_to_virt(uint32_t addr) {
 	return phys_to_virt(addr);
 }
 #undef virt_to_phys
@@ -76,3 +76,26 @@ uint32_t romend(void)
 
 #include "cbfs_core.c"
 
+static uint32_t ram_cbfs_offset;
+
+static uint32_t ram_virt_to_phys(void *addr) {
+	return (uint32_t)addr - ram_cbfs_offset;
+}
+
+static void *ram_phys_to_virt(uint32_t addr) {
+	return (void*)addr + ram_cbfs_offset;
+}
+
+void setup_cbfs_from_ram(void* start, uint32_t size)
+{
+	/* assumes rollover */
+	ram_cbfs_offset = (uint32_t)start + size;
+	virt_to_phys = ram_virt_to_phys;
+	phys_to_virt = ram_phys_to_virt;
+}
+
+void setup_cbfs_from_flash()
+{
+	virt_to_phys = host_virt_to_phys;
+	phys_to_virt = host_phys_to_virt;
+}


From gerrit at coreboot.org  Wed Jan 18 13:33:44 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 18 Jan 2012 13:33:44 +0100
Subject: [coreboot] New patch to review for coreboot: 5d901c1 libpayload:
	style: compare null-pointers with NULL, not 0
References: <I5efbfb75e2894bc8d8e50c8737cfee9738d15eda+0@gerrit.coreboot.org>
Message-ID: <I5efbfb75e2894bc8d8e50c8737cfee9738d15eda+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/551

-gerrit

commit 5d901c1f09cbf1c7b633c96bdcd6d654581bcfbf
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Nov 18 11:56:38 2011 +0100

    libpayload: style: compare null-pointers with NULL, not 0
    
    Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 payloads/libpayload/drivers/usb/usb.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c
index 995b4c2..1f21e6a 100644
--- a/payloads/libpayload/drivers/usb/usb.c
+++ b/payloads/libpayload/drivers/usb/usb.c
@@ -76,7 +76,7 @@ usb_exit (void)
 	if (usb_hcs == 0)
 		return 0;
 	hci_t *controller = usb_hcs;
-	while (controller != 0) {
+	while (controller != NULL) {
 		controller->shutdown(controller);
 		controller = controller->next;
 	}
@@ -92,7 +92,7 @@ usb_poll (void)
 	if (usb_hcs == 0)
 		return;
 	hci_t *controller = usb_hcs;
-	while (controller != 0) {
+	while (controller != NULL) {
 		int i;
 		for (i = 0; i < 128; i++) {
 			if (controller->devices[i] != 0) {


From gerrit at coreboot.org  Wed Jan 18 14:00:06 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 14:00:06 +0100
Subject: [coreboot] Patch merged into coreboot/master: 5d901c1 libpayload:
	style: compare null-pointers with NULL, not 0
References: <I5efbfb75e2894bc8d8e50c8737cfee9738d15eda+0@gerrit.coreboot.org>
Message-ID: <E1RnV7W-0000vK-E8@ra.coresystems.de>

the following patch was just integrated into master:
commit 5d901c1f09cbf1c7b633c96bdcd6d654581bcfbf
Author: Patrick Georgi <patrick.georgi at secunet.com>
Date:   Fri Nov 18 11:56:38 2011 +0100

    libpayload: style: compare null-pointers with NULL, not 0
    
    Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 13:55:15 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Wed Jan 18 14:00:04 2012, giving +2
See http://review.coreboot.org/551 for details.

-gerrit


From paulepanter at users.sourceforge.net  Wed Jan 18 14:13:20 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 18 Jan 2012 14:13:20 +0100
Subject: [coreboot] Finding motherboard specs
In-Reply-To: <20120118102046.14443.qmail@stuge.se>
References: <CABVoSWq+0Jmkpb_40pCkx5XBfF1PwBZN-1aPYGM7yjFFri9qJA@mail.gmail.com>
	<20120118102046.14443.qmail@stuge.se>
Message-ID: <1326892400.29125.83.camel@mattotaupa>

Am Mittwoch, den 18.01.2012, 11:20 +0100 schrieb Peter Stuge:
> Kim C. Callis wrote:
> > Is there a way to check under knoppix the specs on the motherboard
> > to see if this machine is a viable candidate for coreboot
> > replacement?
> 
> Start with lspci

And reading the FAQ [1] is always a good idea too.


Thanks,

Paul


[1] http://www.coreboot.org/FAQ
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From paulepanter at users.sourceforge.net  Wed Jan 18 15:29:11 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 18 Jan 2012 15:29:11 +0100
Subject: [coreboot] ASRock 775i65G (Intel 865g): log files
Message-ID: <1326896951.29125.94.camel@mattotaupa>

Dear coreboot folks,


I got the ASRock 775i65G [1] which has an Intel 865 chipset which is not
yet supported by coreboot. Idwer is trying to port coreboot to the 856
chipset though and as a possible target and for the archive, here are
the log files.

For the record, this board seems to have problems so that the MOSFET ()
on the one corner looks burned [2]. In contrast to the person from the
forum post [2] my board still boots. The MOSFET on my board has the part
number APM038N WI7DS and the board in the forum APM2030N WI8BW. Peter
wrote it would be possible to replace it. Proper MOSFET can be bought at
Ebay [3][4].


Thanks,

Paul


[1] http://www.asrock.com/MB/overview.asp?Model=775i65G
[2] http://forums.ncix.com/forums/topic.php?id=2371121
[3] http://www.ebay.de/itm/270747024710
[4] http://www.ebay.de/itm/250708848592
-------------- next part --------------
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 15
model		: 4
model name	: Intel(R) Pentium(R) 4 CPU 3.00GHz
stepping	: 9
cpu MHz		: 2999.275
cache size	: 1024 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 1
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 5
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc pebs bts nopl pni dtes64 monitor ds_cpl cid cx16 xtpr lahf_lm
bogomips	: 5998.55
clflush size	: 64
cache_alignment	: 128
address sizes	: 36 bits physical, 48 bits virtual
power management:

processor	: 1
vendor_id	: GenuineIntel
cpu family	: 15
model		: 4
model name	: Intel(R) Pentium(R) 4 CPU 3.00GHz
stepping	: 9
cpu MHz		: 2999.275
cache size	: 1024 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 1
apicid		: 1
initial apicid	: 1
fpu		: yes
fpu_exception	: yes
cpuid level	: 5
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc pebs bts nopl pni dtes64 monitor ds_cpl cid cx16 xtpr lahf_lm
bogomips	: 5999.73
clflush size	: 64
cache_alignment	: 128
address sizes	: 36 bits physical, 48 bits virtual
power management:

-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.1.0-3-grml-amd64 (Debian 3.1.0-3+grml.1) (ch at grml.org) (gcc version 4.6.2 (Debian 4.6.2-9) ) #1 SMP Wed Dec 21 23:56:26 UTC 2011
[    0.000000] Command line: initrd=/boot/grml64/initrd.img boot=live live-media-path=/live/grml64/ bootid=grml64201112 apm=power-off vga=791 nomce toram=grml64.squashfs ssh BOOT_IMAGE=/boot/grml64/vmlinuz 
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
[    0.000000]  BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000e4000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000007f740000 (usable)
[    0.000000]  BIOS-e820: 000000007f740000 - 000000007f750000 (ACPI data)
[    0.000000]  BIOS-e820: 000000007f750000 - 000000007f800000 (ACPI NVS)
[    0.000000]  BIOS-e820: 00000000fed00000 - 00000000fed00400 (reserved)
[    0.000000]  BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
[    0.000000]  BIOS-e820: 00000000ff380000 - 0000000100000000 (reserved)
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] DMI present.
[    0.000000] DMI: To Be Filled By O.E.M. To Be Filled By O.E.M./775i65G., BIOS P2.70 09/05/2006
[    0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
[    0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
[    0.000000] No AGP bridge found
[    0.000000] last_pfn = 0x7f740 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-DFFFF uncachable
[    0.000000]   E0000-EFFFF write-through
[    0.000000]   F0000-FFFFF write-protect
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 000000000 mask F80000000 write-back
[    0.000000]   1 base 07F800000 mask FFF800000 uncachable
[    0.000000]   2 disabled
[    0.000000]   3 disabled
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] initial memory mapped : 0 - 20000000
[    0.000000] Base memory trampoline at [ffff88000009a000] 9a000 size 20480
[    0.000000] init_memory_mapping: 0000000000000000-000000007f740000
[    0.000000]  0000000000 - 007f600000 page 2M
[    0.000000]  007f600000 - 007f740000 page 4k
[    0.000000] kernel direct mapping tables up to 7f740000 @ 1fffc000-20000000
[    0.000000] RAMDISK: 7ed05000 - 7f71e000
[    0.000000] ACPI: RSDP 00000000000fa6d0 00014 (v00 ACPIAM)
[    0.000000] ACPI: RSDT 000000007f740000 00030 (v01 A M I  OEMRSDT  09000605 MSFT 00000097)
[    0.000000] ACPI: FACP 000000007f740200 00081 (v02 A M I  OEMFACP  09000605 MSFT 00000097)
[    0.000000] ACPI: DSDT 000000007f740370 03916 (v01  75i6G 75i6G263 00000263 INTL 02002026)
[    0.000000] ACPI: FACS 000000007f750000 00040
[    0.000000] ACPI: APIC 000000007f740300 0006C (v01 A M I  OEMAPIC  09000605 MSFT 00000097)
[    0.000000] ACPI: OEMB 000000007f750040 0003F (v01 A M I  OEMBIOS  09000605 MSFT 00000097)
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] No NUMA configuration found
[    0.000000] Faking a node at 0000000000000000-000000007f740000
[    0.000000] Initmem setup node 0 0000000000000000-000000007f740000
[    0.000000]   NODE_DATA [000000007f73b000 - 000000007f73ffff]
[    0.000000]  [ffffea0000000000-ffffea0001bfffff] PMD -> [ffff88007c400000-ffff88007dffffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000010 -> 0x00001000
[    0.000000]   DMA32    0x00001000 -> 0x00100000
[    0.000000]   Normal   empty
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[2] active PFN ranges
[    0.000000]     0: 0x00000010 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x0007f740
[    0.000000] On node 0 totalpages: 521935
[    0.000000]   DMA zone: 56 pages used for memmap
[    0.000000]   DMA zone: 5 pages reserved
[    0.000000]   DMA zone: 3922 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 7082 pages used for memmap
[    0.000000]   DMA32 zone: 510870 pages, LIFO batch:31
[    0.000000] ACPI: PM-Timer IO Port: 0x808
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x82] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x83] disabled)
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] SMP: Allowing 4 CPUs, 2 hotplug CPUs
[    0.000000] nr_irqs_gsi: 40
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000e4000
[    0.000000] PM: Registered nosave memory: 00000000000e4000 - 0000000000100000
[    0.000000] Allocating PCI resources starting at 7f800000 (gap: 7f800000:7f500000)
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] setup_percpu: NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:4 nr_node_ids:1
[    0.000000] PERCPU: Embedded 27 pages/cpu @ffff88007ea00000 s80768 r8192 d21632 u524288
[    0.000000] pcpu-alloc: s80768 r8192 d21632 u524288 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 2 3 
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 514792
[    0.000000] Policy zone: DMA32
[    0.000000] Kernel command line: initrd=/boot/grml64/initrd.img boot=live live-media-path=/live/grml64/ bootid=grml64201112 apm=power-off vga=791 nomce toram=grml64.squashfs ssh BOOT_IMAGE=/boot/grml64/vmlinuz 
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
[    0.000000] Memory: 2039796k/2088192k available (3409k kernel code, 452k absent, 47944k reserved, 3314k data, 572k init)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU dyntick-idle grace-period acceleration is enabled.
[    0.000000] NR_IRQS:33024 nr_irqs:712 16
[    0.000000] Console: colour dummy device 80x25
[    0.000000] console [tty0] enabled
[    0.000000] allocated 16777216 bytes of page_cgroup
[    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 2999.345 MHz processor.
[    0.004007] Calibrating delay loop (skipped), value calculated using timer frequency.. 5998.69 BogoMIPS (lpj=11997380)
[    0.004017] pid_max: default: 32768 minimum: 301
[    0.004103] Security Framework initialized
[    0.004604] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.006114] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.006793] Mount-cache hash table entries: 256
[    0.007030] Initializing cgroup subsys cpuacct
[    0.007042] Initializing cgroup subsys memory
[    0.008020] Initializing cgroup subsys devices
[    0.008027] Initializing cgroup subsys freezer
[    0.008032] Initializing cgroup subsys net_cls
[    0.008039] Initializing cgroup subsys blkio
[    0.008107] CPU: Physical Processor ID: 0
[    0.008111] CPU: Processor Core ID: 0
[    0.008117] using mwait in idle threads.
[    0.008871] ACPI: Core revision 20110623
[    0.016388] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.056241] CPU0: Intel(R) Pentium(R) 4 CPU 3.00GHz stepping 09
[    0.060003] Performance Events: Netburst events, Netburst P4/Xeon PMU driver.
[    0.060003] ... version:                0
[    0.060003] ... bit width:              40
[    0.060003] ... generic registers:      18
[    0.060003] ... value mask:             000000ffffffffff
[    0.060003] ... max period:             0000007fffffffff
[    0.060003] ... fixed-purpose events:   0
[    0.060003] ... event mask:             000000000003ffff
[    0.060003] NMI watchdog enabled, takes one hw-pmu counter.
[    0.060003] Booting Node   0, Processors  #1
[    0.060003] smpboot cpu 1: start_ip = 9a000
[    0.148056] NMI watchdog enabled, takes one hw-pmu counter.
[    0.148120] Brought up 2 CPUs
[    0.148130] Total of 2 processors activated (11998.52 BogoMIPS).
[    0.148883] devtmpfs: initialized
[    0.152624] PM: Registering ACPI NVS region at 7f750000 (720896 bytes)
[    0.152624] print_constraints: dummy: 
[    0.152624] NET: Registered protocol family 16
[    0.152632] ACPI: bus type pci registered
[    0.152738] PCI: Using configuration type 1 for base access
[    0.153513] bio: create slab <bio-0> at 0
[    0.153513] ACPI: Added _OSI(Module Device)
[    0.153513] ACPI: Added _OSI(Processor Device)
[    0.153513] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.153513] ACPI: Added _OSI(Processor Aggregator Device)
[    0.153513] ACPI: EC: Look up EC in DSDT
[    0.157364] ACPI: Executed 1 blocks of module-level executable AML code
[    0.160556] ACPI Error: Method parse/execution failed [\_PR_.CPU1._PDC] (Node ffff88007b75fd58), AE_INVALID_TABLE_LENGTH (20110623/psparse-536)
[    0.160682] ACPI Error: Method parse/execution failed [\_PR_.CPU2._PDC] (Node ffff88007b75fc18), AE_INVALID_TABLE_LENGTH (20110623/psparse-536)
[    0.161340] ACPI: Interpreter enabled
[    0.161349] ACPI: (supports S0 S1 S4 S5)
[    0.161395] ACPI: Using IOAPIC for interrupt routing
[    0.172178] ACPI: No dock devices found.
[    0.172185] HEST: Table not found.
[    0.172192] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug
[    0.172318] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.172577] pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7] (ignored)
[    0.172582] pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff] (ignored)
[    0.172586] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff] (ignored)
[    0.172590] pci_root PNP0A03:00: host bridge window [mem 0x7f800000-0xffefffff] (ignored)
[    0.172607] pci 0000:00:00.0: [8086:2570] type 0 class 0x000600
[    0.172612] pci 0000:00:00.0: Enabling MCH 'Overflow' Device
[    0.172625] pci 0000:00:00.0: reg 10: [mem 0xfe800000-0xfebfffff pref]
[    0.172688] pci 0000:00:02.0: [8086:2572] type 0 class 0x000300
[    0.172704] pci 0000:00:02.0: reg 10: [mem 0xf0000000-0xf7ffffff pref]
[    0.172713] pci 0000:00:02.0: reg 14: [mem 0xff280000-0xff2fffff]
[    0.172722] pci 0000:00:02.0: reg 18: [io  0xec00-0xec07]
[    0.172780] pci 0000:00:06.0: [8086:2576] type 0 class 0x000880
[    0.172792] pci 0000:00:06.0: reg 10: [mem 0xfecf0000-0xfecf0fff]
[    0.172875] pci 0000:00:1d.0: [8086:24d2] type 0 class 0x000c03
[    0.172921] pci 0000:00:1d.0: reg 20: [io  0xdc00-0xdc1f]
[    0.172960] pci 0000:00:1d.1: [8086:24d4] type 0 class 0x000c03
[    0.173006] pci 0000:00:1d.1: reg 20: [io  0xe000-0xe01f]
[    0.173044] pci 0000:00:1d.2: [8086:24d7] type 0 class 0x000c03
[    0.173091] pci 0000:00:1d.2: reg 20: [io  0xe400-0xe41f]
[    0.173128] pci 0000:00:1d.3: [8086:24de] type 0 class 0x000c03
[    0.173174] pci 0000:00:1d.3: reg 20: [io  0xe800-0xe81f]
[    0.173223] pci 0000:00:1d.7: [8086:24dd] type 0 class 0x000c03
[    0.173247] pci 0000:00:1d.7: reg 10: [mem 0xff27fc00-0xff27ffff]
[    0.173330] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
[    0.173336] pci 0000:00:1d.7: PME# disabled
[    0.173362] pci 0000:00:1e.0: [8086:244e] type 1 class 0x000604
[    0.173411] pci 0000:00:1f.0: [8086:24d0] type 0 class 0x000601
[    0.173479] pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
[    0.173507] pci 0000:00:1f.1: [8086:24db] type 0 class 0x000101
[    0.173523] pci 0000:00:1f.1: reg 10: [io  0x0000-0x0007]
[    0.173534] pci 0000:00:1f.1: reg 14: [io  0x0000-0x0003]
[    0.173545] pci 0000:00:1f.1: reg 18: [io  0x0000-0x0007]
[    0.173555] pci 0000:00:1f.1: reg 1c: [io  0x0000-0x0003]
[    0.173566] pci 0000:00:1f.1: reg 20: [io  0xfc00-0xfc0f]
[    0.173577] pci 0000:00:1f.1: reg 24: [mem 0x00000000-0x000003ff]
[    0.173610] pci 0000:00:1f.3: [8086:24d3] type 0 class 0x000c05
[    0.173657] pci 0000:00:1f.3: reg 20: [io  0x0400-0x041f]
[    0.173699] pci 0000:00:1f.5: [8086:24d5] type 0 class 0x000401
[    0.173716] pci 0000:00:1f.5: reg 10: [io  0xd800-0xd8ff]
[    0.173726] pci 0000:00:1f.5: reg 14: [io  0xd400-0xd43f]
[    0.173736] pci 0000:00:1f.5: reg 18: [mem 0xff27f800-0xff27f9ff]
[    0.173747] pci 0000:00:1f.5: reg 1c: [mem 0xff27f400-0xff27f4ff]
[    0.173787] pci 0000:00:1f.5: PME# supported from D0 D3hot D3cold
[    0.173792] pci 0000:00:1f.5: PME# disabled
[    0.173834] pci 0000:01:05.0: [10ec:8139] type 0 class 0x000200
[    0.173852] pci 0000:01:05.0: reg 10: [io  0xb800-0xb8ff]
[    0.173863] pci 0000:01:05.0: reg 14: [mem 0xff0ffc00-0xff0ffcff]
[    0.173919] pci 0000:01:05.0: supports D1 D2
[    0.173922] pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
[    0.173927] pci 0000:01:05.0: PME# disabled
[    0.173966] pci 0000:00:1e.0: PCI bridge to [bus 01-01] (subtractive decode)
[    0.173976] pci 0000:00:1e.0:   bridge window [io  0xb000-0xbfff]
[    0.173982] pci 0000:00:1e.0:   bridge window [mem 0xff000000-0xff0fffff]
[    0.173989] pci 0000:00:1e.0:   bridge window [io  0x0000-0xffff] (subtractive decode)
[    0.173993] pci 0000:00:1e.0:   bridge window [mem 0x00000000-0xfffffffff] (subtractive decode)
[    0.174007] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.174172] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P4._PRT]
[    0.174456]  pci0000:00: Unable to request _OSC control (_OSC support mask: 0x1e)
[    0.178725] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[    0.178835] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[    0.178940] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7 10 11 12 14 15)
[    0.179047] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 *5 6 7 10 11 12 14 15)
[    0.179155] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[    0.179263] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[    0.179372] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[    0.179479] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[    0.179626] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[    0.179626] vgaarb: loaded
[    0.179626] vgaarb: bridge control possible 0000:00:02.0
[    0.179626] PCI: Using ACPI for IRQ routing
[    0.179626] PCI: pci_cache_line_size set to 64 bytes
[    0.179626] reserve RAM buffer: 000000000009fc00 - 000000000009ffff 
[    0.179626] reserve RAM buffer: 000000007f740000 - 000000007fffffff 
[    0.180161] hpet clockevent registered
[    0.180167] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
[    0.180175] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
[    0.180185] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
[    0.184049] Switching to clocksource hpet
[    0.187615] pnp: PnP ACPI init
[    0.187651] ACPI: bus type pnp registered
[    0.187806] Switched to NOHz mode on CPU #0
[    0.187829] pnp 00:00: [bus 00-ff]
[    0.187834] pnp 00:00: [io  0x0cf8-0x0cff]
[    0.187837] pnp 00:00: [io  0x0000-0x0cf7 window]
[    0.187841] pnp 00:00: [io  0x0d00-0xffff window]
[    0.187844] pnp 00:00: [mem 0x000a0000-0x000bffff window]
[    0.187848] pnp 00:00: [mem 0x00000000 window]
[    0.187851] pnp 00:00: [mem 0x7f800000-0xffefffff window]
[    0.187916] Switched to NOHz mode on CPU #1
[    0.187940] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active)
[    0.188032] pnp 00:01: [dma 4]
[    0.188036] pnp 00:01: [io  0x0000-0x000f]
[    0.188039] pnp 00:01: [io  0x0081-0x0083]
[    0.188042] pnp 00:01: [io  0x0087]
[    0.188045] pnp 00:01: [io  0x0089-0x008b]
[    0.188047] pnp 00:01: [io  0x008f]
[    0.188050] pnp 00:01: [io  0x00c0-0x00df]
[    0.188101] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active)
[    0.188128] pnp 00:02: [io  0x0070-0x0071]
[    0.188144] pnp 00:02: [irq 8]
[    0.188196] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.188217] pnp 00:03: [io  0x0061]
[    0.188266] pnp 00:03: Plug and Play ACPI device, IDs PNP0800 (active)
[    0.188287] pnp 00:04: [io  0x00f0-0x00ff]
[    0.188295] pnp 00:04: [irq 13]
[    0.188344] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
[    0.188934] pnp 00:05: [io  0x02f8-0x02ff]
[    0.188946] pnp 00:05: [irq 3]
[    0.188950] pnp 00:05: [dma 0 disabled]
[    0.189109] pnp 00:05: Plug and Play ACPI device, IDs PNP0510 (active)
[    0.189760] pnp 00:06: [io  0x03f0-0x03f5]
[    0.189764] pnp 00:06: [io  0x03f7]
[    0.189772] pnp 00:06: [irq 6]
[    0.189776] pnp 00:06: [dma 2]
[    0.189871] pnp 00:06: Plug and Play ACPI device, IDs PNP0700 (active)
[    0.190532] pnp 00:07: [io  0x0378-0x037f]
[    0.190536] pnp 00:07: [io  0x0778-0x077b]
[    0.190544] pnp 00:07: [irq 7]
[    0.190548] pnp 00:07: [dma 3]
[    0.190862] pnp 00:07: Plug and Play ACPI device, IDs PNP0401 (active)
[    0.191023] pnp 00:08: [io  0x0010-0x001f]
[    0.191027] pnp 00:08: [io  0x0022-0x003f]
[    0.191031] pnp 00:08: [io  0x0044-0x005f]
[    0.191034] pnp 00:08: [io  0x0062-0x0063]
[    0.191037] pnp 00:08: [io  0x0065-0x006f]
[    0.191040] pnp 00:08: [io  0x0072-0x007f]
[    0.191043] pnp 00:08: [io  0x0080]
[    0.191046] pnp 00:08: [io  0x0084-0x0086]
[    0.191048] pnp 00:08: [io  0x0088]
[    0.191051] pnp 00:08: [io  0x008c-0x008e]
[    0.191054] pnp 00:08: [io  0x0090-0x009f]
[    0.191057] pnp 00:08: [io  0x00a2-0x00bf]
[    0.191060] pnp 00:08: [io  0x00e0-0x00ef]
[    0.191064] pnp 00:08: [io  0x04d0-0x04d1]
[    0.191067] pnp 00:08: [io  0x0800-0x087f]
[    0.191070] pnp 00:08: [io  0x0000-0xffffffffffffffff disabled]
[    0.191073] pnp 00:08: [io  0x0480-0x04bf]
[    0.191076] pnp 00:08: [io  0x0900-0x090f]
[    0.191080] pnp 00:08: [mem 0xfed20000-0xfed8ffff]
[    0.191083] pnp 00:08: [mem 0xff380000-0xffefffff]
[    0.191183] system 00:08: [io  0x04d0-0x04d1] has been reserved
[    0.191191] system 00:08: [io  0x0800-0x087f] has been reserved
[    0.191198] system 00:08: [io  0x0480-0x04bf] has been reserved
[    0.191204] system 00:08: [io  0x0900-0x090f] has been reserved
[    0.191211] system 00:08: [mem 0xfed20000-0xfed8ffff] has been reserved
[    0.191218] system 00:08: [mem 0xff380000-0xffefffff] has been reserved
[    0.191226] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.191334] pnp 00:09: [mem 0xfec00000-0xfec00fff]
[    0.191338] pnp 00:09: [mem 0xfee00000-0xfee00fff]
[    0.191415] system 00:09: [mem 0xfec00000-0xfec00fff] could not be reserved
[    0.191424] system 00:09: [mem 0xfee00000-0xfee00fff] has been reserved
[    0.191430] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.192103] pnp 00:0a: [io  0x03f8-0x03ff]
[    0.192113] pnp 00:0a: [irq 4]
[    0.192116] pnp 00:0a: [dma 0 disabled]
[    0.192247] pnp 00:0a: Plug and Play ACPI device, IDs PNP0501 (active)
[    0.192378] pnp 00:0b: [io  0x0000-0xffffffffffffffff disabled]
[    0.192382] pnp 00:0b: [io  0x0000-0xffffffffffffffff disabled]
[    0.192386] pnp 00:0b: [io  0x0290-0x029f]
[    0.192466] system 00:0b: [io  0x0290-0x029f] has been reserved
[    0.192474] system 00:0b: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.192757] pnp 00:0c: [mem 0x00000000-0x0009ffff]
[    0.192761] pnp 00:0c: [mem 0x000c0000-0x000dffff]
[    0.192764] pnp 00:0c: [mem 0x000e0000-0x000fffff]
[    0.192767] pnp 00:0c: [mem 0x00100000-0x7f7fffff]
[    0.192770] pnp 00:0c: [mem 0xfff00000-0xffffffff]
[    0.192851] system 00:0c: [mem 0x00000000-0x0009ffff] could not be reserved
[    0.192860] system 00:0c: [mem 0x000c0000-0x000dffff] could not be reserved
[    0.192867] system 00:0c: [mem 0x000e0000-0x000fffff] could not be reserved
[    0.192873] system 00:0c: [mem 0x00100000-0x7f7fffff] could not be reserved
[    0.192880] system 00:0c: [mem 0xfff00000-0xffffffff] has been reserved
[    0.192887] system 00:0c: Plug and Play ACPI device, IDs PNP0c01 (active)
[    0.193203] pnp: PnP ACPI: found 13 devices
[    0.193208] ACPI: ACPI bus type pnp unregistered
[    0.202627] PCI: max bus depth: 1 pci_try_num: 2
[    0.202650] pci 0000:00:1f.1: BAR 5: assigned [mem 0x80000000-0x800003ff]
[    0.202662] pci 0000:00:1f.1: BAR 5: set to [mem 0x80000000-0x800003ff] (PCI address [0x80000000-0x800003ff])
[    0.202670] pci 0000:00:1e.0: PCI bridge to [bus 01-01]
[    0.202677] pci 0000:00:1e.0:   bridge window [io  0xb000-0xbfff]
[    0.202685] pci 0000:00:1e.0:   bridge window [mem 0xff000000-0xff0fffff]
[    0.202708] pci 0000:00:1e.0: setting latency timer to 64
[    0.202714] pci_bus 0000:00: resource 0 [io  0x0000-0xffff]
[    0.202717] pci_bus 0000:00: resource 1 [mem 0x00000000-0xfffffffff]
[    0.202721] pci_bus 0000:01: resource 0 [io  0xb000-0xbfff]
[    0.202724] pci_bus 0000:01: resource 1 [mem 0xff000000-0xff0fffff]
[    0.202728] pci_bus 0000:01: resource 4 [io  0x0000-0xffff]
[    0.202731] pci_bus 0000:01: resource 5 [mem 0x00000000-0xfffffffff]
[    0.202832] NET: Registered protocol family 2
[    0.203058] IP route cache hash table entries: 65536 (order: 7, 524288 bytes)
[    0.204529] TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
[    0.207250] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.207893] TCP: Hash tables configured (established 262144 bind 65536)
[    0.207901] TCP reno registered
[    0.207931] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    0.207967] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    0.208231] NET: Registered protocol family 1
[    0.208266] pci 0000:00:02.0: Boot video device
[    0.208378] PCI: CLS 0 bytes, default 64
[    0.208462] Unpacking initramfs...
[    2.344274] Freeing initrd memory: 10340k freed
[    2.351482] audit: initializing netlink socket (disabled)
[    2.351514] type=2000 audit(1326818609.344:1): initialized
[    2.375425] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    2.388051] VFS: Disk quotas dquot_6.5.2
[    2.388113] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    2.388202] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    2.388329] aufs 3.1-20111031
[    2.388340] msgmni has been set to 4004
[    2.388663] alg: No test for stdrng (krng)
[    2.388727] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    2.388737] io scheduler noop registered
[    2.388741] io scheduler deadline registered
[    2.388766] io scheduler cfq registered (default)
[    2.389039] vesafb: mode is 1024x768x16, linelength=2048, pages=4
[    2.389046] vesafb: scrolling: redraw
[    2.389051] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
[    2.389390] vesafb: framebuffer at 0xf0000000, mapped to 0xffffc90000900000, using 3072k, total 8000k
[    2.409808] Console: switching to colour frame buffer device 128x48
[    2.429069] fb0: VESA VGA frame buffer device
[    2.429304] ERST: Table is not found!
[    2.429446] GHES: HEST is not enabled!
[    2.429711] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    2.450295] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    2.480315] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a 16550A
[    2.516565] 00:0a: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    2.528208] Linux agpgart interface v0.103
[    2.528445] agpgart-intel 0000:00:00.0: Intel 865 Chipset
[    2.528677] agpgart-intel 0000:00:00.0: detected gtt size: 131072K total, 131072K mappable
[    2.529344] agpgart-intel 0000:00:00.0: detected 8192K stolen memory
[    2.529791] agpgart-intel 0000:00:00.0: AGP aperture is 128M @ 0xf0000000
[    2.530237] i8042: PNP: No PS/2 controller found. Probing ports directly.
[    2.533288] serio: i8042 KBD port at 0x60,0x64 irq 1
[    2.533490] serio: i8042 AUX port at 0x60,0x64 irq 12
[    2.533941] mousedev: PS/2 mouse device common for all mice
[    2.534225] rtc_cmos 00:02: RTC can wake from S4
[    2.534553] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
[    2.534813] rtc0: alarms up to one month, 114 bytes nvram, hpet irqs
[    2.541754] cpuidle: using governor ladder
[    2.548610] cpuidle: using governor menu
[    2.555796] TCP cubic registered
[    2.563005] NET: Registered protocol family 10
[    2.570399] Mobile IPv6
[    2.576960] NET: Registered protocol family 17
[    2.583617] Registering the dns_resolver key type
[    2.590439] PM: Hibernation image not present or could not be loaded.
[    2.590460] registered taskstats version 1
[    2.603592] rtc_cmos 00:02: setting system clock to 2012-01-17 16:43:29 UTC (1326818609)
[    2.610331] Initializing network drop monitor service
[    2.618720] Freeing unused kernel memory: 572k freed
[    2.625607] Write protecting the kernel read-only data: 6144k
[    2.636085] Freeing unused kernel memory: 668k freed
[    2.646595] Freeing unused kernel memory: 620k freed
[    2.781140] udevd[56]: starting version 175
[    2.846718] usbcore: registered new interface driver usbfs
[    2.846779] usbcore: registered new interface driver hub
[    2.859285] 8139cp: 8139cp: 10/100 PCI Ethernet driver v1.3 (Mar 22, 2004)
[    2.859320] 8139cp 0000:01:05.0: This (id 10ec:8139 rev 10) is not an 8139C+ compatible chip, use 8139too
[    2.860190] 8139too: 8139too Fast Ethernet driver 0.9.28
[    2.860269] 8139too 0000:01:05.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[    2.863890] usbcore: registered new device driver usb
[    2.865233] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.865305] ehci_hcd 0000:00:1d.7: PCI INT D -> GSI 23 (level, low) -> IRQ 23
[    2.865339] ehci_hcd 0000:00:1d.7: setting latency timer to 64
[    2.865348] ehci_hcd 0000:00:1d.7: EHCI Host Controller
[    2.865400] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1
[    2.865452] ehci_hcd 0000:00:1d.7: debug port 1
[    2.867586] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
[    2.867600] ACPI: Power Button [PWRB]
[    2.867740] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[    2.867748] ACPI: Power Button [PWRF]
[    2.869345] ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
[    2.871004] SCSI subsystem initialized
[    2.886703] 8139too 0000:01:05.0: eth0: RealTek RTL8139 at 0xffffc900008b0c00, 00:13:8f:e5:6a:40, IRQ 22
[    2.887353] ehci_hcd 0000:00:1d.7: irq 23, io mem 0xff27fc00
[    2.900890] [drm] Initialized drm 1.1.0 20060810
[    2.902544] libata version 3.00 loaded.
[    2.904456] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
[    2.904548] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    2.904555] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.904561] usb usb1: Product: EHCI Host Controller
[    2.904565] usb usb1: Manufacturer: Linux 3.1.0-3-grml-amd64 ehci_hcd
[    2.904570] usb usb1: SerialNumber: 0000:00:1d.7
[    2.905823] hub 1-0:1.0: USB hub found
[    2.905836] hub 1-0:1.0: 8 ports detected
[    2.907194] uhci_hcd: USB Universal Host Controller Interface driver
[    2.907300] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.907320] uhci_hcd 0000:00:1d.0: setting latency timer to 64
[    2.907327] uhci_hcd 0000:00:1d.0: UHCI Host Controller
[    2.907353] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
[    2.907409] uhci_hcd 0000:00:1d.0: irq 16, io base 0x0000dc00
[    2.907480] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    2.907486] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.907491] usb usb2: Product: UHCI Host Controller
[    2.907494] usb usb2: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.907499] usb usb2: SerialNumber: 0000:00:1d.0
[    2.920273] hub 2-0:1.0: USB hub found
[    2.920288] hub 2-0:1.0: 2 ports detected
[    2.920459] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
[    2.920475] uhci_hcd 0000:00:1d.1: setting latency timer to 64
[    2.920481] uhci_hcd 0000:00:1d.1: UHCI Host Controller
[    2.920499] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
[    2.920552] uhci_hcd 0000:00:1d.1: irq 19, io base 0x0000e000
[    2.920624] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
[    2.920630] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.920635] usb usb3: Product: UHCI Host Controller
[    2.920638] usb usb3: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.920643] usb usb3: SerialNumber: 0000:00:1d.1
[    2.931605] hub 3-0:1.0: USB hub found
[    2.931620] hub 3-0:1.0: 2 ports detected
[    2.931802] ata_piix 0000:00:1f.1: version 2.13
[    2.931848] ata_piix 0000:00:1f.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    2.931920] ata_piix 0000:00:1f.1: setting latency timer to 64
[    2.935324] scsi0 : ata_piix
[    2.936984] scsi1 : ata_piix
[    2.938816] Floppy drive(s): fd0 is 1.44M
[    2.941076] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0xfc00 irq 14
[    2.941086] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0xfc08 irq 15
[    2.943871] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[    2.943891] uhci_hcd 0000:00:1d.2: setting latency timer to 64
[    2.943898] uhci_hcd 0000:00:1d.2: UHCI Host Controller
[    2.943931] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
[    2.943993] uhci_hcd 0000:00:1d.2: irq 18, io base 0x0000e400
[    2.944103] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
[    2.944109] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.944114] usb usb4: Product: UHCI Host Controller
[    2.944119] usb usb4: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.944123] usb usb4: SerialNumber: 0000:00:1d.2
[    2.944399] hub 4-0:1.0: USB hub found
[    2.944412] hub 4-0:1.0: 2 ports detected
[    2.944576] uhci_hcd 0000:00:1d.3: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.944593] uhci_hcd 0000:00:1d.3: setting latency timer to 64
[    2.944600] uhci_hcd 0000:00:1d.3: UHCI Host Controller
[    2.944629] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5
[    2.944670] uhci_hcd 0000:00:1d.3: irq 16, io base 0x0000e800
[    2.944747] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[    2.944754] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.944759] usb usb5: Product: UHCI Host Controller
[    2.944763] usb usb5: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.944768] usb usb5: SerialNumber: 0000:00:1d.3
[    2.945028] hub 5-0:1.0: USB hub found
[    2.945040] hub 5-0:1.0: 2 ports detected
[    2.945263] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.945273] i915 0000:00:02.0: setting latency timer to 64
[    2.969806] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[    2.969813] [drm] Driver supports precise vblank timestamp query.
[    2.970422] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    2.972129] FDC 0 is a post-1991 82077
[    2.996945] [drm] initialized overlay support
[    3.117719] checking generic (f0000000 7d0000) vs hw (f0000000 8000000)
[    3.117724] fb: conflicting fb hw usage inteldrmfb vs VESA VGA - removing generic driver
[    3.117750] Console: switching to colour dummy device 80x25
[    3.118343] fbcon: inteldrmfb (fb0) is primary device
[    3.152531] Console: switching to colour frame buffer device 160x64
[    3.158305] fb0: inteldrmfb frame buffer device
[    3.158308] drm: registered panic notifier
[    3.158344] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[    3.266070] device-mapper: uevent: version 1.0.3
[    3.266233] device-mapper: ioctl: 4.21.0-ioctl (2011-07-06) initialised: dm-devel at redhat.com
[    3.272057] usb 1-4: new high speed USB device number 3 using ehci_hcd
[    3.310852] Uniform Multi-Platform E-IDE driver
[    3.311341] ide_generic: please use "probe_mask=0x3f" module parameter for probing all legacy ISA IDE ports
[    3.348034] Refined TSC clocksource calibration: 2999.659 MHz.
[    3.348043] Switching to clocksource tsc
[    3.492059] usb 1-4: New USB device found, idVendor=058f, idProduct=6387
[    3.492064] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    3.492068] usb 1-4: Product: Mass Storage
[    3.492071] usb 1-4: Manufacturer: Generic
[    3.492074] usb 1-4: SerialNumber: 2E19D9AC
[    3.495890] usbcore: registered new interface driver uas
[    3.497719] Initializing USB Mass Storage driver...
[    3.498101] scsi2 : usb-storage 1-4:1.0
[    3.498297] usbcore: registered new interface driver usb-storage
[    3.498303] USB Mass Storage support registered.
[    3.732019] usb 2-1: new low speed USB device number 2 using uhci_hcd
[    3.911297] usb 2-1: New USB device found, idVendor=046d, idProduct=c30f
[    3.911303] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    3.911307] usb 2-1: Product: Logitech USB Keyboard
[    3.911309] usb 2-1: Manufacturer: Logitech
[    3.936650] input: Logitech Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.0/input/input2
[    3.936811] generic-usb 0003:046D:C30F.0001: input,hidraw0: USB HID v1.10 Keyboard [Logitech Logitech USB Keyboard] on usb-0000:00:1d.0-1/input0
[    3.970389] input: Logitech Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.1/input/input3
[    3.970511] generic-usb 0003:046D:C30F.0002: input,hidraw1: USB HID v1.10 Device [Logitech Logitech USB Keyboard] on usb-0000:00:1d.0-1/input1
[    3.970551] usbcore: registered new interface driver usbhid
[    3.970555] usbhid: USB HID core driver
[    4.498054] scsi 2:0:0:0: Direct-Access     Generic  Flash Disk       8.07 PQ: 0 ANSI: 2
[    4.504408] sd 2:0:0:0: [sda] 4100096 512-byte logical blocks: (2.09 GB/1.95 GiB)
[    4.504900] sd 2:0:0:0: [sda] Write Protect is off
[    4.504905] sd 2:0:0:0: [sda] Mode Sense: 03 00 00 00
[    4.505400] sd 2:0:0:0: [sda] No Caching mode page present
[    4.505403] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.507899] sd 2:0:0:0: [sda] No Caching mode page present
[    4.507904] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.546927]  sda: sda4
[    4.549019] sd 2:0:0:0: [sda] No Caching mode page present
[    4.549024] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.549028] sd 2:0:0:0: [sda] Attached SCSI removable disk
[    5.451241] ISO 9660 Extensions: Microsoft Joliet Level 3
[    5.454866] ISO 9660 Extensions: RRIP_1991A
[   27.190876] loop: module loaded
[   27.311631]  loop0: unknown partition table
[   29.851125] udevd[658]: starting version 175
[   30.078713] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[   30.125797] i801_smbus 0000:00:1f.3: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[   30.182401] ACPI: acpi_idle registered with cpuidle
[   30.465170] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[   30.535154] input: PC Speaker as /devices/platform/pcspkr/input/input4
[   30.665947] intel_rng: FWH not detected
[   30.681734] parport_pc 00:07: reported by Plug and Play ACPI
[   30.681793] parport0: PC-style at 0x378 (0x778), irq 7 [PCSPP,TRISTATE]
[   30.789812] iTCO_vendor_support: vendor-support=0
[   30.791576] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.06
[   30.793242] iTCO_wdt: Found a ICH5 or ICH5R TCO device (Version=1, TCOBASE=0x0860)
[   30.793987] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[   31.255508] snd_intel8x0 0000:00:1f.5: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[   31.255570] snd_intel8x0 0000:00:1f.5: setting latency timer to 64
[   31.584473] intel8x0_measure_ac97_clock: measured 52973 usecs (2553 samples)
[   31.584481] intel8x0: clocking to 48000
[   33.449207] RPC: Registered named UNIX socket transport module.
[   33.449214] RPC: Registered udp transport module.
[   33.449220] RPC: Registered tcp transport module.
[   33.449224] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   33.512544] 8139too 0000:01:05.0: eth0: link up, 100Mbps, full-duplex, lpa 0x45E1
[   33.542259] FS-Cache: Loaded
[   33.605886] FS-Cache: Netfs 'nfs' registered for caching
[   33.629982] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[   36.402715] fuse init (API version 7.17)
[   36.454036] ipmi message handler version 39.2
[   43.712016] eth0: no IPv6 routers present
[   49.748490] end_request: I/O error, dev fd0, sector 0
[  402.938456] ------------[ cut here ]------------
[  402.938478] WARNING: at /tmp/buildd/linux-2.6-3.1.0/debian/build/source_amd64_none/fs/aufs/plink.c:418 au_plink_append+0xf9/0x1fb()
[  402.938485] Hardware name: To Be Filled By O.E.M.
[  402.938489] unexpectedly many pseudo links, 101
[  402.938493] Modules linked in: mperf cpufreq_userspace cpufreq_stats cpufreq_powersave cpufreq_conservative thermal sbs sbshc pci_slot fan container battery acpi_memhotplug acpi_ipmi ipmi_msghandler ac power_supply fuse md_mod configfs nfsd nfs lockd fscache auth_rpcgss nfs_acl sunrpc snd_intel8x0 snd_ac97_codec ac97_bus snd_pcm snd_seq snd_timer snd_seq_device iTCO_wdt iTCO_vendor_support snd psmouse parport_pc serio_raw evdev parport pcspkr shpchp rng_core processor soundcore i2c_i801 pci_hotplug snd_page_alloc loop nls_utf8 isofs sd_mod crc_t10dif usbhid hid usb_storage uas ide_generic ide_core dm_mirror dm_region_hash dm_log dm_mod ata_generic i915 floppy uhci_hcd ata_piix drm_kms_helper drm libata i2c_algo_bit ehci_hcd 8139too 8139cp mii scsi_mod button usbcore i2c_core video thermal_sys [last unloaded: scsi_wait_scan]
[  402.938616] Pid: 3957, comm: dpkg Not tainted 3.1.0-3-grml-amd64 #1
[  402.938619] Call Trace:
[  402.938628]  [<ffffffff810458b5>] ? warn_slowpath_common+0x78/0x8c
[  402.938633]  [<ffffffff81045961>] ? warn_slowpath_fmt+0x45/0x4a
[  402.938638]  [<ffffffff81168954>] ? au_plink_append+0xf9/0x1fb
[  402.938642]  [<ffffffff81165509>] ? aufs_link+0x401/0x78b
[  402.938649]  [<ffffffff810354cb>] ? should_resched+0x5/0x23
[  402.938655]  [<ffffffff810fe181>] ? vfs_link+0xbf/0x10a
[  402.938660]  [<ffffffff810ffd8b>] ? sys_linkat+0xee/0x13a
[  402.938667]  [<ffffffff8134fd92>] ? system_call_fastpath+0x16/0x1b
[  402.938671] ---[ end trace 2616e4ed95efbdff ]---
[  627.859494] parport_pc 00:07: disabled
[  627.878172] parport 0x378 (WARNING): CTR: wrote 0x0c, read 0xff
[  627.878182] parport 0x378 (WARNING): DATA: wrote 0xaa, read 0xff
[  627.878186] parport 0x378: You gave this address, but there is probably no parallel port there!
[  627.878209] parport0: PC-style at 0x378 [PCSPP,TRISTATE]
[  628.053719] hwinfo[5901]: segfault at 0 ip 00007fa8342c41e1 sp 00007fff98dbcbd0 error 4 in libhd.so.16.0[7fa834297000+bb000]
[  704.773973] w83627ehf: Found W83627EHG chip at 0x290
[  704.774542] w83627ehf w83627ehf.656: Setting VID input voltage to VRM10
-------------- next part --------------
[    0.000000] Initializing cgroup subsys cpuset
[    0.000000] Initializing cgroup subsys cpu
[    0.000000] Linux version 3.1.0-3-grml-amd64 (Debian 3.1.0-3+grml.1) (ch at grml.org) (gcc version 4.6.2 (Debian 4.6.2-9) ) #1 SMP Wed Dec 21 23:56:26 UTC 2011
[    0.000000] Command line: initrd=/boot/grml64/initrd.img boot=live live-media-path=/live/grml64/ bootid=grml64201112 apm=power-off vga=791 nomce toram=grml64.squashfs ssh BOOT_IMAGE=/boot/grml64/vmlinuz 
[    0.000000] BIOS-provided physical RAM map:
[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)
[    0.000000]  BIOS-e820: 000000000009fc00 - 00000000000a0000 (reserved)
[    0.000000]  BIOS-e820: 00000000000e4000 - 0000000000100000 (reserved)
[    0.000000]  BIOS-e820: 0000000000100000 - 000000007f740000 (usable)
[    0.000000]  BIOS-e820: 000000007f740000 - 000000007f750000 (ACPI data)
[    0.000000]  BIOS-e820: 000000007f750000 - 000000007f800000 (ACPI NVS)
[    0.000000]  BIOS-e820: 00000000fed00000 - 00000000fed00400 (reserved)
[    0.000000]  BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
[    0.000000]  BIOS-e820: 00000000ff380000 - 0000000100000000 (reserved)
[    0.000000] NX (Execute Disable) protection: active
[    0.000000] DMI present.
[    0.000000] DMI: To Be Filled By O.E.M. To Be Filled By O.E.M./775i65G., BIOS P3.30 12/01/2009
[    0.000000] e820 update range: 0000000000000000 - 0000000000010000 (usable) ==> (reserved)
[    0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
[    0.000000] No AGP bridge found
[    0.000000] last_pfn = 0x7f740 max_arch_pfn = 0x400000000
[    0.000000] MTRR default type: uncachable
[    0.000000] MTRR fixed ranges enabled:
[    0.000000]   00000-9FFFF write-back
[    0.000000]   A0000-DFFFF uncachable
[    0.000000]   E0000-EFFFF write-through
[    0.000000]   F0000-FFFFF write-protect
[    0.000000] MTRR variable ranges enabled:
[    0.000000]   0 base 000000000 mask F80000000 write-back
[    0.000000]   1 base 07F800000 mask FFF800000 uncachable
[    0.000000]   2 disabled
[    0.000000]   3 disabled
[    0.000000]   4 disabled
[    0.000000]   5 disabled
[    0.000000]   6 disabled
[    0.000000]   7 disabled
[    0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
[    0.000000] initial memory mapped : 0 - 20000000
[    0.000000] Base memory trampoline at [ffff88000009a000] 9a000 size 20480
[    0.000000] init_memory_mapping: 0000000000000000-000000007f740000
[    0.000000]  0000000000 - 007f600000 page 2M
[    0.000000]  007f600000 - 007f740000 page 4k
[    0.000000] kernel direct mapping tables up to 7f740000 @ 1fffc000-20000000
[    0.000000] RAMDISK: 7ed05000 - 7f71e000
[    0.000000] ACPI: RSDP 00000000000fac00 00014 (v00 ACPIAM)
[    0.000000] ACPI: RSDT 000000007f740000 00030 (v01 A_M_I  OEMRSDT  12000901 MSFT 00000097)
[    0.000000] ACPI: FACP 000000007f740200 00081 (v02 A_M_I  OEMFACP  12000601 MSFT 00000097)
[    0.000000] ACPI: DSDT 000000007f740370 036A9 (v01  75i6G 75i6G322 00000322 INTL 02002026)
[    0.000000] ACPI: FACS 000000007f750000 00040
[    0.000000] ACPI: APIC 000000007f740300 0006C (v01 A_M_I  OEMAPIC  12000901 MSFT 00000097)
[    0.000000] ACPI: OEMB 000000007f750040 0003F (v01 A_M_I  OEMBIOS  12000901 MSFT 00000097)
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] No NUMA configuration found
[    0.000000] Faking a node at 0000000000000000-000000007f740000
[    0.000000] Initmem setup node 0 0000000000000000-000000007f740000
[    0.000000]   NODE_DATA [000000007f73b000 - 000000007f73ffff]
[    0.000000]  [ffffea0000000000-ffffea0001bfffff] PMD -> [ffff88007c400000-ffff88007dffffff] on node 0
[    0.000000] Zone PFN ranges:
[    0.000000]   DMA      0x00000010 -> 0x00001000
[    0.000000]   DMA32    0x00001000 -> 0x00100000
[    0.000000]   Normal   empty
[    0.000000] Movable zone start PFN for each node
[    0.000000] early_node_map[2] active PFN ranges
[    0.000000]     0: 0x00000010 -> 0x0000009f
[    0.000000]     0: 0x00000100 -> 0x0007f740
[    0.000000] On node 0 totalpages: 521935
[    0.000000]   DMA zone: 56 pages used for memmap
[    0.000000]   DMA zone: 5 pages reserved
[    0.000000]   DMA zone: 3922 pages, LIFO batch:0
[    0.000000]   DMA32 zone: 7082 pages used for memmap
[    0.000000]   DMA32 zone: 510870 pages, LIFO batch:31
[    0.000000] ACPI: PM-Timer IO Port: 0x808
[    0.000000] ACPI: Local APIC address 0xfee00000
[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x01] enabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x82] disabled)
[    0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x83] disabled)
[    0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[    0.000000] ACPI: IRQ0 used by override.
[    0.000000] ACPI: IRQ2 used by override.
[    0.000000] ACPI: IRQ9 used by override.
[    0.000000] Using ACPI (MADT) for SMP configuration information
[    0.000000] SMP: Allowing 4 CPUs, 2 hotplug CPUs
[    0.000000] nr_irqs_gsi: 40
[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000e4000
[    0.000000] PM: Registered nosave memory: 00000000000e4000 - 0000000000100000
[    0.000000] Allocating PCI resources starting at 7f800000 (gap: 7f800000:7f500000)
[    0.000000] Booting paravirtualized kernel on bare hardware
[    0.000000] setup_percpu: NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:4 nr_node_ids:1
[    0.000000] PERCPU: Embedded 27 pages/cpu @ffff88007ea00000 s80768 r8192 d21632 u524288
[    0.000000] pcpu-alloc: s80768 r8192 d21632 u524288 alloc=1*2097152
[    0.000000] pcpu-alloc: [0] 0 1 2 3 
[    0.000000] Built 1 zonelists in Node order, mobility grouping on.  Total pages: 514792
[    0.000000] Policy zone: DMA32
[    0.000000] Kernel command line: initrd=/boot/grml64/initrd.img boot=live live-media-path=/live/grml64/ bootid=grml64201112 apm=power-off vga=791 nomce toram=grml64.squashfs ssh BOOT_IMAGE=/boot/grml64/vmlinuz 
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Checking aperture...
[    0.000000] No AGP bridge found
[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
[    0.000000] Memory: 2039796k/2088192k available (3409k kernel code, 452k absent, 47944k reserved, 3314k data, 572k init)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU dyntick-idle grace-period acceleration is enabled.
[    0.000000] NR_IRQS:33024 nr_irqs:712 16
[    0.000000] Console: colour dummy device 80x25
[    0.000000] console [tty0] enabled
[    0.000000] allocated 16777216 bytes of page_cgroup
[    0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
[    0.000000] Fast TSC calibration using PIT
[    0.000000] Detected 2999.275 MHz processor.
[    0.004007] Calibrating delay loop (skipped), value calculated using timer frequency.. 5998.55 BogoMIPS (lpj=11997100)
[    0.004019] pid_max: default: 32768 minimum: 301
[    0.004106] Security Framework initialized
[    0.004590] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.006108] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
[    0.006786] Mount-cache hash table entries: 256
[    0.007023] Initializing cgroup subsys cpuacct
[    0.007036] Initializing cgroup subsys memory
[    0.007061] Initializing cgroup subsys devices
[    0.008016] Initializing cgroup subsys freezer
[    0.008022] Initializing cgroup subsys net_cls
[    0.008029] Initializing cgroup subsys blkio
[    0.008097] CPU: Physical Processor ID: 0
[    0.008102] CPU: Processor Core ID: 0
[    0.008107] using mwait in idle threads.
[    0.008861] ACPI: Core revision 20110623
[    0.013618] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[    0.053312] CPU0: Intel(R) Pentium(R) 4 CPU 3.00GHz stepping 09
[    0.056003] Performance Events: Netburst events, Netburst P4/Xeon PMU driver.
[    0.056003] ... version:                0
[    0.056003] ... bit width:              40
[    0.056003] ... generic registers:      18
[    0.056003] ... value mask:             000000ffffffffff
[    0.056003] ... max period:             0000007fffffffff
[    0.056003] ... fixed-purpose events:   0
[    0.056003] ... event mask:             000000000003ffff
[    0.056003] NMI watchdog enabled, takes one hw-pmu counter.
[    0.056003] Booting Node   0, Processors  #1
[    0.056003] smpboot cpu 1: start_ip = 9a000
[    0.144057] NMI watchdog enabled, takes one hw-pmu counter.
[    0.144120] Brought up 2 CPUs
[    0.144131] Total of 2 processors activated (11998.28 BogoMIPS).
[    0.144881] devtmpfs: initialized
[    0.148716] PM: Registering ACPI NVS region at 7f750000 (720896 bytes)
[    0.148716] print_constraints: dummy: 
[    0.148716] NET: Registered protocol family 16
[    0.148716] ACPI: bus type pci registered
[    0.148729] PCI: Using configuration type 1 for base access
[    0.149498] bio: create slab <bio-0> at 0
[    0.149498] ACPI: Added _OSI(Module Device)
[    0.149498] ACPI: Added _OSI(Processor Device)
[    0.149498] ACPI: Added _OSI(3.0 _SCP Extensions)
[    0.149498] ACPI: Added _OSI(Processor Aggregator Device)
[    0.149498] ACPI: EC: Look up EC in DSDT
[    0.153263] ACPI: Executed 1 blocks of module-level executable AML code
[    0.156893] ACPI: Interpreter enabled
[    0.156902] ACPI: (supports S0 S1 S4 S5)
[    0.156950] ACPI: Using IOAPIC for interrupt routing
[    0.167161] ACPI: No dock devices found.
[    0.167169] HEST: Table not found.
[    0.167176] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[    0.167303] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
[    0.167559] pci_root PNP0A03:00: host bridge window [io  0x0000-0x0cf7]
[    0.167566] pci_root PNP0A03:00: host bridge window [io  0x0d00-0xffff]
[    0.167572] pci_root PNP0A03:00: host bridge window [mem 0x000a0000-0x000bffff]
[    0.167578] pci_root PNP0A03:00: host bridge window [mem 0x7f800000-0xffefffff]
[    0.167602] pci 0000:00:00.0: [8086:2570] type 0 class 0x000600
[    0.167608] pci 0000:00:00.0: Enabling MCH 'Overflow' Device
[    0.167620] pci 0000:00:00.0: reg 10: [mem 0xfe800000-0xfebfffff pref]
[    0.167682] pci 0000:00:02.0: [8086:2572] type 0 class 0x000300
[    0.167699] pci 0000:00:02.0: reg 10: [mem 0xf0000000-0xf7ffffff pref]
[    0.167708] pci 0000:00:02.0: reg 14: [mem 0xff280000-0xff2fffff]
[    0.167717] pci 0000:00:02.0: reg 18: [io  0xec00-0xec07]
[    0.167775] pci 0000:00:06.0: [8086:2576] type 0 class 0x000880
[    0.167787] pci 0000:00:06.0: reg 10: [mem 0xfecf0000-0xfecf0fff]
[    0.167870] pci 0000:00:1d.0: [8086:24d2] type 0 class 0x000c03
[    0.167920] pci 0000:00:1d.0: reg 20: [io  0xdc00-0xdc1f]
[    0.167961] pci 0000:00:1d.1: [8086:24d4] type 0 class 0x000c03
[    0.168021] pci 0000:00:1d.1: reg 20: [io  0xe000-0xe01f]
[    0.168062] pci 0000:00:1d.2: [8086:24d7] type 0 class 0x000c03
[    0.168110] pci 0000:00:1d.2: reg 20: [io  0xe400-0xe41f]
[    0.168148] pci 0000:00:1d.3: [8086:24de] type 0 class 0x000c03
[    0.168194] pci 0000:00:1d.3: reg 20: [io  0xe800-0xe81f]
[    0.168243] pci 0000:00:1d.7: [8086:24dd] type 0 class 0x000c03
[    0.168267] pci 0000:00:1d.7: reg 10: [mem 0xff27fc00-0xff27ffff]
[    0.168351] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
[    0.168357] pci 0000:00:1d.7: PME# disabled
[    0.168379] pci 0000:00:1e.0: [8086:244e] type 1 class 0x000604
[    0.168430] pci 0000:00:1f.0: [8086:24d0] type 0 class 0x000601
[    0.168497] pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
[    0.168524] pci 0000:00:1f.1: [8086:24db] type 0 class 0x000101
[    0.168540] pci 0000:00:1f.1: reg 10: [io  0x0000-0x0007]
[    0.168551] pci 0000:00:1f.1: reg 14: [io  0x0000-0x0003]
[    0.168562] pci 0000:00:1f.1: reg 18: [io  0x0000-0x0007]
[    0.168573] pci 0000:00:1f.1: reg 1c: [io  0x0000-0x0003]
[    0.168583] pci 0000:00:1f.1: reg 20: [io  0xfc00-0xfc0f]
[    0.168594] pci 0000:00:1f.1: reg 24: [mem 0x00000000-0x000003ff]
[    0.168628] pci 0000:00:1f.3: [8086:24d3] type 0 class 0x000c05
[    0.168674] pci 0000:00:1f.3: reg 20: [io  0x0400-0x041f]
[    0.168716] pci 0000:00:1f.5: [8086:24d5] type 0 class 0x000401
[    0.168733] pci 0000:00:1f.5: reg 10: [io  0xd800-0xd8ff]
[    0.168743] pci 0000:00:1f.5: reg 14: [io  0xd400-0xd43f]
[    0.168753] pci 0000:00:1f.5: reg 18: [mem 0xff27f800-0xff27f9ff]
[    0.168763] pci 0000:00:1f.5: reg 1c: [mem 0xff27f400-0xff27f4ff]
[    0.168803] pci 0000:00:1f.5: PME# supported from D0 D3hot D3cold
[    0.168808] pci 0000:00:1f.5: PME# disabled
[    0.168850] pci 0000:01:05.0: [10ec:8139] type 0 class 0x000200
[    0.168868] pci 0000:01:05.0: reg 10: [io  0xb800-0xb8ff]
[    0.168878] pci 0000:01:05.0: reg 14: [mem 0xff0ffc00-0xff0ffcff]
[    0.168935] pci 0000:01:05.0: supports D1 D2
[    0.168938] pci 0000:01:05.0: PME# supported from D1 D2 D3hot D3cold
[    0.168943] pci 0000:01:05.0: PME# disabled
[    0.168982] pci 0000:00:1e.0: PCI bridge to [bus 01-01] (subtractive decode)
[    0.168992] pci 0000:00:1e.0:   bridge window [io  0xb000-0xbfff]
[    0.168998] pci 0000:00:1e.0:   bridge window [mem 0xff000000-0xff0fffff]
[    0.169005] pci 0000:00:1e.0:   bridge window [io  0x0000-0x0cf7] (subtractive decode)
[    0.169009] pci 0000:00:1e.0:   bridge window [io  0x0d00-0xffff] (subtractive decode)
[    0.169012] pci 0000:00:1e.0:   bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
[    0.169016] pci 0000:00:1e.0:   bridge window [mem 0x7f800000-0xffefffff] (subtractive decode)
[    0.169030] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
[    0.169194] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.P0P4._PRT]
[    0.169475]  pci0000:00: Unable to request _OSC control (_OSC support mask: 0x1e)
[    0.173749] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[    0.173859] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 *5 6 7 10 11 12 14 15)
[    0.173965] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 7 10 11 12 14 15)
[    0.174071] ACPI: PCI Interrupt Link [LNKD] (IRQs *3 4 5 6 7 10 11 12 14 15)
[    0.174178] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[    0.174287] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[    0.174395] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 *5 6 7 10 11 12 14 15)
[    0.174502] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[    0.174654] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[    0.174654] vgaarb: loaded
[    0.174654] vgaarb: bridge control possible 0000:00:02.0
[    0.174654] PCI: Using ACPI for IRQ routing
[    0.174654] PCI: pci_cache_line_size set to 64 bytes
[    0.174654] Expanded resource reserved due to conflict with PCI Bus 0000:00
[    0.174654] reserve RAM buffer: 000000000009fc00 - 000000000009ffff 
[    0.174654] reserve RAM buffer: 000000007f740000 - 000000007fffffff 
[    0.174654] hpet clockevent registered
[    0.174654] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
[    0.174654] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
[    0.174654] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
[    0.180050] Switching to clocksource hpet
[    0.183618] pnp: PnP ACPI init
[    0.183654] ACPI: bus type pnp registered
[    0.183805] Switched to NOHz mode on CPU #0
[    0.183828] pnp 00:00: [bus 00-ff]
[    0.183833] pnp 00:00: [io  0x0cf8-0x0cff]
[    0.183839] pnp 00:00: [io  0x0000-0x0cf7 window]
[    0.183843] pnp 00:00: [io  0x0d00-0xffff window]
[    0.183846] pnp 00:00: [mem 0x000a0000-0x000bffff window]
[    0.183850] pnp 00:00: [mem 0x00000000 window]
[    0.183853] pnp 00:00: [mem 0x7f800000-0xffefffff window]
[    0.183917] Switched to NOHz mode on CPU #1
[    0.183939] pnp 00:00: Plug and Play ACPI device, IDs PNP0a03 (active)
[    0.184033] pnp 00:01: [dma 4]
[    0.184036] pnp 00:01: [io  0x0000-0x000f]
[    0.184040] pnp 00:01: [io  0x0081-0x0083]
[    0.184042] pnp 00:01: [io  0x0087]
[    0.184045] pnp 00:01: [io  0x0089-0x008b]
[    0.184048] pnp 00:01: [io  0x008f]
[    0.184051] pnp 00:01: [io  0x00c0-0x00df]
[    0.184101] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active)
[    0.184126] pnp 00:02: [io  0x0070-0x0071]
[    0.184142] pnp 00:02: [irq 8]
[    0.184192] pnp 00:02: Plug and Play ACPI device, IDs PNP0b00 (active)
[    0.184214] pnp 00:03: [io  0x0061]
[    0.184263] pnp 00:03: Plug and Play ACPI device, IDs PNP0800 (active)
[    0.184284] pnp 00:04: [io  0x00f0-0x00ff]
[    0.184292] pnp 00:04: [irq 13]
[    0.184344] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active)
[    0.185288] pnp 00:05: [io  0x03f0-0x03f5]
[    0.185292] pnp 00:05: [io  0x03f7]
[    0.185300] pnp 00:05: [irq 6]
[    0.185304] pnp 00:05: [dma 2]
[    0.185405] pnp 00:05: Plug and Play ACPI device, IDs PNP0700 (active)
[    0.186063] pnp 00:06: [io  0x0378-0x037f]
[    0.186067] pnp 00:06: [io  0x0778-0x077b]
[    0.186075] pnp 00:06: [irq 7]
[    0.186078] pnp 00:06: [dma 3]
[    0.186385] pnp 00:06: Plug and Play ACPI device, IDs PNP0401 (active)
[    0.186550] pnp 00:07: [io  0x0010-0x001f]
[    0.186554] pnp 00:07: [io  0x0022-0x003f]
[    0.186557] pnp 00:07: [io  0x0044-0x005f]
[    0.186560] pnp 00:07: [io  0x0062-0x0063]
[    0.186563] pnp 00:07: [io  0x0065-0x006f]
[    0.186566] pnp 00:07: [io  0x0072-0x007f]
[    0.186569] pnp 00:07: [io  0x0080]
[    0.186574] pnp 00:07: [io  0x0084-0x0086]
[    0.186577] pnp 00:07: [io  0x0088]
[    0.186580] pnp 00:07: [io  0x008c-0x008e]
[    0.186583] pnp 00:07: [io  0x0090-0x009f]
[    0.186586] pnp 00:07: [io  0x00a2-0x00bf]
[    0.186589] pnp 00:07: [io  0x00e0-0x00ef]
[    0.186592] pnp 00:07: [io  0x04d0-0x04d1]
[    0.186595] pnp 00:07: [io  0x0800-0x087f]
[    0.186598] pnp 00:07: [io  0x0000-0xffffffffffffffff disabled]
[    0.186602] pnp 00:07: [io  0x0480-0x04bf]
[    0.186605] pnp 00:07: [io  0x0900-0x090f]
[    0.186608] pnp 00:07: [mem 0xfed20000-0xfed8ffff]
[    0.186611] pnp 00:07: [mem 0xff380000-0xffefffff]
[    0.186710] system 00:07: [io  0x04d0-0x04d1] has been reserved
[    0.186719] system 00:07: [io  0x0800-0x087f] has been reserved
[    0.186725] system 00:07: [io  0x0480-0x04bf] has been reserved
[    0.186731] system 00:07: [io  0x0900-0x090f] has been reserved
[    0.186738] system 00:07: [mem 0xfed20000-0xfed8ffff] has been reserved
[    0.186745] system 00:07: [mem 0xff380000-0xffefffff] has been reserved
[    0.186752] system 00:07: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.186860] pnp 00:08: [mem 0xfec00000-0xfec00fff]
[    0.186864] pnp 00:08: [mem 0xfee00000-0xfee00fff]
[    0.186939] system 00:08: [mem 0xfec00000-0xfec00fff] could not be reserved
[    0.186948] system 00:08: [mem 0xfee00000-0xfee00fff] has been reserved
[    0.186955] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.187610] pnp 00:09: [io  0x03f8-0x03ff]
[    0.187619] pnp 00:09: [irq 4]
[    0.187623] pnp 00:09: [dma 0 disabled]
[    0.187755] pnp 00:09: Plug and Play ACPI device, IDs PNP0501 (active)
[    0.187887] pnp 00:0a: [io  0x0000-0xffffffffffffffff disabled]
[    0.187891] pnp 00:0a: [io  0x0000-0xffffffffffffffff disabled]
[    0.187895] pnp 00:0a: [io  0x0290-0x029f]
[    0.187971] system 00:0a: [io  0x0290-0x029f] has been reserved
[    0.187980] system 00:0a: Plug and Play ACPI device, IDs PNP0c02 (active)
[    0.188273] pnp 00:0b: [mem 0x00000000-0x0009ffff]
[    0.188277] pnp 00:0b: [mem 0x000c0000-0x000dffff]
[    0.188280] pnp 00:0b: [mem 0x000e0000-0x000fffff]
[    0.188283] pnp 00:0b: [mem 0x00100000-0x7f7fffff]
[    0.188286] pnp 00:0b: [mem 0xfff00000-0xffffffff]
[    0.188373] system 00:0b: [mem 0x00000000-0x0009ffff] could not be reserved
[    0.188381] system 00:0b: [mem 0x000c0000-0x000dffff] could not be reserved
[    0.188387] system 00:0b: [mem 0x000e0000-0x000fffff] could not be reserved
[    0.188394] system 00:0b: [mem 0x00100000-0x7f7fffff] could not be reserved
[    0.188401] system 00:0b: [mem 0xfff00000-0xffffffff] has been reserved
[    0.188408] system 00:0b: Plug and Play ACPI device, IDs PNP0c01 (active)
[    0.188720] pnp: PnP ACPI: found 12 devices
[    0.188726] ACPI: ACPI bus type pnp unregistered
[    0.198121] PCI: max bus depth: 1 pci_try_num: 2
[    0.198144] pci 0000:00:1f.1: BAR 5: assigned [mem 0x7f800000-0x7f8003ff]
[    0.198156] pci 0000:00:1f.1: BAR 5: set to [mem 0x7f800000-0x7f8003ff] (PCI address [0x7f800000-0x7f8003ff])
[    0.198165] pci 0000:00:1e.0: PCI bridge to [bus 01-01]
[    0.198171] pci 0000:00:1e.0:   bridge window [io  0xb000-0xbfff]
[    0.198180] pci 0000:00:1e.0:   bridge window [mem 0xff000000-0xff0fffff]
[    0.198203] pci 0000:00:1e.0: setting latency timer to 64
[    0.198209] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7]
[    0.198212] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff]
[    0.198216] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
[    0.198219] pci_bus 0000:00: resource 7 [mem 0x7f800000-0xffefffff]
[    0.198222] pci_bus 0000:01: resource 0 [io  0xb000-0xbfff]
[    0.198225] pci_bus 0000:01: resource 1 [mem 0xff000000-0xff0fffff]
[    0.198229] pci_bus 0000:01: resource 4 [io  0x0000-0x0cf7]
[    0.198232] pci_bus 0000:01: resource 5 [io  0x0d00-0xffff]
[    0.198235] pci_bus 0000:01: resource 6 [mem 0x000a0000-0x000bffff]
[    0.198238] pci_bus 0000:01: resource 7 [mem 0x7f800000-0xffefffff]
[    0.198339] NET: Registered protocol family 2
[    0.198566] IP route cache hash table entries: 65536 (order: 7, 524288 bytes)
[    0.200041] TCP established hash table entries: 262144 (order: 10, 4194304 bytes)
[    0.202764] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[    0.203412] TCP: Hash tables configured (established 262144 bind 65536)
[    0.203422] TCP reno registered
[    0.203450] UDP hash table entries: 1024 (order: 3, 32768 bytes)
[    0.203485] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
[    0.203720] NET: Registered protocol family 1
[    0.203752] pci 0000:00:02.0: Boot video device
[    0.203864] PCI: CLS 0 bytes, default 64
[    0.203951] Unpacking initramfs...
[    2.340035] Freeing initrd memory: 10340k freed
[    2.347217] audit: initializing netlink socket (disabled)
[    2.347241] type=2000 audit(1326820749.340:1): initialized
[    2.371425] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[    2.384054] VFS: Disk quotas dquot_6.5.2
[    2.384112] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    2.384202] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    2.384329] aufs 3.1-20111031
[    2.384340] msgmni has been set to 4004
[    2.384661] alg: No test for stdrng (krng)
[    2.384725] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253)
[    2.384735] io scheduler noop registered
[    2.384739] io scheduler deadline registered
[    2.384764] io scheduler cfq registered (default)
[    2.385039] vesafb: mode is 1024x768x16, linelength=2048, pages=4
[    2.385045] vesafb: scrolling: redraw
[    2.385050] vesafb: Truecolor: size=0:5:6:5, shift=0:11:5:0
[    2.385351] vesafb: framebuffer at 0xf0000000, mapped to 0xffffc90000900000, using 3072k, total 8000k
[    2.405775] Console: switching to colour frame buffer device 128x48
[    2.425041] fb0: VESA VGA frame buffer device
[    2.425273] ERST: Table is not found!
[    2.425415] GHES: HEST is not enabled!
[    2.425680] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    2.446268] serial8250: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    2.496694] 00:09: ttyS0 at I/O 0x3f8 (irq = 4) is a 16550A
[    2.512210] Linux agpgart interface v0.103
[    2.512445] agpgart-intel 0000:00:00.0: Intel 865 Chipset
[    2.512676] agpgart-intel 0000:00:00.0: detected gtt size: 131072K total, 131072K mappable
[    2.513350] agpgart-intel 0000:00:00.0: detected 8192K stolen memory
[    2.513798] agpgart-intel 0000:00:00.0: AGP aperture is 128M @ 0xf0000000
[    2.514244] i8042: PNP: No PS/2 controller found. Probing ports directly.
[    2.517303] serio: i8042 KBD port at 0x60,0x64 irq 1
[    2.517508] serio: i8042 AUX port at 0x60,0x64 irq 12
[    2.517956] mousedev: PS/2 mouse device common for all mice
[    2.518244] rtc_cmos 00:02: RTC can wake from S4
[    2.518573] rtc_cmos 00:02: rtc core: registered rtc_cmos as rtc0
[    2.518832] rtc0: alarms up to one month, 114 bytes nvram, hpet irqs
[    2.519094] cpuidle: using governor ladder
[    2.526079] cpuidle: using governor menu
[    2.533418] TCP cubic registered
[    2.540209] NET: Registered protocol family 10
[    2.548223] Mobile IPv6
[    2.554895] NET: Registered protocol family 17
[    2.561722] Registering the dns_resolver key type
[    2.568684] PM: Hibernation image not present or could not be loaded.
[    2.568705] registered taskstats version 1
[    2.581967] rtc_cmos 00:02: setting system clock to 2012-01-17 17:19:10 UTC (1326820750)
[    2.588853] Initializing network drop monitor service
[    2.597394] Freeing unused kernel memory: 572k freed
[    2.604402] Write protecting the kernel read-only data: 6144k
[    2.614920] Freeing unused kernel memory: 668k freed
[    2.625510] Freeing unused kernel memory: 620k freed
[    2.762006] udevd[56]: starting version 175
[    2.811752] input: Power Button as /devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0
[    2.811766] ACPI: Power Button [PWRB]
[    2.811901] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[    2.811910] ACPI: Power Button [PWRF]
[    2.827646] usbcore: registered new interface driver usbfs
[    2.827698] usbcore: registered new interface driver hub
[    2.850502] [drm] Initialized drm 1.1.0 20060810
[    2.856174] usbcore: registered new device driver usb
[    2.857219] 8139cp: 8139cp: 10/100 PCI Ethernet driver v1.3 (Mar 22, 2004)
[    2.857230] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    2.857290] 8139cp 0000:01:05.0: This (id 10ec:8139 rev 10) is not an 8139C+ compatible chip, use 8139too
[    2.857318] ehci_hcd 0000:00:1d.7: PCI INT D -> GSI 23 (level, low) -> IRQ 23
[    2.857354] ehci_hcd 0000:00:1d.7: setting latency timer to 64
[    2.857361] ehci_hcd 0000:00:1d.7: EHCI Host Controller
[    2.857422] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1
[    2.857477] ehci_hcd 0000:00:1d.7: debug port 1
[    2.858173] 8139too: 8139too Fast Ethernet driver 0.9.28
[    2.858227] 8139too 0000:01:05.0: PCI INT A -> GSI 22 (level, low) -> IRQ 22
[    2.859321] 8139too 0000:01:05.0: eth0: RealTek RTL8139 at 0xffffc900008aac00, 00:13:8f:e5:6a:40, IRQ 22
[    2.860703] SCSI subsystem initialized
[    2.861375] ehci_hcd 0000:00:1d.7: cache line size of 64 is not supported
[    2.870522] ehci_hcd 0000:00:1d.7: irq 23, io mem 0xff27fc00
[    2.881473] uhci_hcd: USB Universal Host Controller Interface driver
[    2.890818] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
[    2.890914] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[    2.890921] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.890927] usb usb1: Product: EHCI Host Controller
[    2.890931] usb usb1: Manufacturer: Linux 3.1.0-3-grml-amd64 ehci_hcd
[    2.890936] usb usb1: SerialNumber: 0000:00:1d.7
[    2.896285] hub 1-0:1.0: USB hub found
[    2.896300] hub 1-0:1.0: 8 ports detected
[    2.896520] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.896537] uhci_hcd 0000:00:1d.0: setting latency timer to 64
[    2.896545] uhci_hcd 0000:00:1d.0: UHCI Host Controller
[    2.896568] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
[    2.896635] uhci_hcd 0000:00:1d.0: irq 16, io base 0x0000dc00
[    2.896716] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
[    2.896723] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.896729] usb usb2: Product: UHCI Host Controller
[    2.896734] usb usb2: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.896738] usb usb2: SerialNumber: 0000:00:1d.0
[    2.897100] hub 2-0:1.0: USB hub found
[    2.897112] hub 2-0:1.0: 2 ports detected
[    2.897278] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 19 (level, low) -> IRQ 19
[    2.897294] uhci_hcd 0000:00:1d.1: setting latency timer to 64
[    2.897301] uhci_hcd 0000:00:1d.1: UHCI Host Controller
[    2.897319] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
[    2.897379] uhci_hcd 0000:00:1d.1: irq 19, io base 0x0000e000
[    2.897467] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
[    2.897477] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.897484] usb usb3: Product: UHCI Host Controller
[    2.897489] usb usb3: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.897494] usb usb3: SerialNumber: 0000:00:1d.1
[    2.897760] hub 3-0:1.0: USB hub found
[    2.897772] hub 3-0:1.0: 2 ports detected
[    2.897948] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
[    2.897964] uhci_hcd 0000:00:1d.2: setting latency timer to 64
[    2.897972] uhci_hcd 0000:00:1d.2: UHCI Host Controller
[    2.897993] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
[    2.898060] uhci_hcd 0000:00:1d.2: irq 18, io base 0x0000e400
[    2.898142] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
[    2.898150] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.898155] usb usb4: Product: UHCI Host Controller
[    2.898160] usb usb4: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.898165] usb usb4: SerialNumber: 0000:00:1d.2
[    2.898482] hub 4-0:1.0: USB hub found
[    2.898493] hub 4-0:1.0: 2 ports detected
[    2.898633] uhci_hcd 0000:00:1d.3: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.898646] uhci_hcd 0000:00:1d.3: setting latency timer to 64
[    2.898653] uhci_hcd 0000:00:1d.3: UHCI Host Controller
[    2.898668] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5
[    2.898702] uhci_hcd 0000:00:1d.3: irq 16, io base 0x0000e800
[    2.898769] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
[    2.898775] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[    2.898779] usb usb5: Product: UHCI Host Controller
[    2.898783] usb usb5: Manufacturer: Linux 3.1.0-3-grml-amd64 uhci_hcd
[    2.898787] usb usb5: SerialNumber: 0000:00:1d.3
[    2.899875] hub 5-0:1.0: USB hub found
[    2.899890] hub 5-0:1.0: 2 ports detected
[    2.908890] Floppy drive(s): fd0 is 1.44M
[    2.913199] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
[    2.913213] i915 0000:00:02.0: setting latency timer to 64
[    2.916253] libata version 3.00 loaded.
[    2.942190] [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[    2.942197] [drm] Driver supports precise vblank timestamp query.
[    2.942775] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    2.944501] FDC 0 is a post-1991 82077
[    2.973052] [drm] initialized overlay support
[    3.090788] checking generic (f0000000 7d0000) vs hw (f0000000 8000000)
[    3.090794] fb: conflicting fb hw usage inteldrmfb vs VESA VGA - removing generic driver
[    3.090820] Console: switching to colour dummy device 80x25
[    3.091356] fbcon: inteldrmfb (fb0) is primary device
[    3.124531] Console: switching to colour frame buffer device 160x64
[    3.130339] fb0: inteldrmfb frame buffer device
[    3.130342] drm: registered panic notifier
[    3.130402] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
[    3.130458] ata_piix 0000:00:1f.1: version 2.13
[    3.130505] ata_piix 0000:00:1f.1: PCI INT A -> GSI 18 (level, low) -> IRQ 18
[    3.130557] ata_piix 0000:00:1f.1: setting latency timer to 64
[    3.131635] scsi0 : ata_piix
[    3.131903] scsi1 : ata_piix
[    3.135163] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0xfc00 irq 14
[    3.135175] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0xfc08 irq 15
[    3.296067] usb 1-4: new high speed USB device number 3 using ehci_hcd
[    3.344046] Refined TSC clocksource calibration: 2999.658 MHz.
[    3.344054] Switching to clocksource tsc
[    3.406186] device-mapper: uevent: version 1.0.3
[    3.406391] device-mapper: ioctl: 4.21.0-ioctl (2011-07-06) initialised: dm-devel at redhat.com
[    3.450945] Uniform Multi-Platform E-IDE driver
[    3.451447] ide_generic: please use "probe_mask=0x3f" module parameter for probing all legacy ISA IDE ports
[    3.515987] usb 1-4: New USB device found, idVendor=058f, idProduct=6387
[    3.515993] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[    3.515996] usb 1-4: Product: Mass Storage
[    3.515999] usb 1-4: Manufacturer: Generic
[    3.516010] usb 1-4: SerialNumber: 2E19D9AC
[    3.519863] usbcore: registered new interface driver uas
[    3.521701] Initializing USB Mass Storage driver...
[    3.522067] scsi2 : usb-storage 1-4:1.0
[    3.522283] usbcore: registered new interface driver usb-storage
[    3.522289] USB Mass Storage support registered.
[    3.756019] usb 2-1: new low speed USB device number 2 using uhci_hcd
[    3.935522] usb 2-1: New USB device found, idVendor=046d, idProduct=c30f
[    3.935527] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[    3.935531] usb 2-1: Product: Logitech USB Keyboard
[    3.935534] usb 2-1: Manufacturer: Logitech
[    3.960863] input: Logitech Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.0/input/input2
[    3.961032] generic-usb 0003:046D:C30F.0001: input,hidraw0: USB HID v1.10 Keyboard [Logitech Logitech USB Keyboard] on usb-0000:00:1d.0-1/input0
[    3.995615] input: Logitech Logitech USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.1/input/input3
[    3.995728] generic-usb 0003:046D:C30F.0002: input,hidraw1: USB HID v1.10 Device [Logitech Logitech USB Keyboard] on usb-0000:00:1d.0-1/input1
[    3.995766] usbcore: registered new interface driver usbhid
[    3.995772] usbhid: USB HID core driver
[    4.522106] scsi 2:0:0:0: Direct-Access     Generic  Flash Disk       8.07 PQ: 0 ANSI: 2
[    4.528585] sd 2:0:0:0: [sda] 4100096 512-byte logical blocks: (2.09 GB/1.95 GiB)
[    4.529077] sd 2:0:0:0: [sda] Write Protect is off
[    4.529082] sd 2:0:0:0: [sda] Mode Sense: 03 00 00 00
[    4.529577] sd 2:0:0:0: [sda] No Caching mode page present
[    4.529580] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.532083] sd 2:0:0:0: [sda] No Caching mode page present
[    4.532088] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.571103]  sda: sda4
[    4.573197] sd 2:0:0:0: [sda] No Caching mode page present
[    4.573201] sd 2:0:0:0: [sda] Assuming drive cache: write through
[    4.573205] sd 2:0:0:0: [sda] Attached SCSI removable disk
[    5.591524] ISO 9660 Extensions: Microsoft Joliet Level 3
[    5.595149] ISO 9660 Extensions: RRIP_1991A
[   27.323173] loop: module loaded
[   27.444599]  loop0: unknown partition table
[   29.975379] udevd[666]: starting version 175
[   30.189275] ACPI: acpi_idle registered with cpuidle
[   30.251648] i801_smbus 0000:00:1f.3: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[   30.390779] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[   30.553384] intel_rng: FWH not detected
[   30.563080] input: PC Speaker as /devices/platform/pcspkr/input/input4
[   30.576625] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[   30.807002] parport_pc 00:06: reported by Plug and Play ACPI
[   30.807059] parport0: PC-style at 0x378 (0x778), irq 7 [PCSPP,TRISTATE]
[   30.866620] iTCO_vendor_support: vendor-support=0
[   30.871876] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.06
[   30.872947] iTCO_wdt: Found a ICH5 or ICH5R TCO device (Version=1, TCOBASE=0x0860)
[   30.874347] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[   31.216640] snd_intel8x0 0000:00:1f.5: PCI INT B -> GSI 17 (level, low) -> IRQ 17
[   31.216683] snd_intel8x0 0000:00:1f.5: setting latency timer to 64
[   31.540303] intel8x0_measure_ac97_clock: measured 53347 usecs (2571 samples)
[   31.540310] intel8x0: clocking to 48000
[   33.500146] 8139too 0000:01:05.0: eth0: link up, 100Mbps, full-duplex, lpa 0x45E1
[   33.644458] RPC: Registered named UNIX socket transport module.
[   33.644466] RPC: Registered udp transport module.
[   33.644470] RPC: Registered tcp transport module.
[   33.644474] RPC: Registered tcp NFSv4.1 backchannel transport module.
[   33.687586] FS-Cache: Loaded
[   33.739165] FS-Cache: Netfs 'nfs' registered for caching
[   33.763021] Installing knfsd (copyright (C) 1996 okir at monad.swb.de).
[   36.338361] fuse init (API version 7.17)
[   36.389872] ipmi message handler version 39.2
[   44.432010] eth0: no IPv6 routers present
[   49.656423] end_request: I/O error, dev fd0, sector 0
[  190.483621] w83627ehf: Found W83627EHG chip at 0x290
[  190.483847] w83627ehf w83627ehf.656: Setting VID input voltage to VRM10
-------------- next part --------------
# dmidecode 2.11
SMBIOS 2.4 present.
22 structures occupying 1139 bytes.
Table at 0x000FD060.

Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
	Vendor: American Megatrends Inc.
	Version: P2.70
	Release Date: 09/05/2006
	Address: 0xF0000
	Runtime Size: 64 kB
	ROM Size: 512 kB
	Characteristics:
		PCI is supported
		PNP is supported
		BIOS is upgradeable
		BIOS shadowing is allowed
		Boot from CD is supported
		Selectable boot is supported
		BIOS ROM is socketed
		EDD is supported
		5.25"/1.2 MB floppy services are supported (int 13h)
		3.5"/720 kB floppy services are supported (int 13h)
		3.5"/2.88 MB floppy services are supported (int 13h)
		Print screen service is supported (int 5h)
		8042 keyboard services are supported (int 9h)
		Serial services are supported (int 14h)
		Printer services are supported (int 17h)
		CGA/mono video services are supported (int 10h)
		ACPI is supported
		USB legacy is supported
		LS-120 boot is supported
		ATAPI Zip drive boot is supported
		BIOS boot specification is supported
		Function key-initiated network boot is supported
		Targeted content distribution is supported
	BIOS Revision: 8.10

Handle 0x0001, DMI type 1, 27 bytes
System Information
	Manufacturer: To Be Filled By O.E.M.
	Product Name: To Be Filled By O.E.M.
	Version: To Be Filled By O.E.M.
	Serial Number: To Be Filled By O.E.M.
	UUID: 00020003-0004-0005-0006-000700080009
	Wake-up Type: Power Switch
	SKU Number: To Be Filled By O.E.M.
	Family: To Be Filled By O.E.M.

Handle 0x0002, DMI type 2, 15 bytes
Base Board Information
	Manufacturer:                       
	Product Name: 775i65G.
	Version:                       
	Serial Number:                       
	Asset Tag:                       
	Features:
		Board is a hosting board
		Board is replaceable
	Location In Chassis:                       
	Chassis Handle: 0x0003
	Type: Motherboard
	Contained Object Handles: 0

Handle 0x0003, DMI type 3, 21 bytes
Chassis Information
	Manufacturer: To Be Filled By O.E.M.
	Type: Desktop
	Lock: Not Present
	Version: To Be Filled By O.E.M.
	Serial Number: To Be Filled By O.E.M.
	Asset Tag: To Be Filled By O.E.M.
	Boot-up State: Safe
	Power Supply State: Safe
	Thermal State: Safe
	Security Status: None
	OEM Information: 0x00000000
	Height: Unspecified
	Number Of Power Cords: 1
	Contained Elements: 0

Handle 0x0004, DMI type 4, 35 bytes
Processor Information
	Socket Designation: CPUSocket
	Type: Central Processor
	Family: Pentium 4
	Manufacturer: Intel            
	ID: 49 0F 00 00 FF FB EB BF
	Signature: Type 0, Family 15, Model 4, Stepping 9
	Flags:
		FPU (Floating-point unit on-chip)
		VME (Virtual mode extension)
		DE (Debugging extension)
		PSE (Page size extension)
		TSC (Time stamp counter)
		MSR (Model specific registers)
		PAE (Physical address extension)
		MCE (Machine check exception)
		CX8 (CMPXCHG8 instruction supported)
		APIC (On-chip APIC hardware supported)
		SEP (Fast system call)
		MTRR (Memory type range registers)
		PGE (Page global enable)
		MCA (Machine check architecture)
		CMOV (Conditional move instruction supported)
		PAT (Page attribute table)
		PSE-36 (36-bit page size extension)
		CLFSH (CLFLUSH instruction supported)
		DS (Debug store)
		ACPI (ACPI supported)
		MMX (MMX technology supported)
		FXSR (FXSAVE and FXSTOR instructions supported)
		SSE (Streaming SIMD extensions)
		SSE2 (Streaming SIMD extensions 2)
		SS (Self-snoop)
		HTT (Multi-threading)
		TM (Thermal monitor supported)
		PBE (Pending break enabled)
	Version: Intel(R) Pentium(R) 4 CPU 3.00GHz                   
	Voltage: 1.4 V
	External Clock: 200 MHz
	Max Speed: 3000 MHz
	Current Speed: 3000 MHz
	Status: Populated, Enabled
	Upgrade: Other
	L1 Cache Handle: 0x0005
	L2 Cache Handle: 0x0006
	L3 Cache Handle: Not Provided
	Serial Number: To Be Filled By O.E.M.
	Asset Tag: To Be Filled By O.E.M.
	Part Number: To Be Filled By O.E.M.

Handle 0x0005, DMI type 7, 19 bytes
Cache Information
	Socket Designation: L1-Cache
	Configuration: Enabled, Not Socketed, Level 1
	Operational Mode: Write Back
	Location: Internal
	Installed Size: 16 kB
	Maximum Size: 16 kB
	Supported SRAM Types:
		Other
	Installed SRAM Type: Other
	Speed: Unknown
	Error Correction Type: Parity
	System Type: Data
	Associativity: 8-way Set-associative

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
	Socket Designation: L2-Cache
	Configuration: Enabled, Not Socketed, Level 2
	Operational Mode: Write Back
	Location: Internal
	Installed Size: 1024 kB
	Maximum Size: 1024 kB
	Supported SRAM Types:
		Other
	Installed SRAM Type: Other
	Speed: Unknown
	Error Correction Type: Single-bit ECC
	System Type: Unified
	Associativity: 8-way Set-associative

Handle 0x0007, DMI type 5, 20 bytes
Memory Controller Information
	Error Detecting Method: 64-bit ECC
	Error Correcting Capabilities:
		None
	Supported Interleave: One-way Interleave
	Current Interleave: One-way Interleave
	Maximum Memory Module Size: 2048 MB
	Maximum Total Memory Size: 4096 MB
	Supported Speeds:
		70 ns
		60 ns
	Supported Memory Types:
		DIMM
		SDRAM
	Memory Module Voltage: 3.3 V
	Associated Memory Slots: 2
		0x0008
		0x0009
	Enabled Error Correcting Capabilities:
		None

Handle 0x0008, DMI type 6, 12 bytes
Memory Module Information
	Socket Designation: DIMM0
	Bank Connections: 1 0
	Current Speed: Unknown
	Type: DIMM SDRAM
	Installed Size: 1024 MB (Double-bank Connection)
	Enabled Size: 1024 MB (Double-bank Connection)
	Error Status: OK

Handle 0x0009, DMI type 6, 12 bytes
Memory Module Information
	Socket Designation: DIMM1
	Bank Connections: 5 4
	Current Speed: Unknown
	Type: DIMM SDRAM
	Installed Size: 1024 MB (Double-bank Connection)
	Enabled Size: 1024 MB (Double-bank Connection)
	Error Status: OK

Handle 0x000A, DMI type 9, 13 bytes
System Slot Information
	Designation: AGP1
	Type: 32-bit AGP 8x
	Current Usage: Available
	Length: Short
	ID: 0
	Characteristics:
		3.3 V is provided
		Opening is shared
		PME signal is supported

Handle 0x000B, DMI type 9, 13 bytes
System Slot Information
	Designation: PCI1
	Type: 32-bit PCI
	Current Usage: Available
	Length: Short
	ID: 1
	Characteristics:
		3.3 V is provided
		Opening is shared
		PME signal is supported

Handle 0x000C, DMI type 9, 13 bytes
System Slot Information
	Designation: PCI2
	Type: 32-bit PCI
	Current Usage: Available
	Length: Short
	ID: 2
	Characteristics:
		3.3 V is provided
		Opening is shared
		PME signal is supported

Handle 0x000D, DMI type 9, 13 bytes
System Slot Information
	Designation: PCI3
	Type: 32-bit PCI
	Current Usage: Available
	Length: Short
	ID: 3
	Characteristics:
		3.3 V is provided
		Opening is shared
		PME signal is supported

Handle 0x000E, DMI type 16, 15 bytes
Physical Memory Array
	Location: System Board Or Motherboard
	Use: System Memory
	Error Correction Type: None
	Maximum Capacity: 4 GB
	Error Information Handle: Not Provided
	Number Of Devices: 2

Handle 0x000F, DMI type 19, 15 bytes
Memory Array Mapped Address
	Starting Address: 0x00000000000
	Ending Address: 0x0007FFFFFFF
	Range Size: 2 GB
	Physical Array Handle: 0x000E
	Partition Width: 4

Handle 0x0010, DMI type 17, 27 bytes
Memory Device
	Array Handle: 0x000E
	Error Information Handle: Not Provided
	Total Width: 64 bits
	Data Width: 64 bits
	Size: 1024 MB
	Form Factor: DIMM
	Set: None
	Locator: DIMM0
	Bank Locator: BANK0
	Type: SDRAM
	Type Detail: Synchronous
	Speed: Unknown
	Manufacturer: Manufacturer0
	Serial Number: SerNum0
	Asset Tag: AssetTagNum0
	Part Number: PartNum0

Handle 0x0011, DMI type 20, 19 bytes
Memory Device Mapped Address
	Starting Address: 0x00000000000
	Ending Address: 0x0003FFFFFFF
	Range Size: 1 GB
	Physical Device Handle: 0x0010
	Memory Array Mapped Address Handle: 0x000F
	Partition Row Position: 1
	Interleaved Data Depth: 1

Handle 0x0012, DMI type 17, 27 bytes
Memory Device
	Array Handle: 0x000E
	Error Information Handle: Not Provided
	Total Width: 64 bits
	Data Width: 64 bits
	Size: 1024 MB
	Form Factor: DIMM
	Set: None
	Locator: DIMM1
	Bank Locator: BANK1
	Type: SDRAM
	Type Detail: Synchronous
	Speed: Unknown
	Manufacturer: Manufacturer1
	Serial Number: SerNum1
	Asset Tag: AssetTagNum1
	Part Number: PartNum1

Handle 0x0013, DMI type 20, 19 bytes
Memory Device Mapped Address
	Starting Address: 0x00040000000
	Ending Address: 0x0007FFFFFFF
	Range Size: 1 GB
	Physical Device Handle: 0x0012
	Memory Array Mapped Address Handle: 0x000F
	Partition Row Position: 1
	Interleaved Data Depth: 1

Handle 0x0014, DMI type 32, 20 bytes
System Boot Information
	Status: No errors detected

Handle 0x0015, DMI type 127, 4 bytes
End Of Table

-------------- next part --------------
00:00.0 Host bridge [0600]: Intel Corporation 82865G/PE/P DRAM Controller/Host-Hub Interface [8086:2570] (rev 02)
	Subsystem: ASRock Incorporation Device [1849:2570]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx-
	Latency: 0
	Region 0: Memory at fe800000 (32-bit, prefetchable) [size=4M]
	Capabilities: <access denied>
	Kernel driver in use: agpgart-intel
00: 86 80 70 25 06 00 90 20 02 00 00 06 00 00 00 00
10: 08 00 80 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 70 25
30: 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 00 00

00:02.0 VGA compatible controller [0300]: Intel Corporation 82865G Integrated Graphics Controller [8086:2572] (rev 02) (prog-if 00 [VGA controller])
	Subsystem: ASRock Incorporation Device [1849:2572]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx+
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at f0000000 (32-bit, prefetchable) [size=128M]
	Region 1: Memory at ff280000 (32-bit, non-prefetchable) [size=512K]
	Region 2: I/O ports at ec00 [size=8]
	Expansion ROM at <unassigned> [disabled]
	Capabilities: <access denied>
	Kernel driver in use: i915
00: 86 80 72 25 07 00 98 00 02 00 00 03 00 00 00 00
10: 08 00 00 f0 00 00 28 ff 01 ec 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 72 25
30: 00 00 00 00 d0 00 00 00 00 00 00 00 0a 01 00 00

00:06.0 System peripheral [0880]: Intel Corporation 82865G/PE/P Processor to I/O Memory Interface [8086:2576] (rev 02)
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Region 0: Memory at fecf0000 (32-bit, non-prefetchable) [size=4K]
00: 86 80 76 25 02 00 80 00 02 00 80 08 00 00 00 00
10: 00 00 cf fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:1d.0 USB controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 [8086:24d2] (rev 02) (prog-if 00 [UHCI])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 4: I/O ports at dc00 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 d2 24 05 00 80 02 02 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 dc 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00

00:1d.1 USB controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 [8086:24d4] (rev 02) (prog-if 00 [UHCI])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at e000 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 d4 24 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e0 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 05 02 00 00

00:1d.2 USB controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #3 [8086:24d7] (rev 02) (prog-if 00 [UHCI])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at e400 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 d7 24 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e4 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 05 03 00 00

00:1d.3 USB controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #4 [8086:24de] (rev 02) (prog-if 00 [UHCI])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 4: I/O ports at e800 [size=32]
	Kernel driver in use: uhci_hcd
00: 86 80 de 24 05 00 80 02 02 00 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 e8 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 0a 01 00 00

00:1d.7 USB controller [0c03]: Intel Corporation 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller [8086:24dd] (rev 02) (prog-if 20 [EHCI])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin D routed to IRQ 23
	Region 0: Memory at ff27fc00 (32-bit, non-prefetchable) [size=1K]
	Capabilities: <access denied>
	Kernel driver in use: ehci_hcd
00: 86 80 dd 24 06 01 90 02 02 20 03 0c 00 00 00 00
10: 00 fc 27 ff 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 04 00 00

00:1e.0 PCI bridge [0604]: Intel Corporation 82801 PCI Bridge [8086:244e] (rev c2) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
	I/O behind bridge: 0000b000-0000bfff
	Memory behind bridge: ff000000-ff0fffff
	Prefetchable memory behind bridge: fff00000-000fffff
	Secondary status: 66MHz- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR-
	BridgeCtl: Parity- SERR+ NoISA+ VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
00: 86 80 4e 24 07 01 80 00 c2 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 20 b0 b0 80 02
20: 00 ff 00 ff f0 ff 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06 00

00:1f.0 ISA bridge [0601]: Intel Corporation 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge [8086:24d0] (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
00: 86 80 d0 24 0f 00 80 02 02 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:1f.1 IDE interface [0101]: Intel Corporation 82801EB/ER (ICH5/ICH5R) IDE Controller [8086:24db] (rev 02) (prog-if 8a [Master SecP PriP])
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx+
	Latency: 0
	Interrupt: pin A routed to IRQ 18
	Region 0: I/O ports at 01f0 [size=8]
	Region 1: I/O ports at 03f4 [size=1]
	Region 2: I/O ports at 0170 [size=8]
	Region 3: I/O ports at 0374 [size=1]
	Region 4: I/O ports at fc00 [size=16]
	Region 5: Memory at 80000000 (32-bit, non-prefetchable) [size=1K]
	Kernel driver in use: ata_piix
00: 86 80 db 24 07 00 88 02 02 8a 01 01 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 01 fc 00 00 00 00 00 80 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00

00:1f.3 SMBus [0c05]: Intel Corporation 82801EB/ER (ICH5/ICH5R) SMBus Controller [8086:24d3] (rev 02)
	Subsystem: ASRock Incorporation Device [1849:24d0]
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Interrupt: pin B routed to IRQ 17
	Region 4: I/O ports at 0400 [size=32]
	Kernel driver in use: i801_smbus
00: 86 80 d3 24 01 00 80 02 02 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 04 00 00 00 00 00 00 00 00 00 00 49 18 d0 24
30: 00 00 00 00 00 00 00 00 00 00 00 00 0b 02 00 00

00:1f.5 Multimedia audio controller [0401]: Intel Corporation 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller [8086:24d5] (rev 02)
	Subsystem: ASRock Incorporation Device [1849:9761]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
	Interrupt: pin B routed to IRQ 17
	Region 0: I/O ports at d800 [size=256]
	Region 1: I/O ports at d400 [size=64]
	Region 2: Memory at ff27f800 (32-bit, non-prefetchable) [size=512]
	Region 3: Memory at ff27f400 (32-bit, non-prefetchable) [size=256]
	Capabilities: <access denied>
	Kernel driver in use: snd_intel8x0
00: 86 80 d5 24 07 00 90 02 02 00 01 04 00 00 00 00
10: 01 d8 00 00 01 d4 00 00 00 f8 27 ff 00 f4 27 ff
20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 61 97
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 02 00 00

01:05.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. RTL-8139/8139C/8139C+ [10ec:8139] (rev 10)
	Subsystem: ASRock Incorporation Device [1849:8139]
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 32 (8000ns min, 16000ns max)
	Interrupt: pin A routed to IRQ 22
	Region 0: I/O ports at b800 [size=256]
	Region 1: Memory at ff0ffc00 (32-bit, non-prefetchable) [size=256]
	Capabilities: <access denied>
	Kernel driver in use: 8139too
00: ec 10 39 81 07 00 90 02 10 00 00 02 00 20 00 00
10: 01 b8 00 00 00 fc 0f ff 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 49 18 39 81
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 20 40

-------------- next part --------------
w83627ehf-isa-0290
Adapter: ISA adapter
Vcore:        +1.33 V  (min =  +0.00 V, max =  +1.74 V)
in1:          +1.34 V  (min =  +1.71 V, max =  +1.37 V)  ALARM
AVCC:         +3.30 V  (min =  +1.10 V, max =  +3.17 V)  ALARM
+3.3V:        +3.28 V  (min =  +0.75 V, max =  +2.38 V)  ALARM
in4:          +1.66 V  (min =  +1.40 V, max =  +1.00 V)  ALARM
in5:          +1.74 V  (min =  +0.88 V, max =  +1.53 V)  ALARM
in6:          +1.76 V  (min =  +1.97 V, max =  +1.41 V)  ALARM
3VSB:         +3.28 V  (min =  +1.46 V, max =  +3.38 V)
Vbat:         +3.15 V  (min =  +1.65 V, max =  +1.46 V)  ALARM
in9:          +1.60 V  (min =  +0.39 V, max =  +2.03 V)
fan1:           0 RPM  (min =  703 RPM, div = 32)  ALARM
fan2:        2163 RPM  (min =  888 RPM, div = 8)
fan3:           0 RPM  (min = 1081 RPM, div = 32)  ALARM
fan5:           0 RPM  (min = 2812 RPM, div = 32)  ALARM
temp1:        +37.0?C  (high = -67.0?C, hyst = -85.0?C)  ALARM  sensor = thermistor
temp2:        +38.0?C  (high = +80.0?C, hyst = +75.0?C)  sensor = diode
temp3:        +36.0?C  (high = +80.0?C, hyst = +75.0?C)  sensor = thermistor
cpu0_vid:    +0.000 V

-------------- next part --------------
w83627ehf-isa-0290
Adapter: ISA adapter
Vcore:        +1.33 V  (min =  +0.00 V, max =  +1.74 V)
in1:          +1.37 V  (min =  +1.71 V, max =  +1.37 V)  ALARM
AVCC:         +3.28 V  (min =  +1.10 V, max =  +3.17 V)  ALARM
+3.3V:        +3.28 V  (min =  +0.75 V, max =  +2.38 V)  ALARM
in4:          +1.66 V  (min =  +1.40 V, max =  +1.00 V)  ALARM
in5:          +1.74 V  (min =  +0.88 V, max =  +1.53 V)  ALARM
in6:          +1.76 V  (min =  +1.97 V, max =  +1.41 V)  ALARM
3VSB:         +3.30 V  (min =  +1.46 V, max =  +3.38 V)
Vbat:         +3.07 V  (min =  +1.65 V, max =  +1.46 V)  ALARM
in9:          +1.56 V  (min =  +0.39 V, max =  +2.03 V)
fan1:           0 RPM  (min =  703 RPM, div = 64)  ALARM
fan2:        2136 RPM  (min =  888 RPM, div = 8)
fan3:           0 RPM  (min = 1110 RPM, div = 64)  ALARM
fan5:           0 RPM  (min = 3013 RPM, div = 64)  ALARM
temp1:        +37.0?C  (high = -67.0?C, hyst = -85.0?C)  ALARM  sensor = thermistor
temp2:        +36.0?C  (high = +80.0?C, hyst = +75.0?C)  sensor = diode
temp3:        +34.5?C  (high = +80.0?C, hyst = +75.0?C)  sensor = thermistor
cpu0_vid:    +0.000 V

-------------- next part --------------
superiotool r (master-3ad8c54)
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0x4400, id=0x6388
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x8863, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
  Failed. Returned data: chip_id=0x8863
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0x8863, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e
Register dump:
idx 20 21 22 23 24 25 26 27  28 29 2a 2b 2c 2d 2e 2f
val 88 63 ff 00 44 00 00 ff  50 04 00 00 09 41 00 ff
def 88 MM ff 00 MM 00 MM RR  50 04 00 RR 00 21 00 00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f4 f5
val 01 03 f0 06 02 0e 00 ff  00 00
def 01 03 f0 06 02 8e 00 ff  00 00
LDN 0x01 (Parallel port)
idx 30 60 61 70 74 f0
val 00 03 78 07 03 3b
def 01 03 78 07 04 3f
LDN 0x02 (COM1)
idx 30 60 61 70 f0
val 01 03 f8 04 00
def 01 03 f8 04 00
LDN 0x03 (COM2)
idx 30 60 61 70 f0 f1
val 01 02 f8 03 00 5c
def 01 02 f8 03 00 00
LDN 0x05 (Keyboard)
idx 30 60 61 62 63 70 72 f0
val 01 00 60 00 64 01 0c 82
def 01 00 60 00 64 01 0c 83
LDN 0x06 (Serial flash interface)
idx 30 62 63
val 00 ff ff
def 00 00 00
LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port)
idx 30 60 61 62 63 70 f0 f1  f2 f3 f4 f5 f6 f7
val 00 02 01 03 30 00 ff ff  ff ff ff ff ff 00
def 00 02 01 03 30 09 ff 00  00 00 ff 00 00 00
LDN 0x08 (WDTO#, PLED)
idx 30 f5 f6 f7
val 00 ff 00 ff
def 00 00 00 00
LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED)
idx 30 e0 e1 e2 e3 e4 e5 f0  f1 f2 f3 f4 f5 f6 f7
val 0e ff 01 00 ff ff ff a0  f9 00 40 ff f3 00 00
def 00 ff 00 00 ff 00 00 ff  00 00 00 ff 00 00 00
LDN 0x0a (ACPI)
idx 30 70 e0 e1 e2 e3 e4 e5  e6 e7 e8 f2 f3 f4 f6 f7
val 00 00 01 00 ff 24 00 00  0c 00 09 7c 00 00 00 00
def 00 00 01 00 ff 08 00 RR  00 00 RR 7c 00 00 00 00
LDN 0x0b (Hardware monitor)
idx 30 60 61 70 f0 f1
val 01 02 90 00 c1 3f
def 00 00 00 00 c1 00
Hardware monitor (0x0295)
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
Probing for AMD EC Super I/O at 0xaa...
Probing for Server Engines Super I/O at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Infineon Super I/O at 0x2e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Infineon Super I/O at 0x4e...
  Failed. Returned data: id=0xff, rev=0xff
-------------- next part --------------
[   186.462] 
X.Org X Server 1.11.2.902 (1.11.3 RC 2)
Release Date: 2011-12-09
[   186.470] X Protocol Version 11, Revision 0
[   186.472] Build Operating System: Linux 3.1.0-1-amd64 x86_64 Debian
[   186.475] Current Operating System: Linux grml 3.1.0-3-grml-amd64 #1 SMP Wed Dec 21 23:56:26 UTC 2011 x86_64
[   186.477] Kernel command line: initrd=/boot/grml64/initrd.img boot=live live-media-path=/live/grml64/ bootid=grml64201112 apm=power-off vga=791 nomce toram=grml64.squashfs ssh BOOT_IMAGE=/boot/grml64/vmlinuz 
[   186.483] Build Date: 10 December 2011  09:55:45PM
[   186.485] xorg-server 2:1.11.2.902-1 (Cyril Brulebois <kibi at debian.org>) 
[   186.488] Current version of pixman: 0.24.0
[   186.491] 	Before reporting problems, check http://wiki.x.org
	to make sure that you have the latest version.
[   186.496] Markers: (--) probed, (**) from config file, (==) default setting,
	(++) from command line, (!!) notice, (II) informational,
	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
[   186.504] (==) Log file: "/var/log/Xorg.0.log", Time: Tue Jan 17 16:48:28 2012
[   186.514] (==) Using system config directory "/usr/share/X11/xorg.conf.d"
[   186.526] (==) No Layout section.  Using the first Screen section.
[   186.526] (==) No screen section available. Using defaults.
[   186.526] (**) |-->Screen "Default Screen Section" (0)
[   186.526] (**) |   |-->Monitor "<default monitor>"
[   186.548] (==) No monitor specified for screen "Default Screen Section".
	Using a default monitor configuration.
[   186.548] (==) Automatically adding devices
[   186.548] (==) Automatically enabling devices
[   186.552] (WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
[   186.552] 	Entry deleted from font path.
[   186.552] (WW) The directory "/usr/share/fonts/X11/100dpi/" does not exist.
[   186.552] 	Entry deleted from font path.
[   186.553] (WW) The directory "/usr/share/fonts/X11/Type1" does not exist.
[   186.553] 	Entry deleted from font path.
[   186.553] (WW) The directory "/usr/share/fonts/X11/100dpi" does not exist.
[   186.553] 	Entry deleted from font path.
[   186.554] (WW) The directory "/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" does not exist.
[   186.554] 	Entry deleted from font path.
[   186.554] (==) FontPath set to:
	/usr/share/fonts/X11/misc,
	/usr/share/fonts/X11/75dpi/:unscaled,
	/usr/share/fonts/X11/75dpi,
	built-ins
[   186.554] (==) ModulePath set to "/usr/lib/xorg/modules"
[   186.554] (II) The server relies on udev to provide the list of input devices.
	If no devices become available, reconfigure udev or disable AutoAddDevices.
[   186.554] (II) Loader magic: 0x7f8622d45ae0
[   186.554] (II) Module ABI versions:
[   186.554] 	X.Org ANSI C Emulation: 0.4
[   186.554] 	X.Org Video Driver: 11.0
[   186.554] 	X.Org XInput driver : 13.0
[   186.554] 	X.Org Server Extension : 6.0
[   186.555] (--) PCI:*(0:0:2:0) 8086:2572:1849:2572 rev 2, Mem @ 0xf0000000/134217728, 0xff280000/524288, I/O @ 0x0000ec00/8
[   186.555] (II) Open ACPI successful (/var/run/acpid.socket)
[   186.555] (II) LoadModule: "extmod"
[   186.559] (II) Loading /usr/lib/xorg/modules/extensions/libextmod.so
[   186.576] (II) Module extmod: vendor="X.Org Foundation"
[   186.576] 	compiled for 1.11.2.902, module version = 1.0.0
[   186.576] 	Module class: X.Org Server Extension
[   186.576] 	ABI class: X.Org Server Extension, version 6.0
[   186.576] (II) Loading extension SELinux
[   186.576] (II) Loading extension MIT-SCREEN-SAVER
[   186.576] (II) Loading extension XFree86-VidModeExtension
[   186.576] (II) Loading extension XFree86-DGA
[   186.576] (II) Loading extension DPMS
[   186.576] (II) Loading extension XVideo
[   186.576] (II) Loading extension XVideo-MotionCompensation
[   186.576] (II) Loading extension X-Resource
[   186.576] (II) LoadModule: "dbe"
[   186.577] (II) Loading /usr/lib/xorg/modules/extensions/libdbe.so
[   186.592] (II) Module dbe: vendor="X.Org Foundation"
[   186.592] 	compiled for 1.11.2.902, module version = 1.0.0
[   186.592] 	Module class: X.Org Server Extension
[   186.592] 	ABI class: X.Org Server Extension, version 6.0
[   186.592] (II) Loading extension DOUBLE-BUFFER
[   186.592] (II) LoadModule: "glx"
[   186.593] (II) Loading /usr/lib/xorg/modules/extensions/libglx.so
[   186.612] (II) Module glx: vendor="X.Org Foundation"
[   186.612] 	compiled for 1.11.2.902, module version = 1.0.0
[   186.612] 	ABI class: X.Org Server Extension, version 6.0
[   186.612] (==) AIGLX enabled
[   186.612] (II) Loading extension GLX
[   186.612] (II) LoadModule: "record"
[   186.613] (II) Loading /usr/lib/xorg/modules/extensions/librecord.so
[   186.613] (II) Module record: vendor="X.Org Foundation"
[   186.613] 	compiled for 1.11.2.902, module version = 1.13.0
[   186.613] 	Module class: X.Org Server Extension
[   186.613] 	ABI class: X.Org Server Extension, version 6.0
[   186.613] (II) Loading extension RECORD
[   186.613] (II) LoadModule: "dri"
[   186.614] (II) Loading /usr/lib/xorg/modules/extensions/libdri.so
[   186.626] (II) Module dri: vendor="X.Org Foundation"
[   186.627] 	compiled for 1.11.2.902, module version = 1.0.0
[   186.627] 	ABI class: X.Org Server Extension, version 6.0
[   186.627] (II) Loading extension XFree86-DRI
[   186.627] (II) LoadModule: "dri2"
[   186.627] (II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
[   186.627] (II) Module dri2: vendor="X.Org Foundation"
[   186.627] 	compiled for 1.11.2.902, module version = 1.2.0
[   186.627] 	ABI class: X.Org Server Extension, version 6.0
[   186.627] (II) Loading extension DRI2
[   186.627] (==) Matched intel as autoconfigured driver 0
[   186.627] (==) Matched vesa as autoconfigured driver 1
[   186.627] (==) Matched fbdev as autoconfigured driver 2
[   186.627] (==) Assigned the driver to the xf86ConfigLayout
[   186.627] (II) LoadModule: "intel"
[   186.628] (II) Loading /usr/lib/xorg/modules/drivers/intel_drv.so
[   186.652] (II) Module intel: vendor="X.Org Foundation"
[   186.652] 	compiled for 1.11.1.902, module version = 2.17.0
[   186.652] 	Module class: X.Org Video Driver
[   186.652] 	ABI class: X.Org Video Driver, version 11.0
[   186.652] (II) LoadModule: "vesa"
[   186.652] (II) Loading /usr/lib/xorg/modules/drivers/vesa_drv.so
[   186.652] (II) Module vesa: vendor="X.Org Foundation"
[   186.652] 	compiled for 1.11.0, module version = 2.3.0
[   186.652] 	Module class: X.Org Video Driver
[   186.652] 	ABI class: X.Org Video Driver, version 11.0
[   186.652] (II) LoadModule: "fbdev"
[   186.652] (II) Loading /usr/lib/xorg/modules/drivers/fbdev_drv.so
[   186.669] (II) Module fbdev: vendor="X.Org Foundation"
[   186.669] 	compiled for 1.11.0, module version = 0.4.2
[   186.669] 	ABI class: X.Org Video Driver, version 11.0
[   186.669] (II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
	i810-dc100, i810e, i815, i830M, 845G, 854, 852GM/855GM, 865G, 915G,
	E7221 (i915), 915GM, 945G, 945GM, 945GME, Pineview GM, Pineview G,
	965G, G35, 965Q, 946GZ, 965GM, 965GME/GLE, G33, Q35, Q33, GM45,
	4 Series, G45/G43, Q45/Q43, G41, B43, B43, Clarkdale, Arrandale,
	Sandybridge Desktop (GT1), Sandybridge Desktop (GT2),
	Sandybridge Desktop (GT2+), Sandybridge Mobile (GT1),
	Sandybridge Mobile (GT2), Sandybridge Mobile (GT2+),
	Sandybridge Server, Ivybridge Mobile (GT1), Ivybridge Mobile (GT2),
	Ivybridge Desktop (GT1), Ivybridge Desktop (GT2), Ivybridge Server
[   186.669] (II) VESA: driver for VESA chipsets: vesa
[   186.669] (II) FBDEV: driver for framebuffer: fbdev
[   186.669] (--) using VT number 7

[   186.679] (II) Loading /usr/lib/xorg/modules/drivers/intel_drv.so
[   186.679] (WW) Falling back to old probe method for vesa
[   186.679] (WW) Falling back to old probe method for fbdev
[   186.680] (II) Loading sub module "fbdevhw"
[   186.680] (II) LoadModule: "fbdevhw"
[   186.680] (II) Loading /usr/lib/xorg/modules/libfbdevhw.so
[   186.693] (II) Module fbdevhw: vendor="X.Org Foundation"
[   186.693] 	compiled for 1.11.2.902, module version = 0.0.2
[   186.693] 	ABI class: X.Org Video Driver, version 11.0
[   186.693] drmOpenDevice: node name is /dev/dri/card0
[   186.693] drmOpenDevice: open result is 9, (OK)
[   186.693] drmOpenByBusid: Searching for BusID pci:0000:00:02.0
[   186.693] drmOpenDevice: node name is /dev/dri/card0
[   186.693] drmOpenDevice: open result is 9, (OK)
[   186.693] drmOpenByBusid: drmOpenMinor returns 9
[   186.693] drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
[   186.693] (II) intel(0): Creating default Display subsection in Screen section
	"Default Screen Section" for depth/fbbpp 24/32
[   186.693] (==) intel(0): Depth 24, (--) framebuffer bpp 32
[   186.693] (==) intel(0): RGB weight 888
[   186.693] (==) intel(0): Default visual is TrueColor
[   186.693] (II) intel(0): Integrated Graphics Chipset: Intel(R) 865G
[   186.693] (--) intel(0): Chipset: "865G"
[   186.693] (**) intel(0): Relaxed fencing disabled
[   186.694] (**) intel(0): Wait on SwapBuffers? enabled
[   186.694] (**) intel(0): Triple buffering? enabled
[   186.694] (**) intel(0): Framebuffer tiled
[   186.694] (**) intel(0): Pixmaps tiled
[   186.694] (**) intel(0): 3D buffers tiled
[   186.694] (**) intel(0): SwapBuffers wait enabled
[   186.694] (==) intel(0): video overlay key set to 0x101fe
[   186.800] (II) intel(0): Output VGA1 has no monitor section
[   186.907] (II) intel(0): EDID for output VGA1
[   186.907] (II) intel(0): Manufacturer: PTS  Model: 2ff  Serial#: 128708
[   186.907] (II) intel(0): Year: 2003  Week: 37
[   186.907] (II) intel(0): EDID Version: 1.3
[   186.907] (II) intel(0): Analog Display Input,  Input Voltage Level: 0.700/0.700 V
[   186.907] (II) intel(0): Sync:  Separate
[   186.907] (II) intel(0): Max Image Size [cm]: horiz.: 34  vert.: 27
[   186.907] (II) intel(0): Gamma: 2.50
[   186.907] (II) intel(0): DPMS capabilities: StandBy Suspend Off; RGB/Color Display
[   186.907] (II) intel(0): First detailed timing not preferred mode in violation of standard!
[   186.907] (II) intel(0): redX: 0.630 redY: 0.330   greenX: 0.300 greenY: 0.600
[   186.907] (II) intel(0): blueX: 0.148 blueY: 0.098   whiteX: 0.310 whiteY: 0.330
[   186.907] (II) intel(0): Supported established timings:
[   186.907] (II) intel(0): 720x400 at 70Hz
[   186.907] (II) intel(0): 640x480 at 60Hz
[   186.907] (II) intel(0): 640x480 at 67Hz
[   186.907] (II) intel(0): 640x480 at 72Hz
[   186.907] (II) intel(0): 640x480 at 75Hz
[   186.907] (II) intel(0): 800x600 at 56Hz
[   186.907] (II) intel(0): 800x600 at 60Hz
[   186.907] (II) intel(0): 800x600 at 72Hz
[   186.907] (II) intel(0): 800x600 at 75Hz
[   186.907] (II) intel(0): 832x624 at 75Hz
[   186.907] (II) intel(0): 1024x768 at 60Hz
[   186.907] (II) intel(0): 1024x768 at 70Hz
[   186.907] (II) intel(0): 1024x768 at 75Hz
[   186.907] (II) intel(0): 1280x1024 at 75Hz
[   186.907] (II) intel(0): Manufacturer's mask: 0
[   186.907] (II) intel(0): Supported standard timings:
[   186.907] (II) intel(0): #0: hsize: 640  vsize 360  refresh: 70  vid: 51761
[   186.907] (II) intel(0): #1: hsize: 640  vsize 400  refresh: 70  vid: 2609
[   186.907] (II) intel(0): #2: hsize: 720  vsize 405  refresh: 70  vid: 51771
[   186.907] (II) intel(0): #3: hsize: 1024  vsize 768  refresh: 75  vid: 20321
[   186.907] (II) intel(0): #4: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
[   186.907] (II) intel(0): Supported detailed timing:
[   186.907] (II) intel(0): clock: 108.0 MHz   Image Size:  337 x 270 mm
[   186.907] (II) intel(0): h_active: 1280  h_sync: 1328  h_sync_end 1440 h_blank_end 1688 h_border: 0
[   186.907] (II) intel(0): v_active: 1024  v_sync: 1025  v_sync_end 1028 v_blanking: 1066 v_border: 0
[   186.907] (II) intel(0): Ranges: V min: 60 V max: 75 Hz, H min: 30 H max: 80 kHz, PixClock max 145 MHz
[   186.907] (II) intel(0): Monitor name: CY-767C
[   186.907] (II) intel(0): Serial No: FGZJ390128708
[   186.907] (II) intel(0): EDID (in hex):
[   186.907] (II) intel(0): 	00ffffffffffff004293ff02c4f60100
[   186.907] (II) intel(0): 	250d010368221b96e86e06a1544c9926
[   186.907] (II) intel(0): 	194f54bfef0031ca310a3bca614f8180
[   186.907] (II) intel(0): 	000000000000302a009851002a403070
[   186.907] (II) intel(0): 	1300510e1100001e000000fd003c4b1e
[   186.907] (II) intel(0): 	500e000a202020202020000000fc0043
[   186.907] (II) intel(0): 	592d373637430a2020202020000000ff
[   186.907] (II) intel(0): 	0046475a4a333930313238373038003e
[   186.907] (II) intel(0): EDID vendor "PTS", prod id 767
[   186.908] (II) intel(0): Using EDID range info for horizontal sync
[   186.908] (II) intel(0): Using EDID range info for vertical refresh
[   186.908] (II) intel(0): Printing DDC gathered Modelines:
[   186.908] (II) intel(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x0.0   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
[   186.908] (II) intel(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz)
[   186.908] (II) intel(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
[   186.908] (II) intel(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
[   186.908] (II) intel(0): Modeline "640x360"x70.0   20.58  640 648 712 784  360 361 364 375 -hsync +vsync (26.2 kHz)
[   186.908] (II) intel(0): Modeline "640x400"x70.0   23.35  640 656 720 800  400 401 404 417 -hsync +vsync (29.2 kHz)
[   186.908] (II) intel(0): Modeline "720x405"x70.0   26.47  720 736 808 896  405 406 409 422 -hsync +vsync (29.5 kHz)
[   186.908] (II) intel(0): Printing probed modes for output VGA1
[   186.908] (II) intel(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
[   186.908] (II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x75.1   78.80  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.1 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
[   186.908] (II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
[   186.908] (II) intel(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
[   186.908] (II) intel(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x66.7   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz)
[   186.908] (II) intel(0): Modeline "640x480"x60.0   25.20  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
[   186.908] (II) intel(0): Modeline "720x405"x70.0   26.48  720 736 808 896  405 406 409 422 -hsync +vsync (29.6 kHz)
[   186.908] (II) intel(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz)
[   186.908] (II) intel(0): Output VGA1 connected
[   186.908] (II) intel(0): Using exact sizes for initial modes
[   186.908] (II) intel(0): Output VGA1 using initial mode 1280x1024
[   186.908] (II) intel(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
[   186.909] (II) intel(0): Kernel page flipping support detected, enabling
[   186.909] (**) intel(0): Display dimensions: (340, 270) mm
[   186.909] (**) intel(0): DPI set to (95, 96)
[   186.909] (II) Loading sub module "fb"
[   186.909] (II) LoadModule: "fb"
[   186.909] (II) Loading /usr/lib/xorg/modules/libfb.so
[   186.910] (II) Module fb: vendor="X.Org Foundation"
[   186.910] 	compiled for 1.11.2.902, module version = 1.0.0
[   186.910] 	ABI class: X.Org ANSI C Emulation, version 0.4
[   186.910] (II) Loading sub module "dri2"
[   186.910] (II) LoadModule: "dri2"
[   186.910] (II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
[   186.910] (II) Module dri2: vendor="X.Org Foundation"
[   186.910] 	compiled for 1.11.2.902, module version = 1.2.0
[   186.910] 	ABI class: X.Org Server Extension, version 6.0
[   186.910] (II) UnloadModule: "vesa"
[   186.910] (II) Unloading vesa
[   186.910] (II) UnloadModule: "fbdev"
[   186.910] (II) Unloading fbdev
[   186.910] (II) UnloadModule: "fbdevhw"
[   186.910] (II) Unloading fbdevhw
[   186.910] (==) Depth 24 pixmap format is 32 bpp
[   186.910] (II) intel(0): [DRI2] Setup complete
[   186.911] (II) intel(0): [DRI2]   DRI driver: i915
[   186.911] (II) intel(0): Allocated new frame buffer 1280x1024 stride 8192, tiled
[   186.911] (II) UXA(0): Driver registered support for the following operations:
[   186.911] (II)         solid
[   186.911] (II)         copy
[   186.911] (II)         composite (RENDER acceleration)
[   186.911] (II)         put_image
[   186.911] (II)         get_image
[   186.911] (==) intel(0): Backing store disabled
[   186.911] (==) intel(0): Silken mouse enabled
[   186.911] (II) intel(0): Initializing HW Cursor
[   186.940] (II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
[   186.940] (==) intel(0): DPMS enabled
[   186.940] (==) intel(0): Intel XvMC decoder disabled
[   186.940] (II) intel(0): Set up overlay video
[   186.940] (II) intel(0): direct rendering: DRI2 Enabled
[   186.940] (==) intel(0): hotplug detection: "enabled"
[   186.940] (--) RandR disabled
[   186.940] (II) Initializing built-in extension Generic Event Extension
[   186.940] (II) Initializing built-in extension SHAPE
[   186.940] (II) Initializing built-in extension MIT-SHM
[   186.940] (II) Initializing built-in extension XInputExtension
[   186.940] (II) Initializing built-in extension XTEST
[   186.940] (II) Initializing built-in extension BIG-REQUESTS
[   186.940] (II) Initializing built-in extension SYNC
[   186.940] (II) Initializing built-in extension XKEYBOARD
[   186.940] (II) Initializing built-in extension XC-MISC
[   186.940] (II) Initializing built-in extension SECURITY
[   186.940] (II) Initializing built-in extension XINERAMA
[   186.940] (II) Initializing built-in extension XFIXES
[   186.940] (II) Initializing built-in extension RENDER
[   186.940] (II) Initializing built-in extension RANDR
[   186.940] (II) Initializing built-in extension COMPOSITE
[   186.940] (II) Initializing built-in extension DAMAGE
[   186.941] (II) SELinux: Disabled on system
[   186.951] (EE) AIGLX error: dlopen of /usr/lib/x86_64-linux-gnu/dri/i915_dri.so failed (/usr/lib/x86_64-linux-gnu/dri/i915_dri.so: cannot open shared object file: No such file or directory)
[   186.951] (EE) AIGLX: reverting to software rendering
[   186.951] (II) AIGLX: Screen 0 is not DRI capable
[   186.952] (EE) AIGLX error: dlopen of /usr/lib/x86_64-linux-gnu/dri/swrast_dri.so failed (/usr/lib/x86_64-linux-gnu/dri/swrast_dri.so: cannot open shared object file: No such file or directory)
[   186.952] (EE) GLX: could not load software renderer
[   186.952] (II) GLX: no usable GL providers found for screen 0
[   186.952] (II) intel(0): Setting screen physical size to 338 x 270
[   187.239] (II) config/udev: Adding input device Power Button (/dev/input/event1)
[   187.239] (**) Power Button: Applying InputClass "evdev keyboard catchall"
[   187.239] (II) LoadModule: "evdev"
[   187.240] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[   187.256] (II) Module evdev: vendor="X.Org Foundation"
[   187.256] 	compiled for 1.11.0, module version = 2.6.0
[   187.256] 	Module class: X.Org XInput Driver
[   187.256] 	ABI class: X.Org XInput driver, version 13.0
[   187.256] (II) Using input driver 'evdev' for 'Power Button'
[   187.256] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[   187.256] (**) Power Button: always reports core events
[   187.256] (**) Power Button: Device: "/dev/input/event1"
[   187.256] (--) Power Button: Found keys
[   187.256] (II) Power Button: Configuring as keyboard
[   187.256] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/LNXPWRBN:00/input/input1/event1"
[   187.256] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 6)
[   187.257] (**) Option "xkb_rules" "evdev"
[   187.257] (**) Option "xkb_model" "pc105"
[   187.257] (**) Option "xkb_layout" "us"
[   187.257] (II) config/udev: Adding input device Power Button (/dev/input/event0)
[   187.257] (**) Power Button: Applying InputClass "evdev keyboard catchall"
[   187.257] (II) Using input driver 'evdev' for 'Power Button'
[   187.257] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[   187.257] (**) Power Button: always reports core events
[   187.257] (**) Power Button: Device: "/dev/input/event0"
[   187.258] (--) Power Button: Found keys
[   187.258] (II) Power Button: Configuring as keyboard
[   187.258] (**) Option "config_info" "udev:/sys/devices/LNXSYSTM:00/device:00/PNP0C0C:00/input/input0/event0"
[   187.258] (II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD, id 7)
[   187.258] (**) Option "xkb_rules" "evdev"
[   187.258] (**) Option "xkb_model" "pc105"
[   187.258] (**) Option "xkb_layout" "us"
[   187.258] (II) config/udev: Adding input device Logitech Logitech USB Keyboard (/dev/input/event2)
[   187.258] (**) Logitech Logitech USB Keyboard: Applying InputClass "evdev keyboard catchall"
[   187.258] (II) Using input driver 'evdev' for 'Logitech Logitech USB Keyboard'
[   187.259] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[   187.259] (**) Logitech Logitech USB Keyboard: always reports core events
[   187.259] (**) Logitech Logitech USB Keyboard: Device: "/dev/input/event2"
[   187.259] (--) Logitech Logitech USB Keyboard: Found keys
[   187.259] (II) Logitech Logitech USB Keyboard: Configuring as keyboard
[   187.259] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.0/input/input2/event2"
[   187.259] (II) XINPUT: Adding extended input device "Logitech Logitech USB Keyboard" (type: KEYBOARD, id 8)
[   187.259] (**) Option "xkb_rules" "evdev"
[   187.259] (**) Option "xkb_model" "pc105"
[   187.259] (**) Option "xkb_layout" "us"
[   187.260] (II) config/udev: Adding input device Logitech Logitech USB Keyboard (/dev/input/event3)
[   187.260] (**) Logitech Logitech USB Keyboard: Applying InputClass "evdev keyboard catchall"
[   187.260] (II) Using input driver 'evdev' for 'Logitech Logitech USB Keyboard'
[   187.260] (II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
[   187.260] (**) Logitech Logitech USB Keyboard: always reports core events
[   187.260] (**) Logitech Logitech USB Keyboard: Device: "/dev/input/event3"
[   187.260] (--) Logitech Logitech USB Keyboard: Found keys
[   187.260] (II) Logitech Logitech USB Keyboard: Configuring as keyboard
[   187.260] (**) Option "config_info" "udev:/sys/devices/pci0000:00/0000:00:1d.0/usb2/2-1/2-1:1.1/input/input3/event3"
[   187.260] (II) XINPUT: Adding extended input device "Logitech Logitech USB Keyboard" (type: KEYBOARD, id 9)
[   187.260] (**) Option "xkb_rules" "evdev"
[   187.260] (**) Option "xkb_model" "pc105"
[   187.260] (**) Option "xkb_layout" "us"
[   187.261] (II) config/udev: Adding input device PC Speaker (/dev/input/event4)
[   187.261] (II) No input driver/identifier specified (ignoring)
-------------- next part --------------
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From paulepanter at users.sourceforge.net  Wed Jan 18 16:24:10 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 18 Jan 2012 16:24:10 +0100
Subject: [coreboot] ASRock 775i65G (Intel 865g): `inteltool -a` and
 `flashrom -V`
In-Reply-To: <1326896951.29125.94.camel@mattotaupa>
References: <1326896951.29125.94.camel@mattotaupa>
Message-ID: <1326900250.29125.112.camel@mattotaupa>

Dear coreboot folks,


Am Mittwoch, den 18.01.2012, 15:29 +0100 schrieb Paul Menzel:

> I got the ASRock 775i65G [1] which has an Intel 865 chipset which is not
> yet supported by coreboot. Idwer is trying to port coreboot to the 856
> chipset though and as a possible target and for the archive, here are
> the log files.

as requested by Idwer I attach the output of `inteltool -a` and
`flashrom -V`.

[?]


Thanks,

Paul


> [1] http://www.asrock.com/MB/overview.asp?Model=775i65G
> [2] http://forums.ncix.com/forums/topic.php?id=2371121
> [3] http://www.ebay.de/itm/270747024710
> [4] http://www.ebay.de/itm/250708848592

-------------- next part --------------
flashrom v0.9.4-r1485 on Linux 3.1.0-3-grml-amd64 (x86_64), built with libpci 3.1.8, GCC 4.6.2, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1808M loops per second, 10 myus = 10 us, 100 myus = 242 us, 1000 myus = 1000 us, 10000 myus = 10010 us, 4 myus = 4 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "To Be Filled By O.E.M."
DMI string system-product-name: "To Be Filled By O.E.M."
DMI string system-version: "To Be Filled By O.E.M."
DMI string baseboard-manufacturer: "                      "
DMI string baseboard-product-name: "775i65G."
DMI string baseboard-version: "                      "
DMI string chassis-type: "Desktop"
Found chipset "Intel ICH5/ICH5R" with PCI ID 8086:24d0. Enabling flash write... 
BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0
OK.
Disabling flash write protection for board "ASRock 775i65G"... 
Intel ICH LPC bridge: Raising GPIO23.
OK.
The following protocols are supported: FWH.
Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0x03, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0x03, id2 0xe8, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Found Winbond flash chip "W39V040FB" (512 kB, FWH) at physical address 0xfff80000.
Lockout bits:
Hardware bootblock locking (#TBL) is not active.
Hardware remaining chip locking (#WP) is not active..
Lock status of block at 0x00000000 is Full Access.
Lock status of block at 0x00010000 is Full Access.
Lock status of block at 0x00020000 is Full Access.
Lock status of block at 0x00030000 is Full Access.
Lock status of block at 0x00040000 is Full Access.
Lock status of block at 0x00050000 is Full Access.
Lock status of block at 0x00060000 is Full Access.
Lock status of block at 0x00070000 is Full Access.
Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xda, id2 0x54
Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content
Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0xda, id2 0x54
Found Winbond flash chip "W39V040FB" (512 kB, FWH).
No operations were specified.
Restoring PCI config space for 00:1f:0 reg 0x4e
-------------- next part --------------
Intel CPU: Processor Type: 0, Family f, Model 4, Stepping 9
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)

============= GPIOS =============

GPIOBASE = 0x0480 (IO)

gpiobase+0x0000: 0x1a803180 (GPIO_USE_SEL)
gpiobase+0x0004: 0x0100ffff (GP_IO_SEL)
gpiobase+0x0008: 0x00000000 (RESERVED)
gpiobase+0x000c: 0x0b1f0000 (GP_LVL)
gpiobase+0x0010: 0x00000000 (RESERVED)
gpiobase+0x0014: 0x00000000 (GPO_TTL)
gpiobase+0x0018: 0x00040000 (GPO_BLINK)
gpiobase+0x001c: 0x00000000 (RESERVED)
gpiobase+0x0020: 0x00000000 (RESERVED)
gpiobase+0x002c: 0x00001100 (GPI_INV)
gpiobase+0x0030: 0x00000007 (GPIO_USE_SEL2)
gpiobase+0x0034: 0x00000300 (GP_IO_SEL2)
gpiobase+0x0038: 0x00000307 (GP_LVL2)



============= RCBA ==============

This southbridge does not have RCBA.



============= PMBASE ============

PMBASE = 0x0800 (IO)

pmbase+0x0000: 0x0411     (PM1_STS)
pmbase+0x0002: 0x0120     (PM1_EN)
pmbase+0x0004: 0x00000001 (PM1_CNT)
pmbase+0x0008: 0x0092fbe0 (PM1_TMR)
pmbase+0x000c: 0x00000000 (RESERVED)
pmbase+0x0010: 0x00000000 (PROC_CNT)
pmbase+0x0020: 0x00       (RESERVED)
pmbase+0x0028: 0xee3f0000 (GPE0_STS)
pmbase+0x002c: 0x00000000 (GPE0_EN)
pmbase+0x0030: 0x0000002b (SMI_EN)
pmbase+0x0034: 0x00004100 (SMI_STS)
pmbase+0x0038: 0x0000     (ALT_GP_SMI_EN)
pmbase+0x003a: 0xee3f     (ALT_GP_SMI_STS)
pmbase+0x003c: 0x00000000 (RESERVED)
pmbase+0x0040: 0x00       (MON_SMI)
pmbase+0x0042: 0x0000     (RESERVED)
pmbase+0x0044: 0x6f       (DEVACT_STS)
pmbase+0x0048: 0x00       (DEVTRAP_EN)
pmbase+0x0050: 0x00       (RESERVED)



============= MCHBAR ============

BAR6 = 0xfecf0000 (MEM)

0x0000: 0x20202010
0x0004: 0x20202020
0x0010: 0x00000033
0x0060: 0xd2a00545
0x0064: 0x001442c6
0x0068: 0x20500271
0x006c: 0x00008005
0x00b0: 0x00000824
0x00b4: 0x00000824
0x00b8: 0x00000824
0x00bc: 0x00000824
0x0100: 0x000008bf
0x0104: 0x000004ad
0x0130: 0xc6318886
0x0134: 0x00400000
0x0138: 0x2108423c
0x013c: 0x1ff01084
0x0140: 0x0001721c
0x0144: 0x0e380e38
0x0170: 0x1000018b
0x0174: 0x0480006b
0x01a0: 0x3e05dffd
0x01a8: 0x51ffff51
0x01ac: 0x0000ffff
0x01b0: 0x9fff35e5
0x01b4: 0x007d014f
0x0200: 0x00000001
0x0208: 0x0000393d
0x020c: 0x0000453f
0x0300: 0x00000032
0x0800: 0xdddddddd
0x0804: 0xeeeddddd
0x0808: 0xeeeeeeee
0x080c: 0xfffffffe
0x0810: 0xbbbbeeee
0x0814: 0xbbbbbbbb
0x0818: 0xbbbbbbbb
0x081c: 0xbbbbbbbb
0x0820: 0x0b853000
0x0824: 0x81ab068b
0x0828: 0x08001729
0x082c: 0x00000001
0x0900: 0x0a75e000
0x0a00: 0x00000044
0x0a10: 0x00113040
0x0a20: 0x23010203
0x0a24: 0x00003000
0x0a50: 0x0002411a
0x0a54: 0x00426213
0x0b10: 0x9993c4c2
0x0b14: 0x00000f0f
0x0b20: 0x0af5c000
0x0b40: 0x84000000
0x0b44: 0x21084210
0x0b48: 0x08421084
0x0b4c: 0x39ce73a3
0x0b50: 0xdef7bdef
0x0b54: 0xf7bdef7b
0x1000: 0xffffffff
0x1004: 0xffffffff
0x1008: 0xffffffff
0x100c: 0xffffffff
0x1010: 0xffffffff
0x1014: 0xffffffff
0x1018: 0xffffffff
0x101c: 0xffffffff
0x1020: 0xffffffff
0x1024: 0xffffffff
0x1028: 0xffffffff
0x102c: 0xffffffff
0x1030: 0xffffffff
0x1034: 0xffffffff
0x1038: 0xffffffff
0x103c: 0xffffffff
0x1040: 0xffffffff
0x1044: 0xffffffff
0x1048: 0xffffffff
0x104c: 0xffffffff
0x1050: 0xffffffff
0x1054: 0xffffffff
0x1058: 0xffffffff
0x105c: 0xffffffff
0x1060: 0xffffffff
0x1064: 0xffffffff
0x1068: 0xffffffff
0x106c: 0xffffffff
0x1070: 0xffffffff
0x1074: 0xffffffff
0x1078: 0xffffffff
0x107c: 0xffffffff
0x1080: 0xffffffff
0x1084: 0xffffffff
0x1088: 0xffffffff
0x108c: 0xffffffff
0x1090: 0xffffffff
0x1094: 0xffffffff
0x1098: 0xffffffff
0x109c: 0xffffffff
0x10a0: 0xffffffff
0x10a4: 0xffffffff
0x10a8: 0xffffffff
0x10ac: 0xffffffff
0x10b0: 0xffffffff
0x10b4: 0xffffffff
0x10b8: 0xffffffff
0x10bc: 0xffffffff
0x10c0: 0xffffffff
0x10c4: 0xffffffff
0x10c8: 0xffffffff
0x10cc: 0xffffffff
0x10d0: 0xffffffff
0x10d4: 0xffffffff
0x10d8: 0xffffffff
0x10dc: 0xffffffff
0x10e0: 0xffffffff
0x10e4: 0xffffffff
0x10e8: 0xffffffff
0x10ec: 0xffffffff
0x10f0: 0xffffffff
0x10f4: 0xffffffff
0x10f8: 0xffffffff
0x10fc: 0xffffffff
0x1100: 0xffffffff
0x1104: 0xffffffff
0x1108: 0xffffffff
0x110c: 0xffffffff
0x1110: 0xffffffff
0x1114: 0xffffffff
0x1118: 0xffffffff
0x111c: 0xffffffff
0x1120: 0xffffffff
0x1124: 0xffffffff
0x1128: 0xffffffff
0x112c: 0xffffffff
0x1130: 0xffffffff
0x1134: 0xffffffff
0x1138: 0xffffffff
0x113c: 0xffffffff
0x1140: 0xffffffff
0x1144: 0xffffffff
0x1148: 0xffffffff
0x114c: 0xffffffff
0x1150: 0xffffffff
0x1154: 0xffffffff
0x1158: 0xffffffff
0x115c: 0xffffffff
0x1160: 0xffffffff
0x1164: 0xffffffff
0x1168: 0xffffffff
0x116c: 0xffffffff
0x1170: 0xffffffff
0x1174: 0xffffffff
0x1178: 0xffffffff
0x117c: 0xffffffff
0x1180: 0xffffffff
0x1184: 0xffffffff
0x1188: 0xffffffff
0x118c: 0xffffffff
0x1190: 0xffffffff
0x1194: 0xffffffff
0x1198: 0xffffffff
0x119c: 0xffffffff
0x11a0: 0xffffffff
0x11a4: 0xffffffff
0x11a8: 0xffffffff
0x11ac: 0xffffffff
0x11b0: 0xffffffff
0x11b4: 0xffffffff
0x11b8: 0xffffffff
0x11bc: 0xffffffff
0x11c0: 0xffffffff
0x11c4: 0xffffffff
0x11c8: 0xffffffff
0x11cc: 0xffffffff
0x11d0: 0xffffffff
0x11d4: 0xffffffff
0x11d8: 0xffffffff
0x11dc: 0xffffffff
0x11e0: 0xffffffff
0x11e4: 0xffffffff
0x11e8: 0xffffffff
0x11ec: 0xffffffff
0x11f0: 0xffffffff
0x11f4: 0xffffffff
0x11f8: 0xffffffff
0x11fc: 0xffffffff
0x1200: 0xffffffff
0x1204: 0xffffffff
0x1208: 0xffffffff
0x120c: 0xffffffff
0x1210: 0xffffffff
0x1214: 0xffffffff
0x1218: 0xffffffff
0x121c: 0xffffffff
0x1220: 0xffffffff
0x1224: 0xffffffff
0x1228: 0xffffffff
0x122c: 0xffffffff
0x1230: 0xffffffff
0x1234: 0xffffffff
0x1238: 0xffffffff
0x123c: 0xffffffff
0x1240: 0xffffffff
0x1244: 0xffffffff
0x1248: 0xffffffff
0x124c: 0xffffffff
0x1250: 0xffffffff
0x1254: 0xffffffff
0x1258: 0xffffffff
0x125c: 0xffffffff
0x1260: 0xffffffff
0x1264: 0xffffffff
0x1268: 0xffffffff
0x126c: 0xffffffff
0x1270: 0xffffffff
0x1274: 0xffffffff
0x1278: 0xffffffff
0x127c: 0xffffffff
0x1280: 0xffffffff
0x1284: 0xffffffff
0x1288: 0xffffffff
0x128c: 0xffffffff
0x1290: 0xffffffff
0x1294: 0xffffffff
0x1298: 0xffffffff
0x129c: 0xffffffff
0x12a0: 0xffffffff
0x12a4: 0xffffffff
0x12a8: 0xffffffff
0x12ac: 0xffffffff
0x12b0: 0xffffffff
0x12b4: 0xffffffff
0x12b8: 0xffffffff
0x12bc: 0xffffffff
0x12c0: 0xffffffff
0x12c4: 0xffffffff
0x12c8: 0xffffffff
0x12cc: 0xffffffff
0x12d0: 0xffffffff
0x12d4: 0xffffffff
0x12d8: 0xffffffff
0x12dc: 0xffffffff
0x12e0: 0xffffffff
0x12e4: 0xffffffff
0x12e8: 0xffffffff
0x12ec: 0xffffffff
0x12f0: 0xffffffff
0x12f4: 0xffffffff
0x12f8: 0xffffffff
0x12fc: 0xffffffff
0x1300: 0xffffffff
0x1304: 0xffffffff
0x1308: 0xffffffff
0x130c: 0xffffffff
0x1310: 0xffffffff
0x1314: 0xffffffff
0x1318: 0xffffffff
0x131c: 0xffffffff
0x1320: 0xffffffff
0x1324: 0xffffffff
0x1328: 0xffffffff
0x132c: 0xffffffff
0x1330: 0xffffffff
0x1334: 0xffffffff
0x1338: 0xffffffff
0x133c: 0xffffffff
0x1340: 0xffffffff
0x1344: 0xffffffff
0x1348: 0xffffffff
0x134c: 0xffffffff
0x1350: 0xffffffff
0x1354: 0xffffffff
0x1358: 0xffffffff
0x135c: 0xffffffff
0x1360: 0xffffffff
0x1364: 0xffffffff
0x1368: 0xffffffff
0x136c: 0xffffffff
0x1370: 0xffffffff
0x1374: 0xffffffff
0x1378: 0xffffffff
0x137c: 0xffffffff
0x1380: 0xffffffff
0x1384: 0xffffffff
0x1388: 0xffffffff
0x138c: 0xffffffff
0x1390: 0xffffffff
0x1394: 0xffffffff
0x1398: 0xffffffff
0x139c: 0xffffffff
0x13a0: 0xffffffff
0x13a4: 0xffffffff
0x13a8: 0xffffffff
0x13ac: 0xffffffff
0x13b0: 0xffffffff
0x13b4: 0xffffffff
0x13b8: 0xffffffff
0x13bc: 0xffffffff
0x13c0: 0xffffffff
0x13c4: 0xffffffff
0x13c8: 0xffffffff
0x13cc: 0xffffffff
0x13d0: 0xffffffff
0x13d4: 0xffffffff
0x13d8: 0xffffffff
0x13dc: 0xffffffff
0x13e0: 0xffffffff
0x13e4: 0xffffffff
0x13e8: 0xffffffff
0x13ec: 0xffffffff
0x13f0: 0xffffffff
0x13f4: 0xffffffff
0x13f8: 0xffffffff
0x13fc: 0xffffffff
0x1400: 0xffffffff
0x1404: 0xffffffff
0x1408: 0xffffffff
0x140c: 0xffffffff
0x1410: 0xffffffff
0x1414: 0xffffffff
0x1418: 0xffffffff
0x141c: 0xffffffff
0x1420: 0xffffffff
0x1424: 0xffffffff
0x1428: 0xffffffff
0x142c: 0xffffffff
0x1430: 0xffffffff
0x1434: 0xffffffff
0x1438: 0xffffffff
0x143c: 0xffffffff
0x1440: 0xffffffff
0x1444: 0xffffffff
0x1448: 0xffffffff
0x144c: 0xffffffff
0x1450: 0xffffffff
0x1454: 0xffffffff
0x1458: 0xffffffff
0x145c: 0xffffffff
0x1460: 0xffffffff
0x1464: 0xffffffff
0x1468: 0xffffffff
0x146c: 0xffffffff
0x1470: 0xffffffff
0x1474: 0xffffffff
0x1478: 0xffffffff
0x147c: 0xffffffff
0x1480: 0xffffffff
0x1484: 0xffffffff
0x1488: 0xffffffff
0x148c: 0xffffffff
0x1490: 0xffffffff
0x1494: 0xffffffff
0x1498: 0xffffffff
0x149c: 0xffffffff
0x14a0: 0xffffffff
0x14a4: 0xffffffff
0x14a8: 0xffffffff
0x14ac: 0xffffffff
0x14b0: 0xffffffff
0x14b4: 0xffffffff
0x14b8: 0xffffffff
0x14bc: 0xffffffff
0x14c0: 0xffffffff
0x14c4: 0xffffffff
0x14c8: 0xffffffff
0x14cc: 0xffffffff
0x14d0: 0xffffffff
0x14d4: 0xffffffff
0x14d8: 0xffffffff
0x14dc: 0xffffffff
0x14e0: 0xffffffff
0x14e4: 0xffffffff
0x14e8: 0xffffffff
0x14ec: 0xffffffff
0x14f0: 0xffffffff
0x14f4: 0xffffffff
0x14f8: 0xffffffff
0x14fc: 0xffffffff
0x1500: 0xffffffff
0x1504: 0xffffffff
0x1508: 0xffffffff
0x150c: 0xffffffff
0x1510: 0xffffffff
0x1514: 0xffffffff
0x1518: 0xffffffff
0x151c: 0xffffffff
0x1520: 0xffffffff
0x1524: 0xffffffff
0x1528: 0xffffffff
0x152c: 0xffffffff
0x1530: 0xffffffff
0x1534: 0xffffffff
0x1538: 0xffffffff
0x153c: 0xffffffff
0x1540: 0xffffffff
0x1544: 0xffffffff
0x1548: 0xffffffff
0x154c: 0xffffffff
0x1550: 0xffffffff
0x1554: 0xffffffff
0x1558: 0xffffffff
0x155c: 0xffffffff
0x1560: 0xffffffff
0x1564: 0xffffffff
0x1568: 0xffffffff
0x156c: 0xffffffff
0x1570: 0xffffffff
0x1574: 0xffffffff
0x1578: 0xffffffff
0x157c: 0xffffffff
0x1580: 0xffffffff
0x1584: 0xffffffff
0x1588: 0xffffffff
0x158c: 0xffffffff
0x1590: 0xffffffff
0x1594: 0xffffffff
0x1598: 0xffffffff
0x159c: 0xffffffff
0x15a0: 0xffffffff
0x15a4: 0xffffffff
0x15a8: 0xffffffff
0x15ac: 0xffffffff
0x15b0: 0xffffffff
0x15b4: 0xffffffff
0x15b8: 0xffffffff
0x15bc: 0xffffffff
0x15c0: 0xffffffff
0x15c4: 0xffffffff
0x15c8: 0xffffffff
0x15cc: 0xffffffff
0x15d0: 0xffffffff
0x15d4: 0xffffffff
0x15d8: 0xffffffff
0x15dc: 0xffffffff
0x15e0: 0xffffffff
0x15e4: 0xffffffff
0x15e8: 0xffffffff
0x15ec: 0xffffffff
0x15f0: 0xffffffff
0x15f4: 0xffffffff
0x15f8: 0xffffffff
0x15fc: 0xffffffff
0x1600: 0xffffffff
0x1604: 0xffffffff
0x1608: 0xffffffff
0x160c: 0xffffffff
0x1610: 0xffffffff
0x1614: 0xffffffff
0x1618: 0xffffffff
0x161c: 0xffffffff
0x1620: 0xffffffff
0x1624: 0xffffffff
0x1628: 0xffffffff
0x162c: 0xffffffff
0x1630: 0xffffffff
0x1634: 0xffffffff
0x1638: 0xffffffff
0x163c: 0xffffffff
0x1640: 0xffffffff
0x1644: 0xffffffff
0x1648: 0xffffffff
0x164c: 0xffffffff
0x1650: 0xffffffff
0x1654: 0xffffffff
0x1658: 0xffffffff
0x165c: 0xffffffff
0x1660: 0xffffffff
0x1664: 0xffffffff
0x1668: 0xffffffff
0x166c: 0xffffffff
0x1670: 0xffffffff
0x1674: 0xffffffff
0x1678: 0xffffffff
0x167c: 0xffffffff
0x1680: 0xffffffff
0x1684: 0xffffffff
0x1688: 0xffffffff
0x168c: 0xffffffff
0x1690: 0xffffffff
0x1694: 0xffffffff
0x1698: 0xffffffff
0x169c: 0xffffffff
0x16a0: 0xffffffff
0x16a4: 0xffffffff
0x16a8: 0xffffffff
0x16ac: 0xffffffff
0x16b0: 0xffffffff
0x16b4: 0xffffffff
0x16b8: 0xffffffff
0x16bc: 0xffffffff
0x16c0: 0xffffffff
0x16c4: 0xffffffff
0x16c8: 0xffffffff
0x16cc: 0xffffffff
0x16d0: 0xffffffff
0x16d4: 0xffffffff
0x16d8: 0xffffffff
0x16dc: 0xffffffff
0x16e0: 0xffffffff
0x16e4: 0xffffffff
0x16e8: 0xffffffff
0x16ec: 0xffffffff
0x16f0: 0xffffffff
0x16f4: 0xffffffff
0x16f8: 0xffffffff
0x16fc: 0xffffffff
0x1700: 0xffffffff
0x1704: 0xffffffff
0x1708: 0xffffffff
0x170c: 0xffffffff
0x1710: 0xffffffff
0x1714: 0xffffffff
0x1718: 0xffffffff
0x171c: 0xffffffff
0x1720: 0xffffffff
0x1724: 0xffffffff
0x1728: 0xffffffff
0x172c: 0xffffffff
0x1730: 0xffffffff
0x1734: 0xffffffff
0x1738: 0xffffffff
0x173c: 0xffffffff
0x1740: 0xffffffff
0x1744: 0xffffffff
0x1748: 0xffffffff
0x174c: 0xffffffff
0x1750: 0xffffffff
0x1754: 0xffffffff
0x1758: 0xffffffff
0x175c: 0xffffffff
0x1760: 0xffffffff
0x1764: 0xffffffff
0x1768: 0xffffffff
0x176c: 0xffffffff
0x1770: 0xffffffff
0x1774: 0xffffffff
0x1778: 0xffffffff
0x177c: 0xffffffff
0x1780: 0xffffffff
0x1784: 0xffffffff
0x1788: 0xffffffff
0x178c: 0xffffffff
0x1790: 0xffffffff
0x1794: 0xffffffff
0x1798: 0xffffffff
0x179c: 0xffffffff
0x17a0: 0xffffffff
0x17a4: 0xffffffff
0x17a8: 0xffffffff
0x17ac: 0xffffffff
0x17b0: 0xffffffff
0x17b4: 0xffffffff
0x17b8: 0xffffffff
0x17bc: 0xffffffff
0x17c0: 0xffffffff
0x17c4: 0xffffffff
0x17c8: 0xffffffff
0x17cc: 0xffffffff
0x17d0: 0xffffffff
0x17d4: 0xffffffff
0x17d8: 0xffffffff
0x17dc: 0xffffffff
0x17e0: 0xffffffff
0x17e4: 0xffffffff
0x17e8: 0xffffffff
0x17ec: 0xffffffff
0x17f0: 0xffffffff
0x17f4: 0xffffffff
0x17f8: 0xffffffff
0x17fc: 0xffffffff
0x1800: 0xffffffff
0x1804: 0xffffffff
0x1808: 0xffffffff
0x180c: 0xffffffff
0x1810: 0xffffffff
0x1814: 0xffffffff
0x1818: 0xffffffff
0x181c: 0xffffffff
0x1820: 0xffffffff
0x1824: 0xffffffff
0x1828: 0xffffffff
0x182c: 0xffffffff
0x1830: 0xffffffff
0x1834: 0xffffffff
0x1838: 0xffffffff
0x183c: 0xffffffff
0x1840: 0xffffffff
0x1844: 0xffffffff
0x1848: 0xffffffff
0x184c: 0xffffffff
0x1850: 0xffffffff
0x1854: 0xffffffff
0x1858: 0xffffffff
0x185c: 0xffffffff
0x1860: 0xffffffff
0x1864: 0xffffffff
0x1868: 0xffffffff
0x186c: 0xffffffff
0x1870: 0xffffffff
0x1874: 0xffffffff
0x1878: 0xffffffff
0x187c: 0xffffffff
0x1880: 0xffffffff
0x1884: 0xffffffff
0x1888: 0xffffffff
0x188c: 0xffffffff
0x1890: 0xffffffff
0x1894: 0xffffffff
0x1898: 0xffffffff
0x189c: 0xffffffff
0x18a0: 0xffffffff
0x18a4: 0xffffffff
0x18a8: 0xffffffff
0x18ac: 0xffffffff
0x18b0: 0xffffffff
0x18b4: 0xffffffff
0x18b8: 0xffffffff
0x18bc: 0xffffffff
0x18c0: 0xffffffff
0x18c4: 0xffffffff
0x18c8: 0xffffffff
0x18cc: 0xffffffff
0x18d0: 0xffffffff
0x18d4: 0xffffffff
0x18d8: 0xffffffff
0x18dc: 0xffffffff
0x18e0: 0xffffffff
0x18e4: 0xffffffff
0x18e8: 0xffffffff
0x18ec: 0xffffffff
0x18f0: 0xffffffff
0x18f4: 0xffffffff
0x18f8: 0xffffffff
0x18fc: 0xffffffff
0x1900: 0xffffffff
0x1904: 0xffffffff
0x1908: 0xffffffff
0x190c: 0xffffffff
0x1910: 0xffffffff
0x1914: 0xffffffff
0x1918: 0xffffffff
0x191c: 0xffffffff
0x1920: 0xffffffff
0x1924: 0xffffffff
0x1928: 0xffffffff
0x192c: 0xffffffff
0x1930: 0xffffffff
0x1934: 0xffffffff
0x1938: 0xffffffff
0x193c: 0xffffffff
0x1940: 0xffffffff
0x1944: 0xffffffff
0x1948: 0xffffffff
0x194c: 0xffffffff
0x1950: 0xffffffff
0x1954: 0xffffffff
0x1958: 0xffffffff
0x195c: 0xffffffff
0x1960: 0xffffffff
0x1964: 0xffffffff
0x1968: 0xffffffff
0x196c: 0xffffffff
0x1970: 0xffffffff
0x1974: 0xffffffff
0x1978: 0xffffffff
0x197c: 0xffffffff
0x1980: 0xffffffff
0x1984: 0xffffffff
0x1988: 0xffffffff
0x198c: 0xffffffff
0x1990: 0xffffffff
0x1994: 0xffffffff
0x1998: 0xffffffff
0x199c: 0xffffffff
0x19a0: 0xffffffff
0x19a4: 0xffffffff
0x19a8: 0xffffffff
0x19ac: 0xffffffff
0x19b0: 0xffffffff
0x19b4: 0xffffffff
0x19b8: 0xffffffff
0x19bc: 0xffffffff
0x19c0: 0xffffffff
0x19c4: 0xffffffff
0x19c8: 0xffffffff
0x19cc: 0xffffffff
0x19d0: 0xffffffff
0x19d4: 0xffffffff
0x19d8: 0xffffffff
0x19dc: 0xffffffff
0x19e0: 0xffffffff
0x19e4: 0xffffffff
0x19e8: 0xffffffff
0x19ec: 0xffffffff
0x19f0: 0xffffffff
0x19f4: 0xffffffff
0x19f8: 0xffffffff
0x19fc: 0xffffffff
0x1a00: 0xffffffff
0x1a04: 0xffffffff
0x1a08: 0xffffffff
0x1a0c: 0xffffffff
0x1a10: 0xffffffff
0x1a14: 0xffffffff
0x1a18: 0xffffffff
0x1a1c: 0xffffffff
0x1a20: 0xffffffff
0x1a24: 0xffffffff
0x1a28: 0xffffffff
0x1a2c: 0xffffffff
0x1a30: 0xffffffff
0x1a34: 0xffffffff
0x1a38: 0xffffffff
0x1a3c: 0xffffffff
0x1a40: 0xffffffff
0x1a44: 0xffffffff
0x1a48: 0xffffffff
0x1a4c: 0xffffffff
0x1a50: 0xffffffff
0x1a54: 0xffffffff
0x1a58: 0xffffffff
0x1a5c: 0xffffffff
0x1a60: 0xffffffff
0x1a64: 0xffffffff
0x1a68: 0xffffffff
0x1a6c: 0xffffffff
0x1a70: 0xffffffff
0x1a74: 0xffffffff
0x1a78: 0xffffffff
0x1a7c: 0xffffffff
0x1a80: 0xffffffff
0x1a84: 0xffffffff
0x1a88: 0xffffffff
0x1a8c: 0xffffffff
0x1a90: 0xffffffff
0x1a94: 0xffffffff
0x1a98: 0xffffffff
0x1a9c: 0xffffffff
0x1aa0: 0xffffffff
0x1aa4: 0xffffffff
0x1aa8: 0xffffffff
0x1aac: 0xffffffff
0x1ab0: 0xffffffff
0x1ab4: 0xffffffff
0x1ab8: 0xffffffff
0x1abc: 0xffffffff
0x1ac0: 0xffffffff
0x1ac4: 0xffffffff
0x1ac8: 0xffffffff
0x1acc: 0xffffffff
0x1ad0: 0xffffffff
0x1ad4: 0xffffffff
0x1ad8: 0xffffffff
0x1adc: 0xffffffff
0x1ae0: 0xffffffff
0x1ae4: 0xffffffff
0x1ae8: 0xffffffff
0x1aec: 0xffffffff
0x1af0: 0xffffffff
0x1af4: 0xffffffff
0x1af8: 0xffffffff
0x1afc: 0xffffffff
0x1b00: 0xffffffff
0x1b04: 0xffffffff
0x1b08: 0xffffffff
0x1b0c: 0xffffffff
0x1b10: 0xffffffff
0x1b14: 0xffffffff
0x1b18: 0xffffffff
0x1b1c: 0xffffffff
0x1b20: 0xffffffff
0x1b24: 0xffffffff
0x1b28: 0xffffffff
0x1b2c: 0xffffffff
0x1b30: 0xffffffff
0x1b34: 0xffffffff
0x1b38: 0xffffffff
0x1b3c: 0xffffffff
0x1b40: 0xffffffff
0x1b44: 0xffffffff
0x1b48: 0xffffffff
0x1b4c: 0xffffffff
0x1b50: 0xffffffff
0x1b54: 0xffffffff
0x1b58: 0xffffffff
0x1b5c: 0xffffffff
0x1b60: 0xffffffff
0x1b64: 0xffffffff
0x1b68: 0xffffffff
0x1b6c: 0xffffffff
0x1b70: 0xffffffff
0x1b74: 0xffffffff
0x1b78: 0xffffffff
0x1b7c: 0xffffffff
0x1b80: 0xffffffff
0x1b84: 0xffffffff
0x1b88: 0xffffffff
0x1b8c: 0xffffffff
0x1b90: 0xffffffff
0x1b94: 0xffffffff
0x1b98: 0xffffffff
0x1b9c: 0xffffffff
0x1ba0: 0xffffffff
0x1ba4: 0xffffffff
0x1ba8: 0xffffffff
0x1bac: 0xffffffff
0x1bb0: 0xffffffff
0x1bb4: 0xffffffff
0x1bb8: 0xffffffff
0x1bbc: 0xffffffff
0x1bc0: 0xffffffff
0x1bc4: 0xffffffff
0x1bc8: 0xffffffff
0x1bcc: 0xffffffff
0x1bd0: 0xffffffff
0x1bd4: 0xffffffff
0x1bd8: 0xffffffff
0x1bdc: 0xffffffff
0x1be0: 0xffffffff
0x1be4: 0xffffffff
0x1be8: 0xffffffff
0x1bec: 0xffffffff
0x1bf0: 0xffffffff
0x1bf4: 0xffffffff
0x1bf8: 0xffffffff
0x1bfc: 0xffffffff
0x1c00: 0xffffffff
0x1c04: 0xffffffff
0x1c08: 0xffffffff
0x1c0c: 0xffffffff
0x1c10: 0xffffffff
0x1c14: 0xffffffff
0x1c18: 0xffffffff
0x1c1c: 0xffffffff
0x1c20: 0xffffffff
0x1c24: 0xffffffff
0x1c28: 0xffffffff
0x1c2c: 0xffffffff
0x1c30: 0xffffffff
0x1c34: 0xffffffff
0x1c38: 0xffffffff
0x1c3c: 0xffffffff
0x1c40: 0xffffffff
0x1c44: 0xffffffff
0x1c48: 0xffffffff
0x1c4c: 0xffffffff
0x1c50: 0xffffffff
0x1c54: 0xffffffff
0x1c58: 0xffffffff
0x1c5c: 0xffffffff
0x1c60: 0xffffffff
0x1c64: 0xffffffff
0x1c68: 0xffffffff
0x1c6c: 0xffffffff
0x1c70: 0xffffffff
0x1c74: 0xffffffff
0x1c78: 0xffffffff
0x1c7c: 0xffffffff
0x1c80: 0xffffffff
0x1c84: 0xffffffff
0x1c88: 0xffffffff
0x1c8c: 0xffffffff
0x1c90: 0xffffffff
0x1c94: 0xffffffff
0x1c98: 0xffffffff
0x1c9c: 0xffffffff
0x1ca0: 0xffffffff
0x1ca4: 0xffffffff
0x1ca8: 0xffffffff
0x1cac: 0xffffffff
0x1cb0: 0xffffffff
0x1cb4: 0xffffffff
0x1cb8: 0xffffffff
0x1cbc: 0xffffffff
0x1cc0: 0xffffffff
0x1cc4: 0xffffffff
0x1cc8: 0xffffffff
0x1ccc: 0xffffffff
0x1cd0: 0xffffffff
0x1cd4: 0xffffffff
0x1cd8: 0xffffffff
0x1cdc: 0xffffffff
0x1ce0: 0xffffffff
0x1ce4: 0xffffffff
0x1ce8: 0xffffffff
0x1cec: 0xffffffff
0x1cf0: 0xffffffff
0x1cf4: 0xffffffff
0x1cf8: 0xffffffff
0x1cfc: 0xffffffff
0x1d00: 0xffffffff
0x1d04: 0xffffffff
0x1d08: 0xffffffff
0x1d0c: 0xffffffff
0x1d10: 0xffffffff
0x1d14: 0xffffffff
0x1d18: 0xffffffff
0x1d1c: 0xffffffff
0x1d20: 0xffffffff
0x1d24: 0xffffffff
0x1d28: 0xffffffff
0x1d2c: 0xffffffff
0x1d30: 0xffffffff
0x1d34: 0xffffffff
0x1d38: 0xffffffff
0x1d3c: 0xffffffff
0x1d40: 0xffffffff
0x1d44: 0xffffffff
0x1d48: 0xffffffff
0x1d4c: 0xffffffff
0x1d50: 0xffffffff
0x1d54: 0xffffffff
0x1d58: 0xffffffff
0x1d5c: 0xffffffff
0x1d60: 0xffffffff
0x1d64: 0xffffffff
0x1d68: 0xffffffff
0x1d6c: 0xffffffff
0x1d70: 0xffffffff
0x1d74: 0xffffffff
0x1d78: 0xffffffff
0x1d7c: 0xffffffff
0x1d80: 0xffffffff
0x1d84: 0xffffffff
0x1d88: 0xffffffff
0x1d8c: 0xffffffff
0x1d90: 0xffffffff
0x1d94: 0xffffffff
0x1d98: 0xffffffff
0x1d9c: 0xffffffff
0x1da0: 0xffffffff
0x1da4: 0xffffffff
0x1da8: 0xffffffff
0x1dac: 0xffffffff
0x1db0: 0xffffffff
0x1db4: 0xffffffff
0x1db8: 0xffffffff
0x1dbc: 0xffffffff
0x1dc0: 0xffffffff
0x1dc4: 0xffffffff
0x1dc8: 0xffffffff
0x1dcc: 0xffffffff
0x1dd0: 0xffffffff
0x1dd4: 0xffffffff
0x1dd8: 0xffffffff
0x1ddc: 0xffffffff
0x1de0: 0xffffffff
0x1de4: 0xffffffff
0x1de8: 0xffffffff
0x1dec: 0xffffffff
0x1df0: 0xffffffff
0x1df4: 0xffffffff
0x1df8: 0xffffffff
0x1dfc: 0xffffffff
0x1e00: 0xffffffff
0x1e04: 0xffffffff
0x1e08: 0xffffffff
0x1e0c: 0xffffffff
0x1e10: 0xffffffff
0x1e14: 0xffffffff
0x1e18: 0xffffffff
0x1e1c: 0xffffffff
0x1e20: 0xffffffff
0x1e24: 0xffffffff
0x1e28: 0xffffffff
0x1e2c: 0xffffffff
0x1e30: 0xffffffff
0x1e34: 0xffffffff
0x1e38: 0xffffffff
0x1e3c: 0xffffffff
0x1e40: 0xffffffff
0x1e44: 0xffffffff
0x1e48: 0xffffffff
0x1e4c: 0xffffffff
0x1e50: 0xffffffff
0x1e54: 0xffffffff
0x1e58: 0xffffffff
0x1e5c: 0xffffffff
0x1e60: 0xffffffff
0x1e64: 0xffffffff
0x1e68: 0xffffffff
0x1e6c: 0xffffffff
0x1e70: 0xffffffff
0x1e74: 0xffffffff
0x1e78: 0xffffffff
0x1e7c: 0xffffffff
0x1e80: 0xffffffff
0x1e84: 0xffffffff
0x1e88: 0xffffffff
0x1e8c: 0xffffffff
0x1e90: 0xffffffff
0x1e94: 0xffffffff
0x1e98: 0xffffffff
0x1e9c: 0xffffffff
0x1ea0: 0xffffffff
0x1ea4: 0xffffffff
0x1ea8: 0xffffffff
0x1eac: 0xffffffff
0x1eb0: 0xffffffff
0x1eb4: 0xffffffff
0x1eb8: 0xffffffff
0x1ebc: 0xffffffff
0x1ec0: 0xffffffff
0x1ec4: 0xffffffff
0x1ec8: 0xffffffff
0x1ecc: 0xffffffff
0x1ed0: 0xffffffff
0x1ed4: 0xffffffff
0x1ed8: 0xffffffff
0x1edc: 0xffffffff
0x1ee0: 0xffffffff
0x1ee4: 0xffffffff
0x1ee8: 0xffffffff
0x1eec: 0xffffffff
0x1ef0: 0xffffffff
0x1ef4: 0xffffffff
0x1ef8: 0xffffffff
0x1efc: 0xffffffff
0x1f00: 0xffffffff
0x1f04: 0xffffffff
0x1f08: 0xffffffff
0x1f0c: 0xffffffff
0x1f10: 0xffffffff
0x1f14: 0xffffffff
0x1f18: 0xffffffff
0x1f1c: 0xffffffff
0x1f20: 0xffffffff
0x1f24: 0xffffffff
0x1f28: 0xffffffff
0x1f2c: 0xffffffff
0x1f30: 0xffffffff
0x1f34: 0xffffffff
0x1f38: 0xffffffff
0x1f3c: 0xffffffff
0x1f40: 0xffffffff
0x1f44: 0xffffffff
0x1f48: 0xffffffff
0x1f4c: 0xffffffff
0x1f50: 0xffffffff
0x1f54: 0xffffffff
0x1f58: 0xffffffff
0x1f5c: 0xffffffff
0x1f60: 0xffffffff
0x1f64: 0xffffffff
0x1f68: 0xffffffff
0x1f6c: 0xffffffff
0x1f70: 0xffffffff
0x1f74: 0xffffffff
0x1f78: 0xffffffff
0x1f7c: 0xffffffff
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0x1f84: 0xffffffff
0x1f88: 0xffffffff
0x1f8c: 0xffffffff
0x1f90: 0xffffffff
0x1f94: 0xffffffff
0x1f98: 0xffffffff
0x1f9c: 0xffffffff
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0x1fac: 0xffffffff
0x1fb0: 0xffffffff
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0x1fbc: 0xffffffff
0x1fc0: 0xffffffff
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0x1fc8: 0xffffffff
0x1fcc: 0xffffffff
0x1fd0: 0xffffffff
0x1fd4: 0xffffffff
0x1fd8: 0xffffffff
0x1fdc: 0xffffffff
0x1fe0: 0xffffffff
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0x1fec: 0xffffffff
0x1ff0: 0xffffffff
0x1ff4: 0xffffffff
0x1ff8: 0xffffffff
0x1ffc: 0xffffffff
0x2000: 0xffffffff
0x2004: 0xffffffff
0x2008: 0xffffffff
0x200c: 0xffffffff
0x2010: 0xffffffff
0x2014: 0xffffffff
0x2018: 0xffffffff
0x201c: 0xffffffff
0x2020: 0xffffffff
0x2024: 0xffffffff
0x2028: 0xffffffff
0x202c: 0xffffffff
0x2030: 0xffffffff
0x2034: 0xffffffff
0x2038: 0xffffffff
0x203c: 0xffffffff
0x2040: 0xffffffff
0x2044: 0xffffffff
0x2048: 0xffffffff
0x204c: 0xffffffff
0x2050: 0xffffffff
0x2054: 0xffffffff
0x2058: 0xffffffff
0x205c: 0xffffffff
0x2060: 0xffffffff
0x2064: 0xffffffff
0x2068: 0xffffffff
0x206c: 0xffffffff
0x2070: 0xffffffff
0x2074: 0xffffffff
0x2078: 0xffffffff
0x207c: 0xffffffff
0x2080: 0xffffffff
0x2084: 0xffffffff
0x2088: 0xffffffff
0x208c: 0xffffffff
0x2090: 0xffffffff
0x2094: 0xffffffff
0x2098: 0xffffffff
0x209c: 0xffffffff
0x20a0: 0xffffffff
0x20a4: 0xffffffff
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0x20c0: 0xffffffff
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0x20cc: 0xffffffff
0x20d0: 0xffffffff
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0x20dc: 0xffffffff
0x20e0: 0xffffffff
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0x20ec: 0xffffffff
0x20f0: 0xffffffff
0x20f4: 0xffffffff
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0x20fc: 0xffffffff
0x2100: 0xffffffff
0x2104: 0xffffffff
0x2108: 0xffffffff
0x210c: 0xffffffff
0x2110: 0xffffffff
0x2114: 0xffffffff
0x2118: 0xffffffff
0x211c: 0xffffffff
0x2120: 0xffffffff
0x2124: 0xffffffff
0x2128: 0xffffffff
0x212c: 0xffffffff
0x2130: 0xffffffff
0x2134: 0xffffffff
0x2138: 0xffffffff
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0x2140: 0xffffffff
0x2144: 0xffffffff
0x2148: 0xffffffff
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0x2150: 0xffffffff
0x2154: 0xffffffff
0x2158: 0xffffffff
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0x2160: 0xffffffff
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0x2168: 0xffffffff
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0x2170: 0xffffffff
0x2174: 0xffffffff
0x2178: 0xffffffff
0x217c: 0xffffffff
0x2180: 0xffffffff
0x2184: 0xffffffff
0x2188: 0xffffffff
0x218c: 0xffffffff
0x2190: 0xffffffff
0x2194: 0xffffffff
0x2198: 0xffffffff
0x219c: 0xffffffff
0x21a0: 0xffffffff
0x21a4: 0xffffffff
0x21a8: 0xffffffff
0x21ac: 0xffffffff
0x21b0: 0xffffffff
0x21b4: 0xffffffff
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0x21bc: 0xffffffff
0x21c0: 0xffffffff
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0x21cc: 0xffffffff
0x21d0: 0xffffffff
0x21d4: 0xffffffff
0x21d8: 0xffffffff
0x21dc: 0xffffffff
0x21e0: 0xffffffff
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0x21ec: 0xffffffff
0x21f0: 0xffffffff
0x21f4: 0xffffffff
0x21f8: 0xffffffff
0x21fc: 0xffffffff
0x2200: 0xffffffff
0x2204: 0xffffffff
0x2208: 0xffffffff
0x220c: 0xffffffff
0x2210: 0xffffffff
0x2214: 0xffffffff
0x2218: 0xffffffff
0x221c: 0xffffffff
0x2220: 0xffffffff
0x2224: 0xffffffff
0x2228: 0xffffffff
0x222c: 0xffffffff
0x2230: 0xffffffff
0x2234: 0xffffffff
0x2238: 0xffffffff
0x223c: 0xffffffff
0x2240: 0xffffffff
0x2244: 0xffffffff
0x2248: 0xffffffff
0x224c: 0xffffffff
0x2250: 0xffffffff
0x2254: 0xffffffff
0x2258: 0xffffffff
0x225c: 0xffffffff
0x2260: 0xffffffff
0x2264: 0xffffffff
0x2268: 0xffffffff
0x226c: 0xffffffff
0x2270: 0xffffffff
0x2274: 0xffffffff
0x2278: 0xffffffff
0x227c: 0xffffffff
0x2280: 0xffffffff
0x2284: 0xffffffff
0x2288: 0xffffffff
0x228c: 0xffffffff
0x2290: 0xffffffff
0x2294: 0xffffffff
0x2298: 0xffffffff
0x229c: 0xffffffff
0x22a0: 0xffffffff
0x22a4: 0xffffffff
0x22a8: 0xffffffff
0x22ac: 0xffffffff
0x22b0: 0xffffffff
0x22b4: 0xffffffff
0x22b8: 0xffffffff
0x22bc: 0xffffffff
0x22c0: 0xffffffff
0x22c4: 0xffffffff
0x22c8: 0xffffffff
0x22cc: 0xffffffff
0x22d0: 0xffffffff
0x22d4: 0xffffffff
0x22d8: 0xffffffff
0x22dc: 0xffffffff
0x22e0: 0xffffffff
0x22e4: 0xffffffff
0x22e8: 0xffffffff
0x22ec: 0xffffffff
0x22f0: 0xffffffff
0x22f4: 0xffffffff
0x22f8: 0xffffffff
0x22fc: 0xffffffff
0x2300: 0xffffffff
0x2304: 0xffffffff
0x2308: 0xffffffff
0x230c: 0xffffffff
0x2310: 0xffffffff
0x2314: 0xffffffff
0x2318: 0xffffffff
0x231c: 0xffffffff
0x2320: 0xffffffff
0x2324: 0xffffffff
0x2328: 0xffffffff
0x232c: 0xffffffff
0x2330: 0xffffffff
0x2334: 0xffffffff
0x2338: 0xffffffff
0x233c: 0xffffffff
0x2340: 0xffffffff
0x2344: 0xffffffff
0x2348: 0xffffffff
0x234c: 0xffffffff
0x2350: 0xffffffff
0x2354: 0xffffffff
0x2358: 0xffffffff
0x235c: 0xffffffff
0x2360: 0xffffffff
0x2364: 0xffffffff
0x2368: 0xffffffff
0x236c: 0xffffffff
0x2370: 0xffffffff
0x2374: 0xffffffff
0x2378: 0xffffffff
0x237c: 0xffffffff
0x2380: 0xffffffff
0x2384: 0xffffffff
0x2388: 0xffffffff
0x238c: 0xffffffff
0x2390: 0xffffffff
0x2394: 0xffffffff
0x2398: 0xffffffff
0x239c: 0xffffffff
0x23a0: 0xffffffff
0x23a4: 0xffffffff
0x23a8: 0xffffffff
0x23ac: 0xffffffff
0x23b0: 0xffffffff
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0x23b8: 0xffffffff
0x23bc: 0xffffffff
0x23c0: 0xffffffff
0x23c4: 0xffffffff
0x23c8: 0xffffffff
0x23cc: 0xffffffff
0x23d0: 0xffffffff
0x23d4: 0xffffffff
0x23d8: 0xffffffff
0x23dc: 0xffffffff
0x23e0: 0xffffffff
0x23e4: 0xffffffff
0x23e8: 0xffffffff
0x23ec: 0xffffffff
0x23f0: 0xffffffff
0x23f4: 0xffffffff
0x23f8: 0xffffffff
0x23fc: 0xffffffff
0x2400: 0xffffffff
0x2404: 0xffffffff
0x2408: 0xffffffff
0x240c: 0xffffffff
0x2410: 0xffffffff
0x2414: 0xffffffff
0x2418: 0xffffffff
0x241c: 0xffffffff
0x2420: 0xffffffff
0x2424: 0xffffffff
0x2428: 0xffffffff
0x242c: 0xffffffff
0x2430: 0xffffffff
0x2434: 0xffffffff
0x2438: 0xffffffff
0x243c: 0xffffffff
0x2440: 0xffffffff
0x2444: 0xffffffff
0x2448: 0xffffffff
0x244c: 0xffffffff
0x2450: 0xffffffff
0x2454: 0xffffffff
0x2458: 0xffffffff
0x245c: 0xffffffff
0x2460: 0xffffffff
0x2464: 0xffffffff
0x2468: 0xffffffff
0x246c: 0xffffffff
0x2470: 0xffffffff
0x2474: 0xffffffff
0x2478: 0xffffffff
0x247c: 0xffffffff
0x2480: 0xffffffff
0x2484: 0xffffffff
0x2488: 0xffffffff
0x248c: 0xffffffff
0x2490: 0xffffffff
0x2494: 0xffffffff
0x2498: 0xffffffff
0x249c: 0xffffffff
0x24a0: 0xffffffff
0x24a4: 0xffffffff
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0x24ac: 0xffffffff
0x24b0: 0xffffffff
0x24b4: 0xffffffff
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0x24bc: 0xffffffff
0x24c0: 0xffffffff
0x24c4: 0xffffffff
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0x24cc: 0xffffffff
0x24d0: 0xffffffff
0x24d4: 0xffffffff
0x24d8: 0xffffffff
0x24dc: 0xffffffff
0x24e0: 0xffffffff
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0x24e8: 0xffffffff
0x24ec: 0xffffffff
0x24f0: 0xffffffff
0x24f4: 0xffffffff
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0x24fc: 0xffffffff
0x2500: 0xffffffff
0x2504: 0xffffffff
0x2508: 0xffffffff
0x250c: 0xffffffff
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0x2518: 0xffffffff
0x251c: 0xffffffff
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0x2524: 0xffffffff
0x2528: 0xffffffff
0x252c: 0xffffffff
0x2530: 0xffffffff
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0x253c: 0xffffffff
0x2540: 0xffffffff
0x2544: 0xffffffff
0x2548: 0xffffffff
0x254c: 0xffffffff
0x2550: 0xffffffff
0x2554: 0xffffffff
0x2558: 0xffffffff
0x255c: 0xffffffff
0x2560: 0xffffffff
0x2564: 0xffffffff
0x2568: 0xffffffff
0x256c: 0xffffffff
0x2570: 0xffffffff
0x2574: 0xffffffff
0x2578: 0xffffffff
0x257c: 0xffffffff
0x2580: 0xffffffff
0x2584: 0xffffffff
0x2588: 0xffffffff
0x258c: 0xffffffff
0x2590: 0xffffffff
0x2594: 0xffffffff
0x2598: 0xffffffff
0x259c: 0xffffffff
0x25a0: 0xffffffff
0x25a4: 0xffffffff
0x25a8: 0xffffffff
0x25ac: 0xffffffff
0x25b0: 0xffffffff
0x25b4: 0xffffffff
0x25b8: 0xffffffff
0x25bc: 0xffffffff
0x25c0: 0xffffffff
0x25c4: 0xffffffff
0x25c8: 0xffffffff
0x25cc: 0xffffffff
0x25d0: 0xffffffff
0x25d4: 0xffffffff
0x25d8: 0xffffffff
0x25dc: 0xffffffff
0x25e0: 0xffffffff
0x25e4: 0xffffffff
0x25e8: 0xffffffff
0x25ec: 0xffffffff
0x25f0: 0xffffffff
0x25f4: 0xffffffff
0x25f8: 0xffffffff
0x25fc: 0xffffffff
0x2600: 0xffffffff
0x2604: 0xffffffff
0x2608: 0xffffffff
0x260c: 0xffffffff
0x2610: 0xffffffff
0x2614: 0xffffffff
0x2618: 0xffffffff
0x261c: 0xffffffff
0x2620: 0xffffffff
0x2624: 0xffffffff
0x2628: 0xffffffff
0x262c: 0xffffffff
0x2630: 0xffffffff
0x2634: 0xffffffff
0x2638: 0xffffffff
0x263c: 0xffffffff
0x2640: 0xffffffff
0x2644: 0xffffffff
0x2648: 0xffffffff
0x264c: 0xffffffff
0x2650: 0xffffffff
0x2654: 0xffffffff
0x2658: 0xffffffff
0x265c: 0xffffffff
0x2660: 0xffffffff
0x2664: 0xffffffff
0x2668: 0xffffffff
0x266c: 0xffffffff
0x2670: 0xffffffff
0x2674: 0xffffffff
0x2678: 0xffffffff
0x267c: 0xffffffff
0x2680: 0xffffffff
0x2684: 0xffffffff
0x2688: 0xffffffff
0x268c: 0xffffffff
0x2690: 0xffffffff
0x2694: 0xffffffff
0x2698: 0xffffffff
0x269c: 0xffffffff
0x26a0: 0xffffffff
0x26a4: 0xffffffff
0x26a8: 0xffffffff
0x26ac: 0xffffffff
0x26b0: 0xffffffff
0x26b4: 0xffffffff
0x26b8: 0xffffffff
0x26bc: 0xffffffff
0x26c0: 0xffffffff
0x26c4: 0xffffffff
0x26c8: 0xffffffff
0x26cc: 0xffffffff
0x26d0: 0xffffffff
0x26d4: 0xffffffff
0x26d8: 0xffffffff
0x26dc: 0xffffffff
0x26e0: 0xffffffff
0x26e4: 0xffffffff
0x26e8: 0xffffffff
0x26ec: 0xffffffff
0x26f0: 0xffffffff
0x26f4: 0xffffffff
0x26f8: 0xffffffff
0x26fc: 0xffffffff
0x2700: 0xffffffff
0x2704: 0xffffffff
0x2708: 0xffffffff
0x270c: 0xffffffff
0x2710: 0xffffffff
0x2714: 0xffffffff
0x2718: 0xffffffff
0x271c: 0xffffffff
0x2720: 0xffffffff
0x2724: 0xffffffff
0x2728: 0xffffffff
0x272c: 0xffffffff
0x2730: 0xffffffff
0x2734: 0xffffffff
0x2738: 0xffffffff
0x273c: 0xffffffff
0x2740: 0xffffffff
0x2744: 0xffffffff
0x2748: 0xffffffff
0x274c: 0xffffffff
0x2750: 0xffffffff
0x2754: 0xffffffff
0x2758: 0xffffffff
0x275c: 0xffffffff
0x2760: 0xffffffff
0x2764: 0xffffffff
0x2768: 0xffffffff
0x276c: 0xffffffff
0x2770: 0xffffffff
0x2774: 0xffffffff
0x2778: 0xffffffff
0x277c: 0xffffffff
0x2780: 0xffffffff
0x2784: 0xffffffff
0x2788: 0xffffffff
0x278c: 0xffffffff
0x2790: 0xffffffff
0x2794: 0xffffffff
0x2798: 0xffffffff
0x279c: 0xffffffff
0x27a0: 0xffffffff
0x27a4: 0xffffffff
0x27a8: 0xffffffff
0x27ac: 0xffffffff
0x27b0: 0xffffffff
0x27b4: 0xffffffff
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0x27bc: 0xffffffff
0x27c0: 0xffffffff
0x27c4: 0xffffffff
0x27c8: 0xffffffff
0x27cc: 0xffffffff
0x27d0: 0xffffffff
0x27d4: 0xffffffff
0x27d8: 0xffffffff
0x27dc: 0xffffffff
0x27e0: 0xffffffff
0x27e4: 0xffffffff
0x27e8: 0xffffffff
0x27ec: 0xffffffff
0x27f0: 0xffffffff
0x27f4: 0xffffffff
0x27f8: 0xffffffff
0x27fc: 0xffffffff
0x2800: 0xffffffff
0x2804: 0xffffffff
0x2808: 0xffffffff
0x280c: 0xffffffff
0x2810: 0xffffffff
0x2814: 0xffffffff
0x2818: 0xffffffff
0x281c: 0xffffffff
0x2820: 0xffffffff
0x2824: 0xffffffff
0x2828: 0xffffffff
0x282c: 0xffffffff
0x2830: 0xffffffff
0x2834: 0xffffffff
0x2838: 0xffffffff
0x283c: 0xffffffff
0x2840: 0xffffffff
0x2844: 0xffffffff
0x2848: 0xffffffff
0x284c: 0xffffffff
0x2850: 0xffffffff
0x2854: 0xffffffff
0x2858: 0xffffffff
0x285c: 0xffffffff
0x2860: 0xffffffff
0x2864: 0xffffffff
0x2868: 0xffffffff
0x286c: 0xffffffff
0x2870: 0xffffffff
0x2874: 0xffffffff
0x2878: 0xffffffff
0x287c: 0xffffffff
0x2880: 0xffffffff
0x2884: 0xffffffff
0x2888: 0xffffffff
0x288c: 0xffffffff
0x2890: 0xffffffff
0x2894: 0xffffffff
0x2898: 0xffffffff
0x289c: 0xffffffff
0x28a0: 0xffffffff
0x28a4: 0xffffffff
0x28a8: 0xffffffff
0x28ac: 0xffffffff
0x28b0: 0xffffffff
0x28b4: 0xffffffff
0x28b8: 0xffffffff
0x28bc: 0xffffffff
0x28c0: 0xffffffff
0x28c4: 0xffffffff
0x28c8: 0xffffffff
0x28cc: 0xffffffff
0x28d0: 0xffffffff
0x28d4: 0xffffffff
0x28d8: 0xffffffff
0x28dc: 0xffffffff
0x28e0: 0xffffffff
0x28e4: 0xffffffff
0x28e8: 0xffffffff
0x28ec: 0xffffffff
0x28f0: 0xffffffff
0x28f4: 0xffffffff
0x28f8: 0xffffffff
0x28fc: 0xffffffff
0x2900: 0xffffffff
0x2904: 0xffffffff
0x2908: 0xffffffff
0x290c: 0xffffffff
0x2910: 0xffffffff
0x2914: 0xffffffff
0x2918: 0xffffffff
0x291c: 0xffffffff
0x2920: 0xffffffff
0x2924: 0xffffffff
0x2928: 0xffffffff
0x292c: 0xffffffff
0x2930: 0xffffffff
0x2934: 0xffffffff
0x2938: 0xffffffff
0x293c: 0xffffffff
0x2940: 0xffffffff
0x2944: 0xffffffff
0x2948: 0xffffffff
0x294c: 0xffffffff
0x2950: 0xffffffff
0x2954: 0xffffffff
0x2958: 0xffffffff
0x295c: 0xffffffff
0x2960: 0xffffffff
0x2964: 0xffffffff
0x2968: 0xffffffff
0x296c: 0xffffffff
0x2970: 0xffffffff
0x2974: 0xffffffff
0x2978: 0xffffffff
0x297c: 0xffffffff
0x2980: 0xffffffff
0x2984: 0xffffffff
0x2988: 0xffffffff
0x298c: 0xffffffff
0x2990: 0xffffffff
0x2994: 0xffffffff
0x2998: 0xffffffff
0x299c: 0xffffffff
0x29a0: 0xffffffff
0x29a4: 0xffffffff
0x29a8: 0xffffffff
0x29ac: 0xffffffff
0x29b0: 0xffffffff
0x29b4: 0xffffffff
0x29b8: 0xffffffff
0x29bc: 0xffffffff
0x29c0: 0xffffffff
0x29c4: 0xffffffff
0x29c8: 0xffffffff
0x29cc: 0xffffffff
0x29d0: 0xffffffff
0x29d4: 0xffffffff
0x29d8: 0xffffffff
0x29dc: 0xffffffff
0x29e0: 0xffffffff
0x29e4: 0xffffffff
0x29e8: 0xffffffff
0x29ec: 0xffffffff
0x29f0: 0xffffffff
0x29f4: 0xffffffff
0x29f8: 0xffffffff
0x29fc: 0xffffffff
0x2a00: 0xffffffff
0x2a04: 0xffffffff
0x2a08: 0xffffffff
0x2a0c: 0xffffffff
0x2a10: 0xffffffff
0x2a14: 0xffffffff
0x2a18: 0xffffffff
0x2a1c: 0xffffffff
0x2a20: 0xffffffff
0x2a24: 0xffffffff
0x2a28: 0xffffffff
0x2a2c: 0xffffffff
0x2a30: 0xffffffff
0x2a34: 0xffffffff
0x2a38: 0xffffffff
0x2a3c: 0xffffffff
0x2a40: 0xffffffff
0x2a44: 0xffffffff
0x2a48: 0xffffffff
0x2a4c: 0xffffffff
0x2a50: 0xffffffff
0x2a54: 0xffffffff
0x2a58: 0xffffffff
0x2a5c: 0xffffffff
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0x2a64: 0xffffffff
0x2a68: 0xffffffff
0x2a6c: 0xffffffff
0x2a70: 0xffffffff
0x2a74: 0xffffffff
0x2a78: 0xffffffff
0x2a7c: 0xffffffff
0x2a80: 0xffffffff
0x2a84: 0xffffffff
0x2a88: 0xffffffff
0x2a8c: 0xffffffff
0x2a90: 0xffffffff
0x2a94: 0xffffffff
0x2a98: 0xffffffff
0x2a9c: 0xffffffff
0x2aa0: 0xffffffff
0x2aa4: 0xffffffff
0x2aa8: 0xffffffff
0x2aac: 0xffffffff
0x2ab0: 0xffffffff
0x2ab4: 0xffffffff
0x2ab8: 0xffffffff
0x2abc: 0xffffffff
0x2ac0: 0xffffffff
0x2ac4: 0xffffffff
0x2ac8: 0xffffffff
0x2acc: 0xffffffff
0x2ad0: 0xffffffff
0x2ad4: 0xffffffff
0x2ad8: 0xffffffff
0x2adc: 0xffffffff
0x2ae0: 0xffffffff
0x2ae4: 0xffffffff
0x2ae8: 0xffffffff
0x2aec: 0xffffffff
0x2af0: 0xffffffff
0x2af4: 0xffffffff
0x2af8: 0xffffffff
0x2afc: 0xffffffff
0x2b00: 0xffffffff
0x2b04: 0xffffffff
0x2b08: 0xffffffff
0x2b0c: 0xffffffff
0x2b10: 0xffffffff
0x2b14: 0xffffffff
0x2b18: 0xffffffff
0x2b1c: 0xffffffff
0x2b20: 0xffffffff
0x2b24: 0xffffffff
0x2b28: 0xffffffff
0x2b2c: 0xffffffff
0x2b30: 0xffffffff
0x2b34: 0xffffffff
0x2b38: 0xffffffff
0x2b3c: 0xffffffff
0x2b40: 0xffffffff
0x2b44: 0xffffffff
0x2b48: 0xffffffff
0x2b4c: 0xffffffff
0x2b50: 0xffffffff
0x2b54: 0xffffffff
0x2b58: 0xffffffff
0x2b5c: 0xffffffff
0x2b60: 0xffffffff
0x2b64: 0xffffffff
0x2b68: 0xffffffff
0x2b6c: 0xffffffff
0x2b70: 0xffffffff
0x2b74: 0xffffffff
0x2b78: 0xffffffff
0x2b7c: 0xffffffff
0x2b80: 0xffffffff
0x2b84: 0xffffffff
0x2b88: 0xffffffff
0x2b8c: 0xffffffff
0x2b90: 0xffffffff
0x2b94: 0xffffffff
0x2b98: 0xffffffff
0x2b9c: 0xffffffff
0x2ba0: 0xffffffff
0x2ba4: 0xffffffff
0x2ba8: 0xffffffff
0x2bac: 0xffffffff
0x2bb0: 0xffffffff
0x2bb4: 0xffffffff
0x2bb8: 0xffffffff
0x2bbc: 0xffffffff
0x2bc0: 0xffffffff
0x2bc4: 0xffffffff
0x2bc8: 0xffffffff
0x2bcc: 0xffffffff
0x2bd0: 0xffffffff
0x2bd4: 0xffffffff
0x2bd8: 0xffffffff
0x2bdc: 0xffffffff
0x2be0: 0xffffffff
0x2be4: 0xffffffff
0x2be8: 0xffffffff
0x2bec: 0xffffffff
0x2bf0: 0xffffffff
0x2bf4: 0xffffffff
0x2bf8: 0xffffffff
0x2bfc: 0xffffffff
0x2c00: 0xffffffff
0x2c04: 0xffffffff
0x2c08: 0xffffffff
0x2c0c: 0xffffffff
0x2c10: 0xffffffff
0x2c14: 0xffffffff
0x2c18: 0xffffffff
0x2c1c: 0xffffffff
0x2c20: 0xffffffff
0x2c24: 0xffffffff
0x2c28: 0xffffffff
0x2c2c: 0xffffffff
0x2c30: 0xffffffff
0x2c34: 0xffffffff
0x2c38: 0xffffffff
0x2c3c: 0xffffffff
0x2c40: 0xffffffff
0x2c44: 0xffffffff
0x2c48: 0xffffffff
0x2c4c: 0xffffffff
0x2c50: 0xffffffff
0x2c54: 0xffffffff
0x2c58: 0xffffffff
0x2c5c: 0xffffffff
0x2c60: 0xffffffff
0x2c64: 0xffffffff
0x2c68: 0xffffffff
0x2c6c: 0xffffffff
0x2c70: 0xffffffff
0x2c74: 0xffffffff
0x2c78: 0xffffffff
0x2c7c: 0xffffffff
0x2c80: 0xffffffff
0x2c84: 0xffffffff
0x2c88: 0xffffffff
0x2c8c: 0xffffffff
0x2c90: 0xffffffff
0x2c94: 0xffffffff
0x2c98: 0xffffffff
0x2c9c: 0xffffffff
0x2ca0: 0xffffffff
0x2ca4: 0xffffffff
0x2ca8: 0xffffffff
0x2cac: 0xffffffff
0x2cb0: 0xffffffff
0x2cb4: 0xffffffff
0x2cb8: 0xffffffff
0x2cbc: 0xffffffff
0x2cc0: 0xffffffff
0x2cc4: 0xffffffff
0x2cc8: 0xffffffff
0x2ccc: 0xffffffff
0x2cd0: 0xffffffff
0x2cd4: 0xffffffff
0x2cd8: 0xffffffff
0x2cdc: 0xffffffff
0x2ce0: 0xffffffff
0x2ce4: 0xffffffff
0x2ce8: 0xffffffff
0x2cec: 0xffffffff
0x2cf0: 0xffffffff
0x2cf4: 0xffffffff
0x2cf8: 0xffffffff
0x2cfc: 0xffffffff
0x2d00: 0xffffffff
0x2d04: 0xffffffff
0x2d08: 0xffffffff
0x2d0c: 0xffffffff
0x2d10: 0xffffffff
0x2d14: 0xffffffff
0x2d18: 0xffffffff
0x2d1c: 0xffffffff
0x2d20: 0xffffffff
0x2d24: 0xffffffff
0x2d28: 0xffffffff
0x2d2c: 0xffffffff
0x2d30: 0xffffffff
0x2d34: 0xffffffff
0x2d38: 0xffffffff
0x2d3c: 0xffffffff
0x2d40: 0xffffffff
0x2d44: 0xffffffff
0x2d48: 0xffffffff
0x2d4c: 0xffffffff
0x2d50: 0xffffffff
0x2d54: 0xffffffff
0x2d58: 0xffffffff
0x2d5c: 0xffffffff
0x2d60: 0xffffffff
0x2d64: 0xffffffff
0x2d68: 0xffffffff
0x2d6c: 0xffffffff
0x2d70: 0xffffffff
0x2d74: 0xffffffff
0x2d78: 0xffffffff
0x2d7c: 0xffffffff
0x2d80: 0xffffffff
0x2d84: 0xffffffff
0x2d88: 0xffffffff
0x2d8c: 0xffffffff
0x2d90: 0xffffffff
0x2d94: 0xffffffff
0x2d98: 0xffffffff
0x2d9c: 0xffffffff
0x2da0: 0xffffffff
0x2da4: 0xffffffff
0x2da8: 0xffffffff
0x2dac: 0xffffffff
0x2db0: 0xffffffff
0x2db4: 0xffffffff
0x2db8: 0xffffffff
0x2dbc: 0xffffffff
0x2dc0: 0xffffffff
0x2dc4: 0xffffffff
0x2dc8: 0xffffffff
0x2dcc: 0xffffffff
0x2dd0: 0xffffffff
0x2dd4: 0xffffffff
0x2dd8: 0xffffffff
0x2ddc: 0xffffffff
0x2de0: 0xffffffff
0x2de4: 0xffffffff
0x2de8: 0xffffffff
0x2dec: 0xffffffff
0x2df0: 0xffffffff
0x2df4: 0xffffffff
0x2df8: 0xffffffff
0x2dfc: 0xffffffff
0x2e00: 0xffffffff
0x2e04: 0xffffffff
0x2e08: 0xffffffff
0x2e0c: 0xffffffff
0x2e10: 0xffffffff
0x2e14: 0xffffffff
0x2e18: 0xffffffff
0x2e1c: 0xffffffff
0x2e20: 0xffffffff
0x2e24: 0xffffffff
0x2e28: 0xffffffff
0x2e2c: 0xffffffff
0x2e30: 0xffffffff
0x2e34: 0xffffffff
0x2e38: 0xffffffff
0x2e3c: 0xffffffff
0x2e40: 0xffffffff
0x2e44: 0xffffffff
0x2e48: 0xffffffff
0x2e4c: 0xffffffff
0x2e50: 0xffffffff
0x2e54: 0xffffffff
0x2e58: 0xffffffff
0x2e5c: 0xffffffff
0x2e60: 0xffffffff
0x2e64: 0xffffffff
0x2e68: 0xffffffff
0x2e6c: 0xffffffff
0x2e70: 0xffffffff
0x2e74: 0xffffffff
0x2e78: 0xffffffff
0x2e7c: 0xffffffff
0x2e80: 0xffffffff
0x2e84: 0xffffffff
0x2e88: 0xffffffff
0x2e8c: 0xffffffff
0x2e90: 0xffffffff
0x2e94: 0xffffffff
0x2e98: 0xffffffff
0x2e9c: 0xffffffff
0x2ea0: 0xffffffff
0x2ea4: 0xffffffff
0x2ea8: 0xffffffff
0x2eac: 0xffffffff
0x2eb0: 0xffffffff
0x2eb4: 0xffffffff
0x2eb8: 0xffffffff
0x2ebc: 0xffffffff
0x2ec0: 0xffffffff
0x2ec4: 0xffffffff
0x2ec8: 0xffffffff
0x2ecc: 0xffffffff
0x2ed0: 0xffffffff
0x2ed4: 0xffffffff
0x2ed8: 0xffffffff
0x2edc: 0xffffffff
0x2ee0: 0xffffffff
0x2ee4: 0xffffffff
0x2ee8: 0xffffffff
0x2eec: 0xffffffff
0x2ef0: 0xffffffff
0x2ef4: 0xffffffff
0x2ef8: 0xffffffff
0x2efc: 0xffffffff
0x2f00: 0xffffffff
0x2f04: 0xffffffff
0x2f08: 0xffffffff
0x2f0c: 0xffffffff
0x2f10: 0xffffffff
0x2f14: 0xffffffff
0x2f18: 0xffffffff
0x2f1c: 0xffffffff
0x2f20: 0xffffffff
0x2f24: 0xffffffff
0x2f28: 0xffffffff
0x2f2c: 0xffffffff
0x2f30: 0xffffffff
0x2f34: 0xffffffff
0x2f38: 0xffffffff
0x2f3c: 0xffffffff
0x2f40: 0xffffffff
0x2f44: 0xffffffff
0x2f48: 0xffffffff
0x2f4c: 0xffffffff
0x2f50: 0xffffffff
0x2f54: 0xffffffff
0x2f58: 0xffffffff
0x2f5c: 0xffffffff
0x2f60: 0xffffffff
0x2f64: 0xffffffff
0x2f68: 0xffffffff
0x2f6c: 0xffffffff
0x2f70: 0xffffffff
0x2f74: 0xffffffff
0x2f78: 0xffffffff
0x2f7c: 0xffffffff
0x2f80: 0xffffffff
0x2f84: 0xffffffff
0x2f88: 0xffffffff
0x2f8c: 0xffffffff
0x2f90: 0xffffffff
0x2f94: 0xffffffff
0x2f98: 0xffffffff
0x2f9c: 0xffffffff
0x2fa0: 0xffffffff
0x2fa4: 0xffffffff
0x2fa8: 0xffffffff
0x2fac: 0xffffffff
0x2fb0: 0xffffffff
0x2fb4: 0xffffffff
0x2fb8: 0xffffffff
0x2fbc: 0xffffffff
0x2fc0: 0xffffffff
0x2fc4: 0xffffffff
0x2fc8: 0xffffffff
0x2fcc: 0xffffffff
0x2fd0: 0xffffffff
0x2fd4: 0xffffffff
0x2fd8: 0xffffffff
0x2fdc: 0xffffffff
0x2fe0: 0xffffffff
0x2fe4: 0xffffffff
0x2fe8: 0xffffffff
0x2fec: 0xffffffff
0x2ff0: 0xffffffff
0x2ff4: 0xffffffff
0x2ff8: 0xffffffff
0x2ffc: 0xffffffff
0x3000: 0xffffffff
0x3004: 0xffffffff
0x3008: 0xffffffff
0x300c: 0xffffffff
0x3010: 0xffffffff
0x3014: 0xffffffff
0x3018: 0xffffffff
0x301c: 0xffffffff
0x3020: 0xffffffff
0x3024: 0xffffffff
0x3028: 0xffffffff
0x302c: 0xffffffff
0x3030: 0xffffffff
0x3034: 0xffffffff
0x3038: 0xffffffff
0x303c: 0xffffffff
0x3040: 0xffffffff
0x3044: 0xffffffff
0x3048: 0xffffffff
0x304c: 0xffffffff
0x3050: 0xffffffff
0x3054: 0xffffffff
0x3058: 0xffffffff
0x305c: 0xffffffff
0x3060: 0xffffffff
0x3064: 0xffffffff
0x3068: 0xffffffff
0x306c: 0xffffffff
0x3070: 0xffffffff
0x3074: 0xffffffff
0x3078: 0xffffffff
0x307c: 0xffffffff
0x3080: 0xffffffff
0x3084: 0xffffffff
0x3088: 0xffffffff
0x308c: 0xffffffff
0x3090: 0xffffffff
0x3094: 0xffffffff
0x3098: 0xffffffff
0x309c: 0xffffffff
0x30a0: 0xffffffff
0x30a4: 0xffffffff
0x30a8: 0xffffffff
0x30ac: 0xffffffff
0x30b0: 0xffffffff
0x30b4: 0xffffffff
0x30b8: 0xffffffff
0x30bc: 0xffffffff
0x30c0: 0xffffffff
0x30c4: 0xffffffff
0x30c8: 0xffffffff
0x30cc: 0xffffffff
0x30d0: 0xffffffff
0x30d4: 0xffffffff
0x30d8: 0xffffffff
0x30dc: 0xffffffff
0x30e0: 0xffffffff
0x30e4: 0xffffffff
0x30e8: 0xffffffff
0x30ec: 0xffffffff
0x30f0: 0xffffffff
0x30f4: 0xffffffff
0x30f8: 0xffffffff
0x30fc: 0xffffffff
0x3100: 0xffffffff
0x3104: 0xffffffff
0x3108: 0xffffffff
0x310c: 0xffffffff
0x3110: 0xffffffff
0x3114: 0xffffffff
0x3118: 0xffffffff
0x311c: 0xffffffff
0x3120: 0xffffffff
0x3124: 0xffffffff
0x3128: 0xffffffff
0x312c: 0xffffffff
0x3130: 0xffffffff
0x3134: 0xffffffff
0x3138: 0xffffffff
0x313c: 0xffffffff
0x3140: 0xffffffff
0x3144: 0xffffffff
0x3148: 0xffffffff
0x314c: 0xffffffff
0x3150: 0xffffffff
0x3154: 0xffffffff
0x3158: 0xffffffff
0x315c: 0xffffffff
0x3160: 0xffffffff
0x3164: 0xffffffff
0x3168: 0xffffffff
0x316c: 0xffffffff
0x3170: 0xffffffff
0x3174: 0xffffffff
0x3178: 0xffffffff
0x317c: 0xffffffff
0x3180: 0xffffffff
0x3184: 0xffffffff
0x3188: 0xffffffff
0x318c: 0xffffffff
0x3190: 0xffffffff
0x3194: 0xffffffff
0x3198: 0xffffffff
0x319c: 0xffffffff
0x31a0: 0xffffffff
0x31a4: 0xffffffff
0x31a8: 0xffffffff
0x31ac: 0xffffffff
0x31b0: 0xffffffff
0x31b4: 0xffffffff
0x31b8: 0xffffffff
0x31bc: 0xffffffff
0x31c0: 0xffffffff
0x31c4: 0xffffffff
0x31c8: 0xffffffff
0x31cc: 0xffffffff
0x31d0: 0xffffffff
0x31d4: 0xffffffff
0x31d8: 0xffffffff
0x31dc: 0xffffffff
0x31e0: 0xffffffff
0x31e4: 0xffffffff
0x31e8: 0xffffffff
0x31ec: 0xffffffff
0x31f0: 0xffffffff
0x31f4: 0xffffffff
0x31f8: 0xffffffff
0x31fc: 0xffffffff
0x3200: 0xffffffff
0x3204: 0xffffffff
0x3208: 0xffffffff
0x320c: 0xffffffff
0x3210: 0xffffffff
0x3214: 0xffffffff
0x3218: 0xffffffff
0x321c: 0xffffffff
0x3220: 0xffffffff
0x3224: 0xffffffff
0x3228: 0xffffffff
0x322c: 0xffffffff
0x3230: 0xffffffff
0x3234: 0xffffffff
0x3238: 0xffffffff
0x323c: 0xffffffff
0x3240: 0xffffffff
0x3244: 0xffffffff
0x3248: 0xffffffff
0x324c: 0xffffffff
0x3250: 0xffffffff
0x3254: 0xffffffff
0x3258: 0xffffffff
0x325c: 0xffffffff
0x3260: 0xffffffff
0x3264: 0xffffffff
0x3268: 0xffffffff
0x326c: 0xffffffff
0x3270: 0xffffffff
0x3274: 0xffffffff
0x3278: 0xffffffff
0x327c: 0xffffffff
0x3280: 0xffffffff
0x3284: 0xffffffff
0x3288: 0xffffffff
0x328c: 0xffffffff
0x3290: 0xffffffff
0x3294: 0xffffffff
0x3298: 0xffffffff
0x329c: 0xffffffff
0x32a0: 0xffffffff
0x32a4: 0xffffffff
0x32a8: 0xffffffff
0x32ac: 0xffffffff
0x32b0: 0xffffffff
0x32b4: 0xffffffff
0x32b8: 0xffffffff
0x32bc: 0xffffffff
0x32c0: 0xffffffff
0x32c4: 0xffffffff
0x32c8: 0xffffffff
0x32cc: 0xffffffff
0x32d0: 0xffffffff
0x32d4: 0xffffffff
0x32d8: 0xffffffff
0x32dc: 0xffffffff
0x32e0: 0xffffffff
0x32e4: 0xffffffff
0x32e8: 0xffffffff
0x32ec: 0xffffffff
0x32f0: 0xffffffff
0x32f4: 0xffffffff
0x32f8: 0xffffffff
0x32fc: 0xffffffff
0x3300: 0xffffffff
0x3304: 0xffffffff
0x3308: 0xffffffff
0x330c: 0xffffffff
0x3310: 0xffffffff
0x3314: 0xffffffff
0x3318: 0xffffffff
0x331c: 0xffffffff
0x3320: 0xffffffff
0x3324: 0xffffffff
0x3328: 0xffffffff
0x332c: 0xffffffff
0x3330: 0xffffffff
0x3334: 0xffffffff
0x3338: 0xffffffff
0x333c: 0xffffffff
0x3340: 0xffffffff
0x3344: 0xffffffff
0x3348: 0xffffffff
0x334c: 0xffffffff
0x3350: 0xffffffff
0x3354: 0xffffffff
0x3358: 0xffffffff
0x335c: 0xffffffff
0x3360: 0xffffffff
0x3364: 0xffffffff
0x3368: 0xffffffff
0x336c: 0xffffffff
0x3370: 0xffffffff
0x3374: 0xffffffff
0x3378: 0xffffffff
0x337c: 0xffffffff
0x3380: 0xffffffff
0x3384: 0xffffffff
0x3388: 0xffffffff
0x338c: 0xffffffff
0x3390: 0xffffffff
0x3394: 0xffffffff
0x3398: 0xffffffff
0x339c: 0xffffffff
0x33a0: 0xffffffff
0x33a4: 0xffffffff
0x33a8: 0xffffffff
0x33ac: 0xffffffff
0x33b0: 0xffffffff
0x33b4: 0xffffffff
0x33b8: 0xffffffff
0x33bc: 0xffffffff
0x33c0: 0xffffffff
0x33c4: 0xffffffff
0x33c8: 0xffffffff
0x33cc: 0xffffffff
0x33d0: 0xffffffff
0x33d4: 0xffffffff
0x33d8: 0xffffffff
0x33dc: 0xffffffff
0x33e0: 0xffffffff
0x33e4: 0xffffffff
0x33e8: 0xffffffff
0x33ec: 0xffffffff
0x33f0: 0xffffffff
0x33f4: 0xffffffff
0x33f8: 0xffffffff
0x33fc: 0xffffffff
0x3400: 0xffffffff
0x3404: 0xffffffff
0x3408: 0xffffffff
0x340c: 0xffffffff
0x3410: 0xffffffff
0x3414: 0xffffffff
0x3418: 0xffffffff
0x341c: 0xffffffff
0x3420: 0xffffffff
0x3424: 0xffffffff
0x3428: 0xffffffff
0x342c: 0xffffffff
0x3430: 0xffffffff
0x3434: 0xffffffff
0x3438: 0xffffffff
0x343c: 0xffffffff
0x3440: 0xffffffff
0x3444: 0xffffffff
0x3448: 0xffffffff
0x344c: 0xffffffff
0x3450: 0xffffffff
0x3454: 0xffffffff
0x3458: 0xffffffff
0x345c: 0xffffffff
0x3460: 0xffffffff
0x3464: 0xffffffff
0x3468: 0xffffffff
0x346c: 0xffffffff
0x3470: 0xffffffff
0x3474: 0xffffffff
0x3478: 0xffffffff
0x347c: 0xffffffff
0x3480: 0xffffffff
0x3484: 0xffffffff
0x3488: 0xffffffff
0x348c: 0xffffffff
0x3490: 0xffffffff
0x3494: 0xffffffff
0x3498: 0xffffffff
0x349c: 0xffffffff
0x34a0: 0xffffffff
0x34a4: 0xffffffff
0x34a8: 0xffffffff
0x34ac: 0xffffffff
0x34b0: 0xffffffff
0x34b4: 0xffffffff
0x34b8: 0xffffffff
0x34bc: 0xffffffff
0x34c0: 0xffffffff
0x34c4: 0xffffffff
0x34c8: 0xffffffff
0x34cc: 0xffffffff
0x34d0: 0xffffffff
0x34d4: 0xffffffff
0x34d8: 0xffffffff
0x34dc: 0xffffffff
0x34e0: 0xffffffff
0x34e4: 0xffffffff
0x34e8: 0xffffffff
0x34ec: 0xffffffff
0x34f0: 0xffffffff
0x34f4: 0xffffffff
0x34f8: 0xffffffff
0x34fc: 0xffffffff
0x3500: 0xffffffff
0x3504: 0xffffffff
0x3508: 0xffffffff
0x350c: 0xffffffff
0x3510: 0xffffffff
0x3514: 0xffffffff
0x3518: 0xffffffff
0x351c: 0xffffffff
0x3520: 0xffffffff
0x3524: 0xffffffff
0x3528: 0xffffffff
0x352c: 0xffffffff
0x3530: 0xffffffff
0x3534: 0xffffffff
0x3538: 0xffffffff
0x353c: 0xffffffff
0x3540: 0xffffffff
0x3544: 0xffffffff
0x3548: 0xffffffff
0x354c: 0xffffffff
0x3550: 0xffffffff
0x3554: 0xffffffff
0x3558: 0xffffffff
0x355c: 0xffffffff
0x3560: 0xffffffff
0x3564: 0xffffffff
0x3568: 0xffffffff
0x356c: 0xffffffff
0x3570: 0xffffffff
0x3574: 0xffffffff
0x3578: 0xffffffff
0x357c: 0xffffffff
0x3580: 0xffffffff
0x3584: 0xffffffff
0x3588: 0xffffffff
0x358c: 0xffffffff
0x3590: 0xffffffff
0x3594: 0xffffffff
0x3598: 0xffffffff
0x359c: 0xffffffff
0x35a0: 0xffffffff
0x35a4: 0xffffffff
0x35a8: 0xffffffff
0x35ac: 0xffffffff
0x35b0: 0xffffffff
0x35b4: 0xffffffff
0x35b8: 0xffffffff
0x35bc: 0xffffffff
0x35c0: 0xffffffff
0x35c4: 0xffffffff
0x35c8: 0xffffffff
0x35cc: 0xffffffff
0x35d0: 0xffffffff
0x35d4: 0xffffffff
0x35d8: 0xffffffff
0x35dc: 0xffffffff
0x35e0: 0xffffffff
0x35e4: 0xffffffff
0x35e8: 0xffffffff
0x35ec: 0xffffffff
0x35f0: 0xffffffff
0x35f4: 0xffffffff
0x35f8: 0xffffffff
0x35fc: 0xffffffff
0x3600: 0xffffffff
0x3604: 0xffffffff
0x3608: 0xffffffff
0x360c: 0xffffffff
0x3610: 0xffffffff
0x3614: 0xffffffff
0x3618: 0xffffffff
0x361c: 0xffffffff
0x3620: 0xffffffff
0x3624: 0xffffffff
0x3628: 0xffffffff
0x362c: 0xffffffff
0x3630: 0xffffffff
0x3634: 0xffffffff
0x3638: 0xffffffff
0x363c: 0xffffffff
0x3640: 0xffffffff
0x3644: 0xffffffff
0x3648: 0xffffffff
0x364c: 0xffffffff
0x3650: 0xffffffff
0x3654: 0xffffffff
0x3658: 0xffffffff
0x365c: 0xffffffff
0x3660: 0xffffffff
0x3664: 0xffffffff
0x3668: 0xffffffff
0x366c: 0xffffffff
0x3670: 0xffffffff
0x3674: 0xffffffff
0x3678: 0xffffffff
0x367c: 0xffffffff
0x3680: 0xffffffff
0x3684: 0xffffffff
0x3688: 0xffffffff
0x368c: 0xffffffff
0x3690: 0xffffffff
0x3694: 0xffffffff
0x3698: 0xffffffff
0x369c: 0xffffffff
0x36a0: 0xffffffff
0x36a4: 0xffffffff
0x36a8: 0xffffffff
0x36ac: 0xffffffff
0x36b0: 0xffffffff
0x36b4: 0xffffffff
0x36b8: 0xffffffff
0x36bc: 0xffffffff
0x36c0: 0xffffffff
0x36c4: 0xffffffff
0x36c8: 0xffffffff
0x36cc: 0xffffffff
0x36d0: 0xffffffff
0x36d4: 0xffffffff
0x36d8: 0xffffffff
0x36dc: 0xffffffff
0x36e0: 0xffffffff
0x36e4: 0xffffffff
0x36e8: 0xffffffff
0x36ec: 0xffffffff
0x36f0: 0xffffffff
0x36f4: 0xffffffff
0x36f8: 0xffffffff
0x36fc: 0xffffffff
0x3700: 0xffffffff
0x3704: 0xffffffff
0x3708: 0xffffffff
0x370c: 0xffffffff
0x3710: 0xffffffff
0x3714: 0xffffffff
0x3718: 0xffffffff
0x371c: 0xffffffff
0x3720: 0xffffffff
0x3724: 0xffffffff
0x3728: 0xffffffff
0x372c: 0xffffffff
0x3730: 0xffffffff
0x3734: 0xffffffff
0x3738: 0xffffffff
0x373c: 0xffffffff
0x3740: 0xffffffff
0x3744: 0xffffffff
0x3748: 0xffffffff
0x374c: 0xffffffff
0x3750: 0xffffffff
0x3754: 0xffffffff
0x3758: 0xffffffff
0x375c: 0xffffffff
0x3760: 0xffffffff
0x3764: 0xffffffff
0x3768: 0xffffffff
0x376c: 0xffffffff
0x3770: 0xffffffff
0x3774: 0xffffffff
0x3778: 0xffffffff
0x377c: 0xffffffff
0x3780: 0xffffffff
0x3784: 0xffffffff
0x3788: 0xffffffff
0x378c: 0xffffffff
0x3790: 0xffffffff
0x3794: 0xffffffff
0x3798: 0xffffffff
0x379c: 0xffffffff
0x37a0: 0xffffffff
0x37a4: 0xffffffff
0x37a8: 0xffffffff
0x37ac: 0xffffffff
0x37b0: 0xffffffff
0x37b4: 0xffffffff
0x37b8: 0xffffffff
0x37bc: 0xffffffff
0x37c0: 0xffffffff
0x37c4: 0xffffffff
0x37c8: 0xffffffff
0x37cc: 0xffffffff
0x37d0: 0xffffffff
0x37d4: 0xffffffff
0x37d8: 0xffffffff
0x37dc: 0xffffffff
0x37e0: 0xffffffff
0x37e4: 0xffffffff
0x37e8: 0xffffffff
0x37ec: 0xffffffff
0x37f0: 0xffffffff
0x37f4: 0xffffffff
0x37f8: 0xffffffff
0x37fc: 0xffffffff
0x3800: 0xffffffff
0x3804: 0xffffffff
0x3808: 0xffffffff
0x380c: 0xffffffff
0x3810: 0xffffffff
0x3814: 0xffffffff
0x3818: 0xffffffff
0x381c: 0xffffffff
0x3820: 0xffffffff
0x3824: 0xffffffff
0x3828: 0xffffffff
0x382c: 0xffffffff
0x3830: 0xffffffff
0x3834: 0xffffffff
0x3838: 0xffffffff
0x383c: 0xffffffff
0x3840: 0xffffffff
0x3844: 0xffffffff
0x3848: 0xffffffff
0x384c: 0xffffffff
0x3850: 0xffffffff
0x3854: 0xffffffff
0x3858: 0xffffffff
0x385c: 0xffffffff
0x3860: 0xffffffff
0x3864: 0xffffffff
0x3868: 0xffffffff
0x386c: 0xffffffff
0x3870: 0xffffffff
0x3874: 0xffffffff
0x3878: 0xffffffff
0x387c: 0xffffffff
0x3880: 0xffffffff
0x3884: 0xffffffff
0x3888: 0xffffffff
0x388c: 0xffffffff
0x3890: 0xffffffff
0x3894: 0xffffffff
0x3898: 0xffffffff
0x389c: 0xffffffff
0x38a0: 0xffffffff
0x38a4: 0xffffffff
0x38a8: 0xffffffff
0x38ac: 0xffffffff
0x38b0: 0xffffffff
0x38b4: 0xffffffff
0x38b8: 0xffffffff
0x38bc: 0xffffffff
0x38c0: 0xffffffff
0x38c4: 0xffffffff
0x38c8: 0xffffffff
0x38cc: 0xffffffff
0x38d0: 0xffffffff
0x38d4: 0xffffffff
0x38d8: 0xffffffff
0x38dc: 0xffffffff
0x38e0: 0xffffffff
0x38e4: 0xffffffff
0x38e8: 0xffffffff
0x38ec: 0xffffffff
0x38f0: 0xffffffff
0x38f4: 0xffffffff
0x38f8: 0xffffffff
0x38fc: 0xffffffff
0x3900: 0xffffffff
0x3904: 0xffffffff
0x3908: 0xffffffff
0x390c: 0xffffffff
0x3910: 0xffffffff
0x3914: 0xffffffff
0x3918: 0xffffffff
0x391c: 0xffffffff
0x3920: 0xffffffff
0x3924: 0xffffffff
0x3928: 0xffffffff
0x392c: 0xffffffff
0x3930: 0xffffffff
0x3934: 0xffffffff
0x3938: 0xffffffff
0x393c: 0xffffffff
0x3940: 0xffffffff
0x3944: 0xffffffff
0x3948: 0xffffffff
0x394c: 0xffffffff
0x3950: 0xffffffff
0x3954: 0xffffffff
0x3958: 0xffffffff
0x395c: 0xffffffff
0x3960: 0xffffffff
0x3964: 0xffffffff
0x3968: 0xffffffff
0x396c: 0xffffffff
0x3970: 0xffffffff
0x3974: 0xffffffff
0x3978: 0xffffffff
0x397c: 0xffffffff
0x3980: 0xffffffff
0x3984: 0xffffffff
0x3988: 0xffffffff
0x398c: 0xffffffff
0x3990: 0xffffffff
0x3994: 0xffffffff
0x3998: 0xffffffff
0x399c: 0xffffffff
0x39a0: 0xffffffff
0x39a4: 0xffffffff
0x39a8: 0xffffffff
0x39ac: 0xffffffff
0x39b0: 0xffffffff
0x39b4: 0xffffffff
0x39b8: 0xffffffff
0x39bc: 0xffffffff
0x39c0: 0xffffffff
0x39c4: 0xffffffff
0x39c8: 0xffffffff
0x39cc: 0xffffffff
0x39d0: 0xffffffff
0x39d4: 0xffffffff
0x39d8: 0xffffffff
0x39dc: 0xffffffff
0x39e0: 0xffffffff
0x39e4: 0xffffffff
0x39e8: 0xffffffff
0x39ec: 0xffffffff
0x39f0: 0xffffffff
0x39f4: 0xffffffff
0x39f8: 0xffffffff
0x39fc: 0xffffffff
0x3a00: 0xffffffff
0x3a04: 0xffffffff
0x3a08: 0xffffffff
0x3a0c: 0xffffffff
0x3a10: 0xffffffff
0x3a14: 0xffffffff
0x3a18: 0xffffffff
0x3a1c: 0xffffffff
0x3a20: 0xffffffff
0x3a24: 0xffffffff
0x3a28: 0xffffffff
0x3a2c: 0xffffffff
0x3a30: 0xffffffff
0x3a34: 0xffffffff
0x3a38: 0xffffffff
0x3a3c: 0xffffffff
0x3a40: 0xffffffff
0x3a44: 0xffffffff
0x3a48: 0xffffffff
0x3a4c: 0xffffffff
0x3a50: 0xffffffff
0x3a54: 0xffffffff
0x3a58: 0xffffffff
0x3a5c: 0xffffffff
0x3a60: 0xffffffff
0x3a64: 0xffffffff
0x3a68: 0xffffffff
0x3a6c: 0xffffffff
0x3a70: 0xffffffff
0x3a74: 0xffffffff
0x3a78: 0xffffffff
0x3a7c: 0xffffffff
0x3a80: 0xffffffff
0x3a84: 0xffffffff
0x3a88: 0xffffffff
0x3a8c: 0xffffffff
0x3a90: 0xffffffff
0x3a94: 0xffffffff
0x3a98: 0xffffffff
0x3a9c: 0xffffffff
0x3aa0: 0xffffffff
0x3aa4: 0xffffffff
0x3aa8: 0xffffffff
0x3aac: 0xffffffff
0x3ab0: 0xffffffff
0x3ab4: 0xffffffff
0x3ab8: 0xffffffff
0x3abc: 0xffffffff
0x3ac0: 0xffffffff
0x3ac4: 0xffffffff
0x3ac8: 0xffffffff
0x3acc: 0xffffffff
0x3ad0: 0xffffffff
0x3ad4: 0xffffffff
0x3ad8: 0xffffffff
0x3adc: 0xffffffff
0x3ae0: 0xffffffff
0x3ae4: 0xffffffff
0x3ae8: 0xffffffff
0x3aec: 0xffffffff
0x3af0: 0xffffffff
0x3af4: 0xffffffff
0x3af8: 0xffffffff
0x3afc: 0xffffffff
0x3b00: 0xffffffff
0x3b04: 0xffffffff
0x3b08: 0xffffffff
0x3b0c: 0xffffffff
0x3b10: 0xffffffff
0x3b14: 0xffffffff
0x3b18: 0xffffffff
0x3b1c: 0xffffffff
0x3b20: 0xffffffff
0x3b24: 0xffffffff
0x3b28: 0xffffffff
0x3b2c: 0xffffffff
0x3b30: 0xffffffff
0x3b34: 0xffffffff
0x3b38: 0xffffffff
0x3b3c: 0xffffffff
0x3b40: 0xffffffff
0x3b44: 0xffffffff
0x3b48: 0xffffffff
0x3b4c: 0xffffffff
0x3b50: 0xffffffff
0x3b54: 0xffffffff
0x3b58: 0xffffffff
0x3b5c: 0xffffffff
0x3b60: 0xffffffff
0x3b64: 0xffffffff
0x3b68: 0xffffffff
0x3b6c: 0xffffffff
0x3b70: 0xffffffff
0x3b74: 0xffffffff
0x3b78: 0xffffffff
0x3b7c: 0xffffffff
0x3b80: 0xffffffff
0x3b84: 0xffffffff
0x3b88: 0xffffffff
0x3b8c: 0xffffffff
0x3b90: 0xffffffff
0x3b94: 0xffffffff
0x3b98: 0xffffffff
0x3b9c: 0xffffffff
0x3ba0: 0xffffffff
0x3ba4: 0xffffffff
0x3ba8: 0xffffffff
0x3bac: 0xffffffff
0x3bb0: 0xffffffff
0x3bb4: 0xffffffff
0x3bb8: 0xffffffff
0x3bbc: 0xffffffff
0x3bc0: 0xffffffff
0x3bc4: 0xffffffff
0x3bc8: 0xffffffff
0x3bcc: 0xffffffff
0x3bd0: 0xffffffff
0x3bd4: 0xffffffff
0x3bd8: 0xffffffff
0x3bdc: 0xffffffff
0x3be0: 0xffffffff
0x3be4: 0xffffffff
0x3be8: 0xffffffff
0x3bec: 0xffffffff
0x3bf0: 0xffffffff
0x3bf4: 0xffffffff
0x3bf8: 0xffffffff
0x3bfc: 0xffffffff
0x3c00: 0xffffffff
0x3c04: 0xffffffff
0x3c08: 0xffffffff
0x3c0c: 0xffffffff
0x3c10: 0xffffffff
0x3c14: 0xffffffff
0x3c18: 0xffffffff
0x3c1c: 0xffffffff
0x3c20: 0xffffffff
0x3c24: 0xffffffff
0x3c28: 0xffffffff
0x3c2c: 0xffffffff
0x3c30: 0xffffffff
0x3c34: 0xffffffff
0x3c38: 0xffffffff
0x3c3c: 0xffffffff
0x3c40: 0xffffffff
0x3c44: 0xffffffff
0x3c48: 0xffffffff
0x3c4c: 0xffffffff
0x3c50: 0xffffffff
0x3c54: 0xffffffff
0x3c58: 0xffffffff
0x3c5c: 0xffffffff
0x3c60: 0xffffffff
0x3c64: 0xffffffff
0x3c68: 0xffffffff
0x3c6c: 0xffffffff
0x3c70: 0xffffffff
0x3c74: 0xffffffff
0x3c78: 0xffffffff
0x3c7c: 0xffffffff
0x3c80: 0xffffffff
0x3c84: 0xffffffff
0x3c88: 0xffffffff
0x3c8c: 0xffffffff
0x3c90: 0xffffffff
0x3c94: 0xffffffff
0x3c98: 0xffffffff
0x3c9c: 0xffffffff
0x3ca0: 0xffffffff
0x3ca4: 0xffffffff
0x3ca8: 0xffffffff
0x3cac: 0xffffffff
0x3cb0: 0xffffffff
0x3cb4: 0xffffffff
0x3cb8: 0xffffffff
0x3cbc: 0xffffffff
0x3cc0: 0xffffffff
0x3cc4: 0xffffffff
0x3cc8: 0xffffffff
0x3ccc: 0xffffffff
0x3cd0: 0xffffffff
0x3cd4: 0xffffffff
0x3cd8: 0xffffffff
0x3cdc: 0xffffffff
0x3ce0: 0xffffffff
0x3ce4: 0xffffffff
0x3ce8: 0xffffffff
0x3cec: 0xffffffff
0x3cf0: 0xffffffff
0x3cf4: 0xffffffff
0x3cf8: 0xffffffff
0x3cfc: 0xffffffff
0x3d00: 0xffffffff
0x3d04: 0xffffffff
0x3d08: 0xffffffff
0x3d0c: 0xffffffff
0x3d10: 0xffffffff
0x3d14: 0xffffffff
0x3d18: 0xffffffff
0x3d1c: 0xffffffff
0x3d20: 0xffffffff
0x3d24: 0xffffffff
0x3d28: 0xffffffff
0x3d2c: 0xffffffff
0x3d30: 0xffffffff
0x3d34: 0xffffffff
0x3d38: 0xffffffff
0x3d3c: 0xffffffff
0x3d40: 0xffffffff
0x3d44: 0xffffffff
0x3d48: 0xffffffff
0x3d4c: 0xffffffff
0x3d50: 0xffffffff
0x3d54: 0xffffffff
0x3d58: 0xffffffff
0x3d5c: 0xffffffff
0x3d60: 0xffffffff
0x3d64: 0xffffffff
0x3d68: 0xffffffff
0x3d6c: 0xffffffff
0x3d70: 0xffffffff
0x3d74: 0xffffffff
0x3d78: 0xffffffff
0x3d7c: 0xffffffff
0x3d80: 0xffffffff
0x3d84: 0xffffffff
0x3d88: 0xffffffff
0x3d8c: 0xffffffff
0x3d90: 0xffffffff
0x3d94: 0xffffffff
0x3d98: 0xffffffff
0x3d9c: 0xffffffff
0x3da0: 0xffffffff
0x3da4: 0xffffffff
0x3da8: 0xffffffff
0x3dac: 0xffffffff
0x3db0: 0xffffffff
0x3db4: 0xffffffff
0x3db8: 0xffffffff
0x3dbc: 0xffffffff
0x3dc0: 0xffffffff
0x3dc4: 0xffffffff
0x3dc8: 0xffffffff
0x3dcc: 0xffffffff
0x3dd0: 0xffffffff
0x3dd4: 0xffffffff
0x3dd8: 0xffffffff
0x3ddc: 0xffffffff
0x3de0: 0xffffffff
0x3de4: 0xffffffff
0x3de8: 0xffffffff
0x3dec: 0xffffffff
0x3df0: 0xffffffff
0x3df4: 0xffffffff
0x3df8: 0xffffffff
0x3dfc: 0xffffffff
0x3e00: 0xffffffff
0x3e04: 0xffffffff
0x3e08: 0xffffffff
0x3e0c: 0xffffffff
0x3e10: 0xffffffff
0x3e14: 0xffffffff
0x3e18: 0xffffffff
0x3e1c: 0xffffffff
0x3e20: 0xffffffff
0x3e24: 0xffffffff
0x3e28: 0xffffffff
0x3e2c: 0xffffffff
0x3e30: 0xffffffff
0x3e34: 0xffffffff
0x3e38: 0xffffffff
0x3e3c: 0xffffffff
0x3e40: 0xffffffff
0x3e44: 0xffffffff
0x3e48: 0xffffffff
0x3e4c: 0xffffffff
0x3e50: 0xffffffff
0x3e54: 0xffffffff
0x3e58: 0xffffffff
0x3e5c: 0xffffffff
0x3e60: 0xffffffff
0x3e64: 0xffffffff
0x3e68: 0xffffffff
0x3e6c: 0xffffffff
0x3e70: 0xffffffff
0x3e74: 0xffffffff
0x3e78: 0xffffffff
0x3e7c: 0xffffffff
0x3e80: 0xffffffff
0x3e84: 0xffffffff
0x3e88: 0xffffffff
0x3e8c: 0xffffffff
0x3e90: 0xffffffff
0x3e94: 0xffffffff
0x3e98: 0xffffffff
0x3e9c: 0xffffffff
0x3ea0: 0xffffffff
0x3ea4: 0xffffffff
0x3ea8: 0xffffffff
0x3eac: 0xffffffff
0x3eb0: 0xffffffff
0x3eb4: 0xffffffff
0x3eb8: 0xffffffff
0x3ebc: 0xffffffff
0x3ec0: 0xffffffff
0x3ec4: 0xffffffff
0x3ec8: 0xffffffff
0x3ecc: 0xffffffff
0x3ed0: 0xffffffff
0x3ed4: 0xffffffff
0x3ed8: 0xffffffff
0x3edc: 0xffffffff
0x3ee0: 0xffffffff
0x3ee4: 0xffffffff
0x3ee8: 0xffffffff
0x3eec: 0xffffffff
0x3ef0: 0xffffffff
0x3ef4: 0xffffffff
0x3ef8: 0xffffffff
0x3efc: 0xffffffff
0x3f00: 0xffffffff
0x3f04: 0xffffffff
0x3f08: 0xffffffff
0x3f0c: 0xffffffff
0x3f10: 0xffffffff
0x3f14: 0xffffffff
0x3f18: 0xffffffff
0x3f1c: 0xffffffff
0x3f20: 0xffffffff
0x3f24: 0xffffffff
0x3f28: 0xffffffff
0x3f2c: 0xffffffff
0x3f30: 0xffffffff
0x3f34: 0xffffffff
0x3f38: 0xffffffff
0x3f3c: 0xffffffff
0x3f40: 0xffffffff
0x3f44: 0xffffffff
0x3f48: 0xffffffff
0x3f4c: 0xffffffff
0x3f50: 0xffffffff
0x3f54: 0xffffffff
0x3f58: 0xffffffff
0x3f5c: 0xffffffff
0x3f60: 0xffffffff
0x3f64: 0xffffffff
0x3f68: 0xffffffff
0x3f6c: 0xffffffff
0x3f70: 0xffffffff
0x3f74: 0xffffffff
0x3f78: 0xffffffff
0x3f7c: 0xffffffff
0x3f80: 0xffffffff
0x3f84: 0xffffffff
0x3f88: 0xffffffff
0x3f8c: 0xffffffff
0x3f90: 0xffffffff
0x3f94: 0xffffffff
0x3f98: 0xffffffff
0x3f9c: 0xffffffff
0x3fa0: 0xffffffff
0x3fa4: 0xffffffff
0x3fa8: 0xffffffff
0x3fac: 0xffffffff
0x3fb0: 0xffffffff
0x3fb4: 0xffffffff
0x3fb8: 0xffffffff
0x3fbc: 0xffffffff
0x3fc0: 0xffffffff
0x3fc4: 0xffffffff
0x3fc8: 0xffffffff
0x3fcc: 0xffffffff
0x3fd0: 0xffffffff
0x3fd4: 0xffffffff
0x3fd8: 0xffffffff
0x3fdc: 0xffffffff
0x3fe0: 0xffffffff
0x3fe4: 0xffffffff
0x3fe8: 0xffffffff
0x3fec: 0xffffffff
0x3ff0: 0xffffffff
0x3ff4: 0xffffffff
0x3ff8: 0xffffffff
0x3ffc: 0xffffffff



============= EPBAR =============

This northbridge does not have EPBAR.



============= DMIBAR ============

This northbridge does not have DMIBAR.


========= PCIEXBAR ========

Error: This northbridge does not have PCIEXBAR.



===================== SHARED MSRs (All Cores) =====================
 MSR 0x00000000 = 0x00000000:0x00000000 (IA32_P5_MC_ADDR)
 MSR 0x00000001 = 0x00000000:0x00000000 (IA32_P5_MC_TYPE)
 MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
 MSR 0x00000017 = 0x00120000:0x00000000 (IA32_PLATFORM_ID)
 MSR 0x0000002A = 0x00000000:0x00000080 (MSR_EBC_HARD_POWERON)
 MSR 0x0000002B = 0x00000000:0x0000000E (MSR_EBC_SOFT_POWRON)
 MSR 0x0000002C = 0x00000000:0x0F12010F (MSR_EBC_FREQUENCY_ID)
 MSR 0x0000019C = 0x00000000:0x00000000 (IA32_THERM_STATUS)
 MSR 0x0000019D = 0x00000000:0x00000E2D (MSR_THERM2_CTL)
 MSR 0x000001A0 = 0x00000000:0x20840489 (IA32_MISC_ENABLE)
 MSR 0x000001A1 = 0x00000000:0x00000000 (MSR_PLATFORM_BRV)
 MSR 0x00000200 = 0x00000000:0x00000006 (IA32_MTRR_PHYSBASE0)
 MSR 0x00000201 = 0x0000000F:0x80000800 (IA32_MTRR_PHYSMASK0)
 MSR 0x00000202 = 0x00000000:0x7F800000 (IA32_MTRR_PHYSBASE1)
 MSR 0x00000203 = 0x0000000F:0xFF800800 (IA32_MTRR_PHYSMASK1)
 MSR 0x00000204 = 0x00000000:0xF0000001 (IA32_MTRR_PHYSBASE2)
 MSR 0x00000205 = 0x0000000F:0xF8000800 (IA32_MTRR_PHYSMASK2)
 MSR 0x00000206 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE3)
 MSR 0x00000207 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK3)
 MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4)
 MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4)
 MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5)
 MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5)
 MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6)
 MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6)
 MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
 MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
 MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
 MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
 MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
 MSR 0x00000268 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C0000)
 MSR 0x00000269 = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_C8000)
 MSR 0x0000026A = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D0000)
 MSR 0x0000026B = 0x00000000:0x00000000 (IA32_MTRR_FIX4K_D8000)
 MSR 0x0000026C = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E0000)
 MSR 0x0000026D = 0x04040404:0x04040404 (IA32_MTRR_FIX4K_E8000)
 MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
 MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
 MSR 0x000002FF = 0x00000000:0x00000C00 (IA32_MTRR_DEF_TYPE)
 MSR 0x00000300 = 0x000000FC:0x2DC51DBC (MSR_BPU_COUNTER0)
 MSR 0x00000301 = 0x00000000:0x00000000 (MSR_BPU_COUNTER1)
 MSR 0x00000302 = 0x000000FB:0x36EB7E38 (MSR_BPU_COUNTER2)
 MSR 0x00000303 = 0x00000000:0x00000000 (MSR_BPU_COUNTER3)
 MSR 0x00000400 = 0x00000000:0x0000FFFF (IA32_MC0_CTL)
 MSR 0x00000401 = 0x00000000:0x00000000 (IA32_MC0_STATUS)
 MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
 MSR 0x00000403 = 0x00000000:0x00000000 (IA32_MC0_MISC)
 MSR 0x00000404 = 0x00000000:0x00018000 (IA32_MC1_CTL)
 MSR 0x00000405 = 0x00000000:0x00000000 (IA32_MC1_STATUS)
 MSR 0x00000406 = 0x00000000:0x00000000 (IA32_MC1_ADDR)
 (*) MSR 0x00000407 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC1_MISC)
 MSR 0x00000408 = 0x00000000:0x00000080 (IA32_MC2_CTL)
 MSR 0x00000409 = 0x00000000:0x00000000 (IA32_MC2_STATUS)
 (*) MSR 0x0000040A = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC2_ADDR)
 (*) MSR 0x0000040B = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC2_MISC)
 MSR 0x0000040C = 0x00000000:0x0000007E (IA32_MC3_CTL)
 MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
 MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
 MSR 0x0000040F = 0x00000000:0x00000000 (IA32_MC3_MISC)
 (*) MSR 0x00000410 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_CTL)
 (*) MSR 0x00000411 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_STATUS)
 (*) MSR 0x00000412 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_ADDR)
 (*) MSR 0x00000413 = 0xFFFFFFFF:0xFFFFFFFF (IA32_MC4_MISC)

====================== UNIQUE MSRs  (core 0) ======================
 MSR 0x00000010 = 0x0000025F:0x77A7D49B (IA32_TIME_STAMP_COUNTER)
 MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE)
 (*) MSR 0x0000003A = 0xFFFFFFFF:0xFFFFFFFF (IA32_FEATURE_CONTROL)
 MSR 0x0000008B = 0x00000003:0x00000000 (IA32_BIOS_SIGN_ID)
 (*) MSR 0x0000009B = 0xFFFFFFFF:0xFFFFFFFF (IA32_SMM_MONITOR_CTL)
 MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP)
 MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
 MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP)
 MSR 0x00000176 = 0xFFFFFFFF:0x813521A0 (IA32_SYSENTER_EIP)
 MSR 0x00000179 = 0x00000000:0x00180204 (IA32_MCG_CAP)
 MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
 MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX)
 MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX)
 MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX)
 MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX)
 MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI)
 MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI)
 MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP)
 MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP)
 MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS)
 MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP)
 MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC)
 MSR 0x00000190 = 0x00000000:0x00000000 (MSR_MCG_R8)
 MSR 0x00000191 = 0x00000000:0x00000000 (MSR_MCG_R9)
 MSR 0x00000192 = 0x00000000:0x00000000 (MSR_MCG_R10)
 MSR 0x00000193 = 0x00000000:0x00000000 (MSR_MCG_R11)
 MSR 0x00000194 = 0x00000000:0x00000000 (MSR_MCG_R12)
 MSR 0x00000195 = 0x00000000:0x00000000 (MSR_MCG_R13)
 MSR 0x00000196 = 0x00000000:0x00000000 (MSR_MCG_R14)
 MSR 0x00000197 = 0x00000000:0x00000000 (MSR_MCG_R15)
 MSR 0x00000198 = 0x00000F2D:0x00000F2D (IA32_PERF_STATUS)
 MSR 0x00000199 = 0x00000000:0x00000F2D (IA32_PERF_CTL)
 MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
 MSR 0x0000019B = 0x00000000:0x00000000 (IA32_THERM_INTERRUPT)
 MSR 0x000001A0 = 0x00000000:0x20840489 (IA32_MISC_ENABLE)
 MSR 0x000001D7 = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
 MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
 MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA)
 MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
 MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT)
 MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA)

====================== UNIQUE MSRs  (core 1) ======================
 MSR 0x00000010 = 0x0000025F:0x77B053E6 (IA32_TIME_STAMP_COUNTER)
 MSR 0x0000001B = 0x00000000:0xFEE00800 (IA32_APIC_BASE)
 (*) MSR 0x0000003A = 0xFFFFFFFF:0xFFFFFFFF (IA32_FEATURE_CONTROL)
 MSR 0x0000008B = 0x00000003:0x00000000 (IA32_BIOS_SIGN_ID)
 (*) MSR 0x0000009B = 0xFFFFFFFF:0xFFFFFFFF (IA32_SMM_MONITOR_CTL)
 MSR 0x000000FE = 0x00000000:0x00000508 (IA32_MTRRCAP)
 MSR 0x00000174 = 0x00000000:0x00000010 (IA32_SYSENTER_CS)
 MSR 0x00000175 = 0x00000000:0x00000000 (IA32_SYSENTER_ESP)
 MSR 0x00000176 = 0xFFFFFFFF:0x813521A0 (IA32_SYSENTER_EIP)
 MSR 0x00000179 = 0x00000000:0x00180204 (IA32_MCG_CAP)
 MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
 MSR 0x00000180 = 0x00000000:0x00000000 (MSR_MCG_RAX)
 MSR 0x00000181 = 0x00000000:0x00000000 (MSR_MCG_RBX)
 MSR 0x00000182 = 0x00000000:0x00000000 (MSR_MCG_RCX)
 MSR 0x00000183 = 0x00000000:0x00000000 (MSR_MCG_RDX)
 MSR 0x00000184 = 0x00000000:0x00000000 (MSR_MCG_RSI)
 MSR 0x00000185 = 0x00000000:0x00000000 (MSR_MCG_RDI)
 MSR 0x00000186 = 0x00000000:0x00000000 (MSR_MCG_RBP)
 MSR 0x00000187 = 0x00000000:0x00000000 (MSR_MCG_RSP)
 MSR 0x00000188 = 0x00000000:0x00000000 (MSR_MCG_RFLAGS)
 MSR 0x00000189 = 0x00000000:0x00000000 (MSR_MCG_RIP)
 MSR 0x0000018A = 0x00000000:0x00000000 (MSR_MCG_MISC)
 MSR 0x00000190 = 0x00000000:0x00000000 (MSR_MCG_R8)
 MSR 0x00000191 = 0x00000000:0x00000000 (MSR_MCG_R9)
 MSR 0x00000192 = 0x00000000:0x00000000 (MSR_MCG_R10)
 MSR 0x00000193 = 0x00000000:0x00000000 (MSR_MCG_R11)
 MSR 0x00000194 = 0x00000000:0x00000000 (MSR_MCG_R12)
 MSR 0x00000195 = 0x00000000:0x00000000 (MSR_MCG_R13)
 MSR 0x00000196 = 0x00000000:0x00000000 (MSR_MCG_R14)
 MSR 0x00000197 = 0x00000000:0x00000000 (MSR_MCG_R15)
 MSR 0x00000198 = 0x00000F2D:0x00000F2D (IA32_PERF_STATUS)
 MSR 0x00000199 = 0x00000000:0x00000F2D (IA32_PERF_CTL)
 MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
 MSR 0x0000019B = 0x00000000:0x00000000 (IA32_THERM_INTERRUPT)
 MSR 0x000001A0 = 0x00000000:0x20840489 (IA32_MISC_ENABLE)
 MSR 0x000001D7 = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
 MSR 0x000001D8 = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
 MSR 0x000001D9 = 0x00000000:0x00000000 (MSR_DEBUGCTLA)
 MSR 0x000001DA = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
 MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT)
 MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA)

(*) Some MSRs could not be read. The marked values are unreliable.



============= AMBs ============

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From wmkamp at datakamp.de  Wed Jan 18 16:11:09 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Wed, 18 Jan 2012 16:11:09 +0100
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local><CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
	<F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>

Hello Kerry, hello Marc,

sounds good but solves not my problem. The enumeration of the SB800 GPP ports works fine with Linux.
But coreboot fails because the SB GPP ports are not yet initialized when coreboot probes them.
The function sbPcieGppEarlyInit will be executed after coreboot PCI probing of the SB GPP ports.
You can see that in late.c.
I put that function now in the right place in the case (0x15<<0 | 0) statement so probing succeeds.
And my Intel LAN GB82574 will be enumerated as I can see in the log.
But if I do that coreboot hangs in tables.c with postcode 0x9c and I can't imagine why.
I need the correct enumeration in coreboot because the Intel LAN chip tools only works under DOS.

Wolfgang

-----Urspr?ngliche Nachricht-----
Von: She, Kerry [mailto:Kerry.She at amd.com] 
Gesendet: Mittwoch, 18. Januar 2012 08:49
An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
Cc: coreboot at coreboot.org; chia, kenneth
Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization

Hello Marc and Wolfgang

> -----Original Message-----
> From: coreboot-bounces at coreboot.org 
> [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of She, Kerry
> Sent: Tuesday, January 17, 2012 4:07 PM
> To: Marc Jones; Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Walfqang,
> 
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> bounces at coreboot.org]
> > On Behalf Of Marc Jones
> > Sent: Tuesday, January 17, 2012 3:23 AM
> > To: Wolfgang Kamp - datakamp
> > Cc: coreboot at coreboot.org
> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port 
> > Initialization
> >
> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp 
> > <wmkamp at datakamp.de> wrote:
> > > Hello,
> > >
> > >
> > >
> > > I found a problem with the PCI enumeration of the PCIe Ports in 
> > > the CIMX/SB800 Southbridge for the INAGUA platform.
> > >
> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the 
> > > function sb_Before_PCI_Init after
> > >
> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 
> > > <<3)
> |
> > 0
> > > are probed in the routine ../devices/pci_device.c function
> > >
> > > pci_probe_dev they are not yet initialized. The probing fails and
> also
> > > devices behind the bridge are not recognized.
> > >
> > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> > >
> > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15 
> > > <<3)
> |
> > 0 the
> > > enumeration succeed but coreboot crashes later into nothing. The 
> > > Sage Debugger fails.
> > >
> > > I can't imagine why.
> > >
> > >
> > >
> > > Marc have you any idea?
> >
> > This looks like a problem in the sb800 cimx wrapper logic. Cimx 
> > doesn't treat the devices separately. it lumps all the configuration 
> > and enables together, making the coreboot chipset device enable 
> > callback fail to enable the device, so it gets disabled. The sb900 
> > wrapper appears to fix this issue with cimx setup in early init. You 
> > may want to try porting those changes to the sb800.
> >
> > I don't know why it fails later, but I assume it is due to the 
> > missing config since you moved the call earlier in the process. You 
> > could try calling it multiple times. I'm not sure how it handles that, though.
> >
> > Kerry,
> > Do you have any comments?
> If the enumeration fail, I suggest you should check the PCIE deassert 
> GPIO setting.
> Thanks

I found the recent amd/inagua code in the git tree is not boot on my platform and more.
I made an update to make my platform works now.
The missing mainboard specific GPIO setting also added back, So the sb800 GPP enumeration works now.

Please reference following link and the attachment.
http://review.coreboot.org/#change,542
http://review.coreboot.org/#change,543
http://review.coreboot.org/#change,544
http://review.coreboot.org/#change,545
http://review.coreboot.org/#change,546

Thanks
Kerry  
 


From marcj303 at gmail.com  Wed Jan 18 19:28:20 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 18 Jan 2012 11:28:20 -0700
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
	<CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
	<F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
Message-ID: <CALrs_3jQBQG5k7DApO_MgUe5vozsce7yPJT3NQQmiZu5ETk+rg@mail.gmail.com>

On Wed, Jan 18, 2012 at 8:11 AM, Wolfgang Kamp - datakamp
<wmkamp at datakamp.de> wrote:
> Hello Kerry, hello Marc,
>
> sounds good but solves not my problem. The enumeration of the SB800 GPP ports works fine with Linux.
> But coreboot fails because the SB GPP ports are not yet initialized when coreboot probes them.
> The function sbPcieGppEarlyInit will be executed after coreboot PCI probing of the SB GPP ports.
> You can see that in late.c.
> I put that function now in the right place in the case (0x15<<0 | 0) statement so probing succeeds.
> And my Intel LAN GB82574 will be enumerated as I can see in the log.
> But if I do that coreboot hangs in tables.c with postcode 0x9c and I can't imagine why.
> I need the correct enumeration in coreboot because the Intel LAN chip tools only works under DOS.
>
> Wolfgang
>

Kerry,

I agree with Wolfgang. I think that the sb800 has an issue.

>> > The sb900 wrapper appears to fix this issue with cimx setup in early init.

The device isn't visible in late init. The coreboot chip device scan
will disable the device when it isn't found. The configuration needs
to be set in early init like the sb900. Do you agree?

Marc


> -----Urspr?ngliche Nachricht-----
> Von: She, Kerry [mailto:Kerry.She at amd.com]
> Gesendet: Mittwoch, 18. Januar 2012 08:49
> An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org; chia, kenneth
> Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>
> Hello Marc and Wolfgang
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org
>> [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of She, Kerry
>> Sent: Tuesday, January 17, 2012 4:07 PM
>> To: Marc Jones; Wolfgang Kamp - datakamp
>> Cc: coreboot at coreboot.org
>> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>>
>> Hello Walfqang,
>>
>> > -----Original Message-----
>> > From: coreboot-bounces at coreboot.org [mailto:coreboot-
>> bounces at coreboot.org]
>> > On Behalf Of Marc Jones
>> > Sent: Tuesday, January 17, 2012 3:23 AM
>> > To: Wolfgang Kamp - datakamp
>> > Cc: coreboot at coreboot.org
>> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
>> > Initialization
>> >
>> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
>> > <wmkamp at datakamp.de> wrote:
>> > > Hello,
>> > >
>> > >
>> > >
>> > > I found a problem with the PCI enumeration of the PCIe Ports in
>> > > the CIMX/SB800 Southbridge for the INAGUA platform.
>> > >
>> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
>> > > function sb_Before_PCI_Init after
>> > >
>> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
>> > > <<3)
>> |
>> > 0
>> > > are probed in the routine ../devices/pci_device.c function
>> > >
>> > > pci_probe_dev they are not yet initialized. The probing fails and
>> also
>> > > devices behind the bridge are not recognized.
>> > >
>> > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
>> > >
>> > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
>> > > <<3)
>> |
>> > 0 the
>> > > enumeration succeed but coreboot crashes later into nothing. The
>> > > Sage Debugger fails.
>> > >
>> > > I can't imagine why.
>> > >
>> > >
>> > >
>> > > Marc have you any idea?
>> >
>> > This looks like a problem in the sb800 cimx wrapper logic. Cimx
>> > doesn't treat the devices separately. it lumps all the configuration
>> > and enables together, making the coreboot chipset device enable
>> > callback fail to enable the device, so it gets disabled. The sb900
>> > wrapper appears to fix this issue with cimx setup in early init. You
>> > may want to try porting those changes to the sb800.
>> >
>> > I don't know why it fails later, but I assume it is due to the
>> > missing config since you moved the call earlier in the process. You
>> > could try calling it multiple times. I'm not sure how it handles that, though.
>> >
>> > Kerry,
>> > Do you have any comments?
>> If the enumeration fail, I suggest you should check the PCIE deassert
>> GPIO setting.
>> Thanks
>
> I found the recent amd/inagua code in the git tree is not boot on my platform and more.
> I made an update to make my platform works now.
> The missing mainboard specific GPIO setting also added back, So the sb800 GPP enumeration works now.
>
> Please reference following link and the attachment.
> http://review.coreboot.org/#change,542
> http://review.coreboot.org/#change,543
> http://review.coreboot.org/#change,544
> http://review.coreboot.org/#change,545
> http://review.coreboot.org/#change,546
>
> Thanks
> Kerry
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



-- 
http://se-eng.com


From gerrit at coreboot.org  Wed Jan 18 20:08:50 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 20:08:50 +0100
Subject: [coreboot] Patch merged into coreboot/master: 44085b2 Clean up AMD
	romstage.c whitespace indent issues
References: <I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9+0@gerrit.coreboot.org>
Message-ID: <E1RnasM-0000xF-Oz@ra.coresystems.de>

the following patch was just integrated into master:
commit 44085b2509c0422a43b2c5a88b93f81e2be3a9c7
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 15:41:03 2012 -0700

    Clean up AMD romstage.c whitespace indent issues
    
    Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 02:09:35 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jan 18 20:08:48 2012, giving +2
See http://review.coreboot.org/538 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 20:13:40 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 20:13:40 +0100
Subject: [coreboot] Patch set updated for coreboot: d579042 Remove
	duplicated line of code in AMD wrappers.
References: <I438da05c770ded0bd32256f1c157cabcc383667a+0@gerrit.coreboot.org>
Message-ID: <I438da05c770ded0bd32256f1c157cabcc383667a+3@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/541

-gerrit

commit d579042843cb3faf2e240730a1f7ef9ecba9ff89
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:34:03 2012 -0700

    Remove duplicated line of code in AMD wrappers.
    
    This line was unnecessary and was duplicated on several mainboards.
    
    Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/agesawrapper.c        |    1 -
 src/mainboard/amd/persimmon/agesawrapper.c     |    1 -
 src/mainboard/amd/south_station/agesawrapper.c |    1 -
 src/mainboard/amd/union_station/agesawrapper.c |    1 -
 src/mainboard/asrock/e350m1/agesawrapper.c     |    1 -
 5 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index c33d20f..715202a 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -511,7 +511,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index f9847c2..6e9997f 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -515,7 +515,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/south_station/agesawrapper.c b/src/mainboard/amd/south_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/south_station/agesawrapper.c
+++ b/src/mainboard/amd/south_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/amd/union_station/agesawrapper.c b/src/mainboard/amd/union_station/agesawrapper.c
index 0fbb3e4..7750e7d 100644
--- a/src/mainboard/amd/union_station/agesawrapper.c
+++ b/src/mainboard/amd/union_station/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 
diff --git a/src/mainboard/asrock/e350m1/agesawrapper.c b/src/mainboard/asrock/e350m1/agesawrapper.c
index fc87029..742344a 100644
--- a/src/mainboard/asrock/e350m1/agesawrapper.c
+++ b/src/mainboard/asrock/e350m1/agesawrapper.c
@@ -510,7 +510,6 @@ agesawrapper_amdlaterunaptask (
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	ApExeParams.StdHeader.Func = 0;
 	ApExeParams.StdHeader.ImageBasePtr = 0;
-	ApExeParams.StdHeader.ImageBasePtr = 0;
 	ApExeParams.FunctionNumber = Func;
 	ApExeParams.RelatedDataBlock = ConfigPtr;
 


From gerrit at coreboot.org  Wed Jan 18 20:16:24 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 20:16:24 +0100
Subject: [coreboot] Patch set updated for coreboot: 4a10baf Remove old AMD
	#define
References: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+0@gerrit.coreboot.org>
Message-ID: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+3@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/540

-gerrit

commit 4a10bafe4a530f4ae3afc6ae5a1c692a702d9df6
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:30:31 2012 -0700

    Remove old AMD #define
    
    The #define REQUIRED_CALLOUTS is no longer used on these platforms.
    
    Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/persimmon/BiosCallOuts.h     |    1 -
 src/mainboard/amd/south_station/BiosCallOuts.h |    1 -
 src/mainboard/amd/union_station/BiosCallOuts.h |    1 -
 3 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.h b/src/mainboard/amd/persimmon/BiosCallOuts.h
index e023e38..d9e4497 100644
--- a/src/mainboard/amd/persimmon/BiosCallOuts.h
+++ b/src/mainboard/amd/persimmon/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS			12
 #define BIOS_HEAP_START_ADDRESS		0x00010000
 #define BIOS_HEAP_SIZE				0x20000		/* 64MB */
 
diff --git a/src/mainboard/amd/south_station/BiosCallOuts.h b/src/mainboard/amd/south_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/south_station/BiosCallOuts.h
+++ b/src/mainboard/amd/south_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 
diff --git a/src/mainboard/amd/union_station/BiosCallOuts.h b/src/mainboard/amd/union_station/BiosCallOuts.h
index b187fa2..750b59d 100644
--- a/src/mainboard/amd/union_station/BiosCallOuts.h
+++ b/src/mainboard/amd/union_station/BiosCallOuts.h
@@ -23,7 +23,6 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#define REQUIRED_CALLOUTS     12
 #define BIOS_HEAP_START_ADDRESS  0x00010000
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 


From gerrit at coreboot.org  Wed Jan 18 20:17:37 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Wed, 18 Jan 2012 20:17:37 +0100
Subject: [coreboot] Patch set updated for coreboot: 3e176ae Clean up AMD
	romstage.c serial output
References: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+0@gerrit.coreboot.org>
Message-ID: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+3@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/539

-gerrit

commit 3e176aefd315f1ca0932c510241b0b7f599fa6e3
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 16:51:24 2012 -0700

    Clean up AMD romstage.c serial output
    
    This cleans up the strings in romstage.c, removing the ugly "got past".
    Also, cleaned up comments and some spacing.
    
    Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
    Signed-off-by: Marc Jones <marcj303 at gmail.com>
---
 src/mainboard/amd/inagua/romstage.c        |   52 +++++++++++++-----------
 src/mainboard/amd/persimmon/romstage.c     |   60 ++++++++++++++++-----------
 src/mainboard/amd/south_station/romstage.c |   56 +++++++++++++++-----------
 src/mainboard/amd/torpedo/get_bus_conf.c   |   22 ++++------
 src/mainboard/amd/torpedo/romstage.c       |   60 ++++++++++++++-------------
 src/mainboard/amd/union_station/romstage.c |   54 +++++++++++++++----------
 src/mainboard/asrock/e350m1/romstage.c     |   60 +++++++++++++++------------
 7 files changed, 200 insertions(+), 164 deletions(-)

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index d5fa8c5..88c018e 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -63,47 +63,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
-	}
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index bf8535f..dfb1aca 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -9,12 +9,12 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #include <stdint.h>
@@ -46,12 +46,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -67,43 +69,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-	}
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -115,6 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }
diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c
index 95f27bd..8ebe7a6 100644
--- a/src/mainboard/amd/south_station/romstage.c
+++ b/src/mainboard/amd/south_station/romstage.c
@@ -43,12 +43,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr (0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -64,47 +66,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-	}
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);  // Should never see this post code.
+	post_code(0x54);  /* Should never see this post code. */
 }
 
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index 7dbe9a5..13eadaa 100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -54,7 +54,6 @@ u32 bus_type[256];
 
 u32 sbdn_sb900;
 
-//KZ [092110]extern void get_pci1234(void);
 
 static u32 get_bus_conf_done = 0;
 
@@ -70,8 +69,7 @@ void get_bus_conf(void)
 
 	get_bus_conf_done = 1;
 
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__);
 /*
  * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
  * but functionally within the coreboot model, this is the best place to make the
@@ -87,12 +85,12 @@ void get_bus_conf(void)
  * of each of the write functions called prior to the ACPI write functions, so this
  * becomes the best place for this call.
  */
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate ");
 	status = agesawrapper_amdinitlate();
-	if (status) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n",
-		       status);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
+	if (status)
+		printk(BIOS_DEBUG, "error level: %x \n", status);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	sbdn_sb900 = 0;
 
@@ -106,7 +104,6 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;	/* pci */
 
-//  bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
 	bus_sb900[0] = (pci1234x[0] >> 16) & 0xff;
 
 	/* sb900 */
@@ -114,7 +111,6 @@ void get_bus_conf(void)
 
 	if (dev) {
 		bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
 		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 		bus_isa++;
 		for (j = bus_sb900[1]; j < bus_isa; j++)
@@ -122,8 +118,7 @@ void get_bus_conf(void)
 	}
 
 	for (i = 0; i < 4; i++) {
-		dev =
-		    dev_find_slot(bus_sb900[0],
+		dev = dev_find_slot(bus_sb900[0],
 				  PCI_DEVFN(sbdn_sb900 + 0x14, i));
 		if (dev) {
 			bus_sb900[2 + i] =
@@ -139,6 +134,5 @@ void get_bus_conf(void)
 	bus_isa = 10;
 
 	sb_Late_Post();
-	printk(BIOS_DEBUG,
-	       "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+	printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__);
 }
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index ea902d8..2e1d8fc 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -45,12 +45,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
@@ -77,54 +77,56 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x36);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x38);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "sb_before_pci_init ");
 	sb_before_pci_init();
-	printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
+	printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
+	printk(BIOS_DEBUG, "setup_i8259\n");
 	setup_i8259();
-	printk(BIOS_DEBUG, "Got past setup_i8259\n");
 
 	/* Initialize i8254 timers */
 	post_code(0x42);
+	printk(BIOS_DEBUG, "setup_i8254\n");
 	setup_i8254();
-	printk(BIOS_DEBUG, "Got past setup_i8254\n");
+
 
 	post_code(0x43);
 	copy_and_run(0);
-	printk(BIOS_DEBUG, "Got past copy_and_run\n");
+	printk(BIOS_ERR, "Error: copy_and_run returned!\n");
 
 	post_code(0x44);	// Should never see this post code.
 }
diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c
index e7f05e8..26a05e8 100644
--- a/src/mainboard/amd/union_station/romstage.c
+++ b/src/mainboard/amd/union_station/romstage.c
@@ -43,8 +43,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
@@ -61,47 +63,55 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
-	}
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv ();
-	if(val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);  // Should never see this post code.
+	post_code(0x54);  /* Should never see this post code. */
 }
 
diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c
index 133aca7..8b46b19 100644
--- a/src/mainboard/asrock/e350m1/romstage.c
+++ b/src/mainboard/asrock/e350m1/romstage.c
@@ -47,12 +47,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	u32 val;
 	u8 reg8;
 
-	// all cores: allow caching of flash chip code and data
-	// (there are no cache-as-ram reliability concerns with family 14h)
+	/*
+	 * All cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
 	__writemsr(0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
 	__writemsr(0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
 
-	// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	/* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */
 	__writemsr(0xc0010062, 0);
 
 	if (!cpu_init_detectedx && boot_cpu()) {
@@ -68,47 +70,50 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x34);
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
 	post_code(0x35);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitmmio ");
 	val = agesawrapper_amdinitmmio();
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x37);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitreset ");
 	val = agesawrapper_amdinitreset();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
-		       val);
-	}
-
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x39);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitearly ");
 	val = agesawrapper_amdinitearly();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x40);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitpost ");
 	val = agesawrapper_amdinitpost();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	post_code(0x41);
+	printk(BIOS_DEBUG, "agesawrapper_amdinitenv ");
 	val = agesawrapper_amdinitenv();
-	if (val) {
-		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
-		       val);
-	}
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+	if (val)
+		printk(BIOS_DEBUG, "error level: %x \n", val);
+	else
+		printk(BIOS_DEBUG, "passed.\n");
 
 	/* Initialize i8259 pic */
 	post_code(0x41);
@@ -120,6 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x50);
 	copy_and_run(0);
+	printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
 
-	post_code(0x54);	// Should never see this post code.
+	post_code(0x54);	/* Should never see this post code. */
 }


From gerrit at coreboot.org  Wed Jan 18 23:01:21 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 23:01:21 +0100
Subject: [coreboot] Patch merged into coreboot/master: 4a10baf Remove old
	AMD #define
References: <I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef+0@gerrit.coreboot.org>
Message-ID: <E1RndZJ-0007pL-LK@ra.coresystems.de>

the following patch was just integrated into master:
commit 4a10bafe4a530f4ae3afc6ae5a1c692a702d9df6
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:30:31 2012 -0700

    Remove old AMD #define
    
    The #define REQUIRED_CALLOUTS is no longer used on these platforms.
    
    Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 20:58:50 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jan 18 22:58:05 2012, giving +2
See http://review.coreboot.org/540 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 23:01:29 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 23:01:29 +0100
Subject: [coreboot] Patch merged into coreboot/master: d579042 Remove
	duplicated line of code in AMD wrappers.
References: <I438da05c770ded0bd32256f1c157cabcc383667a+0@gerrit.coreboot.org>
Message-ID: <E1RndZR-0007sC-1I@ra.coresystems.de>

the following patch was just integrated into master:
commit d579042843cb3faf2e240730a1f7ef9ecba9ff89
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 17:34:03 2012 -0700

    Remove duplicated line of code in AMD wrappers.
    
    This line was unnecessary and was duplicated on several mainboards.
    
    Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 20:47:42 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jan 18 22:58:40 2012, giving +2
See http://review.coreboot.org/541 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 23:01:38 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 23:01:38 +0100
Subject: [coreboot] Patch merged into coreboot/master: 80f420e Add subsystem
	callbacks for VT8237x and VT890 family of chipsets
References: <Id34615f0c229d276d72cdf984cf82ea8cc1a85bb+0@gerrit.coreboot.org>
Message-ID: <E1RndZa-0007yq-Ch@ra.coresystems.de>

the following patch was just integrated into master:
commit 80f420e5d626dc84c98196c2b9dd9d58cd3ad1d5
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Fri Apr 22 20:48:21 2011 +0200

    Add subsystem callbacks for VT8237x and VT890 family of chipsets
    
    Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Build-Tested: build bot (Jenkins) at Sat Jan  7 15:30:25 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jan 18 23:00:46 2012, giving +2
See http://review.coreboot.org/523 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 23:09:25 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 18 Jan 2012 23:09:25 +0100
Subject: [coreboot] Patch merged into coreboot/master: 3e176ae Clean up AMD
	romstage.c serial output
References: <I0124df76eb442f8a0009a31a8632e4fd67ed7782+0@gerrit.coreboot.org>
Message-ID: <E1Rndh7-0000Xu-VK@ra.coresystems.de>

the following patch was just integrated into master:
commit 3e176aefd315f1ca0932c510241b0b7f599fa6e3
Author: Marc Jones <marcj303 at gmail.com>
Date:   Tue Jan 17 16:51:24 2012 -0700

    Clean up AMD romstage.c serial output
    
    This cleans up the strings in romstage.c, removing the ugly "got past".
    Also, cleaned up comments and some spacing.
    
    Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
    Signed-off-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jan 18 21:10:23 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jan 18 22:55:58 2012, giving +2
See http://review.coreboot.org/539 for details.

-gerrit


From gerrit at coreboot.org  Wed Jan 18 23:26:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 18 Jan 2012 23:26:42 +0100
Subject: [coreboot] New patch to review for coreboot: 7c77c17 Move SeaBIOS
	output out of coreboot source tree
References: <I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec+0@gerrit.coreboot.org>
Message-ID: <I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/552

-gerrit

commit 7c77c17c2998ba7b9e3ad4ae926a8030f50180ee
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Wed Jan 18 23:25:16 2012 +0100

    Move SeaBIOS output out of coreboot source tree
    
    Make sure SeaBIOS build files live under $(OUT) instead of
    in the source tree.
    
    Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 payloads/external/SeaBIOS/Makefile.inc |   30 +++++++++++++++---------------
 src/arch/x86/Makefile.inc              |    4 +++-
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 99d402c..5e34d6a 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -9,37 +9,37 @@ all: build
 
 seabios:
 	echo "    Cloning SeaBIOS from Git"
-	git clone git://git.seabios.org/seabios.git
+	cd $(OUT) && git clone git://git.seabios.org/seabios.git
 
 fetch: seabios
-	cd seabios; git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
+	cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
 	then echo "    Fetching new commits from the SeaBIOS git repo"; git fetch; fi
 
 checkout: fetch
 	echo "    Checking out SeaBIOS revision $(TAG-y)"
-	cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+	cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
 
 config: checkout
 	echo "    CONFIG     SeaBIOS $(TAG-y)"
-	$(MAKE) -C seabios defconfig
-	echo "CONFIG_COREBOOT=y" >> seabios/.config
-	echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config
-	echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> seabios/.config
-	echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config
-	echo "CONFIG_LZMA=y" >> seabios/.config
-	echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config
-	echo "CONFIG_VGAHOOKS=y" >> seabios/.config
+	$(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out
+	echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config
+	echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config
 	# This shows how to force a previously set .config option *off*
-	#echo "# CONFIG_SMBIOS is not set" >> seabios/.config
+	#echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config
 
 build: config
 	echo "    MAKE       SeaBIOS $(TAG-y)"
-	$(MAKE) -C seabios
+	$(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out
 
 clean:
-	test -d seabios && $(MAKE) -C seabios clean || exit 0
+	test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out || exit 0
 
 distclean:
-	rm -rf seabios
+	rm -rf $(OUT)/seabios
 
 .PHONY: checkout config build clean distclean clone fetch
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 54f0f82..3442b49 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -387,7 +387,9 @@ seabios:
 			CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
 			OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
 			CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
-			CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE)
+			CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \
+			OUT=$(abspath $(obj))/
+
 filo:
 	$(MAKE) -C payloads/external/FILO -f Makefile.inc \
 			HOSTCC="$(HOSTCC)" \


From gerrit at coreboot.org  Wed Jan 18 23:31:18 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 18 Jan 2012 23:31:18 +0100
Subject: [coreboot] New patch to review for coreboot: 5af98c9 Leave SSE and
	MMX instructions enabled in coreboot
References: <I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e+0@gerrit.coreboot.org>
Message-ID: <I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/553

-gerrit

commit 5af98c9e3b9c2dc27085247946a48346c33ea4cd
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Wed Jan 18 23:28:52 2012 +0100

    Leave SSE and MMX instructions enabled in coreboot
    
    In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
    instructions in the CPU after romstage.
    
    Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Makefile.inc   |    7 ------
 src/cpu/x86/mmx_disable.inc |   24 -----------------------
 src/cpu/x86/sse_disable.inc |   44 -------------------------------------------
 3 files changed, 0 insertions(+), 75 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 54f0f82..cbe38dd 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -204,13 +204,6 @@ endif
 
 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_disable.inc
-endif
-ifeq ($(CONFIG_MMX),y)
-crt0s += $(src)/cpu/x86/mmx_disable.inc
-endif
-
 ifeq ($(CONFIG_ROMCC),y)
 crt0s += $(src)/arch/x86/init/crt0_romcc_epilogue.inc
 endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/cpu/x86/mmx_disable.inc
deleted file mode 100644
index 1a4e70f..0000000
--- a/src/cpu/x86/mmx_disable.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm at xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
-
diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc
deleted file mode 100644
index 37458c9..0000000
--- a/src/cpu/x86/sse_disable.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm at xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Put the processor back into a reset state
-	 * with respect to the XMM registers.
-	 */
-	xorps %xmm0, %xmm0
-	xorps %xmm1, %xmm1
-	xorps %xmm2, %xmm2
-	xorps %xmm3, %xmm3
-	xorps %xmm4, %xmm4
-	xorps %xmm5, %xmm5
-	xorps %xmm6, %xmm6
-	xorps %xmm7, %xmm7
-
-	/*
-	 * Disable SSE instructions.
-	 *
-	 * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the
-	 * processor can no longer execute SSE instructions, and unmasked
-	 * SIMD floating point exceptions will generate an invalid opcode
-	 * exception (#UD).
-	 */
-	movl	%cr4, %eax
-	andl	$~(3 << 9), %eax
-	movl	%eax, %cr4
-


From Kerry.She at amd.com  Thu Jan 19 03:17:59 2012
From: Kerry.She at amd.com (She, Kerry)
Date: Thu, 19 Jan 2012 10:17:59 +0800
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local><CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com><F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com><F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
Message-ID: <F53A09371FB723428826B442A4B20A410908118E@sbjgexmb1.amd.com>

Hello, Wolfgang

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Wolfgang Kamp - datakamp
> Sent: Wednesday, January 18, 2012 11:11 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Kerry, hello Marc,
> 
> sounds good but solves not my problem. The enumeration of the SB800 GPP
> ports works fine with Linux.
> But coreboot fails because the SB GPP ports are not yet initialized when
> coreboot probes them.
> The function sbPcieGppEarlyInit will be executed after coreboot PCI
> probing of the SB GPP ports.
> You can see that in late.c.
> I put that function now in the right place in the case (0x15<<0 | 0)
> statement so probing succeeds.
> And my Intel LAN GB82574 will be enumerated as I can see in the log.
> But if I do that coreboot hangs in tables.c with postcode 0x9c and I
> can't imagine why.
It seems that there is a resource allocation problem.
If you have a smartprobe to trace the code, you can find out what memory address read/write fail in tables.c

Thanks
Kerry

> I need the correct enumeration in coreboot because the Intel LAN chip
> tools only works under DOS.
> 
> Wolfgang
> 
> -----Urspr?ngliche Nachricht-----
> Von: She, Kerry [mailto:Kerry.She at amd.com]
> Gesendet: Mittwoch, 18. Januar 2012 08:49
> An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org; chia, kenneth
> Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Marc and Wolfgang
> 
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org]
> > On Behalf Of She, Kerry
> > Sent: Tuesday, January 17, 2012 4:07 PM
> > To: Marc Jones; Wolfgang Kamp - datakamp
> > Cc: coreboot at coreboot.org
> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> >
> > Hello Walfqang,
> >
> > > -----Original Message-----
> > > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> > bounces at coreboot.org]
> > > On Behalf Of Marc Jones
> > > Sent: Tuesday, January 17, 2012 3:23 AM
> > > To: Wolfgang Kamp - datakamp
> > > Cc: coreboot at coreboot.org
> > > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
> > > Initialization
> > >
> > > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
> > > <wmkamp at datakamp.de> wrote:
> > > > Hello,
> > > >
> > > >
> > > >
> > > > I found a problem with the PCI enumeration of the PCIe Ports in
> > > > the CIMX/SB800 Southbridge for the INAGUA platform.
> > > >
> > > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
> > > > function sb_Before_PCI_Init after
> > > >
> > > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
> > > > <<3)
> > |
> > > 0
> > > > are probed in the routine ../devices/pci_device.c function
> > > >
> > > > pci_probe_dev they are not yet initialized. The probing fails and
> > also
> > > > devices behind the bridge are not recognized.
> > > >
> > > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> > > >
> > > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
> > > > <<3)
> > |
> > > 0 the
> > > > enumeration succeed but coreboot crashes later into nothing. The
> > > > Sage Debugger fails.
> > > >
> > > > I can't imagine why.
> > > >
> > > >
> > > >
> > > > Marc have you any idea?
> > >
> > > This looks like a problem in the sb800 cimx wrapper logic. Cimx
> > > doesn't treat the devices separately. it lumps all the configuration
> > > and enables together, making the coreboot chipset device enable
> > > callback fail to enable the device, so it gets disabled. The sb900
> > > wrapper appears to fix this issue with cimx setup in early init. You
> > > may want to try porting those changes to the sb800.
> > >
> > > I don't know why it fails later, but I assume it is due to the
> > > missing config since you moved the call earlier in the process. You
> > > could try calling it multiple times. I'm not sure how it handles that,
> though.
> > >
> > > Kerry,
> > > Do you have any comments?
> > If the enumeration fail, I suggest you should check the PCIE deassert
> > GPIO setting.
> > Thanks
> 
> I found the recent amd/inagua code in the git tree is not boot on my
> platform and more.
> I made an update to make my platform works now.
> The missing mainboard specific GPIO setting also added back, So the sb800
> GPP enumeration works now.
> 
> Please reference following link and the attachment.
> http://review.coreboot.org/#change,542
> http://review.coreboot.org/#change,543
> http://review.coreboot.org/#change,544
> http://review.coreboot.org/#change,545
> http://review.coreboot.org/#change,546
> 
> Thanks
> Kerry
> 
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From Kerry.She at amd.com  Thu Jan 19 03:34:10 2012
From: Kerry.She at amd.com (She, Kerry)
Date: Thu, 19 Jan 2012 10:34:10 +0800
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <CALrs_3jQBQG5k7DApO_MgUe5vozsce7yPJT3NQQmiZu5ETk+rg@mail.gmail.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local><CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com><F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com><F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com><4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
	<CALrs_3jQBQG5k7DApO_MgUe5vozsce7yPJT3NQQmiZu5ETk+rg@mail.gmail.com>
Message-ID: <F53A09371FB723428826B442A4B20A41090811CC@sbjgexmb1.amd.com>

Hello, Marc

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Marc Jones
> Sent: Thursday, January 19, 2012 2:28 AM
> To: Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> On Wed, Jan 18, 2012 at 8:11 AM, Wolfgang Kamp - datakamp
> <wmkamp at datakamp.de> wrote:
> > Hello Kerry, hello Marc,
> >
> > sounds good but solves not my problem. The enumeration of the SB800 GPP
> ports works fine with Linux.
> > But coreboot fails because the SB GPP ports are not yet initialized
> when coreboot probes them.
> > The function sbPcieGppEarlyInit will be executed after coreboot PCI
> probing of the SB GPP ports.
> > You can see that in late.c.
> > I put that function now in the right place in the case (0x15<<0 | 0)
> statement so probing succeeds.
> > And my Intel LAN GB82574 will be enumerated as I can see in the log.
> > But if I do that coreboot hangs in tables.c with postcode 0x9c and I
> can't imagine why.
> > I need the correct enumeration in coreboot because the Intel LAN chip
> tools only works under DOS.
> >
> > Wolfgang
> >
> 
> Kerry,
> 
> I agree with Wolfgang. I think that the sb800 has an issue.
> 
> >> > The sb900 wrapper appears to fix this issue with cimx setup in early
> init.
Yes, sb900 put the sb_before_pci_init wrapper call at romstage.
The problem is we can't get the configuration information from devicetree.cb in this way,
all the configuration option is defined in a header file.


> The device isn't visible in late init. The coreboot chip device scan
> will disable the device when it isn't found. The configuration needs
> to be set in early init like the sb900. Do you agree?
I think this is a compromise choice, we can unhide/hide the gpp device according to the devicetree.cb setting in sb800 dev_enable(), and then call the cimx function.


BTW. We using this way in the RD890 wrapper.
Thanks

Kerry

> Marc
> 
> 
> > -----Urspr?ngliche Nachricht-----
> > Von: She, Kerry [mailto:Kerry.She at amd.com]
> > Gesendet: Mittwoch, 18. Januar 2012 08:49
> > An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
> > Cc: coreboot at coreboot.org; chia, kenneth
> > Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> >
> > Hello Marc and Wolfgang
> >
> >> -----Original Message-----
> >> From: coreboot-bounces at coreboot.org
> >> [mailto:coreboot-bounces at coreboot.org]
> >> On Behalf Of She, Kerry
> >> Sent: Tuesday, January 17, 2012 4:07 PM
> >> To: Marc Jones; Wolfgang Kamp - datakamp
> >> Cc: coreboot at coreboot.org
> >> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> >>
> >> Hello Walfqang,
> >>
> >> > -----Original Message-----
> >> > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> >> bounces at coreboot.org]
> >> > On Behalf Of Marc Jones
> >> > Sent: Tuesday, January 17, 2012 3:23 AM
> >> > To: Wolfgang Kamp - datakamp
> >> > Cc: coreboot at coreboot.org
> >> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
> >> > Initialization
> >> >
> >> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
> >> > <wmkamp at datakamp.de> wrote:
> >> > > Hello,
> >> > >
> >> > >
> >> > >
> >> > > I found a problem with the PCI enumeration of the PCIe Ports in
> >> > > the CIMX/SB800 Southbridge for the INAGUA platform.
> >> > >
> >> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
> >> > > function sb_Before_PCI_Init after
> >> > >
> >> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
> >> > > <<3)
> >> |
> >> > 0
> >> > > are probed in the routine ../devices/pci_device.c function
> >> > >
> >> > > pci_probe_dev they are not yet initialized. The probing fails and
> >> also
> >> > > devices behind the bridge are not recognized.
> >> > >
> >> > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> >> > >
> >> > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
> >> > > <<3)
> >> |
> >> > 0 the
> >> > > enumeration succeed but coreboot crashes later into nothing. The
> >> > > Sage Debugger fails.
> >> > >
> >> > > I can't imagine why.
> >> > >
> >> > >
> >> > >
> >> > > Marc have you any idea?
> >> >
> >> > This looks like a problem in the sb800 cimx wrapper logic. Cimx
> >> > doesn't treat the devices separately. it lumps all the configuration
> >> > and enables together, making the coreboot chipset device enable
> >> > callback fail to enable the device, so it gets disabled. The sb900
> >> > wrapper appears to fix this issue with cimx setup in early init. You
> >> > may want to try porting those changes to the sb800.
> >> >
> >> > I don't know why it fails later, but I assume it is due to the
> >> > missing config since you moved the call earlier in the process. You
> >> > could try calling it multiple times. I'm not sure how it handles
> that, though.
> >> >
> >> > Kerry,
> >> > Do you have any comments?
> >> If the enumeration fail, I suggest you should check the PCIE deassert
> >> GPIO setting.
> >> Thanks
> >
> > I found the recent amd/inagua code in the git tree is not boot on my
> platform and more.
> > I made an update to make my platform works now.
> > The missing mainboard specific GPIO setting also added back, So the
> sb800 GPP enumeration works now.
> >
> > Please reference following link and the attachment.
> > http://review.coreboot.org/#change,542
> > http://review.coreboot.org/#change,543
> > http://review.coreboot.org/#change,544
> > http://review.coreboot.org/#change,545
> > http://review.coreboot.org/#change,546
> >
> > Thanks
> > Kerry
> >
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 
> 
> --
> http://se-eng.com
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From gerrit at coreboot.org  Thu Jan 19 05:33:40 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 19 Jan 2012 05:33:40 +0100
Subject: [coreboot] Patch set updated for coreboot: 9f6afb5 Inagua: Indent
	and wihtespace cleanup
References: <Ie574e08f138c88084c8ce06d0d0acc489013e3d7+0@gerrit.coreboot.org>
Message-ID: <Ie574e08f138c88084c8ce06d0d0acc489013e3d7+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/547

-gerrit

commit 9f6afb597ae330d2246182bb0878fb76bc1212bd
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Jan 19 13:25:55 2012 +0800

    Inagua: Indent and wihtespace cleanup
    
    Change-Id: Ie574e08f138c88084c8ce06d0d0acc489013e3d7
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/BiosCallOuts.c           |  980 ++++++++++----------
 src/mainboard/amd/inagua/BiosCallOuts.h           |   12 +-
 src/mainboard/amd/inagua/Kconfig                  |  135 ++--
 src/mainboard/amd/inagua/PlatformGnbPcie.c        |  204 +++---
 src/mainboard/amd/inagua/PlatformGnbPcieComplex.h |   15 +-
 src/mainboard/amd/inagua/acpi_tables.c            |    2 +-
 src/mainboard/amd/inagua/agesawrapper.c           |  148 ++--
 src/mainboard/amd/inagua/agesawrapper.h           |   18 +-
 src/mainboard/amd/inagua/buildOpts.c              |  208 +++---
 src/mainboard/amd/inagua/devicetree.cb            |  120 ++--
 src/mainboard/amd/inagua/dimmSpd.c                |  146 ++--
 src/mainboard/amd/inagua/get_bus_conf.c           |  158 ++--
 src/mainboard/amd/inagua/irq_tables.c             |    6 +-
 src/mainboard/amd/inagua/mainboard.c              |   30 +-
 src/mainboard/amd/inagua/mptable.c                |  140 ++--
 src/mainboard/amd/inagua/platform_cfg.h           |    8 +-
 16 files changed, 1163 insertions(+), 1167 deletions(-)

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index 434e83f..3c38239 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -26,494 +26,494 @@
 
 STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
-  {AGESA_ALLOCATE_BUFFER,
-   BiosAllocateBuffer
-  },
+	{AGESA_ALLOCATE_BUFFER,
+		BiosAllocateBuffer
+	},
 
-  {AGESA_DEALLOCATE_BUFFER,
-   BiosDeallocateBuffer
-  },
+	{AGESA_DEALLOCATE_BUFFER,
+		BiosDeallocateBuffer
+	},
 
-  {AGESA_DO_RESET,
-   BiosReset
-  },
+	{AGESA_DO_RESET,
+		BiosReset
+	},
 
-  {AGESA_LOCATE_BUFFER,
-   BiosLocateBuffer
-  },
+	{AGESA_LOCATE_BUFFER,
+		BiosLocateBuffer
+	},
 
-  {AGESA_READ_SPD,
-   BiosReadSpd
-  },
+	{AGESA_READ_SPD,
+		BiosReadSpd
+	},
 
-  {AGESA_READ_SPD_RECOVERY,
-   BiosDefaultRet
-  },
+	{AGESA_READ_SPD_RECOVERY,
+		BiosDefaultRet
+	},
 
-  {AGESA_RUNFUNC_ONAP,
-   BiosRunFuncOnAp
-  },
+	{AGESA_RUNFUNC_ONAP,
+		BiosRunFuncOnAp
+	},
 
 	{AGESA_GNB_PCIE_SLOT_RESET,
-	 BiosGnbPcieSlotReset
+		BiosGnbPcieSlotReset
 	},
 
 	{AGESA_HOOKBEFORE_DRAM_INIT,
-	 BiosHookBeforeDramInit
+		BiosHookBeforeDramInit
 	},
 
 	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
-	 BiosHookBeforeDramInitRecovery
-  },
+		BiosHookBeforeDramInitRecovery
+	},
 
-  {AGESA_HOOKBEFORE_DQS_TRAINING,
-   BiosHookBeforeDQSTraining
-  },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,
+		BiosHookBeforeDQSTraining
+	},
 
-  {AGESA_HOOKBEFORE_EXIT_SELF_REF,
-   BiosHookBeforeExitSelfRefresh
-  },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,
+		BiosHookBeforeExitSelfRefresh
+	},
 };
 
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINTN i;
-  AGESA_STATUS CalloutStatus;
+	UINTN i;
+	AGESA_STATUS CalloutStatus;
 	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
 
 	CalloutStatus = AGESA_UNSUPPORTED;
 
 	for (i = 0; i < CallOutCount; i++) {
 		if (BiosCallouts[i].CalloutName == Func) {
-  CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
-  return CalloutStatus;
-    }
-  }
+			CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+			return CalloutStatus;
+		}
+	}
 
 	return CalloutStatus;
 }
 
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AvailableHeapSize;
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              CurrNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              BestFitNodeOffset;
-  UINT32              BestFitPrevNodeOffset;
-  UINT32              NextFreeOffset;
-  BIOS_BUFFER_NODE   *CurrNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *BestFitNodePtr;
-  BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
-  BIOS_BUFFER_NODE   *NextFreePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
-  AllocParams->BufferPointer = NULL;
-
-  AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
-    /* First allocation */
-    CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-    CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
-    CurrNodePtr->BufferSize = AllocParams->BufferLength;
-    CurrNodePtr->NextNodeOffset = 0;
-    AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
-
-    /* Update the remaining free space */
-    FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
-    FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-    FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
-    FreedNodePtr->NextNodeOffset = 0;
-
-    /* Update the offsets for Allocated and Freed nodes */
-    BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
-    BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
-  } else {
-    /* Find out whether BufferHandle has been allocated on the heap. */
-    /* If it has, return AGESA_BOUNDS_CHK */
-    CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-    CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-
-    while (CurrNodeOffset != 0) {
-      CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
-      if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
-        return AGESA_BOUNDS_CHK;
-      }
-      CurrNodeOffset = CurrNodePtr->NextNodeOffset;
-      /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
-       to the end of the allocated nodes list.
-      */
-    }
-    /* Find the node that best fits the requested buffer size */
-    FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-    PrevNodeOffset = FreedNodeOffset;
-    BestFitNodeOffset = 0;
-    BestFitPrevNodeOffset = 0;
-    while (FreedNodeOffset != 0) {
-      FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-      if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        if (BestFitNodeOffset == 0) {
-          /* First node that fits the requested buffer size */
-          BestFitNodeOffset = FreedNodeOffset;
-          BestFitPrevNodeOffset = PrevNodeOffset;
-        } else {
-          /* Find out whether current node is a better fit than the previous nodes */
-          BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-          if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
-            BestFitNodeOffset = FreedNodeOffset;
-            BestFitPrevNodeOffset = PrevNodeOffset;
-          }
-        }
-      }
-      PrevNodeOffset = FreedNodeOffset;
-      FreedNodeOffset = FreedNodePtr->NextNodeOffset;
-    } /* end of while loop */
-
-
-    if (BestFitNodeOffset == 0) {
-      /* If we could not find a node that fits the requested buffer */
-      /* size, return AGESA_BOUNDS_CHK */
-      return AGESA_BOUNDS_CHK;
-    } else {
-      BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-      BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
-
-      /* If BestFitNode is larger than the requested buffer, fragment the node further */
-      if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
-        NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
-
-        NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
-        NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
-        NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
-      } else {
-        /* Otherwise, next free node is NextNodeOffset of BestFitNode */
-        NextFreeOffset = BestFitNodePtr->NextNodeOffset;
-      }
-
-      /* If BestFitNode is the first buffer in the list, then update
-         StartOfFreedNodes to reflect the new free node
-      */
-      if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
-        BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
-      } else {
-        BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
-      }
-
-      /* Add BestFitNode to the list of Allocated nodes */
-      CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
-      BestFitNodePtr->BufferSize = AllocParams->BufferLength;
-      BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
-      BestFitNodePtr->NextNodeOffset = 0;
-
-      /* Remove BestFitNode from list of Freed nodes */
-      AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
-    }
-  }
-
-  return AGESA_SUCCESS;
+	UINT32              AvailableHeapSize;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              CurrNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              BestFitNodeOffset;
+	UINT32              BestFitPrevNodeOffset;
+	UINT32              NextFreeOffset;
+	BIOS_BUFFER_NODE   *CurrNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *BestFitNodePtr;
+	BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+	BIOS_BUFFER_NODE   *NextFreePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+	AllocParams->BufferPointer = NULL;
+
+	AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+		/* First allocation */
+		CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+		CurrNodePtr->BufferSize = AllocParams->BufferLength;
+		CurrNodePtr->NextNodeOffset = 0;
+		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+		/* Update the remaining free space */
+		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+		FreedNodePtr->NextNodeOffset = 0;
+
+		/* Update the offsets for Allocated and Freed nodes */
+		BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+		BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+	} else {
+		/* Find out whether BufferHandle has been allocated on the heap. */
+		/* If it has, return AGESA_BOUNDS_CHK */
+		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+		while (CurrNodeOffset != 0) {
+			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+				return AGESA_BOUNDS_CHK;
+			}
+			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+			   to the end of the allocated nodes list.
+			   */
+		}
+		/* Find the node that best fits the requested buffer size */
+		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+		PrevNodeOffset = FreedNodeOffset;
+		BestFitNodeOffset = 0;
+		BestFitPrevNodeOffset = 0;
+		while (FreedNodeOffset != 0) {
+			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				if (BestFitNodeOffset == 0) {
+					/* First node that fits the requested buffer size */
+					BestFitNodeOffset = FreedNodeOffset;
+					BestFitPrevNodeOffset = PrevNodeOffset;
+				} else {
+					/* Find out whether current node is a better fit than the previous nodes */
+					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+						BestFitNodeOffset = FreedNodeOffset;
+						BestFitPrevNodeOffset = PrevNodeOffset;
+					}
+				}
+			}
+			PrevNodeOffset = FreedNodeOffset;
+			FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+		} /* end of while loop */
+
+
+		if (BestFitNodeOffset == 0) {
+			/* If we could not find a node that fits the requested buffer */
+			/* size, return AGESA_BOUNDS_CHK */
+			return AGESA_BOUNDS_CHK;
+		} else {
+			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+			/* If BestFitNode is larger than the requested buffer, fragment the node further */
+			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+			} else {
+				/* Otherwise, next free node is NextNodeOffset of BestFitNode */
+				NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+			}
+
+			/* If BestFitNode is the first buffer in the list, then update
+			   StartOfFreedNodes to reflect the new free node
+			   */
+			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+			} else {
+				BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+			}
+
+			/* Add BestFitNode to the list of Allocated nodes */
+			CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+			BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+			BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+			BestFitNodePtr->NextNodeOffset = 0;
+
+			/* Remove BestFitNode from list of Freed nodes */
+			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+		}
+	}
+
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 
-  UINT8               *BiosHeapBaseAddr;
-  UINT32              AllocNodeOffset;
-  UINT32              PrevNodeOffset;
-  UINT32              NextNodeOffset;
-  UINT32              FreedNodeOffset;
-  UINT32              EndNodeOffset;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_BUFFER_NODE   *PrevNodePtr;
-  BIOS_BUFFER_NODE   *FreedNodePtr;
-  BIOS_BUFFER_NODE   *NextNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
-
-  /* Find target node to deallocate in list of allocated nodes.
-     Return AGESA_BOUNDS_CHK if the BufferHandle is not found
-  */
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  PrevNodeOffset = AllocNodeOffset;
-
-  while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      return AGESA_BOUNDS_CHK;
-    }
-    PrevNodeOffset = AllocNodeOffset;
-    AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-    AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-  }
-
-  /* Remove target node from list of allocated nodes */
-  PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-  PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-
-  /* Zero out the buffer, and clear the BufferHandle */
-  LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
-  AllocNodePtr->BufferHandle = 0;
-  AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
-
-  /* Add deallocated node in order to the list of freed nodes */
-  FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-  FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
-
-  EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
-
-  if (AllocNodeOffset < FreedNodeOffset) {
-    /* Add to the start of the freed list */
-    if (EndNodeOffset == FreedNodeOffset) {
-      /* If the freed node is adjacent to the first node in the list, concatenate both nodes */
-      AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
-
-      /* Clear the BufferSize and NextNodeOffset of the previous first node */
-      FreedNodePtr->BufferSize = 0;
-      FreedNodePtr->NextNodeOffset = 0;
-    } else {
-      /* Otherwise, add freed node to the start of the list
-         Update NextNodeOffset and BufferSize to include the
-         size of BIOS_BUFFER_NODE
-      */
-      AllocNodePtr->NextNodeOffset = FreedNodeOffset;
-    }
-    /* Update StartOfFreedNodes to the new first node */
-    BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
-  } else {
-    /* Traverse list of freed nodes to find where the deallocated node
-       should be place
-    */
-    NextNodeOffset = FreedNodeOffset;
-    NextNodePtr = FreedNodePtr;
-    while (AllocNodeOffset > NextNodeOffset) {
-      PrevNodeOffset = NextNodeOffset;
-      if (NextNodePtr->NextNodeOffset == 0) {
-        break;
-      }
-      NextNodeOffset = NextNodePtr->NextNodeOffset;
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-    }
-
-    /* If deallocated node is adjacent to the next node,
-       concatenate both nodes
-    */
-    if (NextNodeOffset == EndNodeOffset) {
-      NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
-      AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
-      AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
-
-      NextNodePtr->BufferSize = 0;
-      NextNodePtr->NextNodeOffset = 0;
-    } else {
-      /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
-      AllocNodePtr->NextNodeOffset = NextNodeOffset;
-    }
-    /* If deallocated node is adjacent to the previous node,
-       concatenate both nodes
-    */
-    PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
-    EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
-    if (AllocNodeOffset == EndNodeOffset) {
-      PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
-      PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
-      AllocNodePtr->BufferSize = 0;
-      AllocNodePtr->NextNodeOffset = 0;
-    } else {
-      PrevNodePtr->NextNodeOffset = AllocNodeOffset;
-    }
-  }
-  return AGESA_SUCCESS;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              AllocNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              NextNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              EndNodeOffset;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_BUFFER_NODE   *PrevNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *NextNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	/* Find target node to deallocate in list of allocated nodes.
+	   Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+	   */
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	PrevNodeOffset = AllocNodeOffset;
+
+	while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			return AGESA_BOUNDS_CHK;
+		}
+		PrevNodeOffset = AllocNodeOffset;
+		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	}
+
+	/* Remove target node from list of allocated nodes */
+	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+	/* Zero out the buffer, and clear the BufferHandle */
+	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	AllocNodePtr->BufferHandle = 0;
+	AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+	/* Add deallocated node in order to the list of freed nodes */
+	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+	if (AllocNodeOffset < FreedNodeOffset) {
+		/* Add to the start of the freed list */
+		if (EndNodeOffset == FreedNodeOffset) {
+			/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+			AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+			/* Clear the BufferSize and NextNodeOffset of the previous first node */
+			FreedNodePtr->BufferSize = 0;
+			FreedNodePtr->NextNodeOffset = 0;
+		} else {
+			/* Otherwise, add freed node to the start of the list
+			   Update NextNodeOffset and BufferSize to include the
+			   size of BIOS_BUFFER_NODE
+			   */
+			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+		}
+		/* Update StartOfFreedNodes to the new first node */
+		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+	} else {
+		/* Traverse list of freed nodes to find where the deallocated node
+		   should be place
+		   */
+		NextNodeOffset = FreedNodeOffset;
+		NextNodePtr = FreedNodePtr;
+		while (AllocNodeOffset > NextNodeOffset) {
+			PrevNodeOffset = NextNodeOffset;
+			if (NextNodePtr->NextNodeOffset == 0) {
+				break;
+			}
+			NextNodeOffset = NextNodePtr->NextNodeOffset;
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+		}
+
+		/* If deallocated node is adjacent to the next node,
+		   concatenate both nodes
+		   */
+		if (NextNodeOffset == EndNodeOffset) {
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+			NextNodePtr->BufferSize = 0;
+			NextNodePtr->NextNodeOffset = 0;
+		} else {
+			/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+			AllocNodePtr->NextNodeOffset = NextNodeOffset;
+		}
+		/* If deallocated node is adjacent to the previous node,
+		   concatenate both nodes
+		   */
+		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+		if (AllocNodeOffset == EndNodeOffset) {
+			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+			AllocNodePtr->BufferSize = 0;
+			AllocNodePtr->NextNodeOffset = 0;
+		} else {
+			PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+		}
+	}
+	return AGESA_SUCCESS;
 }
 
 AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  UINT32              AllocNodeOffset;
-  UINT8               *BiosHeapBaseAddr;
-  BIOS_BUFFER_NODE   *AllocNodePtr;
-  BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
-  AGESA_BUFFER_PARAMS *AllocParams;
-
-  AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
-
-  BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
-  BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
-
-  AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-  AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	UINT32              AllocNodeOffset;
+	UINT8               *BiosHeapBaseAddr;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			AllocParams->BufferPointer = NULL;
+			AllocParams->BufferLength = 0;
+			return AGESA_BOUNDS_CHK;
+		} else {
+			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		}
+	}
+
+	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+	AllocParams->BufferLength = AllocNodePtr->BufferSize;
 
-  while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
-    if (AllocNodePtr->NextNodeOffset == 0) {
-      AllocParams->BufferPointer = NULL;
-      AllocParams->BufferLength = 0;
-      return AGESA_BOUNDS_CHK;
-    } else {
-      AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-      AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
-    }
-  }
-
-  AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
-  AllocParams->BufferLength = AllocNodePtr->BufferSize;
-
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 
 }
 
 AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
+	AGESA_STATUS        Status;
 
 	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
-  return Status;
+	return Status;
 }
 
 AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS        Status;
-  UINT8                 Value;
-  UINTN               ResetType;
-  AMD_CONFIG_PARAMS   *StdHeader;
-
-  ResetType = Data;
-  StdHeader = ConfigPtr;
-
-  //
-  // Perform the RESET based upon the ResetType. In case of
-  // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
-  // AmdResetManager. During the critical condition, where reset is required
-  // immediately, the reset will be invoked directly by writing 0x04 to port
-  // 0xCF9 (Reset Port).
-  //
-  switch (ResetType) {
-  case WARM_RESET_WHENEVER:
-  case COLD_RESET_WHENEVER:
-    break;
-
-  case WARM_RESET_IMMEDIATELY:
-  case COLD_RESET_IMMEDIATELY:
-      Value = 0x06;
-      LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
-    break;
-
-  default:
-    break;
-  }
-
-  Status = 0;
-  return Status;
+	AGESA_STATUS        Status;
+	UINT8                 Value;
+	UINTN               ResetType;
+	AMD_CONFIG_PARAMS   *StdHeader;
+
+	ResetType = Data;
+	StdHeader = ConfigPtr;
+
+	//
+	// Perform the RESET based upon the ResetType. In case of
+	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+	// AmdResetManager. During the critical condition, where reset is required
+	// immediately, the reset will be invoked directly by writing 0x04 to port
+	// 0xCF9 (Reset Port).
+	//
+	switch (ResetType) {
+		case WARM_RESET_WHENEVER:
+		case COLD_RESET_WHENEVER:
+			break;
+
+		case WARM_RESET_IMMEDIATELY:
+		case COLD_RESET_IMMEDIATELY:
+			Value = 0x06;
+			LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+			break;
+
+		default:
+			break;
+	}
+
+	Status = 0;
+	return Status;
 }
 
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
+	AGESA_STATUS Status;
 	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
 
-  return Status;
+	return Status;
 }
 
 AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_UNSUPPORTED;
+	return AGESA_UNSUPPORTED;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS      Status;
-  UINTN             FcnData;
-  MEM_DATA_STRUCT   *MemData;
-  UINT32            AcpiMmioAddr;
-  UINT32            GpioMmioAddr;
-  UINT8             Data8;
-  UINT16            Data16;
-  UINT8             TempData8;
-
-  FcnData = Data;
-  MemData = ConfigPtr;
-
-  Status  = AGESA_SUCCESS;
+	AGESA_STATUS      Status;
+	UINTN             FcnData;
+	MEM_DATA_STRUCT   *MemData;
+	UINT32            AcpiMmioAddr;
+	UINT32            GpioMmioAddr;
+	UINT8             Data8;
+	UINT16            Data16;
+	UINT8             TempData8;
+
+	FcnData = Data;
+	MemData = ConfigPtr;
+
+	Status  = AGESA_SUCCESS;
 	/* Get SB MMIO Base (AcpiMmioAddr) */
-  WriteIo8 (0xCD6, 0x27);
-  Data8   = ReadIo8(0xCD7);
-  Data16  = Data8<<8;
-  WriteIo8 (0xCD6, 0x26);
-  Data8   = ReadIo8(0xCD7);
-  Data16  |= Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
-  Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
-  Data8 &= ~BIT5;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x03;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  Data8 |= BIT2+BIT3;
-  Data8 &= ~BIT4;
-  TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-  TempData8 &= 0x23;
-  TempData8 |= Data8;
-  Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
-
-  switch(MemData->ParameterListPtr->DDR3Voltage){
-    case VOLT1_35:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_25:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-      break;
-    case VOLT1_5:
-    default:
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
-      Data8 |= (UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-      Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
-      Data8 &= ~(UINT8)BIT6;
-      Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
-  }
-  return Status;
+	WriteIo8 (0xCD6, 0x27);
+	Data8   = ReadIo8(0xCD7);
+	Data16  = Data8<<8;
+	WriteIo8 (0xCD6, 0x26);
+	Data8   = ReadIo8(0xCD7);
+	Data16  |= Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 &= ~BIT5;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
+	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 &= ~BIT5;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x03;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	Data8 |= BIT2+BIT3;
+	Data8 &= ~BIT4;
+	TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 &= 0x23;
+	TempData8 |= Data8;
+	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
+	switch(MemData->ParameterListPtr->DDR3Voltage){
+		case VOLT1_35:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 |= (UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+			break;
+		case VOLT1_25:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+			break;
+		case VOLT1_5:
+		default:
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
+			Data8 |= (UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
+			Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
+			Data8 &= ~(UINT8)BIT6;
+			Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+	}
+	return Status;
 }
 
 /*	Call the host environment interface to provide a user hook opportunity. */
@@ -525,82 +525,82 @@ AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *Con
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  return AGESA_SUCCESS;
+	return AGESA_SUCCESS;
 }
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
-  AGESA_STATUS Status;
-  UINTN                 FcnData;
-  PCIe_SLOT_RESET_INFO  *ResetInfo;
-
-  UINT32  GpioMmioAddr;
-  UINT32  AcpiMmioAddr;
-  UINT8   Data8;
-  UINT16  Data16;
-
-  FcnData   = Data;
-  ResetInfo = ConfigPtr;
-  // Get SB800 MMIO Base (AcpiMmioAddr)
-  WriteIo8(0xCD6, 0x27);
-  Data8 = ReadIo8(0xCD7);
-  Data16=Data8<<8;
-  WriteIo8(0xCD6, 0x26);
-  Data8 = ReadIo8(0xCD7);
-  Data16|=Data8;
-  AcpiMmioAddr = (UINT32)Data16 << 16;
-  Status = AGESA_UNSUPPORTED;
-  GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
-  switch (ResetInfo->ResetId)
-  {
-  case 4:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 6:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  case 7:
-		switch (ResetInfo->ResetControl) {
-      case AssertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
-        Data8 &= ~(UINT8)BIT6 ;
-        Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      case DeassertSlotReset:
-        Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
-        Data8 |= BIT6 ;
-        Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
-        Status = AGESA_SUCCESS;
-        break;
-      }
-      break;
-  }
-  return  Status;
+	AGESA_STATUS Status;
+	UINTN                 FcnData;
+	PCIe_SLOT_RESET_INFO  *ResetInfo;
+
+	UINT32  GpioMmioAddr;
+	UINT32  AcpiMmioAddr;
+	UINT8   Data8;
+	UINT16  Data16;
+
+	FcnData   = Data;
+	ResetInfo = ConfigPtr;
+	// Get SB800 MMIO Base (AcpiMmioAddr)
+	WriteIo8(0xCD6, 0x27);
+	Data8 = ReadIo8(0xCD7);
+	Data16=Data8<<8;
+	WriteIo8(0xCD6, 0x26);
+	Data8 = ReadIo8(0xCD7);
+	Data16|=Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	Status = AGESA_UNSUPPORTED;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	switch (ResetInfo->ResetId)
+	{
+		case 4:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);   // MXM_GPIO0. GPIO21
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8);       // MXM_GPIO0. GPIO21
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+		case 6:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);   // PCIE_RST#_LAN, GPIO25
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);       // PCIE_RST#_LAN, GPIO25
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+		case 7:
+			switch (ResetInfo->ResetControl) {
+				case AssertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+					Data8 &= ~(UINT8)BIT6 ;
+					Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);   // MPCIE_RST0, GPIO02
+					Status = AGESA_SUCCESS;
+					break;
+				case DeassertSlotReset:
+					Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+					Data8 |= BIT6 ;
+					Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8);       // MPCIE_RST0, GPIO02
+					Status = AGESA_SUCCESS;
+					break;
+			}
+			break;
+	}
+	return  Status;
 }
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index f7124b9..e713ac3 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -28,15 +28,15 @@
 #define BIOS_HEAP_SIZE       0x20000   /* 64MB */
 
 typedef struct _BIOS_HEAP_MANAGER {
-  //UINT32 AvailableSize;
-  UINT32 StartOfAllocatedNodes;
-  UINT32 StartOfFreedNodes;
+	//UINT32 AvailableSize;
+	UINT32 StartOfAllocatedNodes;
+	UINT32 StartOfFreedNodes;
 } BIOS_HEAP_MANAGER;
 
 typedef struct _BIOS_BUFFER_NODE {
-  UINT32 BufferHandle;
-  UINT32 BufferSize;
-  UINT32 NextNodeOffset;
+	UINT32 BufferHandle;
+	UINT32 BufferSize;
+	UINT32 NextNodeOffset;
 } BIOS_BUFFER_NODE;
 /*
  * CALLOUTS
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index b0c5f1a..a5920af 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -20,108 +20,108 @@
 if BOARD_AMD_INAGUA
 
 config BOARD_SPECIFIC_OPTIONS # dummy
-        def_bool y
-  select ARCH_X86
-  select CPU_AMD_AGESA_FAMILY14
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
-  select NORTHBRIDGE_AMD_AGESA_FAMILY14
-  select SOUTHBRIDGE_AMD_CIMX_SB800
-  select SUPERIO_SMSC_KBC1100
-  select BOARD_HAS_FADT
-        select HAVE_BUS_CONFIG
-        select HAVE_OPTION_TABLE
-        select HAVE_PIRQ_TABLE
-        select HAVE_MP_TABLE
-        select HAVE_MAINBOARD_RESOURCES
-        select HAVE_HARD_RESET
-        select SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        select LIFT_BSP_APIC_ID
-  select SERIAL_CPU_INIT
-  select AMDMCT
-        select HAVE_ACPI_TABLES
-  select BOARD_ROMSIZE_KB_2048
-  select ENABLE_APIC_EXT_ID
-        select GFXUMA
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_AGESA_FAMILY14
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY14
+	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SUPERIO_SMSC_KBC1100
+	select BOARD_HAS_FADT
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select AMDMCT
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_2048
+	select ENABLE_APIC_EXT_ID
+	select GFXUMA
 
 config AMD_AGESA
-        bool
-        default y
+	bool
+	default y
 
 config MAINBOARD_DIR
-        string
-        default amd/inagua
+	string
+	default amd/inagua
 
 config APIC_ID_OFFSET
-        hex
-        default 0x0
+	hex
+	default 0x0
 
 config MAINBOARD_PART_NUMBER
-        string
-        default "Inagua"
+	string
+	default "Inagua"
 
 config HW_MEM_HOLE_SIZEK
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config MAX_CPUS
-        int
-        default 2
+	int
+	default 2
 
 config MAX_PHYSICAL_CPUS
-        int
-        default 1
+	int
+	default 1
 
 config HW_MEM_HOLE_SIZE_AUTO_INC
-        bool
-        default n
+	bool
+	default n
 
 config MEM_TRAIN_SEQ
-        int
-        default 2
+	int
+	default 2
 
 config IRQ_SLOT_COUNT
-        int
-        default 11
+	int
+	default 11
 
 config RAMTOP
-        hex
-        default 0x1000000
+	hex
+	default 0x1000000
 
 config HEAP_SIZE
-        hex
-        default 0xc0000
+	hex
+	default 0xc0000
 
 config STACK_SIZE
-        hex
-        default 0x10000
+	hex
+	default 0x10000
 
 config ACPI_SSDTX_NUM
-        int
-        default 0
+	int
+	default 0
 
 config RAMBASE
-        hex
-        default 0x200000
+	hex
+	default 0x200000
 
 config SIO_PORT
-        hex
-        default 0x2e
+	hex
+	default 0x2e
 
 config DRIVERS_PS2_KEYBOARD
-        bool
-        default y
+	bool
+	default y
 
 config WARNINGS_ARE_ERRORS
-        bool
-        default n
+	bool
+	default n
 
 config ONBOARD_VGA_IS_PRIMARY
-        bool
-        default y
+	bool
+	default y
 
 config VGA_BIOS
-        bool
-        default n
+	bool
+	default n
 
 #config VGA_BIOS_FILE
 #        string "VGA BIOS path and filename"
@@ -129,14 +129,13 @@ config VGA_BIOS
 #        default "rom/video/OntarioGenericVBios.bin"
 
 config VGA_BIOS_ID
-        string "VGA device PCI IDs"
-        depends on VGA_BIOS
-        default "1002,9802"
+	string "VGA device PCI IDs"
+	depends on VGA_BIOS
+	default "1002,9802"
 
 config SB800_AHCI_ROM
-        bool
-        default n
-
+	bool
+	default n
 
 endif # BOARD_AMD_INAGUA
 
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index f758006..539ca48 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -44,8 +44,8 @@
 /*---------------------------------------------------------------------------------------*/
 VOID
 OemCustomizeInitEarly (
-	IN	OUT AMD_EARLY_PARAMS	*InitEarly
-	)
+		IN	OUT AMD_EARLY_PARAMS	*InitEarly
+		)
 {
 	AGESA_STATUS		 Status;
 	VOID				 *BrazosPcieComplexListPtr;
@@ -54,105 +54,105 @@ OemCustomizeInitEarly (
 
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
-PCIe_PORT_DESCRIPTOR PortList [] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
-        {
-          0,
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
-        }
-};
-
-PCIe_DDI_DESCRIPTOR DdiList [] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
-        {
-          0,   //Descriptor flags
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
-        },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
-        {
-          DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
-        }
-};
-
-PCIe_COMPLEX_DESCRIPTOR Brazos = {
-        DESCRIPTOR_TERMINATE_LIST,
-        0,
-        &PortList[0],
-        &DdiList[0]
-};
-
-  // GNB PCIe topology Porting
-
-  //
-  // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-  //
-  AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
-                                         sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
-                                         sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
-
-  AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
-  AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
-  Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
-  if ( Status!= AGESA_SUCCESS) {
-    // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
-    ASSERT(FALSE);
-	return;
-  }
-
-  BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
-  BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
-
-  AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
-  BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
-  LibAmdMemFill (BrazosPcieComplexListPtr,
-                   0,
-                   sizeof (PCIe_COMPLEX_DESCRIPTOR),
-                   &InitEarly->StdHeader);
-
-  LibAmdMemFill (BrazosPciePortPtr,
-                   0,
-                   sizeof (PCIe_PORT_DESCRIPTOR) * 5,
-                   &InitEarly->StdHeader);
-
-  LibAmdMemFill (BrazosPcieDdiPtr,
-                   0,
-                   sizeof (PCIe_DDI_DESCRIPTOR) * 2,
-                   &InitEarly->StdHeader);
-
-  LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
-  LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
-
-
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
-  ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
-
-  InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
-  InitEarly->GnbConfig.PsppPolicy      = 0;
+	PCIe_PORT_DESCRIPTOR PortList [] = {
+		// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
+		{
+			0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
+		{
+			0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
+		{
+			0,
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
+		},
+		// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
+			PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
+		}
+	};
+
+	PCIe_DDI_DESCRIPTOR DdiList [] = {
+		// Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
+		{
+			0,   //Descriptor flags
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+			PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
+		},
+		// Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
+		{
+			DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+			PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+			PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
+		}
+	};
+
+	PCIe_COMPLEX_DESCRIPTOR Brazos = {
+		DESCRIPTOR_TERMINATE_LIST,
+		0,
+		&PortList[0],
+		&DdiList[0]
+	};
+
+	// GNB PCIe topology Porting
+
+	//
+	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	//
+	AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+			sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+			sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
+
+	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+	if ( Status!= AGESA_SUCCESS) {
+		// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+		ASSERT(FALSE);
+		return;
+	}
+
+	BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+	BrazosPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
+	BrazosPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	LibAmdMemFill (BrazosPcieComplexListPtr,
+			0,
+			sizeof (PCIe_COMPLEX_DESCRIPTOR),
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (BrazosPciePortPtr,
+			0,
+			sizeof (PCIe_PORT_DESCRIPTOR) * 5,
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (BrazosPcieDdiPtr,
+			0,
+			sizeof (PCIe_DDI_DESCRIPTOR) * 2,
+			&InitEarly->StdHeader);
+
+	LibAmdMemCopy  (BrazosPcieComplexListPtr, &Brazos, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+	LibAmdMemCopy  (BrazosPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 5, &InitEarly->StdHeader);
+	LibAmdMemCopy  (BrazosPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) *2, &InitEarly->StdHeader);
+
+
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
+
+	InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+	InitEarly->GnbConfig.PsppPolicy      = 0;
 }
 
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index b51089f..6477892 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -29,7 +29,7 @@
 #define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port5
@@ -37,7 +37,7 @@
 #define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port6
@@ -45,7 +45,7 @@
 #define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port7
@@ -53,7 +53,7 @@
 #define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
 //GNB GPP Port8
@@ -61,12 +61,9 @@
 #define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
 #define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
 #define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
-                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
 
-VOID
-OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  );
+VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS    *InitEarly);
 
 #endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 8ed7d4f..8f47591 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -86,7 +86,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 	/* Write SB800 IOAPIC, only one */
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
+			CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 			current, 0, 0, 2, 0);
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index fe2fe6b..113f962 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -78,8 +78,8 @@ VOID *AcpiAlib		= NULL;
  */
 UINT32
 agesawrapper_amdinitcpuio (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS				Status;
 	UINT64						MsrReg;
@@ -127,8 +127,8 @@ agesawrapper_amdinitcpuio (
 
 UINT32
 agesawrapper_amdinitmmio (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS				Status;
 	UINT64						MsrReg;
@@ -141,9 +141,9 @@ agesawrapper_amdinitmmio (
 	UINT8						Index;
 
 	/*
-	 Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	 Address MSR register.
-	*/
+	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	   Address MSR register.
+	   */
 
 	for (Index = 0; Index < 8; Index++) {
 		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
@@ -157,8 +157,8 @@ agesawrapper_amdinitmmio (
 	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
 
 	/*
-	 Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
-	*/
+	   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	   */
 	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
 	MsrReg = MsrReg | 0x0000400000000000ull;
 	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
@@ -177,22 +177,22 @@ agesawrapper_amdinitmmio (
 
 UINT32
 agesawrapper_amdinitreset (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_RESET_PARAMS AmdResetParams;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	LibAmdMemFill (&AmdResetParams,
-					0,
-					sizeof (AMD_RESET_PARAMS),
-					&(AmdResetParams.StdHeader));
+			0,
+			sizeof (AMD_RESET_PARAMS),
+			&(AmdResetParams.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
 	AmdParamStruct.AllocationMethod = ByHost;
@@ -209,21 +209,21 @@ agesawrapper_amdinitreset (
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	AmdReleaseStruct (&AmdParamStruct);
 	return (UINT32)status;
- }
+}
 
 UINT32
 agesawrapper_amdinitearly (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_EARLY_PARAMS	 *AmdEarlyParamsPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -245,8 +245,8 @@ agesawrapper_amdinitearly (
 
 UINT32
 agesawrapper_amdinitpost (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	UINT16					i;
@@ -255,9 +255,9 @@ agesawrapper_amdinitpost (
 	BIOS_HEAP_MANAGER		*BiosManagerPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
 	AmdParamStruct.AllocationMethod = PreMemHeap;
@@ -287,8 +287,8 @@ agesawrapper_amdinitpost (
 
 UINT32
 agesawrapper_amdinitenv (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
@@ -296,9 +296,9 @@ agesawrapper_amdinitenv (
 	UINT32				 PciValue;
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -311,7 +311,7 @@ agesawrapper_amdinitenv (
 	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
 	/* Initialize Subordinate Bus Number and Secondary Bus Number
 	 * In platform BIOS this address is allocated by PCI enumeration code
-		 Modify D1F0x18
+	 Modify D1F0x18
 	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
@@ -323,8 +323,8 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize GMM Base Address for Legacy Bridge Mode
-	*	Modify B1D5F0x18
-	*/
+	 *	Modify B1D5F0x18
+	 */
 	PciAddress.Address.Bus = 1;
 	PciAddress.Address.Device = 5;
 	PciAddress.Address.Function = 0;
@@ -335,16 +335,16 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize FB Base Address for Legacy Bridge Mode
-	* Modify B1D5F0x10
-	*/
+	 * Modify B1D5F0x10
+	 */
 	PciAddress.Address.Register = 0x10;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x80000000;
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize GMM Base Address for Pcie Mode
-	*	Modify B0D1F0x18
-	*/
+	 *	Modify B0D1F0x18
+	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
 	PciAddress.Address.Function = 0;
@@ -355,16 +355,16 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize FB Base Address for Pcie Mode
-	*	Modify B0D1F0x10
-	*/
+	 *	Modify B0D1F0x10
+	 */
 	PciAddress.Address.Register = 0x10;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x80000000;
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize MMIO Base and Limit Address
-	*	Modify B0D1F0x20
-	*/
+	 *	Modify B0D1F0x20
+	 */
 	PciAddress.Address.Bus = 0;
 	PciAddress.Address.Device = 1;
 	PciAddress.Address.Function = 0;
@@ -375,8 +375,8 @@ agesawrapper_amdinitenv (
 	LibAmdPciWrite (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
 	/* Initialize MMIO Prefetchable Memory Limit and Base
-	*	Modify B0D1F0x24
-	*/
+	 *	Modify B0D1F0x24
+	 */
 	PciAddress.Address.Register = 0x24;
 	LibAmdPciRead (AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 	PciValue |= 0x8FF18001;
@@ -388,8 +388,8 @@ agesawrapper_amdinitenv (
 
 VOID *
 agesawrapper_getlateinitptr (
-	int pick
-	)
+		int pick
+		)
 {
 	switch (pick) {
 		case PICK_DMI:
@@ -413,8 +413,8 @@ agesawrapper_getlateinitptr (
 
 UINT32
 agesawrapper_amdinitmid (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
@@ -423,9 +423,9 @@ agesawrapper_amdinitmid (
 	agesawrapper_amdinitcpuio ();
 
 	LibAmdMemFill (&AmdParamStruct,
-					0,
-					sizeof (AMD_INTERFACE_PARAMS),
-					&(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -445,17 +445,17 @@ agesawrapper_amdinitmid (
 
 UINT32
 agesawrapper_amdinitlate (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS Status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
 	AMD_LATE_PARAMS * AmdLateParamsPtr;
 
 	LibAmdMemFill (&AmdParamStruct,
-		       0,
-		       sizeof (AMD_INTERFACE_PARAMS),
-		       &(AmdParamStruct.StdHeader));
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
 
 	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
 	AmdParamStruct.AllocationMethod = PostMemDram;
@@ -484,10 +484,10 @@ agesawrapper_amdinitlate (
 	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
 	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
-		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
-		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
-		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
-		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+			"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+			"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+			__func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+			AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
 
 	/* Don't release the structure until coreboot has copied the ACPI tables.
 	 * AmdReleaseStruct (&AmdLateParams);
@@ -498,18 +498,18 @@ agesawrapper_amdinitlate (
 
 UINT32
 agesawrapper_amdlaterunaptask (
-	UINT32 Func,
-	UINT32 Data,
-	VOID *ConfigPtr
-	)
+		UINT32 Func,
+		UINT32 Data,
+		VOID *ConfigPtr
+		)
 {
 	AGESA_STATUS Status;
 	AP_EXE_PARAMS ApExeParams;
 
 	LibAmdMemFill (&ApExeParams,
-				 0,
-				 sizeof (AP_EXE_PARAMS),
-				 &(ApExeParams.StdHeader));
+			0,
+			sizeof (AP_EXE_PARAMS),
+			&(ApExeParams.StdHeader));
 
 	ApExeParams.StdHeader.AltImageBasePtr = 0;
 	ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
@@ -529,16 +529,16 @@ agesawrapper_amdlaterunaptask (
 
 UINT32
 agesawrapper_amdreadeventlog (
-	VOID
-	)
+		VOID
+		)
 {
 	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
 
 	LibAmdMemFill (&AmdEventParams,
-					0,
-					sizeof (EVENT_PARAMS),
-					&(AmdEventParams.StdHeader));
+			0,
+			sizeof (EVENT_PARAMS),
+			&(AmdEventParams.StdHeader));
 
 	AmdEventParams.StdHeader.AltImageBasePtr = 0;
 	AmdEventParams.StdHeader.CalloutPtr = NULL;
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index f8d924e..3e819b7 100644
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -39,13 +39,13 @@
 #define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
 
 enum {
-  PICK_DMI,       /* DMI Interface */
-  PICK_PSTATE,    /* Acpi Pstate SSDT Table */
-  PICK_SRAT,      /* SRAT Table */
-  PICK_SLIT,      /* SLIT Table */
-  PICK_WHEA_MCE,  /* WHEA MCE table */
-  PICK_WHEA_CMC,  /* WHEA CMV table */
-  PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+	PICK_DMI,       /* DMI Interface */
+	PICK_PSTATE,    /* Acpi Pstate SSDT Table */
+	PICK_SRAT,      /* SRAT Table */
+	PICK_SLIT,      /* SLIT Table */
+	PICK_WHEA_MCE,  /* WHEA MCE table */
+	PICK_WHEA_CMC,  /* WHEA CMV table */
+	PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
 };
 
 /*----------------------------------------------------------------------------------------
@@ -54,8 +54,8 @@ enum {
  */
 
 typedef struct {
-  UINT32 CalloutName;
-  AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+	UINT32 CalloutName;
+	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
 } BIOS_CALLOUT_STRUCT;
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 6506c2e..49eb7bf 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -89,12 +89,12 @@
 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
-  #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
-  #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSD        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
+#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
+#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
 #define BLDOPT_REMOVE_SRAT						FALSE
 #define BLDOPT_REMOVE_SLIT						FALSE
 #define BLDOPT_REMOVE_WHEA						FALSE
@@ -329,65 +329,65 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  *  use its default conservative settings.
  */
 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
-  //
-  // The following macros are supported (use comma to separate macros):
-  //
-  // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
-  //      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
-  //      AGESA will base on this value to disable unused MemClk to save power.
-  //      Example:
-  //      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
-  //           Bit AM3/S1g3 pin name
-  //           0   M[B,A]_CLK_H/L[0]
-  //           1   M[B,A]_CLK_H/L[1]
-  //           2   M[B,A]_CLK_H/L[2]
-  //           3   M[B,A]_CLK_H/L[3]
-  //           4   M[B,A]_CLK_H/L[4]
-  //           5   M[B,A]_CLK_H/L[5]
-  //           6   M[B,A]_CLK_H/L[6]
-  //           7   M[B,A]_CLK_H/L[7]
-  //      And platform has the following routing:
-  //           CS0   M[B,A]_CLK_H/L[4]
-  //           CS1   M[B,A]_CLK_H/L[2]
-  //           CS2   M[B,A]_CLK_H/L[3]
-  //           CS3   M[B,A]_CLK_H/L[5]
-  //      Then platform can specify the following macro:
-  //      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
-  //
-  // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
-  //      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
-  //      AGESA will base on this value to tristate unused CKE to save power.
-  //
-  // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
-  //      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
-  //      AGESA will base on this value to tristate unused ODT pins to save power.
-  //
-  // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
-  //      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
-  //      AGESA will base on this value to tristate unused Chip select to save power.
-  //
-  // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
-  //      Specifies the number of DIMM slots per channel.
-  //
-  // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
-  //      Specifies the number of Chip selects per channel.
-  //
-  // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
-  //      Specifies the number of channels per socket.
-  //
-  // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
-  //      Specifies DDR bus speed of channel ChannelID on socket SocketID.
-  //
-  // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
-  //      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
-  //
-  // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
-  //      Byte6Seed, Byte7Seed, ByteEccSeed)
-  //      Specifies the write leveling seed for a channel of a socket.
-  //
-  NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
-  NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
-  PSO_END
+	//
+	// The following macros are supported (use comma to separate macros):
+	//
+	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+	//      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+	//      AGESA will base on this value to disable unused MemClk to save power.
+	//      Example:
+	//      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+	//           Bit AM3/S1g3 pin name
+	//           0   M[B,A]_CLK_H/L[0]
+	//           1   M[B,A]_CLK_H/L[1]
+	//           2   M[B,A]_CLK_H/L[2]
+	//           3   M[B,A]_CLK_H/L[3]
+	//           4   M[B,A]_CLK_H/L[4]
+	//           5   M[B,A]_CLK_H/L[5]
+	//           6   M[B,A]_CLK_H/L[6]
+	//           7   M[B,A]_CLK_H/L[7]
+	//      And platform has the following routing:
+	//           CS0   M[B,A]_CLK_H/L[4]
+	//           CS1   M[B,A]_CLK_H/L[2]
+	//           CS2   M[B,A]_CLK_H/L[3]
+	//           CS3   M[B,A]_CLK_H/L[5]
+	//      Then platform can specify the following macro:
+	//      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+	//
+	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+	//      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+	//      AGESA will base on this value to tristate unused CKE to save power.
+	//
+	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+	//      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+	//      AGESA will base on this value to tristate unused ODT pins to save power.
+	//
+	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+	//      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+	//      AGESA will base on this value to tristate unused Chip select to save power.
+	//
+	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+	//      Specifies the number of DIMM slots per channel.
+	//
+	// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
+	//      Specifies the number of Chip selects per channel.
+	//
+	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+	//      Specifies the number of channels per socket.
+	//
+	// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
+	//      Specifies DDR bus speed of channel ChannelID on socket SocketID.
+	//
+	// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
+	//      Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
+	//
+	// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+	//      Byte6Seed, Byte7Seed, ByteEccSeed)
+	//      Specifies the write leveling seed for a channel of a socket.
+	//
+	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+	NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
+	PSO_END
 };
 
 /*
@@ -399,45 +399,45 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 //DA Customer table
 CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
 {
- // Hardcoded Memory Training Values
-
- // The following macro should be used to override training values for your platform
- //
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
- //
- //   NOTE:
- //   The following training hardcode values are example values that were taken from a tilapia motherboard
- //   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
- //   the table and replace the byte lane values with your own.
- //
- //                                                                               ------------------ BYTE LANES ----------------------
- //                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
- // Write Data Timing
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
- // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
-
- // DQS Receiver Enable
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
- // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
-
- // Write DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
-
- // Read DQS Delays
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
- // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
- //--------------------------------------------------------------------------------------------------------------------------------------------------
- // TABLE END
-  NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+	// Hardcoded Memory Training Values
+
+	// The following macro should be used to override training values for your platform
+	//
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+	//
+	//   NOTE:
+	//   The following training hardcode values are example values that were taken from a tilapia motherboard
+	//   with a particular DIMM configuration.  To hardcode your own values, uncomment the appropriate line in
+	//   the table and replace the byte lane values with your own.
+	//
+	//                                                                               ------------------ BYTE LANES ----------------------
+	//                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+	// Write Data Timing
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+	// DQS Receiver Enable
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+	// Write DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+	// Read DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+	//--------------------------------------------------------------------------------------------------------------------------------------------------
+	// TABLE END
+	NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
 };
 CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
 
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 60bb29b..100a5cc 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -17,56 +17,56 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 chip northbridge/amd/agesa/family14/root_complex
-        device lapic_cluster 0 on
-                chip cpu/amd/agesa/family14
-                  device lapic 0 on end
-                end
-        end
-        device pci_domain 0 on
-                subsystemid 0x1022 0x1510 inherit
-                chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-#                       device pci 18.0 on #  northbridge
-                                chip northbridge/amd/agesa/family14 # PCI side of HT root complex
-                                        device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
-                                        device pci 1.1 on end # Internal Multimedia
-                                        device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
-                                        device pci 5.0 off end # PCIE P2P bridge MXM lane 1
-                                        device pci 6.0 on end # PCIE P2P bridge  LAN
-                                        device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
-                                        device pci 8.0 off end # NB/SB Link P2P bridge
-                                end # agesa northbridge
+	device lapic_cluster 0 on
+		chip cpu/amd/agesa/family14
+			device lapic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x1510 inherit
+		chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+#			device pci 18.0 on #  northbridge
+				chip northbridge/amd/agesa/family14 # PCI side of HT root complex
+					device pci 0.0 on end # Root Complex
+					device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
+					device pci 1.1 on end # Internal Multimedia
+					device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
+					device pci 5.0 off end # PCIE P2P bridge MXM lane 1
+					device pci 6.0 on end # PCIE P2P bridge  LAN
+					device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
+					device pci 8.0 off end # NB/SB Link P2P bridge
+				end # agesa northbridge
 
-                                chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
-                                        device pci 11.0 on end # SATA
-                                        device pci 12.0 on end # USB
-                                        device pci 12.1 on end # USB
-                                        device pci 12.2 on end # USB
-                                        device pci 13.0 on end # USB
-                                        device pci 13.1 on end # USB
-                                        device pci 13.2 on end # USB
-                                        device pci 14.0 on # SM
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end
-                                                end
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end
-                                        end # SM
-                                        device pci 14.1 on end # IDE    0x439c
-                                        device pci 14.2 on end # HDA    0x4383
-                                        device pci 14.3 on # LPC        0x439d
-					        chip superio/smsc/kbc1100
-                                                        device pnp 2e.7 on #  Keyboard
-                                                                io 0x60 = 0x60
-                                                                io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                                irq 0x72 = 12
-                                                        end
-                                                end # kbc1100
+				chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB
+					device pci 12.1 on end # USB
+					device pci 12.2 on end # USB
+					device pci 13.0 on end # USB
+					device pci 13.1 on end # USB
+					device pci 13.2 on end # USB
+					device pci 14.0 on # SM
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x439c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x439d
+						chip superio/smsc/kbc1100
+							device pnp 2e.7 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+						end # kbc1100
 					end #LPC
 					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
-	  				device pci 14.5 on end # USB 2
+					device pci 14.5 on end # USB 2
 					device pci 15.0 on end # PCIe PortA  Express Card
 					device pci 15.1 on end # PCIe PortB  NEC USB3.0
 					device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
@@ -74,20 +74,20 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 16.0 on end # OHCI USB3
 					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
-		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
+					register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
-#                       end #  device pci 18.0
+#			end #  device pci 18.0
 # These seem unnecessary
-                        device pci 18.0 on end
-                        #device pci 18.0 on end
-                        device pci 18.1 on end
-                        device pci 18.2 on end
-                        device pci 18.3 on end
-                        device pci 18.4 on end
-                        device pci 18.5 on end
-                        device pci 18.6 on end
-                        device pci 18.7 on end
-                end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
-        end #pci_domain
+			device pci 18.0 on end
+			#device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+			device pci 18.6 on end
+			device pci 18.7 on end
+		end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
+	end #pci_domain
 end #northbridge/amd/agesa/family14/root_complex
 
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index 3719112..7a8e82a 100644
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -26,19 +26,19 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
 
 /*#pragma optimize ("", off) // for source level debug
-*---------------------------------------------------------------------------
-*
-* SPD address table - porting required
-*/
+ *---------------------------------------------------------------------------
+ *
+ * SPD address table - porting required
+ */
 
 static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
-   {
-   // socket 0
-      {
-         {0xA0, 0xA2},  // channel 0 dimms
-         {0x00, 0x00},  // channel 1 dimms
-      },
-   };
+{
+	// socket 0
+	{
+		{0xA0, 0xA2},  // channel 0 dimms
+		{0x00, 0x00},  // channel 1 dimms
+	},
+};
 
 /*-----------------------------------------------------------------------------
  *
@@ -47,30 +47,30 @@ static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
 
 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 {
-   unsigned int status;
-   UINT64 limit;
+	unsigned int status;
+	UINT64 limit;
 
-   address |= 1; // set read bit
+	address |= 1; // set read bit
 
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 1, 0x1F);                // clear error status
-   __outbyte (iobase + 3, offset);              // offset in eeprom
-   __outbyte (iobase + 4, address);             // slave address and read bit
-   __outbyte (iobase + 2, 0x48);                // read byte command
+	__outbyte (iobase + 0, 0xFF);                // clear error status
+	__outbyte (iobase + 1, 0x1F);                // clear error status
+	__outbyte (iobase + 3, offset);              // offset in eeprom
+	__outbyte (iobase + 4, address);             // slave address and read bit
+	__outbyte (iobase + 2, 0x48);                // read byte command
 
-   // time limit to avoid hanging for unexpected error status (should never happen)
-   limit = __rdtsc () + 2000000000 / 10;
+	// time limit to avoid hanging for unexpected error status (should never happen)
+	limit = __rdtsc () + 2000000000 / 10;
 	for (;;) {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;                      // check for done with no errors
+	return status;
 }
 
 /*-----------------------------------------------------------------------------
@@ -81,25 +81,25 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 
 static int readSmbusByte (int iobase, int address, char *buffer)
 {
-   unsigned int status;
-   UINT64 limit;
+	unsigned int status;
+	UINT64 limit;
 
-   __outbyte (iobase + 0, 0xFF);                // clear error status
-   __outbyte (iobase + 2, 0x44);                // read command
+	__outbyte (iobase + 0, 0xFF);                // clear error status
+	__outbyte (iobase + 2, 0x44);                // read command
 
-   // time limit to avoid hanging for unexpected error status
-   limit = __rdtsc () + 2000000000 / 10;
+	// time limit to avoid hanging for unexpected error status
+	limit = __rdtsc () + 2000000000 / 10;
 	for (;;) {
-      status = __inbyte (iobase);
-      if (__rdtsc () > limit) break;
-      if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-      if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
-      break;
-      }
-
-   buffer [0] = __inbyte (iobase + 5);
-   if (status == 2) status = 0;                      // check for done with no errors
-   return status;
+		status = __inbyte (iobase);
+		if (__rdtsc () > limit) break;
+		if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	buffer [0] = __inbyte (iobase + 5);
+	if (status == 2) status = 0;                      // check for done with no errors
+	return status;
 }
 
 /*---------------------------------------------------------------------------
@@ -113,47 +113,47 @@ static int readSmbusByte (int iobase, int address, char *buffer)
 
 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
 {
-   int index, error;
+	int index, error;
 
-   /* read the first byte using offset zero */
-   error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
-   if (error) return error;
+	/* read the first byte using offset zero */
+	error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0);
+	if (error) return error;
 
-   /* read the remaining bytes using auto-increment for speed */
+	/* read the remaining bytes using auto-increment for speed */
 	for (index = 1; index < count; index++) {
-      error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
-      if (error) return error;
-      }
+		error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
+		if (error) return error;
+	}
 
-   return 0;
+	return 0;
 }
 
 static void writePmReg (int reg, int data)
-   {
-   __outbyte (0xCD6, reg);
-   __outbyte (0xCD7, data);
-   }
+{
+	__outbyte (0xCD6, reg);
+	__outbyte (0xCD7, data);
+}
 
 static void setupFch (int ioBase)
 {
-   writePmReg (0x2D, ioBase >> 8);
-   writePmReg (0x2C, ioBase | 1);
-   writePmReg (0x29, 0x80);
-   writePmReg (0x28, 0x61);
-   __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
+	writePmReg (0x2D, ioBase >> 8);
+	writePmReg (0x2C, ioBase | 1);
+	writePmReg (0x29, 0x80);
+	writePmReg (0x28, 0x61);
+	__outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
 }
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
 {
-   int spdAddress, ioBase;
+	int spdAddress, ioBase;
 
-   if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
-   if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
-   if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
+	if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
+	if (info->MemChannelId >= DIMENSION (spdAddressLookup[0]   )) return AGESA_ERROR;
+	if (info->DimmId       >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
 
-   spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
-   if (spdAddress == 0) return AGESA_ERROR;
+	spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+	if (spdAddress == 0) return AGESA_ERROR;
 	ioBase = SMBUS0_BASE_ADDRESS;
-   setupFch (ioBase);
-   return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
+	setupFch (ioBase);
+	return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
 }
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index 13d198a..229477d 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -31,19 +31,19 @@
 
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
+ * and acpi_tables busnum is default.
+ */
 u8 bus_isa;
 u8 bus_sb800[3];
 u32 apicid_sb800;
 
 /*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
 u32 pci1234x[] = {
-  0x0000ff0,
+	0x0000ff0,
 };
 
 u32 bus_type[256];
@@ -55,81 +55,81 @@ static u32 get_bus_conf_done = 0;
 void get_bus_conf(void)
 {
 	u32 apicid_base;
-  u32 status;
-
-  device_t dev;
-  int i, j;
-
-  if (get_bus_conf_done == 1)
-    return;   /* do it only once */
-
-  get_bus_conf_done = 1;
-
-/*
- * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
- * but functionally within the coreboot model, this is the best place to make the
- * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM.  The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain".  There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions.  The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written.  This routine is called at the beginning
- * of each of the write functions called prior to the ACPI write functions, so this
- * becomes the best place for this call.
- */
-  status = agesawrapper_amdinitlate();
-  if(status) {
-    printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-  }
-
-  sbdn_sb800 = 0;
-
-  for (i = 0; i < 3; i++) {
-    bus_sb800[i] = 0;
-  }
-
-  for (i = 0; i < 256; i++) {
-    bus_type[i] = 0; /* default ISA bus. */
-  }
-
-  bus_type[0] = 1;  /* pci */
-
-//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-  bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
-
-  /* sb800 */
-  dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
-
-  if (dev) {
-    bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-    bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-    bus_isa++;
-    for (j = bus_sb800[1]; j < bus_isa; j++)
-      bus_type[j] = 1;
-  }
-
-  for (i = 0; i < 4; i++) {
-    dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
-    if (dev) {
-      bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-      bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-      bus_isa++;
-    }
-  }
-
-  for (j = bus_sb800[2]; j < bus_isa; j++)
-    bus_type[j] = 1;
-
-  /* I/O APICs:   APIC ID Version State   Address */
-  bus_isa = 10;
+	u32 status;
+
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;   /* do it only once */
+
+	get_bus_conf_done = 1;
+
+	/*
+	 * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+	 * but functionally within the coreboot model, this is the best place to make the
+	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+	 * after the decision about S3 resume is made, and before the system tables are
+	 * written into RAM.  The routine that is responsible for writing the tables is
+	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * specific entry point between the S3 resume decision point and the call to
+	 * "write_tables", and the next platform specific entry points are the calls to
+	 * the ACPI table write functions.  The first of ose would seem to be the right
+	 * place, but other table write functions, e.g. the PIRQ table write function, are
+	 * called before the ACPI tables are written.  This routine is called at the beginning
+	 * of each of the write functions called prior to the ACPI write functions, so this
+	 * becomes the best place for this call.
+	 */
+	status = agesawrapper_amdinitlate();
+	if(status) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+	}
+
+	sbdn_sb800 = 0;
+
+	for (i = 0; i < 3; i++) {
+		bus_sb800[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+	bus_type[0] = 1;  /* pci */
+
+	//  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
+
+	/* sb800 */
+	dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
+
+	if (dev) {
+		bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb800[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	for (i = 0; i < 4; i++) {
+		dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
+		if (dev) {
+			bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+			bus_isa++;
+		}
+	}
+
+	for (j = bus_sb800[2]; j < bus_isa; j++)
+		bus_type[j] = 1;
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
 	apicid_base = CONFIG_MAX_CPUS;
 	apicid_sb800 = apicid_base;
 
 #if CONFIG_AMD_SB_CIMX
-  sb_Late_Post();
+	sb_Late_Post();
 #endif
 }
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
index 28432dd..de25b48 100644
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ b/src/mainboard/amd/inagua/irq_tables.c
@@ -27,9 +27,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+		u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+		u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+		u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 89a3c6b..17c985d 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -74,8 +74,8 @@ void set_pcie_dereset(void)
 uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
-* enable the dedicated function in INAGUA    board.
-*************************************************/
+ * enable the dedicated function in INAGUA    board.
+ *************************************************/
 static void inagua_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -87,14 +87,14 @@ static void inagua_enable(device_t dev)
 	/* TOP_MEM: the top of DRAM below 4G */
 	msr = rdmsr(TOP_MEM);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr.lo, msr.hi);
+		(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+		 __func__, msr.lo, msr.hi);
 
 	/* TOP_MEM2: the top of DRAM above 4G */
 	msr2 = rdmsr(TOP_MEM2);
 	printk
-	    (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
-	     __func__, msr2.lo, msr2.hi);
+		(BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+		 __func__, msr2.lo, msr2.hi);
 
 	/* refer to UMA Size Consideration in Family14h BKDG. */
 	sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON()
@@ -102,16 +102,16 @@ static void inagua_enable(device_t dev)
 		uma_memory_size = 0x18000000;	/* >= 2G memory, 384M recommended UMA */
 	}
 	else {
-	  if (sys_mem >= 0x40000000) {
-		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
+		if (sys_mem >= 0x40000000) {
+			uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
 		} else {
-		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
-	  }
+			uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
+		}
 	}
 
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
-		    __func__, uma_memory_size, uma_memory_base);
+			__func__, uma_memory_size, uma_memory_base);
 
 	/* TODO: TOP_MEM2 */
 #else
@@ -127,16 +127,16 @@ int add_mainboard_resources(struct lb_memory *mem)
 {
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
- 	 */
+	 */
 #if (CONFIG_GFXUMA == 1)
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
-		    uma_memory_base, uma_memory_size);
+			uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
-			    uma_memory_size);
+			uma_memory_size);
 #endif
 	return 0;
 }
 struct chip_operations mainboard_ops = {
 	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
-	.enable_dev = inagua_enable,
+		.enable_dev = inagua_enable,
 };
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 0a2096b..b339348 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -50,115 +50,115 @@ u8 intr_data[] = {
 
 static void *smp_write_config_table(void *v)
 {
-  struct mp_config_table *mc;
-  int bus_isa;
+	struct mp_config_table *mc;
+	int bus_isa;
 
-  mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
-  memcpy(mc->mpc_oem, "AMD     ", 8);
+	mptable_init(mc, LAPIC_ADDR);
+	memcpy(mc->mpc_oem, "AMD     ", 8);
 
 	smp_write_processors(mc);
 
-  get_bus_conf();
+	get_bus_conf();
 
 	mptable_write_buses(mc, NULL, &bus_isa);
 
-  /* I/O APICs:   APIC ID Version State   Address */
+	/* I/O APICs:   APIC ID Version State   Address */
 
-  u32 dword;
-  u8 byte;
+	u32 dword;
+	u8 byte;
 
-  ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
-  dword &= 0xFFFFFFF0;
-  smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
+	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	dword &= 0xFFFFFFF0;
+	smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
-  for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
-    outb(byte | 0x80, 0xC00);
-    outb(intr_data[byte], 0xC01);
-  }
+	for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+		outb(byte | 0x80, 0xC00);
+		outb(intr_data[byte], 0xC01);
+	}
 
-    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
-  smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
 	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
-  /* PCI interrupts are level triggered, and are
-   * associated with a specific bus/device/function tuple.
-   */
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
 #if CONFIG_GENERATE_ACPI_TABLES == 0
 #define PCI_INT(bus, dev, fn, pin) \
-		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
 #define PCI_INT(bus, dev, fn, pin)
 #endif
 
-  /* APU Internal Graphic Device*/
-  PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
-  PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+	/* APU Internal Graphic Device*/
+	PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+	PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
 	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
-  PCI_INT(0x0, 0x14, 0x0, 0x10);
+	PCI_INT(0x0, 0x14, 0x0, 0x10);
 	/* Southbridge HD Audio: */
 	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
 	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
-  PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
-  PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
-  PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
-  PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
-  PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-
-  /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
-
-  /* on board NIC & Slot PCIE.  */
-
-  /* PCI slots */
-  /* PCI_SLOT 0. */
-  PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
-  PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
-  PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
-  PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
-
-  /* PCI_SLOT 1. */
-  PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
-  PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
-  PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
-  PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
-
-  /* PCI_SLOT 2. */
-  PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
-  PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
-  PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
-  PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
-
-  PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
-  PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
-  PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
+	PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+	PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+	PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+	PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+	PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+
+	/* sata */
+	PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+	/* on board NIC & Slot PCIE.  */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
+
+	PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
+	PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
+	PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
 	/* PCIe PortA */
-  PCI_INT(0x0, 0x15, 0x0, 0x10);
+	PCI_INT(0x0, 0x15, 0x0, 0x10);
 	/* PCIe PortB */
-  PCI_INT(0x0, 0x15, 0x1, 0x11);
+	PCI_INT(0x0, 0x15, 0x1, 0x11);
 	/* PCIe PortC */
-  PCI_INT(0x0, 0x15, 0x2, 0x12);
+	PCI_INT(0x0, 0x15, 0x2, 0x12);
 	/* PCIe PortD */
-  PCI_INT(0x0, 0x15, 0x3, 0x13);
+	PCI_INT(0x0, 0x15, 0x3, 0x13);
 
-  /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
 	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-  /* There is no extension information... */
+	/* There is no extension information... */
 
-  /* Compute the checksums */
-  return mptable_finalize(mc);
+	/* Compute the checksums */
+	return mptable_finalize(mc);
 }
 
 unsigned long write_smp_table(unsigned long addr)
 {
-  void *v;
-  v = smp_write_floating_table(addr, 0);
-  return (unsigned long)smp_write_config_table(v);
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 87b2893..2a3342c 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -38,13 +38,13 @@
  */
 #ifndef BIOS_SIZE
 #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
-  #define BIOS_SIZE BIOS_SIZE_1M
+#define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
-  #define BIOS_SIZE BIOS_SIZE_2M
+#define BIOS_SIZE BIOS_SIZE_2M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
-  #define BIOS_SIZE BIOS_SIZE_4M
+#define BIOS_SIZE BIOS_SIZE_4M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
-  #define BIOS_SIZE BIOS_SIZE_8M
+#define BIOS_SIZE BIOS_SIZE_8M
 #endif
 #endif
 


From gerrit at coreboot.org  Thu Jan 19 05:33:40 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 19 Jan 2012 05:33:40 +0100
Subject: [coreboot] Patch set updated for coreboot: f8df726 Inagua: Inagua
	GNB ddi lanes and pcie lanes config update
References: <I40aaf28119b946b3a6383ceff7c734c9c3fd313e+0@gerrit.coreboot.org>
Message-ID: <I40aaf28119b946b3a6383ceff7c734c9c3fd313e+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/544

-gerrit

commit f8df7260201d3f579e552ba3239a94d70f631d0b
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Jan 19 13:18:37 2012 +0800

    Inagua: Inagua GNB ddi lanes and pcie lanes config update
    
    DDI lanes configuration update to make LVDS works.
    Pcie lanes configuration update to make MiniPcie slot 1 works.
    
    Change-Id: I40aaf28119b946b3a6383ceff7c734c9c3fd313e
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/PlatformGnbPcie.c |   24 ++++++++----------------
 1 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index ea080a5..f758006 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -55,25 +55,19 @@ OemCustomizeInitEarly (
 	ALLOCATE_HEAP_PARAMS AllocHeapParams;
 
 PCIe_PORT_DESCRIPTOR PortList [] = {
-        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) MXM
         {
           0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
         },
-        // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
-        {
-          0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
-          PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
-          PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
-        },
-        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN
         {
           0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
           PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
         },
-        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+        // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1
         {
           0,
           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
@@ -88,19 +82,17 @@ PCIe_PORT_DESCRIPTOR PortList [] = {
 };
 
 PCIe_DDI_DESCRIPTOR DdiList [] = {
-        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+        // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 to LVDS
         {
           0,   //Descriptor flags
           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
-          {ConnectorTypeDP, Aux1, Hdp1}
+          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeLvds, Aux1, Hdp1)
         },
-        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+        // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 to VGA
         {
           DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
-          //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
-          {ConnectorTypeDP, Aux2, Hdp2}
+          PCIE_DDI_DATA_INITIALIZER (ConnectorTypeAutoDetect, Aux2, Hdp2)
         }
 };
 


From gerrit at coreboot.org  Thu Jan 19 05:33:40 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 19 Jan 2012 05:33:40 +0100
Subject: [coreboot] Patch set updated for coreboot: 18d1ed4 Inagua:
	devicetree.cb update
References: <I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a+0@gerrit.coreboot.org>
Message-ID: <I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/545

-gerrit

commit 18d1ed4c01ca2f9c8286347d9c8987d098072254
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Jan 19 13:18:37 2012 +0800

    Inagua: devicetree.cb update
    
    Add the slots connection comments to devicetree.cb
    
    Change-Id: I3ccb2641c8d04a6a3c66ac11a562ba3b0dc0578a
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/devicetree.cb |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 62cf32d..60bb29b 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -30,10 +30,10 @@ chip northbridge/amd/agesa/family14/root_complex
                                         device pci 0.0 on end # Root Complex
                                         device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
                                         device pci 1.1 on end # Internal Multimedia
-                                        device pci 4.0 on end # PCIE P2P bridge 0x9604
-                                        device pci 5.0 off end # PCIE P2P bridge 0x9605
-                                        device pci 6.0 on end # PCIE P2P bridge 0x9606
-                                        device pci 7.0 off end # PCIE P2P bridge 0x9607
+                                        device pci 4.0 on  end # PCIE P2P bridge MXM lane 0
+                                        device pci 5.0 off end # PCIE P2P bridge MXM lane 1
+                                        device pci 6.0 on end # PCIE P2P bridge  LAN
+                                        device pci 7.0 on end # PCIE P2P bridge  MINIPCIE SLOT1
                                         device pci 8.0 off end # NB/SB Link P2P bridge
                                 end # agesa northbridge
 
@@ -67,10 +67,10 @@ chip northbridge/amd/agesa/family14/root_complex
 					end #LPC
 					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
-					device pci 15.0 on end # PCIe PortA
-					device pci 15.1 on end # PCIe PortB
-					device pci 15.2 on end # PCIe PortC
-					device pci 15.3 on end # PCIe PortD
+					device pci 15.0 on end # PCIe PortA  Express Card
+					device pci 15.1 on end # PCIe PortB  NEC USB3.0
+					device pci 15.2 on end # PCIe PortC  MINIPCIE SLOT2
+					device pci 15.3 on end # PCIe PortD  PCIE X1 SLOT
 					device pci 16.0 on end # OHCI USB3
 					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1


From gerrit at coreboot.org  Thu Jan 19 05:33:41 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 19 Jan 2012 05:33:41 +0100
Subject: [coreboot] Patch set updated for coreboot: cabbc86 Inagua:
	mainboard specific GPIO setting
References: <I563b2e6354a958a28f5d0162e7a4d60aa437fb9b+0@gerrit.coreboot.org>
Message-ID: <I563b2e6354a958a28f5d0162e7a4d60aa437fb9b+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/543

-gerrit

commit cabbc861db8d8551fb7ef725b3ce6cbbbb507996
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Jan 19 13:18:36 2012 +0800

    Inagua: mainboard specific GPIO setting
    
    Pcie device connected to Hudson/sb800 southbridge GPP training can works,
    by applying this mainbaind specific GPIO PCIE De-Assert setting.
    
    Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/mainboard.c |   28 +++++++++++++++++++++++++++-
 1 files changed, 27 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 1fd5fae..89a3c6b 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -26,6 +26,7 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 //#include <southbridge/amd/sb800/sb800.h>
+#include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "chip.h"
 
 void set_pcie_reset(void);
@@ -40,11 +41,34 @@ void set_pcie_reset(void)
 }
 
 /**
- * TODO
  * mainboard specific SB CIMx callback
  */
 void set_pcie_dereset(void)
 {
+	/**
+	 * GPIO32 Pcie Device DeAssert for APU
+	 * GPIO25 Pcie LAN,       APU GPP2
+	 * GPIO02 MINIPCIE SLOT1, APU GPP3
+	 * GPIO50 Pcie Device DeAssert for Hudson Southbridge
+	 * GPIO05 Express Card,     SB  GPP0
+	 * GPIO26 NEC USB3.0GPPUSB, SB  GPP1
+	 * GPIO00 MINIPCIE SLOT2,   SB  GPP2
+	 * GPIO05 Pcie X1 Slot,     SB  GPP3
+	 */
+
+	/* Multi-function pins switch to GPIO0-35, these pins are shared with
+	 * PCI pins, make sure Husson PCI device is disabled.
+	 */
+	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 1);
+
+	/* select IOMux to function1/2, corresponds to GPIO */
+	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG32, AccWidthUint8, ~(BIT0 | BIT1), 1);
+	RWMEM(ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG50, AccWidthUint8, ~(BIT0 | BIT1), 2);
+
+
+	/* output low */
+	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG32, AccWidthUint8, ~(0xFF), 0x48);
+	RWMEM(ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG50, AccWidthUint8, ~(0xFF), 0x48);
 }
 
 uint64_t uma_memory_base, uma_memory_size;
@@ -95,6 +119,8 @@ static void inagua_enable(device_t dev)
 	uma_memory_base = 0x30000000;	/* 1GB  system memory supported */
 #endif
 
+	/* Inagua mainboard specific setting */
+	set_pcie_dereset();
 }
 
 int add_mainboard_resources(struct lb_memory *mem)


From gerrit at coreboot.org  Thu Jan 19 05:33:41 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Thu, 19 Jan 2012 05:33:41 +0100
Subject: [coreboot] Patch set updated for coreboot: 5254c95 Inagua:
	Synchronize AMD/inagua mainboard.
References: <Ia038e5a2b9550fe81bb075f31e30b98354758e9e+0@gerrit.coreboot.org>
Message-ID: <Ia038e5a2b9550fe81bb075f31e30b98354758e9e+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/542

-gerrit

commit 5254c959694e2fae803b1d44f49dd277cc74f81f
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Thu Jan 19 13:18:36 2012 +0800

    Inagua: Synchronize AMD/inagua mainboard.
    
    AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
    Persimmom update a lot in the last few month, sync these modification to inagua.
    
    Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
 src/mainboard/amd/inagua/BiosCallOuts.c    |  122 ++++++-----------------
 src/mainboard/amd/inagua/BiosCallOuts.h    |    2 +
 src/mainboard/amd/inagua/Kconfig           |   25 +-----
 src/mainboard/amd/inagua/Makefile.inc      |    7 ++
 src/mainboard/amd/inagua/OptionsIds.h      |    6 +-
 src/mainboard/amd/inagua/PlatformGnbPcie.c |   58 ++++++------
 src/mainboard/amd/inagua/acpi/ssdt2.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt3.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt4.asl    |   84 ----------------
 src/mainboard/amd/inagua/acpi/ssdt5.asl    |   85 ----------------
 src/mainboard/amd/inagua/acpi_tables.c     |    7 +-
 src/mainboard/amd/inagua/agesawrapper.c    |    8 +-
 src/mainboard/amd/inagua/agesawrapper.h    |    9 +-
 src/mainboard/amd/inagua/buildOpts.c       |  116 +++++++++++++---------
 src/mainboard/amd/inagua/devicetree.cb     |    8 +-
 src/mainboard/amd/inagua/dimmSpd.c         |   39 ++++----
 src/mainboard/amd/inagua/dsdt.asl          |    9 +-
 src/mainboard/amd/inagua/fadt.c            |    4 +-
 src/mainboard/amd/inagua/get_bus_conf.c    |   23 +---
 src/mainboard/amd/inagua/irq_tables.c      |    3 +-
 src/mainboard/amd/inagua/mainboard.c       |   14 ++-
 src/mainboard/amd/inagua/mptable.c         |  146 ++++++---------------------
 src/mainboard/amd/inagua/platform_cfg.h    |    2 +-
 src/mainboard/amd/inagua/romstage.c        |   23 +++--
 24 files changed, 250 insertions(+), 718 deletions(-)

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
index a72f96b..434e83f 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.c
+++ b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -19,13 +19,12 @@
 
 #include "agesawrapper.h"
 #include "amdlib.h"
+#include "dimmSpd.h"
 #include "BiosCallOuts.h"
-#include "Ids.h"
-#include "OptionsIds.h"
 #include "heapManager.h"
 #include "SB800.h"
 
-STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
   {AGESA_ALLOCATE_BUFFER,
    BiosAllocateBuffer
@@ -55,102 +54,44 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] =
    BiosRunFuncOnAp
   },
 
-  {AGESA_GET_IDS_INIT_DATA,
-   BiosGetIdsInitData
+	{AGESA_GNB_PCIE_SLOT_RESET,
+	 BiosGnbPcieSlotReset
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT,
+	 BiosHookBeforeDramInit
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+	 BiosHookBeforeDramInitRecovery
   },
 
   {AGESA_HOOKBEFORE_DQS_TRAINING,
    BiosHookBeforeDQSTraining
   },
 
-  {AGESA_HOOKBEFORE_DRAM_INIT,
-   BiosHookBeforeDramInit
-  },
   {AGESA_HOOKBEFORE_EXIT_SELF_REF,
    BiosHookBeforeExitSelfRefresh
   },
-  {AGESA_GNB_PCIE_SLOT_RESET,
-   BiosGnbPcieSlotReset
-  },
 };
 
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   UINTN i;
   AGESA_STATUS CalloutStatus;
+	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
 
-  for (i = 0; i < REQUIRED_CALLOUTS; i++)
-  {
-    if (BiosCallouts[i].CalloutName == Func)
-    {
-      break;
-    }
-  }
-
-  if(i >= REQUIRED_CALLOUTS)
-  {
-    return AGESA_UNSUPPORTED;
-  }
+	CalloutStatus = AGESA_UNSUPPORTED;
 
+	for (i = 0; i < CallOutCount; i++) {
+		if (BiosCallouts[i].CalloutName == Func) {
   CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
-
   return CalloutStatus;
-}
-
-
-CONST IDS_NV_ITEM IdsData[] =
-{
-  /*{
-    AGESA_IDS_NV_MAIN_PLL_CON,
-    0x1
-  },
-  {
-    AGESA_IDS_NV_MAIN_PLL_FID_EN,
-    0x1
-  },
-  {
-    AGESA_IDS_NV_MAIN_PLL_FID,
-    0x8
-  },
-
-  {
-    AGESA_IDS_NV_CUSTOM_NB_PSTATE,
-  },
-  {
-    AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
-  },
-  {
-    AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
-  },
-  {
-    AGESA_IDS_NV_FORCE_NB_PSTATE,
-  },
-*/
-  {
-    0xFFFF,
-    0xFFFF
-  }
-};
-
-#define   NUM_IDS_ENTRIES    (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
-
-
-AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
-{
-  UINTN   i;
-  IDS_NV_ITEM *IdsPtr;
-
-  IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
-
-  if (Data == IDS_CALLOUT_INIT) {
-    for (i = 0; i < NUM_IDS_ENTRIES; i++) {
-      IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
-      IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
     }
   }
-  return AGESA_SUCCESS;
-}
 
+	return CalloutStatus;
+}
 
 AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
@@ -210,7 +151,6 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
        to the end of the allocated nodes list.
       */
-
     }
     /* Find the node that best fits the requested buffer size */
     FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
@@ -343,7 +283,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       /* Clear the BufferSize and NextNodeOffset of the previous first node */
       FreedNodePtr->BufferSize = 0;
       FreedNodePtr->NextNodeOffset = 0;
-
     } else {
       /* Otherwise, add freed node to the start of the list
          Update NextNodeOffset and BufferSize to include the
@@ -390,7 +329,6 @@ AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
     if (AllocNodeOffset == EndNodeOffset) {
       PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
       PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
-
       AllocNodePtr->BufferSize = 0;
       AllocNodePtr->NextNodeOffset = 0;
     } else {
@@ -438,7 +376,7 @@ AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS        Status;
 
-  Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+	Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr);
   return Status;
 }
 
@@ -481,7 +419,7 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
   AGESA_STATUS Status;
-  Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
 
   return Status;
 }
@@ -511,7 +449,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   MemData = ConfigPtr;
 
   Status  = AGESA_SUCCESS;
-  /* Get SB800 MMIO Base (AcpiMmioAddr) */
+	/* Get SB MMIO Base (AcpiMmioAddr) */
   WriteIo8 (0xCD6, 0x27);
   Data8   = ReadIo8(0xCD7);
   Data16  = Data8<<8;
@@ -534,12 +472,14 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   TempData8 &= 0x23;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+
   Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
   Data8 &= ~BIT5;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
   TempData8 &= 0x03;
   TempData8 |= Data8;
   Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+
   Data8 |= BIT2+BIT3;
   Data8 &= ~BIT4;
   TempData8  = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
@@ -575,6 +515,13 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   }
   return Status;
 }
+
+/*	Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
@@ -607,8 +554,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
   switch (ResetInfo->ResetId)
   {
   case 4:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
         Data8 &= ~(UINT8)BIT6 ;
@@ -624,8 +570,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       }
       break;
   case 6:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
         Data8 &= ~(UINT8)BIT6 ;
@@ -641,8 +586,7 @@ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
       }
       break;
   case 7:
-      switch (ResetInfo->ResetControl)
-      {
+		switch (ResetInfo->ResetControl) {
       case AssertSlotReset:
         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
         Data8 &= ~(UINT8)BIT6 ;
diff --git a/src/mainboard/amd/inagua/BiosCallOuts.h b/src/mainboard/amd/inagua/BiosCallOuts.h
index 4efe15f..f7124b9 100644
--- a/src/mainboard/amd/inagua/BiosCallOuts.h
+++ b/src/mainboard/amd/inagua/BiosCallOuts.h
@@ -64,6 +64,8 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt
 /*  Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*	Call the host environment interface to provide a user hook opportunity. */
 AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 /* PCIE slot reset control */
 AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index 4bb0d60..b0c5f1a 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -22,8 +22,6 @@ if BOARD_AMD_INAGUA
 config BOARD_SPECIFIC_OPTIONS # dummy
         def_bool y
   select ARCH_X86
-        select DIMM_DDR3
-        select DIMM_UNREGISTERED
   select CPU_AMD_AGESA_FAMILY14
   select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX
   select NORTHBRIDGE_AMD_AGESA_FAMILY14
@@ -81,18 +79,6 @@ config MEM_TRAIN_SEQ
         int
         default 2
 
-config SB_HT_CHAIN_ON_BUS0
-        int
-        default 1
-
-config HT_CHAIN_END_UNITID_BASE
-        hex
-        default 0x1
-
-config HT_CHAIN_UNITID_BASE
-        hex
-        default 0x0
-
 config IRQ_SLOT_COUNT
         int
         default 11
@@ -147,19 +133,10 @@ config VGA_BIOS_ID
         depends on VGA_BIOS
         default "1002,9802"
 
-config AHCI_ROM
+config SB800_AHCI_ROM
         bool
         default n
 
-#config AHCI_ROM_FILE
-#        string "AHCI ROM path and filename"
-#        depends on AHCI_ROM
-#        default "rom/ahci/sb800.bin"
-
-config AHCI_ROM_ID
-        string "AHCI device PCI IDs"
-        depends on AHCI_ROM
-        default "1002,4391"
 
 endif # BOARD_AMD_INAGUA
 
diff --git a/src/mainboard/amd/inagua/Makefile.inc b/src/mainboard/amd/inagua/Makefile.inc
index d9fc200..8a72727 100755
--- a/src/mainboard/amd/inagua/Makefile.inc
+++ b/src/mainboard/amd/inagua/Makefile.inc
@@ -17,6 +17,13 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+ifeq ($(CONFIG_AHCI_BIOS),y)
+stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
+cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
+pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
+pci$(stripped_ahcibios_id).rom-type := optionrom
+endif
+
 romstage-y += buildOpts.c
 romstage-y += agesawrapper.c
 romstage-y += dimmSpd.c
diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h
index eb756df..028d58f 100644
--- a/src/mainboard/amd/inagua/OptionsIds.h
+++ b/src/mainboard/amd/inagua/OptionsIds.h
@@ -51,11 +51,9 @@
  **/
 
 #define IDSOPT_IDS_ENABLED     TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-#define IDSOPT_TRACING_ENABLED TRUE
-//#define IDSOPT_PERF_ANALYSIS   TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
 #define IDSOPT_ASSERT_ENABLED  TRUE
-//#undef IDSOPT_DEBUG_ENABLED
+
 //#define IDSOPT_DEBUG_ENABLED  FALSE
 //#undef IDSOPT_HOST_SIMNOW
 //#define IDSOPT_HOST_SIMNOW    FALSE
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c
index 4f00071..ea080a5 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcie.c
+++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c
@@ -26,6 +26,34 @@
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
 
+/*---------------------------------------------------------------------------------------*/
+/**
+ *	OemCustomizeInitEarly
+ *
+ *	Description:
+ *	This is the stub function will call the host environment through the binary block
+ *	interface (call-out port) to provide a user hook opportunity
+ *
+ *	Parameters:
+ *	@param[in]		**PeiServices
+ *	@param[in]		*InitEarly
+ *
+ *	@retval		 VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+	IN	OUT AMD_EARLY_PARAMS	*InitEarly
+	)
+{
+	AGESA_STATUS		 Status;
+	VOID				 *BrazosPcieComplexListPtr;
+	VOID				 *BrazosPciePortPtr;
+	VOID				 *BrazosPcieDdiPtr;
+
+	ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
 PCIe_PORT_DESCRIPTOR PortList [] = {
         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
         {
@@ -83,34 +111,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
         &DdiList[0]
 };
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-  IN  OUT AMD_EARLY_PARAMS    *InitEarly
-  )
-{
-  AGESA_STATUS         Status;
-  VOID                 *BrazosPcieComplexListPtr;
-  VOID                 *BrazosPciePortPtr;
-  VOID                 *BrazosPcieDdiPtr;
-
-  ALLOCATE_HEAP_PARAMS AllocHeapParams;
-
   // GNB PCIe topology Porting
 
   //
@@ -126,7 +126,7 @@ OemCustomizeInitEarly (
   if ( Status!= AGESA_SUCCESS) {
     // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
     ASSERT(FALSE);
-    return Status;
+	return;
   }
 
   BrazosPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
diff --git a/src/mainboard/amd/inagua/acpi/ssdt2.asl b/src/mainboard/amd/inagua/acpi/ssdt2.asl
deleted file mode 100644
index ef1a4bf..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt2.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-		// BUS ? Second HT Chain
-		Name (HCIN, 0xcc)  // HC2 0x01
-
-		Name (_UID,	 0xdd)	// HC 0x03
-
-		Name (_HID, "PNP0A03")
-
-		Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-		{
-			Return (DADD(GHCN(HCIN), 0x00000000))
-		}
-
-		Method (_BBN, 0, NotSerialized)
-		{
-			 Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-		}
-
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (\_SB.GHCE(HCIN))
-		}
-
-		Method (_CRS, 0, NotSerialized)
-		{
-			Name (BUF0, ResourceTemplate () { })
-			Store( GHCN(HCIN), Local4)
-			Store( GHCL(HCIN), Local5)
-
-			Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-			Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-			Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-			Return (Local3)
-		}
-
-			#include "acpi/pci2_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt3.asl b/src/mainboard/amd/inagua/acpi/ssdt3.asl
deleted file mode 100644
index 68a4b95..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt3.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci3_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt4.asl b/src/mainboard/amd/inagua/acpi/ssdt4.asl
deleted file mode 100644
index e06fe8a..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt4.asl
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-		External (DADD, MethodObj)
-		External (GHCE, MethodObj)
-		External (GHCN, MethodObj)
-		External (GHCL, MethodObj)
-		External (GHCD, MethodObj)
-		External (GNUS, MethodObj)
-		External (GIOR, MethodObj)
-		External (GMEM, MethodObj)
-		External (GWBN, MethodObj)
-		External (GBUS, MethodObj)
-
-		External (PICF)
-
-		External (\_SB.PCI0.LNKA, DeviceObj)
-		External (\_SB.PCI0.LNKB, DeviceObj)
-		External (\_SB.PCI0.LNKC, DeviceObj)
-		External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci4_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi/ssdt5.asl b/src/mainboard/amd/inagua/acpi/ssdt5.asl
deleted file mode 100644
index a141a37..0000000
--- a/src/mainboard/amd/inagua/acpi/ssdt5.asl
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-
-DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440)
-{
-	Scope (_SB)
-	{
-	External (DADD, MethodObj)
-	External (GHCE, MethodObj)
-	External (GHCN, MethodObj)
-	External (GHCL, MethodObj)
-	External (GHCD, MethodObj)
-	External (GNUS, MethodObj)
-	External (GIOR, MethodObj)
-	External (GMEM, MethodObj)
-	External (GWBN, MethodObj)
-	External (GBUS, MethodObj)
-
-	External (PICF)
-
-	External (\_SB.PCI0.LNKA, DeviceObj)
-	External (\_SB.PCI0.LNKB, DeviceObj)
-	External (\_SB.PCI0.LNKC, DeviceObj)
-	External (\_SB.PCI0.LNKD, DeviceObj)
-
-		Device (PCIX)
-		{
-
-			// BUS ? Second HT Chain
-			Name (HCIN, 0xcc)  // HC2 0x01
-
-			Name (_UID,	 0xdd)	// HC 0x03
-
-			Name (_HID, "PNP0A03")
-
-			Method (_ADR, 0, NotSerialized) //Fake bus should be 0
-			{
-				Return (DADD(GHCN(HCIN), 0x00000000))
-			}
-
-			Method (_BBN, 0, NotSerialized)
-			{
-				Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
-			}
-
-			Method (_STA, 0, NotSerialized)
-			{
-				Return (\_SB.GHCE(HCIN))
-			}
-
-			Method (_CRS, 0, NotSerialized)
-			{
-				Name (BUF0, ResourceTemplate () { })
-				Store( GHCN(HCIN), Local4)
-				Store( GHCL(HCIN), Local5)
-
-				Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
-				Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
-				Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
-				Return (Local3)
-			}
-
-			#include "acpi/pci5_hc.asl"
-		}
-	}
-
-}
-
diff --git a/src/mainboard/amd/inagua/acpi_tables.c b/src/mainboard/amd/inagua/acpi_tables.c
index 2e6e50f..8ed7d4f 100644
--- a/src/mainboard/amd/inagua/acpi_tables.c
+++ b/src/mainboard/amd/inagua/acpi_tables.c
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -245,9 +246,10 @@ unsigned long write_acpi_tables(unsigned long start)
 		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
 		current += ssdt->length;
+		acpi_add_table(rsdp,ssdt);
 	}
 	else {
-		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
+		printk(BIOS_DEBUG, "  AGESA SSDT Pstate table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
 #endif
@@ -275,6 +277,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	printk(BIOS_DEBUG, "slit\n");
 	dump_mem(slit, ((void *)slit) + slit->header.length);
 
+	printk(BIOS_DEBUG, "alib\n");
+	dump_mem(ssdt, ((void *)alib) + alib->length);
+
 	printk(BIOS_DEBUG, "ssdt\n");
 	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
 
diff --git a/src/mainboard/amd/inagua/agesawrapper.c b/src/mainboard/amd/inagua/agesawrapper.c
index 715202a..fe2fe6b 100644
--- a/src/mainboard/amd/inagua/agesawrapper.c
+++ b/src/mainboard/amd/inagua/agesawrapper.c
@@ -57,7 +57,6 @@ VOID *AcpiWheaMce	= NULL;
 VOID *AcpiWheaCmc	= NULL;
 VOID *AcpiAlib		= NULL;
 
-
 /*------------------------------------------------------------------------------
  *				T Y P E D E F S		 A N D		 S T R U C T U R E S
  *------------------------------------------------------------------------------
@@ -190,7 +189,6 @@ agesawrapper_amdinitreset (
 					sizeof (AMD_INTERFACE_PARAMS),
 					&(AmdParamStruct.StdHeader));
 
-
 	LibAmdMemFill (&AmdResetParams,
 					0,
 					sizeof (AMD_RESET_PARAMS),
@@ -485,6 +483,12 @@ agesawrapper_amdinitlate (
 	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
 	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
 
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
 	/* Don't release the structure until coreboot has copied the ACPI tables.
 	 * AmdReleaseStruct (&AmdLateParams);
 	 */
diff --git a/src/mainboard/amd/inagua/agesawrapper.h b/src/mainboard/amd/inagua/agesawrapper.h
index f6e6dec..f8d924e 100644
--- a/src/mainboard/amd/inagua/agesawrapper.h
+++ b/src/mainboard/amd/inagua/agesawrapper.h
@@ -22,7 +22,6 @@
  *----------------------------------------------------------------------------------------
  */
 
-
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
@@ -39,7 +38,6 @@
 #define AMD_APU_SSID    0x1234
 #define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
 
-
 enum {
   PICK_DMI,       /* DMI Interface */
   PICK_PSTATE,    /* Acpi Pstate SSDT Table */
@@ -50,8 +48,6 @@ enum {
   PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
 };
 
-
-
 /*----------------------------------------------------------------------------------------
  *                  T Y P E D E F S     A N D     S T R U C T U  R E S
  *----------------------------------------------------------------------------------------
@@ -77,15 +73,18 @@ typedef struct {
  *---------------------------------------------------------------------------------------
  */
 
-//void brazos_platform_stage(void);
 UINT32 agesawrapper_amdinitreset (void);
 UINT32 agesawrapper_amdinitearly (void);
 UINT32 agesawrapper_amdinitenv (void);
 UINT32 agesawrapper_amdinitlate (void);
 UINT32 agesawrapper_amdinitpost (void);
 UINT32 agesawrapper_amdinitmid (void);
+
 UINT32 agesawrapper_amdreadeventlog (void);
+
+UINT32 agesawrapper_amdinitcpuio (void);
 UINT32 agesawrapper_amdinitmmio (void);
+UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
 void *agesawrapper_getlateinitptr (int pick);
 
 #endif
diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c
index 919f6be..6506c2e 100644
--- a/src/mainboard/amd/inagua/buildOpts.c
+++ b/src/mainboard/amd/inagua/buildOpts.c
@@ -33,8 +33,6 @@
  * @e \$Revision: 23714 $   @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
  */
 
-#include "AGESA.h"
-#include "CommonReturns.h"
 #include "Filecode.h"
 #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
 
@@ -80,16 +78,16 @@
 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT     TRUE
 
 #define BLDOPT_REMOVE_UDIMMS_SUPPORT          FALSE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT        TRUE
+#define BLDOPT_REMOVE_RDIMMS_SUPPORT			TRUE
 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT         FALSE
 #define BLDOPT_REMOVE_ECC_SUPPORT             FALSE
 //#define BLDOPT_REMOVE_DCT_INTERLEAVE        TRUE
 #define BLDOPT_REMOVE_BANK_INTERLEAVE         FALSE
-//#define BLDOPT_REMOVE_NODE_INTERLEAVE       TRUE
+#define BLDOPT_REMOVE_NODE_INTERLEAVE			TRUE
 #define BLDOPT_REMOVE_PARALLEL_TRAINING       FALSE
 #define BLDOPT_REMOVE_DQS_TRAINING            FALSE
-//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT    TRUE
-//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT     TRUE
+#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT		TRUE
+#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT		TRUE
 #define BLDOPT_REMOVE_ACPI_PSTATES          FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PPC        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_PCT        FALSE
@@ -97,17 +95,17 @@
   #define BLDCFG_REMOVE_ACPI_PSTATES_PSS        FALSE
   #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS       FALSE
   #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT     FALSE
-//#define BLDOPT_REMOVE_SRAT            TRUE
-//#define BLDOPT_REMOVE_SLIT            TRUE
-//#define BLDOPT_REMOVE_WHEA            TRUE
-//#define BLDOPT_REMOVE_DMI             TRUE
-//#define BLDOPT_REMOVE_HT_ASSIST         TRUE
-//#define BLDOPT_REMOVE_ATM_MODE          TRUE
+#define BLDOPT_REMOVE_SRAT						FALSE
+#define BLDOPT_REMOVE_SLIT						FALSE
+#define BLDOPT_REMOVE_WHEA						FALSE
+#define BLDOPT_REMOVE_DMI						TRUE
+#define BLDOPT_REMOVE_HT_ASSIST					TRUE
+#define BLDOPT_REMOVE_ATM_MODE					TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E       TRUE
 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT     FALSE
 //#define BLDOPT_REMOVE_C6_STATE          TRUE
-//#define BLDOPT_REMOVE_GFX_RECOVERY        TRUE
+#define BLDOPT_REMOVE_GFX_RECOVERY				TRUE
 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
 
 /*
@@ -123,30 +121,7 @@
 #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
 #define AGESA_ENTRY_INIT_RESUME                   TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE             FALSE
-#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
-
-/*
- * Agesa configuration values selection.
- * Uncomment and specify the value for the configuration options
- * needed by the system.
- */
-
-/* The fixed MTRR values to be set after memory initialization. */
-CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
-{
-  { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
-  { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1E },
-  { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1E },
-  { CPU_LIST_TERMINAL }
-};
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES		FALSE
 
 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
@@ -201,7 +176,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD             FALSE
 //#define BLDCFG_USE_UNIT_ID_CLUMPING             FALSE
 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP       0
-//#define BLDCFG_CFG_GNB_HD_AUDIO                 TRUE
+#define BLDCFG_CFG_GNB_HD_AUDIO					TRUE
 //#define BLDCFG_CFG_ABM_SUPPORT                  FALSE
 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE         0
 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL       0
@@ -244,7 +219,33 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #define BLDCFG_HEAP_DRAM_ADDRESS                0xB0000
 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 
+/*
+ * Agesa configuration values selection.
+ * Uncomment and specify the value for the configuration options
+ * needed by the system.
+ */
+#include "AGESA.h"
+#include "CommonReturns.h"
+
+/* The fixed MTRR values to be set after memory initialization. */
+CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
+{
+	{ AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
+	{ AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
+	{ AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
+	{ CPU_LIST_TERMINAL }
+};
+
 /*  Include the files that instantiate the configuration definitions.  */
+
 #include "cpuRegisters.h"
 #include "cpuFamRegisters.h"
 #include "cpuFamilyTranslation.h"
@@ -253,7 +254,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 #include "CreateStruct.h"
 #include "cpuFeatures.h"
 #include "Table.h"
-#include "CommonReturns.h"
 #include "cpuEarlyInit.h"
 #include "cpuLateInit.h"
 #include "GnbInterface.h"
@@ -271,13 +271,37 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
  * version string as appropriate for the release. The trunk copy of this file
  * should also be updated/incremented for the next expected version, + trailing 'X'
  ****************************************************************************/
-                  // This is the delivery package title, "BrazosPI"
-                  // This string MUST be exactly 8 characters long
+// This is the delivery package title, "BrazosPI"
+// This string MUST be exactly 8 characters long
 #define AGESA_PACKAGE_STRING  {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 
-                  // This is the release version number of the AGESA component
-                  // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+// This is the release version number of the AGESA component
+// This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING	{'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
+
+/* MEMORY_BUS_SPEED */
+#define DDR400_FREQUENCY				200 ///< DDR 400
+#define DDR533_FREQUENCY				266 ///< DDR 533
+#define DDR667_FREQUENCY				333 ///< DDR 667
+#define DDR800_FREQUENCY				400 ///< DDR 800
+#define DDR1066_FREQUENCY				533 ///< DDR 1066
+#define DDR1333_FREQUENCY				667 ///< DDR 1333
+#define DDR1600_FREQUENCY				800 ///< DDR 1600
+#define DDR1866_FREQUENCY				933 ///< DDR 1866
+#define UNSUPPORTED_DDR_FREQUENCY		934 ///< Highest limit of DDR frequency
+
+/* QUANDRANK_TYPE*/
+#define QUADRANK_REGISTERED				0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED				1 ///< Quadrank unbuffered DIMM
+
+/* USER_MEMORY_TIMING_MODE */
+#define TIMING_MODE_AUTO				0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED				1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC			2 ///< Set user specified speed
+
+/* POWER_DOWN_MODE */
+#define POWER_DOWN_BY_CHANNEL			0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT		1 ///< Chip select power down mode
 
 // The following definitions specify the default values for various parameters in which there are
 // no clearly defined defaults to be used in the common file.  The values below are based on product
@@ -373,7 +397,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 #include "mn.h"
 
 //DA Customer table
-UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
+CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
 {
  // Hardcoded Memory Training Values
 
@@ -415,7 +439,7 @@ UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] =
  // TABLE END
   NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
 };
-UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
+CONST UINT8 SizeOfTableON = sizeof (AGESA_MEM_TABLE_ON) / sizeof (AGESA_MEM_TABLE_ON[0]);
 
 /* ***************************************************************************
  *   Optional User code to be included into the AGESA build
diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb
index 32d9a26..62cf32d 100644
--- a/src/mainboard/amd/inagua/devicetree.cb
+++ b/src/mainboard/amd/inagua/devicetree.cb
@@ -28,7 +28,7 @@ chip northbridge/amd/agesa/family14/root_complex
 #                       device pci 18.0 on #  northbridge
                                 chip northbridge/amd/agesa/family14 # PCI side of HT root complex
                                         device pci 0.0 on end # Root Complex
-                                        device pci 1.0 on end # Internal Graphics P2P bridge
+                                        device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806
                                         device pci 1.1 on end # Internal Multimedia
                                         device pci 4.0 on end # PCIE P2P bridge 0x9604
                                         device pci 5.0 off end # PCIE P2P bridge 0x9605
@@ -65,14 +65,14 @@ chip northbridge/amd/agesa/family14/root_complex
                                                         end
                                                 end # kbc1100
 					end #LPC
-					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
 	  				device pci 14.5 on end # USB 2
 					device pci 15.0 on end # PCIe PortA
 					device pci 15.1 on end # PCIe PortB
 					device pci 15.2 on end # PCIe PortC
 					device pci 15.3 on end # PCIe PortD
-					device pci 16.0 off end # OHCI USB3
-					device pci 16.2 off end # EHCI USB3
+					device pci 16.0 on end # OHCI USB3
+					device pci 16.2 on end # EHCI USB3
 					register "gpp_configuration" = "4" #1:1:1:1
 		  			register "boot_switch_sata_ide" = "0"	# 0: boot from SATA. 1: IDE
 				end	#southbridge/amd/cimx/sb800
diff --git a/src/mainboard/amd/inagua/dimmSpd.c b/src/mainboard/amd/inagua/dimmSpd.c
index d82cb5d..3719112 100644
--- a/src/mainboard/amd/inagua/dimmSpd.c
+++ b/src/mainboard/amd/inagua/dimmSpd.c
@@ -20,6 +20,7 @@
 #include "Porting.h"
 #include "AGESA.h"
 #include "amdlib.h"
+#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
 #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
@@ -30,13 +31,12 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 * SPD address table - porting required
 */
 
-#define SMBUS_BASE_ADDR		0xB00
-static const UINT8 spdAddressLookup [1] [2] [1] =  // socket, channel, dimm
+static const UINT8 spdAddressLookup [1] [2] [2] =  // socket, channel, dimm
    {
    // socket 0
       {
-         {0xA0},  // channel 0 dimms
-         {0xA2},  // channel 1 dimms
+         {0xA0, 0xA2},  // channel 0 dimms
+         {0x00, 0x00},  // channel 1 dimms
       },
    };
 
@@ -46,7 +46,7 @@ static const UINT8 spdAddressLookup [1] [2] [1] =  // socket, channel, dimm
  */
 
 static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
-   {
+{
    unsigned int status;
    UINT64 limit;
 
@@ -60,8 +60,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
 
    // time limit to avoid hanging for unexpected error status (should never happen)
    limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
+	for (;;) {
       status = __inbyte (iobase);
       if (__rdtsc () > limit) break;
       if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
@@ -72,7 +71,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
    buffer [0] = __inbyte (iobase + 5);
    if (status == 2) status = 0;                      // check for done with no errors
    return status;
-   }
+}
 
 /*-----------------------------------------------------------------------------
  *
@@ -81,7 +80,7 @@ static int readSmbusByteData (int iobase, int address, char *buffer, int offset)
  */
 
 static int readSmbusByte (int iobase, int address, char *buffer)
-   {
+{
    unsigned int status;
    UINT64 limit;
 
@@ -90,8 +89,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
 
    // time limit to avoid hanging for unexpected error status
    limit = __rdtsc () + 2000000000 / 10;
-   for (;;)
-      {
+	for (;;) {
       status = __inbyte (iobase);
       if (__rdtsc () > limit) break;
       if ((status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
@@ -102,7 +100,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
    buffer [0] = __inbyte (iobase + 5);
    if (status == 2) status = 0;                      // check for done with no errors
    return status;
-   }
+}
 
 /*---------------------------------------------------------------------------
  *
@@ -114,7 +112,7 @@ static int readSmbusByte (int iobase, int address, char *buffer)
  */
 
 static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
-   {
+{
    int index, error;
 
    /* read the first byte using offset zero */
@@ -122,14 +120,13 @@ static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count)
    if (error) return error;
 
    /* read the remaining bytes using auto-increment for speed */
-   for (index = 1; index < count; index++)
-      {
+	for (index = 1; index < count; index++) {
       error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
       if (error) return error;
       }
 
    return 0;
-   }
+}
 
 static void writePmReg (int reg, int data)
    {
@@ -138,16 +135,16 @@ static void writePmReg (int reg, int data)
    }
 
 static void setupFch (int ioBase)
-   {
+{
    writePmReg (0x2D, ioBase >> 8);
    writePmReg (0x2C, ioBase | 1);
    writePmReg (0x29, 0x80);
    writePmReg (0x28, 0x61);
    __outbyte (ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz
-   }
+}
 
 AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
-   {
+{
    int spdAddress, ioBase;
 
    if (info->SocketId     >= DIMENSION (spdAddressLookup      )) return AGESA_ERROR;
@@ -156,7 +153,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 
    spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
    if (spdAddress == 0) return AGESA_ERROR;
-   ioBase = SMBUS_BASE_ADDR;
+	ioBase = SMBUS0_BASE_ADDRESS;
    setupFch (ioBase);
    return readspd (ioBase, spdAddress, (void *) info->Buffer, 128);
-   }
+}
diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl
index d7506c9..4a61328 100644
--- a/src/mainboard/amd/inagua/dsdt.asl
+++ b/src/mainboard/amd/inagua/dsdt.asl
@@ -27,7 +27,7 @@ DefinitionBlock (
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */	/* Include global debug methods if needed */
+	/* #include "../../../arch/i386/acpi/debug.asl" */		/* Include global debug methods if needed */
 
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
@@ -36,7 +36,7 @@ DefinitionBlock (
 	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
 	Name(PBLN, 0x0)	/* Length of BIOS area */
 
-	Name(PCBA, 0xE0000000)	/* Base address of PCIe config space */
+	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
 	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
 
 	Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
@@ -1379,7 +1379,7 @@ DefinitionBlock (
 
 				/* Real Time Clock Device */
 				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B01"))	/* AT Real Time Clock */
+					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 					Name(_CRS, ResourceTemplate() {
 						IRQNoFlags(){8}
 						IO(Decode16,0x0070, 0x0070, 0, 2)
@@ -1483,9 +1483,8 @@ DefinitionBlock (
 					0xF300			/* length */
 				)
 
-#if 0
-				Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	/* VGA memory space */
+#if 0
 				Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1)	/* Assume C0000-E0000 empty */
 				Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS)   /* BIOS ROM area */
 
diff --git a/src/mainboard/amd/inagua/fadt.c b/src/mainboard/amd/inagua/fadt.c
index c84edfb..020d011 100644
--- a/src/mainboard/amd/inagua/fadt.c
+++ b/src/mainboard/amd/inagua/fadt.c
@@ -40,9 +40,9 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = 244;
-	header->revision = 1;
+	header->revision = 3;
 	memcpy(header->oem_id, OEM_ID, 6);
-  memcpy(header->oem_table_id, "AMD     ", 8);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->asl_compiler_revision = 0;
 
diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c
index ab58c99..13d198a 100644
--- a/src/mainboard/amd/inagua/get_bus_conf.c
+++ b/src/mainboard/amd/inagua/get_bus_conf.c
@@ -24,6 +24,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <cpu/amd/amdfam14.h>
+#include "agesawrapper.h"
 #if CONFIG_AMD_SB_CIMX
 #include <sb_cimx.h>
 #endif
@@ -34,6 +35,7 @@
 */
 u8 bus_isa;
 u8 bus_sb800[3];
+u32 apicid_sb800;
 
 /*
 * Here you only need to set value in pci1234 for HT-IO that could be installed or not
@@ -44,27 +46,15 @@ u32 pci1234x[] = {
   0x0000ff0,
 };
 
-/*
-* HT Chain device num, actually it is unit id base of every ht device in chain,
-* assume every chain only have 4 ht device at most
-*/
-u32 hcdnx[] = {
-  0x20202020,
-};
-
 u32 bus_type[256];
-
 u32 sbdn_sb800;
 
-//KZ [092110]extern void get_pci1234(void);
-
 static u32 get_bus_conf_done = 0;
 
 
-
-
 void get_bus_conf(void)
 {
+	u32 apicid_base;
   u32 status;
 
   device_t dev;
@@ -105,7 +95,6 @@ void get_bus_conf(void)
     bus_type[i] = 0; /* default ISA bus. */
   }
 
-
   bus_type[0] = 1;  /* pci */
 
 //  bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
@@ -114,8 +103,6 @@ void get_bus_conf(void)
   /* sb800 */
   dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
 
-
-
   if (dev) {
     bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 
@@ -133,12 +120,14 @@ void get_bus_conf(void)
       bus_isa++;
     }
   }
+
   for (j = bus_sb800[2]; j < bus_isa; j++)
     bus_type[j] = 1;
 
-
   /* I/O APICs:   APIC ID Version State   Address */
   bus_isa = 10;
+	apicid_base = CONFIG_MAX_CPUS;
+	apicid_sb800 = apicid_base;
 
 #if CONFIG_AMD_SB_CIMX
   sb_Late_Post();
diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
index a8ea5aa..28432dd 100644
--- a/src/mainboard/amd/inagua/irq_tables.c
+++ b/src/mainboard/amd/inagua/irq_tables.c
@@ -23,8 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
-//#include <cpu/amd/amdfam10_sysconf.h>
-
+#include <cpu/amd/amdfam14.h>
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index e5025b6..1fd5fae 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -28,7 +28,8 @@
 //#include <southbridge/amd/sb800/sb800.h>
 #include "chip.h"
 
-//#define SMBUS_IO_BASE 0x6000
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
 
 /**
  * TODO
@@ -49,11 +50,12 @@ void set_pcie_dereset(void)
 uint64_t uma_memory_base, uma_memory_size;
 
 /*************************************************
-* enable the dedicated function in inagua board.
+* enable the dedicated function in INAGUA    board.
 *************************************************/
 static void inagua_enable(device_t dev)
 {
-	printk(BIOS_INFO, "Mainboard Inagua Enable. dev=0x%p\n", dev);
+	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
 #if (CONFIG_GFXUMA == 1)
 	msr_t msr, msr2;
 	uint32_t sys_mem;
@@ -78,11 +80,11 @@ static void inagua_enable(device_t dev)
 	else {
 	  if (sys_mem >= 0x40000000) {
 		  uma_memory_size = 0x10000000;	/* >= 1G memory, 256M recommended UMA */
-	  }
-	  else {
+		} else {
 		  uma_memory_size = 0x4000000;	/* <1G memory, 64M recommended UMA */
 	  }
 	}
+
 	uma_memory_base = msr.lo - uma_memory_size;	/* TOP_MEM1 */
 	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
 		    __func__, uma_memory_size, uma_memory_base);
@@ -109,6 +111,6 @@ int add_mainboard_resources(struct lb_memory *mem)
 	return 0;
 }
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("AMD INAGUA Mainboard")
+	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
 	.enable_dev = inagua_enable,
 };
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index 73d946c..0a2096b 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -24,114 +24,55 @@
 #include <arch/io.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
+#include <cpu/amd/amdfam14.h>
 #include <SBPLATFORM.h>
 
-#define IO_APIC_ID    CONFIG_MAX_PHYSICAL_CPUS + 1
 extern u8 bus_sb800[2];
 
+extern u32 apicid_sb800;
 
 extern u32 bus_type[256];
 extern u32 sbdn_sb800;
-u32 apicid_sb800;
-
-u8 picr_data[] = {
-  0x0B,0x0A,0x0B,0x05,0x1F,0x1F,0x1F,0x1F,0x50,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x1F,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0A,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x0B,0x0A,0x0B,0x05
-};
+
 u8 intr_data[] = {
-  0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-  0x1F,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x10,0x11,0x12,0x13
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,
+	[0x18] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
+	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x50] = 0x10,0x11,0x12,0x13
 };
 
-static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
-{
-  mc->mpc_length += length;
-  mc->mpc_entry_count++;
-}
-static void my_smp_write_bus(struct mp_config_table *mc,
-  unsigned char id, const char *bustype)
-{
-  struct mpc_config_bus *mpc;
-  mpc = smp_next_mpc_entry(mc);
-  memset(mpc, '\0', sizeof(*mpc));
-  mpc->mpc_type = MP_BUS;
-  mpc->mpc_busid = id;
-  memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
-  smp_add_mpc_entry(mc, sizeof(*mpc));
-}
 static void *smp_write_config_table(void *v)
 {
   struct mp_config_table *mc;
   int bus_isa;
-  int boot_apic_id;
-  unsigned apic_version;
-  unsigned cpu_features;
-  unsigned cpu_feature_flags;
-  struct cpuid_result result;
-  unsigned long cpu_flag;
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
   mptable_init(mc, LAPIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
-  /*Inagua used dure core cpu with one die */
-  boot_apic_id = lapicid();
-  apic_version = lapic_read(LAPIC_LVR) & 0xff;
-  result = cpuid(1);
-  cpu_features = result.eax;
-  cpu_feature_flags = result.edx;
-  cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR;
-  smp_write_processor(mc,
-      0, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
-
-  cpu_flag = MPC_CPU_ENABLED;
-  smp_write_processor(mc,
-      1, apic_version,
-      cpu_flag, cpu_features, cpu_feature_flags
-    );
+	smp_write_processors(mc);
 
   get_bus_conf();
 
-  //mptable_write_buses(mc, NULL, &bus_isa);
-  my_smp_write_bus(mc, 0, "PCI   ");
-  my_smp_write_bus(mc, 1, "PCI   ");
-  bus_isa = 0x02;
-  my_smp_write_bus(mc, bus_isa, "ISA   ");
+	mptable_write_buses(mc, NULL, &bus_isa);
 
   /* I/O APICs:   APIC ID Version State   Address */
 
-  device_t dev;
   u32 dword;
   u8 byte;
 
   ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
   dword &= 0xFFFFFFF0;
-  /* Set IO APIC ID onto IO_APIC_ID */
-  write32 (dword, 0x00);
-  write32 (dword + 0x10, IO_APIC_ID << 24);
-  apicid_sb800 = IO_APIC_ID;
   smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
 
-  /* PIC IRQ routine */
-  for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
-    outb(byte, 0xC00);
-    outb(picr_data[byte], 0xC01);
-  }
-
-  /* APIC IRQ routine */
   for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
     outb(byte | 0x80, 0xC00);
     outb(intr_data[byte], 0xC01);
@@ -141,55 +82,37 @@ static void *smp_write_config_table(void *v)
 #define IO_LOCAL_INT(type, intr, apicid, pin) \
   smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
 
-  //mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
-  /*I/O Ints:          Type    Trigger             Polarity               Bus ID   IRQ  APIC ID       PIN# */
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_sb800, 0x0);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_sb800, 0x1);
-  smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x2, apicid_sb800, 0x2);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_sb800, 0x3);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_sb800, 0x4);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  0, 0x49, apicid_sb800, 0x11);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_sb800, 0x6);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_sb800, 0x7);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_sb800, 0x8);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x9, apicid_sb800, 0x9);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0xa, apicid_sb800, 0xa);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,  bus_isa, 0x1c, apicid_sb800, 0x13);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_sb800, 0xc);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_sb800, 0xd);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_sb800, 0xe);
-  smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_sb800, 0xf);
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
 
   /* PCI interrupts are level triggered, and are
    * associated with a specific bus/device/function tuple.
    */
-#define PCI_INT(bus, dev, int_sign, pin) \
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+#if CONFIG_GENERATE_ACPI_TABLES == 0
+#define PCI_INT(bus, dev, fn, pin) \
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
+#else
+#define PCI_INT(bus, dev, fn, pin)
+#endif
 
   /* APU Internal Graphic Device*/
   PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
   PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
 
-  /* SMBUS */
+	//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
   PCI_INT(0x0, 0x14, 0x0, 0x10);
+	/* Southbridge HD Audio: */
+	PCI_INT(0x0, 0x14, 0x2, 0x12);
 
-  /* Southbridge HD Audio */
-  PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
-
-  /* USB */
-  PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+	PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
   PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
   PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
   PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
   PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
   PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
-  PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
 
   /* sata */
-  PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
   PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
 
-
   /* on board NIC & Slot PCIE.  */
 
   /* PCI slots */
@@ -215,21 +138,18 @@ static void *smp_write_config_table(void *v)
   PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
   PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
 
-  /* PCIe Lan*/
-  PCI_INT(0x0, 0x06, 0x0, 0x13);
-
-  /* FCH PCIe PortA */
+	/* PCIe PortA */
   PCI_INT(0x0, 0x15, 0x0, 0x10);
-  /* FCH PCIe PortB */
+	/* PCIe PortB */
   PCI_INT(0x0, 0x15, 0x1, 0x11);
-  /* FCH PCIe PortC */
+	/* PCIe PortC */
   PCI_INT(0x0, 0x15, 0x2, 0x12);
-  /* FCH PCIe PortD */
+	/* PCIe PortD */
   PCI_INT(0x0, 0x15, 0x3, 0x13);
 
   /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
-  IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
-  IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
   /* There is no extension information... */
 
   /* Compute the checksums */
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index aa7cb5c..87b2893 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -103,7 +103,7 @@
  * @breif INCHIP Sata Controller Mode
  *   NOTE: DO NOT ALLOW SATA & IDE use same mode
  */
-#define SATA_MODE			NATIVE_IDE_MODE
+#define SATA_MODE			CONFIG_SB800_SATA_MODE
 
 /**
  * @breif INCHIP Sata IDE Controller Mode
diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 88c018e..27022d4 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <lib.h>
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -25,9 +26,11 @@
 #include <arch/stages.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
+#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/kbc1100/kbc1100_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -35,21 +38,21 @@
 #include "pc80/i8259.c"
 #include "sb_cimx.h"
 #include "SBPLATFORM.h"
-#include <arch/cpu.h>
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-u32 agesawrapper_amdinitmmio(void);
-u32 agesawrapper_amdinitreset(void);
-u32 agesawrapper_amdinitearly(void);
-u32 agesawrapper_amdinitenv(void);
-u32 agesawrapper_amdinitlate(void);
-u32 agesawrapper_amdinitpost(void);
-u32 agesawrapper_amdinitmid(void);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* all cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
+	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+	/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	 */
+	__writemsr (0xc0010062, 0);
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_Poweron_Init();


From wmkamp at datakamp.de  Thu Jan 19 14:27:59 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Thu, 19 Jan 2012 14:27:59 +0100
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <F53A09371FB723428826B442A4B20A410908118E@sbjgexmb1.amd.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local><CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com><F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com><F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
	<F53A09371FB723428826B442A4B20A410908118E@sbjgexmb1.amd.com>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCF7@DATAKAMPONE.datakamp2008.local>



Hello Kerry,

if someone could tell me how debugging coreboot with SmartProbe really works under Ubuntu,
I will proceed. The Sage Wiki is not sufficient.
What happens if the LAN Chip GDB82574 generates interrupts after enumeration?

Regards

Wolfgang



Hello, Wolfgang

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Wolfgang Kamp - datakamp
> Sent: Wednesday, January 18, 2012 11:11 PM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Kerry, hello Marc,
> 
> sounds good but solves not my problem. The enumeration of the SB800 GPP
> ports works fine with Linux.
> But coreboot fails because the SB GPP ports are not yet initialized when
> coreboot probes them.
> The function sbPcieGppEarlyInit will be executed after coreboot PCI
> probing of the SB GPP ports.
> You can see that in late.c.
> I put that function now in the right place in the case (0x15<<0 | 0)
> statement so probing succeeds.
> And my Intel LAN GB82574 will be enumerated as I can see in the log.
> But if I do that coreboot hangs in tables.c with postcode 0x9c and I
> can't imagine why.
It seems that there is a resource allocation problem.
If you have a smartprobe to trace the code, you can find out what memory address read/write fail in tables.c

Thanks
Kerry

> I need the correct enumeration in coreboot because the Intel LAN chip
> tools only works under DOS.
> 
> Wolfgang
> 
> -----Urspr?ngliche Nachricht-----
> Von: She, Kerry [mailto:Kerry.She at amd.com]
> Gesendet: Mittwoch, 18. Januar 2012 08:49
> An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org; chia, kenneth
> Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> 
> Hello Marc and Wolfgang
> 
> > -----Original Message-----
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org]
> > On Behalf Of She, Kerry
> > Sent: Tuesday, January 17, 2012 4:07 PM
> > To: Marc Jones; Wolfgang Kamp - datakamp
> > Cc: coreboot at coreboot.org
> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
> >
> > Hello Walfqang,
> >
> > > -----Original Message-----
> > > From: coreboot-bounces at coreboot.org [mailto:coreboot-
> > bounces at coreboot.org]
> > > On Behalf Of Marc Jones
> > > Sent: Tuesday, January 17, 2012 3:23 AM
> > > To: Wolfgang Kamp - datakamp
> > > Cc: coreboot at coreboot.org
> > > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
> > > Initialization
> > >
> > > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
> > > <wmkamp at datakamp.de> wrote:
> > > > Hello,
> > > >
> > > >
> > > >
> > > > I found a problem with the PCI enumeration of the PCIe Ports in
> > > > the CIMX/SB800 Southbridge for the INAGUA platform.
> > > >
> > > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
> > > > function sb_Before_PCI_Init after
> > > >
> > > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
> > > > <<3)
> > |
> > > 0
> > > > are probed in the routine ../devices/pci_device.c function
> > > >
> > > > pci_probe_dev they are not yet initialized. The probing fails and
> > also
> > > > devices behind the bridge are not recognized.
> > > >
> > > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
> > > >
> > > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
> > > > <<3)
> > |
> > > 0 the
> > > > enumeration succeed but coreboot crashes later into nothing. The
> > > > Sage Debugger fails.
> > > >
> > > > I can't imagine why.
> > > >
> > > >
> > > >
> > > > Marc have you any idea?
> > >
> > > This looks like a problem in the sb800 cimx wrapper logic. Cimx
> > > doesn't treat the devices separately. it lumps all the configuration
> > > and enables together, making the coreboot chipset device enable
> > > callback fail to enable the device, so it gets disabled. The sb900
> > > wrapper appears to fix this issue with cimx setup in early init. You
> > > may want to try porting those changes to the sb800.
> > >
> > > I don't know why it fails later, but I assume it is due to the
> > > missing config since you moved the call earlier in the process. You
> > > could try calling it multiple times. I'm not sure how it handles that,
> though.
> > >
> > > Kerry,
> > > Do you have any comments?
> > If the enumeration fail, I suggest you should check the PCIE deassert
> > GPIO setting.
> > Thanks
> 
> I found the recent amd/inagua code in the git tree is not boot on my
> platform and more.
> I made an update to make my platform works now.
> The missing mainboard specific GPIO setting also added back, So the sb800
> GPP enumeration works now.
> 
> Please reference following link and the attachment.
> http://review.coreboot.org/#change,542
> http://review.coreboot.org/#change,543
> http://review.coreboot.org/#change,544
> http://review.coreboot.org/#change,545
> http://review.coreboot.org/#change,546
> 
> Thanks
> Kerry
> 
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot







From marcj303 at gmail.com  Thu Jan 19 18:48:22 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 19 Jan 2012 10:48:22 -0700
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <F53A09371FB723428826B442A4B20A41090811CC@sbjgexmb1.amd.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
	<CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
	<F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
	<CALrs_3jQBQG5k7DApO_MgUe5vozsce7yPJT3NQQmiZu5ETk+rg@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090811CC@sbjgexmb1.amd.com>
Message-ID: <CALrs_3jy78dQ3nigRYGU+c+==bhuU48S-F_a=hSg4qkgo-rsOQ@mail.gmail.com>

On Wed, Jan 18, 2012 at 7:34 PM, She, Kerry <Kerry.She at amd.com> wrote:
> Hello, Marc
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Marc Jones
>> Sent: Thursday, January 19, 2012 2:28 AM
>> To: Wolfgang Kamp - datakamp
>> Cc: coreboot at coreboot.org
>> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>>
>> On Wed, Jan 18, 2012 at 8:11 AM, Wolfgang Kamp - datakamp
>> <wmkamp at datakamp.de> wrote:
>> > Hello Kerry, hello Marc,
>> >
>> > sounds good but solves not my problem. The enumeration of the SB800 GPP
>> ports works fine with Linux.
>> > But coreboot fails because the SB GPP ports are not yet initialized
>> when coreboot probes them.
>> > The function sbPcieGppEarlyInit will be executed after coreboot PCI
>> probing of the SB GPP ports.
>> > You can see that in late.c.
>> > I put that function now in the right place in the case (0x15<<0 | 0)
>> statement so probing succeeds.
>> > And my Intel LAN GB82574 will be enumerated as I can see in the log.
>> > But if I do that coreboot hangs in tables.c with postcode 0x9c and I
>> can't imagine why.
>> > I need the correct enumeration in coreboot because the Intel LAN chip
>> tools only works under DOS.
>> >
>> > Wolfgang
>> >
>>
>> Kerry,
>>
>> I agree with Wolfgang. I think that the sb800 has an issue.
>>
>> >> > The sb900 wrapper appears to fix this issue with cimx setup in early
>> init.
> Yes, sb900 put the sb_before_pci_init wrapper call at romstage.
> The problem is we can't get the configuration information from devicetree.cb in this way,
> all the configuration option is defined in a header file.
>
>
>> The device isn't visible in late init. The coreboot chip device scan
>> will disable the device when it isn't found. The configuration needs
>> to be set in early init like the sb900. Do you agree?
> I think this is a compromise choice, we can unhide/hide the gpp device according to the devicetree.cb setting in sb800 dev_enable(), and then call the cimx function.
>
>
> BTW. We using this way in the RD890 wrapper.

OK, This is an obvious problem in the wrapper implementation. We need
to get these synced up. This highlights the problem of the additional
cimx config information that must be loaded in the cimx configuration
table file that isn't defined by devicetree.cb. Lets see if we can
work on this next.

Marc



> Thanks
>
> Kerry
>
>> Marc
>>
>>
>> > -----Urspr?ngliche Nachricht-----
>> > Von: She, Kerry [mailto:Kerry.She at amd.com]
>> > Gesendet: Mittwoch, 18. Januar 2012 08:49
>> > An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
>> > Cc: coreboot at coreboot.org; chia, kenneth
>> > Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>> >
>> > Hello Marc and Wolfgang
>> >
>> >> -----Original Message-----
>> >> From: coreboot-bounces at coreboot.org
>> >> [mailto:coreboot-bounces at coreboot.org]
>> >> On Behalf Of She, Kerry
>> >> Sent: Tuesday, January 17, 2012 4:07 PM
>> >> To: Marc Jones; Wolfgang Kamp - datakamp
>> >> Cc: coreboot at coreboot.org
>> >> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>> >>
>> >> Hello Walfqang,
>> >>
>> >> > -----Original Message-----
>> >> > From: coreboot-bounces at coreboot.org [mailto:coreboot-
>> >> bounces at coreboot.org]
>> >> > On Behalf Of Marc Jones
>> >> > Sent: Tuesday, January 17, 2012 3:23 AM
>> >> > To: Wolfgang Kamp - datakamp
>> >> > Cc: coreboot at coreboot.org
>> >> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
>> >> > Initialization
>> >> >
>> >> > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
>> >> > <wmkamp at datakamp.de> wrote:
>> >> > > Hello,
>> >> > >
>> >> > >
>> >> > >
>> >> > > I found a problem with the PCI enumeration of the PCIe Ports in
>> >> > > the CIMX/SB800 Southbridge for the INAGUA platform.
>> >> > >
>> >> > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
>> >> > > function sb_Before_PCI_Init after
>> >> > >
>> >> > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
>> >> > > <<3)
>> >> |
>> >> > 0
>> >> > > are probed in the routine ../devices/pci_device.c function
>> >> > >
>> >> > > pci_probe_dev they are not yet initialized. The probing fails and
>> >> also
>> >> > > devices behind the bridge are not recognized.
>> >> > >
>> >> > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
>> >> > >
>> >> > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
>> >> > > <<3)
>> >> |
>> >> > 0 the
>> >> > > enumeration succeed but coreboot crashes later into nothing. The
>> >> > > Sage Debugger fails.
>> >> > >
>> >> > > I can't imagine why.
>> >> > >
>> >> > >
>> >> > >
>> >> > > Marc have you any idea?
>> >> >
>> >> > This looks like a problem in the sb800 cimx wrapper logic. Cimx
>> >> > doesn't treat the devices separately. it lumps all the configuration
>> >> > and enables together, making the coreboot chipset device enable
>> >> > callback fail to enable the device, so it gets disabled. The sb900
>> >> > wrapper appears to fix this issue with cimx setup in early init. You
>> >> > may want to try porting those changes to the sb800.
>> >> >
>> >> > I don't know why it fails later, but I assume it is due to the
>> >> > missing config since you moved the call earlier in the process. You
>> >> > could try calling it multiple times. I'm not sure how it handles
>> that, though.
>> >> >
>> >> > Kerry,
>> >> > Do you have any comments?
>> >> If the enumeration fail, I suggest you should check the PCIE deassert
>> >> GPIO setting.
>> >> Thanks
>> >
>> > I found the recent amd/inagua code in the git tree is not boot on my
>> platform and more.
>> > I made an update to make my platform works now.
>> > The missing mainboard specific GPIO setting also added back, So the
>> sb800 GPP enumeration works now.
>> >
>> > Please reference following link and the attachment.
>> > http://review.coreboot.org/#change,542
>> > http://review.coreboot.org/#change,543
>> > http://review.coreboot.org/#change,544
>> > http://review.coreboot.org/#change,545
>> > http://review.coreboot.org/#change,546
>> >
>> > Thanks
>> > Kerry
>> >
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>>
>>
>>
>> --
>> http://se-eng.com
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
>



-- 
http://se-eng.com


From marcj303 at gmail.com  Thu Jan 19 18:53:06 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 19 Jan 2012 10:53:06 -0700
Subject: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCF7@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDCC9@DATAKAMPONE.datakamp2008.local>
	<CALrs_3hd-Zt1fvpXu8w_+MAesH9TYVdoQ3c_dBsCQOW3reEaGw@mail.gmail.com>
	<F53A09371FB723428826B442A4B20A41090155A5@sbjgexmb1.amd.com>
	<F53A09371FB723428826B442A4B20A4109080D5E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCEB@DATAKAMPONE.datakamp2008.local>
	<F53A09371FB723428826B442A4B20A410908118E@sbjgexmb1.amd.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDCF7@DATAKAMPONE.datakamp2008.local>
Message-ID: <CALrs_3jMRv2VsW=iRs9fsn-7SbWM45T_nXPJQh1Zbj7sWQ-MaA@mail.gmail.com>

On Thu, Jan 19, 2012 at 6:27 AM, Wolfgang Kamp - datakamp
<wmkamp at datakamp.de> wrote:
>
>
> Hello Kerry,
>
> if someone could tell me how debugging coreboot with SmartProbe really works under Ubuntu,
> I will proceed. The Sage Wiki is not sufficient.
> What happens if the LAN Chip GDB82574 generates interrupts after enumeration?
>
It depends on the mptable and/or acpi table. The kernel will ussually
tellyou if it is getting spurious interrupts, or not getting interrupt
is thinks it should.

You can contact me in IRC or gtalk if you want to talk about the
smartprobe setup.

Marc


> Regards
>
> Wolfgang
>
>
>
> Hello, Wolfgang
>
>> -----Original Message-----
>> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
>> On Behalf Of Wolfgang Kamp - datakamp
>> Sent: Wednesday, January 18, 2012 11:11 PM
>> To: coreboot at coreboot.org
>> Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>>
>> Hello Kerry, hello Marc,
>>
>> sounds good but solves not my problem. The enumeration of the SB800 GPP
>> ports works fine with Linux.
>> But coreboot fails because the SB GPP ports are not yet initialized when
>> coreboot probes them.
>> The function sbPcieGppEarlyInit will be executed after coreboot PCI
>> probing of the SB GPP ports.
>> You can see that in late.c.
>> I put that function now in the right place in the case (0x15<<0 | 0)
>> statement so probing succeeds.
>> And my Intel LAN GB82574 will be enumerated as I can see in the log.
>> But if I do that coreboot hangs in tables.c with postcode 0x9c and I
>> can't imagine why.
> It seems that there is a resource allocation problem.
> If you have a smartprobe to trace the code, you can find out what memory address read/write fail in tables.c
>
> Thanks
> Kerry
>
>> I need the correct enumeration in coreboot because the Intel LAN chip
>> tools only works under DOS.
>>
>> Wolfgang
>>
>> -----Urspr?ngliche Nachricht-----
>> Von: She, Kerry [mailto:Kerry.She at amd.com]
>> Gesendet: Mittwoch, 18. Januar 2012 08:49
>> An: She, Kerry; Marc Jones; Wolfgang Kamp - datakamp
>> Cc: coreboot at coreboot.org; chia, kenneth
>> Betreff: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>>
>> Hello Marc and Wolfgang
>>
>> > -----Original Message-----
>> > From: coreboot-bounces at coreboot.org
>> > [mailto:coreboot-bounces at coreboot.org]
>> > On Behalf Of She, Kerry
>> > Sent: Tuesday, January 17, 2012 4:07 PM
>> > To: Marc Jones; Wolfgang Kamp - datakamp
>> > Cc: coreboot at coreboot.org
>> > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port Initialization
>> >
>> > Hello Walfqang,
>> >
>> > > -----Original Message-----
>> > > From: coreboot-bounces at coreboot.org [mailto:coreboot-
>> > bounces at coreboot.org]
>> > > On Behalf Of Marc Jones
>> > > Sent: Tuesday, January 17, 2012 3:23 AM
>> > > To: Wolfgang Kamp - datakamp
>> > > Cc: coreboot at coreboot.org
>> > > Subject: Re: [coreboot] Issue with CIMX/SB800 PCIe Port
>> > > Initialization
>> > >
>> > > On Mon, Jan 16, 2012 at 10:18 AM, Wolfgang Kamp - datakamp
>> > > <wmkamp at datakamp.de> wrote:
>> > > > Hello,
>> > > >
>> > > >
>> > > >
>> > > > I found a problem with the PCI enumeration of the PCIe Ports in
>> > > > the CIMX/SB800 Southbridge for the INAGUA platform.
>> > > >
>> > > > The .../southbridge/amd/cimx/sb800/late.c routine calls the
>> > > > function sb_Before_PCI_Init after
>> > > >
>> > > > case (0x16 >>3) | 2. This means when the PCI Express ports (0x15
>> > > > <<3)
>> > |
>> > > 0
>> > > > are probed in the routine ../devices/pci_device.c function
>> > > >
>> > > > pci_probe_dev they are not yet initialized. The probing fails and
>> > also
>> > > > devices behind the bridge are not recognized.
>> > > >
>> > > > Behind the PCIe bridge I have an Intel 82574 LAN chip.
>> > > >
>> > > > But if I move the call to sb_Before_PCI_Init behind case ?(0x15
>> > > > <<3)
>> > |
>> > > 0 the
>> > > > enumeration succeed but coreboot crashes later into nothing. The
>> > > > Sage Debugger fails.
>> > > >
>> > > > I can't imagine why.
>> > > >
>> > > >
>> > > >
>> > > > Marc have you any idea?
>> > >
>> > > This looks like a problem in the sb800 cimx wrapper logic. Cimx
>> > > doesn't treat the devices separately. it lumps all the configuration
>> > > and enables together, making the coreboot chipset device enable
>> > > callback fail to enable the device, so it gets disabled. The sb900
>> > > wrapper appears to fix this issue with cimx setup in early init. You
>> > > may want to try porting those changes to the sb800.
>> > >
>> > > I don't know why it fails later, but I assume it is due to the
>> > > missing config since you moved the call earlier in the process. You
>> > > could try calling it multiple times. I'm not sure how it handles that,
>> though.
>> > >
>> > > Kerry,
>> > > Do you have any comments?
>> > If the enumeration fail, I suggest you should check the PCIE deassert
>> > GPIO setting.
>> > Thanks
>>
>> I found the recent amd/inagua code in the git tree is not boot on my
>> platform and more.
>> I made an update to make my platform works now.
>> The missing mainboard specific GPIO setting also added back, So the sb800
>> GPP enumeration works now.
>>
>> Please reference following link and the attachment.
>> http://review.coreboot.org/#change,542
>> http://review.coreboot.org/#change,543
>> http://review.coreboot.org/#change,544
>> http://review.coreboot.org/#change,545
>> http://review.coreboot.org/#change,546
>>
>> Thanks
>> Kerry
>>
>>
>> --
>> coreboot mailing list: coreboot at coreboot.org
>> http://www.coreboot.org/mailman/listinfo/coreboot
>
>
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



-- 
http://se-eng.com


From gerrit at coreboot.org  Fri Jan 20 06:44:38 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:38 +0100
Subject: [coreboot] New patch to review for coreboot: 45052d3 AGESA F15:
	AGESA family15 model 00-0fh cpu wrapper
References: <I7580bc063c09d99d3fca8b20cd39df2384a6ad44+0@gerrit.coreboot.org>
Message-ID: <I7580bc063c09d99d3fca8b20cd39df2384a6ad44+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/555

-gerrit

commit 45052d32dd94a81330d80c4c4825a7fdadb5062e
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:58:14 2012 +0800

    AGESA F15: AGESA family15 model 00-0fh cpu wrapper
    
    Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/cpu/amd/agesa/Kconfig                  |    7 +-
 src/cpu/amd/agesa/Makefile.inc             |    3 +-
 src/cpu/amd/agesa/family15/Kconfig         |   82 +++++++++++++++
 src/cpu/amd/agesa/family15/Makefile.inc    |   30 ++++++
 src/cpu/amd/agesa/family15/chip.h          |   23 +++++
 src/cpu/amd/agesa/family15/chip_name.c     |   25 +++++
 src/cpu/amd/agesa/family15/model_15_init.c |  147 ++++++++++++++++++++++++++++
 src/include/cpu/amd/amdfam15.h             |   41 ++++++++
 8 files changed, 356 insertions(+), 2 deletions(-)

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 60bb74b..8eaa11d 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,6 +17,11 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+config AMD_AGESA
+        bool
+        default n
+
 source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig
+source src/cpu/amd/agesa/family15/Kconfig
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 4331435..fb536dd 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -19,6 +19,7 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += family10
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 
 ramstage-y += apic_timer.c
 cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
new file mode 100644
index 0000000..0f2f920
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -0,0 +1,82 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config CPU_AMD_AGESA_FAMILY15
+	bool
+	select PCI_IO_CFG_EXT
+	select AMD_AGESA
+
+if CPU_AMD_AGESA_FAMILY15
+
+config CPU_AMD_SOCKET_G34
+	bool
+	default n
+	help
+	  AMD G34 Socket
+
+config CPU_AMD_SOCKET_C32
+	bool
+	default n
+	help
+	  AMD C32 Socket
+
+config CPU_AMD_SOCKET_AM3R2
+	bool
+	default n
+	help
+	  AMD AM3r2 Socket
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+
+config EXT_CONF_SUPPORT
+	bool
+	default n
+
+config CBB
+	hex
+	default 0x0
+
+config CDB
+	hex
+	default 0x18
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff80000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x80000
+
+config HAVE_INIT_TIMER
+	bool
+	default y
+
+config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
+        bool "Redirect AGESA IDS_HDT_CONSOLE to serial console"
+        default n
+        depends on CPU_AMD_AGESA_FAMILY15
+        help
+          This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
+
+          Warning: Only enable this option when debuging or tracing AMD AGESA code.
+
+endif #CPU_AMD_AGESA_FAMILY15
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
new file mode 100644
index 0000000..936d3c8
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -0,0 +1,30 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+subdirs-y += ../../mtrr
+subdirs-y += ../../../x86/tsc
+subdirs-y += ../../../x86/lapic
+subdirs-y += ../../../x86/cache
+subdirs-y += ../../../x86/mtrr
+subdirs-y += ../../../x86/pae
+subdirs-y += ../../../x86/smm
+
+ramstage-y += chip_name.c
+driver-y += model_15_init.c
+
diff --git a/src/cpu/amd/agesa/family15/chip.h b/src/cpu/amd/agesa/family15/chip.h
new file mode 100644
index 0000000..0171e7f
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_agesa_family15_ops;
+
+struct cpu_amd_agesa_family15_config {
+};
diff --git a/src/cpu/amd/agesa/family15/chip_name.c b/src/cpu/amd/agesa/family15/chip_name.c
new file mode 100644
index 0000000..963a423
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/chip_name.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_agesa_family15_ops = {
+	CHIP_NAME("AMD CPU Family 15h")
+};
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
new file mode 100644
index 0000000..d100338
--- /dev/null
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/pae.h>
+
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/amdfam15.h>
+
+static msr_t rdmsr_amd(u32 index)
+{
+	msr_t result;
+	__asm__ __volatile__(
+			"rdmsr"
+			:"=a"(result.lo), "=d"(result.hi)
+			:"c"(index), "D"(0x9c5a203a)
+			);
+	return result;
+}
+
+static void wrmsr_amd(u32 index, msr_t msr)
+{
+	__asm__ __volatile__(
+			"wrmsr"
+			: /* No outputs */
+			:"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
+			);
+}
+
+static void model_15_init(device_t dev)
+{
+	printk(BIOS_DEBUG, "Model 15 Init.\n");
+
+	u8 i;
+	msr_t msr;
+	int msrno;
+#if CONFIG_LOGICAL_CPUS == 1
+	u32 siblings;
+#endif
+
+	disable_cache ();
+	/* Enable access to AMD RdDram and WrDram extension bits */
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, msr);
+
+	// BSP: make a0000-bffff UC, c0000-fffff WB, same as ApMtrrSettingsList for APs
+	msr.lo = msr.hi = 0;
+	wrmsr (0x259, msr);
+	msr.lo = msr.hi = 0x1e1e1e1e;
+	for (msrno = 0x268; msrno <= 0x26f; msrno++)
+		wrmsr (msrno, msr);
+
+	msr.lo = 0x04040404; msr.hi = 0x04040404;
+	wrmsr(0x259, msr);
+
+	/* disable access to AMD RdDram and WrDram extension bits */
+	msr = rdmsr(SYSCFG_MSR);
+	msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
+	wrmsr(SYSCFG_MSR, msr);
+	enable_cache ();
+
+	/* zero the machine check error status registers */
+	msr.lo = 0;
+	msr.hi = 0;
+	for (i = 0; i < 6; i++) {
+		wrmsr(MCI_STATUS + (i * 4), msr);
+	}
+
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+#if CONFIG_LOGICAL_CPUS == 1
+	siblings = cpuid_ecx(0x80000008) & 0xff;
+
+	if (siblings > 0) {
+		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
+		msr.lo |= 1 << 28;
+		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
+
+		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
+		msr.hi |= 1 << (33 - 32);
+		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
+	}
+	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
+#endif
+
+	/* DisableCf8ExtCfg */
+	msr = rdmsr(NB_CFG_MSR);
+	msr.hi &= ~(1 << (46 - 32));
+	wrmsr(NB_CFG_MSR, msr);
+
+
+	/* Write protect SMM space with SMMLOCK. */
+	msr = rdmsr(HWCR_MSR);
+	msr.lo |= (1 << 0);
+	wrmsr(HWCR_MSR, msr);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init = model_15_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_AMD, 0x100F80},    /* HY-D0 */
+	{ X86_VENDOR_AMD, 0x100F90},    /* HY-D0 */
+	{ X86_VENDOR_AMD, 0x100F81},    /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x100F91},    /* HY-D1 */
+	{ X86_VENDOR_AMD, 0x600f00 },   /* OR_A0x */
+	{ X86_VENDOR_AMD, 0x600f01 },   /* OR_A0x */
+	{ X86_VENDOR_AMD, 0x600f10 },   /* OR_B0x */
+	{ X86_VENDOR_AMD, 0x600f11 },   /* OR_B1x */
+	{ X86_VENDOR_AMD, 0x600f12 },   /* OR_B2x */
+	{ X86_VENDOR_AMD, 0x600f13 },   /* OR_B3x */
+	{ X86_VENDOR_AMD, 0x600f20 },   /* OR_C0x */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver model_15 __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
new file mode 100644
index 0000000..3d300de
--- /dev/null
+++ b/src/include/cpu/amd/amdfam15.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef CPU_AMD_FAM15_H
+#define CPU_AMD_FAM15_H
+
+#include <cpu/x86/msr.h>
+
+#define MCI_STATUS			0x00000401
+#define HWCR_MSR			0xC0010015
+#define NB_CFG_MSR			0xC001001f
+
+#define LS_CFG_MSR			0xC0011020
+#define IC_CFG_MSR			0xC0011021
+#define DC_CFG_MSR			0xC0011022
+#define CU_CFG_MSR			0xC0011023
+#define CU_CFG2_MSR			0xC001102A
+
+#define CPU_ID_FEATURES_MSR		0xC0011004
+#define CPU_ID_EXT_FEATURES_MSR		0xC0011005
+
+static msr_t rdmsr_amd(u32 index);
+static void wrmsr_amd(u32 index, msr_t msr);
+
+#endif /* CPU_AMD_FAM15_H */


From gerrit at coreboot.org  Fri Jan 20 06:44:40 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:40 +0100
Subject: [coreboot] New patch to review for coreboot: 8a593e4 AGESA F15:
	AGESA family15 model 00-0fh northbridge wrapper
References: <I87c4d47f19161c604b0285102bb3809c8337375a+0@gerrit.coreboot.org>
Message-ID: <I87c4d47f19161c604b0285102bb3809c8337375a+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/556

-gerrit

commit 8a593e46648c43b27eece78406748f7f9867377c
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:58:34 2012 +0800

    AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
    
    Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/northbridge/amd/agesa/Kconfig                  |    3 +-
 src/northbridge/amd/agesa/Makefile.inc             |    3 +-
 src/northbridge/amd/agesa/family15/Kconfig         |   49 +
 src/northbridge/amd/agesa/family15/Makefile.inc    |   20 +
 src/northbridge/amd/agesa/family15/bootblock.c     |   25 +
 src/northbridge/amd/agesa/family15/chip.h          |   24 +
 src/northbridge/amd/agesa/family15/northbridge.c   | 1174 ++++++++++++++++++++
 src/northbridge/amd/agesa/family15/northbridge.h   |   26 +
 .../amd/agesa/family15/root_complex/Kconfig        |    2 +
 .../amd/agesa/family15/root_complex/chip.h         |   24 +
 10 files changed, 1348 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 3bcb0bb..2ed9fd5 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -24,4 +24,5 @@ config CONSOLE_VGA_MULTI
 source src/northbridge/amd/agesa/family10/Kconfig
 source src/northbridge/amd/agesa/family12/Kconfig
 source src/northbridge/amd/agesa/family14/Kconfig
+source src/northbridge/amd/agesa/family15/Kconfig
 
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 1da8f60..eef1cd3 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -19,3 +19,4 @@
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10) += family10
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
diff --git a/src/northbridge/amd/agesa/family15/Kconfig b/src/northbridge/amd/agesa/family15/Kconfig
new file mode 100644
index 0000000..52f7a1e
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/Kconfig
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+config NORTHBRIDGE_AMD_AGESA_FAMILY15
+	bool
+	select HAVE_DEBUG_RAM_SETUP
+	select HAVE_DEBUG_SMBUS
+	select HYPERTRANSPORT_PLUGIN_SUPPORT
+	select MMCONF_SUPPORT
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+
+if NORTHBRIDGE_AMD_AGESA_FAMILY15
+config HT3_SUPPORT
+	bool
+	default y
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xF8000000
+config MMCONF_BUS_NUMBER
+	int
+	default 64
+config BOOTBLOCK_NORTHBRIDGE_INIT
+  string
+  default "northbridge/amd/agesa/family15/bootblock.c"
+endif #NORTHBRIDGE_AMD_AGESA_FAMILY15
+
+source "src/northbridge/amd/agesa/family15/root_complex/Kconfig"
diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc
new file mode 100644
index 0000000..255fe10
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
diff --git a/src/northbridge/amd/agesa/family15/bootblock.c b/src/northbridge/amd/agesa/family15/bootblock.c
new file mode 100644
index 0000000..fc62c3e
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/bootblock.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+
+static void bootblock_northbridge_init(void) {
+}
diff --git a/src/northbridge/amd/agesa/family15/chip.h b/src/northbridge/amd/agesa/family15/chip.h
new file mode 100644
index 0000000..cec1fc4
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_family15_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_family15_ops;
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
new file mode 100644
index 0000000..c16c8d3
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -0,0 +1,1174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+
+#include <cpu/x86/lapic.h>
+
+#include <Porting.h>
+#include <AGESA.h>
+#include <Options.h>
+#include <Topology.h>
+#include <cpu/amd/amdfam15.h>
+#include <cpuRegisters.h>
+#include "agesawrapper.h"
+#include "root_complex/chip.h"
+#include "northbridge.h"
+#include "chip.h"
+#if CONFIG_AMD_SB_CIMX
+#include "sb_cimx.h"
+#endif
+
+#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)
+
+#if (defined CONFIG_EXT_CONF_SUPPORT) && CONFIG_EXT_CONF_SUPPORT == 1
+#error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!
+#endif
+
+typedef struct dram_base_mask {
+	u32 base; //[47:27] at [28:8]
+	u32 mask; //[47:27] at [28:8] and enable at bit 0
+} dram_base_mask_t;
+
+static unsigned node_nums;
+static unsigned sblink;
+static device_t __f0_dev[MAX_NODE_NUMS];
+static device_t __f1_dev[MAX_NODE_NUMS];
+static device_t __f2_dev[MAX_NODE_NUMS];
+static device_t __f4_dev[MAX_NODE_NUMS];
+static unsigned fx_devs = 0;
+
+
+static dram_base_mask_t get_dram_base_mask(u32 nodeid)
+{
+	device_t dev;
+	dram_base_mask_t d;
+	dev = __f1_dev[0];
+	u32 temp;
+	temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
+	d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out  DramMask [26:24] too
+	temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+	d.mask |= temp<<21;
+	temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16]
+	d.mask |= (temp & 1); // enable bit
+	d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too
+	temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0]
+	d.base |= temp<<21;
+	return d;
+}
+
+static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
+			u32 io_min, u32 io_max)
+{
+	u32 i;
+	u32 tempreg;
+	/* io range allocation */
+	tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit
+	for (i=0; i<node_nums; i++)
+		pci_write_config32(__f1_dev[i], reg+4, tempreg);
+	tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4));	      //base :ISA and VGA ?
+#if 0
+	// FIXME: can we use VGA reg instead?
+	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+		printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link %s\n",
+				__func__, dev_path(dev), link);
+		tempreg |= PCI_IO_BASE_VGA_EN;
+	}
+	if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+		tempreg |= PCI_IO_BASE_NO_ISA;
+	}
+#endif
+	for (i=0; i<node_nums; i++)
+		pci_write_config32(__f1_dev[i], reg, tempreg);
+}
+
+static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes)
+{
+	u32 i;
+	u32 tempreg;
+	/* io range allocation */
+	tempreg = (nodeid&0xf) | (linkn<<4) |	 (mmio_max&0xffffff00); //limit
+	for (i=0; i<nodes; i++)
+		pci_write_config32(__f1_dev[i], reg+4, tempreg);
+	tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
+	for (i=0; i<node_nums; i++)
+		pci_write_config32(__f1_dev[i], reg, tempreg);
+}
+
+static device_t get_node_pci(u32 nodeid, u32 fn)
+{
+#if MAX_NODE_NUMS == 64
+	if (nodeid < 32) {
+		return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+	} else {
+		return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn));
+	}
+#else
+	return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn));
+#endif
+}
+
+static void get_fx_devs(void)
+{
+	int i;
+	for (i = 0; i < MAX_NODE_NUMS; i++) {
+		__f0_dev[i] = get_node_pci(i, 0);
+		__f1_dev[i] = get_node_pci(i, 1);
+		__f2_dev[i] = get_node_pci(i, 2);
+		__f4_dev[i] = get_node_pci(i, 4);
+		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+			fx_devs = i+1;
+	}
+	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+		die("Cannot find 0:0x18.[0|1]\n");
+	}
+	printk(BIOS_DEBUG, "fx_devs=0x%x\n", fx_devs);
+}
+
+static u32 f1_read_config32(unsigned reg)
+{
+	if (fx_devs == 0)
+		get_fx_devs();
+	return pci_read_config32(__f1_dev[0], reg);
+}
+
+static void f1_write_config32(unsigned reg, u32 value)
+{
+	int i;
+	if (fx_devs == 0)
+		get_fx_devs();
+	for(i = 0; i < fx_devs; i++) {
+		device_t dev;
+		dev = __f1_dev[i];
+		if (dev && dev->enabled) {
+			pci_write_config32(dev, reg, value);
+		}
+	}
+}
+
+static u32 amdfam15_nodeid(device_t dev)
+{
+#if MAX_NODE_NUMS == 64
+	unsigned busn;
+	busn = dev->bus->secondary;
+	if (busn != CONFIG_CBB) {
+		return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32;
+	} else {
+		return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+	}
+
+#else
+	return (dev->path.pci.devfn >> 3) - CONFIG_CDB;
+#endif
+}
+
+static void set_vga_enable_reg(u32 nodeid, u32 linkn)
+{
+	u32 val;
+
+	val =  1 | (nodeid<<4) | (linkn<<12);
+	/* it will routing
+	 * (1)mmio 0xa0000:0xbffff
+	 * (2)io   0x3b0:0x3bb, 0x3c0:0x3df
+	 */
+	f1_write_config32(0xf4, val);
+
+}
+
+/**
+ * @return
+ *  @retval 2  resoure not exist, usable
+ *  @retval 0  resource exist, not usable
+ *  @retval 1  resource exist, resource has been allocated before
+ */
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+			unsigned goal_link)
+{
+	struct resource *res;
+	unsigned nodeid, link = 0;
+	int result;
+	res = 0;
+	for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
+		device_t dev;
+		dev = __f0_dev[nodeid];
+		if (!dev)
+			continue;
+		for (link = 0; !res && (link < 8); link++) {
+			res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
+		}
+	}
+	result = 2;
+	if (res) {
+		result = 0;
+		if ((goal_link == (link - 1)) &&
+			(goal_nodeid == (nodeid - 1)) &&
+			(res->flags <= 1)) {
+			result = 1;
+		}
+	}
+	return result;
+}
+
+static struct resource *amdfam15_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+{
+	struct resource *resource;
+	u32 free_reg, reg;
+	resource = 0;
+	free_reg = 0;
+	for (reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+		int result;
+		result = reg_useable(reg, dev, nodeid, link);
+		if (result == 1) {
+			/* I have been allocated this one */
+			break;
+		}
+		else if (result > 1) {
+			/* I have a free register pair */
+			free_reg = reg;
+		}
+	}
+	if (reg > 0xd8) {
+		reg = free_reg; // if no free, the free_reg still be 0
+	}
+
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+
+	return resource;
+}
+
+static struct resource *amdfam15_find_mempair(device_t dev, u32 nodeid, u32 link)
+{
+	struct resource *resource;
+	u32 free_reg, reg;
+	resource = 0;
+	free_reg = 0;
+	for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
+		int result;
+		result = reg_useable(reg, dev, nodeid, link);
+		if (result == 1) {
+			/* I have been allocated this one */
+			break;
+		}
+		else if (result > 1) {
+			/* I have a free register pair */
+			free_reg = reg;
+		}
+	}
+	if (reg > 0xb8) {
+		reg = free_reg;
+	}
+
+	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
+	return resource;
+}
+
+
+static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link)
+{
+	struct resource *resource;
+
+	/* Initialize the io space constraints on the current bus */
+	resource = amdfam15_find_iopair(dev, nodeid, link);
+	if (resource) {
+		u32 align;
+		align = log2(HT_IO_HOST_ALIGN);
+		resource->base	= 0;
+		resource->size	= 0;
+		resource->align = align;
+		resource->gran	= align;
+		resource->limit = 0xffffUL;
+		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
+	}
+
+	/* Initialize the prefetchable memory constraints on the current bus */
+	resource = amdfam15_find_mempair(dev, nodeid, link);
+	if (resource) {
+		resource->base = 0;
+		resource->size = 0;
+		resource->align = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
+		resource->limit = 0xffffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+		resource->flags |= IORESOURCE_BRIDGE;
+	}
+
+
+	/* Initialize the memory constraints on the current bus */
+	resource = amdfam15_find_mempair(dev, nodeid, link);
+	if (resource) {
+		resource->base = 0;
+		resource->size = 0;
+		resource->align = log2(HT_MEM_HOST_ALIGN);
+		resource->gran = log2(HT_MEM_HOST_ALIGN);
+		resource->limit = 0xffffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
+	}
+
+}
+
+
+static void read_resources(device_t dev)
+{
+	u32 nodeid;
+	struct bus *link;
+
+#if CONFIG_AMD_SB_CIMX
+	//sb_Before_Pci_Init();
+#endif
+	nodeid = amdfam15_nodeid(dev);
+	for (link = dev->link_list; link; link = link->next) {
+		if (link->children) {
+			amdfam15_link_read_bases(dev, nodeid, link->link_num);
+		}
+	}
+}
+
+
+static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
+{
+	resource_t rbase, rend;
+	unsigned reg, link_num;
+	char buf[50];
+
+
+	/* Make certain the resource has actually been set */
+	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
+		return;
+	}
+
+	/* If I have already stored this resource don't worry about it */
+	if (resource->flags & IORESOURCE_STORED) {
+		return;
+	}
+
+	/* Only handle PCI memory and IO resources */
+	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+		return;
+
+	/* Ensure I am actually looking at a resource of function 1 */
+	if ((resource->index & 0xffff) < 0x1000) {
+		return;
+	}
+	/* Get the base address */
+	rbase = resource->base;
+
+	/* Get the limit (rounded up) */
+	rend  = resource_end(resource);
+
+	/* Get the register and link */
+	reg  = resource->index & 0xfff; // 4k
+	link_num = IOINDEX_LINK(resource->index);
+
+	if (resource->flags & IORESOURCE_IO) {
+		set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
+	}
+	else if (resource->flags & IORESOURCE_MEM) {
+		set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums) ;// [39:8]
+	}
+	resource->flags |= IORESOURCE_STORED;
+	sprintf(buf, " <node %x link %x>",
+			nodeid, link_num);
+	report_resource_stored(dev, resource, buf);
+}
+
+/**
+ * I tried to reuse the resource allocation code in set_resource()
+ * but it is too difficult to deal with the resource allocation magic.
+ */
+
+static void create_vga_resource(device_t dev, unsigned nodeid)
+{
+	struct bus *link;
+
+
+	/* find out which link the VGA card is connected,
+	 * we only deal with the 'first' vga card */
+	for (link = dev->link_list; link; link = link->next) {
+		if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+			extern device_t vga_pri; // the primary vga device, defined in device.c
+			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
+					link->secondary,link->subordinate);
+			/* We need to make sure the vga_pri is under the link */
+			if((vga_pri->bus->secondary >= link->secondary ) &&
+					(vga_pri->bus->secondary <= link->subordinate )
+			  )
+#endif
+				break;
+		}
+	}
+
+	/* no VGA card installed */
+	if (link == NULL)
+		return;
+
+	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink);
+	set_vga_enable_reg(nodeid, sblink);
+}
+
+
+static void set_resources(device_t dev)
+{
+	unsigned nodeid;
+	struct bus *bus;
+	struct resource *res;
+
+	/* Find the nodeid */
+	nodeid = amdfam15_nodeid(dev);
+
+	create_vga_resource(dev, nodeid); //TODO: do we need this?
+
+	/* Set each resource we have found */
+	for (res = dev->resource_list; res; res = res->next) {
+		set_resource(dev, res, nodeid);
+	}
+
+	for (bus = dev->link_list; bus; bus = bus->next) {
+		if (bus->children) {
+			assign_resources(bus);
+		}
+	}
+}
+
+static void northbridge_init(struct device *dev)
+{
+}
+
+static unsigned scan_chains(device_t dev, unsigned max)
+{
+	unsigned nodeid;
+	struct bus *link;
+	device_t io_hub = NULL;
+	u32 next_unitid = 0x18;
+	nodeid = amdfam15_nodeid(dev);
+	if (nodeid == 0) {
+		for (link = dev->link_list; link; link = link->next) {
+			//if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */
+			if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */
+				io_hub = link->children;
+				if (!io_hub || !io_hub->enabled) {
+					die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n");
+				}
+				/* Now that nothing is overlapping it is safe to scan the children. */
+				max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0);
+			}
+		}
+	}
+	return max;
+}
+
+static struct device_operations northbridge_operations = {
+	.read_resources	  = read_resources,
+	.set_resources	  = set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = northbridge_init,
+	.scan_bus	  = scan_chains,
+	.enable		  = 0,
+	.ops_pci	  = 0,
+};
+
+static const struct pci_driver family15_northbridge __pci_driver = {
+	.ops	= &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x1600,
+};
+
+static const struct pci_driver family10_northbridge __pci_driver = {
+	.ops	= &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x1200,
+};
+
+struct chip_operations northbridge_amd_agesa_family15_ops = {
+	CHIP_NAME("AMD FAM15 Northbridge")
+	.enable_dev = 0,
+};
+
+static void domain_read_resources(device_t dev)
+{
+	unsigned reg;
+
+
+	/* Find the already assigned resource pairs */
+	get_fx_devs();
+	for (reg = 0x80; reg <= 0xd8; reg+= 0x08) {
+		u32 base, limit;
+		base  = f1_read_config32(reg);
+		limit = f1_read_config32(reg + 0x04);
+		/* Is this register allocated? */
+		if ((base & 3) != 0) {
+			unsigned nodeid, reg_link;
+			device_t reg_dev;
+			if (reg<0xc0) { // mmio
+				nodeid = (limit & 0xf) + (base&0x30);
+			} else { // io
+				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
+			}
+			reg_link = (limit >> 4) & 7;
+			reg_dev = __f0_dev[nodeid];
+			if (reg_dev) {
+				/* Reserve the resource  */
+				struct resource *res;
+				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+				if (res) {
+					res->flags = 1;
+				}
+			}
+		}
+	}
+	/* FIXME: do we need to check extend conf space?
+	   I don't believe that much preset value */
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 0
+	pci_domain_read_resources(dev);
+
+
+#else
+	struct bus *link;
+	struct resource *resource;
+	for (link=dev->link_list; link; link = link->next) {
+		/* Initialize the system wide io space constraints */
+		resource = new_resource(dev, 0|(link->link_num<<2));
+		resource->base	= 0x400;
+		resource->limit = 0xffffUL;
+		resource->flags = IORESOURCE_IO;
+
+		/* Initialize the system wide prefetchable memory resources constraints */
+		resource = new_resource(dev, 1|(link->link_num<<2));
+		resource->limit = 0xfcffffffffULL;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+		/* Initialize the system wide memory resources constraints */
+		resource = new_resource(dev, 2|(link->link_num<<2));
+		resource->limit = 0xfcffffffffULL;
+		resource->flags = IORESOURCE_MEM;
+	}
+#endif
+}
+
+static void domain_enable_resources(device_t dev)
+{
+	u32 val;
+	/* Must be called after PCI enumeration and resource allocation */
+	printk(BIOS_DEBUG, "\nFam15 - domain_enable_resources: AmdInitMid.\n");
+	val = agesawrapper_amdinitmid();
+	if (val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitmid failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
+}
+
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+struct hw_mem_hole_info {
+	unsigned hole_startk;
+	int node_id;
+};
+static struct hw_mem_hole_info get_hw_mem_hole_info(void)
+{
+	struct hw_mem_hole_info mem_hole;
+	int i;
+	mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+	mem_hole.node_id = -1;
+	for (i = 0; i < node_nums; i++) {
+		dram_base_mask_t d;
+		u32 hole;
+		d = get_dram_base_mask(i);
+		if (!(d.mask & 1)) continue; // no memory on this node
+		hole = pci_read_config32(__f1_dev[i], 0xf0);
+		if (hole & 1) { // we find the hole
+			mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+			mem_hole.node_id = i; // record the node No with hole
+			break; // only one hole
+		}
+	}
+	//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
+	if (mem_hole.node_id == -1) {
+		resource_t limitk_pri = 0;
+		for (i=0; i<node_nums; i++) {
+			dram_base_mask_t d;
+			resource_t base_k, limit_k;
+			d = get_dram_base_mask(i);
+			if (!(d.base & 1)) continue;
+			base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+			if (base_k > 4 *1024 * 1024) break; // don't need to go to check
+			if (limitk_pri != base_k) { // we find the hole
+				mem_hole.hole_startk = (unsigned)limitk_pri; // must beblow 4G
+				mem_hole.node_id = i;
+				break; //only one hole
+			}
+			limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
+			limitk_pri = limit_k;
+		}
+	}
+	return mem_hole;
+}
+#endif
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+#if CONFIG_GFXUMA == 1
+extern uint64_t uma_memory_base, uma_memory_size;
+static void add_uma_resource(struct device *dev, int index)
+{
+	struct resource *resource;
+
+	printk(BIOS_DEBUG, "Adding UMA memory area\n");
+	resource = new_resource(dev, index);
+	resource->base = (resource_t) uma_memory_base;
+	resource->size = (resource_t) uma_memory_size;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+			IORESOURCE_FIXED | IORESOURCE_STORED |
+			IORESOURCE_ASSIGNED;
+}
+#endif
+
+static void domain_set_resources(device_t dev)
+{
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+	struct resource *io, *mem1, *mem2;
+	struct resource *res;
+#endif
+	unsigned long mmio_basek;
+	u32 pci_tolm;
+	int i, idx;
+	struct bus *link;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	struct hw_mem_hole_info mem_hole;
+	u32 reset_memhole = 1;
+#endif
+
+#if CONFIG_PCI_64BIT_PREF_MEM == 1
+
+	for (link = dev->link_list; link; link = link->next) {
+		/* Now reallocate the pci resources memory with the
+		 * highest addresses I can manage.
+		 */
+		mem1 = find_resource(dev, 1|(link->link_num<<2));
+		mem2 = find_resource(dev, 2|(link->link_num<<2));
+
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+				mem1->base, mem1->limit, mem1->size, mem1->align);
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+				mem2->base, mem2->limit, mem2->size, mem2->align);
+
+		/* See if both resources have roughly the same limits */
+		if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
+				((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
+		{
+			/* If so place the one with the most stringent alignment first */
+			if (mem2->align > mem1->align) {
+				struct resource *tmp;
+				tmp = mem1;
+				mem1 = mem2;
+				mem2 = tmp;
+			}
+			/* Now place the memory as high up as it will go */
+			mem2->base = resource_max(mem2);
+			mem1->limit = mem2->base - 1;
+			mem1->base = resource_max(mem1);
+		}
+		else {
+			/* Place the resources as high up as they will go */
+			mem2->base = resource_max(mem2);
+			mem1->base = resource_max(mem1);
+		}
+
+		printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+				mem1->base, mem1->limit, mem1->size, mem1->align);
+		printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+				mem2->base, mem2->limit, mem2->size, mem2->align);
+	}
+
+	for (res = &dev->resource_list; res; res = res->next)
+	{
+		res->flags |= IORESOURCE_ASSIGNED;
+		res->flags |= IORESOURCE_STORED;
+		report_resource_stored(dev, res, "");
+	}
+#endif
+
+	pci_tolm = 0xffffffffUL;
+	for (link = dev->link_list; link; link = link->next) {
+		pci_tolm = find_pci_tolm(link);
+	}
+
+	// FIXME handle interleaved nodes. If you fix this here, please fix
+	// amdk8, too.
+	mmio_basek = pci_tolm >> 10;
+	/* Round mmio_basek to something the processor can support */
+	mmio_basek &= ~((1 << 6) -1);
+
+	// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+	// MMIO hole. If you fix this here, please fix amdk8, too.
+	/* Round the mmio hole to 64M */
+	mmio_basek &= ~((64*1024) - 1);
+
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+	/* if the hw mem hole is already set in raminit stage, here we will compare
+	 * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
+	 * use hole_basek as mmio_basek and we don't need to reset hole.
+	 * otherwise We reset the hole to the mmio_basek
+	 */
+
+	mem_hole = get_hw_mem_hole_info();
+
+	// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+	if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
+		mmio_basek = mem_hole.hole_startk;
+		reset_memhole = 0;
+	}
+#endif
+
+	idx = 0x10;
+	for (i = 0; i < node_nums; i++) {
+		dram_base_mask_t d;
+		resource_t basek, limitk, sizek; // 4 1T
+
+		d = get_dram_base_mask(i);
+
+		if (!(d.mask & 1)) continue;
+		basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here
+		limitk = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9 ;
+
+		sizek = limitk - basek;
+
+
+		/* see if we need a hole from 0xa0000 to 0xbffff */
+		if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) {
+			ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek);
+			idx += 0x10;
+			basek = (8*64)+(16*16);
+			sizek = limitk - ((8*64)+(16*16));
+
+		}
+
+		//printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk);
+
+		/* split the region to accomodate pci memory space */
+		if ((basek < 4*1024*1024 ) && (limitk > mmio_basek)) {
+			if (basek <= mmio_basek) {
+				unsigned pre_sizek;
+				pre_sizek = mmio_basek - basek;
+				if (pre_sizek>0) {
+					ram_resource(dev, (idx | i), basek, pre_sizek);
+					idx += 0x10;
+					sizek -= pre_sizek;
+#if CONFIG_WRITE_HIGH_TABLES==1
+					if (high_tables_base==0) {
+						/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+						high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
+						high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+#endif
+						high_tables_size = HIGH_TABLES_SIZE * 1024;
+						printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
+							 HIGH_TABLES_SIZE, high_tables_base);
+					}
+#endif
+				}
+				basek = mmio_basek;
+			}
+			if ((basek + sizek) <= 4*1024*1024) {
+				sizek = 0;
+			}
+			else {
+				basek = 4*1024*1024;
+				sizek -= (4*1024*1024 - mmio_basek);
+			}
+		}
+
+#if CONFIG_GFXUMA == 1
+		/* Deduct uma memory before reporting because
+		 * this is what the mtrr code expects */
+		sizek -= uma_memory_size / 1024;
+#endif
+		ram_resource(dev, (idx | i), basek, sizek);
+		idx += 0x10;
+#if CONFIG_WRITE_HIGH_TABLES==1
+		printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+				i, mmio_basek, basek, limitk);
+		if (high_tables_base==0) {
+			/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+			high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
+			high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+#endif
+			high_tables_size = HIGH_TABLES_SIZE * 1024;
+		}
+#endif
+	}
+
+#if CONFIG_GFXUMA == 1
+	add_uma_resource(dev, 7);
+#endif
+
+	for(link = dev->link_list; link; link = link->next) {
+		if (link->children) {
+			assign_resources(link);
+		}
+	}
+}
+
+
+static struct device_operations pci_domain_ops = {
+	.read_resources	  = domain_read_resources,
+	.set_resources	  = domain_set_resources,
+	.enable_resources = domain_enable_resources,
+	.init		  = NULL,
+	.scan_bus	  = pci_domain_scan_bus,
+
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+
+static void sysconf_init(device_t dev) // first node
+{
+	sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1
+	node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0]
+}
+
+static void add_more_links(device_t dev, unsigned total_links)
+{
+	struct bus *link, *last = NULL;
+	int link_num;
+
+	for (link = dev->link_list; link; link = link->next)
+		last = link;
+
+	if (last) {
+		int links = total_links - last->link_num;
+		link_num = last->link_num;
+		if (links > 0) {
+			link = malloc(links*sizeof(*link));
+			if (!link)
+				die("Couldn't allocate more links!\n");
+			memset(link, 0, links*sizeof(*link));
+			last->next = link;
+		}
+	}
+	else {
+		link_num = -1;
+		link = malloc(total_links*sizeof(*link));
+		memset(link, 0, total_links*sizeof(*link));
+		dev->link_list = link;
+	}
+
+	for (link_num = link_num + 1; link_num < total_links; link_num++) {
+		link->link_num = link_num;
+		link->dev = dev;
+		link->next = link + 1;
+		last = link;
+		link = link->next;
+	}
+	last->next = NULL;
+}
+
+/* dummy read_resources */
+static void lapic_read_resources(device_t dev)
+{
+}
+
+static struct device_operations lapic_ops = {
+	.read_resources   = lapic_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = 0,
+	.scan_bus         = 0,
+	.enable           = 0,
+	.ops_pci          = 0,
+};
+
+static u32 cpu_bus_scan(device_t dev, u32 max)
+{
+	struct bus *cpu_bus;
+	device_t dev_mc;
+#if CONFIG_CBB
+	device_t pci_domain;
+#endif
+	int i,j;
+	int coreid_bits;
+	int core_max = 0;
+	unsigned ApicIdCoreIdSize;
+	unsigned core_nums;
+	int siblings = 0;
+	unsigned int family;
+
+#if CONFIG_CBB
+	dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00
+	if (dev_mc && dev_mc->bus) {
+		printk(BIOS_DEBUG, "%s found", dev_path(dev_mc));
+		pci_domain = dev_mc->bus->dev;
+		if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+			printk(BIOS_DEBUG, "\n%s move to ",dev_path(dev_mc));
+			dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+			printk(BIOS_DEBUG, "%s",dev_path(dev_mc));
+		} else {
+			printk(BIOS_DEBUG, " but it is not under pci_domain directly ");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	if (!dev_mc) {
+		dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+		if (dev_mc && dev_mc->bus) {
+			printk(BIOS_DEBUG, "%s found\n", dev_path(dev_mc));
+			pci_domain = dev_mc->bus->dev;
+			if (pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) {
+				if ((pci_domain->link_list) && (pci_domain->link_list->children == dev_mc)) {
+					printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+					dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff
+					printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+					while (dev_mc) {
+						printk(BIOS_DEBUG, "%s move to ",dev_path(dev_mc));
+						dev_mc->path.pci.devfn -= PCI_DEVFN(0x18,0);
+						printk(BIOS_DEBUG, "%s\n",dev_path(dev_mc));
+						dev_mc = dev_mc->sibling;
+					}
+				}
+			}
+		}
+	}
+#endif
+	dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));
+	if (!dev_mc) {
+		printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB);
+		die("");
+	}
+	sysconf_init(dev_mc);
+#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
+	if (node_nums>32) { // need to put node 32 to node 63 to bus 0xfe
+		if (pci_domain->link_list && !pci_domain->link_list->next) {
+			struct bus *new_link = new_link(pci_domain);
+			pci_domain->link_list->next = new_link;
+			new_link->link_num = 1;
+			new_link->dev = pci_domain;
+			new_link->children = 0;
+			printk(BIOS_DEBUG, "%s links now 2\n", dev_path(pci_domain));
+		}
+		pci_domain->link_list->next->secondary = CONFIG_CBB - 1;
+	}
+#endif
+
+	/* Get Max Number of cores(MNC) */
+	coreid_bits = (cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT) & 0x0000F000) >> 12;
+	core_max = 1 << (coreid_bits & 0x000F); //mnc
+
+	ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF);
+	if (ApicIdCoreIdSize) {
+		core_nums = (1 << ApicIdCoreIdSize) - 1;
+	} else {
+		core_nums = 3; //quad core
+	}
+
+	/* Find which cpus are present */
+	cpu_bus = dev->link_list;
+	for (i = 0; i < node_nums; i++) {
+		device_t cdb_dev, cpu;
+		struct device_path cpu_path;
+		unsigned busn, devn;
+		struct bus *pbus;
+
+		busn = CONFIG_CBB;
+		devn = CONFIG_CDB + i;
+		pbus = dev_mc->bus;
+#if CONFIG_CBB && (MAX_NODE_NUMS > 32)
+		if (i >= 32) {
+			busn--;
+			devn -= 32;
+			pbus = pci_domain->link_list->next;
+		}
+#endif
+
+		/* Find the cpu's pci device */
+		cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+		if (!cdb_dev) {
+			/* If I am probing things in a weird order
+			 * ensure all of the cpu's pci devices are found.
+			 */
+			int fn;
+			for(fn = 0; fn <= 5; fn++) { //FBDIMM?
+				cdb_dev = pci_probe_dev(NULL, pbus,
+							PCI_DEVFN(devn, fn));
+			}
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0));
+		} else {
+			/* Ok, We need to set the links for that device.
+			 * otherwise the device under it will not be scanned
+			 */
+			int linknum;
+#if CONFIG_HT3_SUPPORT==1
+			linknum = 8;
+#else
+			linknum = 4;
+#endif
+			add_more_links(cdb_dev, linknum);
+		}
+
+		family = cpuid_eax(1);
+		family = (family >> 20) & 0xFF;
+		if (family == 1) { //f10
+			u32 dword;
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3));
+			dword = pci_read_config32(cdb_dev, 0xe8);
+			siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12);
+		} else if (family == 6) {//f15
+			cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 5));
+			if (cdb_dev && cdb_dev->enabled) {
+				siblings = pci_read_config32(cdb_dev, 0x84);
+				siblings &= 0xFF;
+			}
+		} else {
+			siblings = 0; //default one core
+		}
+		printk(BIOS_SPEW, "%s family%xh, core_max=0x%x, core_nums=0x%x, siblings=0x%x\n",
+				dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings);
+
+		for (j = 0; j <= siblings; j++ ) {
+			extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
+			u32 modules = TopologyConfiguration.PlatformNumberOfModules;
+			u32 lapicid_start = 0;
+
+			/* Build the cpu device path */
+			cpu_path.type = DEVICE_PATH_APIC;
+			/*
+			 * APIC ID calucation is tightly coupled with AGESA v5 code.
+			 * This calculation MUST match the assignment calculation done
+			 * in LocalApicInitializationAtEarly() function.
+			 * And reference GetLocalApicIdForCore()
+			 *
+			 * Apply apic enumeration rules
+			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+			 * put the local-APICs at m..z
+			 *
+			 * This is needed because many IO-APIC devices only have 4 bits
+			 * for their APIC id and therefore must reside at 0..15
+                         */
+#ifndef CFG_PLAT_NUM_IO_APICS /* defined in mainboard buildOpts.c */
+#define CFG_PLAT_NUM_IO_APICS 3
+#endif
+			if ((node_nums * core_max) + CFG_PLAT_NUM_IO_APICS >= 0x10) {
+				lapicid_start = (CFG_PLAT_NUM_IO_APICS - 1) / core_max;
+				lapicid_start = (lapicid_start + 1) * core_max;
+				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
+			}
+			cpu_path.apic.apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
+			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
+					i, j, cpu_path.apic.apic_id);
+
+			/* See if I can find the cpu */
+			cpu = find_dev_path(cpu_bus, &cpu_path);
+			/* Enable the cpu if I have the processor */
+			if (cdb_dev && cdb_dev->enabled) {
+				if (!cpu) {
+					cpu = alloc_dev(cpu_bus, &cpu_path);
+				}
+				if (cpu) {
+					cpu->enabled = 1;
+				}
+			}
+			/* Disable the cpu if I don't have the processor */
+			if (cpu && (!cdb_dev || !cdb_dev->enabled)) {
+				cpu->enabled = 0;
+			}
+			/* Report what I have done */
+			if (cpu) {
+				cpu->path.apic.node_id = i;
+				cpu->path.apic.core_id = j;
+				if (cpu->path.type == DEVICE_PATH_APIC) {
+					cpu->ops = &lapic_ops;
+				}
+				printk(BIOS_DEBUG, "CPU: %s %s\n",
+					dev_path(cpu), cpu->enabled?"enabled":"disabled");
+			}
+		} //j
+	}
+	return max;
+}
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static void cpu_bus_read_resources(device_t dev)
+{
+#if CONFIG_MMCONF_SUPPORT
+	struct resource *resource = new_resource(dev, 0xc0010058);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		IORESOURCE_FIXED | IORESOURCE_STORED |  IORESOURCE_ASSIGNED;
+#endif
+}
+
+static void cpu_bus_set_resources(device_t dev)
+{
+	struct resource *resource = find_resource(dev, 0xc0010058);
+	if (resource) {
+		report_resource_stored(dev, resource, " <mmconfig>");
+	}
+	pci_dev_set_resources(dev);
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources	  = cpu_bus_read_resources,
+	.set_resources	  = cpu_bus_set_resources,
+	.enable_resources = cpu_bus_noop,
+	.init		  = cpu_bus_init,
+	.scan_bus	  = cpu_bus_scan,
+};
+
+
+static void root_complex_enable_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+
+struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = {
+	CHIP_NAME("AMD FAM15 Root Complex")
+	.enable_dev = root_complex_enable_dev,
+};
diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h
new file mode 100644
index 0000000..7606b32
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/northbridge.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM15_H
+#define NORTHBRIDGE_AMD_AGESA_FAM15_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */
diff --git a/src/northbridge/amd/agesa/family15/root_complex/Kconfig b/src/northbridge/amd/agesa/family15/root_complex/Kconfig
new file mode 100644
index 0000000..032b836
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/root_complex/Kconfig
@@ -0,0 +1,2 @@
+config NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+	bool
diff --git a/src/northbridge/amd/agesa/family15/root_complex/chip.h b/src/northbridge/amd/agesa/family15/root_complex/chip.h
new file mode 100644
index 0000000..06b3510
--- /dev/null
+++ b/src/northbridge/amd/agesa/family15/root_complex/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_amd_agesa_family15_root_complex_config
+{
+};
+
+extern struct chip_operations northbridge_amd_agesa_family15_root_complex_ops;


From gerrit at coreboot.org  Fri Jan 20 06:44:41 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:41 +0100
Subject: [coreboot] New patch to review for coreboot: 44a54d6 RD890
	Northbridge: AMD RD890/SR56X0 Northbridge CIMX code
References: <If9908ffeb5b707a660db38dc44f5118347cbcc06+0@gerrit.coreboot.org>
Message-ID: <If9908ffeb5b707a660db38dc44f5118347cbcc06+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/557

-gerrit

commit 44a54d614258e1954ee91bdfc759d362b03f031f
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:58:44 2012 +0800

    RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code
    
    Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/cimx/Makefile.inc               |    1 +
 src/vendorcode/amd/cimx/rd890/HotplugFirmware.h    | 1397 ++++++++++++++++
 src/vendorcode/amd/cimx/rd890/Makefile.inc         |  118 ++
 src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c        |  236 +++
 src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.h        |   77 +
 src/vendorcode/amd/cimx/rd890/amdAcpiLib.c         |  186 +++
 src/vendorcode/amd/cimx/rd890/amdAcpiLib.h         |  136 ++
 src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c        |  148 ++
 src/vendorcode/amd/cimx/rd890/amdAcpiMadt.h        |   66 +
 src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c     |  436 +++++
 src/vendorcode/amd/cimx/rd890/amdDebugOutLib.h     |   54 +
 src/vendorcode/amd/cimx/rd890/amdSbLib.c           |  216 +++
 src/vendorcode/amd/cimx/rd890/amdSbLib.h           |   85 +
 src/vendorcode/amd/cimx/rd890/nbDef.h              |  532 ++++++
 src/vendorcode/amd/cimx/rd890/nbDispatcher.c       |  201 +++
 src/vendorcode/amd/cimx/rd890/nbEventLog.c         |  106 ++
 src/vendorcode/amd/cimx/rd890/nbEventLog.h         |   95 ++
 src/vendorcode/amd/cimx/rd890/nbHtInit.c           |  626 +++++++
 src/vendorcode/amd/cimx/rd890/nbHtInit.h           |  126 ++
 src/vendorcode/amd/cimx/rd890/nbHtInterface.c      |  125 ++
 src/vendorcode/amd/cimx/rd890/nbInit.c             |  417 +++++
 src/vendorcode/amd/cimx/rd890/nbInit.h             |  107 ++
 src/vendorcode/amd/cimx/rd890/nbInitializer.c      |  133 ++
 src/vendorcode/amd/cimx/rd890/nbInitializer.h      |   57 +
 src/vendorcode/amd/cimx/rd890/nbInterface.c        |  312 ++++
 src/vendorcode/amd/cimx/rd890/nbIoApic.c           |  194 +++
 src/vendorcode/amd/cimx/rd890/nbIoApic.h           |   52 +
 src/vendorcode/amd/cimx/rd890/nbIommu.c            | 1737 ++++++++++++++++++++
 src/vendorcode/amd/cimx/rd890/nbIommu.h            |  326 ++++
 src/vendorcode/amd/cimx/rd890/nbLib.c              | 1138 +++++++++++++
 src/vendorcode/amd/cimx/rd890/nbLib.h              |  352 ++++
 src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c |  121 ++
 src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.h |   63 +
 .../amd/cimx/rd890/nbMaskedMemoryInit32.S          |  117 ++
 src/vendorcode/amd/cimx/rd890/nbMiscInit.c         |  123 ++
 src/vendorcode/amd/cimx/rd890/nbMiscInit.h         |   57 +
 src/vendorcode/amd/cimx/rd890/nbModuleInfo.c       |   70 +
 src/vendorcode/amd/cimx/rd890/nbPcie.h             |  352 ++++
 src/vendorcode/amd/cimx/rd890/nbPcieAspm.c         |  507 ++++++
 src/vendorcode/amd/cimx/rd890/nbPcieAspm.h         |  131 ++
 src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c   |  105 ++
 src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.h   |   52 +
 src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c   |  475 ++++++
 src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c      |  343 ++++
 src/vendorcode/amd/cimx/rd890/nbPcieHotplug.h      |   62 +
 src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c    |  720 ++++++++
 src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c     |  505 ++++++
 src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c    |  486 ++++++
 src/vendorcode/amd/cimx/rd890/nbPcieLib.c          | 1604 ++++++++++++++++++
 src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c    |  160 ++
 src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.h    |   60 +
 src/vendorcode/amd/cimx/rd890/nbPciePllControl.c   |  193 +++
 src/vendorcode/amd/cimx/rd890/nbPciePllControl.h   |   63 +
 src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c    |  182 ++
 src/vendorcode/amd/cimx/rd890/nbPciePortRemap.h    |   52 +
 src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c     |  753 +++++++++
 src/vendorcode/amd/cimx/rd890/nbPcieSb.c           |  195 +++
 src/vendorcode/amd/cimx/rd890/nbPcieSb.h           |   71 +
 src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c  |  436 +++++
 src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.h  |   65 +
 src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c     |  383 +++++
 src/vendorcode/amd/cimx/rd890/nbRecovery.c         |  192 +++
 src/vendorcode/amd/cimx/rd890/nbRecovery.h         |   53 +
 .../amd/cimx/rd890/nbRecoveryInitializer.c         |   98 ++
 src/vendorcode/amd/cimx/rd890/nbRegisters.h        |  420 +++++
 src/vendorcode/amd/cimx/rd890/nbType.h             | 1075 ++++++++++++
 66 files changed, 20136 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc
index bb9b78c..3622312 100644
--- a/src/vendorcode/amd/cimx/Makefile.inc
+++ b/src/vendorcode/amd/cimx/Makefile.inc
@@ -1,2 +1,3 @@
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
diff --git a/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h b/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h
new file mode 100644
index 0000000..a0b416f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/HotplugFirmware.h
@@ -0,0 +1,1397 @@
+/**
+ * @file
+ *
+ * SMU firmware.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  GNB
+ * @e \$Revision: 18962 \$   @e \$Date: 2009-09-07 20:35:39 -0700 (Mon, 07 Sep 2009) \$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef  _HOTPLUGFIRMWARE_H_
+#define  _HOTPLUGFIRMWARE_H_
+
+UINT32 DataBlock0[] = {
+  0xbdff018e,
+  0x16ceee15,
+  0x1cce1807,
+  0xa6082000,
+  0x00a71800,
+  0x8c081808,
+  0xf3256716,
+  0x270000cc,
+  0x601cce0b,
+  0x8308006f,
+  0xf8260100,
+  0x16bd098d,
+  0x02fb2003,
+  0xde1c0206,
+  0x9f343c06,
+  0xbd0fc606,
+  0x06de0004,
+  0xfece016f,
+  0xe702c668,
+  0x69fece00,
+  0x1806de18,
+  0x00e701e6,
+  0xe764fece,
+  0x18c4c600,
+  0x1865fece,
+  0xffc600e7,
+  0x66fece18,
+  0xce00e718,
+  0x00e767fe,
+  0x1806de18,
+  0x1cf701e6,
+  0xf704c600,
+  0x06bd041c,
+  0x06de18e0,
+  0xf701e618,
+  0xfece001c,
+  0xf600e764,
+  0xce18011c,
+  0xe71865fe,
+  0x021cf600,
+  0xe766fece,
+  0x031cf600,
+  0x67fece18,
+  0xf600e718,
+  0xffce4b1c,
+  0xf600e78e,
+  0xffce4a1c,
+  0xbd00e78d,
+  0x00cc2b06,
+  0x7efece01,
+  0x07bd00ed,
+  0x0200ce2b,
+  0x7efece18,
+  0xbd00efcd,
+  0x00ce8407,
+  0xfece1803,
+  0x00efcd7e,
+  0xe674fece,
+  0x2601c100,
+  0x06de181a,
+  0x3701e618,
+  0x081ccc34,
+  0x31480fbd,
+  0x6c06de31,
+  0xc101e601,
+  0xcee62307,
+  0xce180400,
+  0xefcd7efe,
+  0x4b1cf600,
+  0x1cf702ca,
+  0x8effce4b,
+  0xfece00e7,
+  0x2600e675,
+  0x0812bd03,
+  0xfd8009bd,
+  0x1c2a101c,
+  0x180500ce,
+  0xcd7efece,
+  0x01c600ef,
+  0xce540bbd,
+  0xce180600,
+  0xefcd7efe,
+  0xfe200e00,
+  0x0cbd01c6,
+  0xbd01c690,
+  0x00ce9a10,
+  0xfece1807,
+  0x00efcd7e,
+  0x540bbd5f,
+  0x180800ce,
+  0xcd7efece,
+  0xffce00ef,
+  0xe701c68f,
+  0x00ce0e00,
+  0x00efcd09,
+  0x274e1cf6,
+  0x1cf75f29,
+  0x0a00ce4e,
+  0x7efece18,
+  0xc600efcd,
+  0x900cbd01,
+  0x10bd00c6,
+  0x0b00ce9a,
+  0x7efece18,
+  0xce00efcd,
+  0x01c68fff,
+  0xffce00e7,
+  0xf700e687,
+  0x01c54d1c,
+  0x00ce1a27,
+  0xfece180c,
+  0x00efcd7e,
+  0xbd5f1ccc,
+  0x00cefa0a,
+  0xfece180d,
+  0x00efcd7e,
+  0xe675fece,
+  0x18a52600,
+  0x1823f0ce,
+  0x80c400e6,
+  0x00cc9a27,
+  0x7efece10,
+  0x11bd00ed,
+  0xf0ce181c,
+  0x001c1823,
+  0x1100cc80,
+  0xed7efece,
+  0x7c037e00,
+  0x9f3c06de,
+  0x3c08de06,
+  0xd73c0ade,
+  0x3d10ce0b,
+  0xf0c400e6,
+  0x0bd68f18,
+  0x00dd8f18,
+  0x01da8f18,
+  0xdf3800e7,
+  0x08df380a,
+  0x3906df38,
+  0x3c3c06de,
+  0x08de069f,
+  0x3c0ade3c,
+  0x0bee06de,
+  0x1cf70adf,
+  0x06de1800,
+  0x1809ee18,
+  0x1cf700e6,
+  0xf718c607,
+  0xde18061c,
+  0x08e61806,
+  0x7f041cf7,
+  0x007f0900,
+  0xe006bd08,
+  0xfdbe05bd,
+  0x152a101c,
+  0x1cf709d6,
+  0x7f032006,
+  0x06bd061c,
+  0xfa05bde0,
+  0x20101cfc,
+  0x08de1877,
+  0x240a9c18,
+  0x1a06de54,
+  0x081809ee,
+  0xbd01ef1a,
+  0x1cfd0e06,
+  0xdcd82b10,
+  0xffffc30a,
+  0x2708931a,
+  0xf708c638,
+  0x06bd061c,
+  0x06de18e0,
+  0x1801ee18,
+  0x1cf700e6,
+  0xf718c607,
+  0xde18061c,
+  0x08e61806,
+  0xbd041cf7,
+  0x06dee006,
+  0x1801ee1a,
+  0x01ef1a08,
+  0xdf0808de,
+  0x250a9c08,
+  0x1cf75fb6,
+  0xe006bd06,
+  0x1cf712c6,
+  0xe006bd06,
+  0x5ffa05bd,
+  0xbd061cf7,
+  0x5f4fe006,
+  0x380adf38,
+  0x383808df,
+  0xde3906df,
+  0x069f3c06,
+  0xde3c08de,
+  0x0cde3c0a,
+  0xee06de3c,
+  0x180cdf07,
+  0xee1806de,
+  0x0adf1809,
+  0x7f09007f,
+  0x1cf70800,
+  0xf714c600,
+  0xde18061c,
+  0x06e61806,
+  0xbd041cf7,
+  0x05bde006,
+  0x101cfdbe,
+  0x09d6102a,
+  0xbd061cf7,
+  0x05bde006,
+  0x101cfcfa,
+  0xde185f20,
+  0x0a9c1808,
+  0x05bd3d24,
+  0x0cde18e5,
+  0x00df08de,
+  0x00d38f18,
+  0x1cf68f18,
+  0x00e71804,
+  0xffc30adc,
+  0x08931aff,
+  0x04c61d27,
+  0xbd061cf7,
+  0x14c6e006,
+  0xbd061cf7,
+  0xde18e006,
+  0x18081808,
+  0x9c1808df,
+  0x5fc3250a,
+  0xbd061cf7,
+  0x12c6e006,
+  0xbd061cf7,
+  0x528de006,
+  0x061cf75f,
+  0x4fe006bd,
+  0x0cdf385f,
+  0x380adf38,
+  0xdf3808df,
+  0x06de3906,
+  0xbd069f3c,
+  0x1cf67306,
+  0x2702c505,
+  0x205f4f04,
+  0x2708c510,
+  0xffffcc05,
+  0x04c50720,
+  0xffcce527,
+  0x06df38fe,
+  0x3c06de39,
+  0x06bd069f,
+  0x051cf673,
+  0xf62701c4,
+  0xdf385f4f,
+  0x06de3906,
+  0x8d069f3c,
+  0x051cf672,
+  0xf72740c4,
+  0xdf385f4f,
+  0x06de3906,
+  0x8d069f3c,
+  0x061cf65e,
+  0xf72701c5,
+  0x042602c5,
+  0x03205f4f,
+  0x38faffcc,
+  0xde3906df,
+  0x069f3c06,
+  0x001cf75f,
+  0xf7041c7f,
+  0x01c6051c,
+  0x5f061cf7,
+  0xbd071cf7,
+  0x0e8de006,
+  0x5f101cfd,
+  0xbd061cf7,
+  0xdf38e006,
+  0x06de3906,
+  0x8d069f3c,
+  0x051cf616,
+  0x042720c5,
+  0x07205f4f,
+  0xef2710c5,
+  0x38fdffcc,
+  0xde3906df,
+  0x9f3c3c06,
+  0x67fece06,
+  0xfece00e6,
+  0xc400e660,
+  0x831a4f03,
+  0x08270100,
+  0x0200831a,
+  0xe5201a27,
+  0xe668fece,
+  0x041cf700,
+  0xe669fece,
+  0x06de1800,
+  0xce01e718,
+  0x16206afe,
+  0xe66cfece,
+  0x041cf700,
+  0xe66dfece,
+  0x06de1800,
+  0xce01e718,
+  0x00e66efe,
+  0xe602e718,
+  0x071cf700,
+  0x1806de18,
+  0x1cf702e6,
+  0x01e61806,
+  0x38051cf7,
+  0x3906df38,
+  0x9f3c06de,
+  0x001cf606,
+  0xe764fece,
+  0x071cf600,
+  0xe763fece,
+  0x061cf600,
+  0xe762fece,
+  0x051cf600,
+  0xe761fece,
+  0x60fece00,
+  0xe7041cf6,
+  0xc400e600,
+  0xce0b2704,
+  0x00e660fe,
+  0xf72604c4,
+  0xfece0920,
+  0xc400e660,
+  0x38f72704,
+  0xde3906df,
+  0x3c3c3c06,
+  0x06de069f,
+  0x0ec6026f,
+  0x1806de18,
+  0x183d02a6,
+  0x1cc303ed,
+  0x0100ce12,
+  0x1808183c,
+  0x0000ce3c,
+  0x188f183c,
+  0x05bd00e6,
+  0x38383803,
+  0x112600dd,
+  0xee1a06de,
+  0xc38f1803,
+  0x8f181b1c,
+  0xe71801c6,
+  0x06de1800,
+  0x18026c18,
+  0x03c102e6,
+  0x3838b823,
+  0x3906df38,
+  0x3c3c06de,
+  0x069f343c,
+  0x016f06de,
+  0xde180ec6,
+  0x01a61806,
+  0x02ed183d,
+  0x181b1cc3,
+  0x00e6188f,
+  0x712601c1,
+  0x1806de18,
+  0x1cc302ec,
+  0x04ed1812,
+  0x3c0200ce,
+  0xc302ec18,
+  0x3637171c,
+  0x0400ce18,
+  0x06de3c18,
+  0x00e604ee,
+  0xfd2c04bd,
+  0x3838101c,
+  0xce422b38,
+  0x183c0200,
+  0xec1806de,
+  0x131cc302,
+  0xcd3c3637,
+  0x00e604ee,
+  0xfd2c04bd,
+  0x3838101c,
+  0xce222b38,
+  0x183c0200,
+  0xec1806de,
+  0x191cc302,
+  0x00ce3637,
+  0xee183c06,
+  0x00e61804,
+  0xfd2c04bd,
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+  0x07eecd05,
+  0x05eecd3c,
+  0x8400cc3c,
+  0xfecc3637,
+  0xc6363700,
+  0xf814bdfd,
+  0x1806de18,
+  0x0add03ec,
+  0xdd01ec18,
+  0xde0adc08,
+  0xfdc48f08,
+  0x1808df8f,
+  0x08dc03ed,
+  0xcd01ed18,
+  0xcd3c03ee,
+  0xcc3c01ee,
+  0x36374c00,
+  0x3700fecc,
+  0xbdfdc636,
+  0xde18f814,
+  0x03ec1806,
+  0xec180add,
+  0xdc08dd01,
+  0x18078a0a,
+  0x08dc03ed,
+  0xcd01ed18,
+  0xcd3c03ee,
+  0xcc3c01ee,
+  0x36374c00,
+  0x3700fecc,
+  0xbdfdc636,
+  0x8f30f814,
+  0x8f1800c3,
+  0x6000cc35,
+  0xfecc3637,
+  0xc6363700,
+  0x5715bdfd,
+  0xff5d1cfd,
+  0x00cc5b1c,
+  0x4f36378c,
+  0xcc36375f,
+  0x36376000,
+  0x3700fecc,
+  0xbdfdc636,
+  0x00ccf814,
+  0xcc363764,
+  0x363700fe,
+  0x15bdfdc6,
+  0x591cfd57,
+  0xfe571cff,
+  0xfe3c5d1c,
+  0xcc3c5b1c,
+  0x36376000,
+  0x3700fecc,
+  0xbdfdc636,
+  0xffcef814,
+  0x01001d8d,
+  0x1c24f0ce,
+  0xf0ce0300,
+  0xfd00ec0e,
+  0xfe18551c,
+  0xfece551c,
+  0xdd00ec70,
+  0xd38f1800,
+  0xce8f1800,
+  0xef1a16f0,
+  0x23f0ce00,
+  0x3080001c,
+  0x1800c38f,
+  0xdf38358f,
+  0x08df380a,
+  0x38383838,
+  0x3906df38,
+  0x8a8cffb6,
+  0x267f817f,
+  0x038639f7,
+  0x398cffb7,
+  0xffb70186,
+  0xa618398c,
+  0x81048403,
+  0x86042704,
+  0x8604200f,
+  0xa70020f0,
+  0xce183905,
+  0xe6180038,
+  0x80ffce08,
+  0xec1804e7,
+  0xe703a700,
+  0x02ec1802,
+  0xf8c401a7,
+  0x00e702ca,
+  0x02cccc8d,
+  0xe706a700,
+  0x06ec1807,
+  0x08e709a7,
+  0xa704ec18,
+  0x860ae70b,
+  0x0ba71802,
+  0x988da48d,
+  0x38ce1839,
+  0x08e61800,
+  0xe780ffce,
+  0x00ec1804,
+  0x02e703a7,
+  0xa702ec18,
+  0xcaf8c401,
+  0x8d00e704,
+  0x0002cc8d,
+  0x07e706a7,
+  0xa7180486,
+  0x6c14bd0b,
+  0x395c14bd,
+  0x343c06de,
+  0x08de069f,
+  0x3c0ade3c,
+  0xde3c0cde,
+  0x06de3c0e,
+  0xde1801e7,
+  0x08ec1806,
+  0xec180add,
+  0x1808dd06,
+  0x0edd0cec,
+  0xdd0aec18,
+  0x0838ce0c,
+  0xe701e618,
+  0x0038ce00,
+  0x02ed0adc,
+  0x00ed08dc,
+  0xdc0438ce,
+  0xdc02ed0e,
+  0xbd00ed0c,
+  0xdf388614,
+  0x0cdf380e,
+  0x380adf38,
+  0x383108df,
+  0xde3906df,
+  0x9f343c06,
+  0x3c08de06,
+  0xde3c0ade,
+  0x0ede3c0c,
+  0xe706de3c,
+  0x06de1801,
+  0xdd08ec18,
+  0x06ec180a,
+  0x38ce08dd,
+  0x01e61808,
+  0x38ce00e7,
+  0xed0adc00,
+  0xed08dc02,
+  0xc514bd00,
+  0xdd83ffcc,
+  0xde0edc02,
+  0x00ce180c,
+  0x183c8d08,
+  0xde1804df,
+  0x00ea1802,
+  0x0cdf0edd,
+  0xdf180918,
+  0x1800de00,
+  0xde1802df,
+  0x7fff8c04,
+  0x0cded722,
+  0xdf183818,
+  0x1838180e,
+  0x38180cdf,
+  0x180adf18,
+  0x08df1838,
+  0x18381831,
+  0x183906df,
+  0x1fc44f8f,
+  0x09278f18,
+  0x49598f05,
+  0x2609188f,
+  0x064f39f7,
+  0x10008c39,
+  0x008c0a2c,
+  0x05042700,
+  0x39fc2609,
+  0x0e395f4f,
+  0x00fc203e,
+  0x00ffffc0,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00007400,
+  0x07070000,
+  0x00010f0f,
+  0x75000000,
+  0x00000000,
+  0x0f0f0707,
+  0x00000000,
+  0x00007600,
+  0x07070000,
+  0x00000f0f,
+  0x77000000,
+  0x00000000,
+  0x0f0f0707,
+  0x00000000,
+  0x00000000,
+  0x01000100,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000
+};
+
+UINT32 DataBlock1[] = {
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41094109,
+  0x41095c09,
+  0x41094109,
+  0xfb084109,
+  0x41092009,
+  0x00020002,
+  0x00020002
+};
+
+SMU_FIRMWARE_BLOCK FmBlockArray[] = {
+  {
+    0x200,
+    0x51a,
+    &DataBlock0[0]
+  },
+  {
+    0xffc0,
+    0x10,
+    &DataBlock1[0]
+  }
+};
+
+SMU_FIRMWARE_HEADER Fm = {
+  {
+    0x0, 0x0
+  },
+  2,
+  &FmBlockArray[0]
+};
+#endif
+
diff --git a/src/vendorcode/amd/cimx/rd890/Makefile.inc b/src/vendorcode/amd/cimx/rd890/Makefile.inc
new file mode 100644
index 0000000..8a05570
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/Makefile.inc
@@ -0,0 +1,118 @@
+#*****************************************************************************
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+#       its contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#*****************************************************************************
+
+# CIMX Root directory
+CIMX_ROOT = $(src)/vendorcode/amd/cimx
+
+NB_CIMX_INC  = -I$(src)/mainboard/$(MAINBOARDDIR)
+NB_CIMX_INC  += -I$(src)/northbridge/amd/cimx/rd890
+NB_CIMX_INC  += -I$(CIMX_ROOT)/rd890
+
+romstage-y += amdAcpiIvrs.c
+romstage-y += amdAcpiLib.c
+romstage-y += amdAcpiMadt.c
+romstage-y += amdDebugOutLib.c
+romstage-y += amdSbLib.c
+#romstage-y += nbDispatcher.c
+romstage-y += nbEventLog.c
+romstage-y += nbHtInit.c
+romstage-y += nbHtInterface.c
+romstage-y += nbInit.c
+romstage-y += nbInitializer.c
+romstage-y += nbInterface.c
+romstage-y += nbIoApic.c
+romstage-y += nbIommu.c
+romstage-y += nbLib.c
+romstage-y += nbMaskedMemoryInit.c
+romstage-y += nbMiscInit.c
+romstage-y += nbModuleInfo.c
+romstage-y += nbPcieAspm.c
+romstage-y += nbPcieCplBuffers.c
+romstage-y += nbPcieEarlyHwLib.c
+romstage-y += nbPcieHotplug.c
+romstage-y += nbPcieInitEarly.c
+romstage-y += nbPcieInitLate.c
+romstage-y += nbPcieLateHwLib.c
+romstage-y += nbPcieLib.c
+romstage-y += nbPcieLinkWidth.c
+romstage-y += nbPciePllControl.c
+romstage-y += nbPciePortRemap.c
+#romstage-y += nbPcieRecovery.c
+romstage-y += nbPcieSb.c
+romstage-y += nbPcieWorkarounds.c
+romstage-y += nbPowerOnReset.c
+#romstage-y += nbRecovery.c
+#romstage-y += nbRecoveryInitializer.c
+romstage-y += nbMaskedMemoryInit32.S
+
+ramstage-y += amdAcpiIvrs.c
+ramstage-y += amdAcpiLib.c
+ramstage-y += amdAcpiMadt.c
+ramstage-y += amdDebugOutLib.c
+ramstage-y += amdSbLib.c
+#ramstage-y += nbDispatcher.c
+ramstage-y += nbEventLog.c
+ramstage-y += nbHtInit.c
+ramstage-y += nbHtInterface.c
+ramstage-y += nbInit.c
+ramstage-y += nbInitializer.c
+ramstage-y += nbInterface.c
+ramstage-y += nbIoApic.c
+ramstage-y += nbIommu.c
+ramstage-y += nbLib.c
+ramstage-y += nbMaskedMemoryInit.c
+ramstage-y += nbMiscInit.c
+ramstage-y += nbModuleInfo.c
+ramstage-y += nbPcieAspm.c
+ramstage-y += nbPcieCplBuffers.c
+ramstage-y += nbPcieEarlyHwLib.c
+ramstage-y += nbPcieHotplug.c
+ramstage-y += nbPcieInitEarly.c
+ramstage-y += nbPcieInitLate.c
+ramstage-y += nbPcieLateHwLib.c
+ramstage-y += nbPcieLib.c
+ramstage-y += nbPcieLinkWidth.c
+ramstage-y += nbPciePllControl.c
+ramstage-y += nbPciePortRemap.c
+#ramstage-y += nbPcieRecovery.c
+ramstage-y += nbPcieSb.c
+ramstage-y += nbPcieWorkarounds.c
+ramstage-y += nbPowerOnReset.c
+#ramstage-y += nbRecovery.c
+#ramstage-y += nbRecoveryInitializer.c
+ramstage-y += nbMaskedMemoryInit32.S
+
+NB_CIMX_CFLAGS =
+export CIMX_ROOT
+export NB_CIMX_INC
+export NB_CIMX_CFLAGS
+CC := $(CC) $(NB_CIMX_CFLAGS) $(NB_CIMX_INC)
+
+#######################################################################
+
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c
new file mode 100644
index 0000000..c710bf0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.c
@@ -0,0 +1,236 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdAcpiLib.h"
+#include "amdAcpiIvrs.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get first block entry in an IVRS (IOMMU) table
+ *
+ *
+ *
+ * @param[in] IoVirtualizationEntryType   Type of IVHD or IVMD entry (IVHD = 0x10, IVMD = 0x20-0x22, any = 0xFF))
+ * @param[in] Pointer to IVRS ACPI table
+ *
+ */
+VOID*
+LibAmdGetFirstIvrsBlockEntry (
+  IN       UINT8  IoVirtualizationEntryType,
+  IN       VOID   *IvrsPtr
+  )
+{
+  // Start at IVRS pointer + 48 (48 is always the size of IVRS header)
+  UINT8* BlockPtr;
+  // If our pointer is not to an IVRS, return error
+
+//  if (((DESCRIPTION_HEADER*)IvrsPtr)->Signature != 'SRVI') return NULL;
+  if (((DESCRIPTION_HEADER*)IvrsPtr)->Signature != Int32FromChar ('S', 'R', 'V', 'I')) return NULL;
+  BlockPtr = (UINT8*)IvrsPtr + 48;
+  // Search each entry incrementing by it's size field in offset 2 until
+  // we reach the end of the IVRS
+  do {
+    if (*BlockPtr == IoVirtualizationEntryType) {
+      return BlockPtr;
+    }
+    BlockPtr += *((UINT16*) (BlockPtr + 2));
+  } while (BlockPtr < (UINT8*)IvrsPtr + ((DESCRIPTION_HEADER*)IvrsPtr)->Length);
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get next block entry in an IVRS (IOMMU) table
+ *
+ *
+ *
+ * @param[in] IoVirtualizationEntryType   Type of IVHD or IVMD entry (IVHD = 0x10, IVMD = 0x20-0x22, any = 0xFF))
+ * @param[in] CurrentStructurePtr         Pointer to current IVHD or IVMD block in IVRS
+ * @param[in] IvrsPtr                     Pointer to IVRS table
+ *
+ */
+
+VOID*
+LibAmdGetNextIvrsBlockEntry (
+  IN       UINT8 IoVirtualizationEntryType,
+  IN       VOID* CurrentStructurePtr,
+  IN       VOID* IvrsPtr
+  )
+{
+  // Start at the current device entry
+  // Start searching after the current entry
+  UINT8* BlockPtr;
+  // If our pointer is not to an IVRS, return error
+//  if (((DESCRIPTION_HEADER*)IvrsPtr)->Signature != 'SRVI') return NULL;
+  if (((DESCRIPTION_HEADER*)IvrsPtr)->Signature != Int32FromChar ('S', 'R', 'V', 'I')) return NULL;
+
+  BlockPtr = (UINT8*)CurrentStructurePtr + *((UINT16*) ((UINT8*)CurrentStructurePtr + 2));
+
+  // Search each entry incrementing by it's size field in offset 2 until
+  // we reach the end of the IVRS
+  while (BlockPtr < ((UINT8*)IvrsPtr + ((DESCRIPTION_HEADER*)IvrsPtr)->Length)) {
+    if (*BlockPtr == IoVirtualizationEntryType) {
+      return BlockPtr;
+    }
+    BlockPtr += *((UINT16*) (BlockPtr + 2));
+  }
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get pointer to first Device Entry of an IVHD
+ *
+ *
+ *
+ * @param[in] IoVirtualizationEntryType   Type of IVHD device entry to search for. (0xFF returns next entry of any type)
+ *                                        Typical values: 4 byte entries (0-63), 8 byte entries (64-127)
+ * @param[in] IvhdBlockPtr                Pointer to current IVHD block
+ *
+ */
+VOID*
+LibAmdGetFirstDeviceEntry (
+  IN       UINT8 DeviceEntryType,
+  IN       VOID* IvhdBlockPtr
+  )
+{
+  // Start at IVHD pointer + 24 (24 is always the size of IVHD header)
+  // Not much we can do do validate an IVHD input, the only field we know for sure is the type
+  UINT8   *EntryPtr;
+  UINT16  IvhdSize;
+  EntryPtr = (UINT8*)IvhdBlockPtr + 24;
+  IvhdSize = *(UINT16*) ((UINT8*)IvhdBlockPtr + 2);
+  // Search each entry incrementing by it's type field until the end of the IVHD
+  // Types 0-63 are 4 byte size, 64-127 are 8 byte size
+  do {
+    if (*EntryPtr == DeviceEntryType) {
+      return EntryPtr;
+    }
+    if (*EntryPtr < 64) {
+      EntryPtr += 4;
+    } else if ((*EntryPtr >= 64) && (*EntryPtr < 128)) {
+      EntryPtr += 8;
+    } else {
+      ASSERT (TRUE);
+      return NULL;
+    }
+  } while (EntryPtr < ((UINT8*)IvhdBlockPtr + IvhdSize));
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get pointer to Next Device Entry of an IVHD
+ *
+ *
+ *
+ *
+ * @param[in] IoVirtualizationEntryType   Type of IVHD entry. (0xFF returns next entry of any type)
+ *                                        Typical values: 4 byte entries (0-63), 8 byte entries (64-127)
+ * @param[in] CurrentStructurePtr         Pointer to current device entry in IVHD block
+ * @param[in] IvhdBlockPtr                Pointer to current IVHD block
+ */
+VOID*
+LibAmdGetNextDeviceEntry (
+  IN       UINT8 DeviceEntryType,
+  IN       VOID* CurrentDeviceEntry,
+  IN       VOID* IvhdBlockPtr
+  )
+{
+  UINT8   *EntryPtr;
+  UINT16  IvhdSize;
+  // Start at IVHD pointer + 24 (24 is always the size of IVHD header)
+  // Not much we can do do validate an IVHD input, the only field we know for sure is the type
+  EntryPtr = CurrentDeviceEntry;
+
+  if ((*EntryPtr != 0) && (*EntryPtr < 64)) {
+    EntryPtr += 4;
+  } else if ((*EntryPtr >= 64) && (*EntryPtr < 128)) {
+    EntryPtr += 8;
+  }
+  IvhdSize = *(UINT16*) ((UINT8*)IvhdBlockPtr + 2);
+  // Search each entry incrementing by it's type field until the end of the IVHD
+  // Types 0-63 are 4 byte size, 64-127 are 8 byte size
+  while (EntryPtr < ((UINT8*)IvhdBlockPtr + IvhdSize)) {
+    if (*EntryPtr == DeviceEntryType) {
+      return EntryPtr;
+    }
+    if (*EntryPtr < 64) {
+      EntryPtr += 4;
+    } else if ((*EntryPtr >= 64) && (*EntryPtr < 128)) {
+      EntryPtr += 8;
+    } else {
+      ASSERT (TRUE);
+      return NULL;
+    }
+  }
+  return NULL;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.h b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.h
new file mode 100644
index 0000000..4d62c17
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiIvrs.h
@@ -0,0 +1,77 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _AMDACPIIVRS_H_
+#define _AMDACPIIVRS_H_
+
+//#ifndef   ASSERT
+//#define   ASSERT
+//#endif
+
+
+VOID*
+LibAmdGetFirstIvrsBlockEntry (
+  IN  UINT8   IoVirtualizationEntryType,
+  IN  VOID*   IvrsPtr
+);
+
+VOID*
+LibAmdGetNextIvrsBlockEntry (
+  IN  UINT8   IoVirtualizationEntryType,
+  IN  VOID*   CurrentStructurePtr,
+  IN  VOID*   IvrsPtr
+);
+
+VOID*
+LibAmdGetFirstDeviceEntry (
+  IN  UINT8   DeviceEntryType,
+  IN  VOID*   IvhdBlockPtr
+);
+
+VOID*
+LibAmdGetNextDeviceEntry (
+  IN  UINT8   DeviceEntryType,
+  IN  VOID*   CurrentDeviceEntry,
+  IN  VOID*   IvhdBlockPtr
+);
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c
new file mode 100644
index 0000000..60b5ffe
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.c
@@ -0,0 +1,186 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdAcpiLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get ACPI table.
+ *
+ *
+ *
+ * @param[in] Signature  ACPI table signature
+ *
+ */
+
+AGESA_STATUS
+LibAmdGetAcpiTable (
+  IN      UINT32    Signature,
+  IN      VOID      **TablePtr,
+  IN      UINTN     *TableHandle
+  )
+{
+  UINT32  i;
+  UINT32* RsdPtr;
+  UINT32* Rsdt;
+  DESCRIPTION_HEADER* CurrentTable;
+
+  RsdPtr = (UINT32*) (UINTN)0xe0000;
+  Rsdt = NULL;
+
+  do {
+//    if (*RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP') {
+	if ((*RsdPtr == Int32FromChar (' ', 'D', 'S', 'R')) && (*(RsdPtr+1) == Int32FromChar (' ', 'R', 'T', 'P'))) {
+      Rsdt = (UINT32*) (UINTN) (((RSDP*)RsdPtr)->RsdtAddress);
+      break;
+    }
+    RsdPtr += 4;
+  } while (RsdPtr <= (UINT32*) ((UINTN)0xffff0));
+  if (Rsdt != NULL && LibAmdGetAcpiTableChecksum (Rsdt) == 0) {
+    for (i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++) {
+      CurrentTable = (DESCRIPTION_HEADER*) (UINTN)*(UINT32*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i*4);
+      if (CurrentTable->Signature == Signature) {
+        *TablePtr = CurrentTable;
+        return AGESA_SUCCESS;
+      }
+    }
+  }
+  return AGESA_UNSUPPORTED;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set ACPI table.
+ *
+ *
+ *
+ * @param[in] Signature  ACPI table signature
+ *
+ */
+
+AGESA_STATUS
+LibAmdSetAcpiTable (
+  IN      VOID      *TablePtr,
+  IN      BOOLEAN   Checksum,
+  IN      UINTN     *TableHandle
+  )
+{
+  if (Checksum) {
+    LibAmdUpdateAcpiTableChecksum (TablePtr);
+  }
+  return  AGESA_SUCCESS;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get ACPI table checksum
+ *
+ *
+ *
+ * @param[in] Pointer to ACPI table
+ *
+ */
+
+UINT8
+LibAmdGetAcpiTableChecksum (
+  IN       VOID     *TablePtr
+  )
+{
+  UINT32  i;
+  UINT8 Checksum;
+
+  Checksum = 0;
+
+  for (i = 0; i < ((DESCRIPTION_HEADER*)TablePtr)->Length; i++) {
+    Checksum = Checksum + *(UINT8*) ((UINT8*)TablePtr + i);
+  }
+  return Checksum;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Update ACPI table checksum
+ *
+ *
+ *
+ * @param[in] Pointer to ACPI table
+ *
+ */
+
+VOID
+LibAmdUpdateAcpiTableChecksum (
+  IN       VOID     *TablePtr
+  )
+{
+  UINT8 Checksum;
+  Checksum = 0;
+  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+  Checksum = LibAmdGetAcpiTableChecksum (TablePtr);
+  ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiLib.h b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.h
new file mode 100644
index 0000000..46ad04f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiLib.h
@@ -0,0 +1,136 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _AMDACPILIB_H_
+#define _AMDACPILIB_H_
+
+#ifndef   ASSERT
+  #define   ASSERT
+#endif
+
+#pragma pack(push, 1)
+
+///Header for RSDP table
+typedef struct _RSDP {
+  UINT64    Signature;                    ///< signature
+  UINT8     Checksum;                     ///< 8 bit checksum
+  UINT8     OEMID[6];                     ///< OEM identifier
+  UINT8     Revision;                     ///< revision
+  UINT32    RsdtAddress;                  ///< pointer to rsdt
+  UINT32    Length;                       ///< length of RSDP
+  UINT64    XsdtAddress;                  ///< pointer to xsdt
+  UINT8     ExtendedChecksum;             ///< checksum of xsdt
+  UINT8     Reserved[3];                  ///< reserved
+} RSDP;
+
+///Header for general ACPI table
+typedef struct _DESCRIPTION_HEADER {
+  UINT32    Signature;                    ///< signature
+  UINT32    Length;                       ///< length
+  UINT8     Revision;                     ///< revision
+  UINT8     Checksum;                     ///< 8 bit checksum
+  UINT8     OEMID[6];                     ///< OEM identifier
+  UINT8     OEMTableID[8];                ///< OEM table identifier
+  UINT32    OEMRevision;                  ///< OEM revision
+  UINT32    CreatorID;                    ///< table creator identifier
+  UINT32    CreatorRevision;              ///< table revision
+} DESCRIPTION_HEADER;
+
+///IO APIC struct in MADT table
+typedef struct  {
+  UINT8     Type;                         ///< type
+  UINT8     Length;                       ///< length
+  UINT8     ApicId;                       ///< Apic Id
+  UINT8     Reserved;                     ///< reserved
+  UINT32    IoApicBase;                   ///< IO APIC base address
+  UINT32    GlobalInterruptBase;          ///< Global Interrupt Base
+} MADT_IO_APIC_STRUCT;
+
+///Local APIC struct in MADT table
+typedef struct  {
+  UINT8     Type;                         ///< type
+  UINT8     Length;                       ///< length
+  UINT8     AcpiProcessorId;              ///< ACPI Processor ID
+  UINT8     ApicId;                       ///< Apic Id
+  UINT32    Flags;                        ///< Flags
+} MADT_LOCAL_APIC_STRUCT;
+
+///Local SAPIC struct in MADT table
+typedef struct  {
+  UINT8     Type;                         ///< type
+  UINT8     Length;                       ///< length
+  UINT8     ApicId;                       ///< Apic Id
+  UINT8     Reserved;                     ///< reserved
+  UINT32    GlobalInterruptBase;          ///< Global Interrupt Base
+  UINT64    IoApicBase;                   ///< IO SAPIC base address
+} MADT_IO_SAPIC_STRUCT;
+
+#pragma pack(pop)
+
+AGESA_STATUS
+LibAmdSetAcpiTable (
+  IN      VOID      *TablePtr,
+  IN      BOOLEAN   Checksum,
+  IN      UINTN     *TableHandle
+  );
+
+AGESA_STATUS
+LibAmdGetAcpiTable (
+  IN      UINT32  Signature,
+  IN      VOID    **TablePtr,
+  IN      UINTN   *TableHandle
+  );
+
+
+VOID
+LibAmdUpdateAcpiTableChecksum (
+  IN      VOID* TablePtr
+);
+
+UINT8
+LibAmdGetAcpiTableChecksum (
+  IN      VOID* TablePtr
+);
+
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c
new file mode 100644
index 0000000..daf2c1f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.c
@@ -0,0 +1,148 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdAcpiLib.h"
+#include "amdAcpiMadt.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get first block entry in an IVRS (IOMMU) table
+ *
+ *
+ *
+ * @param[in] StructureType         Type of structure entry to find (APIC = 1, 0xFF = next structure)
+ * @param[in] MadtPtr               Pointer to MADT ACPI table
+ *
+ */
+
+VOID*
+LibAmdGetFirstMadtStructure (
+  IN       UINT8  StructureType,
+  IN       VOID   *MadtPtr
+  )
+{
+  // Start at MADT pointer + 48 (48 is always the size of IVRS header)
+  UINT8* BlockPtr;
+
+  // If our pointer is not to an IVRS, return error
+//  if (((DESCRIPTION_HEADER*)MadtPtr)->Signature != 'CIPA') {
+  if (((DESCRIPTION_HEADER*)MadtPtr)->Signature != Int32FromChar ('C', 'I', 'P', 'A')) {
+    return NULL;
+  }
+  BlockPtr = (UINT8*)MadtPtr + 44;
+
+  // Search each entry incrementing by it's size field in offset 2 until
+  // we reach the end of the IVRS
+  do {
+    if (*BlockPtr == StructureType) {
+      return BlockPtr;
+    }
+    BlockPtr += *(BlockPtr + 1);
+  } while (BlockPtr < (UINT8*)MadtPtr + ((DESCRIPTION_HEADER*)MadtPtr)->Length);
+  return NULL;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get next block entry in an IVRS (IOMMU) table
+ *
+ *
+ *
+ * @param[in] StructureType         Type of structure entry to find (APIC = 1, ..., 0xFF = next structure)
+ * @param[in] CurrentStructurePtr   Pointer to current structure in IVRS
+ * @param[in] MadtPtr               Pointer to MADT ACPI table
+ *
+ */
+
+VOID*
+LibAmdGetNextMadtStructure (
+  IN       UINT8  StructureType,
+  IN       VOID   *CurrentStructurePtr,
+  IN       VOID   *MadtPtr
+  )
+{
+  UINT8 *BlockPtr;
+  BlockPtr = (UINT8*)CurrentStructurePtr + (*(UINT8*) ((UINT8*)CurrentStructurePtr + 1));
+
+  // If our pointer is not to an IVRS, return error
+//  if (((DESCRIPTION_HEADER*)MadtPtr)->Signature != 'CIPA') {
+  if (((DESCRIPTION_HEADER*)MadtPtr)->Signature != Int32FromChar ('C', 'I', 'P', 'A')) {
+    return NULL;
+  }
+
+  // Search each entry incrementing by it's size field in offset 2 until
+  // we reach the end of the IVRS
+  while (BlockPtr < ((UINT8*)MadtPtr + ((DESCRIPTION_HEADER*)MadtPtr)->Length)) {
+    if (*BlockPtr == StructureType) {
+      return BlockPtr;
+    }
+    BlockPtr += *(BlockPtr + 1);
+  }
+  return NULL;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.h b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.h
new file mode 100644
index 0000000..9f0aa73
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdAcpiMadt.h
@@ -0,0 +1,66 @@
+/**
+ * @file
+ *
+ * ACPI common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _AMDACPIMADT_H_
+#define _AMDACPIMADT_H_
+
+//#ifndef   ASSERT
+//#define   ASSERT
+//#endif
+
+
+
+VOID*
+LibAmdGetFirstMadtStructure (
+  IN  UINT8   StructureType,
+  IN  VOID*   MadtPtr
+);
+
+VOID*
+LibAmdGetNextMadtStructure (
+  IN  UINT8   StructureType,
+  IN  VOID*   CurrentStructurePtr,
+  IN  VOID*   MadtPtr
+);
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c
new file mode 100644
index 0000000..f40852b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.c
@@ -0,0 +1,436 @@
+/**
+ * @file
+ *
+ * Debug out functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "amdDebugOutLib.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define COM_BASE_ADDRESS  0x3f8
+#define DIVISOR           115200
+#define LF                0x0a
+#define CR                0x0d
+
+typedef CHAR8   *va_list;
+#ifndef _INTSIZEOF
+#define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
+#endif
+#ifndef va_start
+#define va_start(ap, v)  ( ap = (va_list)&(v) + _INTSIZEOF(v) )
+#endif
+#ifndef va_arg
+#define va_arg(ap, t)    ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#endif
+#ifndef  va_end
+#define va_end(ap)      ( ap = (va_list)0 )
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+  UINT8 Index;
+  CHAR8 Buffer[256];
+} StringBuffer;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+SendByteToBuffer (
+  IN  OUT  StringBuffer  *Buffer,
+  IN       CHAR8         Data
+  );
+
+VOID
+SendStringToBuffer (
+     OUT  StringBuffer  *Buffer,
+  IN      CHAR8         *pstr
+  );
+
+VOID
+SendBufferToDebugOut (
+  IN      CHAR8*  Buffer
+  );
+
+VOID
+ItoA (
+  IN      UINT32  Value,
+  IN      UINTN   Radix,
+     OUT  CHAR8   *pstr
+  );
+
+VOID
+SendBufferToHdtOut (
+  IN      CHAR8*  Buffer
+  );
+
+VOID
+SendBufferToSerialOut (
+  IN      CHAR8*  Buffer
+  );
+
+VOID
+InitDebugOut (VOID);
+
+VOID
+InitSerialOut (VOID);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Send format string to debug out
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+
+VOID
+LibAmdTraceDebug (
+  IN       UINT32 Level,
+  IN       CHAR8 *Format,
+  IN       ...
+  )
+{
+  CHAR8         TemBuffer[16];
+  UINT8         Index;
+  StringBuffer  Buffer;
+  va_list       ArgList;
+  if (Level == 0) {
+    return;
+  }
+  Buffer.Index = 0;
+  Index = 1;
+  va_start (ArgList, Format);
+  while (Index != 0) {
+    if (*Format == 0) break;
+    if (*Format == '%') {
+      INT32 Radix;
+      Radix = 0;
+      if (*(Format + 1) == 'd' || *(Format + 1) == 'D') {
+        Radix = 10;
+      }
+        if (*(Format + 1) == 'x' || *(Format + 1) == 'X' ) {
+        Radix = 16;
+      }
+      if (Radix != 0) {
+        ItoA (va_arg (ArgList, INT32), Radix, TemBuffer);
+        SendStringToBuffer (&Buffer, TemBuffer);
+        Format += 2;
+        continue;
+      }
+    }
+    SendByteToBuffer (&Buffer, *Format);
+    if (*(Format) == 0x0a) SendByteToBuffer (&Buffer, 0x0d);
+    Format++;
+  }
+  SendBufferToDebugOut (&Buffer.Buffer[0]);
+  va_end (ArgList);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write string to message buffer
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+
+VOID
+SendStringToBuffer (
+     OUT   StringBuffer  *Buffer,
+  IN       CHAR8         *pstr
+  )
+{
+  while (*pstr != 0) {
+    SendByteToBuffer (Buffer, *pstr);
+    pstr++;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write byte to message buffer
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+
+VOID
+SendByteToBuffer (
+  IN OUT   StringBuffer  *Buffer,
+  IN       CHAR8         Data
+  )
+{
+  if (Buffer->Index < 255) {
+    Buffer->Buffer[Buffer->Index] = Data;
+    Buffer->Buffer[++Buffer->Index] = 0;
+  } else {
+    SendBufferToDebugOut (Buffer->Buffer);
+    Buffer->Index = 0;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Integer To String
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+
+VOID
+ItoA (
+  IN       UINT32  Value,
+  IN       UINTN   Radix,
+     OUT   CHAR8   *pstr
+  )
+{
+  CHAR8 *tsptr;
+  CHAR8 *rsptr;
+  CHAR8  ch1;
+  CHAR8  ch2;
+  UINTN  Reminder;
+
+  tsptr = pstr;
+  rsptr = pstr;
+//Create String
+  do {
+    Reminder = Value % Radix;
+    Value = Value / Radix;
+    if (Reminder < 0xa) {
+      *tsptr = (UINT8)Reminder + '0';
+    } else {
+      *tsptr = (UINT8)Reminder - 0xa + 'a';
+    }
+    tsptr++;
+  } while (Value != 0);
+//Reverse String
+  *tsptr = 0;
+  tsptr--;
+  while (tsptr > rsptr) {
+    ch1 = *tsptr;
+    ch2 = *rsptr;
+    *rsptr = ch1;
+    *tsptr = ch2;
+    tsptr--;
+    rsptr++;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init debug Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+InitDebugOut (
+  VOID
+  )
+{
+#ifdef  SERIAL_OUT_SUPPORT
+  InitSerialOut ();
+#endif
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Serial Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+InitSerialOut (
+  VOID
+  )
+{
+  UINT8   Data;
+  UINT16  Divisor;
+
+  Data = 0x87;
+  LibAmdIoWrite (AccessWidth8, COM_BASE_ADDRESS + 0x3, &Data, NULL);
+  Divisor = 115200 / DIVISOR;
+  Data = (UINT8) (Divisor & 0xFF);
+  LibAmdIoWrite (AccessWidth8 , COM_BASE_ADDRESS + 0x00, &Data, NULL);
+  Data = (UINT8) (Divisor >> 8);
+  LibAmdIoWrite (AccessWidth8, COM_BASE_ADDRESS + 0x01, &Data, NULL);
+  Data = 0x07;
+  LibAmdIoWrite (AccessWidth8, COM_BASE_ADDRESS + 0x3, &Data, NULL);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init HDT Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Send Buffer to debug Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+SendBufferToDebugOut (
+  IN       CHAR8*  Buffer
+  )
+{
+#ifdef  HDT_OUT_SUPPORT
+  SendBufferToHdtOut (Buffer);
+#endif
+
+#ifdef  SERIAL_OUT_SUPPORT
+  SendBufferToSerialOut (Buffer);
+#endif
+}
+
+#ifdef  HDT_OUT_SUPPORT
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Send Buffer to debug Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+SendBufferToHdtOut (
+  IN       CHAR8*  Buffer
+  )
+{
+  UINT32 Dr0Reg;
+  UINT32 Dr7Reg;
+  UINT32 Cr4Reg;
+  UINT64 MsrCurrentValue;
+  UINT64 MsrNewValue;
+
+  // Save the CPU debug registers for restoration at the end of the routine
+  LibAmdMsrRead (0xC001100A, &MsrCurrentValue, NULL);
+  LibAmdReadCpuReg (DR0_REG, &Dr0Reg);
+  LibAmdReadCpuReg (DR7_REG, &Dr7Reg);
+  LibAmdReadCpuReg (CR4_REG, &Cr4Reg);
+
+  //Modify the registers for HDT out
+  LibAmdWriteCpuReg (DR0_REG, 0x8F0);
+  LibAmdWriteCpuReg (DR7_REG, 0x20402);
+  LibAmdWriteCpuReg (CR4_REG, Cr4Reg | 0x8);
+  MsrNewValue = MsrCurrentValue | BIT0;
+  LibAmdMsrWrite (0xC001100A, &MsrNewValue, NULL);
+
+  //HDT out
+  LibAmdIoWrite (AccessWidth32, 0x8F0, &Buffer, NULL);
+
+  // Restore the CPU debug registers
+  LibAmdWriteCpuReg (CR4_REG, Cr4Reg);
+  LibAmdWriteCpuReg (DR7_REG, Dr7Reg);
+  LibAmdWriteCpuReg (DR0_REG, Dr0Reg);
+  LibAmdMsrWrite (0xC001100A, &MsrCurrentValue, NULL);
+}
+#endif
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Send Buffer to debug Output
+ *
+ *
+ *
+ * @param[in] pConfig
+ *
+ */
+VOID
+SendBufferToSerialOut (
+  IN       CHAR8*  Buffer
+  )
+{
+  UINT8   Status;
+  UINT32  Count;
+
+  Count = 10000;
+  while (*Buffer != 0) {
+    do {
+      LibAmdIoRead (AccessWidth8, COM_BASE_ADDRESS + 0x05, &Status, NULL);
+      if (Status == 0xff) return;
+      // Loop  port is ready
+    } while ((Status & 0x20) == 0 && (--Count) != 0);
+    LibAmdIoWrite (AccessWidth8, COM_BASE_ADDRESS + 0x00, Buffer, NULL);
+    Buffer++;
+  }
+}
diff --git a/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.h b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.h
new file mode 100644
index 0000000..3458b80
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdDebugOutLib.h
@@ -0,0 +1,54 @@
+/**
+ * @file
+ *
+ * Debug out functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _AMDDEBUGOUTLIB_H_
+#define _AMDDEBUGOUTLIB_H_
+
+VOID
+LibAmdTraceDebug (
+  IN      UINT32 Level,
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/amdSbLib.c b/src/vendorcode/amd/cimx/rd890/amdSbLib.c
new file mode 100644
index 0000000..22b7fb1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdSbLib.c
@@ -0,0 +1,216 @@
+/**
+ * @file
+ *
+ * SB common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "amdSbLib.h"
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Stall
+ *
+ *
+ *
+ * @param[in] uSec
+ *
+ */
+
+VOID
+LibAmdSbStall (
+  IN      UINT32      uSec,
+  IN      VOID        *ConfigPtr
+  )
+{
+  UINT16  AcpiTimerBaseAddress;
+  UINT32  StartTime;
+  UINT32  ElapsedTime;
+  SB_INFO SbInfo;
+  SbInfo = LibAmdSbGetRevisionInfo (ConfigPtr);
+  if (SbInfo.Type == SB_UNKNOWN) {
+    AcpiTimerBaseAddress = 0;
+  } else {
+    LibAmdSbPmioRead ((SbInfo.Type == SB_SB700) ? 0x24 : 0x64, AccessWidth16, &AcpiTimerBaseAddress, ConfigPtr);
+  }
+  if (AcpiTimerBaseAddress == 0) {
+    uSec = uSec / 2;
+    while (uSec != 0) {
+      LibAmdIoRead (AccessWidth8, 0x80, &StartTime, (AMD_CONFIG_PARAMS *)ConfigPtr);
+      uSec--;
+    }
+  } else {
+    LibAmdIoRead (AccessWidth32, AcpiTimerBaseAddress, &StartTime, (AMD_CONFIG_PARAMS *)ConfigPtr);
+    do {
+      LibAmdIoRead (AccessWidth32, AcpiTimerBaseAddress, &ElapsedTime, (AMD_CONFIG_PARAMS *)ConfigPtr);
+      if (ElapsedTime < StartTime) {
+        ElapsedTime = ElapsedTime + (0xFFFFFFFF - StartTime);
+      } else {
+        ElapsedTime = ElapsedTime - StartTime;
+      }
+    } while ((ElapsedTime*28/100)<uSec); //28/100
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] uSec
+ *
+ */
+
+VOID
+LibAmdSbPmioRead (
+  IN       UINT8         Address,
+  IN       ACCESS_WIDTH  Width,
+     OUT   VOID          *Value,
+  IN       VOID          *ConfigPtr
+  )
+{
+  UINT8 i;
+  if (Width > 0x80) {
+    Width -= 0x80;
+  }
+  for (i = 0; i <= Width; i++) {
+    LibAmdIoWrite (AccessWidth8, 0xCD6, &Address, (AMD_CONFIG_PARAMS *)ConfigPtr);   // SB_IOMAP_REGCD6
+    Address++;
+    LibAmdIoRead (AccessWidth8,0xCD7, (UINT8 *)Value + i, (AMD_CONFIG_PARAMS *)ConfigPtr);     // SB_IOMAP_REGCD7
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] uSec
+ *
+ */
+
+VOID
+LibAmdSbPmioWrite (
+  IN       UINT8         Address,
+  IN       ACCESS_WIDTH  Width,
+  IN       VOID          *Value,
+  IN       VOID          *ConfigPtr
+  )
+{
+  UINT8 i;
+  if (Width > 0x80) {
+    Width -= 0x80;
+  }
+  for (i = 0; i <= Width; i++) {
+    LibAmdIoWrite (AccessWidth8, 0xCD6, &Address, (AMD_CONFIG_PARAMS *)ConfigPtr);    // SB_IOMAP_REGCD6
+    Address++;
+    LibAmdIoWrite (AccessWidth8,0xCD7, (UINT8 *)Value + i, (AMD_CONFIG_PARAMS *)ConfigPtr);     // SB_IOMAP_REGCD7
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SB Type
+ *
+ *
+ *
+ *
+ * @param[in] pConfig  Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+SB_INFO
+LibAmdSbGetRevisionInfo (
+  IN      VOID  *ConfigPtr
+  )
+{
+  UINT32    DeviceId;
+  UINT8     RevisionId;
+  SB_INFO   SbInfo;
+  PCI_ADDR  SbSmbusAddress;
+  SbSmbusAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0x00);
+  LibAmdPciRead (AccessWidth32, SbSmbusAddress, &DeviceId, (AMD_CONFIG_PARAMS *)ConfigPtr);
+  SbInfo.Revision = SB_REV_UNKNOWN;
+  switch (DeviceId) {
+  case 0x43851002:
+    SbSmbusAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0, 0x08);
+    LibAmdPciRead (AccessWidth8, SbSmbusAddress, &RevisionId, (AMD_CONFIG_PARAMS *)ConfigPtr);
+    if (RevisionId >= 0x40) {
+      SbInfo.Type = SB_SB800;
+    } else {
+      SbInfo.Type = SB_SB700;
+    }
+    break;
+  default:
+    SbInfo.Type = SB_UNKNOWN;
+  }
+  return SbInfo;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/amdSbLib.h b/src/vendorcode/amd/cimx/rd890/amdSbLib.h
new file mode 100644
index 0000000..b226dba
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/amdSbLib.h
@@ -0,0 +1,85 @@
+/**
+ * @file
+ *
+ * SB common library
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      Common Library
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _AMDSBLIB_H_
+#define _AMDSBLIB_H_
+
+VOID
+LibAmdSbStall (
+  IN      UINT32        uSec,
+  IN      VOID          *ConfigPtr
+  );
+
+VOID
+LibAmdSbPmioRead (
+  IN       UINT8         Address,
+  IN       ACCESS_WIDTH  Width,
+     OUT   VOID          *Value,
+  IN       VOID          *ConfigPtr
+  );
+
+VOID
+LibAmdSbPmioWrite (
+  IN      UINT8         Address,
+  IN      ACCESS_WIDTH  Width,
+  IN      VOID          *Value,
+  IN      VOID          *ConfigPtr
+  );
+
+#define SB_SB800        0x02
+#define SB_SB700        0x01
+#define SB_UNKNOWN      0xFF
+#define SB_REV_UNKNOWN  0xFF
+
+/// Southbridge info
+typedef  struct {
+  UINT8                 Type;                         ///< SB Model (SB800/SB700/...)
+  UINT8                 Revision;                     ///< SB Revision ID
+} SB_INFO;
+
+SB_INFO
+LibAmdSbGetRevisionInfo (
+  IN      VOID          *ConfigPtr
+  );
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbDef.h b/src/vendorcode/amd/cimx/rd890/nbDef.h
new file mode 100644
index 0000000..8589adc
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbDef.h
@@ -0,0 +1,532 @@
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBDEF_H_
+#define _NBDEF_H_
+
+#pragma pack (push, 1)
+
+AGESA_STATUS
+AmdPowerOnResetInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbPowerOnResetInit (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdHtInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbHtInit (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdEarlyPostInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbEarlyPostInit (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdMidPostInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbMidPostInit (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdLatePostInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbLatePostInit (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdPcieEarlyInit (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+PcieEarlyInit (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+
+AGESA_STATUS
+AmdS3Init (
+  IN  OUT AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+AmdS3InitIommu (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbS3Init (
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+AmdPcieLateInit (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+AmdPcieLateInitWa (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+AmdPcieValidatePortState (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+PcieLateInit (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+PcieLateInitWa (
+  IN      AMD_NB_CONFIG    *NbConfigPtr
+  );
+
+AGESA_STATUS
+PcieValidatePortState (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+PcieLateInitPorts (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+
+AGESA_STATUS
+AmdPcieS3Init (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+BOOLEAN
+PcieLibCheckGen2Disabled (
+  IN      PORT                PortId,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibSetGen2Disabled (
+  IN      PORT                PortId,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+
+PCI_ADDR
+PcieLibGetPortPciAddress (
+  IN        PORT              PortId,
+  IN        AMD_NB_CONFIG     *pConfig
+  );
+
+VOID
+PcieLibSetLinkCompliance (
+  IN        PORT              PortId,
+  IN        AMD_NB_CONFIG     *pConfig
+  );
+
+
+AGESA_STATUS
+PcieLibInitValidateInput (
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibSetPcieMmioBase (
+  IN    UINT16                PcieMmioBase,
+  IN    UINT16                PcieMmioSize,
+  IN    AMD_NB_CONFIG         *pConfig
+ );
+
+AGESA_STATUS
+PcieCheckSelectedPorts (
+  IN      UINT16              SelectedPortMask,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+PCIE_LINK_STATUS
+PcieGetPortsLinkStatus (
+  IN      UINT16              SelectedPortMask,
+  IN  OUT PCIE_LINK_STATUS    *PortLinkStatus,
+  IN      UINT32              Pooling,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+UINT16
+PcieFindPortsWithLinkStatus (
+  IN     PCIE_LINK_STATUS     *PortLinkStatus,
+  IN     PCIE_LINK_STATUS     LinkStatus
+  );
+
+AGESA_STATUS
+PcieBrokenLaneWorkaround (
+  IN      UINT16              SelectedPortMask,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieGen2Workaround (
+  IN      UINT16              SelectedPortMask,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieMiscWorkaround (
+  IN      PCIE_LINK_STATUS    *PortsLinkStatus,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieCheckVco (
+  IN      UINT16              SelectedPortMask,
+  IN      PCIE_LINK_STATUS    *PortsLinkStatus,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+VOID
+PcieLibPortTrainingControl (
+  IN       PORT               PortId,
+  IN       PCIE_LINK_TRAINING Operation,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+PcieLibSetCoreConfiguration (
+  IN        CORE              CoreId,
+  IN        AMD_NB_CONFIG     *pConfig
+  );
+
+VOID
+PcieLibCommonCoreInit (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+LINK_INFO
+PcieLibGetPortLinkInfo (
+  IN        PORT              PortId,
+  IN        AMD_NB_CONFIG     *pConfig
+  );
+
+VOID
+PcieLibPowerOffPortLanes (
+  IN      PORT                PortId,
+  IN      PCIE_LINK_WIDTH     Width,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+BOOLEAN
+PcieLibIsPortReversed (
+  IN        PORT              PortId,
+  IN        AMD_NB_CONFIG     *pConfig
+);
+
+VOID
+PcieLibPowerOffPll (
+  IN      CORE  CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieInitSelectedPorts (
+  IN      UINT16              SelectedPortMask,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibCommonPortInit (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibSetLinkMode (
+  IN      PORT                PortId,
+  IN      PCIE_LINK_MODE      Operation,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PciePreTrainingInit (
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieInitPorts (
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieAfterTrainingInit (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibUnHidePorts (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibHidePorts (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieLibRequestPciReset (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieLibResetSlot (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+VOID
+PcieLibManageTxClock (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibManageLclkClock (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibEnablePllPowerOffInL1 (
+  IN      CORE  CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+CORE
+PcieLibGetCoreId (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+UINT32
+PcieLibGetCoreAddress (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+AGESA_STATUS
+AmdPcieInitializer (
+  IN OUT  AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+PcieLibInitializer (
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+
+BOOLEAN
+PcieLibIsValidPortId (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+);
+
+BOOLEAN
+PcieLibIsValidCoreId (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+);
+
+VOID
+PcieLibPreTrainingInit (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibMiscLateCoreSetting (
+  IN      CORE  CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+AGESA_STATUS
+PcieLateValidateConfiguration (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieForcePortsVisibleOrDisable (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+/*
+VOID
+PcieReportCoreDisableStatus (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+*/
+
+AGESA_STATUS
+PcieLateInitCores (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+AGESA_STATUS
+PcieLateCommonPortInit (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+
+VOID
+PcieLibStrapModeControl (
+  IN      CORE                CoreId,
+  IN      PCIE_STRAP_MODE     Operation,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieLibCoreAfterTrainingInit (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+PORT_STATIC_INFO*
+PcieLibGetStaticPortInfo (
+  IN      PORT                PortId,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+CORE_INFO*
+PcieLibGetCoreInfo (
+  IN      CORE                CoreId,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+PORT
+PcieLibNativePortId (
+  IN      PORT                PortId,
+  IN  OUT AMD_NB_CONFIG       *pConfig
+  );
+
+
+VOID
+PcieNbSbSetupVc (
+  IN      AMD_NB_CONFIG       *pConfig
+ );
+
+
+VOID
+PcieLibLateInit (
+  IN      AMD_NB_CONFIG       *pConfig
+ );
+
+VOID
+PcieLibValidatePortStateInit (
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+VOID
+PcieInitiateSoftwareGen2 (
+  IN      PORT                PortId,
+  IN      AMD_NB_CONFIG       *pConfig
+ );
+
+AGESA_STATUS
+PcieRecoveryInitializer (
+  IN OUT  AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+PCI_CORE_RESET
+PcieLibCoreReset (
+  IN      CORE                CoreId,
+  IN      PCI_CORE_RESET      Operation,
+  IN      AMD_NB_CONFIG       *pConfig
+ );
+
+
+PORT_INFO*
+PcieLibGetPortInfo (
+  IN       PORT               PortId,
+  IN  OUT  AMD_NB_CONFIG      *pConfig
+  );
+
+PCIE_DEVICE_TYPE
+PcieGetDeviceType (
+  IN      PCI_ADDR            Device,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+UINT8
+PcieLibGetActiveCoreMap (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+#pragma pack (pop)
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbDispatcher.c b/src/vendorcode/amd/cimx/rd890/nbDispatcher.c
new file mode 100644
index 0000000..16e86a1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbDispatcher.c
@@ -0,0 +1,201 @@
+/**
+ * @file
+ *
+ *  Function dispatcher.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern AMD_MODULE_HEADER mNbModuleID;
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+CALLCONV
+AmdNbDispatcher (
+  IN OUT   VOID*ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  IMAGE_ENTRY ImageEntry;
+  ImageEntry = NULL;
+  Status = AGESA_UNSUPPORTED;
+  CIMX_INIT_TRACE ((ConfigPtr));
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Entry \n"));
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "    Funcid = %x Callout = %x\n", ((AMD_CONFIG_PARAMS*)ConfigPtr)->Func, ((AMD_CONFIG_PARAMS*)ConfigPtr)->CalloutPtr));
+
+#ifdef B1_IMAGE
+  // 1. Try to execute any B1 specific functions
+  switch (((AMD_CONFIG_PARAMS*)ConfigPtr)->Func) {
+    #ifdef B1_IMAGE
+    // B1 ONLY Functions
+    //
+    //
+    #endif
+  default:
+    break;
+  }
+#endif
+
+  // 2. If not B1 specific function but we are B1, see if we can find B2 instead
+#ifdef B1_IMAGE
+  if (Status == AGESA_UNSUPPORTED) {
+    UINTN ImageStart;
+    UINTN ImageEnd;
+    AMD_IMAGE_HEADER* AltImagePtr;
+    ImageStart = 0xFFF00000;
+    ImageEnd = 0xFFFFFFFF;
+    AltImagePtr = (AMD_IMAGE_HEADER*) (UINTN) ((AMD_CONFIG_PARAMS*)ConfigPtr)->AltImageBasePtr;
+
+    if ((UINTN)AltImagePtr != 0xFFFFFFFF) {
+      if (AltImagePtr != NULL) {
+        ImageStart = (UINT32) (UINTN)AltImagePtr;
+        ImageEnd = ImageStart + 4;
+      }
+      // Locate/test image base that matches this component
+      AltImagePtr = LibAmdLocateImage ((VOID*)ImageStart, (VOID*)ImageEnd, 4096, CIMX_NB_ID);
+      if (AltImagePtr != NULL) {
+        //Invoke alternative Image
+        ImageEntry = (IMAGE_ENTRY) (UINTN) ((UINT8*) AltImagePtr + AltImagePtr->EntryPointAddress);
+        Status = (*ImageEntry) (ConfigPtr);
+      }
+    }
+  }
+#endif
+  if (Status == AGESA_UNSUPPORTED) {
+ // 3. Try to execute any other functions
+    switch (((AMD_CONFIG_PARAMS*)ConfigPtr)->Func) {
+
+#if defined (B1_IMAGE) || defined (B2_IMAGE)
+// B1 & B2 Functions
+    case PH_AmdPowerOnResetInit:
+      Status = LibSystemApiCall (AmdPowerOnResetInit, ConfigPtr);
+      break;
+    case PH_AmdPcieEarlyInit:
+      Status = LibSystemApiCall (AmdPcieEarlyInit, ConfigPtr);
+      break;
+    case PH_AmdInitializer:
+      Status = LibSystemApiCall (AmdInitializer, ConfigPtr);
+      break;
+#endif
+#ifdef B2_IMAGE
+// B2 Functions
+    case PH_AmdNbHtInit :
+      Status = LibSystemApiCall (AmdHtInit, ConfigPtr);
+      break;
+    case PH_AmdEarlyPostInit  :
+      LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
+      Status = LibSystemApiCall (AmdEarlyPostInit, ConfigPtr);
+      break;
+    case PH_AmdMidPostInit  :
+      Status = LibSystemApiCall (AmdMidPostInit, ConfigPtr);
+      break;
+    case PH_AmdLatePostInit :
+      Status = LibSystemApiCall (AmdPcieLateInit, ConfigPtr);
+      Status = LibSystemApiCall (AmdLatePostInit, ConfigPtr);
+      Status = LibSystemApiCall (AmdPcieLateInitWa, ConfigPtr);
+      break;
+    case PH_AmdPcieValidatePortState :
+      Status = LibSystemApiCall (AmdPcieValidatePortState, ConfigPtr);
+      break;
+    case PH_AmdPcieLateInit :
+      Status = LibSystemApiCall (AmdPcieLateInit, ConfigPtr);
+      break;
+    case PH_AmdNbLateInit :
+      Status = LibSystemApiCall (AmdLatePostInit, ConfigPtr);
+      break;
+    case PH_AmdS3Init :
+      LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
+      Status = LibSystemApiCall (AmdS3InitIommu, ConfigPtr);
+      Status = LibSystemApiCall (AmdPcieS3Init, ConfigPtr);
+      Status = LibSystemApiCall (AmdS3Init, ConfigPtr);
+      Status = LibSystemApiCall (AmdPcieLateInitWa, ConfigPtr);
+      break;
+    case PH_AmdNbS3Init :
+      LibSystemApiCall (AmdMaskedMemoryInit, ConfigPtr);
+      Status = LibSystemApiCall (AmdS3Init, ConfigPtr);
+      break;
+    case PH_AmdPcieS3Init :
+      Status = LibSystemApiCall (AmdS3InitIommu, ConfigPtr);
+      Status = LibSystemApiCall (AmdPcieS3Init, ConfigPtr);
+      break;
+#endif
+#ifdef B3_IMAGE
+// B3 Functions
+#endif
+    default:
+      break;
+    }
+  }
+
+ // 4. Try next dispatcher if possible, and we have not already got status back
+  if ((mNbModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
+    MODULE_ENTRY  ModuleEntry;
+    CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 control goes to next Module \n"));
+    ModuleEntry = mNbModuleID.NextBlock->ModuleDispatcher;
+    Status = (*ModuleEntry) (ConfigPtr);
+  }
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_TRACE_ALL), "CIMx - RD890 Exit\n"));
+  return Status;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbEventLog.c b/src/vendorcode/amd/cimx/rd890/nbEventLog.c
new file mode 100644
index 0000000..4c228b0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbEventLog.c
@@ -0,0 +1,106 @@
+
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * This function logs NB events into a callback.
+ *
+ *
+ *
+ * @param[in]  EventClass
+ * @param[in]  EventInfo
+ * @param[in]  DataParam1
+ * @param[in]  DataParam2
+ * @param[in]  DataParam3
+ * @param[in]  DataParam4
+ * @param[in]  NbConfigPtr  Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+LibNbEventLog (
+  IN UINTN          EventClass,
+  IN UINT32         EventInfo,
+  IN UINT32         DataParam1,
+  IN UINT32         DataParam2,
+  IN UINT32         DataParam3,
+  IN UINT32         DataParam4,
+  IN AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  AGESA_EVENT   Event;
+  Event.EventClass = EventClass;
+  Event.EventInfo  = EventInfo;
+  Event.DataParam1 = DataParam1;
+  Event.DataParam2 = DataParam2;
+  Event.DataParam3 = DataParam3;
+  Event.DataParam4 = DataParam4;
+  if (EventClass > ((API_WORKSPACE*)NbConfigPtr->ConfigPtr)->Status) {
+    ((API_WORKSPACE*)NbConfigPtr->ConfigPtr)->Status = EventClass;
+  }
+  LibNbCallBack (PHCB_AmdReportEvent, (UINTN)&Event, NbConfigPtr);
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbEventLog.h b/src/vendorcode/amd/cimx/rd890/nbEventLog.h
new file mode 100644
index 0000000..cf313fa
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbEventLog.h
@@ -0,0 +1,95 @@
+
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBEVENTLOG_H_
+#define _NBEVENTLOG_H_
+
+#pragma pack(push, 1)
+
+/**
+ * Event
+ *
+ */
+typedef struct {
+  UINTN    EventClass;     /**< Event Class.
+                            *  @li <b>AGESA_WARNING</b>
+                            *  @li <b>AGESA_ERROR</b>
+                            *  @li <b>AGESA_FATAL</b>
+                           */
+  UINT32   EventInfo;     /**< Event Info.
+                           *   This parameter used as event identifier
+                           */
+  UINT32   DataParam1;    ///< Event specific data
+  UINT32   DataParam2;    ///< Event specific data
+  UINT32   DataParam3;    ///< Event specific data
+  UINT32   DataParam4;    ///< Event specific data
+} AGESA_EVENT;
+
+
+#define PCIE_ERROR_HOTPLUG_INIT                 0x20010100
+#define PCIE_ERROR_TRAINING_FAIL                0x20010200
+#define PCIE_ERROR_CORE_CONFIGURATION           0x20010300
+#define PCIE_ERROR_BROKEN_LINE                  0x20010400
+#define PCIE_ERROR_GEN2_FAIL                    0x20010500
+#define PCIE_ERROR_VCO_NEGOTIATON               0x20010600
+#define PCIE_ERROR_DEVICE_REMAP                 0x20010700
+#define GENERAL_ERROR_BAD_CONFIGURATION         0x20000100
+#define GENERAL_ERROR_NB_NOT_PRESENT            0x20000200
+#define GENERAL_ERROR_LOCATE_ACPI_TABLE         0x20000300
+
+
+VOID
+LibNbEventLog (
+  IN      UINTN         EventClass,
+  IN      UINT32        EventInfo,
+  IN      UINT32        DataParam1,
+  IN      UINT32        DataParam2,
+  IN      UINT32        DataParam3,
+  IN      UINT32        DataParam4,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  );
+
+#pragma pack(pop)
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInit.c b/src/vendorcode/amd/cimx/rd890/nbHtInit.c
new file mode 100644
index 0000000..687219a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInit.c
@@ -0,0 +1,626 @@
+/**
+ * @file
+ *
+ * HT Initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define LINK_BUFFERS_IFCM  ((1 << 31) + (1 << 25) + (8 << 20) + (1 << 18) + (1 << 8) + (6 << 5) + 0xF)
+#define LINK_BUFFERS_NFCM  ((1 << 31) + (1 << 25) + (8 << 20) + (1 << 18) + (1 << 8) + (6 << 5) + 0x11)
+#define SUBLINK_BUFFERS_IFCM  ((1 << 31) + (1 << 25) + (8 << 20) + (1 << 18) + (1 << 8) + (6 << 5) + 0xF)
+#define SUBLINK_BUFFERS_NFCM  ((1 << 31) + (1 << 25) + (8 << 20) + (1 << 18) + (1 << 8) + (6 << 5) + 0x11)
+
+typedef VOID DUMMY_CALL (VOID);
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+NbInitRasParityMacro (
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT8 IBIASCodeTable[] = {
+//0.2G        0.5G        0.6G
+  0x44, 0x00, 0x44, 0x00, 0xb6,
+//0.8G  1.0G  1.2G  1.4G  1.6G
+  0x44, 0x96, 0xb6, 0x23, 0x44,
+//1.8G  2.0G  2.2G  2.4G  2.6G
+  0x64, 0x96, 0xA6, 0xb6, 0xc6
+};
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Init at early post.
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+HtLibEarlyInit (
+  IN OUT   AMD_NB_CONFIG *pConfig
+  )
+{
+  AGESA_STATUS            Status;
+  UINT32                  Value;
+  PCI_ADDR                ClkPciAddress;
+  PCI_ADDR                CpuPciAddress;
+  PCI_ADDR                LinkPciAddress;
+  HT_CONFIG               *pHtConfig;
+  UINT8                   CpuHtSpeed;
+  UINT8                   NbHtSpeed;
+  HT_INACTIVE_LANE_STATE  InLnSt;
+  BOOLEAN                 IsIfcmEnabled;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "[NBHT]HtLibEarlyInit Enter\n"));
+  pHtConfig = GET_HT_CONFIG_PTR (pConfig);
+  Status = AGESA_SUCCESS;
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Device = 1;
+  CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, pConfig->NbHtPath.NodeID + 0x18, 0,  0);
+  LinkPciAddress.AddressValue = MAKE_SBDFO (0, 0, pConfig->NbHtPath.NodeID + 0x18, ((pConfig->NbHtPath.LinkID & 0xF0) > 0x10)?4:0,  0);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "    Node %d Link %d PciAddress %x\n", pConfig->NbHtPath.NodeID, pConfig->NbHtPath.LinkID, LinkPciAddress.AddressValue));
+  LibNbEnableClkConfig (pConfig);
+//Get Ht Speed  Info
+  LibNbPciRead (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x89), AccessWidth8, &CpuHtSpeed, pConfig);
+  LibNbPciRead (pConfig->NbPciAddress.AddressValue | NB_PCI_REGD1 , AccessWidth8, &NbHtSpeed, pConfig);
+  NbHtSpeed &= 0xf;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "    Ht speed Cpu %x Nb %x\n", CpuHtSpeed, NbHtSpeed));
+//Set IBIAS code
+  LibNbPciRMW (ClkPciAddress.AddressValue | NB_CLK_REGD8, AccessWidth16, (UINT32)~(0x3ff), ((UINT8*)FIX_PTR_ADDR (&IBIASCodeTable[0], NULL))[(pHtConfig->HtReferenceClock / 200)*CpuHtSpeed], pConfig);
+  if (CpuHtSpeed > HT_FREQUENCY_1000M) {
+    UINT8 T0Time;
+    UINT8 ForceFullT0;
+//Enable Protocol checker
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG1E, AccessWidth32, 0, 0x7FFFFFFC, pConfig);
+//Set NB Transmitter Deemphasis
+    if ((pHtConfig->NbTransmitterDeemphasis & 0x80) == 0) {
+      LibHtSetNbTransmitterDeemphasis (pHtConfig->NbTransmitterDeemphasis, pConfig);
+    }
+    LibNbPciRead (CpuPciAddress.AddressValue | 0x16C, AccessWidth32, &Value, pConfig);
+    T0Time = (UINT8) (Value & 0x3F);
+    ForceFullT0 = (UINT8) ((Value >> 13) & 0x7);
+//Enable LS State and set T0Time
+    //T0Time = 0x14; //2us
+    if (pHtConfig->LSx <  HtLinkStateSkipInit) {
+      if (pHtConfig->LSx == HtLinkStateSameAsCpu) {
+        LibNbPciRead (
+          CpuPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 4 + HT_PATH_SUBLINK_ID (pConfig->NbHtPath) * 0x10 + 0x170),
+          AccessWidth32,
+          &Value,
+          pConfig
+          );
+        if ((Value & BIT8) != 0) {
+          pHtConfig->LSx = HtLinkStateLS2;
+        } else {
+          pHtConfig->LSx = HtLinkStateLS1;
+        }
+      } else {
+        if (pHtConfig->LSx >=  HtLinkStateLS2) {
+          T0Time = 0x26; //12us
+          ForceFullT0 = 0x6;
+        } else {
+          T0Time = 0x14; //2us
+          ForceFullT0 = 0x0;
+        }
+      }
+      if (CpuHtSpeed == NbHtSpeed) {
+        LibHtEnableLxState (pHtConfig->LSx, pConfig);
+      }
+    }
+//Set up InLnSt
+    //Match CPU InLnSt except for HT3 LS1
+    LibNbPciRead (
+      CpuPciAddress.AddressValue | 0x16C,
+      AccessWidth32,
+      &Value,
+      pConfig
+      );
+    InLnSt = (Value >> 6) & 0x3;
+
+    // Do not enable HT3 LS1 with InLnSt == 0x1 (PHY_OFF) as per errata 9
+    if (pHtConfig->LSx == HtLinkStateLS1) {
+      if (InLnSt == InactiveLaneStateSameAsPhyOff) {
+        InLnSt = InactiveLaneStateCadCtrlDrivelToLogic0;
+      }
+    }
+    LibNbPciRMW (
+      pConfig->NbPciAddress.AddressValue | NB_PCI_REGA0,
+      AccessWidth8,
+      0x00,
+      T0Time | (InLnSt << 6),
+      pConfig
+      );
+    LibNbPciRMW (
+      CpuPciAddress.AddressValue | 0x16C,
+      AccessWidth16,
+      (UINT32)(~((0x7 << 13) + 0x3f)),
+      T0Time | (ForceFullT0 << 13),
+      pConfig
+      );
+  // Disable command throtling
+    LibNbPciRMW (pConfig->NbPciAddress.AddressValue | (NB_PCI_REGAC + 1), AccessWidth8, (UINT32)~BIT6, BIT6, pConfig);
+    LibNbPciRMW (CpuPciAddress.AddressValue | 0x168, AccessWidth16, (UINT32)~BIT10, BIT10, pConfig);
+  // Enables strict TM4 detection
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessWidth32, (UINT32)~BIT22, BIT22, pConfig);
+  } else {
+  //Set Link Tristate
+    if (pHtConfig->HtLinkTriState < HtLinkTriStateSkip) {
+      if (pHtConfig->HtLinkTriState == HtLinkTriStateSameAsCpu) {
+        LibNbPciRead (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x84), AccessWidth16, &Value, pConfig);
+        if ((Value & BIT13) != 0) {
+          pHtConfig->HtLinkTriState = HtLinkTriStateCadCtl;
+          LibNbPciRead (
+            CpuPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 4 + HT_PATH_SUBLINK_ID (pConfig->NbHtPath) * 0x10 + 0x170),
+            AccessWidth16,
+            &Value,
+            pConfig
+            );
+          if ((Value & BIT8) != 0) {
+            pHtConfig->HtLinkTriState = HtLinkTriStateCadCtlClk;
+          }
+        }
+      }
+      if (pHtConfig->HtLinkTriState >= HtLinkTriStateCadCtl) {
+        UINT16 TriStateValue;
+        TriStateValue = 0;
+        LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REGC8, AccessWidth16 , (UINT32)~BIT13, BIT13, pConfig);
+        LibNbPciRMW (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x84), AccessWidth16, (UINT32)~(BIT13), BIT13, pConfig);
+        if (pHtConfig->HtLinkTriState == HtLinkTriStateCadCtlClk) {
+          TriStateValue = BIT8;
+        }
+        LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REGAC, AccessWidth16, (UINT32)~BIT8, TriStateValue, pConfig);
+        if (LibNbGetCpuFamily () != 0x0) {
+          LibNbPciRMW (
+            CpuPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 4 + HT_PATH_SUBLINK_ID (pConfig->NbHtPath) * 0x10 + 0x170),
+            AccessWidth16,
+            (UINT32)~(BIT8),
+            TriStateValue,
+            pConfig
+            );
+        }
+      }
+    }
+    LibNbPciRMW (
+      pConfig->NbPciAddress.AddressValue | NB_PCI_REGA0,
+      AccessWidth8,
+      0x3f,
+      InactiveLaneStateSameAsPhyOff << 6,
+      pConfig
+      );
+  }
+  //Enable 64bit address mode
+
+  if ((pHtConfig->HtExtendedAddressSupport & 0x80) == 0) {
+    LibNbPciRead (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x85), AccessWidth8, &Value, pConfig);
+    if (pHtConfig->HtExtendedAddressSupport == HtExtAddressingSameAsCpu) {
+      Value &= BIT7;
+    } else {
+      Value = (pHtConfig->HtExtendedAddressSupport == HtExtAddressingEnable)? BIT7 : 0;
+    }
+    LibNbPciRMW (((pConfig->NbPciAddress.AddressValue) | (NB_PCI_REGC8 + 1)), AccessWidth8, 0x7C, Value, pConfig);
+    LibNbPciRMW (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x85), AccessWidth8, 0x7F, Value, pConfig);
+  }
+
+  // Check if IFCM enabled in CPU
+  LibNbPciRead (LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x85), AccessWidth8, &Value, pConfig);
+  IsIfcmEnabled = (Value & BIT4) ? TRUE:FALSE;
+  if (IsIfcmEnabled) {
+    // Enable Isoc in chipset
+    LibNbPciRMW (((pConfig->NbPciAddress.AddressValue) | (NB_PCI_REGC8 + 1)), AccessWidth8, 0xFC, BIT4, pConfig);
+  }
+
+  if (pHtConfig->LinkBufferOptimization == ON) {
+    BOOLEAN IsConnectedToSublink;
+    IsConnectedToSublink = (pConfig->NbHtPath.LinkID & 0xF0) > 0 ? TRUE:FALSE;
+    if (IsConnectedToSublink) {
+      Value = IsIfcmEnabled ? SUBLINK_BUFFERS_IFCM : SUBLINK_BUFFERS_NFCM;
+    } else {
+      Value = IsIfcmEnabled ? LINK_BUFFERS_IFCM : LINK_BUFFERS_NFCM;
+    }
+    LibNbPciRMW (
+      LinkPciAddress.AddressValue | (HT_PATH_LINK_ID (pConfig->NbHtPath) * 32 + 0x90),
+      AccessWidth32,
+      0x0,
+      Value,
+      pConfig
+      );
+  }
+  NbInitRasParityMacro (pConfig);
+  LibNbDisableClkConfig (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "[NBHT]HtLibEarlyInit Exit [0x%x]\n", Status));
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set NB transmitter deemphasis level.
+ *
+ *
+ * @param[in] NbDeemphasisLevel  NB Deemphasis level See HT_CONFIG::NbTransmitterDeemphasis
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ *
+ */
+VOID
+LibHtSetNbTransmitterDeemphasis (
+  IN      UINT8         NbDeemphasisLevel,
+  IN      AMD_NB_CONFIG *pConfig
+  )
+{
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REGA7, AccessWidth8, (UINT32)~0x07, NbDeemphasisLevel + BIT7, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable LSx state
+ *
+ *
+ *
+ * @param[in] LSx     LS State to enable. See HT_CONFIG::LSx
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+LibHtEnableLxState (
+  IN      UINT8         LSx,
+  IN      AMD_NB_CONFIG *pConfig
+  )
+{
+  UINT32  Value;
+  UINT32  NbLSx;
+  UINT32  CpuLSx;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "    Enable HT LS%d\n", LSx));
+  switch (LSx) {
+  case 0:
+    Value = LS0;
+    break;
+  case 1:
+    Value = LS1;
+    break;
+  case 2:
+    Value = LS2;
+    break;
+  case 3:
+    Value = LS3;
+    break;
+  default:
+    Value = 0;
+    CIMX_ASSERT (FALSE);
+    return;
+  }
+  NbLSx = (Value << 7);
+  CpuLSx = (LSx >= 2)?BIT8:0;
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REGAC, AccessWidth16, (UINT32)~(BIT7 + BIT8), NbLSx, pConfig);
+  LibNbPciRMW (
+    MAKE_SBDFO (0, 0, pConfig->NbHtPath.NodeID + 0x18, 0, HT_PATH_LINK_ID (pConfig->NbHtPath) * 4 + HT_PATH_SUBLINK_ID (pConfig->NbHtPath) * 0x10 + 0x170),
+    AccessWidth32,
+    (UINT32)~BIT8,
+    CpuLSx,
+    pConfig
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB validate HY Input parameters
+ *
+ *
+ *
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+HtLibInitValidateInput (
+  IN OUT   AMD_NB_CONFIG *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  HT_CONFIG     *pHtConfig;
+  NB_INFO       NbInfo;
+
+  Status = AGESA_SUCCESS;
+  pHtConfig = GET_HT_CONFIG_PTR (pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  if (pHtConfig == NULL || NbInfo.Type == NB_UNKNOWN) {
+    return  AGESA_FATAL;
+  }
+  if (pHtConfig->sHeader.InitializerID != INITIALIZED_BY_INITIALIZER) {
+    Status = HtLibInitializer (pConfig);
+  }
+  return  Status;
+}
+
+UINT8 SmuWaBasePeriod[] = {
+  0x1F,   //HT 200Mhz
+  0x00,
+  0x1F,   //HT 400Mhz
+  0x00,
+  0x17,   //HT 600Mhz
+  0x1F,   //HT 800Mhz
+  0x27,   //HT 1000Mhz
+  0x2E,   //HT 1200Mhz
+  0x36,   //HT 1400Mhz
+  0x3E,   //HT 1600Mhz
+  0x46,   //HT 1800Mhz
+  0x4E,   //HT 2000Mhz
+  0x55,   //HT 2200Mhz
+  0x5D,   //HT 2400Mhz
+  0x65    //HT 2600Mhz
+};
+
+UINT8 SmuWaBaseDelay[] = {
+  0x3,   //HT 200Mhz
+  0x0,
+  0x3,   //HT 400Mhz
+  0x0,
+  0x2,   //HT 600Mhz
+  0x3,   //HT 800Mhz
+  0x3,   //HT 1000Mhz
+  0x4,   //HT 1200Mhz
+  0x5,   //HT 1400Mhz
+  0x6,   //HT 1600Mhz
+  0x7,   //HT 1800Mhz
+  0x7,   //HT 2000Mhz
+  0x8,   //HT 2200Mhz
+  0x9,   //HT 2400Mhz
+  0xA    //HT 2600Mhz
+};
+
+UINT8 SmuWaPeriod10us[] = {
+  120,
+  100,
+  90,
+  80
+};
+
+UINT8 SmuWaDelay1us[] = {
+  0x0,   //HT 200Mhz
+  0x0,
+  0x0,   //HT 400Mhz
+  0x0,
+  0x0,   //HT 600Mhz
+  0x0,   //HT 800Mhz
+  0x0,   //HT 1000Mhz
+  0x0,   //HT 1200Mhz
+  0x2,   //HT 1400Mhz
+  0x2,   //HT 1600Mhz
+  0x2,   //HT 1800Mhz
+  0x3,   //HT 2000Mhz
+  0x3,   //HT 2200Mhz
+  0x4,   //HT 2400Mhz
+  0x4    //HT 2600Mhz
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get SMU wa data
+ *
+ *
+ *
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ * @retval                      SMU wa data
+ */
+
+UINT32
+LibHtGetSmuWaData (
+  IN       AMD_NB_CONFIG *pConfig
+  )
+{
+  UINT8                 NorthbridgeId;
+  UINT8                 NorthbridgeIndex;
+  UINT8                 NbHtSpeed;
+  UINT16                SmuWaPeriod;
+  UINT16                SmuWaDelay;
+  AMD_NB_CONFIG_BLOCK   *ConfigPtr;
+  NorthbridgeIndex = 0;
+  ConfigPtr = GET_BLOCK_CONFIG_PTR (pConfig);
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    AMD_NB_CONFIG *NbConfigPtr = &ConfigPtr->Northbridges[NorthbridgeId];
+    if (LibNbIsDevicePresent (NbConfigPtr->NbPciAddress, NbConfigPtr)) {
+      if (pConfig == NbConfigPtr) {
+        LibNbPciRead (pConfig->NbPciAddress.AddressValue | NB_PCI_REGD1 , AccessWidth8, &NbHtSpeed, pConfig);
+        NbHtSpeed &= 0xf;
+        SmuWaPeriod = SmuWaPeriod10us [NorthbridgeIndex] * SmuWaBasePeriod [NbHtSpeed];
+        SmuWaDelay = SmuWaDelay1us [NbHtSpeed] * SmuWaBaseDelay [NbHtSpeed];
+        return ((SmuWaPeriod & 0xFF) << 8) | ((SmuWaPeriod & 0xFF00) >> 8) | ((SmuWaDelay & 0xFF) << 24) | ((SmuWaDelay & 0xFF00) << 8);
+      }
+      NorthbridgeIndex++;
+    }
+  }
+  return 0;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init RAS macro
+ *
+ *
+ *
+ *
+ *  @param[in] NbConfigPtr  Northbridge configuration structure pointer.
+ */
+VOID
+NbInitRasParityMacro (
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  PCI_ADDR    CpuPciAddress;
+  UINT32      SaveBase;
+  UINT32      SaveLimit;
+  UINT32      Value;
+  UINT32      Base;
+  UINT32      Limit;
+  UINT32      Index;
+  UINT64      SaveTom;
+  UINT64      Value64;
+  DUMMY_CALL  *RetAddr;
+  UINT8       Node;
+  CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1,  0);
+//Set TOM
+  LibAmdMsrRead (0xC001001a, &SaveTom, (AMD_CONFIG_PARAMS *)NbConfigPtr);
+  Value64 = 0x40000000;
+  LibAmdMsrWrite (0xC001001a, &Value64, (AMD_CONFIG_PARAMS *)NbConfigPtr);
+//Set mmio
+  LibNbPciRead (CpuPciAddress.AddressValue | 0x80, AccessWidth32, &SaveBase, NbConfigPtr);
+  LibNbPciRead (CpuPciAddress.AddressValue | 0x84, AccessWidth32, &SaveLimit, NbConfigPtr);
+  Limit = ((0x50000000 - 1) >> 8) & (~ 0xFF);
+  Limit |= NbConfigPtr->NbHtPath.NodeID | (HT_PATH_LINK_ID (NbConfigPtr->NbHtPath) << 4) | (HT_PATH_SUBLINK_ID (NbConfigPtr->NbHtPath) << 6);
+  Base = ((0x40000000 >> 8) & (~ 0xFF)) | 0x3;
+  for (Node = 0; Node < 8; Node++) {
+    CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1,  0);
+    if (LibNbIsDevicePresent (CpuPciAddress, NbConfigPtr)) {
+      LibNbPciWrite (CpuPciAddress.AddressValue | 0x84, AccessWidth32, &Limit, NbConfigPtr);
+      LibNbPciWrite (CpuPciAddress.AddressValue | 0x80, AccessWidth32, &Base, NbConfigPtr);
+    } else {
+      break;
+    }
+  }
+//set Scan
+  LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG06, AccessWidth32, (UINT32)~BIT27, BIT27, NbConfigPtr);
+  RetAddr = (DUMMY_CALL* ) (UINTN) 0x40000000;
+  *((UINT8*) (UINTN) RetAddr) = 0xC3;
+  for (Index = 0; Index < 64; Index++) {
+    RetAddr ();
+    RetAddr = (DUMMY_CALL*) (UINTN) ((UINT8*) (UINTN) RetAddr + 64);
+  }
+//Reset scan
+  LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG06, AccessWidth32, (UINT32)~BIT27, 0x0, NbConfigPtr);
+  Value = 0;
+// Restore MMIO Map
+  for (Node = 0; Node < 8; Node++) {
+    CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1,  0);
+    if (LibNbIsDevicePresent (CpuPciAddress, NbConfigPtr)) {
+      LibNbPciWrite (CpuPciAddress.AddressValue | 0x80, AccessWidth32, &Value, NbConfigPtr);
+      LibNbPciWrite (CpuPciAddress.AddressValue | 0x84, AccessWidth32, &SaveLimit, NbConfigPtr);
+      LibNbPciWrite (CpuPciAddress.AddressValue | 0x80, AccessWidth32, &SaveBase, NbConfigPtr);
+    } else {
+      break;
+    }
+  }
+// Restore TOM
+  LibAmdMsrWrite (0xC001001a, &SaveTom, (AMD_CONFIG_PARAMS *)NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for all NB.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdHtInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (HtLibInitializer, ConfigPtr);
+  return Status;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * HT config structure initializer
+ *
+ *
+ *
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+HtLibInitializer (
+  IN OUT   AMD_NB_CONFIG *pConfig
+  )
+{
+  HT_CONFIG *pHtConfig;
+
+  pHtConfig = GET_HT_CONFIG_PTR (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "[NBHT]HtLibInitializer Enter\n"));
+  if (pHtConfig == NULL) {
+    return  AGESA_WARNING;
+  }
+  if (pHtConfig->sHeader.InitializerID == INITIALIZED_BY_INITIALIZER) {
+    return  AGESA_SUCCESS;
+  }
+  LibAmdMemFill (pHtConfig, 0, sizeof (HT_CONFIG), (AMD_CONFIG_PARAMS *)&(pHtConfig->sHeader));
+  pHtConfig->sHeader.InitializerID = INITIALIZED_BY_INITIALIZER;
+  pHtConfig->HtExtendedAddressSupport = HtExtAddressingSameAsCpu;
+  pHtConfig->HtLinkTriState = HtLinkTriStateSameAsCpu;
+  pHtConfig->HtReferenceClock = 200;
+// Select LS State
+  pHtConfig->LSx = HtLinkStateSameAsCpu;
+  pHtConfig->LinkBufferOptimization = OFF;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBHT_TRACE), "[NBHT]HtLibInitializer Exit\n"));
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInit.h b/src/vendorcode/amd/cimx/rd890/nbHtInit.h
new file mode 100644
index 0000000..1f8c23d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInit.h
@@ -0,0 +1,126 @@
+/**
+ * @file
+ *
+ * HT definitions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _NBHTINIT_H_
+#define _NBHTINIT_H_
+
+///HT link inactive lane
+typedef enum {
+  InactiveLaneStateCadCtrlDrivelToLogic0 = 0,   ///< No clock
+  InactiveLaneStateSameAsPhyOff,                ///< Same as PHY OFF
+  InactiveLaneStateSameAsOperational,           ///< Same as operational
+  InactiveLaneStateSameAsDisconnected,          ///< Same as disconnected
+} HT_INACTIVE_LANE_STATE;
+
+AGESA_STATUS
+HtLibEarlyInit (
+  IN  OUT   AMD_NB_CONFIG *pConfig
+  );
+
+
+AGESA_STATUS
+HtLibInitValidateInput (
+  IN  OUT   AMD_NB_CONFIG *pConfig
+  );
+
+VOID
+LibHtSetNbTransmitterDeemphasis (
+  IN        UINT8        NbDeemphasisLevel,
+  IN        AMD_NB_CONFIG *pConfig
+  );
+
+VOID
+LibHtEnableLxState (
+  IN        UINT8    LSx,
+  IN        AMD_NB_CONFIG *pConfig
+  );
+
+AGESA_STATUS
+AmdHtInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+HtLibInitializer (
+  IN  OUT   AMD_NB_CONFIG *pConfig
+  );
+
+UINT32
+LibHtGetSmuWaData (
+  IN        AMD_NB_CONFIG *pConfig
+  );
+
+#define LS1    0
+#define LS0    1
+#define LS2    2
+#define LS3    3
+
+/// HT link state
+typedef enum {
+  HtLinkStateLS0 = 0,             ///< LS0
+  HtLinkStateLS1,                 ///< LS1
+  HtLinkStateLS2,                 ///< LS2
+  HtLinkStateLS3,                 ///< LS3
+  HtLinkStateSameAsCpu,           ///< Same as set on CPU
+  HtLinkStateSkipInit = 0x80      ///< Skip initialization
+} HT_LS_STATE;
+
+/// HT Link Tri-state
+typedef enum {
+  HtLinkTriStateCadCtl = 1,     ///< control/data
+  HtLinkTriStateCadCtlClk,      ///< CAD clk
+  HtLinkTriStateSameAsCpu,      ///< Same as set on CPU
+  HtLinkTriStateSkip = 0x80     ///< Skip initialization
+} HT_LINK_TRISTATE;
+
+/// HT Link Tri-state
+typedef enum {
+  HtExtAddressingDisable = 0,     ///< Disable ext addressing
+  HtExtAddressingEnable,          ///< Enable Ext addressing
+  HtExtAddressingSameAsCpu,       ///< Set Ext addressing as on CPU
+  HtExtAddressingSkip = 0x80      ///< Skip initialization
+} HT_EXT_ADDRESSING;
+
+#define HT_PATH_LINK_ID(htPath) (htPath.LinkID & 0xf)
+#define HT_PATH_SUBLINK_ID(htPath) (((htPath.LinkID & 0xf0) == 0) ? 0 : (((htPath.LinkID & 0xf0) >> 4) - 1))
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbHtInterface.c b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
new file mode 100644
index 0000000..ecb5e0d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbHtInterface.c
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ *  HT Init interfaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Early system wide HT init
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+
+AGESA_STATUS
+AmdHtInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NBHT_TRACE), "[NBHT]AmdHtInit Enter\n"));
+  Status = LibNbApiCall (NbHtInit, ConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NBHT_TRACE), "[NBHT]AmdHtInit Exit [0x%x]\n", Status));
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Early Nb HT init.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+
+AGESA_STATUS
+NbHtInit (
+  IN OUT   AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBHT_TRACE), "[NBHT]NbHtInit Enter\n"));
+  Status = HtLibInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0 , 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  Status = HtLibEarlyInit (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBHT_TRACE), "[NBHT]NbHtInit Exit [0x%x]\n", Status));
+  return  Status;
+}
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbInit.c b/src/vendorcode/amd/cimx/rd890/nbInit.c
new file mode 100644
index 0000000..8a5c5db
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbInit.c
@@ -0,0 +1,417 @@
+/**
+ * @file
+ *
+ * NB Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Early post validate input parameters
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbLibEarlyPostInitValidateInput (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  NB_CONFIG     *pNbConfig;
+  NB_INFO       NbInfo;
+
+  Status = AGESA_SUCCESS;
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  if (NbInfo.Type == NB_UNKNOWN) {
+    return  AGESA_FATAL;
+  }
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (pNbConfig->sHeader.InitializerID != INITIALIZED_BY_INITIALIZER) {
+    Status = NbLibInitializer (pConfig);
+  }
+  if (pNbConfig->SysMemoryTomBelow4G == 0) {
+    Status =  AGESA_FATAL;
+  }
+  //pNbConfig->sHeader.InitializerID = PH_AmdEarlyPostInit;
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Mid/Late post validate input parameters
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbLibPostInitValidateInput (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  NB_CONFIG     *pNbConfig;
+  NB_INFO       NbInfo;
+
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  Status = AGESA_SUCCESS;
+  if (NbInfo.Type == NB_UNKNOWN) {
+    return  AGESA_FATAL;
+  }
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (pNbConfig->sHeader.InitializerID != INITIALIZED_BY_INITIALIZER) {
+    Status = AGESA_FATAL;
+  }
+  //pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  //if (pNbConfig->sHeader.InitializerID != PH_AmdEarlyPostInit) {
+  //  return  AGESA_FATAL;
+  //}
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Prepare NB to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbLibPrepareToOS (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG00, AccessS3SaveWidth32, 0xffffffff, BIT7, pConfig);
+  return  AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Multiple NB support
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+NbMultiNbIocInit (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT32    Value;
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (GET_BLOCK_CONFIG_PTR (pConfig)->NumberOfNorthbridges > 0) {
+    if (pConfig->NbPciAddress.AddressValue == 0) {
+      //Primary NB
+      Value = BIT3 + (HT_INTERRUPT_ENCODING_OFFSET << 4);
+    } else {
+      //Secondary NB
+      Value = BIT2 + (HT_INTERRUPT_ENCODING_OFFSET << 4);
+    }
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG75, AccessS3SaveWidth32, (UINT32)~((0x7f << 2) + BIT28) , Value, pConfig);
+  }
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG75, AccessS3SaveWidth32, (UINT32)~(BIT9 + BIT10 + BIT28), pNbConfig->P2PMode << 9, pConfig);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set NB SSID/SVID.
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+NbLibSetSSID (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (pNbConfig->SSID == 0xffffffff) {
+    LibNbPciRead (pConfig->NbPciAddress.AddressValue, AccessWidth32, &pNbConfig->SSID, pConfig);
+  }
+  if (pNbConfig->SSID != 0) {
+    LibNbPciWrite (pConfig->NbPciAddress.AddressValue | NB_PCI_REG50, AccessS3SaveWidth32, &pNbConfig->SSID, pConfig);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Setup UnitId clamping
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+NbLibSetupClumping (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT16    ClumpingCapability;
+  UINT16    Value;
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  Value = 0;
+  if (LibNbGetCpuFamily () == CPU_FAMILY_NPT) {
+    return;
+  }
+  LibNbPciRead (pConfig->NbPciAddress.AddressValue | NB_PCI_REG58, AccessS3SaveWidth16, &ClumpingCapability, pConfig);
+  if ((ClumpingCapability & BIT3) != 0 &&
+      (pNbConfig->UnitIdClumping & DEV3_CLUMPING) != 0 &&
+      !LibNbIsDevicePresent (PcieLibGetPortPciAddress (3, pConfig), pConfig)) {
+    Value |= BIT3;
+  }
+  if ((ClumpingCapability & BIT12) != 0 &&
+      (pNbConfig->UnitIdClumping & DEV12_CLUMPING) != 0 &&
+      !LibNbIsDevicePresent (PcieLibGetPortPciAddress (12, pConfig), pConfig)) {
+    Value |= BIT12;
+  }
+  if (Value != 0) {
+    LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG5C, AccessS3SaveWidth16, 0xffff, Value, pConfig);
+    LibNbPciRMW (MAKE_SBDFO (0, 0, pConfig->NbHtPath.NodeID + 0x18, 0, HT_PATH_LINK_ID (pConfig->NbHtPath) * 4 + HT_PATH_SUBLINK_ID (pConfig->NbHtPath) * 0x10 + 0x110), AccessS3SaveWidth16, 0xffff, Value, pConfig);
+  }
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set top of memory  in NB.
+ *    NB will not pass to CPU any upstream DMA request to address above TOM and TOM2
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbLibSetTopOfMemory (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  NB_CONFIG *pNbConfig;
+  UINT32    RD890_TOM2;
+  UINT32    RD890_TOM3;
+
+  RD890_TOM2 = 0;
+  RD890_TOM3 = 0;
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (pNbConfig->SysMemoryTomBelow4G != 0) {
+    LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG90, AccessS3SaveWidth32, 0, ((UINT32)pNbConfig->SysMemoryTomBelow4G) << 20, pConfig);
+  }
+  if (pNbConfig->SysMemoryTomAbove4G != 0) {
+    if ((pNbConfig->SysMemoryTomAbove4G - 1) <= 0xfffff) {
+      RD890_TOM2 = pNbConfig->SysMemoryTomAbove4G;
+    } else {
+      RD890_TOM2 = (UINT32) (0xFD00000000 >> 20);
+      RD890_TOM3 = pNbConfig->SysMemoryTomAbove4G;
+    }
+  }
+  if (RD890_TOM2 != 0) {
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG31, AccessS3SaveWidth32, 0, (RD890_TOM2 >> 12), pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG30, AccessS3SaveWidth32, 0, (RD890_TOM2 << 20) | 1, pConfig);
+  }
+  if (RD890_TOM3 != 0) {
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG4E, AccessS3SaveWidth32, 0, ((UINT32)pNbConfig->SysMemoryTomAbove4G >> 2) | BIT31, pConfig);
+  }
+  return  AGESA_SUCCESS;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Loget COre APic ID and dtore to scratch
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+NbLibGetCore0ApicId (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT64    Value;
+  UINT32    Apic20;
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  LibAmdMsrRead (0x0000001B, &Value, (AMD_CONFIG_PARAMS *)pConfig);
+  LibNbMemRead ((Value & 0xfffffffff000) + 0x20, AccessWidth32, &Apic20, pConfig);
+  pNbConfig->Reserved = (UINT16) (Apic20 >> 24);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Direct NMI message to Core 0
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+VOID
+NbLibSetNmiRouting (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    NB_MISC_REG12,
+    AccessS3SaveWidth32,
+    0x00ffffff,
+    (UINT32)pNbConfig->Reserved << 24,
+    pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for all NB.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdNbInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (NbLibInitializer, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB config structure initializer
+ *
+ *
+ *
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+NbLibInitializer (
+  IN OUT   AMD_NB_CONFIG *pConfig
+  )
+{
+  UINT64    Value64;
+  NB_CONFIG *pNbConfig;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  if (pNbConfig == NULL) {
+    return  AGESA_WARNING;
+  }
+  if (pNbConfig->sHeader.InitializerID == INITIALIZED_BY_INITIALIZER) {
+    return  AGESA_SUCCESS;
+  }
+  LibAmdMemFill (pNbConfig, 0, sizeof (NB_CONFIG), (AMD_CONFIG_PARAMS *)&(pNbConfig->sHeader));
+  pNbConfig->sHeader.InitializerID = INITIALIZED_BY_INITIALIZER;
+  // Get TOM and TOM2
+  LibAmdMsrRead (0xC001001a, &Value64, (AMD_CONFIG_PARAMS *)pConfig);
+  pNbConfig->SysMemoryTomBelow4G = (UINT16) (Value64 >> 20);
+  LibAmdMsrRead (0xC0010010, &Value64, (AMD_CONFIG_PARAMS *)pConfig);
+  if ((Value64 & BIT21) !=  0) {
+    LibAmdMsrRead (0xC001001d, &Value64, (AMD_CONFIG_PARAMS *)pConfig);
+    pNbConfig->SysMemoryTomAbove4G = (UINT32) (Value64 >> 20);
+  }
+  pNbConfig->P2PMode = 1;
+  pNbConfig->UnitIdClumping = 3;
+  return AGESA_SUCCESS;
+}
+
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbInit.h b/src/vendorcode/amd/cimx/rd890/nbInit.h
new file mode 100644
index 0000000..36a83f8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbInit.h
@@ -0,0 +1,107 @@
+/**
+ * @file
+ *
+ * NB definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBINIT_H_
+#define _NBINIT_H_
+
+
+VOID
+NbLibSetSSID (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+VOID
+NbLibSetupClumping  (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibSetTopOfMemory (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibEarlyPostInitValidateInput (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibPostInitValidateInput (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibPrepareToOS (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+VOID
+NbMultiNbIocInit (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibInitializer (
+  IN OUT  AMD_NB_CONFIG *pConfig
+  );
+
+AGESA_STATUS
+AmdNbInitializer (
+  IN OUT  AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+#ifndef HT_INTERRUPT_ENCODING_OFFSET
+  #define HT_INTERRUPT_ENCODING_OFFSET 0x2
+#endif
+
+VOID
+NbLibSetNmiRouting (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+AGESA_STATUS
+NbLibGetCore0ApicId (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbInitializer.c b/src/vendorcode/amd/cimx/rd890/nbInitializer.c
new file mode 100644
index 0000000..ab4a004
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbInitializer.c
@@ -0,0 +1,133 @@
+/**
+ * @file
+ *
+ *  NB Post Init interfaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbInitializer (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for all NB.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (NbInitializer, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB structure initializer.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbInitializer (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  AGESA_STATUS        Status;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbInitializer Enter\n"));
+  Status = MiscInitializer (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    return  Status;
+  }
+  Status = HtLibInitializer (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    return  Status;
+  }
+  Status = PcieLibInitializer (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    return  Status;
+  }
+  Status = NbLibInitializer (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbInitializer Exit\n"));
+  return  Status;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbInitializer.h b/src/vendorcode/amd/cimx/rd890/nbInitializer.h
new file mode 100644
index 0000000..0ae6d16
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbInitializer.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ *  NB Post Init interfaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _NBINITIALIZER_H_
+#define _NBINITIALIZER_H_
+
+
+AGESA_STATUS
+AmdInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbInitializer (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbInterface.c b/src/vendorcode/amd/cimx/rd890/nbInterface.c
new file mode 100644
index 0000000..7d41b26
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbInterface.c
@@ -0,0 +1,312 @@
+/**
+ * @file
+ *
+ *  NB Post Init interfaces
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Init all NB at early POST.
+ *
+ *
+ *
+  * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdEarlyPostInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (NbEarlyPostInit, ConfigPtr);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Init at early post.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbEarlyPostInit (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbEarlyPostInit Enter\n"));
+
+  Status = NbLibEarlyPostInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  NbLibSetTopOfMemory (NbConfigPtr);
+  NbLibSetupClumping (NbConfigPtr);
+  NbMultiNbIocInit (NbConfigPtr);
+#ifndef EPREADY_WORKAROUND_DISABLED
+  PcieEpReadyWorkaround (NbConfigPtr);
+#endif
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbEarlyPostInit Exit [ %x]\n", Status));
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Init all NB at mid POST.
+ *
+ *
+ *
+  * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdMidPostInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (NbMidPostInit, ConfigPtr);
+#ifndef  IOMMU_SUPPORT_DISABLE
+  NbIommuInit (ConfigPtr);
+#endif
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Init at mid POST.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbMidPostInit (
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMidPostInit Enter\n"));
+  Status = NbLibPostInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  NbLibSetIOAPIC (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMidPostInit Exit [ %x]\n", Status));
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Init all NB at late POST.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdLatePostInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (NbLatePostInit, ConfigPtr);
+#ifndef  IOMMU_SUPPORT_DISABLE
+  NbIommuAcpiFixup (ConfigPtr);
+#endif
+  return  Status;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Init at late post.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbLatePostInit (
+  IN OUT   AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbLatePostInit Enter\n"));
+  Status = NbLibPostInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return Status;
+  }
+  NbLibGetCore0ApicId (NbConfigPtr);
+  NbLibSetNmiRouting (NbConfigPtr);
+  NbLibSetSSID (NbConfigPtr);
+  Status = NbLibPrepareToOS (NbConfigPtr);
+  LibNbSetDefaultIndexes (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbLatePostInit Exit [ %x]\n", Status));
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Init all NB at S3 Resume.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdS3InitIommu (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+
+#ifndef  IOMMU_SUPPORT_DISABLE
+  NbIommuInitS3 (ConfigPtr);
+#endif
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Init all NB at S3 Resume.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdS3Init (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (NbS3Init, ConfigPtr);
+
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Init at S3
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbS3Init (
+  IN OUT   AMD_NB_CONFIG     *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbS3Init Enter\n"));
+  Status = NbLibPostInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return Status;
+  }
+  Status = NbLibSetTopOfMemory (NbConfigPtr);
+  NbLibSetupClumping (NbConfigPtr);
+  NbMultiNbIocInit (NbConfigPtr);
+  NbLibSetSSID (NbConfigPtr);
+  NbLibSetIOAPIC (NbConfigPtr);
+  NbLibSetNmiRouting (NbConfigPtr);
+  Status = NbLibPrepareToOS (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbS3Init Exit [%x]\n", Status));
+  return  Status;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbIoApic.c b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
new file mode 100644
index 0000000..045883d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbIoApic.c
@@ -0,0 +1,194 @@
+/**
+ * @file
+ *
+ * NB IOAPIC Initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*! \var APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[]
+ *  \brief  Default IO APIC interrupt mapping
+ *  \details
+ *  @li Interrupt Info for HT referenced as gDefaultApicDeviceInfoTable[0]
+ *  @li Interrupt Info for IOMMU referenced as gDefaultApicDeviceInfoTable[1]
+ *  @li Interrupt Info for device 2 referenced as gDefaultApicDeviceInfoTable[2]
+ *  @li Interrupt Info for device 3 referenced as gDefaultApicDeviceInfoTable[3]
+ *  @li ...
+ *  @li Interrupt Info for device 13 can be referenced as gDefaultApicDeviceInfoTable[13]
+ */
+CONST APIC_DEVICE_INFO gDefaultApicDeviceInfoTable[] = {
+// Group  Swizzling   Port Int Pin
+  {0,     0,          31},   //HT
+  {0,     0,          31},   //IOMMU
+  {0,     ABCD,       28},   //Dev2  Grp0 [Int - 0..3]
+  {1,     ABCD,       28},   //Dev3  Grp1 [Int - 4..7]
+  {5,     ABCD,       28},   //Dev4  Grp5 [Int - 20..23]
+  {5,     CDAB,       28},   //Dev5  Grp5 [Int - 20..23]
+  {6,     BCDA,       29},   //Dev6  Grp6 [Int - 24..27]
+  {6,     CDAB,       29},   //Dev7  Grp6 [Int - 24..27]
+  {0,     0,          0 },   // Reserved
+  {6,     ABCD,       29},   //Dev9  Grp6 [Int - 24..27]
+  {5,     BCDA,       30},   //Dev10 Grp5 [Int - 20..23]
+  {2,     ABCD,       30},   //Dev11 Grp2 [Int - 8..11]
+  {3,     ABCD,       30},   //Dev12 Grp3 [Int - 12..15]
+  {4,     ABCD,       30}    //Dev13 Grp4 [Int - 16..19]
+};
+
+CONST APIC_REGISTER_INFO gApicRegisterInfoTable[] = {
+  {0,   NB_IOAPICCFG_REG03, 0,  NB_IOAPICCFG_REG06},  //Dev2
+  {8,   NB_IOAPICCFG_REG03, 8,  NB_IOAPICCFG_REG06},  //Dev3
+  {16,  NB_IOAPICCFG_REG03, 16, NB_IOAPICCFG_REG06},  //Dev4
+  {24,  NB_IOAPICCFG_REG03, 24, NB_IOAPICCFG_REG06},  //Dev5
+  {0,   NB_IOAPICCFG_REG04, 0,  NB_IOAPICCFG_REG07},  //Dev6
+  {8,   NB_IOAPICCFG_REG04, 8,  NB_IOAPICCFG_REG07},  //Dev7
+  {0,   0,                  0,  0                 },  //Dev8
+  {16,  NB_IOAPICCFG_REG04, 24 ,NB_IOAPICCFG_REG07},  //Dev9
+  {24,  NB_IOAPICCFG_REG04, 0  ,NB_IOAPICCFG_REG08},  //Dev10
+  {0,   NB_IOAPICCFG_REG05, 8  ,NB_IOAPICCFG_REG08},  //Dev11
+  {8,   NB_IOAPICCFG_REG05, 16 ,NB_IOAPICCFG_REG08},  //Dev12
+  {16,  NB_IOAPICCFG_REG05, 24 ,NB_IOAPICCFG_REG08},  //Dev13
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Configure IO APIC
+ *    Enable IO APIC base address decoding. Enable default forwarding interrupt to SB
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+NbLibSetIOAPIC (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  NB_CONFIG           *pNbConfig;
+  PORT                PortId;
+  APIC_DEVICE_INFO    ApicDeviceInfoTable[sizeof (gDefaultApicDeviceInfoTable) / sizeof (APIC_DEVICE_INFO)];
+  APIC_REGISTER_INFO  *pApicRegisterInfoTable;
+
+  pNbConfig = GET_NB_CONFIG_PTR (pConfig);
+  pApicRegisterInfoTable = (APIC_REGISTER_INFO*)FIX_PTR_ADDR (&gApicRegisterInfoTable[0], NULL);
+  if (pNbConfig->IoApicBaseAddress != 0 ) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "[NB]NbLibSetIOAPIC\n"));
+    //Copy default routing to local memory buffer
+    LibAmdMemCopy (&ApicDeviceInfoTable, (APIC_DEVICE_INFO*)FIX_PTR_ADDR (&gDefaultApicDeviceInfoTable[0], NULL), sizeof (ApicDeviceInfoTable), (AMD_CONFIG_PARAMS *)&(pNbConfig->sHeader));
+    //Callback to platform BIOS to update
+    LibNbCallBack (PHCB_AmdUpdateApicInterruptMapping, (UINTN)&ApicDeviceInfoTable, pConfig);
+    //Setup base address
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    Apic Base %x\n", (UINT32)pNbConfig->IoApicBaseAddress & 0xffffff00));
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX, NB_IOAPICCFG_REG01, AccessS3SaveWidth32, (UINT32) (0xff), (UINT32)pNbConfig->IoApicBaseAddress & 0xffffff00, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX, NB_IOAPICCFG_REG02, AccessS3SaveWidth32, 0x0, ((UINT32*)&pNbConfig->IoApicBaseAddress)[1] , pConfig);
+    //Setup interrupt mapping
+    for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+      PCI_ADDR Port;
+      APIC_REGISTER_INFO RegisterInfo;
+      APIC_DEVICE_INFO  PortInfo;
+      PORT  NativePortId;
+      if (PortId == 8 || !PcieLibIsValidPortId (PortId, pConfig)) {
+        continue;
+      }
+      NativePortId = PcieLibNativePortId (PortId, pConfig);
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      RegisterInfo = pApicRegisterInfoTable[NativePortId - MIN_PORT_ID];
+      PortInfo = ApicDeviceInfoTable[Port.Address.Device];
+      //Setup routing for EP
+      LibNbPciIndexRMW (
+        pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX,
+        RegisterInfo.EpRoutingRegister,
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        (PortInfo.Group | (PortInfo.Swizzle << 4)) << RegisterInfo.EpRoutingOffset,
+        pConfig
+        );
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    EP Routing Dev[%d] NativePortId[%d] PortId[%d] Group - %d Swizzle - %d\n", Port.Address.Device, NativePortId, PortId, PortInfo.Group, PortInfo.Swizzle));
+      //Setup routing for RC
+      LibNbPciIndexRMW (
+        pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX,
+        RegisterInfo.RcRoutingRegister,
+        AccessS3SaveWidth32,
+        0xFFFFFFFF,
+        (PortInfo.Pin) << RegisterInfo.RcRoutingOffset,
+        pConfig
+        );
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    RC Routing Dev[%d] NativeDev[%d] Pin - %d \n", Port.Address.Device, NativePortId, PortInfo.Pin));
+
+    }
+    LibNbPciIndexRMW (
+      pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX,
+      NB_IOAPICCFG_REG09,
+      AccessS3SaveWidth32,
+      0x0,
+      ApicDeviceInfoTable[0].Pin | (ApicDeviceInfoTable[1].Pin << 8),
+      pConfig
+      );
+    //Enable IO API MMIO decoding and configure features
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_IOAPICCFG_INDEX, NB_IOAPICCFG_REG00, AccessS3SaveWidth32, 0x0 , 0x1f , pConfig);
+  }
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbIoApic.h b/src/vendorcode/amd/cimx/rd890/nbIoApic.h
new file mode 100644
index 0000000..f2ba894
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbIoApic.h
@@ -0,0 +1,52 @@
+/**
+ * @file
+ *
+ * NB IOAPIC Initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _NBIOAPIC_H_
+#define _NBIOAPIC_H_
+
+
+VOID
+NbLibSetIOAPIC (
+  IN      AMD_NB_CONFIG  *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbIommu.c b/src/vendorcode/amd/cimx/rd890/nbIommu.c
new file mode 100644
index 0000000..705b1a8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbIommu.c
@@ -0,0 +1,1737 @@
+/**
+ * @file
+ *
+ * Routines for IOMMU.
+ *
+ * Implement the IOMMU init and ACPI feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+#include "amdSbLib.h"
+
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+
+/*----------------------------------------------------------------------------------------
+ *                             R D 8 9 0 / S   D A T A
+ *----------------------------------------------------------------------------------------
+ */
+
+// IOMMU Initialization
+
+INDIRECT_REG_ENTRY
+CONST
+STATIC
+IommuL1Table[] = {
+  // 01.  0x0C [30:28]=7  L1VirtOrderQueues     Increase maximum number virtual queues
+  //                                            for all devices
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP1  | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP2  | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_SB    | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3A | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3B | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_VC1   | L1REG_0C, 0x8FFFFFFF, 0x70000000 },
+  // 02.  0x07 [11]        L1DEBUG_1            Multiple error logs possible
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP1  | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP2  | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5},
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_SB    | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5},
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3A | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5},
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3B | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5},
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_VC1   | L1REG_07, (UINT32)~(BIT8 + BIT9 + BIT10), BIT11 + BIT5},
+  // 02.  0x06 [0]        L1DEBUG_0             Phantom function disable
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP1  | L1REG_06, (UINT32)~BIT0, 0 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP2  | L1REG_06, (UINT32)~BIT0, 0 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_SB    | L1REG_06, (UINT32)~BIT0, 0 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3A | L1REG_06, (UINT32)~BIT0, 0 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_GPP3B | L1REG_06, (UINT32)~BIT0, 0 },
+  { L1CFG_SEL_WR_EN | L1CFG_SEL_VC1   | L1REG_06, (UINT32)~BIT0, 0 }
+};
+
+INDIRECT_REG_ENTRY
+CONST
+STATIC
+IommuL2Table[] = {
+  // 01.  0x0C [29]=1    IFifoClientPriority    Set attribute to VC1 L1 client high priority
+  { L2CFG_SEL_WR_EN | L2REG_0C,    0xD0000000,  0x20000000 },
+  // 02.  0x10 [9:8]=2   DTCInvalidationSel     DTC cache invalidation sequential precise
+  { L2CFG_SEL_WR_EN | L2REG_10,    0xFFFFFC00,  0x00000200 },
+  // 03.  0x14 [9:8]=2   ITCInvalidationSel     ... cache invalidation sequential precise
+  { L2CFG_SEL_WR_EN | L2REG_14,    0xFFFFFC00,  0x00000200 },
+  // 04.  0x18 [9:8]=2   IPTCAInvalidationSel   ... cache invalidation sequential precise
+  { L2CFG_SEL_WR_EN | L2REG_18,    0xFFFFFC00,  0x00000200 },
+  // 05.  0x1C [9:8]=2   IPTCBInvalidationSel   ... cache invalidation sequential precise
+  { L2CFG_SEL_WR_EN | L2REG_1C,    0xFFFFFC00,  0x00000200 },
+  // 06.  0x50 [9:8]=2   PDCInvalidationSel     ... cache invalidation sequential precise
+  { L2CFG_SEL_WR_EN | L2REG_50,    0xFFFFFC00,  0x00000200 },
+  // 07.  0x10 [4]=1     DTCParityEn            DTC cache parity protection
+  { L2CFG_SEL_WR_EN | L2REG_10,    (UINT32)~BIT4,       BIT4       },
+  // 08.  0x14 [4]=1     ITCParityEn            ... cache parity protection
+  { L2CFG_SEL_WR_EN | L2REG_14,    (UINT32)~BIT4,       BIT4       },
+  // 09.  0x18 [4]=1     PTCAParityEn           ... cache parity protection
+  { L2CFG_SEL_WR_EN | L2REG_18,    (UINT32)~BIT4,       BIT4       },
+  // 10. 0x1C [4]=1      PTCBParityEn           ... cache parity protection
+  { L2CFG_SEL_WR_EN | L2REG_1C,    (UINT32)~BIT4,       BIT4       },
+  // 11. 0x50 [4]=1      PDCParityEn            ... cache parity protection
+  { L2CFG_SEL_WR_EN | L2REG_50,    (UINT32)~BIT4,       BIT4       },
+  // 12. 0x80 [0]=1      ERRRuleLock0           Lock fault detection rule sets
+  //     0x30 [0]=1      ERRRuleLock1
+  { L2CFG_SEL_WR_EN | L2REG_80,    (UINT32)~BIT0,       BIT0       },
+  { L2CFG_SEL_WR_EN | L2REG_30,    (UINT32)~BIT0,       BIT0       },
+  // 13. 0x56 [2]=0      L2_CP_CONTROL          Disable CP flush on invalidation
+  //     0x56 [1]=1      L2_CP_CONTROL          Enable CP flush on wait
+  { L2CFG_SEL_WR_EN | L2REG_56,    0xFFFFFFF9,  BIT1       },
+  // A21
+  { L2CFG_SEL_WR_EN | L2REG_06,    0xFFFFFFFF,  BIT6 + BIT7 + BIT5 + BIT8 },
+  { L2CFG_SEL_WR_EN | L2REG_47,    0xFFFFFFFF,  BIT1 + BIT3 + BIT0 + BIT4 + BIT5 },
+  { L2CFG_SEL_WR_EN | L2REG_07,    0xFFFFFFFF,  BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT8 + BIT6},
+
+};
+
+// IOMMU ACPI Initialization
+
+IOMMU_IVRS_HEADER
+STATIC
+RD890S_DfltHeader = {
+//  'SRVI',
+  Int32FromChar ('S', 'R', 'V', 'I'),
+  48,
+  1,
+  0,
+  {'A', 'M', 'D', ' ', ' ', 0},
+  {'R', 'D', '8', '9', '0', 'S', 0, 0},
+  {'1', ' ', ' ', 0},
+  {'A','M','D',' '},
+  {'1', ' ', ' ', 0},
+  0,
+  0
+};
+
+IOMMU_EXCLUSIONTABLE
+STATIC
+RD890S_DfltExclusion = {
+  sizeof (UINTN) + sizeof (IOMMU_EXCLUSIONRANGE) * 0,
+  {{0, 0}}
+};
+
+IOMMU_DEVICELIST
+STATIC
+RD890S_DfltDevices = {
+  (sizeof (UINT16) + sizeof (UINT16) * 12),
+  {
+    DEVICEID_NB,                            // Type 2 entry, Device 0, Func 0 <-- NB all functions
+    DEVICEID_GPP1_0,                        // Type 2 entry, Device 2, Func 0 <-- GPP1 port 0
+    DEVICEID_GPP1_1,                        // Type 2 entry, Device 3, Func 0 <-- GPP1 port 1
+    DEVICEID_GPP3A_0,                       // Type 2 entry, Device 4, Func 0 <-- GPP3a port 0
+    DEVICEID_GPP3A_1,                       // Type 2 entry, Device 5, Func 0 <-- GPP3a port 1
+    DEVICEID_GPP3A_2,                       // Type 2 entry, Device 6, Func 0 <-- GPP3a port 2
+    DEVICEID_GPP3A_3,                       // Type 2 entry, Device 7, Func 0 <-- GPP3a port 3
+    DEVICEID_GPP3A_4,                       // Type 2 entry, Device 9, Func 0 <-- GPP3a port 4
+    DEVICEID_GPP3A_5,                       // Type 2 entry, Device A, Func 0 <-- GPP3a port 5
+    DEVICEID_GPP2_0,                        // Type 2 entry, Device B, Func 0 <-- GPP2 port 0
+    DEVICEID_GPP2_1,                        // Type 2 entry, Device C, Func 0 <-- GPP2 port 1
+    DEVICEID_GPP3B_0,                       // Type 2 entry, Device D, Func 0 <-- GPP3b port 0
+  }
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+*/
+
+// IOMMU Library
+
+BOOLEAN
+NbIommuEnabled (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  );
+
+BOOLEAN
+IommuCheckEnable (
+  IN       PCI_ADDR           IommuPciAddress,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+BOOLEAN
+IommuCheckHp (
+  IN       UINT16             DeviceId,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+BOOLEAN
+IommuCheckPhantom (
+  IN       UINT16             DeviceId,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+UINT32
+IommuGetL1 (
+  IN       UINT16             DeviceId
+  );
+
+UINT8
+IommuGetLog2 (
+  IN       UINT32             Value
+  );
+
+VOID
+IommuRecordBusDevFuncInfo (
+  IN OUT  IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN      UINT16             DeviceId,
+  IN      AMD_NB_CONFIG      *pConfig
+  );
+
+
+AGESA_STATUS
+IommuInit (
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuInitL2CacheControl (
+  IN       IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+);
+
+VOID
+IommuPlaceHeader (
+  IN OUT   VOID               *BufferPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuPlaceIvhdAndScanDevices (
+  IN OUT   VOID               *BufferPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuPlaceIvmdAndExclusions (
+  IN OUT   VOID               *BufferPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuIvhdNorthbridgeDevices (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuIvhdSouthbridgeDevices (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuIvhdApicsAndHpets (
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuCreateDeviceEntry (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN       UINT16             DeviceId,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+IommuCreate4ByteEntry (
+  IN       UINT8            Type,
+  IN       UINT8            Data,
+  IN       UINT16           Word1,
+  IN OUT   IOMMU_IVHD_ENTRY *IvhdPtr
+  );
+
+VOID
+IommuCreate8ByteEntry (
+  IN       UINT8            Type,
+  IN       UINT8            Data,
+  IN       UINT16           Word1,
+  IN       UINT8            Byte4,
+  IN       UINT16           Word5,
+  IN       UINT8            Byte7,
+  IN OUT   IOMMU_IVHD_ENTRY *IvhdPtr
+  );
+
+VOID
+IommuFinalizeIvrs (
+  IN OUT   VOID               *BufferPtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+// IOMMU ACPI Final
+
+UINT64
+IommuGetApicBaseAddress (
+  IN       VOID               *DevicePtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+UINT8
+IommuGetApicId (
+  IN       UINT64             BaseAddress,
+  IN       VOID               *MadtPtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+AGESA_STATUS
+NbIommuHwInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  );
+
+AGESA_STATUS
+NbIommuHwTopologyInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  );
+
+AGESA_STATUS
+IommuTopologyInit (
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                             E X P O R T E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU enable on platform
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_UNSUPPORTED IOMMU not enabled or not found
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+BOOLEAN
+NbIommuEnabled (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  UINT8             NorthbridgeId;
+  BOOLEAN           Result;
+  Result = FALSE;
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    if (ConfigPtr->Northbridges[NorthbridgeId].pNbConfig->IommuBaseAddress != 0) {
+      Result = TRUE;
+      break;
+    }
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu Initialization for all NB in system.
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_UNSUPPORTED IOMMU not enabled or not found
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+AGESA_STATUS
+NbIommuInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  AGESA_STATUS      Status;
+
+  Status = AGESA_SUCCESS;
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuInit Enter\n"));
+
+  if (NbIommuEnabled (ConfigPtr)) {
+    NbIommuHwInit (ConfigPtr);
+    NbIommuAcpiInit (ConfigPtr);
+    NbIommuHwTopologyInit (ConfigPtr);
+  } else {
+    Status = AGESA_UNSUPPORTED;
+  }
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuInit Exit [Status = 0x%x]\n", Status));
+  return Status;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu Initialization for all NB in system.
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_UNSUPPORTED IOMMU not enabled or not found
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+AGESA_STATUS
+NbIommuInitS3 (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  AGESA_STATUS      Status;
+
+  Status = AGESA_SUCCESS;
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuInitS3 Enter\n"));
+
+  if (NbIommuEnabled (ConfigPtr)) {
+    NbIommuHwInit (ConfigPtr);
+    NbIommuHwTopologyInit (ConfigPtr);
+  } else {
+    Status = AGESA_UNSUPPORTED;
+  }
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuInitS3 Exit [Status = 0x%x]\n", Status));
+  return Status;
+}
+
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu HW Initialization for all NB in system.
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+AGESA_STATUS
+NbIommuHwInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  UINT8             NorthbridgeId;
+  AMD_NB_CONFIG     *pConfig;
+
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    pConfig = &ConfigPtr->Northbridges[NorthbridgeId];
+    ConfigPtr->CurrentNorthbridge = NorthbridgeId;
+    IommuInit (pConfig);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu HW Initialization for all NB in system.
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+AGESA_STATUS
+NbIommuHwTopologyInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  UINT8             NorthbridgeId;
+  AMD_NB_CONFIG     *pConfig;
+
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    pConfig = &ConfigPtr->Northbridges[NorthbridgeId];
+    ConfigPtr->CurrentNorthbridge = NorthbridgeId;
+    IommuTopologyInit (pConfig);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu Initialization for all NB in system.
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS     IOMMU initialized and table created
+ * @retval    AGESA_UNSUPPORTED IOMMU not enabled or not found
+ * @retval    AGESA_ERROR       IOMMU initialization failed.
+ *
+ */
+AGESA_STATUS
+NbIommuAcpiInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  UINT8             NorthbridgeId;
+  AGESA_STATUS      Status;
+  AMD_NB_CONFIG     *pConfig;
+  NB_BUFFER_PARAMS  Ivrs;
+  UINTN             IvrsHandle;
+
+  Status = AGESA_SUCCESS;
+  Ivrs.BufferLength = 0;
+  Ivrs.BufferHandle = IVRS_HANDLE;
+  Ivrs.BufferPtr = NULL;
+  pConfig = &ConfigPtr->Northbridges[0];
+  ConfigPtr->CurrentNorthbridge = 0;
+  IvrsHandle = 0;
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiInit Enter\n"));
+
+  // Get a buffer for IVRS
+  Ivrs.BufferLength = IVRS_BUFFER_SIZE;
+  Status = LibNbCallBack (PHCB_AmdAllocateBuffer, (UINTN)&Ivrs, &ConfigPtr->Northbridges[0]);
+  if (Status != AGESA_SUCCESS || Ivrs.BufferPtr == NULL) {
+    // Table creation failed
+    return AGESA_ERROR;
+  }
+
+  // Clear buffer before using
+  LibAmdMemFill (Ivrs.BufferPtr, 0, Ivrs.BufferLength, (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+
+  // PLACE OUR ACPI IVRS TABLE
+  // 1. Create IVRS header
+  // 2. For each northbridge place IVHD
+  // 3. For northbridge 0 only, place IVMD exclusion entries
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    pConfig = &ConfigPtr->Northbridges[NorthbridgeId];
+    ConfigPtr->CurrentNorthbridge = NorthbridgeId;
+    if (NorthbridgeId == 0) {
+      IommuPlaceHeader (Ivrs.BufferPtr, pConfig);
+    }
+    IommuPlaceIvhdAndScanDevices (Ivrs.BufferPtr, pConfig);
+    IommuPlaceIvmdAndExclusions (Ivrs.BufferPtr, pConfig);
+  }
+  IommuFinalizeIvrs (Ivrs.BufferPtr, pConfig);
+
+  LibAmdSetAcpiTable (Ivrs.BufferPtr, TRUE, &IvrsHandle);
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiInit [IVRS TableAddress = 0x%x]\n", (UINT32)(Ivrs.BufferPtr)));
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiInit Exit [Status = 0x%x]\n", Status));
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Iommu IVRS fixup for APICS
+ *
+ * @param[in] ConfigPtr  Northbridges configuration block pointer.
+ * @retval    AGESA_SUCCESS    IOMMU initialized and table patched, or no patching required
+ * @retval    AGESA_ERROR      IOMMU enabled but no previously generated IVRC table found.
+ *
+ */
+AGESA_STATUS
+NbIommuAcpiFixup (
+  IN OUT   AMD_NB_CONFIG_BLOCK  *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  UINT8         ApicId;
+  UINT64        ApicBaseAddress;
+  UINT8         NorthbridgeId;
+  BOOLEAN       IommuFound;
+  VOID          *DevicePtr;
+  VOID          *IvhdPtr;
+  VOID          *IvrsPtr;
+  VOID          *MadtPtr;
+  AMD_NB_CONFIG *pConfig;
+  PCI_ADDR      IommuPciAddress;
+  UINTN         IvrsHandle;
+
+
+  pConfig = &ConfigPtr->Northbridges[0];
+  IommuFound = FALSE;
+  ApicId = 0xFF;
+  ApicBaseAddress = 0;
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiFixup Enter\n"));
+
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    pConfig = &ConfigPtr->Northbridges[NorthbridgeId];
+    ConfigPtr->CurrentNorthbridge = NorthbridgeId;
+    IommuPciAddress = pConfig->NbPciAddress;
+    IommuPciAddress.Address.Function = NB_IOMMU;
+    if (IommuCheckEnable (IommuPciAddress, pConfig)) {
+      IommuFound = TRUE;
+    }
+  }
+
+  // Any Iommus enabled?  If no, we don't need to patch anything
+  if (!IommuFound) {
+    return AGESA_SUCCESS;
+  }
+
+  // Check for an IVRS
+  // Check IVRS for a type 10 block (IVHD)
+  // Check for an MADT
+  // If these conditions fail, abort
+
+//  Status = LibAmdGetAcpiTable ('SRVI', &IvrsPtr, &IvrsHandle);
+  Status = LibAmdGetAcpiTable (Int32FromChar ('S', 'R', 'V', 'I'), &IvrsPtr, &IvrsHandle);
+  if (Status != AGESA_SUCCESS) {
+//    REPORT_EVENT (AGESA_ERROR, GENERAL_ERROR_LOCATE_ACPI_TABLE, 'SRVI', 0, 0, 0, pConfig);
+    REPORT_EVENT (AGESA_ERROR, GENERAL_ERROR_LOCATE_ACPI_TABLE, Int32FromChar ('S', 'R', 'V', 'I'), 0, 0, 0, pConfig);
+    return AGESA_ERROR;
+  }
+
+//  Status = LibAmdGetAcpiTable ('CIPA', &MadtPtr, NULL);
+  Status = LibAmdGetAcpiTable (Int32FromChar ('C', 'I', 'P', 'A'), &MadtPtr, NULL);
+  if (Status != AGESA_SUCCESS) {
+//    REPORT_EVENT (AGESA_ERROR, GENERAL_ERROR_LOCATE_ACPI_TABLE, 'CIPA', 0, 0, 0, pConfig);
+    REPORT_EVENT (AGESA_ERROR, GENERAL_ERROR_LOCATE_ACPI_TABLE, Int32FromChar ('C', 'I', 'P', 'A'), 0, 0, 0, pConfig);
+    return AGESA_ERROR;
+  }
+
+  IvhdPtr = LibAmdGetFirstIvrsBlockEntry (TYPE_IVHD, IvrsPtr);
+  if (IvhdPtr == NULL) {
+    return AGESA_ERROR;
+  }
+
+  // An IVRS can contain one or more IVHD entries (one per IOMMU)
+  // Each IVHD entry can contain one or more APIC entries
+
+  while (IvhdPtr != NULL) {
+    DevicePtr = LibAmdGetFirstDeviceEntry (DE_SPECIAL, IvhdPtr);
+    do {
+      // Be sure to only fix APIC entries
+      if (*(UINT8*) ((UINT8*)DevicePtr + DE_SPECIAL_VARIETY) == VARIETY_IOAPIC) {
+        ApicBaseAddress = IommuGetApicBaseAddress (DevicePtr, pConfig);
+        ApicId = IommuGetApicId (ApicBaseAddress, MadtPtr, pConfig);
+        *(UINT8*)((UINT8*)DevicePtr + DE_SPECIAL_ID) = ApicId;
+      }
+      DevicePtr = LibAmdGetNextDeviceEntry (DE_SPECIAL, DevicePtr, IvhdPtr);
+    } while (DevicePtr != NULL);
+
+    IvhdPtr = LibAmdGetNextIvrsBlockEntry (TYPE_IVHD, IvhdPtr, IvrsPtr);
+  }
+
+  LibAmdSetAcpiTable (IvrsPtr, TRUE, &IvrsHandle);
+
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiFixup [IVRS TableAddress = 0x%x]\n", (UINT32)IvrsPtr));
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiFixup [APIC TableAddress = 0x%x]\n", (UINT32)MadtPtr));
+  CIMX_TRACE ((TRACE_DATA (ConfigPtr, CIMX_NB_TRACE), "[NBIOMMU]NbIommuAcpiFixup Exit\n"));
+
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------
+ *                             P R I V A T E
+ *----------------------------------------------------------------------------------------
+ */
+UINT32  IommuMmioInitTable[] = {
+  0x8,    0x0,
+  0xC,    0x08000000,
+  0x10,   0x0,
+  0x14,   0x08000000,
+  0x2000, 0x0,
+  0x2008, 0x0
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Nb Iommu Initialization.
+ *
+ * @param[in] pConfig       Northbridge configuration pointer
+ * @retval    AGESA_SUCCESS     IOMMU enable and initialized succesfully.
+ * @retval    AGESA_UNSUPPORTED IOMMU not initialized.
+ */
+AGESA_STATUS
+IommuInit (
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT8     CapBase;
+  PCI_ADDR  IommuPciAddress;
+  UINTN     i;
+
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+
+  // If the base address = 0, don't enable IOMMU
+  if (pConfig->pNbConfig->IommuBaseAddress == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  // NBMISCIND:0x75 IOC_FEATURE_CNTL_10_0[10]=1
+  // 0=disable
+  // 1=enable
+
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG75, AccessS3SaveWidth32, (UINT32)~(BIT28), BIT0, pConfig);
+
+  // Get Capabilities pointer 32h (points to 40h) - capability ID 0x0F.  Not found, we have no IOMMU.
+  CapBase = LibNbFindPciCapability (IommuPciAddress.AddressValue, IOMMU_CAPID, pConfig);
+  if (CapBase == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+
+  // IOMMU_ADAPTER_ID_W - RW - 32 bits - nbconfigfunc2:0x68
+  // SUBSYSTEM_VENDOR_ID_W 15:0 0x0 Sets the subsystem vendor ID register header
+  // SUBSYSTEM_ID_W 31:16 0x0 Sets the subsystem ID register in the configuration header
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "[NBIOMMU]Iommu Device Found [PCI Address = 0x%x]\n", IommuPciAddress.AddressValue));
+  if (pConfig->pNbConfig->SSID == PCI_INVALID) {
+    LibNbPciRead (IommuPciAddress.AddressValue, AccessWidth32, &pConfig->pNbConfig->SSID, pConfig);
+  }
+  if (pConfig->pNbConfig->SSID) {
+    LibNbPciWrite (IommuPciAddress.AddressValue | 0x68, AccessS3SaveWidth32, &pConfig->pNbConfig->SSID, pConfig);
+  }
+
+  // Get Capabilities pointer 32h (points to 40h) - capability ID 0x0F
+  // Set Cap_Offset+04h [31:14] Base Address Low [31:14]
+  // Set Cap_Offset+08h [31:0] Base Address High [64:32]
+  // Set Cap_Offset+04h [0] Enable
+  LibNbPciRMW ((IommuPciAddress.AddressValue | (CapBase + 8)), AccessS3SaveWidth32, 0x0, ((UINT32*)&pConfig->pNbConfig->IommuBaseAddress)[1], pConfig);
+  LibNbPciRMW ((IommuPciAddress.AddressValue | (CapBase + 4)), AccessS3SaveWidth32, 0x0, ((UINT32*)&pConfig->pNbConfig->IommuBaseAddress)[0], pConfig);
+
+  // Enable zeroing of address for zero-byte reads when IOMMU enabled
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG01, AccessS3SaveWidth32, (UINT32)~(BIT8 | BIT9), BIT8, pConfig);
+
+  // 8.3.1 L1 Initialization
+  LibNbIndirectTableInit (IommuPciAddress.AddressValue | L1CFG_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR(&IommuL1Table[0],NULL),
+    (sizeof (IommuL1Table) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+
+  // 8.3.3.1 L2 Common Initialization
+  LibNbIndirectTableInit (IommuPciAddress.AddressValue | L2CFG_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR(&IommuL2Table[0], NULL),
+    (sizeof (IommuL2Table) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+  //Configure PDC cache to 12-way set associative cache for A21
+  if (LibNbGetRevisionInfo (pConfig).Revision > NB_REV_A11) {
+    LibNbPciIndexRMW (IommuPciAddress.AddressValue | L2CFG_INDEX, L2CFG_SEL_WR_EN | L2REG_52, AccessS3SaveWidth32, 0x0, 0xF0000002 , pConfig);
+  }
+  // Start and lock the Iommu settings
+  LibNbPciRMW ((IommuPciAddress.AddressValue | (CapBase + 4)), AccessS3SaveWidth32, 0xFFFFFFFF, (UINT32)BIT0, pConfig);
+
+  //Reset IOMMU MMIO registers on system reset
+  for (i = 0; i < (sizeof (IommuMmioInitTable) / sizeof (UINT32)); i = i + 2) {
+    LibNbMemRMW (pConfig->pNbConfig->IommuBaseAddress + IommuMmioInitTable[i], AccessS3SaveWidth32, 0x0, IommuMmioInitTable[i + 1], pConfig);
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Iommu Initialization of topology specific data.
+ *
+ * @param[in] pConfig       Northbridge configuration pointer
+ * @retval    AGESA_SUCCESS     IOMMU enable and initialized succesfully.
+ * @retval    AGESA_UNSUPPORTED IOMMU not initialized.
+ */
+AGESA_STATUS
+IommuTopologyInit (
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  )
+{
+  // Set L2 Caches Hash Control based on maximum bus, device, function
+  IommuInitL2CacheControl ((IOMMU_PCI_TOPOLOGY*) &pConfig->pNbConfig->IommuTpologyInfo, pConfig);
+  return AGESA_SUCCESS;
+}
+
+L2_HASH_CONTROL HashControls[] = {
+  {
+    L2_DTC_CONTROL
+  },
+  {
+    L2_ITC_CONTROL
+  },
+  {
+    L2_PTC_A_CONTROL
+  },
+  {
+    L2_PTC_B_CONTROL
+  },
+  {
+    L2_PDC_CONTROL
+  }
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set L2 Cache Hash Control based on maximum Bus, Dev, Function found
+ *
+ * @param[in] PciPtr            Array of bus, device, function
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ */
+VOID
+IommuInitL2CacheControl (
+  IN       IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT32    Value;
+  PCI_ADDR  IommuPciAddress;
+  UINTN     i;
+  UINT8     FuncBitsUsed;
+  UINT8     DevBitsUsed;
+  UINT8     BusBitsUsed;
+
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    L2Cache Init Max Bus = 0x%x Max Device = 0x%x Mux Func = 0x%x\n", PciPtr->MaxBus, PciPtr->MaxDevice, PciPtr->MaxFunction));
+
+  FuncBitsUsed = CIMX_MAX (IommuGetLog2 (PciPtr->MaxFunction + 1), 3);
+  DevBitsUsed = IommuGetLog2 (PciPtr->MaxDevice + 1);
+  BusBitsUsed = IommuGetLog2 (PciPtr->MaxBus + 1);
+
+  for (i = 0; i < (sizeof (HashControls) / sizeof (L2_HASH_CONTROL)); i++) {
+    UINT8 NBits;
+    UINT8 NFuncBits;
+    UINT8 NDevBits;
+    UINT8 NBusBits;
+    LibNbPciIndexRead (IommuPciAddress.AddressValue | L2CFG_INDEX, L2CFG_SEL_WR_EN | HashControls[i].HashControl, AccessWidth32, &Value, pConfig);
+    NBits = (UINT8) (Value >> 28) - IommuGetLog2 ((Value >> 16) & 0xff);
+    NFuncBits = CIMX_MIN (NBits, 0x3);
+    NBits = NBits - NFuncBits;
+    NDevBits = CIMX_MIN ( NBits, DevBitsUsed + FuncBitsUsed - NFuncBits);
+    NBusBits = NBits - NDevBits;
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    NBusBits = %d, NDevBits = %d, NFuncBits = %d  \n", NBusBits, NDevBits, NFuncBits));
+    LibNbPciIndexRMW (
+      IommuPciAddress.AddressValue | L2CFG_INDEX,
+      L2CFG_SEL_WR_EN | (HashControls[i].HashControl + 1),
+      AccessS3SaveWidth32,
+      0xFFFFFE00,
+      (NFuncBits | (NDevBits << 2) | (NBusBits << 5)) & 0x1FF,
+      pConfig
+      );
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check to see if current PCI Address is an IOMMU
+ *
+ * @param[in] IommuPciAddress   PCI Address to check
+ * @param[in] pConfig           Northbridge configuration structure pointer.
+ * @retval                      TRUE if Iommu is enabled and found
+ */
+BOOLEAN
+IommuCheckEnable (
+  IN      PCI_ADDR       IommuPciAddress,
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT8 CapBase;
+
+  if (pConfig->pNbConfig->IommuBaseAddress == 0x0) {
+    return FALSE;
+  }
+  CapBase = LibNbFindPciCapability (IommuPciAddress.AddressValue, IOMMU_CAPID, pConfig);
+  if (CapBase == 0) {
+    return FALSE;
+  } else {
+    return TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check an RD890 PCIE bridge to see if hot plug is enabled
+ *
+ * @param[in] DeviceId  Device Id to check
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ * @retval    TRUE      if current device supports hotplug
+ */
+BOOLEAN
+IommuCheckHp (
+  IN      UINT16         DeviceId,
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT32    PciData;
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, DeviceId & 0x7, 0);
+
+  LibNbPciRead (PciAddress.AddressValue | NB_PCIP_REG6C, AccessWidth32, &PciData, pConfig);
+
+  // Check for hot plug by reading PCIE_SLOT_CAP pcieConfigDev[13:2]:0x6C [6] HOTPLUG_CAPABLE
+  PciData &= BIT6;
+  if (PciData != 0) {
+    return TRUE;
+  } else {
+    return FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check a PCIE device to see if it supports phantom functions
+ *
+ * @param[in] DeviceId  Device Id to check
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ * @retval    TRUE      if current device supports phantom functions
+ */
+BOOLEAN
+IommuCheckPhantom (
+  IN      UINT16         DeviceId,
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT32    PciData;
+  UINT8     PcieCapBase;
+  PCI_ADDR  PciAddress;
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, DeviceId & 0x7, 0);
+
+  // Check for phantom functions by reading PCIE Device Capabilities register (base + 4) [4:3] 0 = not supported
+  PcieCapBase = LibNbFindPciCapability (PciAddress.AddressValue, PCIE_CAPID, pConfig);
+  if (PcieCapBase != 0) {
+    LibNbPciRead (((PciAddress.AddressValue) | (PcieCapBase + 4)), AccessWidth32, &PciData, pConfig);
+    PciData &= PCIE_PHANTOMMASK;
+    if (PciData != 0) {
+      return TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check to see if current PCI Address is a multi-port PCIE core
+ *
+ * @param[in] DeviceId  16-bit device id to check
+ * @retval              L1 configuration select
+ */
+UINT32
+IommuGetL1 (
+  IN       UINT16 DeviceId
+  )
+{
+  // This function translates an RD890 multi-port pci core to the offset of the L1 entry
+  // corresponding to it.  An unknown device returns as invalid
+  switch (DeviceId) {
+  case DEVICEID_GPP1_0 :
+    return L1CFG_SEL_GPP1;
+  case DEVICEID_GPP1_1 :
+    return L1CFG_SEL_GPP1;
+  case DEVICEID_GPP2_0 :
+    return L1CFG_SEL_GPP2;
+  case DEVICEID_GPP2_1 :
+    return L1CFG_SEL_GPP2;
+  case DEVICEID_GPP3A_0 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3A_1 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3A_2 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3A_3 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3A_4 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3A_5 :
+    return L1CFG_SEL_GPP3A;
+  case DEVICEID_GPP3B_0 :
+    return L1CFG_SEL_GPP3B;
+  default:
+    return PCI_INVALID;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD Device Entries
+ *
+ * @param[in] Value Value to find the logarithm of
+ * @retval          Logarithm of input Value
+ */
+UINT8
+IommuGetLog2 (
+  IN       UINT32 Value
+  )
+{
+  UINT8 Result;
+
+  Result = 0;
+
+  // This code will round a 32bit value to the next highest power of 2
+  Value--;
+  Value |= Value >> 1;
+  Value |= Value >> 2;
+  Value |= Value >> 4;
+  Value |= Value >> 8;
+  Value |= Value >> 16;
+  Value++;
+
+  // Calculate the logarithm
+  while (Value >>= 1) {
+    Result++;
+  }
+
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVRS Header for IOMMU ACPI table
+ *
+ * @param[in, out]  BufferPtr   Pointer to buffer to return IVRS.
+ * @param[in]       pConfig     Northbridge configuration structure pointer.
+ */
+VOID
+IommuPlaceHeader (
+  IN OUT   VOID           *BufferPtr,
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  )
+{
+  IOMMU_IVRS_HEADER *HeaderPtr;
+  HeaderPtr = (IOMMU_IVRS_HEADER *)BufferPtr;
+  LibAmdMemCopy (HeaderPtr, &RD890S_DfltHeader, sizeof (IOMMU_IVRS_HEADER), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVMD (memory device) Create all IVMD entries for a single exclusion table
+ *
+ * @param[in, out]  BufferPtr Pointer to text buffer to return IVRS
+ * @param[in]       pConfig   Northbridge configuration pointer
+ */
+VOID
+IommuPlaceIvmdAndExclusions (
+  IN OUT   VOID           *BufferPtr,
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT8                 EntryCount;
+  UINT8                 CurrentExclusion;
+  AGESA_STATUS          Status;
+  IOMMU_EXCLUSIONTABLE  *pExclusion;
+  IOMMU_IVRS_HEADER     *HeaderPtr;
+  IOMMU_IVMD_ENTRY      *IvmdPtr;
+
+  pExclusion = &RD890S_DfltExclusion;
+  HeaderPtr = (IOMMU_IVRS_HEADER *)BufferPtr;
+  IvmdPtr = (IOMMU_IVMD_ENTRY *)BufferPtr;
+
+  Status = LibNbCallBack (PHCB_AmdGetExclusionTable, (UINTN)&pExclusion, pConfig);
+  if (Status == AGESA_SUCCESS) {
+    EntryCount = (UINT8) ((pExclusion->TableLength - sizeof (UINTN)) / sizeof (IOMMU_EXCLUSIONRANGE));
+    for (CurrentExclusion = 0; CurrentExclusion < EntryCount; CurrentExclusion++) {
+      IvmdPtr = (IOMMU_IVMD_ENTRY*) ((UINT8*)HeaderPtr + HeaderPtr->Length);
+      IvmdPtr->Type = TYPE_IVMD_ALL;    // 20h = All peripherals
+      IvmdPtr->Flags = 0x7;             // Exclusion range
+      IvmdPtr->Length = 32;             // 32 byte structure
+      IvmdPtr->DeviceId = 0;            // Reserved for type 20h
+      IvmdPtr->AuxData = 0;             // Reserved for type 20h
+      IvmdPtr->Reserved = 0;
+      IvmdPtr->BlockStartAddress = pExclusion->ExclusionRange[CurrentExclusion].Start;
+      IvmdPtr->BlockLength = pExclusion->ExclusionRange[CurrentExclusion].Length;
+      HeaderPtr->Length += 32;          // Update size of IVRS
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD (hardware device) Entry for IOMMU ACPI table
+ *
+ * @param[in, out]  BufferPtr Pointer to text buffer to return IVRS
+ * @param[in]       pConfig   Northbridge configuration pointer
+ */
+VOID
+IommuPlaceIvhdAndScanDevices (
+  IN OUT   VOID           *BufferPtr,
+  IN OUT   AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT32              Value;
+  IOMMU_PCI_TOPOLOGY  PciFlags;
+  IOMMU_IVRS_HEADER   *HeaderPtr;
+  IOMMU_IVHD_ENTRY    *IvhdPtr;
+  PCI_ADDR            IommuPciAddress;
+
+  HeaderPtr = (IOMMU_IVRS_HEADER *)BufferPtr;
+  IvhdPtr = (IOMMU_IVHD_ENTRY *)BufferPtr;
+  //PciFlags.PhantomFunction = FALSE;
+  PciFlags.MaxBus = 0;
+  PciFlags.MaxDevice = 0;
+  PciFlags.MaxFunction = 0;
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+
+  IvhdPtr = (IOMMU_IVHD_ENTRY*) ((UINT8*)HeaderPtr + HeaderPtr->Length);
+  IvhdPtr->Type = TYPE_IVHD;        // Hardware block
+  IvhdPtr->Flags = FLAGS_COHERENT | FLAGS_IOTLBSUP | FLAGS_ISOC | FLAGS_RESPASSPW | FLAGS_PASSPW;
+  IvhdPtr->Length = 24;             // Length = 24 with no devices
+  IvhdPtr->DeviceId = (UINT16)((IommuPciAddress.AddressValue >> 12) & 0xFFFF); // Change 32 bit ID into 16 bit
+  IvhdPtr->CapabilityOffset = (UINT16) (LibNbFindPciCapability (IommuPciAddress.AddressValue, IOMMU_CAPID, pConfig));
+  IvhdPtr->BaseAddress = pConfig->pNbConfig->IommuBaseAddress;
+  IvhdPtr->PciSegment = 0;
+  LibNbPciRead (IommuPciAddress.AddressValue | (IvhdPtr->CapabilityOffset + 0x10), AccessWidth32, &Value, pConfig);
+  IvhdPtr->IommuInfo = (UINT16)(Value & 0x1f); //Set MSInum.
+  IvhdPtr->IommuInfo |= ((0x13) << 8); //set UnitID
+  IvhdPtr->Reserved = 0;
+
+  IommuIvhdNorthbridgeDevices (&PciFlags, IvhdPtr, pConfig);
+  if (IommuPciAddress.Address.Bus == 0) {
+    IommuIvhdSouthbridgeDevices (&PciFlags, IvhdPtr, pConfig);
+  }
+  IommuIvhdApicsAndHpets (IvhdPtr, pConfig);
+  pConfig->pNbConfig->IommuTpologyInfo = *((UINT32*) &PciFlags);
+  HeaderPtr->Length += IvhdPtr->Length;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD Device Entries
+ *
+ * @param[in, out]  PciPtr    Pci topology flags
+ * @param[in, out]  IvhdPtr   Pointer to IVHD where entry is appended
+ * @param[in]       pConfig   NB config block
+ */
+VOID
+IommuIvhdNorthbridgeDevices (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT16            CurrentDevice;
+  UINT16            DeviceId;
+  UINT8             EntryCount;
+  IOMMU_DEVICELIST  *pDevices;
+  PCI_ADDR          NbPciAddress;
+  PCI_ADDR          IommuPciAddress;
+
+  pDevices = &RD890S_DfltDevices;
+  NbPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress = pConfig->NbPciAddress;
+
+  IommuPciAddress.Address.Function = NB_IOMMU;
+  EntryCount = (UINT8) ((pDevices->TableLength - sizeof (UINT16)) / sizeof (UINT16));
+
+  // Run RD890S device table, fixed for current bus
+  for (CurrentDevice = 0; CurrentDevice < EntryCount; CurrentDevice++) {
+    DeviceId = (UINT16) (NbPciAddress.Address.Bus << 8) | pDevices->Device[CurrentDevice];
+    IommuCreateDeviceEntry (PciPtr, DeviceId, IvhdPtr, pConfig);
+
+    // CHECK HOTPLUG OR PHANTOM FUNCTION SUPPORT
+    // For each device, reset PhantomEnable, but set it as a one-shot.  If any device under the northbridge PCIE bridge
+    // device has phantom function support enabled, set the L1.  Additionally, check the bridge for hotplug, and set the
+    // L1 if so.
+
+    //PciPtr->PhantomFunction = FALSE;
+    //if (PciPtr->PhantomFunction || IommuCheckHp (DeviceId, pConfig)) {
+    //  if (IommuGetL1 (DeviceId) != PCI_INVALID && LibNbGetRevisionInfo (pConfig).Revision != NB_REV_A11) {
+    //    // Determine from deviceID which L1
+    //    LibNbPciIndexRMW (IommuPciAddress.AddressValue | L1CFG_INDEX, L1CFG_SEL_WR_EN | IommuGetL1 (DeviceId), AccessS3SaveWidth32, (UINT32)~BIT0, BIT0, pConfig);
+    //  }
+    //}
+    //PciPtr->PhantomFunction = FALSE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD Device Entries
+ *
+ * @param[in, out]  PciPtr        PCI topology flags
+ * @param[in, out]  IvhdPtr       Pointer to IVHD where entry is appended
+ * @param[in]       pConfig       NB config structute
+ */
+VOID
+IommuIvhdSouthbridgeDevices (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT16    DeviceId;
+  PCI_ADDR  IommuPciAddress;
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+
+  // Assume Device 0x10 Function 0 - Device 0x17 Function 7 belong to the SB
+  //PciPtr->PhantomFunction = FALSE;
+  for (DeviceId = (0x10 << 3); (DeviceId < (0x18 << 3)); DeviceId++) {
+    IommuCreateDeviceEntry (PciPtr, DeviceId, IvhdPtr, pConfig);
+    //if (PciPtr->PhantomFunction) {
+    //    // Enable SB phantom enable
+    //  LibNbPciIndexRMW (IommuPciAddress.AddressValue | L1CFG_INDEX, L1CFG_SEL_WR_EN | L1CFG_SEL_SB, AccessS3SaveWidth32, (UINT32)~BIT0, BIT0, pConfig);
+    //}
+    //PciPtr->PhantomFunction = FALSE;
+  }
+
+#if defined (IVHD_APIC_SUPPORT) || defined (IVHD_HPET_SUPPORT)
+  DeviceId = (SB_DEV << 3);                                       // Bus 0 Dev 14 Func 0
+#endif
+
+#ifdef  IVHD_APIC_SUPPORT
+  // Southbridge IOAPIC
+  IommuCreate8ByteEntry (DE_SPECIAL, DATA_ALLINTS, 0, 0xFF, DeviceId, VARIETY_IOAPIC, IvhdPtr);
+#endif
+
+#ifdef  IVHD_HPET_SUPPORT
+  // Southbridge HPET
+  IommuCreate8ByteEntry (DE_SPECIAL, DATA_ALLINTS, 0, 0, DeviceId, VARIETY_HPET, IvhdPtr);
+#endif
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD Device Entries
+ *
+ * @param[in, out]  IvhdPtr     Pointer to buffer to return IVRS.
+ * @param[in]       pConfig       NB config structute
+ */
+VOID
+IommuIvhdApicsAndHpets (
+  IN OUT   IOMMU_IVHD_ENTRY *IvhdPtr,
+  IN OUT   AMD_NB_CONFIG    *pConfig
+  )
+{
+#ifdef  IVHD_APIC_SUPPORT
+  PCI_ADDR  PciAddress;
+  UINT16    DeviceId;
+  UINT32    PciData;
+
+  PciAddress = pConfig->NbPciAddress;
+
+  // Northbridge IOAPIC
+  DeviceId = (UINT16)((PciAddress.Address.Bus << 8)) | 1;          // Bus X Dev 0 Func 0
+  LibNbPciRead (PciAddress.AddressValue | 0x4C, AccessWidth32, &PciData, pConfig);
+  if (PciData & (UINT32)BIT1) {
+    IommuCreate8ByteEntry (DE_SPECIAL, DATA_NOINTS, 0, 0xFF, DeviceId, VARIETY_IOAPIC, IvhdPtr);
+  }
+#endif
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD device entry (type 2 for single function or 3/4 for multifunction) at end of IVHD entry
+ *
+ * @param[in, out]  PciPtr        Pci topology flags
+ * @param[in]       DeviceId      DeviceID of entry to potentially create
+ * @param[in, out]  IvhdPtr       Pointer to IVHD
+ * @param[in]       pConfig       NB config structute
+ */
+VOID
+IommuCreateDeviceEntry (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN       UINT16             DeviceId,
+  IN OUT   IOMMU_IVHD_ENTRY   *IvhdPtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  // 8 BYTE DEVICE ENTRY:
+  // [0] Type (0x2 = Device, 0x3 = Device Range Start, 0x4 = Device Range End
+  // [1] DeviceID LSB (Device/Function)
+  // [2] DeviceID MSB (Bus)
+  // [3] Data (0 = No legacy interrupts)
+
+  // DEVICEID
+  // A 16 bit bus/device/function DeviceId consists of:
+  // [15:8] Bus
+  // [7:3] Device
+  // [2:0] Function
+
+  PCI_ADDR  PciAddress;
+  UINT32    PciData;
+  UINT8     DeviceCount;
+  UINT8     FunctionCount;
+  UINT8     PcieCapBase;
+  UINT8     PcixCapBase;
+
+  BOOLEAN   LegacyBridge;
+  BOOLEAN   MultiFunction;
+  BOOLEAN   SubFunction;
+  BOOLEAN   DiscreteEntry;
+  UINT8     HighFunction;
+  UINT32    ClassCode;
+  UINT16    ExtendedCapabilityPtr;
+  SB_INFO   SbInfo;
+  UINT8     SataEnableRegValue;
+  BOOLEAN   SrIovDevice;
+
+  PcieCapBase = 0;
+  PcixCapBase = 0;
+  LegacyBridge = FALSE;
+  MultiFunction = FALSE;
+  SubFunction = FALSE;
+  DiscreteEntry = FALSE;
+  HighFunction = 0;
+  SataEnableRegValue = 0;
+  SrIovDevice = FALSE;
+
+  //For SB700, get combined mode status
+  SbInfo = LibAmdSbGetRevisionInfo ((pConfig == NULL)?NULL:GET_BLOCK_CONFIG_PTR (pConfig));
+  if (SbInfo.Type == SB_SB700) {
+    LibNbPciRead (MAKE_SBDFO (0, 0, 0x14, 0, SATA_ENABLE_REG), AccessWidth8, &SataEnableRegValue , pConfig);
+  }
+
+
+  // If the device to check does not exist, exit
+  PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, DeviceId & 0x7, 0);
+  if (!LibNbIsDevicePresent (PciAddress, pConfig)) {
+    return;
+  };
+  LibNbPciRead (PciAddress.AddressValue | PCI_CLASS, AccessWidth32, &ClassCode, pConfig);
+  ClassCode = (ClassCode >> 16) & 0xFFFF;   // Keep class code and sub-class only
+
+  // THREE STAGES TO THIS FUNCTION
+  // 1. Check for multifunction or special devices
+  // 2. Place device entry for the current device ID
+  // 3. If a bridge, decide if we need to traverse further
+
+  // STEP 1 - CHECK FUNCTIONS ON THIS DEVICE
+  // To make decisions, we will need several pieces of information about this device not found with current SBDFO
+  // 1. Multifunction device - To determine if a device entry, or device range entry is needed - check function 0 only
+  // 2. DisableRange - We will create single entries a device containing a PCI or PCIE bridge
+  // 3. How many functions on this device?
+
+  PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, 0, 0);
+  LibNbPciRead (PciAddress.AddressValue | PCI_HEADER, AccessWidth32, &PciData, pConfig);
+  if ((PciData & PCI_MULTIFUNCTION) != 0) {
+    MultiFunction = TRUE;
+  } else {
+    DiscreteEntry = TRUE;
+  }
+  if ((DeviceId & 0x7) != 0 && MultiFunction) {
+    SubFunction = TRUE;
+  }
+
+  if (MultiFunction) {
+    for (FunctionCount = 0; FunctionCount < 8; FunctionCount++) {
+      PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, FunctionCount, 0);
+      LibNbPciRead (PciAddress.AddressValue | PCI_HEADER, AccessWidth32, &PciData, pConfig);
+      if (PciData != PCI_INVALID) {
+        HighFunction = FunctionCount;
+      }
+      LibNbPciRead (PciAddress.AddressValue | PCI_CLASS, AccessWidth32, &PciData, pConfig);
+      if (((PciData >> 16) & 0xFFFF) == PCI_BRIDGE_CLASS) {
+        DiscreteEntry = TRUE;
+      }
+    }
+  }
+
+  // For SR IOV devices set for all functions to be available
+  if (MultiFunction && (!DiscreteEntry) && (!SubFunction)) {
+    PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, 0, 0);
+    ExtendedCapabilityPtr = LibNbFindPcieExtendedCapability (PciAddress.AddressValue, 0x10, pConfig);
+    if (ExtendedCapabilityPtr != 0) {
+      SrIovDevice = TRUE;
+    }
+  }
+    // STEP 2 - PLACE DEVICE ENTRY
+    // We have already decided whether we should use discrete type2 entries, or ranged type3/4 entries
+    // Place each device entry at the end of the current IVHD
+    // In each case, increment the maximum bus/device/function for L2 cache control done after the IVHD is created
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "[NBIOMMU]Placing Entry for Device [0x%x]\n", DeviceId));
+
+  //if (IommuCheckPhantom (DeviceId, pConfig)) {
+  //  PciPtr->PhantomFunction = TRUE;
+  //}
+
+  if (!MultiFunction || DiscreteEntry) {
+    //For Device 0x14, function 0, Set DATA_ALLINTS
+    if (DeviceId == (SB_DEV << 3)) {
+      IommuCreate4ByteEntry (DE_SELECT, DATA_ALLINTS, DeviceId, IvhdPtr);
+    } else if (DeviceId == DEVICEID_IDE) {
+      // For IDE device 0x14, function 1, first check if in combined mode
+      if (SataEnableRegValue & SATA_COMBINED_MODE) {
+        // Create Alias entry in combined mode
+        IommuCreate8ByteEntry (DE_ALIASSELECT, DATA_NOINTS, DEVICEID_IDE, 0, DEVICEID_SATA, 00, IvhdPtr);
+      } else {
+        //Create select entry if not in the combined mode
+        IommuCreate4ByteEntry (DE_SELECT, 0, DeviceId, IvhdPtr);
+      }
+    } else {
+      // For all other single function devices other than device 0x14, functions 0 or 1, create select entry
+      IommuCreate4ByteEntry (DE_SELECT, 0, DeviceId, IvhdPtr);
+    }
+
+    // Record the largest bus, device, function which will be used as a mask by the Iommu L2 cache
+    // Record if phantom device present for current device.  Only set it if present, do not clear.
+//    if (IommuCheckPhantom (DeviceId, pConfig)) {
+//      PciPtr->PhantomFunction = TRUE;
+//    }
+    IommuRecordBusDevFuncInfo (PciPtr, DeviceId, pConfig);
+  }
+
+  if (MultiFunction && (!DiscreteEntry) && (!SubFunction)) {
+
+    // This is a multifunction device without a bridge, so create a type 3 and 4 device entry
+    IommuCreate4ByteEntry (DE_START, 0, DeviceId, IvhdPtr);
+    if (SrIovDevice) {
+      IommuCreate4ByteEntry (DE_END, 0, (DeviceId | 0x00FF), IvhdPtr);
+    } else {
+      IommuCreate4ByteEntry (DE_END, 0, DeviceId + HighFunction, IvhdPtr);
+    }
+
+    // Record the largest bus, device, function which will be used as a mask by the Iommu L2 cache
+    // Record if phantom device present for current device.  Only set it if present, do not clear.
+//    if (IommuCheckPhantom (DeviceId, pConfig)) {
+//      PciPtr->PhantomFunction = TRUE;
+//    }
+    IommuRecordBusDevFuncInfo (PciPtr, DeviceId + HighFunction, pConfig);
+  }
+
+  if (ClassCode == PCI_BRIDGE_CLASS) {
+    UINTN   Type;
+    UINT32  BusData;
+    // STEP 3 - BRIDGE DEVICE
+    // These are treated a little differently.  We already created the entry for the bridge itself...
+    // For a PCIe bridge, continue down the bridge device creating more entries until we find an endpoint
+    // For a PCI bridge, define the entire sub-bus range as belonging to this source id
+    // For a PCIX bridge, figure out which mode it is operating in
+    PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, DeviceId & 0x7, 0);
+    LibNbPciRead (PciAddress.AddressValue | PCI_BUS, AccessWidth32, &BusData, pConfig);
+    PcieCapBase = LibNbFindPciCapability (PciAddress.AddressValue, PCIE_CAPID, pConfig);
+    PcixCapBase = LibNbFindPciCapability (PciAddress.AddressValue, PCIX_CAPID, pConfig);
+
+    Type = 0;
+    if (PcieCapBase != 0) {
+      Type = 1;
+      LibNbPciRead (PciAddress.AddressValue | PcieCapBase, AccessWidth32, &PciData, pConfig);
+      PciData = (PciData >> 16) & PCIE_PORTMASK;    // [7:4] are Device/Port type, 01
+      if (PciData == PCIE_PCIE2PCIX) {
+        Type = 2;
+      }
+    }
+    if (PcixCapBase != 0) {
+      Type = 2;
+    }
+
+    //For Hot plug capable devices, create 'Start of range' and 'End of range' IVRS'.
+    // This will override Type 1 and Type 2.
+    if (IommuCheckHp (DeviceId, pConfig)) {
+      Type = 3;
+    }
+
+    switch (Type) {
+    case  0:
+      //PCI
+      IommuRecordBusDevFuncInfo (PciPtr, DeviceId, pConfig);
+      IommuCreate8ByteEntry (DE_ALIASSTART, DATA_NOINTS, (UINT16) (BusData & 0xFF00), 0, DeviceId, 0, IvhdPtr);
+      IommuCreate4ByteEntry (DE_END, 0, (UINT16) (((BusData & 0xFF0000) >> 8) + 0xFF), IvhdPtr);
+      break;
+    case  1:
+      //Pcie (non hot plug)
+      for (DeviceCount = 0; DeviceCount <= 0x1f; DeviceCount++) {
+        for (FunctionCount = 0; FunctionCount <= 0x7; FunctionCount++) {
+          IommuCreateDeviceEntry (PciPtr, ((UINT16) (BusData & 0xFF00)) | (DeviceCount << 3) | FunctionCount, IvhdPtr, pConfig);
+        }
+      }
+      break;
+    case  2:
+      //PCIx
+      IommuRecordBusDevFuncInfo (PciPtr, (UINT16) (BusData & 0xFF00), pConfig);
+      IommuCreate8ByteEntry (DE_ALIASSTART, DATA_NOINTS, (UINT16) ((BusData & 0xFF00) | ( 1 << 3)), 0, (UINT16) (BusData & 0xFF00), 0, IvhdPtr);
+      IommuCreate4ByteEntry (DE_END, 0, (UINT16) (((BusData & 0xFF0000) >> 8) + 0xFF), IvhdPtr);
+      break;
+    case 3:
+      //For Hot plug ports, set all devices and functions behind the secondary bus.
+      IommuCreate4ByteEntry (DE_START, 0, (UINT16) (BusData & 0xFF00), IvhdPtr);            // Secondary bus, Device 0, Function 0
+      IommuCreate4ByteEntry (DE_END, 0, (UINT16) ((BusData & 0xFF00) | (0x1F << 3) | 7), IvhdPtr); // Secondary bus, Device 1f, Function 7
+      break;
+    default:
+      CIMX_ASSERT (FALSE);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Place IVHD device entry (type 2 for single function or 3/4 for multifunction) at end of IVHD entry
+ *
+ * @param[in, out]  PciPtr        Pci topology flags
+ * @param[in]       DeviceId      DeviceID
+ * @param[in]       pConfig       NB config structute
+ */
+VOID
+IommuRecordBusDevFuncInfo (
+  IN OUT   IOMMU_PCI_TOPOLOGY *PciPtr,
+  IN       UINT16             DeviceId,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT16    ExtendedCapabilityPtr;
+  PCI_ADDR  Device;
+  Device.AddressValue = MAKE_SBDFO (0, DeviceId >> 8, (DeviceId >> 3) & 0x1f, DeviceId & 0x7, 0);
+#ifdef  EXCLUDE_SB_DEVICE_FROM_L2_HASH
+  if ((UINT8)Device.Address.Bus == 0) {
+    AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR (pConfig);
+    if (ConfigPtr->PlatformType == ServerPlatform) {
+      return;
+    }
+  }
+#endif
+  Device.AddressValue = MAKE_SBDFO (0, DeviceId >> 8, (DeviceId >> 3) & 0x1f, DeviceId & 0x7, 0);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NB_TRACE), "    Device Data For L2 Hash Bus = 0x%x Device = 0x%x Func = 0x%x\n", Device.Address.Bus, Device.Address.Device, Device.Address.Function));
+  ExtendedCapabilityPtr = LibNbFindPcieExtendedCapability (Device.AddressValue, 0x10, pConfig);
+  if (ExtendedCapabilityPtr != 0) {
+    UINT16  TotalVF;
+    LibNbPciRead (Device.AddressValue | (ExtendedCapabilityPtr + 0xE), AccessWidth16, &TotalVF, pConfig);
+    PciPtr->MaxFunction = CIMX_MAX (PciPtr->MaxFunction, TotalVF);
+  }
+  PciPtr->MaxBus = CIMX_MAX (PciPtr->MaxBus, (UINT8)Device.Address.Bus);
+  PciPtr->MaxDevice = CIMX_MAX (PciPtr->MaxDevice, (UINT8)Device.Address.Device);
+  PciPtr->MaxFunction = CIMX_MAX (PciPtr->MaxFunction, (UINT16) (UINT8)Device.Address.Function);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Append data entry to IVRS
+ *
+ * @param[in]      Type       IVRC entry type
+ * @param[in]      Data       IVRC entry data
+ * @param[in]      Word1      IVRC entry data
+ * @param[in, out] IvhdPtr    Current IVHD pointer
+ *
+ */
+VOID
+IommuCreate4ByteEntry (
+  IN       UINT8            Type,
+  IN       UINT8            Data,
+  IN       UINT16           Word1,
+  IN OUT   IOMMU_IVHD_ENTRY *IvhdPtr
+  )
+{
+  UINT32 Buffer;
+  UINT16 AlignedDeviceEntryIndex;
+  UINT16 DeviceEntryIndex;
+
+  Buffer = Type + (Word1 << 8) + (Data << 24);
+  DeviceEntryIndex = (IvhdPtr->Length - 24) / sizeof (UINT32);
+  AlignedDeviceEntryIndex = DeviceEntryIndex;
+
+#ifdef IVHD_MIN_8BYTE_ALIGNMENT
+  AlignedDeviceEntryIndex = (DeviceEntryIndex + 1) & 0xfffe;
+#endif
+
+  IvhdPtr->DeviceEntry[AlignedDeviceEntryIndex] = Buffer;
+  IvhdPtr->Length += (4 + (AlignedDeviceEntryIndex - DeviceEntryIndex) * 4);
+  CIMX_TRACE ((TRACE_DATA (NULL, CIMX_NB_TRACE), "[NBIOMMU]Added entry - [0x%x]\n", Buffer));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Append data entry to IVRS
+ *
+ * @param[in]      Type       IVRC entry type
+ * @param[in]      Data       IVRC entry data
+ * @param[in]      Word1      IVRC entry data
+ * @param[in]      Byte4      IVRC entry data
+ * @param[in]      Word5      IVRC entry data
+ * @param[in]      Byte7      IVRC entry data
+ * @param[in, out] IvhdPtr    Current IVHD pointer
+ *
+ */
+VOID
+IommuCreate8ByteEntry (
+  IN       UINT8            Type,
+  IN       UINT8            Data,
+  IN       UINT16           Word1,
+  IN       UINT8            Byte4,
+  IN       UINT16           Word5,
+  IN       UINT8            Byte7,
+  IN OUT   IOMMU_IVHD_ENTRY *IvhdPtr
+  )
+{
+  UINT16 AlignedDeviceEntryIndex;
+  UINT16 DeviceEntryIndex;
+  UINT64 Buffer;
+
+  Buffer = Type + (Word1 << 8) + ((UINT32)Data << 24);
+  ((UINT32*)&Buffer)[1] = Byte4 + (Word5 << 8) + (Byte7 << 24);
+  DeviceEntryIndex = (IvhdPtr->Length - 24) / sizeof (UINT32);
+  AlignedDeviceEntryIndex = DeviceEntryIndex;
+
+#if defined (IVHD_MIN_8BYTE_ALIGNMENT) || defined (IVHD_SIZE_ALIGNMENT)
+  AlignedDeviceEntryIndex = (DeviceEntryIndex + 1) & 0xfffe;
+#endif
+  IvhdPtr->DeviceEntry[AlignedDeviceEntryIndex] = ((UINT32*)&Buffer)[0];
+  IvhdPtr->DeviceEntry[AlignedDeviceEntryIndex + 1] = ((UINT32*)&Buffer)[1];
+  IvhdPtr->Length += (8 + (AlignedDeviceEntryIndex - DeviceEntryIndex) * 4);
+  CIMX_TRACE ((TRACE_DATA (NULL, CIMX_NB_TRACE), "[NBIOMMU]Added entry - [0x%llx]\n", Buffer));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set checksum, IvInfo, finish IVRS table
+ *
+ * @param[in, out] BufferPtr     Pointer to text buffer to return IVRS.
+ * @param[in, out] pConfig       Northbridge configuration structure pointer.
+ *
+ */
+VOID
+IommuFinalizeIvrs (
+  IN OUT   VOID           *BufferPtr,
+  IN       AMD_NB_CONFIG  *pConfig
+  )
+{
+  IOMMU_IVRS_HEADER *HeaderPtr;
+  PCI_ADDR          IommuPciAddress;
+  UINT32            PciData;
+
+  HeaderPtr = (IOMMU_IVRS_HEADER *)BufferPtr;
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+
+  // Find common IvInfo (largest shared) 0x50
+  // [22] = ATS Translation Reserved
+  // [21:15] = VA Size
+  // [14:8] = PA Size
+
+  LibNbPciRead (IommuPciAddress.AddressValue | RD890S_CAP_MISC, AccessWidth32, &PciData, pConfig);
+  PciData &= (IVINFO_ATSMASK | IVINFO_VAMASK | IVINFO_PAMASK);
+  HeaderPtr->IvInfo = PciData;
+
+  //LibAmdUpdateAcpiTableChecksum (HeaderPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Nb Iommu Fixup of IVRS APIC entries
+ *
+ * @param[in]      DevicePtr     Pointer to current device entry
+ * @param[in]      pConfig       Northbridge configuration structure pointer.
+ *
+ */
+UINT64
+IommuGetApicBaseAddress (
+  IN      VOID           *DevicePtr,
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  PCI_ADDR  PciAddress;
+  UINT16    DeviceId;
+  UINT32    Data;
+
+  // If no pointer provided, return no base address
+  if (DevicePtr == NULL) {
+    return 0;
+  }
+
+  // Special entry can be IOAPIC or other(HPET).  We only care about the IOAPIC.
+  if (*(UINT8*) ((UINT8*)DevicePtr + DE_SPECIAL_VARIETY) != VARIETY_IOAPIC) {
+    return 0;
+  }
+
+  DeviceId = *(UINT16*) ((UINT8*)DevicePtr + DE_DEVICEID);
+  PciAddress.AddressValue = MAKE_SBDFO (0, (DeviceId >> 8) & 0xFF, (DeviceId >> 3) & 0x1F, 0, 0);
+
+  // An APIC entry will only be created for AMD northbridge or southbridges, so
+  // we can assume PCI dev/func = 0, 0 will be a northbridge IOAPIC device
+  // and any other will be a southbridge IOAPIC device.  If the device was not
+  // already enabled and known to be an AMD device, no entry would have been created.
+
+  if ((PciAddress.Address.Device == NB_PCI_DEV) && (PciAddress.Address.Function == NB_HOST)) {
+
+    // We have an AMD NB, check function 0
+    Data = 1;
+    PciAddress.Address.Function = 0;
+    LibNbPciWrite (PciAddress.AddressValue | 0xF8, AccessS3SaveWidth32, &Data, pConfig);
+    LibNbPciRead (PciAddress.AddressValue | 0xFC, AccessWidth32, &Data, pConfig);
+  } else {
+    SB_INFO  SbInfo;
+    SbInfo = LibAmdSbGetRevisionInfo ((pConfig == NULL)?NULL:GET_BLOCK_CONFIG_PTR (pConfig));
+    if (SbInfo.Type == SB_SB700) {
+      PciAddress.Address.Function = 0;
+      LibNbPciRead (PciAddress.AddressValue | 0x74, AccessWidth32, &Data, pConfig);
+    } else {
+      LibAmdSbPmioRead ( 0x34, AccessWidth32, &Data, pConfig);
+    }
+  }
+  return ((UINT64) (Data & 0xFFFFFF00));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Nb Iommu Fixup of IVRS APIC entries
+ *
+ * @param[in]      BaseAddress   Base address to match
+ * @param[in]      MadtPtr       Pointer to current device entry
+ * @param[in]      pConfig       Northbridge configuration structure pointer.
+ *
+ */
+UINT8
+IommuGetApicId (
+  IN      UINT64         BaseAddress,
+  IN      VOID           *MadtPtr,
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  VOID  *EntryPtr;
+
+  EntryPtr = LibAmdGetFirstMadtStructure (MADT_APIC_TYPE, MadtPtr);
+
+  do {
+    // If our base address for a known device matches this MADT, get the APIC ID
+    if (*(UINT32*) ((UINT8*)EntryPtr + MADT_APIC_BASE) == (UINT32)BaseAddress) {
+      return *(UINT8*) ((UINT8*)EntryPtr + MADT_APIC_ID);
+    }
+    EntryPtr = LibAmdGetNextMadtStructure (MADT_APIC_TYPE, EntryPtr, MadtPtr);
+  } while (EntryPtr != NULL);
+  return 0xFF;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disconnect unused PCIe core from IOMMU block.
+ *
+ * @param[in]      CoreId        Pcie Core Id
+ * @param[in]      pConfig       Northbridge configuration structure pointer.
+ *
+ */
+VOID
+NbIommuDisconnectPcieCore (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCI_ADDR  IommuPciAddress;
+  UINT32    Value;
+  IommuPciAddress = pConfig->NbPciAddress;
+  IommuPciAddress.Address.Function = NB_IOMMU;
+  Value = 1 << ((0x4310 >> (CoreId * 4)) & 0xf);
+  LibNbPciIndexRMW (IommuPciAddress.AddressValue | L2CFG_INDEX, L2CFG_SEL_WR_EN | L2REG_46, AccessS3SaveWidth32, 0xFFFFFFFF, Value , pConfig);
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbIommu.h b/src/vendorcode/amd/cimx/rd890/nbIommu.h
new file mode 100644
index 0000000..7fc2c5c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbIommu.h
@@ -0,0 +1,326 @@
+/**
+ * @file
+ *
+ * Routines for IOMMU.
+ *
+ * Implement the IOMMU init and ACPI feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+// Identifying an IOMMU:
+// RD890S - IOMMU present
+// all other (including RD890) - IOMMU not present
+// Class = System Base Peripheral (08h)
+// Subclass = IOMMU (06h)
+// Programming Interface Code = 0h
+// Must reside on top/root complex PCI hierarchy
+// There is always a NB device at bus 0 device 0 function 0 (fcn 2 for IOMMU) - device ID 0x5A23
+
+// Inputs:
+// From OEM: Get exclusion table
+// From OEM: Get text buffer
+
+// Outputs:
+// To OEM: Complete IVRS table for linking
+
+#ifndef _NBIOMMU_H_
+#define _NBIOMMU_H_
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+NbIommuInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+AGESA_STATUS
+NbIommuInitS3 (
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+AGESA_STATUS
+NbIommuAcpiInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+AGESA_STATUS
+NbIommuAcpiFixup (
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+VOID
+NbIommuDisconnectPcieCore (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+// IOMMU Architectural
+#define IVRS_BUFFER_SIZE        0x2000      // Default 8KB allocated to table
+//#define IVHD_MIN_8BYTE_ALIGNMENT          // Align IVHD entries on 8 byte boundary
+#define IVHD_SIZE_ALIGNMENT                 // Align IVHD entries on MOD entry-size boundary
+#define IVHD_HPET_SUPPORT                   // Create HPET entries
+#define IVHD_APIC_SUPPORT                   // Create IOAPIC entries
+
+// IOMMU Northbridge
+#define RD890S_CAP_MISC         0x50        // RD890/S Capabilities Misc Info
+#define NB_PCI_DEV              0           // PCI NB device number
+#define NB_HOST                 0           // Function 0 = NB HOST
+#define NB_IOMMU                2           // Function 2 = IOMMU
+#define SB_DEV                  0x14        // PCI SB device number
+#define SB_SMBUS                3           // Function 3 = SMBUS
+#define SB_SATA                 0x11        // SB SATA
+#define SATA_ENABLE_REG         0xAD        // Dev. 0x14, Func 0, Reg 0xAD for SATA combined mode
+#define SATA_COMBINED_MODE      BIT3        // Bit 3 of SB_ENABLE_REG., 1 = Combined mode
+
+#define IOMMU_CAP_HEADER_OFFSET 0x00
+#define IOMMU_BASE_LOW_OFFSET   0x04
+#define IOMMU_BASE_HIGH_OFFSET  0x08
+#define IOMMU_RANGE_OFFSET      0x0C
+#define IOMMU_MISC_OFFSET       0x10
+
+#define DEVICEID_NB       ((0 << 8) + (NB_PCI_DEV << 3) + NB_HOST)
+#define DEVICEID_IOMMU    ((0 << 8) + (NB_PCI_DEV << 3) + NB_IOMMU)
+#define DEVICEID_GPP1_0   ((0 << 8) + (0x2 << 3) + 0)
+#define DEVICEID_GPP1_1   ((0 << 8) + (0x3 << 3) + 0)
+#define DEVICEID_GPP2_0   ((0 << 8) + (0xB << 3) + 0)
+#define DEVICEID_GPP2_1   ((0 << 8) + (0xC << 3) + 0)
+#define DEVICEID_GPP3A_0  ((0 << 8) + (0x4 << 3) + 0)
+#define DEVICEID_GPP3A_1  ((0 << 8) + (0x5 << 3) + 0)
+#define DEVICEID_GPP3A_2  ((0 << 8) + (0x6 << 3) + 0)
+#define DEVICEID_GPP3A_3  ((0 << 8) + (0x7 << 3) + 0)
+#define DEVICEID_GPP3A_4  ((0 << 8) + (0x9 << 3) + 0)
+#define DEVICEID_GPP3A_5  ((0 << 8) + (0xA << 3) + 0)
+#define DEVICEID_GPP3B_0  ((0 << 8) + (0xD << 3) + 0)
+
+#define DEVICEID_SATA     ((0 << 8) + (0x11 << 3) + 0)
+#define DEVICEID_IDE      ((0 << 8) + (0x14 << 3) + 1)
+
+#define L1CFG_INDEX             0xF8
+// There is an L1 for each device (6), which is selected by [19:16] of L1CFG_INDEX
+// e.g. (LibNbPciIndexRead (Address | L1CFGIND, L1_REG_0C | L1_CFG_SEL, AccessWidth32, &Value, pConfig)
+#define L1CFG_SEL_WR_EN         0x80000000
+#define L1CFG_SEL_GPP1          0x00000000
+#define L1CFG_SEL_GPP2          0x00010000
+#define L1CFG_SEL_SB            0x00020000
+#define L1CFG_SEL_GPP3A         0x00030000
+#define L1CFG_SEL_GPP3B         0x00040000
+#define L1CFG_SEL_VC1           0x00050000
+#define L1REG_06                0x6
+#define L1REG_0C                0xC
+#define L1REG_0D                0xD
+#define L1REG_07                0x7
+#define L1CFG_DATA              0xFC
+
+#define L2CFG_INDEX             0xF0
+// e.g. (LibNbPciIndexRead (Address | L2CFGIND, L2_REG_0C, AccessWidth16, &Value, pConfig)
+#define L2CFG_SEL_WR_EN         0x100
+#define L2REG_06                0x6
+#define L2REG_07                0x7
+#define L2REG_0C                0xC
+#define L2REG_10                0x10
+#define L2REG_11                0x11
+#define L2REG_14                0x14
+#define L2REG_15                0x15
+#define L2REG_18                0x18
+#define L2REG_19                0x19
+#define L2REG_1C                0x1C
+#define L2REG_1D                0x1D
+#define L2REG_46                0x46
+#define L2REG_47                0x47
+#define L2REG_50                0x50
+#define L2REG_51                0x51
+#define L2REG_52                0x52
+#define L2REG_56                0x56
+#define L2REG_30                0x30
+#define L2REG_80                0x80
+#define L2CFG_DATA              0xF4
+
+// PCI/PCIe Architectural
+#define PCIE_CAPID              0x10
+#define PCIE_PORTMASK           0xF0              // Device cap reg 2
+#define PCIE_PCIE2PCIX          0x70              // Device cap reg 2
+#define PCIE_PHANTOMMASK        0x18              // Device cap reg 4
+#define PCIX_CAPID              0x07
+#define IOMMU_CAPID             0x0F
+
+#define PCI_DVID                0x00
+#define PCI_INVALID             0xFFFFFFFF
+#define PCI_CLASS               0x08
+#define PCI_HEADER              0x0C
+#define PCI_MULTIFUNCTION       0x00800000
+#define PCI_BUS                 0x18
+#define PCI_SUBMASK             0xFF0000
+#define PCI_SECMASK             0xFF00
+#define PCI_PRIMASK             0xFF
+#define PCI_BRIDGE_CLASS        0x0604
+
+// IVRS Table Access
+#define TYPE_IVHD               0x10
+#define IVINFO_ATSMASK          0x00400000          // [22] = ATS
+#define IVINFO_VAMASK           0x003F8000          // [21:15] = Virtual Address Size
+#define IVINFO_PAMASK           0x00007F00          // [14:8] = Physical Address Size
+#define FLAGS_COHERENT          BIT5
+#define FLAGS_IOTLBSUP          BIT4
+#define FLAGS_ISOC              BIT3
+#define FLAGS_RESPASSPW         BIT2
+#define FLAGS_PASSPW            BIT1
+
+#define TYPE_IVMD_ALL           0x20
+#define TYPE_IVMD_SELECT        0x21
+#define TYPE_IVMD_RANGE         0x22
+
+#define DE_PAD4                 1
+#define DE_BYTE0                0
+#define DE_BYTE1                1
+#define DE_BYTE2                2
+#define DE_BYTE3                3
+#define DE_SELECT               2
+#define DATA_NOINTS             0
+#define DATA_LINT_EINT_INIT     BIT7 + BIT6 + BIT1 + BIT0
+#define DATA_ALLINTS            0xD7
+#define DE_START                3
+#define DE_END                  4
+#define DE_PAD8                 64
+#define DE_BYTE4                4
+#define DE_BYTE5                5
+#define DE_BYTE6                6
+#define DE_BYTE7                7
+#define DE_ALIASSELECT          66
+#define DE_ALIASSTART           67
+#define DE_SPECIAL              72
+#define VARIETY_IOAPIC          0x1
+#define VARIETY_HPET            0x2
+#define DE_SPECIAL_VARIETY      7
+#define DE_DEVICEID             5
+#define DE_SPECIAL_ID           4
+
+// MADT Table Access
+#define MADT_APIC_TYPE          0x1
+#define MADT_APIC_ID            0x2
+#define MADT_APIC_BASE          0x4
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+#pragma pack (push, 1)
+
+/// IVRS header
+typedef struct {
+  UINT32  Signature;                        ///< see IOMMU specification for details
+  UINT32  Length;                           ///< see IOMMU specification for details
+  UINT8   Revision;                         ///< see IOMMU specification for details
+  UINT8   Checksum;                         ///< see IOMMU specification for details
+  CHAR8   OemId[6];                         ///< see IOMMU specification for details
+  CHAR8   OemTableId[8];                    ///< see IOMMU specification for details
+  CHAR8   OemRevision[4];                   ///< see IOMMU specification for details
+  CHAR8   CreatorId[4];                     ///< see IOMMU specification for details
+  CHAR8   CreatorRevision[4];               ///< see IOMMU specification for details
+  UINT32  IvInfo;                           ///< see IOMMU specification for details
+  UINT64  Reserved;                         ///< see IOMMU specification for details
+} IOMMU_IVRS_HEADER;
+
+/// DeviceID
+typedef struct {
+  UINT16  TableLength;                      ///< length of table
+  UINT16  Device[];                         ///< DeviceID
+} IOMMU_DEVICELIST;
+
+/// PCI Topology Based Settings
+typedef struct {
+//  BOOLEAN PhantomFunction;                    ///< phantom functions present
+  UINT8   MaxBus;                           ///< max bus accumulator
+  UINT8   MaxDevice;                        ///< max device accumulator
+  UINT16  MaxFunction;                      ///< max function accumulator
+} IOMMU_PCI_TOPOLOGY;
+
+/// IVHD for each hardware definition (i.e. # of northbridges)
+typedef struct {
+  UINT8   Type;                             ///< see IOMMU specification for details
+  UINT8   Flags;                            ///< see IOMMU specification for details
+  UINT16  Length;                           ///< see IOMMU specification for details
+  UINT16  DeviceId;                         ///< see IOMMU specification for details
+  UINT16  CapabilityOffset;                 ///< see IOMMU specification for details
+  UINT64  BaseAddress;                      ///< see IOMMU specification for details
+  UINT16  PciSegment;                       ///< see IOMMU specification for details
+  UINT16  IommuInfo;                        ///< see IOMMU specification for details
+  UINT32  Reserved;                         ///< see IOMMU specification for details
+  UINT32  DeviceEntry[];                    ///< see IOMMU specification for details
+} IOMMU_IVHD_ENTRY;
+
+/// IVMD for each memory range
+typedef struct {
+  UINT8   Type;                             ///< see IOMMU specification for details
+  UINT8   Flags;                            ///< see IOMMU specification for details
+  UINT16  Length;                           ///< see IOMMU specification for details
+  UINT16  DeviceId;                         ///< see IOMMU specification for details
+  UINT16  AuxData;                          ///< see IOMMU specification for details
+  UINT64  Reserved;                         ///< see IOMMU specification for details
+  UINT64  BlockStartAddress;                ///< see IOMMU specification for details
+  UINT64  BlockLength;                      ///< see IOMMU specification for details
+} IOMMU_IVMD_ENTRY;
+
+//#define IVRS_HANDLE 'SRVI'
+#define IVRS_HANDLE Int32FromChar ('S', 'R', 'V', 'I')
+
+#define L2_DTC_CONTROL    0x10
+#define L2_ITC_CONTROL    0x14
+#define L2_PTC_A_CONTROL  0x18
+#define L2_PTC_B_CONTROL  0x1C
+#define L2_PDC_CONTROL    0x50
+
+#define EXCLUDE_SB_DEVICE_FROM_L2_HASH
+
+/// L2 cache init
+typedef struct {
+  UINT8 HashControl;                        ///<Control regsiter block address
+} L2_HASH_CONTROL;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbLib.c b/src/vendorcode/amd/cimx/rd890/nbLib.c
new file mode 100644
index 0000000..5862768
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbLib.c
@@ -0,0 +1,1138 @@
+/**
+ * @file
+ *
+ * NB library functions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get silicon type and revision info.
+ *
+ *
+ *
+ * @param[in]   NbConfigPtr configuration structure pointer.
+ * @retval      NB_INFO Northbrige Info Structure.
+ */
+/*----------------------------------------------------------------------------------------*/
+NB_INFO
+LibNbGetRevisionInfo (
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  NB_INFO RevisionInfo;
+  UINT16  DeviceId;
+  UINT8   RevisionId;
+  UINT32  PrivateId;
+  LibNbPciRead (NbConfigPtr->NbPciAddress.AddressValue | 0x8, AccessWidth8, &RevisionId, NbConfigPtr);
+  RevisionInfo.Revision = RevisionId;
+  LibNbPciRead (NbConfigPtr->NbPciAddress.AddressValue | 0x2, AccessWidth16, &DeviceId, NbConfigPtr);
+  switch (DeviceId) {
+  case  0x5956:
+    RevisionInfo.Type = NB_RD890TV;
+    break;
+  case  0x5957:
+    RevisionInfo.Type = NB_RX780;
+    break;
+  case  0x5958:
+    RevisionInfo.Type = NB_RD780;
+    break;
+  case  0x5A10:
+    RevisionInfo.Type = NB_SR5690;
+    break;
+  case  0x5A11:
+    RevisionInfo.Type = NB_RD890;
+    break;
+  case  0x5A12:
+    RevisionInfo.Type = NB_SR5670;
+    break;
+  case  0x5A13:
+    RevisionInfo.Type = NB_SR5650;
+    break;
+  case  0x5A14:
+    RevisionInfo.Type = NB_990FX;
+    LibNbPciIndexRead (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG7D, AccessWidth32, &PrivateId, NbConfigPtr);
+    PrivateId = (PrivateId >> 21) & 0x0f;
+    if (PrivateId == 1) {
+      RevisionInfo.Type = NB_990FX;
+    }
+    if (PrivateId == 2) {
+      RevisionInfo.Type = NB_990X;
+    }
+    if (PrivateId == 3) {
+      RevisionInfo.Type = NB_970;
+    }
+    break;
+  default:
+    RevisionInfo.Type = NB_UNKNOWN;
+    CIMX_ASSERT (FALSE);
+  }
+  return  RevisionInfo;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Call Back routine.
+ *
+ *
+ *
+ * @param[in] CallBackId   Callback ID.
+ * @param[in] Data         Callback specific data.
+ * @param[in] NbConfigPtr  Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+LibNbCallBack (
+  IN       UINT32          CallBackId,
+  IN OUT   UINTN           Data,
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  CALLOUT_ENTRY CallBackPtr = GET_BLOCK_CONFIG_PTR (NbConfigPtr)->StandardHeader.CalloutPtr;
+
+  Status = AGESA_UNSUPPORTED;
+  if (CallBackPtr != NULL) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NBLIB]LibNbCallBack CallBackId = 0x%x\n", CallBackId));
+    Status = (*CallBackPtr) (CallBackId, Data, GET_BLOCK_CONFIG_PTR (NbConfigPtr));
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NBLIB]LibNbCallBack Return = 0x%x\n", Status));
+  }
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Call Back routine.
+ *
+ *
+ *
+ * @param[in] SystemApi    Pointer to System API
+ * @param[in] ConfigPtr  Northbridge block configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+LibSystemApiCall (
+  IN       SYSTEM_API             SystemApi,
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  )
+{
+  API_WORKSPACE Workspace;
+  UINT8         NorthbridgeId;
+
+  LibAmdMemFill (&Workspace, 0, sizeof (API_WORKSPACE), (AMD_CONFIG_PARAMS *)&(ConfigPtr->StandardHeader));
+  Workspace.ConfigPtr = ConfigPtr;
+  Workspace.Status = AGESA_SUCCESS;
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    ConfigPtr->Northbridges[NorthbridgeId].ConfigPtr = &Workspace.ConfigPtr;
+  }
+  if (SystemApi != NULL) {
+    (*SystemApi)(ConfigPtr);
+  }
+  return Workspace.Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Call Back routine.
+ *
+ *
+ *
+ * @param[in] NbApi       Pointer to NB API
+ * @param[in] ConfigPtr   Northbridge block configuration structure pointer
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+LibNbApiCall (
+  IN       NB_API                NbApi,
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  )
+{
+  UINT8         NorthbridgeId;
+  AGESA_STATUS  Status;
+
+  Status = AGESA_SUCCESS;
+  for (NorthbridgeId = 0; NorthbridgeId <= ConfigPtr->NumberOfNorthbridges; NorthbridgeId++) {
+    AMD_NB_CONFIG *NbConfigPtr = &ConfigPtr->Northbridges[NorthbridgeId];
+    ConfigPtr->CurrentNorthbridge = NorthbridgeId;
+    if (!LibNbIsDevicePresent (NbConfigPtr->NbPciAddress, NbConfigPtr)) {
+      REPORT_EVENT (AGESA_WARNING, GENERAL_ERROR_NB_NOT_PRESENT, 0 , 0, 0, 0, NbConfigPtr);
+      continue;
+    }
+    if (NbApi != NULL) {
+      Status = (*NbApi) (NbConfigPtr);
+      if (Status == AGESA_FATAL) {
+        break;
+      }
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCI register.
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Width       Access width.
+ * @param[in] Value       Pointer to new register value.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbPciWrite (
+  IN      UINT32          Address,
+  IN      ACCESS_WIDTH    Width,
+  IN      VOID            *Value,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCI_ADDR  DeviceAddress;
+  DeviceAddress.AddressValue = Address;
+  LibAmdPciWrite (Width, DeviceAddress, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCI register
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Width       Access width.
+ * @param[in] Value       Pointer to save register value.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+LibNbPciRead (
+  IN       UINT32         Address,
+  IN       ACCESS_WIDTH   Width,
+     OUT   VOID           *Value,
+  IN       AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  PCI_ADDR  DeviceAddress;
+  DeviceAddress.AddressValue = Address;
+  LibAmdPciRead (Width, DeviceAddress, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write  PCI register
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Width       Access width.
+ * @param[in] Mask        AND Mask.
+ * @param[in] Data        OR Mask.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+LibNbPciRMW (
+  IN       UINT32         Address,
+  IN       ACCESS_WIDTH   Width,
+  IN       UINT32         Mask,
+  IN       UINT32         Data,
+  IN       AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  UINT32  Value;
+  LibNbPciRead (Address,  Width, &Value, NbConfigPtr);
+  Value = (Value & Mask) | Data;
+  LibNbPciWrite (Address, Width, &Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PCI Index/Data Address space
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Index       Index Address.
+ * @param[in] Width       Access width of Index/Data register.
+ * @param[in] Value       Pointer to save register value.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbPciIndexRead (
+  IN       UINT32        Address,
+  IN       UINT32        Index,
+  IN       ACCESS_WIDTH  Width,
+     OUT   UINT32        *Value,
+  IN       AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = (1 << ((Width < 0x80)? (Width - 1): (Width - 0x81)));
+  LibNbPciWrite (Address, Width, &Index, NbConfigPtr);
+  LibNbPciRead (Address + IndexOffset, Width, Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PCI Index/Data Address space
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Index       Index Address.
+ * @param[in] Width       Access width of Index/Data register.
+ * @param[in] Value       Pointer to save register value.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbPciIndexWrite (
+  IN      UINT32        Address,
+  IN      UINT32        Index,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        *Value,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT32  IndexOffset;
+  IndexOffset = (1 << ((Width < 0x80)? (Width - 1): (Width - 0x81)));
+  LibNbPciWrite (Address, Width, &Index, NbConfigPtr);
+  LibNbPciWrite (Address + IndexOffset , Width, Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write  PCI Index/Data Address space
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Index       Index Address.
+ * @param[in] Width       Access width of Index/Data register.
+ * @param[in] Mask       AND Mask.
+ * @param[in] Data       OR Mask.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbPciIndexRMW (
+  IN      UINT32        Address,
+  IN      UINT32        Index,
+  IN      ACCESS_WIDTH  Width,
+  IN      UINT32        Mask,
+  IN      UINT32        Data,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT32  Value;
+  LibNbPciIndexRead (Address, Index, Width, &Value, NbConfigPtr);
+  Value = (Value & Mask) | Data;
+  LibNbPciIndexWrite (Address, Index, Width, &Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Program table of indirect register.
+ *
+ *
+ *
+ * @param[in] Address     Compressed PCIE address identical to PCI_ADDR.AddressValue
+ * @param[in] Index       Index Address. Index address OR with INDIRECT_REG_ENTRY.Register
+ * @param[in] pTable      Pointer to indirect register table.
+ * @param[in] Length      Number of entry in indirect register table.
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+LibNbIndirectTableInit (
+  IN      UINT32              Address,
+  IN      UINT32              Index,
+  IN      INDIRECT_REG_ENTRY  *pTable,
+  IN      UINTN               Length,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  )
+{
+  UINTN i;
+  for (i = 0; i < Length; i++) {
+    LibNbPciIndexRMW (Address, Index | pTable[i].Register , AccessS3SaveWidth32, pTable[i].Mask, pTable[i].Data, NbConfigPtr);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCI capability pointer
+ *
+ *
+ *
+ *
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+
+UINT8
+LibNbFindPciCapability (
+  IN      UINT32        Address,
+  IN      UINT8         CapabilityId,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT8     CapabilityPtr;
+  UINT8     CurrentCapabilityId;
+  PCI_ADDR  Device;
+  Device.AddressValue = Address;
+  CapabilityPtr = 0x34;
+  if (!LibNbIsDevicePresent (Device, NbConfigPtr)) {
+    return  0;
+  }
+  while (CapabilityPtr != 0) {
+    LibNbPciRead (Address | CapabilityPtr, AccessWidth8 , &CapabilityPtr, NbConfigPtr);
+    if (CapabilityPtr) {
+      LibNbPciRead (Address | CapabilityPtr , AccessWidth8 , &CurrentCapabilityId, NbConfigPtr);
+      if (CurrentCapabilityId == CapabilityId) break;
+      CapabilityPtr++;
+    }
+  }
+  return  CapabilityPtr;
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Find PCIe extended capability pointer
+ *
+ *
+ *
+ *
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+
+UINT16
+LibNbFindPcieExtendedCapability (
+  IN      UINT32        Address,
+  IN      UINT16        ExtendedCapabilityId,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT16  CapabilityPtr;
+  UINT32  ExtendedCapabilityIdBlock;
+  if (LibNbFindPciCapability (Address, 0x10, NbConfigPtr) != 0) {
+    CapabilityPtr = 0x100;
+    LibNbPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, NbConfigPtr);
+    if (ExtendedCapabilityIdBlock != 0 && (UINT16)ExtendedCapabilityIdBlock != 0xffff) {
+      do {
+        if ((UINT16)ExtendedCapabilityIdBlock == ExtendedCapabilityId) {
+          return  CapabilityPtr;
+        }
+        CapabilityPtr = (UINT16) ((ExtendedCapabilityIdBlock >> 20) & 0xfff);
+        LibNbPciRead (Address | CapabilityPtr , AccessWidth32 , &ExtendedCapabilityIdBlock, NbConfigPtr);
+      } while (CapabilityPtr !=  0);
+    }
+  }
+  return  0;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read IO space
+ *
+ *
+ *
+ * @param[in] Address     IO Port address.
+ * @param[in] Width       Access width
+ * @param[in] Value       Pointer to save IO port value;
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbIoRead (
+  IN       UINT16         Address,
+  IN       ACCESS_WIDTH   Width,
+     OUT   VOID           *Value,
+  IN       AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  LibAmdIoRead (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write IO space
+ *
+ *
+ *
+ * @param[in] Address     IO Port address.
+ * @param[in] Width       Access width
+ * @param[in] Value       Pointer to new IO port value
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+VOID
+LibNbIoWrite (
+  IN      UINT16         Address,
+  IN      ACCESS_WIDTH   Width,
+  IN      VOID           *Value,
+  IN      AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  LibAmdIoWrite (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write IO space
+ *
+ *
+ *
+ * @param[in] Address     IO Port address.
+ * @param[in] Width       Access width
+ * @param[in] Mask       AND Mask
+ * @param[in] Data       OR Mask
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbIoRMW (
+  IN      UINT16         Address,
+  IN      ACCESS_WIDTH   Width,
+  IN      UINT32         Mask,
+  IN      UINT32         Data,
+  IN      AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  UINT32  Value;
+  LibNbIoRead (Address, Width, &Value, NbConfigPtr);
+  Value = (Value & Mask) | Data;
+  LibNbIoWrite (Address, Width, &Value, NbConfigPtr);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read CPU HT link Phy register
+ *
+ *
+ *
+ * @param[in] Node        Node device Address (0x18 - Node 0, 0x19 - Mode 1 etc.)
+ * @param[in] Link        HT Link ID (0 - Link 0, 1 - Link 1 etc.)
+ * @param[in] Register    Register address.
+ * @param[in] Value       Pointer to save register value
+ * @param[in] NbConfigPtr Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbCpuHTLinkPhyRead (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       UINT16        Register,
+     OUT   UINT32        *Value,
+  IN       AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT32    Data;
+  PCI_ADDR  CpuPciAddress;
+  UINT8     LinkId;
+  LinkId = Link & 0xf;
+  CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, Node, 4, 0);
+  LibNbPciRMW (CpuPciAddress.AddressValue | (LinkId * 8 + 0x180), AccessWidth32, 0x0, Register | ((Register & 0xfe00)?BIT29:0), NbConfigPtr);
+  do {
+    LibNbPciRead (CpuPciAddress.AddressValue | (LinkId * 8 + 0x180), AccessWidth32, &Data, NbConfigPtr);
+  } while ((Data & BIT31) == 0);
+  LibNbPciRead (CpuPciAddress.AddressValue | (LinkId * 8 + 0x184), AccessWidth32, Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write CPU HT link Phy register
+ *
+ *
+ *
+ * @param[in] Node        Node device Address (0x18 - Node 0, 0x19 - Mode 1 etc.)
+ * @param[in] Link        HT Link ID (0 - Link 0, 1 - Link 1 etc.)
+ * @param[in] Register    Register address.
+ * @param[in] Value       Pointer to new register value
+ * @param[in] NbConfigPtr Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbCpuHTLinkPhyWrite (
+  IN       UINT8         Node,
+  IN       UINT8         Link,
+  IN       UINT16        Register,
+  IN       UINT32        *Value,
+  IN       AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  UINT32    Data;
+  PCI_ADDR  CpuPciAddress;
+  UINT8     LinkId;
+  LinkId = Link & 0xf;
+  CpuPciAddress.AddressValue = MAKE_SBDFO (0, 0, Node, 4, 0);
+  LibNbPciWrite (CpuPciAddress.AddressValue | (LinkId * 8 + 0x184), AccessWidth32, Value, NbConfigPtr);
+  LibNbPciRMW (CpuPciAddress.AddressValue | (LinkId * 8 + 0x180), AccessWidth32, 0x0, Register | BIT30 | ((Register & 0xfe00)?BIT29:0), NbConfigPtr);
+  do {
+    LibNbPciRead (CpuPciAddress.AddressValue | (LinkId * 8 + 0x180), AccessWidth32, &Data, NbConfigPtr);
+  } while ((Data & BIT31) == 0);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Read/Modify/Write CPU HT link Phy register
+ *
+ *
+ *
+ * @param[in] Node        Node device Address (0x18 - Node 0, 0x19 - Mode 1 etc.)
+ * @param[in] Link        HT Link ID (0 - Link 0, 1 - Link 1 etc.)
+ * @param[in] Register    Register address.
+ * @param[in] Mask        AND Mask.
+ * @param[in] Data        OR Mask.
+ * @param[in] NbConfigPtr Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+LibNbCpuHTLinkPhyRMW (
+  IN       UINT8           Node,
+  IN       UINT8           Link,
+  IN       UINT16          Register,
+  IN       UINT32          Mask,
+  IN       UINT32          Data,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32  Value;
+  LibNbCpuHTLinkPhyRead (Node, Link, Register, &Value, NbConfigPtr);
+  Value = (Value & Mask) | Data;
+  LibNbCpuHTLinkPhyWrite (Node, Link, Register, &Value, NbConfigPtr);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Clock Config space access.
+ *    Enable access to Clock Config Space at 0:0:1 PCI address.
+ *
+ *
+ * @param[in] pConfig Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbEnableClkConfig (
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  LibNbPciRMW (NB_SBDFO | NB_PCI_REG4C, AccessS3SaveWidth8, (UINT32)~BIT0, BIT0, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Disable Clock Config space access.
+ *    Disable access to Clock Config Space at 0:0:1 PCI address.
+ *
+ *
+ * @param[in] pConfig Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbDisableClkConfig (
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  LibNbPciRMW (NB_SBDFO | NB_PCI_REG4C, AccessS3SaveWidth8, (UINT32)~BIT0, 0x0 , pConfig);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if PCI Device Present
+ *
+ *
+ *
+ * @param[in] Device      Device PCI address.
+ * @param[in] NbConfigPtr Northbridge configuration block pointer.
+ *
+ * @retval    TRUE        Device present.
+ * @retval    FALSE       Device not present.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+BOOLEAN
+LibNbIsDevicePresent (
+  IN      PCI_ADDR          Device,
+  IN      AMD_NB_CONFIG     *NbConfigPtr
+  )
+{
+  UINT32 VendorId;
+  LibNbPciRead (Device.AddressValue, AccessWidth32, &VendorId, NbConfigPtr);
+  return (VendorId == 0xffffffff)?FALSE:TRUE;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if IOMMU enabled
+ *
+ *
+ *
+ * @param[in] NbConfigPtr Northbridge configuration block pointer.
+ *
+ * @retval    TRUE        IOMMU not enabled.
+ * @retval    FALSE       IOMMU not enabled.
+ */
+/*----------------------------------------------------------------------------------------*/
+BOOLEAN
+LibNbIsIommuEnabled (
+  IN      AMD_NB_CONFIG     *NbConfigPtr
+  )
+{
+  PCI_ADDR  IommuAddress;
+  IommuAddress.AddressValue = NbConfigPtr->NbPciAddress.AddressValue;
+  IommuAddress.Address.Function = 2;
+  if (LibNbIsDevicePresent (IommuAddress, NbConfigPtr)) {
+    UINT8 Value;
+    LibNbPciRead (IommuAddress.AddressValue | 0x44, AccessWidth8, &Value, NbConfigPtr);
+    if ((Value & BIT0) != 0) {
+      return  TRUE;
+    }
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reverse bit in DWORD.
+ *    Reverse bits in bitfield inside DWORD.
+ *
+ *
+ * @param[in] Data        Value to reverse.
+ * @param[in] StartBit    Start bit.
+ * @param[in] StopBit     Stop bit.
+ * @retval                Reversed Value.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+UINT32
+LibNbBitReverse (
+  IN    UINT32    Data,
+  IN    UINT8     StartBit,
+  IN    UINT8     StopBit
+  )
+{
+
+  UINT32 Bitr;
+  UINT32 Bitl;
+  UINT32 Distance;
+
+  while (StartBit < StopBit) {
+    Bitr = Data & (1 << StartBit );
+    Bitl = Data & (1 << StopBit );
+    Distance =    StopBit - StartBit;
+    Data = (Data & ((UINT32)~(Bitl | Bitr))) | (Bitr << Distance ) | (Bitl >> Distance);
+    StartBit++;
+    StopBit--;
+  }
+  return Data;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read CPU family
+ *
+ *
+ *
+ * @retval  0xXX00000    CPU family.
+ *
+ */
+UINT32
+LibNbGetCpuFamily (
+  VOID
+  )
+{
+  CPUID_DATA Cpuid;
+  CpuidRead (0x1, &Cpuid);
+  return Cpuid.EAX_Reg & 0xff00000;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Load Firmware block
+ *
+ *
+ *
+ * @param[in]   Address             Address to load firmware
+ * @param[in]   Size                Firmware block size
+ * @param[in]   FirmwareBlockPtr    Pointer to firmware block
+ * @param[in]   NbConfigPtr         Northbridge configuration block pointer.
+ *
+ */
+VOID
+LibNbLoadMcuFirmwareBlock (
+  IN      UINT16          Address,
+  IN      UINT16          Size,
+  IN      UINT32          *FirmwareBlockPtr,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32    i;
+  PCI_ADDR  ClkPciAddress;
+  UINT32    Selector;
+
+  Selector =  (Address >=  0x200)?0x0000000:0x10000;
+  ClkPciAddress = NbConfigPtr->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  LibNbEnableClkConfig (NbConfigPtr);
+  for (i = 0; i < Size; i++) {
+    LibNbPciIndexWrite (ClkPciAddress.AddressValue | MC_CLK_INDEX, Selector | (Address + (i * 4)), AccessWidth32, &FirmwareBlockPtr[i], NbConfigPtr);
+  }
+  LibNbDisableClkConfig (NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read SMU firmware ram
+ *
+ *
+ *
+ * @param[in]   Address             Address to read
+ * @param[in]   NbConfigPtr         Northbridge configuration block pointer.
+ *
+ */
+UINT32
+LibNbReadMcuRam (
+  IN      UINT16          Address,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32    Value;
+  PCI_ADDR  ClkPciAddress;
+  UINT32    Selector;
+
+  Selector = (Address >=  0x200) ? 0x0000000 : 0x10000;
+  ClkPciAddress = NbConfigPtr->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  LibNbEnableClkConfig (NbConfigPtr);
+  LibNbPciIndexRead (ClkPciAddress.AddressValue | MC_CLK_INDEX, Selector | (Address), AccessWidth32, &Value, NbConfigPtr);
+  LibNbDisableClkConfig (NbConfigPtr);
+  return Value;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * MCU Control
+ *
+ *
+ *
+ * @param[in]   Operation       Set/Reset MCU controller
+ * @param[in]   NbConfigPtr     Northbridge configuration block pointer.
+ */
+VOID
+LibNbMcuControl (
+  IN      NB_MCU_MODE     Operation,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCI_ADDR  ClkPciAddress;
+  UINT32    Value;
+
+  Value =  (Operation == AssertReset)?0x00000ee1:0x00000ee2;
+  ClkPciAddress = NbConfigPtr->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "LibNbMcuControl Operation [0x%x]\n", Operation));
+  LibNbEnableClkConfig (NbConfigPtr);
+  LibNbPciIndexWrite (ClkPciAddress.AddressValue | MC_CLK_INDEX, 0x00030000, AccessWidth32, &Value, NbConfigPtr);
+  LibNbDisableClkConfig (NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read/Modify/Write memory space
+ *
+ *
+ *
+ * @param[in] Address     Memory address.
+ * @param[in] Width       Access width
+ * @param[in] Mask        AND Mask
+ * @param[in] Data        OR Mask
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbMemRMW (
+  IN      UINT64          Address,
+  IN      ACCESS_WIDTH    Width,
+  IN      UINT32          Mask,
+  IN      UINT32          Data,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32  Value;
+  LibNbMemRead (Address, Width, &Value, NbConfigPtr);
+  Value = (Value & Mask) | Data;
+  LibNbMemWrite (Address, Width, &Value, NbConfigPtr);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read memory space
+ *
+ *
+ *
+ * @param[in] Address     Memory address.
+ * @param[in] Width       Access width
+ * @param[in] Value       Pointer to memory to store value
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbMemRead (
+  IN      UINT64          Address,
+  IN      ACCESS_WIDTH    Width,
+  IN      VOID            *Value,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  LibAmdMemRead (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write memory space
+ *
+ *
+ *
+ * @param[in] Address     Memory address.
+ * @param[in] Width       Access width
+ * @param[in] Value       Pointer to memory to get value
+ * @param[in] NbConfigPtr Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbMemWrite (
+  IN       UINT64          Address,
+  IN       ACCESS_WIDTH    Width,
+     OUT   VOID            *Value,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  LibAmdMemWrite (Width, Address, Value, (AMD_CONFIG_PARAMS *)((NbConfigPtr == NULL)?NULL:GET_BLOCK_CONFIG_PTR (NbConfigPtr)));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Scan Pci Bridge
+ *
+ *
+ *
+ * @param[in]   This            Pointer to PCI topology scan protocol
+ * @param[in]   Bridge          Address of PCI to PCI bridge to scan.
+ */
+
+SCAN_STATUS
+LibNbScanPciBridgeBuses (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Bridge
+  )
+{
+  SCAN_STATUS Status;
+  UINT8       CurrentBus;
+  UINT8       MinBus;
+  UINT8       MaxBus;
+  PCI_ADDR    Device;
+
+  CIMX_ASSERT (This != NULL);
+  if (This->ScanBus == NULL) {
+    return  SCAN_FINISHED;
+  }
+  LibNbPciRead (Bridge.AddressValue | 0x19, AccessWidth8,  &MinBus, This->pConfig);
+  LibNbPciRead (Bridge.AddressValue | 0x1A, AccessWidth8,  &MaxBus, This->pConfig);
+  if (MinBus == 0 || MaxBus == 0) {
+    return  SCAN_FINISHED;
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Scan bridge %d:%d:%d \n", Bridge.Address.Bus, Bridge.Address.Device, Bridge.Address.Function));
+  for (CurrentBus = MinBus; CurrentBus <= MaxBus; CurrentBus++) {
+    Device.AddressValue = MAKE_SBDFO (0, CurrentBus, 0, 0, 0);
+    Status = This->ScanBus (This, Device);
+  }
+  return  SCAN_FINISHED;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Scan Pci Bus
+ *
+ *
+ *
+ * @param[in]   This            Pointer to PCI topology scan protocol
+ * @param[in]   Device          Pci address device to start bus scan from
+ */
+/*----------------------------------------------------------------------------------------*/
+SCAN_STATUS
+LibNbScanPciBus (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Device
+  )
+{
+  SCAN_STATUS Status;
+  UINT32      CurrentDevice;
+  CIMX_ASSERT (This != NULL);
+  if (This->ScanDevice == NULL) {
+    return  SCAN_FINISHED;
+  }
+  for (CurrentDevice = Device.Address.Device; CurrentDevice <= 0x1f; CurrentDevice++) {
+    Device.Address.Device = CurrentDevice;
+    if (LibNbIsDevicePresent (Device, This->pConfig)) {
+      Status = This->ScanDevice (This, Device);
+      if (Status == SCAN_STOP_BUS_ENUMERATION) {
+        return Status;
+      }
+
+    }
+  }
+  return  SCAN_FINISHED;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Scan Pci Device
+ *
+ *
+ *
+ * @param[in]   This            Pointer to PCI topology scan protocol
+ * @param[in]   Device          Pci address device to scan
+ */
+/*----------------------------------------------------------------------------------------*/
+
+SCAN_STATUS
+LibNbScanPciDevice (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Device
+  )
+{
+  SCAN_STATUS Status;
+  UINT8       Header;
+  UINT32      CurrentFunction;
+  UINT32      MaxFunction;
+  CIMX_ASSERT (This != NULL);
+  if (This->ScanFunction == NULL) {
+    return  SCAN_FINISHED;
+  }
+  LibNbPciRead (Device.AddressValue | 0x0E , AccessWidth8, &Header, This->pConfig);
+  MaxFunction = (Header & 0x80)?7:0;
+  for (CurrentFunction = Device.Address.Function; CurrentFunction <= MaxFunction; CurrentFunction++) {
+    Device.Address.Function = CurrentFunction;
+    if (LibNbIsDevicePresent (Device, This->pConfig)) {
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Scan function %d:%d:%d \n", Device.Address.Bus, Device.Address.Device, Device.Address.Function));
+      Status = This->ScanFunction (This, Device);
+      if (Status == SCAN_STOP_DEVICE_ENUMERATION || Status == SCAN_STOP_BUS_ENUMERATION) {
+        return Status;
+      }
+    }
+  }
+  return  SCAN_FINISHED;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set default Indexes
+ *
+ *
+ * @param[in]   NbConfigPtr     Northbridge configuration block pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+
+VOID
+LibNbSetDefaultIndexes (
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCI_ADDR  PciAddress;
+  PORT      PortId;
+  LibNbPciRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_HTIU_INDEX, AccessWidth32, 0x0, 0x0, NbConfigPtr);
+  LibNbPciRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, AccessWidth32, 0x0, 0x0, NbConfigPtr);
+  LibNbPciRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_BIF_INDEX,  AccessWidth32, 0x0, SB_CORE, NbConfigPtr);
+  PciAddress.AddressValue = NbConfigPtr->NbPciAddress.AddressValue;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    PciAddress.Address.Device = PortId;
+    LibNbPciRMW (PciAddress.AddressValue | NB_BIF_INDEX,  AccessWidth32, 0x0, 0x0, NbConfigPtr);
+  }
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbLib.h b/src/vendorcode/amd/cimx/rd890/nbLib.h
new file mode 100644
index 0000000..af10946
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbLib.h
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * CNB Library function
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBLIB_H_
+#define _NBLIB_H_
+
+#pragma pack(push, 1)
+
+/// NB_MCU_MODE
+typedef enum {
+  AssertReset,                              ///< Assert reset
+  DeAssertReset                             ///< Deassert reset
+} NB_MCU_MODE;
+
+/// SMU Firmware revision
+typedef struct {
+  UINT16              MajorRev;             ///< Major revision
+  UINT16              MinorRev;             ///< Minor revision
+} SMU_FIRMWARE_REV;
+
+/// Firmware block
+typedef struct {
+  UINT16              Address;              ///< Block Address
+  UINT16              Length;               ///< Block length in DWORD
+  UINT32              *Data;                ///< Pointer to data array
+} SMU_FIRMWARE_BLOCK;
+
+/// Firmware header
+typedef struct {
+  SMU_FIRMWARE_REV    Revision;              ///< Revision info
+  UINT16              NumberOfBlock;         ///< Number of blocks
+  SMU_FIRMWARE_BLOCK  *BlockArray;           ///< Pointer to block definition array
+} SMU_FIRMWARE_HEADER;
+
+
+NB_INFO
+LibNbGetRevisionInfo (
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+AGESA_STATUS
+LibNbCallBack (
+  IN      UINT32              CallBackId,
+  IN  OUT UINTN               Data,
+  IN  OUT AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciWrite (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciRead (
+  IN       UINT32              Address,
+  IN       ACCESS_WIDTH        Width,
+     OUT   VOID                *Value,
+  IN       AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciRMW (
+  IN      UINT32              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT32              Mask,
+  IN      UINT32              Data,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciIndexRead (
+  IN       UINT32              Address,
+  IN       UINT32              Index,
+  IN       ACCESS_WIDTH        Width,
+     OUT   UINT32              *Value,
+  IN       AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciIndexWrite (
+  IN      UINT32              Address,
+  IN      UINT32              Index,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT32              *Value,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbPciIndexRMW (
+  IN      UINT32              Address,
+  IN      UINT32              Index,
+  IN      ACCESS_WIDTH        Width,
+  IN      UINT32              Mask,
+  IN      UINT32              Data,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbIndirectTableInit (
+  IN      UINT32              Address,
+  IN      UINT32              Index,
+  IN      INDIRECT_REG_ENTRY  *pTable,
+  IN      UINTN               Length,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+UINT8
+LibNbFindPciCapability (
+  IN      UINT32              Address,
+  IN      UINT8               CapabilityId,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbIoRMW (
+  IN      UINT16              Address,
+  IN      ACCESS_WIDTH                Width,
+  IN      UINT32              Mask,
+  IN      UINT32              Data,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbCpuHTLinkPhyRead (
+  IN        UINT8               Node,
+  IN        UINT8               Link,
+  IN        UINT16              Register,
+     OUT    UINT32              *Value,
+  IN        AMD_NB_CONFIG        *NbConfigPtr
+ );
+
+VOID
+LibNbCpuHTLinkPhyWrite (
+  IN      UINT8               Node,
+  IN      UINT8               Link,
+  IN      UINT16              Register,
+  IN      UINT32              *Value,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+);
+
+VOID
+LibNbCpuHTLinkPhyRMW (
+  IN      UINT8               Node,
+  IN      UINT8               Link,
+  IN      UINT16              Register,
+  IN      UINT32              Mask,
+  IN      UINT32              Data,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+);
+
+VOID
+LibNbEnableClkConfig (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+LibNbDisableClkConfig (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+BOOLEAN
+LibNbIsDevicePresent (
+  IN      PCI_ADDR            Device,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+UINT32
+LibNbBitReverse (
+  IN      UINT32              Data,
+  IN      UINT8               StartBit,
+  IN      UINT8               StopBit
+  );
+
+UINT32
+LibNbGetCpuFamily (
+  VOID
+  );
+
+VOID
+LibNbIoWrite (
+  IN      UINT16              Address,
+  IN      ACCESS_WIDTH        Width,
+  IN      VOID                *Value,
+  IN      AMD_NB_CONFIG       *NbConfigPtr
+  );
+
+VOID
+LibNbIoRead (
+  IN       UINT16             Address,
+  IN       ACCESS_WIDTH       Width,
+     OUT   VOID               *Value,
+  IN       AMD_NB_CONFIG      *NbConfigPtr
+  );
+
+VOID
+LibNbLoadMcuFirmwareBlock (
+  IN      UINT16          Address,
+  IN      UINT16          Size,
+  IN      UINT32          *FirmwareBlockPtr,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+UINT32
+LibNbReadMcuRam (
+  IN      UINT16          Address,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+VOID
+LibNbMcuControl (
+  IN      NB_MCU_MODE     Operation,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+
+AGESA_STATUS
+LibSystemApiCall (
+  IN       SYSTEM_API            SystemApi,
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+AGESA_STATUS
+LibNbApiCall (
+  IN       NB_API                NbApi,
+  IN OUT   AMD_NB_CONFIG_BLOCK   *ConfigPtr
+  );
+
+VOID
+LibNbMemRMW (
+  IN      UINT64          Address,
+  IN      ACCESS_WIDTH    Width,
+  IN      UINT32          Mask,
+  IN      UINT32          Data,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+VOID
+LibNbMemRead (
+  IN      UINT64          Address,
+  IN      ACCESS_WIDTH    Width,
+  IN      VOID            *Value,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+VOID
+LibNbMemWrite (
+  IN      UINT64          Address,
+  IN      ACCESS_WIDTH    Width,
+     OUT  VOID            *Value,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+struct _PCI_SCAN_PROTOCOL;
+typedef struct _PCI_SCAN_PROTOCOL PCI_SCAN_PROTOCOL;
+typedef UINT32  SCAN_STATUS;
+
+typedef SCAN_STATUS (*SCAN_ENTRY) (PCI_SCAN_PROTOCOL *This, PCI_ADDR  Device);
+
+#define SCAN_FINISHED                   0x0
+#define SCAN_STOP_DEVICE_ENUMERATION    0x1
+#define SCAN_STOP_BUS_ENUMERATION       0x2
+
+
+/// PCI topology scan protocol
+struct _PCI_SCAN_PROTOCOL {
+  SCAN_ENTRY    ScanBus;                ///< Pointer to function to scan device on PCI bus.
+  SCAN_ENTRY    ScanDevice;             ///< Pointer to function to scan function on PCI device.
+  SCAN_ENTRY    ScanFunction;           ///< Pointer to scan PCI function.
+  AMD_NB_CONFIG *pConfig;               ///< NB configuration info.
+};
+
+SCAN_STATUS
+LibNbScanPciBus (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Device
+  );
+
+SCAN_STATUS
+LibNbScanPciDevice (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Device
+  );
+
+SCAN_STATUS
+LibNbScanPciBridgeBuses (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Bridge
+  );
+
+VOID
+LibNbSetDefaultIndexes (
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+UINT16
+LibNbFindPcieExtendedCapability (
+  IN      UINT32        Address,
+  IN      UINT16        ExtendedCapabilityId,
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  );
+
+BOOLEAN
+LibNbIsIommuEnabled (
+  IN      AMD_NB_CONFIG     *NbConfigPtr
+  );
+
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
new file mode 100644
index 0000000..8394835
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.c
@@ -0,0 +1,121 @@
+/**
+ * @file
+ *
+ * NB RAS
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern  UINT16 NbInitMaskedMemoryLength;
+
+typedef VOID (*MASKED_MEMORY_INIT_PROC) (IN UINT32 PciAddress, IN UINT16 AlinkAddress);
+
+
+AGESA_STATUS
+AmdMaskedMemoryInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (NbMaskedMemoryInit, ConfigPtr);
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Mask Memory
+ *
+ *
+ *
+ * @param[in] pConfig Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+NbMaskedMemoryInit (
+  IN      AMD_NB_CONFIG  *pConfig
+  )
+{
+  AGESA_STATUS            Status;
+  UINT8                   ExecutionBuffer[300];
+  SCRATCH_1               Scratch;
+  UINT16                  AlinkPort;
+
+  Status = AGESA_SUCCESS;
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+  if (Scratch.MaskMemoryInit == OFF) {
+    return  Status;
+  }
+  Scratch.MaskMemoryInit = OFF;
+  LibNbPciIndexWrite (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+  CIMX_ASSERT (NbInitMaskedMemoryLength < 300);
+  LibAmdMemCopy ((VOID*)ExecutionBuffer, (VOID*) (UINTN)NbInitMaskedMemory, NbInitMaskedMemoryLength, (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+  PcieSbAgetAlinkIoAddress (&AlinkPort, pConfig);
+  (*((MASKED_MEMORY_INIT_PROC)(UINTN)ExecutionBuffer))(pConfig->NbPciAddress.AddressValue, AlinkPort);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG87, AccessS3SaveWidth32, 0x0, 0xffffffff, pConfig);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG88, AccessS3SaveWidth32, 0x0, 0xffffffff, pConfig);
+  return Status;
+}
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.h b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.h
new file mode 100644
index 0000000..c364fe2
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit.h
@@ -0,0 +1,63 @@
+/**
+ * @file
+ *
+ * NB RAS
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBMASKEDMEMORYINIT_H_
+#define _NBMASKEDMEMORYINIT_H_
+
+AGESA_STATUS
+AmdMaskedMemoryInit (
+  IN OUT  AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+NbMaskedMemoryInit (
+  IN      AMD_NB_CONFIG         *pConfig
+  );
+
+VOID
+NbInitMaskedMemory (
+  IN      UINT32                PciAddress,
+  IN      UINT16                AlinkAddress
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S
new file mode 100644
index 0000000..3c148aa
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbMaskedMemoryInit32.S
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/******************************************************************************
+* CIMX Northbridge
+*
+* Contains CIMX 32 bit library code
+*
+* Description: nbMaskedMemoryInit32.S - nb Masked Memory Init 32bit ASM code
+*
+******************************************************************************/
+
+.altmacro
+
+#include <cpu/x86/post_code.h>
+
+        .section ".text"
+        .code32
+        .globl NbInitMaskedMemory, NbInitMaskedMemoryLength
+
+/*
+* PciAddress   = 8(%ebp)
+* AlinkAddress = 12(%ebp)
+*/
+.type NbInitMaskedMemory, @function
+
+NbInitMaskedMemory:
+        push    %ebp
+        movl     %esp, %ebp
+        pusha
+        cmp $0, 12(%ebp)
+        jz	0f
+        mov 12(%ebp), %dx
+        mov $0x80000004, %eax
+        out %eax, %dx
+        add $4, %dx
+        in %dx, %eax
+        btr $2, %eax
+        out %eax, %dx
+       0:
+        mov 8(%ebp), %eax
+        shr $4, %eax
+        or  $0x80000060, %eax
+        mov %eax, %ebx
+        mov $0x0cf8, %dx
+        out %eax, %dx
+        mov $0x0cfc, %dx
+        mov $(0x80 | 0x1B), %eax      # NB_MISC_REG1B
+        out %eax, %dx
+        mov %ebx, %eax
+        mov $0x64, %al
+        mov $0x0cf8, %dx
+        out %eax, %dx
+        mov $0x0cfc, %dx
+        in  %dx, %eax
+        and $(~(0x01ff << 21)), %eax
+        bts $15, %eax
+        xor %ecx, %ecx
+        out %eax, %dx
+StartInit:
+        and $(~(0xff << 22)), %eax
+        shl $22, %ecx
+        or  %ecx, %eax
+        shr $22, %ecx
+        out %eax, %dx
+        bts $21, %eax
+        out %eax, %dx
+        btr $21, %eax
+        out %eax, %dx
+        cmp $0x0ff, %cl
+        je  DoneInit
+        inc %ecx
+        jmp StartInit
+DoneInit:
+        btr $15, %eax
+        out %eax, %dx
+        cmp $0, 12(%ebp)
+        jz	1f
+        mov 12(%ebp), %dx
+        mov $0x80000004, %eax
+        out %eax, %dx
+        add $4, %dx
+        in  %dx, %eax
+        bts $2, %eax
+        out %eax, %dx
+        1:
+        popa
+	movl %ebp, %esp
+        pop     %ebp
+        ret
+NbInitMaskedMemoryLength = ( . - NbInitMaskedMemory)
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbMiscInit.c b/src/vendorcode/amd/cimx/rd890/nbMiscInit.c
new file mode 100644
index 0000000..ded6934
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbMiscInit.c
@@ -0,0 +1,123 @@
+/**
+ * @file
+ *
+ * NB Initialization.
+ *
+ * Init IOAPIC/IOMMU/Misc NB features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for all NB.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdMiscInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (MiscInitializer, ConfigPtr);
+  return Status;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB structure initializer.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr    Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+MiscInitializer (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  )
+{
+  AMD_NB_CONFIG_BLOCK *ConfigPtr;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMiscInitializer Enter\n"));
+  ConfigPtr = GET_BLOCK_CONFIG_PTR (NbConfigPtr);
+  if (ConfigPtr == NULL) {
+    return  AGESA_FATAL;
+  }
+  if (ConfigPtr->PlatformType == DetectPlatform) {
+    NB_INFO NbInfo;
+    NbInfo = LibNbGetRevisionInfo (NbConfigPtr);
+    if (NbInfo.Type != NB_UNKNOWN && NbInfo.Type >= NB_SR5690 && NbInfo.Type <= NB_SR5650) {
+      ConfigPtr->PlatformType = ServerPlatform;
+    } else {
+      ConfigPtr->PlatformType = DesktopPlatform;
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NB_TRACE), "[NB]NbMiscInitializer Exit\n"));
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbMiscInit.h b/src/vendorcode/amd/cimx/rd890/nbMiscInit.h
new file mode 100644
index 0000000..2537e78
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbMiscInit.h
@@ -0,0 +1,57 @@
+/**
+ * @file
+ *
+ * NB definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBMISCINIT_H_
+#define _NBMISCINIT_H_
+
+AGESA_STATUS
+AmdMiscInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+AGESA_STATUS
+MiscInitializer (
+  IN OUT   AMD_NB_CONFIG  *NbConfigPtr
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbModuleInfo.c b/src/vendorcode/amd/cimx/rd890/nbModuleInfo.c
new file mode 100644
index 0000000..175e3b3
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbModuleInfo.c
@@ -0,0 +1,70 @@
+/**
+ * @file
+ *
+ *  Function dispatcher.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+VOLATILE  AMD_MODULE_HEADER mNbModuleID = {
+//  'DOM$',
+  Int32FromChar ('D', 'O', 'M', '$'),
+  CIMX_NB_ID,
+  CIMX_NB_REVISION,
+  AmdNbDispatcher,
+  NULL
+};
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcie.h b/src/vendorcode/amd/cimx/rd890/nbPcie.h
new file mode 100644
index 0000000..5012058
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcie.h
@@ -0,0 +1,352 @@
+/**
+ * @file
+ *
+ * PCIE definitions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIE_H_
+#define _NBPCIE_H_
+
+#pragma pack(push, 1)
+
+/// PCIe Link Aspm mode
+typedef enum {
+  PcieLinkAspmDisabled,                     ///< Disabled
+  PcieLinkAspmL0s,                          ///< L0s only
+  PcieLinkAspmL1,                           ///< L1 only
+  PcieLinkAspmL0sAndL1,                     ///< L0s and L1
+  PcieLinkAspmL0sDownstreamOnly,            ///< L0s Donnstream Port Only
+  PcieLinkAspmL0sDownstreamOnlyAndL1        ///< L0s Donnstream Port and L1
+} PCIE_LINK_ASPM;
+
+/// PCIe device type
+typedef enum {
+  PcieDeviceEndPoint,                       ///< Endpoint
+  PcieDeviceLegacyEndPoint,                 ///< Legacy endpoint
+  PcieDeviceRootComplex = 4,                ///< Root complex
+  PcieDeviceUpstreamPort,                   ///< Upstream port
+  PcieDeviceDownstreamPort,                 ///< Downstream Port
+  PcieDevicePcieToPcix,                     ///< PCIe to PCI/PCIx bridge
+  PcieDevicePcixToPcie,                     ///< PCI/PCIx to PCIe bridge
+  PcieNotPcieDevice = 0xff                  ///< unknown device
+} PCIE_DEVICE_TYPE;
+
+/// PCIe Link Mode
+typedef enum {
+  PcieLinkModeGen2,                         ///< Gen 2
+  PcieLinkModeGen1,                         ///< Gen 1
+  PcieLinkModeGen2SoftwareInitiated,        ///< Gen 2 software
+  PcieLinkModeGen2AdvertizeOnly             ///< Gen 2 advertise only
+} PCIE_LINK_MODE;
+
+/// PCIE Link Status
+typedef enum {
+  PcieLinkStatusNotConnected,               ///< not connected
+  PcieLinkStatusConnected,                  ///< connected
+  PcieLinkStatusInCompliance,               ///< compliant
+  PcieLinkStatusTrainingInProgress,         ///< training in progress
+  PcieLinkStatusVcoNegotiationInProgress,   ///< Vco negotiation in progress
+} PCIE_LINK_STATUS;
+
+/// PCIE Link Width Information
+typedef enum {
+  PcieLinkMaxWidth,                         ///< max width
+  PcieLinkCurrentWidth,                     ///< current width
+} PCIE_LINK_WIDTH_INFO;
+
+/// PCIE Link Training
+typedef enum {
+  PcieLinkTrainingRelease,                  ///< training release
+  PcieLinkTrainingHold                      ///< training hold
+} PCIE_LINK_TRAINING;
+
+/// PCIE Strap Mode
+typedef enum {
+  PcieCoreStrapConfigStart,                 ///< start
+  PcieCoreStrapConfigStop                   ///< stop
+} PCIE_STRAP_MODE;
+
+/// PCIE Link Width
+typedef enum {
+  PcieLinkWidth_x0 = 0,                     ///< x0
+  PcieLinkWidth_x1 = 1,                     ///< x1
+  PcieLinkWidth_x2,                         ///< x2
+  PcieLinkWidth_x4,                         ///< x4
+  PcieLinkWidth_x8,                         ///< x8
+  PcieLinkWidth_x12,                        ///< x12
+  PcieLinkWidth_x16                         ///< x16
+} PCIE_LINK_WIDTH;
+
+/// PCIe Transmitter deemphasis advertise
+typedef enum {
+  PcieTxDeemphasis6dB = 0,                  ///< -6dB
+  PcieTxDeemphasis3p5dB,                    ///< -3.5dB
+} PCIE_LINK_DEEMPASIS;
+
+/// PCIe Transmitter deemphasis advertise
+typedef enum {
+  PcieTxDriveStrangth26mA = 0,              ///< 26mA
+  PcieTxDriveStrangth20mA,                  ///< 20mA
+  PcieTxDriveStrangth22mA,                  ///< 22mA
+  PcieTxDriveStrangth24mA,                  ///< 24mA
+} PCIE_LINK_DRIVE_STRANGTH;
+
+/// PCIe Channel type
+typedef enum {
+  PcieShortChannel   = 1,                   ///< Short Channel
+  PcieMediumChannel,                        ///< Medium Channel
+  PcieLongChannel,                          ///< Long Channel
+} NB_PCIE_CHANNEL_TYPE;
+
+/// PCI Core Reset
+typedef enum {
+  PcieCoreResetAllDeassert = 1,             ///< deassert
+  PcieCoreResetAllAssert,                   ///< assert
+  PcieCoreResetAllCheck,                    ///< check
+} PCI_CORE_RESET;
+
+/// Misc PCIE Core Setting
+typedef struct {
+  UINT32  CoreDisabled            :1;       ///< Core  not present or disabled
+  UINT32  PowerOffPll             :1;       ///< Enable power off PLL if group of lanes controlled by PLL unused
+  UINT32  PowerOffPllInL1         :1;       ///< Enable Power off PLL in L1
+  UINT32  LclkClockGating         :1;       ///< Enable LCLK clock gating
+  UINT32  TxClockGating           :1;       ///< Enable TX clock gating
+  UINT32  PowerOffUnusedLanes     :1;       ///< Enable Power off pads for unused Lanes
+  UINT32  CplBufferAllocation     :1;       ///< Enable special/optimized CPL buffer allocation
+  UINT32  PerformanceMode         :1;       ///< Enable support PCIe Reference Clock overclocking. In addition to rump-up PCIe reference clock
+  UINT32  TxDriveStrength         :2;       /**< TX Drive strength (Only applicable if PCIE_CORE_SETTING::ChannelType == 0).
+                                             *   @li @b 0 - 26mA
+                                             *   @li @b 1 - 20mA
+                                             *   @li @b 2 - 22mA
+                                             *   @li @b 3 - 24mA
+                                             */
+  UINT32  SkipConfiguration       :1;       ///< Special case to skip core configuration (configured outside of CIMx)
+  UINT32  TxHalfSwingMode         :1;       ///< Half Swing Mode for PCIe Transmitters (Only applicable if PCIE_CORE_SETTING::ChannelType == 0).
+  UINT32  ChannelType             :3;        /**< Group PCIe PHY setting for channel with specific trace length
+                                             *   @li @b 0 - Use individual parameters to configure PCIe PHY (see PCIE_CORE_SETTING::TxHalfSwingMode,
+                                                 PCIE_CORE_SETTING::TxDriveStrength, PCIE_EXT_PORT_CONFIG::PortDeemphasis).
+                                             *   @li @b 1 - Short Channel.
+                                             *   @li @b 2 - Midium Channel.
+                                             *   @li @b 3 - Long  Channel.
+                                             */
+  UINT32  DetectPowerOffPllInL1   :1;       ///< Enable detection if endpoint L1 acceptable latency allow Enable Power off PLL in L1.
+  UINT32  TxClockOff              :1;       ///< Disable TX clock if possible
+  UINT32  LclkClockOff            :1;       ///< Disable LCLK clock if possible
+  UINT32  RefClockInput           :1;       ///< Use dedicated ref. clock input (only applicable GPP1 and GPP2 cores). By default SB ref clock is used.
+  UINT32  Reserved                :2;       ///<
+  UINT32  CoreDisableStatus       :1;       /**< Output status of core disable/enable
+                                             *   @li @b 0 = Core not disabled
+                                             *   @li @b 1 = Core Disabled
+                                             */
+} PCIE_CORE_SETTING;
+
+/// Misc Configuration
+typedef struct {
+  UINT32  DisableHideUnusedPorts  :1;       ///< Hide unused ports if no EP was detected and port  non hotpluggable
+  UINT32  Peer2Peer               :1;       ///< Enable Peer to Peer.
+  UINT32  DisableGfxWorkaround    :1;       ///< disable RV370/RV380 workaround
+  UINT32  NbSbVc1                 :1;       ///< Enable VC1 for NB SB Audio traffic
+} PCIE_MISC_CONFIG;
+
+/// Extended PCIE Port Configuration
+typedef struct {
+  UINT32  PortL1ImmediateACK      :1;       ///< Validation feature
+  UINT32  PortLinkWidth           :3;       /**< Port Link width
+                                             *   @li @b 0 - Auto. Default max link width.
+                                             *   @li @b 1 - x1
+                                             *   @li @b 2 - x2
+                                             *   @li @b 3 - x4
+                                             *   @li @b 4 - x8
+                                             *   @li @b 6 - x16
+                                             */
+  UINT32  PortMapping             :4;       /**< Device number mapping info
+                                             *   @li @b 0 - Default mapping
+                                             *   @li @b n - PCI device number for port (Valid device numbers are 2/3/4/5/6/7/9/10/11/12/13).
+                                             */
+  UINT32  PortHotplugDevMap       :2;       /**< PCA9539 device map.
+                                             *Only valid if PortHotplug = 1
+                                             */
+  UINT32  PortHotplugByteMap      :1;       /**< PCA9539 channel map.
+                                             *Only valid if PortHotplug = 1
+                                             */
+  UINT32  PortPowerLimit          :8;       ///< Slot power limit in W
+  UINT32  Reserved                :2;       ///< Reserved
+  UINT32  PortDeemphasis          :2;       /**< Port deempasis adverise (Only applicable if PCIE_CORE_SETTING::ChannelType == 0).
+                                             *   @li @b 0 - 6dB
+                                             *   @li @b 1 - 3.5dB
+                                             */
+
+} PCIE_EXT_PORT_CONFIG;
+
+/// PCIE Port Configuration
+typedef struct {
+  UINT32  PortPresent             :1;       /**< Port connection
+                                             *   @li @b 0 - Port has no slot or EP connected. Link not needs to be trained.
+                                             *   @li @b 1 - Has slot or EP connected. Link needs to be trained.
+                                             */
+  UINT32  PortDetected            :1;       /**< Scratch bit to record status of training
+                                             *   @li @b 0 - EP not detected
+                                             *   @li @b 1 - EP detected
+                                             */
+  UINT32  PortCompliance          :1;       /**< Link compliance mode
+                                             *   @li @b 0 - Link in operational mode
+                                             *   @li @b 1 - Force link into compliance mode
+                                             */
+  UINT32  PortLinkMode            :2;       /**< Link speed mode configuration
+                                             *   @li @b 0 - GEN2 Autonomous (GEN2 capability advertized and and immediate link speed change initiated).
+                                             *   @li @b 1 - GEN1
+                                             *   @li @b 2 - GEN2 Software Initiated (Port trained to Gen1 thereafter if EP report GEN2 capability port reconfigured to GEN2)
+                                             *   @li @b 3 - GEN2 advertize only (RC only advertize GEN2 capability and not initiate transition to GEN2 speed)
+                                             */
+  UINT32  PortHotplug             :2;       /**< Port Hotplug configuration
+                                             *   @li @b 0 - Hotplug Disabled
+                                             *   @li @b 1 - Server Hotplug Enabled
+                                             *   @li @b 2 - Reserved
+                                             *   @li @b 3 - Reserved
+                                             */
+  UINT32  PortAspm                :3;       /**< Port ASPM support
+                                             *   @li @b 0 - Disabled
+                                             *   @li @b 1 - L0s enable
+                                             *   @li @b 2 - L1 enable
+                                             *   @li @b 3 - L0s + L1 enable
+                                             *   @li @b 4 - L0s Downstream Only
+                                             *   @li @b 5 - L0s Downstream Only + L1
+                                             *   @li <b>4..7</b> - Reserved
+                                             */
+  UINT32  PortReversed            :1;       /**< Port lanes reversed
+                                             *   @li @b 0 - Lanes non reversed
+                                             *   @li @b 1 - Lanes reversed
+                                             */
+  UINT32  ForcePortDisable        :1;       /**< Port Disable after PCIE training
+                                             *   @li @b 0 - Do not force port disable
+                                             *   @li @b 1 - Force port disable
+                                             */
+  UINT32  PortAlwaysVisible       :1;       /**< Port always visible
+                                             *   @li @b 1 - Port always visible
+                                             */
+} PCIE_PORT_CONFIG;
+
+/// PCIE default configuration parameters structure
+typedef  struct {
+  PCIE_MISC_CONFIG          PcieConfiguration;        ///< PCIE configuration
+  PCIE_CORE_SETTING         CoreSetting[5];           ///< Core Setting
+  UINT16                    DeviceInitMaskS1;         ///< Bit mask of ports id to be initialized at stage 1
+  UINT16                    DeviceInitMaskS2;         ///< Bit mask of ports id to be initialized at stage 2
+  UINT16                    ResetToTrainingDelay;     ///< Delay (in 1ms) after reset deassert before training started
+  UINT16                    TrainingToLinkTestDelay;  ///< Delay (in 1ms) after training started but before pooling link state
+  UINT16                    ReceiverDetectionPooling; ///< Total amount time (in 1ms of pooling for passing receiver detection stage
+} PCIE_DEFAULT_CONFIG;
+
+/// Link Info
+typedef struct {
+  UINT8                     LinkWidth;                ///< width
+  UINT8                     MaxLinkWidth;             ///< max width
+  UINT8                     Line0Offset;              ///< line 0 offset
+} LINK_INFO;
+
+/// Port Static Info
+typedef struct {
+  UINT8                     TrainingAddress;          ///< training address
+  UINT8                     ReversalAddress;          ///< reversal address
+  UINT8                     DeemphasisAddress;        ///< de-emphasis address
+  UINT8                     MappingAddress;           ///< mapping address
+  UINT8                     HotplugAddress;           ///< Hotplug address
+} PORT_STATIC_INFO;
+
+/// Core Info
+typedef struct {
+  UINT32                    CoreSelector;                   ///< core selector
+  UINT16                    PortIdBitMap;                   ///< port Id
+  UINT8                     TrainingRegister;               ///< training
+  UINT8                     DeemphasisRegister;             ///< de-emphasis
+  UINT8                     StrapRegister;                  ///< strap
+  UINT8                     StrapAddress;                   ///< strap address
+  UINT8                     HotplugRegister;                ///< Hotplug descriptor register
+  UINT8                     TxDriveStrengthRegister;        ///< Tx drive strength register
+  UINT8                     TxDriveStrengthOffset;          ///< Tx drive strength bit offeset
+  UINT8                     TxHalfSwingRegister;            ///< Tx half swing register
+  UINT8                     TxHalfSwingOffset;              ///< Tx half swing bit offset
+  UINT8                     TxHalfSwingDeepmhasisRegister;  ///< Tx half swing deephasis register
+  UINT8                     TxHalfSwingDeepmhasisOffset;    ///< Tx half swing deephasis register
+  UINT8                     TxOffOffset;                    ///< Tx shutdown enable offset
+  UINT8                     LclkOffOffset;                  ///< Lclk shutdown enable offset
+  UINT8                     LclkPermOffOffset;              ///< Lclk Perm shutdown enable offset
+} CORE_INFO;
+
+/// Port Information
+typedef struct {
+  UINT8     MaxLinkWidth;                   ///< max link width
+  UINT8     Line0Offset;                    ///< offset
+  UINT8     SlaveCplBuffers;                ///< Alternative to default CPL buffer count
+} PORT_INFO;
+
+/// GPP Configuration Info
+typedef struct {
+  PORT_INFO *PortInfoPtr;                   ///< port information
+  UINT32    PortIdMap;                      ///< port id map
+} GPP_CFG_INFO;
+
+
+#define   GPP1_CORE               0x40000
+#define   GPP2_CORE               0x60000
+#define   GPP3a_CORE              0x70000
+#define   GPP3b_CORE              0x30000
+#define   SB_CORE                 0x50000
+
+#define   GPP_CONFIG_GPP420000    0x01
+#define   GPP_CONFIG_GPP411000    0x02
+#define   GPP_CONFIG_GPP222000    0x03
+#define   GPP_CONFIG_GPP221100    0x04
+#define   GPP_CONFIG_GPP211110    0x05
+#define   GPP_CONFIG_GPP111111    0x06
+
+#define   GFX_CONFIG_A            0x01
+#define   GFX_CONFIG_B            0x02
+
+#define   GFX_CONFIG_AAAA         (GFX_CONFIG_A | (GFX_CONFIG_A << 8) | (GFX_CONFIG_A << 16) | (GFX_CONFIG_A << 24))
+#define   GFX_CONFIG_AABB         (GFX_CONFIG_A | (GFX_CONFIG_A << 8) | (GFX_CONFIG_B << 16) | (GFX_CONFIG_B << 24))
+
+#define   PCIE_CAP_ID             0x10
+
+
+#pragma pack(pop)
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
new file mode 100644
index 0000000..38bc41f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.c
@@ -0,0 +1,507 @@
+/**
+ * @file
+ *
+ * ASPM support.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+VOID
+PcieAspmSetOnRc (
+  IN      PCI_ADDR        Device,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+SCAN_STATUS
+PcieSetDeviceAspm (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Function
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Port ASPM.
+ * Enable ASPM states on RC and EP. Only states supported  by both RC and EP
+ * will be enabled.
+ *
+ *
+ * @param[in] PortId    Pcie Port ID
+ * @param[in] AsmpState ASPM states to enable.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+PcieAsmpEnableOnPort (
+  IN      PORT            PortId,
+  IN      PCIE_LINK_ASPM  AsmpState,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCI_ADDR  Port;
+  UINT8     Lx;
+  PCI_ADDR  NbPciAddress;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "PcieAsmpEnableOnPort Enter PortId [%d]\n", PortId));
+  NbPciAddress.AddressValue = NB_SBDFO;
+  switch (AsmpState) {
+  case PcieLinkAspmDisabled:
+    return ;
+  case PcieLinkAspmL0s:
+    Lx = ASPM_UPSTREAM_L0s | ASPM_DOWNSTREAM_L0s;
+    break;
+  case PcieLinkAspmL1:
+    Lx = ASPM_L1;
+    break;
+  case PcieLinkAspmL0sAndL1:
+    Lx = ASPM_UPSTREAM_L0s | ASPM_DOWNSTREAM_L0s | ASPM_L1;
+    break;
+  case PcieLinkAspmL0sDownstreamOnly:
+    Lx = ASPM_DOWNSTREAM_L0s;
+    break;
+  case PcieLinkAspmL0sDownstreamOnlyAndL1:
+    Lx = ASPM_DOWNSTREAM_L0s | ASPM_L1;
+    break;
+  default:
+    CIMX_ASSERT (FALSE);
+    return ;
+  }
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+//NB-SB link
+  if (PortId == 8 && NbPciAddress.AddressValue == 0) {
+    if (PcieSbInitAspm ((Lx & ASPM_L1) | ((Lx & ASPM_UPSTREAM_L0s)?ASPM_L0s:0), pConfig) == AGESA_SUCCESS) {
+      PcieAspmEnableOnFunction (Port, (Lx & ASPM_L1) | ((Lx & ASPM_DOWNSTREAM_L0s)?ASPM_L0s:0), pConfig);
+    }
+    return ;
+  }
+  PcieAspmSetOnRc (Port, Lx, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "PcieAsmpEnableOnPort Exit. Lx[0x%x]\n", Lx));
+  return ;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Common Clock on PCIe Link
+ *
+ *
+ *
+ * @param[in] Downstream  Downstream PCIe port PCI address
+ * @param[in] Upstream    Upstream PCIe port PCI address
+ * @param[in] pConfig     Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+VOID
+PcieAspmEnableCommonClock (
+  IN      PCI_ADDR        Downstream,
+  IN      PCI_ADDR        Upstream,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT16  DownstreamCommonClockCap;
+  UINT16  UpstreamCommonClockCap;
+  UINT16  Value;
+  UINT8   DownstreamPcieCapPtr;
+  UINT8   UpstreamPcieCapPtr;
+  DownstreamPcieCapPtr = LibNbFindPciCapability (Downstream.AddressValue, PCIE_CAP_ID, pConfig);
+  UpstreamPcieCapPtr = LibNbFindPciCapability (Upstream.AddressValue, PCIE_CAP_ID, pConfig);
+  if (DownstreamPcieCapPtr == 0 || UpstreamPcieCapPtr == 0) {
+    return ;
+  }
+  LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessWidth16, &DownstreamCommonClockCap, pConfig);
+  if ((DownstreamCommonClockCap & BIT6) != 0) {
+    //Aready enabled
+    return ;
+  }
+  LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x12) , AccessWidth16, &DownstreamCommonClockCap, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Downstream Common Clock Capability %d:%d:%d - %x\n", Downstream.Address.Bus, Downstream.Address.Device, Downstream.Address.Function,  DownstreamCommonClockCap));
+  LibNbPciRead (Upstream.AddressValue | (UpstreamPcieCapPtr + 0x12) , AccessWidth16, &UpstreamCommonClockCap, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Upstream   Common Clock Capability %d:%d:%d - %x\n", Upstream.Address.Bus, Upstream.Address.Device, Upstream.Address.Function,  UpstreamCommonClockCap));
+  if ((DownstreamCommonClockCap & UpstreamCommonClockCap & BIT12) != 0) {
+    //Enable common clock
+    PcieAspmCommonClockOnFunction (Downstream, pConfig);
+    PcieAspmCommonClockOnDevice (Upstream, pConfig);
+//    LibNbPciRMW (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT6, pConfig);
+//    LibNbPciRMW (Upstream.AddressValue | (UpstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT6, pConfig);
+    //Reatrain link
+    LibNbPciRMW (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x10) , AccessS3SaveWidth8, 0xff, BIT5, pConfig);
+    do {
+      LibNbPciRead (Downstream.AddressValue | (DownstreamPcieCapPtr + 0x12) , AccessWidth16, (UINT16*)&Value, pConfig);
+      STALL (GET_BLOCK_CONFIG_PTR (pConfig), 200, CIMX_S3_SAVE);
+    } while ((Value & BIT11) != 0);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set  "Common Clock" enable on function
+ *
+ *
+ *
+ * @param[in] Device      PCI address of function.
+ * @param[in] pConfig     Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmCommonClockOnDevice (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8 Value;
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+  LibNbPciRead (Device.AddressValue | 0x0E , AccessWidth8, &Value, pConfig);
+  MaxFunc = (Value & BIT7)?7:0;
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (LibNbIsDevicePresent (Device, pConfig)) {
+      PcieAspmCommonClockOnFunction (Device, pConfig);
+    }
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set  "Common Clock" enable on function
+ *
+ *
+ *
+ * @param[in] Function    PCI address of function.
+ * @param[in] pConfig     Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmCommonClockOnFunction (
+  IN      PCI_ADDR        Function,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = LibNbFindPciCapability (Function.AddressValue, PCIE_CAP_ID, pConfig);
+  if (PcieCapPtr != 0) {
+    LibNbPciRMW (Function.AddressValue | (PcieCapPtr + 0x10) , AccessS3SaveWidth8, (UINT32)~(BIT6), BIT6, pConfig);
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable ASPM on PCIe Link
+ *
+ *
+ *
+ * @param[in] Downstream  Downstream PCIe port PCI address
+ * @param[in] Upstream    Upstream PCIe port PCI address
+ * @param[in] Lx          Lx ASPM bitmap.
+ *                          Lx[0] - reserved
+ *                          Lx[1] - L1 enable
+ *                          Lx[2] - L0s enable for upstream ports
+ *                          Lx[3] - L0s enable for downstream ports
+ * @param[in] pConfig     Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+VOID
+PcieAspmEnableOnLink (
+  IN      PCI_ADDR        Downstream,
+  IN      PCI_ADDR        Upstream,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  ASPM_LINK_INFO AspmLinkInfo;
+  AspmLinkInfo.UpstreamLxCap = PcieAspmGetPmCapability (Upstream, pConfig);
+  AspmLinkInfo.DownstreamLxCap = PcieAspmGetPmCapability (Downstream, pConfig);
+  AspmLinkInfo.DownstreamPort = Downstream;
+  AspmLinkInfo.UpstreamPort = Upstream;
+  AspmLinkInfo.RequestedLx = Lx;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Downstream ASPM Capability %d:%d:%d - %x\n", Downstream.Address.Bus, Downstream.Address.Device, Downstream.Address.Function,  AspmLinkInfo.DownstreamLxCap));
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Upstream   ASPM Capability %d:%d:%d - %x\n", Upstream.Address.Bus, Upstream.Address.Device, Upstream.Address.Function,  AspmLinkInfo.UpstreamLxCap));
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Requested  ASPM State - %x\n", Lx));
+  AspmLinkInfo.DownstreamLx = AspmLinkInfo.UpstreamLxCap & AspmLinkInfo.DownstreamLxCap & Lx & ASPM_L1;
+  AspmLinkInfo.UpstreamLx = AspmLinkInfo.DownstreamLx;
+  if ((AspmLinkInfo.UpstreamLxCap & ASPM_L0s) != 0 && (Lx & ASPM_UPSTREAM_L0s) != 0) {
+    AspmLinkInfo.UpstreamLx |= ASPM_L0s;
+  }
+  if ((AspmLinkInfo.DownstreamLxCap & ASPM_L0s) != 0 && (Lx & ASPM_DOWNSTREAM_L0s) != 0) {
+    AspmLinkInfo.DownstreamLx |= ASPM_L0s;
+  }
+#ifndef ASPM_WORKAROUND_DISABLE
+  PcieAspmWorkarounds (&AspmLinkInfo, pConfig);
+#endif
+  LibNbCallBack (PHCB_AmdPcieAsmpInfo, (UINTN)&AspmLinkInfo, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Upstream   ASPM State - %x\n", AspmLinkInfo.UpstreamLx));
+  PcieAspmEnableOnDevice (Upstream, AspmLinkInfo.UpstreamLx, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Downstream ASPM State - %x\n", AspmLinkInfo.DownstreamLx));
+  PcieAspmEnableOnFunction (Downstream, AspmLinkInfo.DownstreamLx, pConfig);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set ASMP State on all function of PCI device
+ *
+ *
+ *
+ * @param[in] Device    PCI address of device.
+ * @param[in] Lx        Lx ASPM bitmap.
+ *                        Lx[0] = L0s enable
+ *                        Lx[1] - L1 enable
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmEnableOnDevice (
+  IN      PCI_ADDR        Device,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8 Value;
+  UINT8 MaxFunc;
+  UINT8 CurrentFunc;
+
+  LibNbPciRead (Device.AddressValue | 0x0E , AccessWidth8, &Value, pConfig);
+  MaxFunc = (Value & BIT7)?7:0;
+  for (CurrentFunc = 0; CurrentFunc <= MaxFunc; CurrentFunc++) {
+    Device.Address.Function = CurrentFunc;
+    if (LibNbIsDevicePresent (Device, pConfig)) {
+      PcieAspmEnableOnFunction (Device, Lx, pConfig);
+    }
+  }
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set  ASMP State on PCIe device function
+ *
+ *
+ *
+ * @param[in] Function    PCI address of function.
+ * @param[in] Lx          Lx ASPM bitmap.
+ *                          Lx[0] = L0s enable
+ *                          Lx[1] - L1 enable
+ * @param[in] pConfig     Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmEnableOnFunction (
+  IN      PCI_ADDR        Function,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8       PcieCapPtr;
+  PcieCapPtr = LibNbFindPciCapability (Function.AddressValue, PCIE_CAP_ID, pConfig);
+  if (PcieCapPtr != 0) {
+    LibNbPciRMW (Function.AddressValue | (PcieCapPtr + 0x10) , AccessS3SaveWidth8, (UINT32)~(BIT0 & BIT1), Lx, pConfig);
+  }
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Port/Endpoint ASMP capability
+ *
+ *
+ *
+ * @param[in] Device    PCI address of downstream port.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ * @retval    Bitmap of actual supported Lx states
+ */
+ /*----------------------------------------------------------------------------------------*/
+UINT8
+PcieAspmGetPmCapability (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8 PcieCapPtr;
+  UINT8 Value;
+  PcieCapPtr = LibNbFindPciCapability (Device.AddressValue, PCIE_CAP_ID, pConfig);
+  if (PcieCapPtr == 0) {
+    return 0;
+  }
+  LibNbPciRead (Device.AddressValue | (PcieCapPtr + 0x0D) , AccessWidth8, &Value, pConfig);
+  return (Value >> 2) & 3;
+}
+
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Scan PCIe topology
+ *
+ *
+ *
+ * @param[in] This          Pointer to instance of scan protocol
+ * @param[in] Function      PCI address of found device/function.
+ *
+ * @retval    SCAN_FINISHED Scan for device finished.
+ */
+ /*----------------------------------------------------------------------------------------*/
+SCAN_STATUS
+PcieSetDeviceAspm (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Function
+  )
+{
+  PCIE_DEVICE_TYPE  DeviceType;
+  UINT8             SecondaryBus;
+  ASPM_WORKSPACE    *WorkspacePtr;
+  WorkspacePtr =    (ASPM_WORKSPACE*)This;
+
+  DeviceType = PcieGetDeviceType (Function, This->pConfig);
+  if (DeviceType == PcieDeviceRootComplex || DeviceType == PcieDeviceDownstreamPort) {
+    PCI_ADDR        UpstreamDevice;
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Reached downstream port\n"));
+    //Lets enable Common clock
+    LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
+    LibNbPciRMW(Function.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffff, 0, This->pConfig);  //This done to help UEFI bootscript restore bud topology.
+    if (SecondaryBus == 0) {
+      return  SCAN_FINISHED;
+    }
+    //New Downstream Port
+    WorkspacePtr->LinkCount++;
+    if (WorkspacePtr->DownstreamPort.AddressValue == 0) {
+      WorkspacePtr->DownstreamPort.AddressValue = Function.AddressValue;
+    }
+    //Lets enable Common clock
+    UpstreamDevice.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    if (LibNbIsDevicePresent (UpstreamDevice, This->pConfig)) {
+      PcieAspmEnableCommonClock (Function, UpstreamDevice, This->pConfig);
+    }
+    This->ScanBus (This, UpstreamDevice);
+    if (WorkspacePtr->DownstreamPort.AddressValue == Function.AddressValue) {
+      WorkspacePtr->DownstreamPort.AddressValue = 0;
+      PcieAspmEnableOnLink (Function, UpstreamDevice, WorkspacePtr->Lx, This->pConfig);
+    }
+  } else if (DeviceType == PcieDeviceUpstreamPort ) {
+    PCI_ADDR DownstreamDevice;
+
+    if (WorkspacePtr->DownstreamPort.AddressValue == 0) {
+      return  SCAN_FINISHED;
+    }
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Reached upstream port\n"));
+    LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
+    LibNbPciRMW(Function.AddressValue | 0x18, AccessS3SaveWidth32, 0xffffffff, 0, This->pConfig); //This done to help UEFI bootscript restore bud topology.
+    if (SecondaryBus == 0) {
+      return  SCAN_FINISHED;
+    }
+    DownstreamDevice.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    This->ScanBus (This, DownstreamDevice);
+  } else if (DeviceType < PcieDeviceLegacyEndPoint) {
+    // We reach end of link @toDo code to check exit latency.
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Reached endpoint \n"));
+  }
+  return  SCAN_FINISHED;
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Scan RC PCIe topology to setup ASPM
+ *
+ *
+ *
+ * @param[in] Device    PCI address of downstream port.
+ * @param[in] Lx        Lx ASPM bitmap.
+ *                        Lx[0] - reserved
+ *                        Lx[1] - L1 enable
+ *                        Lx[2] - L0s enable for upstream ports
+ *                        Lx[3] - L0s enable for downstream ports
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+ /*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmSetOnRc (
+  IN      PCI_ADDR        Device,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  ASPM_WORKSPACE AspmWorkspace;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieSetPortAspm Enter\n"));
+  LibAmdMemFill (&AspmWorkspace, 0, sizeof (AspmWorkspace), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+  AspmWorkspace.ScanPciePort.pConfig = pConfig;
+  AspmWorkspace.ScanPciePort.ScanBus = LibNbScanPciBus;
+  AspmWorkspace.ScanPciePort.ScanDevice = LibNbScanPciDevice;
+  AspmWorkspace.ScanPciePort.ScanFunction = PcieSetDeviceAspm;
+  AspmWorkspace.Lx = Lx;
+  AspmWorkspace.ScanPciePort.ScanFunction (&AspmWorkspace.ScanPciePort, Device);
+  if (AspmWorkspace.LinkCount > 1) {
+    LibNbScanPciBridgeBuses (&AspmWorkspace.ScanPciePort, Device);
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieSetPortAspm Exit\n"));
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieAspm.h b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.h
new file mode 100644
index 0000000..63a88a0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieAspm.h
@@ -0,0 +1,131 @@
+/**
+ * @file
+ *
+ * ASPM support.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _NBPCIEASPM_H_
+#define _NBPCIEASPM_H_
+
+VOID
+PcieAsmpEnableOnPort (
+  IN      PORT            PortId,
+  IN      PCIE_LINK_ASPM  AsmpState,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+UINT8
+PcieAspmGetPmCapability (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+
+VOID
+PcieAspmEnableOnDevice (
+  IN      PCI_ADDR        Device,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+VOID
+PcieAspmEnableOnFunction (
+  IN      PCI_ADDR        Function,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+VOID
+PcieAspmEnableOnLink (
+  IN      PCI_ADDR        Downstream,
+  IN      PCI_ADDR        Upstream,
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+VOID
+PcieAspmEnableCommonClock (
+  IN      PCI_ADDR        Downstream,
+  IN      PCI_ADDR        Upstream,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+
+VOID
+PcieAspmCommonClockOnDevice (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+VOID
+PcieAspmCommonClockOnFunction (
+  IN      PCI_ADDR        Function,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+#pragma pack (push, 1)
+
+/// Framework for ASPM enable
+typedef struct  {
+  PCI_SCAN_PROTOCOL ScanPciePort;   ///< PCI scan protocol
+  PCI_ADDR          DownstreamPort; ///< Downstream port to enable ASPM
+  UINT8             MaxL0sLatency;  ///< TBD
+  UINT8             MaxL1Latency;   ///< TBD
+  UINT8             LinkCount;      ///< TBD
+  UINT8             Lx;             ///< ASPM state to enable
+} ASPM_WORKSPACE;
+
+#define ASPM_UPSTREAM_L0s   BIT2
+#define ASPM_DOWNSTREAM_L0s BIT3
+#define ASPM_L1             BIT1
+#define ASPM_L0s            BIT0
+
+/// Framework for callback ASPM capability callback
+typedef struct  {
+  PCI_ADDR          DownstreamPort; ///< Downstream port PCI address to enable ASPM
+  PCI_ADDR          UpstreamPort;   ///< Upstream port PCI address to enable ASPM
+  UINT8             DownstreamLxCap; ///< Downstream port ASPM capability
+  UINT8             UpstreamLxCap;  ///< Upstream port ASPM capability
+  UINT8             DownstreamLx;   ///< Downstream port ASPM setting
+  UINT8             UpstreamLx;     ///< Upstream port ASPM setting
+  UINT8             RequestedLx;    ///< Requested port ASPM setting
+} ASPM_LINK_INFO;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c
new file mode 100644
index 0000000..a77623e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.c
@@ -0,0 +1,105 @@
+/**
+ * @file
+ *
+ * PCIe link width control.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate CPL buffers
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.  *
+ */
+VOID
+PcieLibCplBufferAllocation (
+  IN      CORE              CoreId,
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  PORT     PortId;
+  BOOLEAN  IsAllocationEnabled;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCplBufferAllocation Enter [CoreId = %d]\n", CoreId));
+  IsAllocationEnabled = FALSE;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig) && PcieLibGetCoreId (PortId, pConfig) == CoreId) {
+      PCI_ADDR  Port;
+      PORT_INFO *pPortInfo;
+      pPortInfo = PcieLibGetPortInfo (PortId, pConfig);
+      if (pPortInfo->SlaveCplBuffers != 0) {
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    PortId %d , Port Address 0x%x, CplBuffers, %d\n", PortId, Port.AddressValue, pPortInfo->SlaveCplBuffers));
+        LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG10, AccessWidth32, (UINT32)~(0x3f << 8), pPortInfo->SlaveCplBuffers << 8, pConfig);
+        IsAllocationEnabled = TRUE;
+      }
+    }
+  }
+  if (IsAllocationEnabled) {
+    CORE  CoreAddress;
+    CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG20 | CoreAddress, AccessWidth32, (UINT32)~(BIT11), BIT11, pConfig);
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCplBufferAllocation Exit\n"));
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.h b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.h
new file mode 100644
index 0000000..87d3b30
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieCplBuffers.h
@@ -0,0 +1,52 @@
+/**
+ * @file
+ *
+ * PCIe link width control.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIECPLBUFFERS_H_
+#define _NBPCIECPLBUFFERS_H_
+
+VOID
+PcieLibCplBufferAllocation (
+  IN      CORE              CoreId,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c
new file mode 100644
index 0000000..1111556
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieEarlyHwLib.c
@@ -0,0 +1,475 @@
+/**
+ * @file
+ *
+ *  PCIe silicon specific functions library.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "HotplugFirmware.h"
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MCU_CLEAR_BLOCK_LENGTH  16
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+INDIRECT_REG_ENTRY
+STATIC
+PcieMiscInitTable[] = {
+  {
+    NB_MISC_REG20,
+    (UINT32)~BIT1,
+    0x0
+  }, //enable static device remapping by default
+  {
+    NB_MISC_REG22,
+    0xffffffff,
+    BIT27 | (0x8 << 12) | (0x8 << 16) | (0x8 << 20)
+  },
+  {
+    NB_MISC_REG2B,
+    0xffffffff,
+    (0x8 << 12)
+  },
+  {
+    NB_MISC_REG6C,
+    0xffffffff,
+    (0x8 << 16)
+  },
+  {
+    NB_MISC_REG6B,
+    0xffffffff,
+    (UINT32) (0x1f << 27)
+  }, //[13][12]Turn Off Offset Cancellation
+  {
+    NB_MISC_REG37,
+    (UINT32)~(BIT11 + BIT12 + BIT13),
+    0x0
+  }, //[14][13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG67,
+    (UINT32)~(BIT26 + BIT10 + BIT11),
+    BIT11
+  }, //[13]Disables Rx Clock gating in CDR
+     //[16]Sets Electrical  Idle Threshold
+  {
+    NB_MISC_REG2C,
+    (UINT32)~(BIT10),
+    0x0
+  }, //[13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG2A,
+    (UINT32)~(BIT17 + BIT16),
+    BIT17
+  }, //[16]Sets Electrical l Idle Threshold
+  {
+    NB_MISC_REG32,
+    (UINT32)~(0x3F << 20),
+    (UINT32) (0x2A << 20)
+  }  //[17][16]Sets Electrical Idle Threshold
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc Initialization prior port training.
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+PcieLibPreTrainingInit (
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32      Value;
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      ServerHotplugMask;
+  BOOLEAN     SmuWa;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibPreTrainingInit Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  ServerHotplugMask = 0;
+//Init Misc registers
+  LibNbIndirectTableInit (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieMiscInitTable[0],NULL),
+    (sizeof (PcieMiscInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+//Setup peer-to-peer
+  if (pPcieConfig->PcieConfiguration.Peer2Peer == ON) {
+    if (pPcieConfig->CoreConfiguration[PcieLibGetCoreId (3, pConfig)] == GFX_CONFIG_AABB) {
+      Value = 0x08080404;
+    } else {
+      Value = 0x08080008;
+    }
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG49, AccessWidth32, 0, Value, pConfig);
+    if (pPcieConfig->CoreConfiguration[PcieLibGetCoreId (12, pConfig)] == GFX_CONFIG_AABB) {
+      Value = 0xFFFF0404;
+    } else {
+      Value = 0xFFFF0008;
+    }
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG2F, AccessWidth32, 0, Value, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG48, AccessWidth32, (UINT32)~(BIT8), 0xffff0000, pConfig);
+  }
+
+ //Remap device number
+#ifndef DEVICE_REMAP_DISABLE
+  if (PciePortRemapInit (pConfig) != AGESA_SUCCESS ) {
+    REPORT_EVENT (AGESA_ERROR, PCIE_ERROR_DEVICE_REMAP, 0, 0, 0, 0, pConfig);
+  }
+#endif
+
+#ifndef HOTPLUG_SUPPORT_DISABLED
+  ServerHotplugMask = PcieInitHotplug (pConfig);
+#endif
+
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG4A, AccessWidth32, &Value, pConfig);
+  SmuWa = ((Value & BIT21) != 0) ? TRUE : FALSE;
+
+  if (SmuWa || ServerHotplugMask != 0) {
+    UINT32  BlockIndex;
+    UINT32  SmuWaData;
+    UINT16  Address;
+    UINT32  Data[MCU_CLEAR_BLOCK_LENGTH];
+
+    LibNbMcuControl (AssertReset, pConfig);
+    // clear SMU RAM
+    LibAmdMemFill (&Data[0], 0, sizeof (Data), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+    for (Address = 0; Address < (16 * 1024); Address = Address + 4 * MCU_CLEAR_BLOCK_LENGTH) {
+      LibNbLoadMcuFirmwareBlock (Address, MCU_CLEAR_BLOCK_LENGTH, &Data[0], pConfig);
+    }
+    //Load SMU firmware
+    for (BlockIndex = 0; BlockIndex < Fm.NumberOfBlock; BlockIndex++) {
+      LibNbLoadMcuFirmwareBlock (Fm.BlockArray[BlockIndex].Address, Fm.BlockArray[BlockIndex].Length, Fm.BlockArray[BlockIndex].Data, pConfig);
+    }
+    if (SmuWa) {
+      SmuWaData = LibHtGetSmuWaData (pConfig);
+      LibNbLoadMcuFirmwareBlock (0xFE70, 0x1, &SmuWaData, pConfig);
+    }
+    SmuWaData = ((SmuWa == TRUE) ? 0x100 : 0x100) | ((ServerHotplugMask != 0) ?  0x1 : 0);
+    LibNbLoadMcuFirmwareBlock (0xFE74, 0x1, &SmuWaData, pConfig);
+
+    LibNbMcuControl (DeAssertReset, pConfig);
+  }
+
+#ifndef HOTPLUG_SUPPORT_DISABLED
+  PcieCheckHotplug (ServerHotplugMask, pConfig);
+#endif
+
+}
+
+INDIRECT_REG_ENTRY  PcieCoreInitTable[] = {
+  {
+    NB_BIFNB_REG10,
+    (UINT32)~(BIT10 + BIT11 + BIT12),
+    BIT12
+  },
+  {
+    NB_BIFNB_REG20,
+    (UINT32)~(BIT8 + BIT9),
+    BIT9
+  },
+  {
+    NB_BIFNB_REG02,
+    (UINT32)~(BIT0),
+    BIT0
+  },
+  {
+    NB_BIFNB_REG40,
+    (UINT32)~(BIT14 + BIT15),
+    BIT15
+  },
+  {
+    NB_BIFNB_REGC2,
+    (UINT32)~(BIT25),
+    BIT25
+  },
+  {
+    NB_BIFNB_REGC1,
+    (UINT32)~(BIT0),
+    (BIT0 + BIT1 + BIT2)
+  },
+  {
+    NB_BIFNB_REG1C,
+    0x0,
+    (4 << 6) + (4 << 1) + 1
+  }
+};
+
+INDIRECT_REG_ENTRY  PcieRd790CoreInitTable[] = {
+  {
+    NB_BIFNB_REGC2,
+    (UINT32)~(BIT14),
+    (BIT14)
+  },
+  {
+    NB_BIFNB_REGC1,
+    (UINT32)~(BIT2),
+    0x0
+  },
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Core registers
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieLibCommonCoreInit (
+  IN       CORE              CoreId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32  CoreAddress;
+  NB_INFO NbInfo;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCommonCoreInit (CoreId = %d) Enter\n", CoreId));
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+
+  LibNbIndirectTableInit (
+    pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+    CoreAddress,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieCoreInitTable[0],NULL),
+    (sizeof (PcieCoreInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+
+  if (CoreAddress == SB_CORE) {
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG10 | CoreAddress, AccessWidth32, (UINT32)~BIT9, BIT9, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG06, AccessWidth32, (UINT32)~BIT26, BIT26 + BIT1, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG1C | CoreAddress, AccessWidth32, (UINT32)~BIT0, 0x0, pConfig);
+  }
+  if ( NbInfo.Type < NB_SR5690 ) {
+    LibNbIndirectTableInit (
+      pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+      CoreAddress,
+      (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieRd790CoreInitTable[0], NULL),
+      (sizeof (PcieRd790CoreInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+      pConfig
+      );
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCommonCoreInit Exit\n"));
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Core after training is completed
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.  *
+ */
+
+
+VOID
+PcieLibCoreAfterTrainingInit (
+  IN       CORE              CoreId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32      CoreAddress;
+  PCIE_CONFIG *pPcieConfig;
+  PCI_ADDR    ClkPciAddress;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG20 | CoreAddress, AccessWidth32, (UINT32)~(BIT9), 0, pConfig);
+//Save core setting in scratch register
+  LibNbPciIndexWrite (
+    pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+    NB_BIFNB_REG01 | CoreAddress,
+    AccessWidth32,
+    (UINT32*)&pPcieConfig->CoreSetting[CoreId],
+    pConfig
+    );
+//Save general setting in scratch
+  LibNbEnableClkConfig (pConfig);
+  LibNbPciWrite (ClkPciAddress.AddressValue | NB_CLK_REG78, AccessWidth32, &pPcieConfig->PcieConfiguration, pConfig);
+  LibNbDisableClkConfig (pConfig);
+
+}
+
+
+INDIRECT_REG_ENTRY  PciePortInitTable[] = {
+  {
+    NB_BIFNBP_REG02,
+    (UINT32)~(BIT15),
+    BIT15
+  },
+  {
+    NB_BIFNBP_REGA1,
+    (UINT32)~(BIT24 + BIT26),
+    BIT11
+  },
+  {
+    NB_BIFNBP_REGB1,
+    0xffffffff,
+    BIT28 + BIT23 + BIT19 + BIT20
+  },
+  {
+    NB_BIFNBP_REGA4,
+    (UINT32)~(BIT0),
+    0x0
+  },
+  {
+    NB_BIFNBP_REGA2,
+    (UINT32)~(BIT13),
+    BIT13
+  },
+  {
+    NB_BIFNBP_REGA3,
+    (UINT32)~(BIT9),
+    BIT9
+  },
+  {
+    NB_BIFNBP_REGA0,
+    0xffff000f,
+    0x6830
+  },
+  {
+    NB_BIFNBP_REGC1,
+    0xfffffff0,
+    0xC
+  },
+  {
+    NB_BIFNBP_REG70,
+    (UINT32)~(BIT16 + BIT17 + BIT18),
+    BIT16 + BIT18
+  }
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init port registers
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieLibCommonPortInit (
+  IN       PORT              PortId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  PCI_ADDR    Port;
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      PcieSlotCapability;
+  UINT32      CoreAddress;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCommonPortInit PortId %d Enter\n", PortId));
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  CoreAddress = PcieLibGetCoreAddress (PcieLibGetCoreId (PortId, pConfig), pConfig);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+
+  LibNbIndirectTableInit (
+    Port.AddressValue | NB_BIF_INDEX,
+    0x0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PciePortInitTable[0],NULL),
+    (sizeof (PciePortInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+  if (CoreAddress == GPP3a_CORE || CoreAddress == SB_CORE || CoreAddress == GPP3b_CORE) {
+    LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG70, AccessWidth32, (UINT32)~(BIT16 + BIT17 + BIT18), (BIT17 + BIT18), pConfig);
+    if (CoreAddress == GPP3a_CORE) {
+      LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGB1, AccessWidth32, (UINT32)~(BIT22), BIT22, pConfig);
+    }
+  }
+// Set completion timeout
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG80, AccessS3SaveWidth8, 0xF0, 0x6, pConfig);
+  //if (CoreAddress != SB_CORE) {
+  //  LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG10, AccessWidth32, (UINT32)~BIT0, 0x0, pConfig);
+  //}
+//For hotplug ports
+  //if (pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF ||
+  //    pPcieConfig->PcieConfiguration.DisableHideUnusedPorts == ON ||
+  //    LibNbGetRevisionInfo (pConfig).Revision == NB_REV_A11) {
+  LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG20, AccessWidth32, (UINT32)~BIT19, 0x0, pConfig);
+  //}
+
+// Enable Immediate ACK
+  if (pPcieConfig->ExtPortConfiguration[PortId].PortL1ImmediateACK == ON) {
+    LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA0, AccessWidth32, (UINT32)~BIT23, BIT23, pConfig);
+  }
+//Set up slot capability
+  PcieSlotCapability = (pPcieConfig->ExtPortConfiguration[PortId].PortPowerLimit << 7) |
+                       ((Port.Address.Device | Port.Address.Bus << 5 ) << 19);
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessS3SaveWidth32, (UINT32)~((0x3ff << 7) | (0x1fff << 19)), PcieSlotCapability, pConfig);
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG5A, AccessS3SaveWidth16, (UINT32)~BIT8, BIT8, pConfig);
+//Set interrupt pin info
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG3D, AccessS3SaveWidth8, 0x0, 0x1, pConfig);
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibCommonPortInit Exit\n"));
+};
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c
new file mode 100644
index 0000000..25ef38f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.c
@@ -0,0 +1,343 @@
+/**
+ * @file
+ *
+ * Routines to support Hotplug.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdSbLib.h"
+
+#ifndef  HOTPLUG_SUPPORT_DISABLED
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define ATTN_BUTTON_PRESENT     BIT0
+#define PWR_CONTROLLER_PRESENT  BIT1
+#define MRL_SENSOR_PRESENT      BIT2
+#define ATTN_INDICATOR_PRESENT  BIT3
+#define PWR_INDICATOR_PRESENT   BIT4
+#define HOTPLUG_SURPRISE        BIT5
+#define HOTPLUG_CAPABLE         BIT6
+
+#define ATTN_BUTTON_PRESSED     BIT0
+#define PWR_FAULT_DETECTED      BIT1
+#define MRL_SENSOR_CHANGED      BIT2
+#define PRESENCE_DETECT_CHANGED BIT3
+#define COMMAND_COMPLETED       BIT4
+#define MRL_SENSOR_STATE        BIT5
+#define PRESENCE_DETECT_STATE   BIT6
+#define DL_STATE_CHANGED        BIT8
+
+#define PWR_CONTROLLER_CNTL     BIT10
+#define NO_COMMAND_COMPLETED_SUPPORTED  BIT18
+#define SERVER_HOTPLUG_CAPABILITY \
+  (ATTN_BUTTON_PRESENT | PWR_CONTROLLER_PRESENT | ATTN_INDICATOR_PRESENT | PWR_INDICATOR_PRESENT | HOTPLUG_CAPABLE)
+#define NATIVE_HOTPLUG_CAPABILITY \
+  (HOTPLUG_SURPRISE | HOTPLUG_CAPABLE)
+
+#define SERVER_HOTPLUG  1
+#define NATIVE_HOTPLUG  2
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+ /*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Ports Hotplug capability.
+ * Initialize hotplug controller init port hotplug capability
+ *
+ *
+ * @param[in] pConfig  Northbridge configuration structure pointer.
+ *
+ * @retval    AGESA_SUCCESS Hotplug controller successfully initialized.
+ * @retval    AGESA_FAIL    Failure during initialization of hotplug controller.
+ */
+/*----------------------------------------------------------------------------------------*/
+UINT32
+PcieInitHotplug (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT32        ServerHotplugPortMask;
+  PORT          PortId;
+  PCI_ADDR      ClkPciAddress;
+  NB_INFO       NbInfo;
+  PCIE_CONFIG   *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitHotplug Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  ServerHotplugPortMask = 0;
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  if (NbInfo.Type == NB_SR5690) {
+    for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+      if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON &&
+        pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF ) {
+        PCI_ADDR  Port;
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        if (pPcieConfig->PortConfiguration[PortId].PortHotplug == SERVER_HOTPLUG) {
+          UINT8  HpDescriptorRegister;
+          UINT8  HpDescriptorOffset;
+          ServerHotplugPortMask |= 1 << PortId;
+          HpDescriptorOffset = (PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig))->HotplugAddress;
+          if (HpDescriptorOffset != 0xff) {
+            ServerHotplugPortMask |= 1 << PortId;
+            HpDescriptorRegister = (PcieLibGetCoreInfo (PcieLibGetCoreId (PortId, pConfig), pConfig))->HotplugRegister;
+            //Enable CLK config
+            LibNbEnableClkConfig (pConfig);
+            //Setup descriptor
+            LibNbPciRMW (
+              ClkPciAddress.AddressValue | HpDescriptorRegister ,
+              AccessWidth32,
+              0xffffffff,
+              ((1 << 3) | (pPcieConfig->ExtPortConfiguration[PortId].PortHotplugDevMap << 2) | pPcieConfig->ExtPortConfiguration[PortId].PortHotplugByteMap) << HpDescriptorOffset,
+              pConfig
+              );
+            //Hide CLK config
+            LibNbDisableClkConfig (pConfig);
+            // Enable power fault
+            LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG10, AccessWidth32, (UINT32)~BIT4, BIT4, pConfig);
+            //Set up capability. Keep NO_COMMAND_COMPLETED_SUPPORTED (bit 18) to zero
+            LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xfffbffff, SERVER_HOTPLUG_CAPABILITY, pConfig);
+            //Clear Status
+            LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
+          }
+        }
+        if (pPcieConfig->PortConfiguration[PortId].PortHotplug == NATIVE_HOTPLUG) {
+          LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xffffffff, NATIVE_HOTPLUG_CAPABILITY, pConfig);
+        }
+      }
+    }
+  }
+  return ServerHotplugPortMask;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Ports Hotplug capability.
+ * Initialize hotplug controller init port hotplug capability
+ *
+ * @param[in] ServerHotplugPortMask  ServerHotplugPortMask
+ * @param[in] pConfig  Northbridge configuration structure pointer.
+ *
+ * @retval    AGESA_SUCCESS Hotplug controller successfully initialized.
+ * @retval    AGESA_FAIL    Failure during initialization of hotplug controller.
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+PcieCheckHotplug (
+  IN     UINT32          ServerHotplugPortMask,
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  PORT          PortId;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckHotplug Enter\n"));
+    //Check if Firmware loaded successfully
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    //Check Firmware Loaded successfully
+    if ((ServerHotplugPortMask & (1 << PortId)) != 0) {
+      UINT32    Count;
+      PCI_ADDR  Port;
+      UINT16    SlotStatus;
+
+      Count = 30;       //Setup counter for 30ms
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      do {
+        STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, 0);
+        LibNbPciRead (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, &SlotStatus, pConfig);
+      } while ((SlotStatus & (ATTN_BUTTON_PRESSED | PWR_FAULT_DETECTED)) == 0 && --Count != 0);
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Hotplug Firmware Init PortId = %d SlotStatus = 0x%x Retry = %d\n", PortId, SlotStatus, Count));
+      if ((SlotStatus & PWR_FAULT_DETECTED) != 0 || (SlotStatus & (PWR_FAULT_DETECTED | ATTN_BUTTON_PRESSED)) == 0) {
+        REPORT_EVENT (AGESA_ERROR, PCIE_ERROR_HOTPLUG_INIT, PortId, 0, 0, 0, pConfig);
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    ERROR!!!Hotplug Firmware Init FAIL\n"));
+        LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, (UINT32)~SERVER_HOTPLUG_CAPABILITY, 0x0, pConfig);
+      } else {
+        //Clear Status
+        LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
+        if ((SlotStatus & PRESENCE_DETECT_CHANGED) != 0) {
+          //Power on slot
+          LibNbPciRMW (Port.AddressValue | NB_PCIP_REG70, AccessWidth16, (UINT32)~PWR_CONTROLLER_CNTL, 0x0, pConfig);
+        }
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckHotplug Exit\n"));
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init Ports Hotplug capability.
+ * Initialize hotplug controller init port hotplug capability
+ *
+ *
+ * @param[in] pConfig  Northbridge configuration structure pointer.
+ *
+ * @retval    AGESA_SUCCESS Hotplug controller successfully initialized.
+ * @retval    AGESA_FAIL    Failure during initialization of hotplug controller.
+ */
+/*----------------------------------------------------------------------------------------*/
+/*
+AGESA_STATUS
+PcieInitHotplug (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT32        ServerHotplugPortMask;
+  PORT          PortId;
+  PCI_ADDR      ClkPciAddress;
+  NB_INFO       NbInfo;
+  PCIE_CONFIG   *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitHotplug Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  ServerHotplugPortMask = 0;
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  Status = AGESA_SUCCESS;
+  if (NbInfo.Type == NB_SR5690) {
+    for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+      if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON &&
+        pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF ) {
+        PCI_ADDR  Port;
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        if (pPcieConfig->PortConfiguration[PortId].PortHotplug == SERVER_HOTPLUG) {
+          UINT8  HpDescriptorRegister;
+          UINT8  HpDescriptorOffset;
+          ServerHotplugPortMask |= 1 << PortId;
+          HpDescriptorOffset = (PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig))->HotplugAddress;
+          if (HpDescriptorOffset != 0xff) {
+            ServerHotplugPortMask |= 1 << PortId;
+            HpDescriptorRegister = (PcieLibGetCoreInfo (PcieLibGetCoreId (PortId, pConfig), pConfig))->HotplugRegister;
+            //Enable CLK config
+            LibNbEnableClkConfig (pConfig);
+            //Setup descriptor
+            LibNbPciRMW (
+              ClkPciAddress.AddressValue | HpDescriptorRegister ,
+              AccessWidth32,
+              0xffffffff,
+              ((1 << 3) | (pPcieConfig->ExtPortConfiguration[PortId].PortHotplugDevMap << 2) | pPcieConfig->ExtPortConfiguration[PortId].PortHotplugByteMap) << HpDescriptorOffset,
+              pConfig
+              );
+            //Hide CLK config
+            LibNbDisableClkConfig (pConfig);
+            // Enable power fault
+            LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG10, AccessWidth32, (UINT32)~BIT4, BIT4, pConfig);
+            //Set up capability. Keep NO_COMMAND_COMPLETED_SUPPORTED (bit 18) to zero
+            LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xfffbffff, SERVER_HOTPLUG_CAPABILITY, pConfig);
+            //Clear Status
+            LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
+          }
+        }
+        if (pPcieConfig->PortConfiguration[PortId].PortHotplug == NATIVE_HOTPLUG) {
+          LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, 0xffffffff, NATIVE_HOTPLUG_CAPABILITY, pConfig);
+        }
+      }
+    }
+    if (ServerHotplugPortMask != 0) {
+      UINT32  FirmwareLength;
+      FirmwareLength = sizeof (Firmware);
+      if (FirmwareLength > 0) {
+        UINT32 *pFirmware;
+        pFirmware = (UINT32*)FIX_PTR_ADDR (&Firmware[0], NULL);
+        //Load firmware
+        LibNbMcuControl (AssertReset, pConfig);
+        LibNbLoadMcuFirmwareBlock (0x200, (sizeof (Firmware) -  64), pFirmware, pConfig);
+        LibNbLoadMcuFirmwareBlock (0xFFC0, 64, &pFirmware[(sizeof (Firmware) -  64) / 4], pConfig);
+        LibNbMcuControl (DeAssertReset, pConfig);
+      }
+    }
+    //Check if Firmware loaded successfully
+    for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+      //Check Firmware Loaded successfully
+      if ((ServerHotplugPortMask & (1 << PortId)) != 0) {
+        UINT32    Count;
+        PCI_ADDR  Port;
+        UINT16    SlotStatus;
+
+        Count = 30;       //Setup counter for 30ms
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        do {
+          STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, 0);
+          LibNbPciRead (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, &SlotStatus, pConfig);
+        } while ((SlotStatus & (ATTN_BUTTON_PRESSED | PWR_FAULT_DETECTED)) == 0 && --Count != 0);
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Hotplug Firmware Init PortId = %d SlotStatus = 0x%x Retry = %d\n", PortId, SlotStatus, Count));
+        if ((SlotStatus & PWR_FAULT_DETECTED) != 0 || (SlotStatus & (PWR_FAULT_DETECTED | ATTN_BUTTON_PRESSED)) == 0) {
+          Status = AGESA_ERROR;
+          REPORT_EVENT (AGESA_ERROR, PCIE_ERROR_HOTPLUG_INIT, PortId, 0, 0, 0, pConfig);
+          CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    ERROR!!!Hotplug Firmware Init FAIL\n", PortId));
+          LibNbPciRMW (Port.AddressValue | NB_PCIP_REG6C, AccessWidth32, ~SERVER_HOTPLUG_CAPABILITY, 0x0, pConfig);
+        } else {
+          //Clear Status
+          LibNbPciRMW (Port.AddressValue | NB_PCIP_REG72, AccessWidth16, 0xffffffff, 0x11F, pConfig);
+          if ((SlotStatus & PRESENCE_DETECT_CHANGED) != 0) {
+            //Power on slot
+            LibNbPciRMW (Port.AddressValue | NB_PCIP_REG70, AccessWidth16, ~PWR_CONTROLLER_CNTL, 0x0, pConfig);
+          }
+        }
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitHotplug Exit. Status[0x%x]\n", Status));
+  return  Status;
+}
+*/
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.h b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.h
new file mode 100644
index 0000000..1b7ba04
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieHotplug.h
@@ -0,0 +1,62 @@
+/**
+ * @file
+ *
+ * PCIe hotplug support.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#ifndef _NBPCIEHOTPLUG_H_
+#define _NBPCIEHOTPLUG_H_
+
+
+UINT32
+PcieInitHotplug (
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+VOID
+PcieCheckHotplug (
+  IN     UINT32               ServerHotplugPortMask,
+  IN     AMD_NB_CONFIG        *pConfig
+  );
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
new file mode 100644
index 0000000..6fdf2b1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitEarly.c
@@ -0,0 +1,720 @@
+/**
+ * @file
+ *
+ *  PCIe Early initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+ /*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIE Init for all NB.
+ *    Basic programming / EP training. After this call EP are fully operational.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+AmdPcieEarlyInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+
+  Status = LibNbApiCall (PcieEarlyInit, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge PCIE Init.
+ *    Basic programming / EP training. After this call EP are fully operational on particular NB.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr   Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieEarlyInit (
+  IN OUT   AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieEarlyInit Enter\n"));
+  Status = PcieLibInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0 , 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  Status = PciePreTrainingInit (NbConfigPtr);
+  Status = PcieInitPorts (NbConfigPtr);
+  Status = PcieAfterTrainingInit (NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieEarlyInit Exit [0x%x]\n", Status));
+  return  Status;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc initialization prior port link training started
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PciePreTrainingInit (
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  CORE        CoreId ;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePreTrainingInit Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  //Unhide all ports
+  PcieLibUnHidePorts (pConfig);
+  if (pPcieConfig->PcieMmioBaseAddress != 0 && pPcieConfig->PcieMmioSize != 0) {
+    PcieLibSetPcieMmioBase (pPcieConfig->PcieMmioBaseAddress, pPcieConfig->PcieMmioSize, pConfig);
+  }
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    CoreId %d  CoreSetting = 0x%x\n", CoreId, *((UINT32*)&pConfig->pPcieConfig->CoreSetting[CoreId])));
+    //if (pPcieConfig->CoreSetting[CoreId].CoreDisabled == OFF) {
+      //Configure cores
+    if (pPcieConfig->CoreSetting[CoreId].SkipConfiguration == OFF) {
+      PcieLibSetCoreConfiguration (CoreId, pConfig);
+    }
+      //Init core registers
+    PcieLibCommonCoreInit (CoreId, pConfig);
+    //}
+  }
+  PcieLibPreTrainingInit (pConfig);
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    CoreId %d  CoreSetting = 0x%x\n", CoreId, *((UINT32*)&pConfig->pPcieConfig->CoreSetting[CoreId])));
+    //Init CPL buffer allocation
+    //if (pPcieConfig->CoreSetting[CoreId].CoreDisabled == OFF && pPcieConfig->CoreSetting[CoreId].CplBufferAllocation == ON) {
+    if (pPcieConfig->CoreSetting[CoreId].CplBufferAllocation == ON) {
+      PcieLibCplBufferAllocation (CoreId, pConfig);
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePreTrainingInit Exit\n"));
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc initialization after port training complete
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieAfterTrainingInit (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  CORE        CoreId;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+//    if (pPcieConfig->CoreSetting[CoreId].CoreDisabled == OFF) {
+      //Configure cores
+    PcieLibCoreAfterTrainingInit (CoreId, pConfig);
+//    }
+  }
+  //Hide all Ports
+  PcieLibHidePorts (pConfig);
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Train PCIE Ports
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieInitPorts (
+  IN OUT   AMD_NB_CONFIG     *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+
+  Status = AGESA_SUCCESS;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  if (pPcieConfig->DeviceInitMaskS1 != 0) {
+    Status = PcieInitSelectedPorts (pPcieConfig->DeviceInitMaskS1, pConfig);
+  }
+  if (pPcieConfig->DeviceInitMaskS2 != 0) {
+    Status = PcieInitSelectedPorts (pPcieConfig->DeviceInitMaskS2, pConfig);
+  }
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Train PCIE Ports selected for this stage
+ *
+ *
+ *  @param[in] SelectedPortMask Bitmap of port ID selected for training.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieInitSelectedPorts (
+  IN       UINT16          SelectedPortMask,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+  PORT          PortId;
+  BOOLEAN       RequestResetDelay;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitSelectedPorts (Ports = 0x%x) Enter\n", SelectedPortMask));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  Status = AGESA_SUCCESS;
+  RequestResetDelay = FALSE;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    PortId %d  PortConfiguration = 0x%x ExtPortConfiguration = 0x%x\n", PortId, *((UINT32*)&pPcieConfig->PortConfiguration[PortId]), *((UINT32*)&pPcieConfig->ExtPortConfiguration[PortId])));
+    if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+      if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON && PcieLibIsValidPortId (PortId, pConfig)) {
+        PCIE_LINK_MODE    LinkMode;
+        //Deassert slot reset. Bring EP out of reset
+        Status = LibNbCallBack (PHCB_AmdPortResetDeassert, 1 << PortId, pConfig);
+        if (Status == AGESA_SUCCESS) {
+          //STALL (GET_BLOCK_CONFIG_PTR (pConfig), pPcieConfig->ResetToTrainingDelay * 1000, 0);
+          RequestResetDelay = TRUE;
+        }
+        //Init common registers
+        PcieLibCommonPortInit (PortId, pConfig);
+        //Check if we already have device failure to go to Gen2 before
+        if (PcieLibCheckGen2Disabled (PortId, pConfig)) {
+          pPcieConfig->PortConfiguration[PortId].PortLinkMode = PcieLinkModeGen1;
+          pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis = PcieTxDeemphasis6dB; // this is to workaround Gen2
+        }
+        //@todo  Add handling for scratch register for PCIE Gen
+        switch (pPcieConfig->PortConfiguration[PortId].PortLinkMode) {
+        case  PcieLinkModeGen2:
+        case  PcieLinkModeGen2AdvertizeOnly:
+        case  PcieLinkModeGen1:
+          LinkMode = pPcieConfig->PortConfiguration[PortId].PortLinkMode;
+          break;
+        default:
+          LinkMode = PcieLinkModeGen1;
+        }
+        PcieLibSetLinkMode (PortId, LinkMode, pConfig);
+        //Enable Compliance Mode
+        if (pPcieConfig->PortConfiguration[PortId].PortCompliance == ON) {
+          PcieLibSetLinkCompliance (PortId, pConfig);
+        }
+      } else {
+        //Port disabled
+        SelectedPortMask  &= (~(1 <<  PortId));
+      }
+    }
+  }
+  if (RequestResetDelay) {
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), pPcieConfig->ResetToTrainingDelay * 1000, 0);
+  }
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+        //Release Port Training
+      PcieLibPortTrainingControl (PortId, PcieLinkTrainingRelease, pConfig);
+    }
+  }
+  STALL (GET_BLOCK_CONFIG_PTR (pConfig), pPcieConfig->TrainingToLinkTestDelay * 1000, 0);
+  Status = PcieCheckSelectedPorts (SelectedPortMask, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitSelectedPorts Exit\n"));
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check link state on selected ports.
+ *
+ *
+ *
+ *  @param[in] SelectedPortMask Bitmap of port ID selected for training.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieCheckSelectedPorts (
+  IN    UINT16          SelectedPortMask,
+  IN    AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS      Status;
+  PCIE_CONFIG       *pPcieConfig;
+  PORT              PortId;
+  UINT16            PortMask;
+  UINT16            CurrentPortMask;
+  PCIE_LINK_STATUS  PortsLinkStatus[MAX_PORT_ID + 1];
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckSelectedPorts (Ports = 0x%x) Enter\n", SelectedPortMask));
+  Status = AGESA_SUCCESS;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  PortMask = SelectedPortMask;
+  // Clear up link state storage
+  LibAmdMemFill (PortsLinkStatus, 0, sizeof (PortsLinkStatus), (AMD_CONFIG_PARAMS *)&(pPcieConfig->sHeader));
+  // Initial check for link status on all ports
+  if (PortMask != 0) {
+    PcieGetPortsLinkStatus (PortMask, &PortsLinkStatus[0], pPcieConfig->ReceiverDetectionPooling, pConfig);
+  }
+  // Check if training on any ports in progress
+  PortMask = PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusTrainingInProgress);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    #1 PortMask  = 0x%x\n", PortMask));
+  if (PortMask != 0) {
+    // Try to recover ports in case of broken lane
+    if (PcieBrokenLaneWorkaround (PortMask, pConfig) != AGESA_UNSUPPORTED) {
+      // Update port status array
+      PortMask |= PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusConnected);
+      PcieGetPortsLinkStatus (PortMask, &PortsLinkStatus[0], pPcieConfig->ReceiverDetectionPooling, pConfig);
+    }
+  }
+  // Check if training on any ports still in progress
+  CurrentPortMask = PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusTrainingInProgress);
+  if (PortMask != CurrentPortMask) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_BROKEN_LINE, (PortMask^CurrentPortMask)&PortMask, 0, 0, 0, pConfig);
+  }
+  PortMask = CurrentPortMask;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    #2 PortMask  = 0x%x\n", PortMask));
+  if (PortMask != 0) {
+    // Try to recover port training by downgrading link speed to Gen1
+    if (PcieGen2Workaround (PortMask, pConfig) != AGESA_UNSUPPORTED) {
+      PortMask |= PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusConnected);
+      PcieGetPortsLinkStatus (PortMask, &PortsLinkStatus[0], pPcieConfig->ReceiverDetectionPooling, pConfig);
+    }
+  }
+  // Check if training on any ports still in progress
+  CurrentPortMask = PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusTrainingInProgress);
+  if (PortMask != CurrentPortMask) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_GEN2_FAIL, (PortMask^CurrentPortMask)&PortMask, 0, 0, 0, pConfig);
+  }
+  PortMask = CurrentPortMask;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    #3 PortMask  = 0x%x\n", PortMask));
+  if (PortMask != 0) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_TRAINING_FAIL, PortMask, 0, 0, 0, pConfig);
+    PcieMiscWorkaround (&PortsLinkStatus[0], pConfig);
+  }
+  //Get bitmap of successfully trained ports
+  PortMask = PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusConnected);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    #4 PortMask  = 0x%x\n", PortMask));
+  if (PortMask != 0) {
+    // Check if VCO negotiation is completed
+    PcieCheckVco (PortMask, &PortsLinkStatus[0], pConfig);
+  }
+  CurrentPortMask = PcieFindPortsWithLinkStatus (&PortsLinkStatus[0], PcieLinkStatusConnected);
+  if (PortMask != CurrentPortMask) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_VCO_NEGOTIATON, (PortMask^CurrentPortMask)&PortMask, 0, 0, 0, pConfig);
+  }
+  PortMask = CurrentPortMask;
+  //Update status port status info
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+      PCI_ADDR Port;
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      if (PortsLinkStatus[PortId] == PcieLinkStatusInCompliance) {
+        pPcieConfig->PortConfiguration[PortId].PortCompliance = ON;
+      } else {
+        if (PortsLinkStatus[PortId] == PcieLinkStatusConnected) {
+          if (LibNbCallBack (PHCB_AmdPortTrainingCompleted, Port.AddressValue, pConfig) == AGESA_ERROR) {
+            PortsLinkStatus[PortId] = 0;
+          }
+          if (PortsLinkStatus[PortId] == PcieLinkStatusConnected &&
+            pPcieConfig->PcieConfiguration.DisableGfxWorkaround == OFF &&
+            PcieLibGetPortLinkInfo (PortId, pConfig).MaxLinkWidth >= PcieLinkWidth_x8 &&
+            PcieGfxWorkarounds (PortId, pConfig) != AGESA_SUCCESS) {
+            //CIMX_ASSERT (FALSE);
+            PortsLinkStatus[PortId] = 0;
+          }
+          if (PortsLinkStatus[PortId] == PcieLinkStatusConnected) {
+            pPcieConfig->PortConfiguration[PortId].PortDetected = ON;
+            PcieLibSetLinkWidth (PortId, pPcieConfig->ExtPortConfiguration[PortId].PortLinkWidth, pConfig);
+          }
+        }
+        if (pPcieConfig->PortConfiguration[PortId].PortDetected == OFF &&
+          pPcieConfig->PortConfiguration[PortId].PortHotplug == OFF) {
+            //Port training on Hold if Link in not connected and not in compliance
+          PcieLibPortTrainingControl (PortId, PcieLinkTrainingHold, pConfig);
+        }
+      }
+      if (pPcieConfig->PortConfiguration[PortId].PortDetected == OFF ||
+          pPcieConfig->PortConfiguration[PortId].PortHotplug == ON) {
+        // For all port without devices and hotplug ports
+        LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG70, AccessWidth32, (UINT32)~BIT19, BIT19, pConfig);
+      }
+      LibNbPciIndexWrite (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG01,  AccessWidth32, (UINT32*)&pPcieConfig->PortConfiguration[PortId], pConfig);
+      LibNbPciWrite (Port.AddressValue | NB_PCIP_REG108, AccessWidth32, (UINT32*)&pPcieConfig->ExtPortConfiguration[PortId], pConfig);
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieCheckSelectedPorts Exit\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Workaround for broken TX line.
+ *
+ *
+ *
+ *  @param[in] SelectedPortMask Bitmap of port ID selected for training.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieBrokenLaneWorkaround (
+  IN    UINT16          SelectedPortMask,
+  IN    AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PORT          PortId;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieBrokenLaneWorkaround Enter\n"));
+  Status = AGESA_UNSUPPORTED;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+      LINK_INFO LinkInfo = PcieLibGetPortLinkInfo (PortId, pConfig);
+      if (LinkInfo.MaxLinkWidth > PcieLinkWidth_x1 && LinkInfo.LinkWidth < LinkInfo.MaxLinkWidth) {
+        PcieLibPowerOffPortLanes (PortId, LinkInfo.LinkWidth, pConfig);
+        if (PcieLibResetSlot (PortId, pConfig) == AGESA_SUCCESS) {
+          Status = AGESA_SUCCESS;
+        }
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieBrokenLaneWorkaround Exit\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Workaround for device violating Gen2 spec.
+ *      Downgrade link speed to Gen1.
+ *
+ *
+ *
+ *  @param[in] SelectedPortMask   Bitmap of port ID selected for training.
+ *  @param[in] pConfig            Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieGen2Workaround (
+  IN    UINT16          SelectedPortMask,
+  IN    AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+  PORT          PortId;
+  BOOLEAN       RequestPciReset;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieGen2Workaround Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  RequestPciReset = FALSE;
+  Status = AGESA_UNSUPPORTED;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+      if (pPcieConfig->PortConfiguration[PortId].PortLinkMode == PcieLinkModeGen2 ||
+          pPcieConfig->PortConfiguration[PortId].PortLinkMode == PcieLinkModeGen2AdvertizeOnly ||
+          pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis == PcieTxDeemphasis3p5dB) {
+        //Degrade link speed to Gen1
+        pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis = PcieTxDeemphasis6dB;
+        PcieLibSetLinkMode (PortId, PcieLinkModeGen1, pConfig);
+        PcieLibSetGen2Disabled (PortId, pConfig);
+        if (PcieLibResetSlot (PortId, pConfig) != AGESA_SUCCESS) {
+          //Slot reset  logic not supported request PCI reset.
+          RequestPciReset = TRUE;
+        }
+        //Report back to caller that potential downgrade case is detected.
+        Status = AGESA_SUCCESS;
+      }
+    }
+    if (RequestPciReset) {
+      PcieLibRequestPciReset (pConfig);
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieGen2Workaround Enter\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Try to recover system by issuing system wide PCI reset.
+ *
+ *
+ *
+ *  @param[in] PortsLinkStatus  Array of link status for every Port
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieMiscWorkaround (
+  IN      PCIE_LINK_STATUS  *PortsLinkStatus,
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PORT          PortId;
+  UINT16        PortMask;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieMiscWorkaround Enter\n"));
+  Status = AGESA_UNSUPPORTED;
+  PortMask = PcieFindPortsWithLinkStatus (PortsLinkStatus, PcieLinkStatusTrainingInProgress);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if ((PortMask & (1 <<  PortId)) != 0) {
+      if (PcieLibRequestPciReset (pConfig)!= AGESA_SUCCESS) {
+        break;
+      }
+      PortMask = PcieFindPortsWithLinkStatus (PortsLinkStatus, PcieLinkStatusTrainingInProgress);
+      if (PortMask == 0) {
+        break;
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieMiscWorkaround Exit\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check VCO negotiation complete.
+ *    Routine will retry retrain device infinitely if VCO negotiation is failing.
+ *
+ *
+ *  @param[in] SelectedPortMask Bitmap of port ID selected for training.
+ *  @param[in] PortsLinkStatus  Array of link status for every Port
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieCheckVco (
+  IN       UINT16             SelectedPortMask,
+  IN       PCIE_LINK_STATUS   *PortsLinkStatus,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT16        VcoNegotiationInProgressPortMask;
+  PORT          PortId;
+  UINT16        VcoStatus;
+  UINT32        LinkRetrainCount;
+  UINT32        VcoPoll;
+  UINT32        Value;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]VcoNegotiationInProgress Enter\n"));
+  Status = AGESA_SUCCESS;
+  VcoNegotiationInProgressPortMask = SelectedPortMask;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (VcoNegotiationInProgressPortMask & (1 <<  PortId)) {
+      // For each port where VCO needs to be checked
+      PCI_ADDR  Port;
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      PortsLinkStatus[PortId] = PcieLinkStatusVcoNegotiationInProgress;
+      for (LinkRetrainCount = 0; LinkRetrainCount < 10; LinkRetrainCount++) {
+        // Poll for 200 ms for VC0 negotioation completion
+        for (VcoPoll = 0; VcoPoll < 200; VcoPoll++) {
+          LibNbPciRead (Port.AddressValue | NB_PCIP_REG12A, AccessWidth16, &VcoStatus, pConfig);
+          if ((VcoStatus & BIT1) != 0) {
+            STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, 0);
+          } else {
+            PortsLinkStatus[PortId] = PcieLinkStatusConnected;
+            break;
+          }
+        }  //For each VcoPoll
+        if (PortsLinkStatus[PortId] == PcieLinkStatusVcoNegotiationInProgress) {
+          CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_MISC), "   Vco Not Completed. Retrain link on PortId %d\n", PortId));
+          LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, pConfig);
+          Value = (Value & 0xfffffe80) | ((Value & 0x70) >> 4) | BIT8;
+          LibNbPciIndexWrite (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, pConfig);
+        } else {
+          break;    //Vco negotiations complete
+        }
+      }  //For each LinkRetrainCount
+      if (PortsLinkStatus[PortId] == PcieLinkStatusVcoNegotiationInProgress) {
+        PortsLinkStatus[PortId] = PcieLinkStatusNotConnected;
+      }
+    } // Vco negotiations required
+  }  //For each port
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]VcoNegotiationInProgress Exit\n"));
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bit map of ports with particular link status
+ *
+ *
+ *
+ *  @param[in] PortLinkStatus   Pointer to array of link status for every Port
+ *  @param[in] LinkStatus       LinkStatus to search for.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+UINT16
+PcieFindPortsWithLinkStatus (
+  IN       PCIE_LINK_STATUS  *PortLinkStatus,
+  IN       PCIE_LINK_STATUS   LinkStatus
+  )
+{
+  UINT16  PortMask;
+  PORT    PortId;
+
+  PortMask = 0;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PortLinkStatus[PortId] == LinkStatus) PortMask |= (1 << PortId);
+  }
+  return PortMask;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Gather link state for selected ports.
+ *
+ *
+ *  @param[in] SelectedPortMask Bitmap of port ID selected for training.
+ *  @param[in] PortLinkStatus   Pointer to array of link status for every Port
+ *  @param[in] Pooling          Time in MS to pool for link status change.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+PCIE_LINK_STATUS
+PcieGetPortsLinkStatus (
+  IN       UINT16             SelectedPortMask,
+  IN OUT   PCIE_LINK_STATUS   *PortLinkStatus,
+  IN       UINT32             Pooling,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  PCIE_LINK_STATUS  Status;
+  PORT              PortId;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieGetPortsLinkStatus Enter\n"));
+  Status = PcieLinkStatusNotConnected;
+  Pooling *= 10;
+  while (Pooling-- != 0 && Status != PcieLinkStatusConnected) {
+    Status = PcieLinkStatusConnected;                                            //Set up initial overall state as connected
+    for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+      //Work only on selected ports
+      if ((SelectedPortMask & (1 <<  PortId)) != 0) {
+        PCI_ADDR  Port;
+        UINT32    LinkState;
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);    //Get PCI address of this port
+        //Get link state
+        LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA5, AccessWidth32, &LinkState, pConfig);
+        LinkState &= 0x3F;
+        //CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_MISC), "    PortId %d LinkState = 0x%x \n", PortId, LinkState));
+        printk(BIOS_INFO, "[NBPCIE]  PortId %02d LinkState = 0x%x \n", PortId, LinkState);
+        //Check if link in L0 state
+
+        if (LinkState == 0x10) {
+          PortLinkStatus[PortId] = PcieLinkStatusConnected;
+        } else {
+          Status = PcieLinkStatusNotConnected;
+          //Check if link in compliance mode
+          if (LinkState == 0x7) {
+            PortLinkStatus[PortId] = PcieLinkStatusInCompliance;
+          } else {
+            //Check if we passed receiver detection. It will indicate that device present.
+            if (LinkState > 0x4) {
+              PortLinkStatus[PortId] = PcieLinkStatusTrainingInProgress;
+            }
+          }
+        }
+      }
+    }
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 100, 0);
+  }
+  return Status;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
new file mode 100644
index 0000000..17ae4f7
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieInitLate.c
@@ -0,0 +1,505 @@
+/**
+ * @file
+ *
+ * PCIE Late Initialization
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd PCIE Late Init for all NB.
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+AGESA_STATUS
+AmdPcieLateInit (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (PcieLateInit, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd PCIE Late Init for all NB.
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+AGESA_STATUS
+AmdPcieLateInitWa (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (PcieLateInitWa, ConfigPtr);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd PCIE Special Init for all NB.
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+AGESA_STATUS
+AmdPcieValidatePortState (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (PcieValidatePortState, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd PCIE S3 Init fro all NB.
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+AGESA_STATUS
+AmdPcieS3Init (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = LibNbApiCall (PcieLateInit, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB PCIE Late Init.
+ *    Extended  programming. Enable power management and misc capability.
+ *    Prepare PCIE subsystem to boot to OS.
+ *
+ *
+ * @param[in] NbConfigPtr  Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateInit (
+  IN      AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  PcieLibUnHidePorts (NbConfigPtr);
+  Status = PcieLateValidateConfiguration (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    PcieLibHidePorts (NbConfigPtr);
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  PcieLibLateInit (NbConfigPtr);
+  Status = PcieLateInitPorts (NbConfigPtr);
+  Status = PcieLateInitCores (NbConfigPtr);
+  PcieLibHidePorts (NbConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB PCIE Late Init.
+ *    Extended  programming. Enable power management and misc capability.
+ *    Prepare PCIE subsystem to boot to OS.
+ *
+ *
+ * @param[in] NbConfigPtr  Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateInitWa (
+  IN      AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  UINT32        Value;
+  BOOLEAN       SmuWa;
+  LibNbPciIndexRead (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG4A, AccessWidth32, &Value, NbConfigPtr);
+  SmuWa = ((Value & BIT21) != 0) ? TRUE : FALSE;
+  if (SmuWa) {
+    UINT32 SmuWaData;
+    LibNbMcuControl (AssertReset, NbConfigPtr);
+    SmuWaData = LibNbReadMcuRam (0xFE74, NbConfigPtr);
+    SmuWaData &= 0x00ff;
+    LibNbLoadMcuFirmwareBlock (0xFE74, 0x1, &SmuWaData, NbConfigPtr);
+    LibNbMcuControl (DeAssertReset, NbConfigPtr);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Late init PCIE Ports
+ *
+ *
+ *
+*  @param[in] NbConfigPtr          Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateInitPorts (
+  IN     AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+  PORT          PortId;
+  BOOLEAN       IsIommuEnabled;
+  NB_INFO       NbInfo;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateInitPorts Enter\n"));
+  IsIommuEnabled = LibNbIsIommuEnabled (NbConfigPtr);
+  NbInfo = LibNbGetRevisionInfo (NbConfigPtr);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  Status = AGESA_SUCCESS;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    CORE  CoreId;
+    CoreId = PcieLibGetCoreId (PortId, NbConfigPtr);
+    if (!PcieLibIsValidCoreId (CoreId, NbConfigPtr)) {
+      PcieLibPowerOffPortLanes (PortId, PcieLinkWidth_x0, NbConfigPtr);
+    } else if (PcieLibIsValidPortId (PortId, NbConfigPtr)) {
+      PCIE_LINK_WIDTH LinkWidth;
+      PCI_ADDR        Port;
+      LinkWidth = PcieLibGetLinkWidth (PortId, NbConfigPtr);
+      CoreId = PcieLibGetCoreId (PortId, NbConfigPtr);
+      Port = PcieLibGetPortPciAddress (PortId, NbConfigPtr);
+      PcieLateCommonPortInit (PortId, NbConfigPtr);
+      if (pPcieConfig->PortConfiguration[PortId].PortDetected == ON) {
+        if (pPcieConfig->PortConfiguration[PortId].PortLinkMode == PcieLinkModeGen2SoftwareInitiated) {
+          PcieInitiateSoftwareGen2 (PortId, NbConfigPtr);
+        }
+        PcieAsmpEnableOnPort (PortId, (UINT8)pPcieConfig->PortConfiguration[PortId].PortAspm, NbConfigPtr);
+      }
+      LibNbPciIndexRMW (Port.AddressValue  | NB_BIF_INDEX, NB_BIFNBP_REG70 , AccessS3SaveWidth32, (UINT32)~BIT12, 0, NbConfigPtr); //PCIE should not ignore malformed packet error or ATS request
+      if (pPcieConfig->PortConfiguration[PortId].PortCompliance == OFF &&
+          pPcieConfig->PortConfiguration[PortId].PortHotplug == OFF &&
+          pPcieConfig->CoreSetting[CoreId].PowerOffUnusedLanes == ON) {
+          PcieLibPowerOffPortLanes (PortId, LinkWidth, NbConfigPtr);
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateInitPorts Exit\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Late init PCIE Cores. Core level feature/power management etc.
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateInitCores (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+  CORE          CoreId;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateInitCores Enter\n"));
+  Status = AGESA_SUCCESS;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Init CoreId [%d]\n", CoreId));
+    if (pPcieConfig->CoreSetting[CoreId].PowerOffPllInL1 == ON) {
+      PcieLibEnablePllPowerOffInL1 (CoreId, pConfig);
+    }
+    if (pPcieConfig->CoreSetting[CoreId].PowerOffPll == ON) {
+      PcieLibPowerOffPll (CoreId, pConfig);
+    }
+    PcieLibMiscLateCoreSetting (CoreId, pConfig);
+    PcieLibManageTxClock   (CoreId, pConfig);
+    PcieLibManageLclkClock (CoreId, pConfig);
+  }
+#ifndef VC1_SUPPORT_DISABLE
+  if (NB_SBDFO == 0 && pPcieConfig->PcieConfiguration.NbSbVc1 == ON) {
+    PcieNbSbSetupVc (pConfig);
+  }
+#endif
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateInitCores Exit\n"));
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Set up NB-SB virtual channel for audio traffic
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieNbSbSetupVc (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT32    VCStatus;
+  PCI_ADDR  Port;
+
+  Port = PcieLibGetPortPciAddress (8, pConfig);
+  if (PcieSbSetupVc (pConfig) == AGESA_SUCCESS) {
+    LibNbPciRMW (Port.AddressValue | NB_PCIP_REG124, AccessS3SaveWidth8, 0x01, 0, pConfig);
+    LibNbPciRMW (Port.AddressValue | NB_PCIP_REG130, AccessS3SaveWidth32, (UINT32)~(BIT24 + BIT25 + BIT26), 0xFE + BIT24, pConfig);
+    LibNbPciRMW (Port.AddressValue | NB_PCIP_REG130, AccessS3SaveWidth32, 0xffffffff, BIT31, pConfig);
+    do {
+      STALL (GET_BLOCK_CONFIG_PTR (pConfig), 200, CIMX_S3_SAVE);
+      LibNbPciRead (Port.AddressValue | NB_PCIP_REG134, AccessWidth32, &VCStatus, pConfig);
+    } while (VCStatus & BIT17);
+    PcieSbEnableVc (pConfig);
+  }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Late common Port Init
+ *
+ *
+ *  @param[in] PortId           Port Id
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateCommonPortInit (
+  IN     PORT        PortId,
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  Status = AGESA_SUCCESS;
+
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Initiate SW Gen2 switch
+ *
+ *
+ *
+ *  @param[in] PortId           Port Id.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieInitiateSoftwareGen2 (
+  IN     PORT            PortId,
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8     LinkSpeedCap;
+  UINT8     PcieCapPtr;
+  UINT8     SecondaryBus;
+  UINT32    Value;
+  UINT32    Counter;
+  PCI_ADDR  Ep;
+  PCI_ADDR  Port;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitiateSoftwareGen2 PortId[%d] Enter\n", PortId));
+  Counter = 5000;
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  LibNbPciRead (Port.AddressValue | NB_PCIP_REG19, AccessWidth8, &SecondaryBus, pConfig);
+  Ep.AddressValue = 0;
+  Ep.Address.Bus = SecondaryBus;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] SecondaryBus = 0x%x \n", SecondaryBus));
+  PcieCapPtr = LibNbFindPciCapability (Ep.AddressValue, PCIE_CAP_ID, pConfig);
+  LibNbPciRead (Ep.AddressValue | (PcieCapPtr + 0xC), AccessWidth8, &LinkSpeedCap, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE] PcieCapPtr = 0x%x \n", PcieCapPtr));
+  if ((LinkSpeedCap & 0xf) < 2) {
+    return;
+  }
+  PcieLibSetLinkMode (PortId, PcieLinkModeGen2, pConfig);
+  LibNbPciIndexRMW (Port.AddressValue  | NB_BIF_INDEX, NB_BIFNBP_REGA4 , AccessS3SaveWidth32, (UINT32)~(BIT18), BIT18 , pConfig);
+  do {
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 200, CIMX_S3_SAVE);
+    LibNbPciIndexRead (Port.AddressValue | NB_PCIP_REGE0, NB_BIFNBP_REGA5, AccessWidth32, &Value, pConfig);
+  } while ((UINT8)Value != 0x10 && Counter-- != 0);
+  LibNbPciIndexRead (Port.AddressValue | NB_PCIP_REGE0, NB_BIFNBP_REGA4, AccessWidth32, &Value, pConfig);
+  if ((Value & BIT24) != 0) {
+  //Initiate link speed change
+    LibNbPciIndexRMW (Port.AddressValue | NB_PCIP_REGE0, NB_BIFNBP_REGA4, AccessS3SaveWidth32, ((UINT32)~BIT7), BIT7, pConfig);
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieInitiateSoftwareGen2 Exit\n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Validate input parameters configuration for PCie Late Init call.
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLateValidateConfiguration (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  NB_INFO     NbInfo;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateValidateConfiguration Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  if (pPcieConfig == NULL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, pConfig);
+    CIMX_ASSERT (FALSE);
+    return  AGESA_FATAL;
+  }
+  if (pPcieConfig->sHeader.InitializerID != INITIALIZED_BY_INITIALIZER) {
+    PcieLibInitializer (pConfig);
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLateValidateConfiguration Exit\n"));
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PcieValidatePortState
+ *    Port disable or port visibility control
+ *
+ *
+ * @param[in] NbConfigPtr  Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieValidatePortState (
+  IN     AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+
+  Status = AGESA_SUCCESS;
+  PcieLibUnHidePorts (NbConfigPtr);
+  PcieLibValidatePortStateInit (NbConfigPtr);
+  PcieForcePortsVisibleOrDisable (NbConfigPtr);
+  PcieLibHidePorts (NbConfigPtr);
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PciePortsVisibleOrDisable
+ *    Set ports always visible or disable based on input parameter
+ *
+ *
+ *
+*  @param[in] NbConfigPtr          Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieForcePortsVisibleOrDisable (
+  IN     AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCIE_CONFIG   *pPcieConfig;
+  PORT          PortId;
+  PCI_ADDR      Port;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, NbConfigPtr)) {
+      Port = PcieLibGetPortPciAddress (PortId, NbConfigPtr);
+      if (pPcieConfig->PortConfiguration[PortId].ForcePortDisable == ON ) {
+        pPcieConfig->PortConfiguration[PortId].PortPresent = OFF;
+        pPcieConfig->PortConfiguration[PortId].PortDetected = OFF;
+      }
+      if (pPcieConfig->PortConfiguration[PortId].PortAlwaysVisible == ON) {
+        LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG70, AccessWidth32, (UINT32)~BIT19, BIT19, NbConfigPtr);
+        pPcieConfig->PortConfiguration[PortId].PortPresent = ON;
+        pPcieConfig->PortConfiguration[PortId].PortDetected = ON;
+      }
+      LibNbPciIndexWrite (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG01,  AccessWidth32, (UINT32*)&pPcieConfig->PortConfiguration[PortId], NbConfigPtr);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
new file mode 100644
index 0000000..8b1782e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLateHwLib.c
@@ -0,0 +1,486 @@
+/**
+ * @file
+ *
+ *  PCIe silicon specific functions library.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc Initialization in late init
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+PcieLibLateInit (
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  CORE  CoreId;
+  PORT  PortId;
+  PCIE_CONFIG *pPcieConfig;
+  PCI_ADDR ClkPciAddress;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  //Restore general setting in scratch
+  LibNbEnableClkConfig (pConfig);
+  LibNbPciRead (ClkPciAddress.AddressValue | NB_CLK_REG78, AccessWidth32, &pPcieConfig->PcieConfiguration, pConfig);
+  LibNbDisableClkConfig (pConfig);
+  // Restore Core setting from scratch
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+//    if (PcieLibIsCoreAccessible (CoreId, pConfig) && pPcieConfig->CoreSetting[CoreId].CoreDisabled != ON ) {
+    UINT32  CoreAddress;
+    CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+    LibNbPciIndexRead (
+      pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+      NB_BIFNB_REG01 | CoreAddress,
+      AccessWidth32,
+      (UINT32*)&pPcieConfig->CoreSetting[CoreId],
+      pConfig
+      );
+//  } else {
+//    pPcieConfig->CoreSetting[CoreId].CoreDisabled = ON;
+//  }
+//    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Recover Core Setting CoreId %d Setting %x Enter\n", CoreId, (UINT32)(pPcieConfig->CoreSetting[CoreId])));
+  }
+  // Restore port Setting from scratch
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig)) {
+      PCI_ADDR Port;
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      //Reload port configuration from scratch register
+      LibNbPciIndexRead (
+        Port.AddressValue | NB_BIF_INDEX,
+        NB_BIFNBP_REG01,
+        AccessWidth32,
+        (UINT32*)&pPcieConfig->PortConfiguration[PortId],
+        pConfig
+        );
+      LibNbPciRead (Port.AddressValue | NB_PCIP_REG108, AccessWidth32, (UINT32*)&pPcieConfig->ExtPortConfiguration[PortId], pConfig);
+//      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Recover Port setting PortId %d Setting %x Enter\n", PortId, (UINT32)(pPcieConfig->PortConfiguration[PortId])));
+    } else {
+      *((UINT32*)&pPcieConfig->ExtPortConfiguration[PortId]) = 0;
+      *((UINT32*)&pPcieConfig->PortConfiguration[PortId]) = 0;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc Initialization in validate port state
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+
+VOID
+PcieLibValidatePortStateInit (
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  CORE        CoreId;
+  PORT        PortId;
+  UINT32      PortAlwaysVisible;
+  UINT32      ForcePortDisable;
+  PCIE_CONFIG *pPcieConfig;
+  PCI_ADDR    ClkPciAddress;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  //Restore general setting in scratch
+  LibNbEnableClkConfig (pConfig);
+  LibNbPciRead (ClkPciAddress.AddressValue | NB_CLK_REG78, AccessWidth32, &pPcieConfig->PcieConfiguration, pConfig);
+  LibNbDisableClkConfig (pConfig);
+  // Restore Core setting from scratch
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+//    if (PcieLibIsCoreAccessible (CoreId, pConfig) && pPcieConfig->CoreSetting[CoreId].CoreDisabled != ON ) {
+    UINT32  CoreAddress;
+    CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+    LibNbPciIndexRead (
+      pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+      NB_BIFNB_REG01 | CoreAddress,
+      AccessWidth32,
+      (UINT32*)&pPcieConfig->CoreSetting[CoreId],
+      pConfig
+      );
+//  } else {
+//    pPcieConfig->CoreSetting[CoreId].CoreDisabled = ON;
+//  }
+//    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Recover Core Setting CoreId %d Setting %x Enter\n", CoreId, (UINT32)(pPcieConfig->CoreSetting[CoreId])));
+  }
+  // Restore port Setting from scratch
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig)) {
+      PCI_ADDR Port;
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      PortAlwaysVisible = pPcieConfig->PortConfiguration[PortId].PortAlwaysVisible;
+      ForcePortDisable = pPcieConfig->PortConfiguration[PortId].ForcePortDisable;
+      //Reload port configuration from scratch register
+      LibNbPciIndexRead (
+        Port.AddressValue | NB_BIF_INDEX,
+        NB_BIFNBP_REG01,
+        AccessWidth32,
+        (UINT32*)&pPcieConfig->PortConfiguration[PortId],
+        pConfig
+        );
+      pPcieConfig->PortConfiguration[PortId].PortAlwaysVisible = PortAlwaysVisible;
+      pPcieConfig->PortConfiguration[PortId].ForcePortDisable = ForcePortDisable;
+      LibNbPciRead (Port.AddressValue | NB_PCIP_REG108, AccessWidth32, (UINT32*)&pPcieConfig->ExtPortConfiguration[PortId], pConfig);
+//      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Recover Port setting PortId %d Setting %x Enter\n", PortId, (UINT32)(pPcieConfig->PortConfiguration[PortId])));
+    } else {
+      *((UINT32*)&pPcieConfig->ExtPortConfiguration[PortId]) = 0;
+      *((UINT32*)&pPcieConfig->PortConfiguration[PortId]) = 0;
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable LCLK clock gating or shutdown LCLK clock banch if possible
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieLibManageLclkClock (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT32      Value;
+  UINT32      Mask;
+  PCI_ADDR    ClkPciAddress;
+  UINT32      CoreAddress;
+  PCIE_CONFIG *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibManageLclkClock [CoreId %d] Enter \n", CoreId));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  ClkPciAddress = pConfig->NbPciAddress;
+  ClkPciAddress.Address.Function = 1;
+  LibNbEnableClkConfig (pConfig);
+
+  if (pPcieConfig->CoreSetting[CoreId].LclkClockGating == ON) {
+    ClkPciAddress.Address.Register = NB_CLK_REGE8;
+    Value = 0;
+    Mask = 0;
+    switch (CoreAddress) {
+    case  GPP1_CORE:
+      ClkPciAddress.Address.Register = NB_CLK_REG94;
+      Mask = BIT16;
+      break;
+    case  GPP2_CORE:
+      Value = BIT28;
+      break;
+    case  GPP3a_CORE:
+      Value = BIT31;
+      break;
+    case  GPP3b_CORE:
+      Value = BIT25;
+      break;
+    case  SB_CORE:
+      ClkPciAddress.Address.Register = NB_CLK_REG94;
+      Mask = BIT24;
+      break;
+    default:
+      CIMX_ASSERT (FALSE);
+    }
+    LibNbPciRMW (ClkPciAddress.AddressValue, AccessS3SaveWidth32, ~Mask, Value, pConfig);
+  }
+  if (pPcieConfig->CoreSetting[CoreId].LclkClockOff == ON) {
+    UINT8   ActiveCoreMap;
+    ActiveCoreMap = PcieLibGetActiveCoreMap (pConfig);
+    if ((ActiveCoreMap & (1 << CoreId)) == 0) {
+      //Core not active we can shutdown LCLK permanantly
+      CORE_INFO *pCoreInfo;
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Shutdown LCKL clock\n"));
+      pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
+      ClkPciAddress.Address.Register = NB_CLK_REGE0;
+      pPcieConfig->CoreSetting[CoreId].CoreDisableStatus = ON;
+      // We have to setup Index for BIFNB to point out to SB core. After this point core registers no longer accesasable
+      LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, 0x00 | SB_CORE, AccessS3SaveWidth32, 0xffffffff, 0x00, pConfig);
+      LibNbPciRMW (ClkPciAddress.AddressValue, AccessS3SaveWidth32, 0xffffffff, 1 << pCoreInfo->LclkOffOffset, pConfig);
+
+      Value = 0;
+      if (CoreAddress == GPP1_CORE) {
+        if ((ActiveCoreMap & 0xb) == 0 && !LibNbIsIommuEnabled (pConfig)) {
+        // Can shutdown master core
+          Value = 1 << pCoreInfo->LclkPermOffOffset;
+        }
+      } else {
+        Value = 1 << pCoreInfo->LclkPermOffOffset;
+      }
+      if (Value != 0) {
+        NbIommuDisconnectPcieCore (CoreId, pConfig);
+        LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG27, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
+
+      }
+    }
+  }
+  LibNbDisableClkConfig (pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power Off Pll for unused lanes.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieLibPowerOffPll (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      CoreAddress;
+  UINT32      PowerOfPllValue;
+  UINT32      PadsMap;
+  //UINT32      TxClockOffValue;
+  UINT32      PowerOfPllRegister;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  PowerOfPllValue = 0;
+  PadsMap = 0;
+  //TxClockOffValue = 0;
+  PowerOfPllRegister = NB_MISC_REG23;
+
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG65 | CoreAddress, AccessS3SaveWidth32, &PadsMap, pConfig);
+  if (CoreAddress == GPP1_CORE || CoreAddress == GPP2_CORE) {
+    if ((PadsMap & 0xf0) == 0xf0) {
+      //Power Off PLL1
+      PowerOfPllValue |= (BIT1 | BIT3);
+      if ((PadsMap & 0x0f) == 0x0f && pPcieConfig->CoreConfiguration[CoreId] != GFX_CONFIG_AABB) {
+        //Power Off PLL0
+        PowerOfPllValue |= (BIT0 | BIT2);
+      }
+    }
+    if (CoreAddress == GPP2_CORE) {
+      PowerOfPllValue <<= 8;
+      //TxClockOffValue = BIT1;
+    } else {
+      //TxClockOffValue = BIT0;
+    }
+    if ((UINT16)PadsMap != 0xffff) {
+      //TxClockOffValue = 0;          //Do not disable TX clock in case any line is ON
+    }
+  }
+  if (CoreAddress == GPP3a_CORE ) {
+    if ((UINT16)PadsMap == 0x3F3F) {
+      PowerOfPllValue = BIT18 | BIT16;
+      //TxClockOffValue = BIT2;
+    }
+  }
+  if (CoreAddress == GPP3b_CORE ) {
+    PowerOfPllRegister = NB_MISC_REG2E;
+    if ((UINT16)PadsMap == 0x0F0F) {
+      PowerOfPllValue = BIT8 | BIT6;
+      //TxClockOffValue = BIT3;
+    }
+  }
+  //Power Off Pll
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, PowerOfPllRegister , AccessS3SaveWidth32, 0xffffffff, PowerOfPllValue, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Power off PLL CoreId %d, Value 0x%x\n", CoreId, PowerOfPllValue));
+  //Turn off TXCLK
+  //LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, TxClockOffValue, pConfig);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable TX clock gating or shutdown TX clock if possible
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.  *
+ */
+VOID
+PcieLibManageTxClock (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      CoreAddress;
+  UINT32      Value;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  if (pPcieConfig->CoreSetting[CoreId].TxClockGating == ON) {
+    switch (CoreAddress) {
+    case  GPP1_CORE:
+      Value = BIT4;
+      break;
+    case  GPP2_CORE:
+      Value = BIT5;
+      break;
+    case  GPP3a_CORE:
+      Value = BIT6;
+      break;
+    case  GPP3b_CORE:
+      Value = BIT24;
+      break;
+    case  SB_CORE:
+      Value = BIT7;
+      break;
+    default:
+      Value = 0;
+      CIMX_ASSERT (FALSE);
+    }
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG40 | CoreAddress, AccessS3SaveWidth32, (UINT32)~BIT6, BIT6, pConfig);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG11 | CoreAddress, AccessS3SaveWidth32, 0xfffffff0, 0x0C, pConfig);
+  }
+  if (pPcieConfig->CoreSetting[CoreId].TxClockOff == ON) {
+    UINT8   ActiveCoreMap;
+    ActiveCoreMap = PcieLibGetActiveCoreMap (pConfig);
+    if ((ActiveCoreMap & (1 << CoreId)) == 0) {
+      //Core not active we can shutdown TX clk permanantly
+      CORE_INFO *pCoreInfo;
+      CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Shutdown TX clock\n"));
+      pPcieConfig->CoreSetting[CoreId].CoreDisableStatus = ON;
+      pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
+      LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG07, AccessS3SaveWidth32, 0xffffffff, 1 << pCoreInfo->TxOffOffset, pConfig);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable Pll Power Down in L1.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.  *
+ */
+VOID
+PcieLibEnablePllPowerOffInL1 (
+  IN      CORE            CoreId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      Value;
+  UINT32      CoreAddress;
+  PORT        PortId;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  if (pPcieConfig->CoreSetting[CoreId].DetectPowerOffPllInL1 == ON && !PciePllOffComatibilityTest (CoreId, pConfig)) {
+    return;
+  }
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig) && PcieLibGetCoreId (PortId, pConfig) == CoreId) {
+      if (pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF) {
+        // set up max exit latency requirment for hotplug ports
+        PCI_ADDR  Port;
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGC1 , AccessS3SaveWidth32, 0xffffffff, 0xf, pConfig);
+      }
+    }
+  }
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  Value = BIT8;
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG40 | CoreAddress, AccessS3SaveWidth32, (UINT32)~(BIT9 + BIT4), BIT3 + BIT0 + BIT12, pConfig);
+  if (CoreAddress == GPP3b_CORE || CoreAddress == GPP3a_CORE || CoreAddress == SB_CORE) {
+    Value |= BIT3;
+  }
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG02 | CoreAddress, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc. core setting.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express- Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieLibMiscLateCoreSetting (
+  IN       CORE  CoreId,
+  IN       AMD_NB_CONFIG   *pConfig
+  )
+{
+//Lock
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX,
+    NB_BIFNB_REG10 | PcieLibGetCoreAddress (CoreId, pConfig),
+    AccessS3SaveWidth32,
+    0xffffffff,
+    BIT0,
+    pConfig
+    );
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLib.c b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
new file mode 100644
index 0000000..2e91cb6
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLib.c
@@ -0,0 +1,1604 @@
+/**
+ * @file
+ *
+ *  PCIe silicon specific functions library.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+UINT32
+PcieLibGetCoreConfiguration (
+  IN       CORE              CoreId,
+  IN       AMD_NB_CONFIG     *pConfig
+  );
+
+AGESA_STATUS
+PcieLibValidateGfxConfig (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+CORE_INFO  CoreInfoTable[] = {
+  { // GPP1_CORE_ID = 0       It is GFX Core (GPP1 Core)
+    GPP1_CORE,            // Core Selector
+    (BIT2 | BIT3),        // Port ID Mask. Defines what ports belongs
+    NB_MISC_REG08,
+    NB_MISC_REG28,        // De-emphasis register
+    NB_MISC_REG26,        // Strap control register
+    28,                   // Strap bit offset
+    NB_CLK_REGF0,
+    NB_MISC_REG35, 26,    // TX drive strength and offset
+    NB_MISC_REG35, 18,    // TX half swing
+    NB_MISC_REG36, 24,    // TX zero deemphasis
+    0,
+    28,
+    23
+  },
+  { // GPP2_CORE_ID = 1       It is GFX2 Core (GPP2 Core)
+    GPP2_CORE,            // Core Selector
+    (BIT11 | BIT12),      // Port ID Mask. Defines what ports belongs
+    NB_MISC_REG08,
+    NB_MISC_REG27,        // De-emphasis register
+    NB_MISC_REG26,        // Strap control register
+    29,                   // Strap bit offset
+    NB_CLK_REGF0,
+    NB_MISC_REG35, 28,    // TX drive strength and offset
+    NB_MISC_REG35, 19,    // TX half swing
+    NB_MISC_REG36, 26,    // TX zero deemphasis
+    1,
+    29,
+    24
+  },
+  { // GPP3a_CORE_ID = 2       It is GPP Core (GPP3a Core)
+    GPP3a_CORE,           // Core Selector
+    (BIT4 | BIT5 | BIT6 | BIT7 | BIT9 | BIT10), // Port ID Mask. Defines what ports belongs
+    NB_MISC_REG08,
+    NB_MISC_REG28,        // De-emphasis register
+    NB_MISC_REG26,        // Strap control register
+    30,                   // Strap bit offset
+    NB_CLK_REGF4,
+    NB_MISC_REG35, 30,    // TX drive strength and offset
+    NB_MISC_REG35, 20,    // TX half swing
+    NB_MISC_REG36, 28,    // TX zero deemphasis
+    2,
+    30,
+    25
+  },
+  { // GPP3b_CORE_ID = 3       It is GPP2 Core (GPP3b Core)
+    GPP3b_CORE,           // Core Selector
+    (BIT13),              // Port ID Mask. Defines what ports belongs
+    NB_MISC_REG2A,
+    NB_MISC_REG2D,        // De-emphasis register
+    NB_MISC_REG2D,        // Strap control register
+    21,                   // Strap bit offset
+    NB_CLK_REGF4,
+    NB_MISC_REG2C, 4,     // TX drive strength and offset
+    NB_MISC_REG2C, 2,     // TX half swing
+    NB_MISC_REG2B, 10,    // TX zero deemphasis
+    3,
+    31,
+    26
+  },
+  { // SB_CORE_ID  = 4       It is SB Core
+    SB_CORE,              // Core Selector
+    (BIT8),               // Port ID Mask. Defines what ports belongs
+    NB_MISC_REG08,
+    NB_MISC_REG6F,        // De-emphasis register
+    0x0,
+    0x0,
+    0x0,
+    NB_MISC_REG68, 8,     // TX drive strength and offset
+    NB_MISC_REG67, 27,    // TX half swing
+    NB_MISC_REG68, 20,    // TX zero deemphasis
+    0xff,
+    0xff,
+    0xff
+  }
+};
+
+
+PORT_INFO pGfxPortFullA = {
+  PcieLinkWidth_x16, 0, 0
+};
+
+PORT_INFO pGfxPortA = {
+  PcieLinkWidth_x8, 0, 96
+};
+
+PORT_INFO pGfxPortB = {
+  PcieLinkWidth_x8, 8, 96
+};
+
+PORT_INFO pGpp420000[] = {
+  {PcieLinkWidth_x4, 0, 56},
+  {PcieLinkWidth_x2, 4, 28}
+};
+
+PORT_INFO pGpp411000[] = {
+  {PcieLinkWidth_x4, 0, 56},
+  {PcieLinkWidth_x1, 4, 14},
+  {PcieLinkWidth_x1, 5, 14}
+};
+
+PORT_INFO pGpp222000[] = {
+  {PcieLinkWidth_x2, 0, 28},
+  {PcieLinkWidth_x2, 2, 28},
+  {PcieLinkWidth_x2, 4, 28}
+};
+
+PORT_INFO pGpp221100[] = {
+  {PcieLinkWidth_x2, 0, 28},
+  {PcieLinkWidth_x2, 2, 28},
+  {PcieLinkWidth_x1, 4, 14},
+  {PcieLinkWidth_x1, 5, 14}
+};
+
+PORT_INFO pGpp211110[] = {
+  {PcieLinkWidth_x2, 0, 28},
+  {PcieLinkWidth_x1, 2, 14},
+  {PcieLinkWidth_x1, 3, 14},
+  {PcieLinkWidth_x1, 4, 14},
+  {PcieLinkWidth_x4, 0, 0 },  //Dummy entry
+  {PcieLinkWidth_x1, 5, 14}
+};
+
+PORT_INFO pGpp111111[] = {
+  {PcieLinkWidth_x1, 0, 14},
+  {PcieLinkWidth_x1, 1, 14},
+  {PcieLinkWidth_x1, 2, 14},
+  {PcieLinkWidth_x1, 3, 14},
+  {PcieLinkWidth_x4, 0, 0 },  //Dummy entry
+  {PcieLinkWidth_x1, 4, 14},
+  {PcieLinkWidth_x1, 5, 14}
+};
+
+GPP_CFG_INFO GppCfgInfoTable[] = {
+  {pGpp420000, 0xff50fff4},
+  {pGpp411000, 0xf650fff4},
+  {pGpp222000, 0xff60f5f4},
+  {pGpp221100, 0xf760f5f4},
+  {pGpp211110, 0xf97065f4},
+  {pGpp111111, 0xfA907654}
+};
+
+CONST PORT_STATIC_INFO  PortInfoTable[] = {
+//Training  Reversal  Deemp    Mapping   Hotplug Offset
+  {4 ,      3,        0 ,      4       , 0         },  //2
+  {5 ,      4,        1 ,      8       , 8         },  //3
+  {21,      7,        2 ,      12      , 0         },  //4
+  {22,      8,        3 ,      16      , 8         },  //5
+  {23,      9,        4 ,      20      , 16        },  //6
+  {24,      10,       5 ,      24      , 0xFF      },  //7
+  {20,      0,        1 ,      0xFF    , 0xFF      },  //8
+  {25,      11,       6 ,      28      , 0xFF      },  //9
+  {26,      12,       7 ,      0       , 0xFF      },  //10
+  {6 ,      5,        30,      4       , 16        },  //11
+  {7 ,      6,        31,      8       , 24        },  //12
+  {4 ,      25,       5 ,      12      , 24        }   //13
+};
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Port Training Control
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] Operation Release or Hold training
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+VOID
+PcieLibPortTrainingControl (
+  IN       PORT               PortId,
+  IN       PCIE_LINK_TRAINING Operation,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  CORE              CoreId;
+  CORE_INFO         *pCoreInfo;
+  PORT_STATIC_INFO  *pStaticPortInfo;
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  pStaticPortInfo = PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig);
+  pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    pCoreInfo->TrainingRegister,
+    AccessWidth32,
+    ~(1 << pStaticPortInfo->TrainingAddress),
+    (Operation == PcieLinkTrainingHold)?(1 << pStaticPortInfo->TrainingAddress):0,
+    pConfig
+    );
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCI address of Port.
+ * Function return pcie Address based on port mapping and core configuration.
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+PCI_ADDR
+PcieLibGetPortPciAddress (
+  IN       PORT             PortId,
+  IN       AMD_NB_CONFIG    *pConfig
+  )
+{
+  PCI_ADDR  Port;
+  UINT32  RemapEnable;
+  UINT32  RemapValue;
+  PORT_STATIC_INFO  *pPortStaticInfo;
+
+  RemapEnable = 0;
+  RemapValue = 0;
+  pPortStaticInfo = PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig);
+  Port.AddressValue = pConfig->NbPciAddress.AddressValue;
+
+  LibNbPciIndexRead (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    NB_MISC_REG20,
+    AccessWidth32,
+    &RemapEnable,
+    pConfig
+    );
+  if (pPortStaticInfo->MappingAddress != 0xff && RemapEnable & BIT0) {
+    LibNbPciIndexRead (
+      pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+      (PortId > 9)? NB_MISC_REG21:NB_MISC_REG20,
+      AccessWidth32,
+      &RemapValue,
+      pConfig
+      );
+    RemapValue = (RemapValue >> pPortStaticInfo->MappingAddress) & 0xf;
+  }
+  if (RemapValue == 0) {
+    RemapValue = PortId;
+  }
+  Port.Address.Device = RemapValue;
+  return  Port;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Core register selector.
+ * Function return selector to access BIFNB register space for selected core
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+UINT32
+PcieLibGetCoreAddress (
+  IN       CORE             CoreId,
+  IN       AMD_NB_CONFIG    *pConfig
+  )
+{
+  return  PcieLibGetCoreInfo (CoreId, pConfig)->CoreSelector;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Core Id
+ * Function return PCIE core ID base on Port ID
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ * @retval              Core ID.
+ */
+CORE
+PcieLibGetCoreId (
+  IN       PORT           PortId,
+  IN       AMD_NB_CONFIG  *pConfig
+  )
+{
+  CORE_INFO *pCoreInfoTable = (CORE_INFO*)FIX_PTR_ADDR (&CoreInfoTable[0], NULL);
+  CORE  CoreId;
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    if (pCoreInfoTable[CoreId].PortIdBitMap & (1 << PortId)) {
+      break;
+    }
+  }
+    return  CoreId;
+}
+
+/*
+INDIRECT_REG_ENTRY
+STATIC
+PcieMiscInitTable[] = {
+  {
+    NB_MISC_REG20,
+    (UINT32)~BIT1,
+    0x0
+  }, //enable static device remapping by default
+  {
+    NB_MISC_REG22,
+    0xffffffff,
+    BIT27
+  }, //[10]CMGOOD_OVERRIDE for all 5 pcie cores.
+  {
+    NB_MISC_REG6B,
+    0xffffffff,
+    (UINT32) (0x1f << 27)
+  }, //[13][12]Turn Off Offset Cancellation
+  {
+    NB_MISC_REG37,
+    (UINT32)~(BIT11 + BIT12 + BIT13),
+    0x0
+  }, //[14][13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG67,
+    (UINT32)~(BIT26 + BIT10 + BIT11),
+    BIT11
+  }, //[13]Disables Rx Clock gating in CDR
+     //[16]Sets Electrical  Idle Threshold
+  {
+    NB_MISC_REG2C,
+    (UINT32)~(BIT10),
+    0x0
+  }, //[13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG2A,
+    (UINT32)~(BIT17 + BIT16),
+    BIT17
+  }, //[16]Sets Electrical l Idle Threshold
+  {
+    NB_MISC_REG32,
+    (UINT32)~(0x3F << 20),
+    (UINT32) (0x2A << 20)
+  }  //[17][16]Sets Electrical Idle Threshold
+};
+*/
+
+
+
+UINT8 GppConfigTable[] = {
+  0x0, 0x1, 0x2, 0xC, 0xA, 0x4, 0xB
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Core Configuration.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieLibSetCoreConfiguration (
+  IN       CORE           CoreId,
+  IN       AMD_NB_CONFIG  *pConfig
+  )
+{
+  UINT32      LaneReversalValue;
+  PORT        PortId;
+  PCIE_CONFIG *pPcieConfig;
+  CORE_INFO   *pCoreInfo;
+  CORE        CoreAddress;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibSetCoreConfiguration CoreId = %d Configuration = 0x%x Enter\n", CoreId, pPcieConfig->CoreConfiguration[CoreId]));
+  pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  LaneReversalValue = 0;
+  PcieLibCoreReset (CoreId, PcieCoreResetAllAssert, pConfig);
+  PcieLibStrapModeControl (CoreId, PcieCoreStrapConfigStart, pConfig);
+  //Setup GFX/GFX2 core configuration
+  if (CoreAddress == GPP1_CORE || CoreAddress == GPP2_CORE) {
+    if (pPcieConfig->CoreConfiguration[CoreId] == GFX_CONFIG_AABB) {
+      LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, 0xffffffff, (CoreAddress == GPP1_CORE)?BIT8:BIT9, pConfig);
+      STALL (GET_BLOCK_CONFIG_PTR (pConfig), 2000, 0);
+    }
+    if (pPcieConfig->CoreSetting[CoreId].RefClockInput == ON) {
+      LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG6C, AccessWidth32, 0xffffffff, (CoreAddress == GPP1_CORE)?BIT9:BIT31, pConfig);
+    }
+  }
+  //Setup GPP core configuration
+  if (CoreAddress == GPP3a_CORE) {
+    UINT32  Mux;
+    UINT8   *pGppConfigTable;
+
+    Mux = 0;
+    pGppConfigTable = (UINT8*)FIX_PTR_ADDR (&GppConfigTable[0], NULL);
+    LibNbPciIndexRMW (
+      pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+      NB_MISC_REG67, AccessWidth32,
+      0xfffffff0,
+      (UINT32)pGppConfigTable[pPcieConfig->CoreConfiguration[CoreId]],
+      pConfig
+      );
+    switch (pPcieConfig->CoreConfiguration[CoreId]) {
+    case  GPP_CONFIG_GPP420000:
+      Mux = (pPcieConfig->PortConfiguration[6].PortReversed == ON)?0xF05BA00:0x055B000;
+      break;
+    case  GPP_CONFIG_GPP411000:
+      Mux = 0x215B400;
+      break;
+    case  GPP_CONFIG_GPP222000:
+    case  GPP_CONFIG_GPP211110:
+      Mux = (pPcieConfig->PortConfiguration[4].PortReversed == ON)?0xFFF0AAA:0xFF0BAA0;
+      break;
+    case  GPP_CONFIG_GPP221100:
+      Mux = 0x215B400;
+      break;
+    case  GPP_CONFIG_GPP111111:
+      Mux = 0x2AA3554;
+      break;
+    default:
+      CIMX_ASSERT (FALSE);
+    }
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32,  0xf0000000, Mux, pConfig);
+  }
+  PcieLibStrapModeControl (CoreId, PcieCoreStrapConfigStop, pConfig);
+  PcieLibCoreReset (CoreId, PcieCoreResetAllDeassert, pConfig);
+  //Setup lane reversal
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig)) {
+      if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON &&
+          pPcieConfig->PortConfiguration[PortId].PortReversed == ON &&
+          (pCoreInfo->PortIdBitMap & (1 << PortId)) != 0) {
+        PORT_STATIC_INFO *pStaticPortInfo = PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig);
+        LaneReversalValue |= (1 << (pStaticPortInfo->ReversalAddress));
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Port reversed Port Id %d Native Id %d, Reversal Address %d \n", PortId, PcieLibNativePortId (PortId, pConfig), pStaticPortInfo->ReversalAddress));
+      }
+    }
+  }
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    (CoreAddress == GPP3b_CORE) ? NB_MISC_REG2D : NB_MISC_REG27,
+    AccessWidth32, 0xffffffff,
+    LaneReversalValue,
+    pConfig
+    );
+  //Setup performance mode
+  if (pPcieConfig->CoreSetting[CoreId].PerformanceMode == ON) {
+    UINT32  RegisterAddress;
+    switch (CoreAddress) {
+    case  GPP1_CORE:
+      RegisterAddress = NB_MISC_REG33;
+      break;
+    case  GPP2_CORE:
+      RegisterAddress = NB_MISC_REG22;
+      break;
+    default:
+      RegisterAddress = 0;
+      break;
+    }
+    if (RegisterAddress != 0) {
+      LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, RegisterAddress , AccessWidth32, 0xfffffC00, 0xB5, pConfig);
+    }
+  }
+  //Setup Tx Drive Strength
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    pCoreInfo->TxDriveStrengthRegister ,
+    AccessWidth32,
+    ~(0x3 << pCoreInfo->TxDriveStrengthOffset),
+    pPcieConfig->CoreSetting[CoreId].TxDriveStrength << pCoreInfo->TxDriveStrengthOffset,
+    pConfig
+    );
+  //Setup Tx half swing
+  if (pPcieConfig->CoreSetting[CoreId].TxHalfSwingMode == ON) {
+    LibNbPciIndexRMW (
+      pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+      pCoreInfo->TxHalfSwingRegister,
+      AccessWidth32,
+      ~(0x1 << pCoreInfo->TxHalfSwingOffset),
+      0x0,
+      pConfig
+    );
+    // Setup half swing deemphasis
+    LibNbPciIndexRMW (
+      pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+      pCoreInfo->TxHalfSwingDeepmhasisRegister ,
+      AccessWidth32,
+      ~(0x3 << pCoreInfo->TxHalfSwingDeepmhasisOffset),
+      0x0,
+      pConfig
+    );
+  }
+  //Finalize straps for this core
+  PcieLibStrapModeControl (CoreId, PcieCoreStrapConfigStart, pConfig);
+  PcieLibStrapModeControl (CoreId, PcieCoreStrapConfigStop, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibSetCoreConfiguration Exit\n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Core Configuration
+ * Function return GPPSB/GFX/GFX2 core configuration.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+UINT32
+PcieLibGetCoreConfiguration (
+  IN       CORE              CoreId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32  CoreConfiguration;
+  UINT32  Value;
+  CORE    CoreAddress;
+
+  CoreConfiguration = 0,
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+//  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibGetCoreConfiguration (Core = 0x%x) Enter\n", CoreAddress));
+  if (CoreAddress == GPP1_CORE || CoreAddress == GPP2_CORE) {
+    LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, &Value, pConfig);
+    CoreConfiguration = (Value & ((CoreAddress == GPP1_CORE) ? BIT8:BIT9))? GFX_CONFIG_AABB:GFX_CONFIG_AAAA;
+  } else {
+    if (CoreAddress == GPP3a_CORE) {
+      UINT8 *pGppConfigTable;
+      pGppConfigTable = (UINT8*)FIX_PTR_ADDR (&GppConfigTable[0], NULL);
+      LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG67, AccessWidth32, &Value, pConfig);
+      while (pGppConfigTable[CoreConfiguration] != (Value & 0xf)) {
+        CoreConfiguration++;
+      }
+    }
+  }
+//  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibGetCoreConfiguration (CoreConfiguration = 0x%x) Exit\n", CoreConfiguration));
+  return    CoreConfiguration;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return link misc information (max link width, current link width, lane 0 map)
+ *
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+LINK_INFO
+PcieLibGetPortLinkInfo (
+  IN       PORT                PortId,
+  IN       AMD_NB_CONFIG       *pConfig
+  )
+{
+  UINT32    Value;
+  PCI_ADDR  Port;
+  PORT_INFO *pPortInfo;
+  LINK_INFO LinkInfo = {0, 0, 0};
+
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  pPortInfo = PcieLibGetPortInfo (PortId, pConfig);
+//Read current link width
+  LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, pConfig);
+  Value = (Value >> 4) & 0xf;
+  LinkInfo.LinkWidth = (UINT8)Value;
+  LinkInfo.MaxLinkWidth = pPortInfo->MaxLinkWidth;
+  LinkInfo.Line0Offset = pPortInfo->Line0Offset;
+//  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    PortId %d LinkWidth 0x%x MaxLinkWidth 0x%x Line0Offset %d\n", PortId, LinkInfo.LinkWidth, LinkInfo.MaxLinkWidth,LinkInfo.Line0Offset));
+  return  LinkInfo;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if port in lane reversed configuration.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+BOOLEAN
+PcieLibIsPortReversed (
+  IN       PORT              PortId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  BOOLEAN Result;
+  UINT32  Value;
+  PCIE_CONFIG *pPcieConfig;
+  PCI_ADDR Port;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REG50, AccessWidth32, &Value, pConfig);
+  if (pPcieConfig->PortConfiguration[PortId].PortReversed == ON || (Value & BIT0) != 0) {
+    Result = TRUE;
+  } else {
+    Result = FALSE;
+  }
+  return Result;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if core id valid for current silicon
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+BOOLEAN
+PcieLibIsValidCoreId (
+  IN       CORE               CoreId,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT32  CoreAddress;
+  NB_INFO NbInfo;
+
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  if (CoreAddress == GPP3b_CORE) {
+    if (NbInfo.Type == NB_RD890 || NbInfo.Type == NB_SR5690) {
+      return TRUE;
+    } else {
+      return FALSE;
+    }
+  }
+  if (CoreAddress == GPP2_CORE && (NbInfo.Type == NB_RD780 || NbInfo.Type == NB_RX780 || NbInfo.Type == NB_SR5650 || NbInfo.Type == NB_990X || NbInfo.Type == NB_970)) {
+    return FALSE;
+  }
+  return TRUE;
+}
+
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if port Id valid for current core configuration
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+BOOLEAN
+PcieLibIsValidPortId (
+  IN       PORT               PortId,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  CORE  CoreId;
+  NB_INFO NbInfo;
+
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  if (!PcieLibIsValidCoreId (CoreId, pConfig)) {
+    return FALSE;
+  }
+  if ((PortId == 3 || PortId == 12) && PcieLibGetCoreConfiguration (CoreId, pConfig) != GFX_CONFIG_AABB) {
+    return FALSE;
+  }
+  if (PortId == 3  && NbInfo.Type == NB_970)  {
+    return FALSE;
+  }
+  if (PortId == 12 && NbInfo.Type == NB_SR5670) {
+    return FALSE;
+  }
+  if (PortId == 13 || PortId == 8) {
+    return TRUE;
+  } else {
+    return (PcieLibNativePortId (PortId, pConfig) == 0xf)?FALSE:TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Link mode. Gen1/Gen2/Gen2-Advertize
+ *
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] Operation Link Mode
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+
+VOID
+PcieLibSetLinkMode (
+  IN       PORT               PortId,
+  IN       PCIE_LINK_MODE     Operation,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  PCI_ADDR          Port;
+  UINT8             LinkSpeed;
+  UINT32            LinkDeemphasisMask;
+  UINT32            LinkDeemphasisValue;
+  UINT32            RegA4Value;
+  UINT32            RegA2Value;
+  UINT32            RegC0Value;
+  CORE_INFO         *pCoreInfo;
+  PORT_STATIC_INFO  *pStaticPortInfo;
+  PCIE_CONFIG       *pPcieConfig;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibSetLinkMode PortId %d Operation %d Enter\n", PortId, Operation));
+  LinkSpeed = 2;
+  RegA4Value = BIT29 + BIT0;
+  RegA2Value = 0;
+  RegC0Value = 0;
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  pStaticPortInfo = PcieLibGetStaticPortInfo (PcieLibNativePortId (PortId, pConfig), pConfig);
+  pCoreInfo = PcieLibGetCoreInfo (PcieLibGetCoreId (PortId, pConfig), pConfig);
+
+  LinkDeemphasisValue = pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis << pStaticPortInfo->DeemphasisAddress;
+  LinkDeemphasisMask = ~(1 << pStaticPortInfo->DeemphasisAddress);
+
+  if (Operation == PcieLinkModeGen1 || Operation == PcieLinkModeGen2AdvertizeOnly) {
+    RegC0Value = BIT15;
+    RegA2Value = BIT13;
+    if (Operation == PcieLinkModeGen1) {
+      RegA4Value = 0;
+      LinkSpeed = 1;
+      LinkDeemphasisValue = 0;
+    }
+  }
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "     pCoreInfo->DeemphasisRegister %x pStaticPortInfo->DeemphasisAddress %x LinkDeemphasisMask %x, LinkDeemphasisValue  %x\n", pCoreInfo->DeemphasisRegister, pStaticPortInfo->DeemphasisAddress, LinkDeemphasisMask, LinkDeemphasisValue));
+  LibNbPciIndexRMW (Port.AddressValue  | NB_BIF_INDEX, NB_BIFNBP_REGA4 , AccessWidth32, (UINT32)~(BIT0 + BIT29), RegA4Value , pConfig);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, pCoreInfo->DeemphasisRegister, AccessWidth32, LinkDeemphasisMask, LinkDeemphasisValue , pConfig);
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG88, AccessWidth8, 0xF0, LinkSpeed, pConfig);
+  LibNbPciIndexRMW (Port.AddressValue  | NB_BIF_INDEX, NB_BIFNBP_REGC0 , AccessWidth32, (UINT32)~(BIT15), RegC0Value , pConfig);
+  LibNbPciIndexRMW (Port.AddressValue  | NB_BIF_INDEX, NB_BIFNBP_REGA2 , AccessWidth32, (UINT32)~(BIT13), RegA2Value , pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Request PCIE reset to be executed
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLibRequestPciReset (
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  SCRATCH_1     Scratch;
+
+  Status = AGESA_UNSUPPORTED;
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+  if (Scratch.ResetCount == 0xf) {
+    Scratch.ResetCount = 0;
+  }
+  if (Scratch.ResetCount < 5) {
+    ++Scratch.ResetCount;
+    LibNbPciIndexWrite (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+    if (LibNbCallBack (PHCB_AmdGeneratePciReset, WARM_RESET , pConfig) != AGESA_SUCCESS) {
+      LibNbIoRMW (0xCF9, AccessWidth8, 0, 0x6, pConfig);
+    }
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Control Core Reset
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] Operation Assert/Deassert/Check core reset
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+PCI_CORE_RESET
+PcieLibCoreReset (
+  IN      CORE            CoreId,
+  IN      PCI_CORE_RESET  Operation,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT32 Value;
+  UINT32 CalibrationReset;
+  UINT32 GlobalReset;
+  UINT32 RegisterAddress;
+  UINT32 CoreAddress;
+
+  RegisterAddress = NB_MISC_REG08;
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  switch (CoreAddress) {
+  case  GPP3b_CORE:
+    RegisterAddress = NB_MISC_REG2A;            // break missing and it is not an error.
+  case  GPP1_CORE:
+    CalibrationReset = BIT14;
+    GlobalReset = BIT15;
+    break;
+  case  GPP2_CORE:
+    CalibrationReset = BIT12;
+    GlobalReset = BIT13;
+    break;
+  case  GPP3a_CORE:
+    CalibrationReset = BIT30;
+    GlobalReset = BIT31;
+    break;
+  default:
+    return PcieCoreResetAllDeassert;
+  }
+  switch (Operation) {
+  case PcieCoreResetAllDeassert:
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, RegisterAddress, AccessS3SaveWidth32, ~CalibrationReset, 0x0, pConfig);
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 200, 0);
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, RegisterAddress, AccessS3SaveWidth32, ~GlobalReset, 0x0, pConfig);
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 2000, 0);
+    break;
+  case PcieCoreResetAllAssert:
+    LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, RegisterAddress, AccessS3SaveWidth32, 0xffffffff, CalibrationReset | GlobalReset, pConfig);
+    break;
+  case PcieCoreResetAllCheck:
+    LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, RegisterAddress, AccessS3SaveWidth32, &Value, pConfig);
+    Operation = (Value & (CalibrationReset | GlobalReset))?PcieCoreResetAllAssert:PcieCoreResetAllDeassert;
+    break;
+  default:
+    CIMX_ASSERT (FALSE);
+  }
+  return Operation;
+}
+
+UINT8  GfxLineMapTable[] = {
+  0x00, 0x01, 0x01, 0x03, 0x0f, 0x00, 0xFF
+};
+UINT8  GppLineMapTable[] = {
+  0x00, 0x01, 0x03, 0x0F
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Power off port lanes.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] Width     Port Link Width.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+VOID
+PcieLibPowerOffPortLanes (
+  IN       PORT              PortId,
+  IN       PCIE_LINK_WIDTH   Width,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  CORE      CoreId;
+  LINK_INFO LinkInfo;
+  UINT32    PowerOffPads;
+  UINT32    CoreAddress;
+  UINT8*    pLineMapTable;
+  UINT16    MaxLaneBitMap;
+  UINT16    LaneBitMap;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibPowerOffPortLanes (PortId = %d, Width = %d) Enter\n", PortId, Width));
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  LinkInfo = PcieLibGetPortLinkInfo (PortId, pConfig);
+  CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+  if (CoreAddress == GPP1_CORE || CoreAddress == GPP2_CORE) {
+    pLineMapTable = &GfxLineMapTable[0];
+    LinkInfo.Line0Offset /= 2;
+  } else {
+    pLineMapTable = &GppLineMapTable[0];
+  }
+  pLineMapTable = (UINT8*)FIX_PTR_ADDR (pLineMapTable, NULL);
+  LaneBitMap = pLineMapTable[Width];
+  MaxLaneBitMap = pLineMapTable[LinkInfo.MaxLinkWidth];
+  if (PcieLibIsPortReversed (PortId, pConfig)) {
+    LaneBitMap = (UINT16)LibNbBitReverse ((UINT32)LaneBitMap, LibAmdBitScanForward (MaxLaneBitMap), LibAmdBitScanReverse (MaxLaneBitMap));
+  }
+  PowerOffPads = (MaxLaneBitMap ^ LaneBitMap) << LinkInfo.Line0Offset;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Pads %x  Exit\n", PowerOffPads));
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_BIF_INDEX, NB_BIFNB_REG65 | CoreAddress, AccessWidth32, 0xffffffff, PowerOffPads | (PowerOffPads << 8), pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibPowerOffPortLanes  Exit\n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Hide Unused Ports
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieLibHidePorts (
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32      PresentPortMask;
+  UINT32      DetectedPortMask;
+  UINT32      HotplugPortMask;
+  UINT32      Value;
+  PORT        PortId;
+  PCIE_CONFIG *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibHidePorts Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  PresentPortMask = 0;
+  DetectedPortMask = 0;
+  HotplugPortMask = 0;
+  // Hide SB Port
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG00, AccessS3SaveWidth32, (UINT32)~BIT6, 0, pConfig);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON && PcieLibIsValidPortId (PortId, pConfig)) {
+      PCI_ADDR Port;
+      Port = PcieLibGetPortPciAddress (PortId, pConfig);
+      if (pPcieConfig->PortConfiguration[PortId].PortDetected == ON ) {
+        DetectedPortMask |= 1 << Port.Address.Device;
+      }
+      if (pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF) {
+        HotplugPortMask |= 1 << Port.Address.Device;
+      }
+      PresentPortMask |= 1 << Port.Address.Device;
+    }
+  }
+
+  if (pPcieConfig->PcieConfiguration.DisableHideUnusedPorts == ON) {
+    Value = PresentPortMask;
+  } else {
+    Value = DetectedPortMask | HotplugPortMask;
+  }
+  //CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Present Port 0x%x Visible Ports 0x%xExit\n",PresentPortMask,VisiblePortMask));
+  Value = (~((Value & (0xFC)) + ((Value & 0x3E00) << 7))) & 0x1F00FC;
+  // Hide GFX/GFX2/GPP/GPP2 Ports
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, 0xffffffff, Value, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibHidePorts Exit\n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * UnHide all PCIE Ports
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+VOID
+PcieLibUnHidePorts (
+  IN      AMD_NB_CONFIG    *pConfig
+  )
+{
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, (UINT32)~0x1F00FCul, 0, pConfig);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG00, AccessS3SaveWidth32, (UINT32)~BIT6, BIT6, pConfig);
+}
+
+
+
+PCIE_DEFAULT_CONFIG PcieDefaultConfig = {
+  {0, 1, 0, 0},
+  {
+    {0, 1, 1, 1, 1, 1, 1, 0, PcieTxDriveStrangth22mA, 0, 0, PcieMediumChannel, 1, 1, 1},   //GPP1
+    {0, 1, 1, 1, 1, 1, 1, 0, PcieTxDriveStrangth22mA, 0, 0, PcieMediumChannel, 1, 1, 1},   //GPP2
+    {0, 1, 1, 1, 1, 1, 1, 0, PcieTxDriveStrangth22mA, 0, 0, PcieMediumChannel, 1, 1, 1},   //GPP3a
+    {0, 1, 1, 1, 1, 1, 0, 0, PcieTxDriveStrangth22mA, 0, 0, PcieMediumChannel, 1, 1, 1},   //GPP3b
+    {0, 1, 0, 1, 1, 1, 0, 0, PcieTxDriveStrangth22mA, 0, 0, PcieMediumChannel, 0, 0, 0}    //SB
+  },
+  (BIT2 + BIT4 + BIT5 + BIT6 + BIT7 + BIT8 + BIT9 + BIT10 + BIT11 + BIT13) | (BIT3 + BIT12),
+  0,
+  2,
+  0,
+  60,
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for all NB.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdPcieInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  Status = LibNbApiCall (PcieLibInitializer, ConfigPtr);
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize default PCIE_CONFIG setting
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLibInitializer (
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  CORE                CoreId;
+  PCIE_CONFIG         *pPcieConfig;
+  PCIE_DEFAULT_CONFIG *pPcieDefaultConfig;
+  AMD_NB_CONFIG_BLOCK *ConfigPtr;
+  PORT                PortId;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibInitializer Enter\n"));
+  pPcieConfig  = GET_PCIE_CONFIG_PTR (pConfig);
+  if (pPcieConfig == NULL) {
+    return  AGESA_WARNING;
+  }
+  if (pPcieConfig->sHeader.InitializerID == INITIALIZED_BY_INITIALIZER) {
+    return  AGESA_SUCCESS;
+  }
+  ConfigPtr = GET_BLOCK_CONFIG_PTR (pConfig);
+  LibAmdMemFill (pPcieConfig, 0, sizeof (PCIE_CONFIG), (AMD_CONFIG_PARAMS *)&(pPcieConfig->sHeader));
+  pPcieConfig->sHeader.InitializerID = INITIALIZED_BY_INITIALIZER;
+  pPcieDefaultConfig = (PCIE_DEFAULT_CONFIG*)FIX_PTR_ADDR (&PcieDefaultConfig, NULL);
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    pPcieConfig->CoreSetting[CoreId] = pPcieDefaultConfig->CoreSetting[CoreId];
+  }
+  pPcieConfig->PcieConfiguration = pPcieDefaultConfig->PcieConfiguration;
+  if (ConfigPtr->PlatformType == DesktopPlatform) {
+    pPcieConfig->PcieConfiguration.NbSbVc1 = ON;
+  }
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis = PcieTxDeemphasis3p5dB;
+  }
+  pPcieConfig->CoreConfiguration[2] = PcieLibGetCoreConfiguration (2, pConfig);
+  pPcieConfig->ReceiverDetectionPooling = pPcieDefaultConfig->ReceiverDetectionPooling;
+  pPcieConfig->ResetToTrainingDelay = pPcieDefaultConfig->ResetToTrainingDelay;
+  pPcieConfig->ExtPortConfiguration[8].PortL1ImmediateACK = ON;
+  pPcieConfig->TrainingToLinkTestDelay = pPcieDefaultConfig->TrainingToLinkTestDelay;
+  pPcieConfig->DeviceInitMaskS1 = pPcieDefaultConfig->DeviceInitMaskS1;
+  pPcieConfig->DeviceInitMaskS2 = pPcieDefaultConfig->DeviceInitMaskS2;
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibInitializer Exit\n"));
+  return  AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Validate Gfx Core Configuration
+ *
+ *
+ *
+ *
+ *
+ */
+AGESA_STATUS
+PcieLibValidateGfxConfig (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  CORE        CoreId;
+  PCIE_CONFIG *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieLibValidateGfxConfig Enter\n"));
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    CoreConfiguration[%d] = \n", CoreId));
+  if (pPcieConfig->CoreConfiguration[CoreId] == 0x0) {
+    pPcieConfig->CoreConfiguration[CoreId] = (pPcieConfig->PortConfiguration[PortId].PortPresent == ON)?GFX_CONFIG_AABB:GFX_CONFIG_AAAA;
+  } else {
+    if (pPcieConfig->CoreConfiguration[CoreId] != GFX_CONFIG_AABB &&
+      pPcieConfig->CoreConfiguration[CoreId] != GFX_CONFIG_AAAA) {
+      //We have received request for unknown configuration.
+      //pPcieConfig->CoreSetting[CoreId].CoreDisabled = ON;
+      pPcieConfig->PortConfiguration[PortId].PortPresent = 0;
+      pPcieConfig->PortConfiguration[PortId - 1].PortPresent = 0;
+      return AGESA_WARNING;
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    CoreConfiguration[%d] = %x\n", CoreId, pPcieConfig->CoreConfiguration[CoreId]));
+  return  AGESA_SUCCESS;
+}
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Validate input parameters for early PCIE init.
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieLibInitValidateInput (
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PCIE_CONFIG   *pPcieConfig;
+  NB_INFO       NbInfo;
+  CORE          CoreId;
+  PORT          PortId;
+
+  NbInfo = LibNbGetRevisionInfo (pConfig);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  if (NbInfo.Type == NB_UNKNOWN || pPcieConfig == NULL) {
+    return  AGESA_FATAL;
+  }
+  Status = AGESA_SUCCESS;
+  //Validate GFX configuration
+  if (PcieLibValidateGfxConfig (3, pConfig) != AGESA_SUCCESS) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_CORE_CONFIGURATION, GPP1_CORE , 0, 0, 0, pConfig);
+    Status = AGESA_WARNING;
+  }
+  if (PcieLibValidateGfxConfig (12, pConfig) != AGESA_SUCCESS) {
+    REPORT_EVENT (AGESA_WARNING, PCIE_ERROR_CORE_CONFIGURATION, GPP2_CORE , 0, 0, 0, pConfig);
+    Status = AGESA_WARNING;
+  }
+  //Enable SB port on NB - SB chain and disable otherwise
+  pPcieConfig->PortConfiguration[8].PortPresent = (pConfig->NbPciAddress.AddressValue == 0)?ON:OFF;
+
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    if (pPcieConfig->PcieConfiguration.DisableHideUnusedPorts == ON) {
+      //pPcieConfig->CoreSetting[CoreId].PowerOffUnusedLanes = OFF;
+      pPcieConfig->CoreSetting[CoreId].TxClockOff = OFF;
+      pPcieConfig->CoreSetting[CoreId].LclkClockOff = OFF;
+      pPcieConfig->CoreSetting[CoreId].PowerOffPll = OFF;
+    }
+    if (pPcieConfig->CoreSetting[CoreId].ChannelType != 0) {
+      //Set Trasmitter drive strength based on cahnnel type
+      if (pPcieConfig->CoreSetting[CoreId].ChannelType == PcieLongChannel) {
+        pPcieConfig->CoreSetting[CoreId].TxDriveStrength = (NbInfo.Revision == NB_REV_A11)? PcieTxDriveStrangth24mA : PcieTxDriveStrangth26mA;
+      } else {
+        pPcieConfig->CoreSetting[CoreId].TxDriveStrength = PcieTxDriveStrangth22mA;
+      }
+      // Enable half swing mode
+      if (pPcieConfig->CoreSetting[CoreId].ChannelType == PcieShortChannel) {
+        pPcieConfig->CoreSetting[CoreId].TxHalfSwingMode = ON;
+      } else {
+        pPcieConfig->CoreSetting[CoreId].TxHalfSwingMode = OFF;
+      }
+    }
+  }
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    CoreId = PcieLibGetCoreId (PortId, pConfig);
+    if (pPcieConfig->ExtPortConfiguration[PortId].PortPowerLimit == 0) {
+      pPcieConfig->ExtPortConfiguration[PortId].PortPowerLimit = 75;  //Set 75W by default
+    }
+    if (pPcieConfig->CoreSetting[CoreId].ChannelType != 0) {
+      if (pPcieConfig->CoreSetting[CoreId].ChannelType == PcieLongChannel) {
+        pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis = PcieTxDeemphasis6dB;
+      } else {
+        pPcieConfig->ExtPortConfiguration[PortId].PortDeemphasis = PcieTxDeemphasis3p5dB;
+      }
+    }
+  }
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Enable PCIE Extended configuration MMIO.
+ *
+ *
+ *
+ * @param[in] PcieMmioBase  MMIO Base Address in 1MB unit.
+ * @param[in] PcieMmioSize  MMIO Size in 1MB unit
+ * @param[in] pConfig       Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieLibSetPcieMmioBase (
+  IN      UINT16          PcieMmioBase,
+  IN      UINT16          PcieMmioSize,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8 BAR3BusRange;
+
+  BAR3BusRange = LibAmdBitScanReverse ((UINT32)PcieMmioSize);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG00, AccessWidth32, (UINT32)~BIT3, 0x0, pConfig);
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG7F, AccessWidth8, (UINT32)~BIT6, BIT6, pConfig);
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | (NB_PCI_REG84 + 2), AccessWidth8, (UINT32)~(0x7), (BAR3BusRange > 8)?0:BAR3BusRange, pConfig);
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG1C, AccessWidth32, 0, (UINT32) (PcieMmioBase << 20), pConfig);
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG7F, AccessWidth8, (UINT32)~BIT6, 0, pConfig);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG32, AccessWidth32, 0xffffffff, BIT28, pConfig);
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG00, AccessWidth32, 0xffffffff, BIT3, pConfig);
+  LibNbPciRMW (pConfig->NbPciAddress.AddressValue | NB_PCI_REG04, AccessWidth8, (UINT32)~BIT1, BIT1, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Assert/Deassert Strap valid enables programming for misc strap features.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] Operation Assert or deassert strap valid.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieLibStrapModeControl (
+  IN       CORE            CoreId,
+  IN       PCIE_STRAP_MODE Operation,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  CORE_INFO *pCoreInfo;
+
+  pCoreInfo = PcieLibGetCoreInfo (CoreId, pConfig);
+  LibNbPciIndexRMW (
+    pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    pCoreInfo->StrapRegister,
+    AccessS3SaveWidth32,
+    ~(1 << pCoreInfo->StrapAddress),
+    (Operation == PcieCoreStrapConfigStart)?(1 << pCoreInfo->StrapAddress):0,
+    pConfig
+    );
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Pcie Port Info.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+PORT_INFO*
+PcieLibGetPortInfo (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  CORE          CoreId;
+  UINT32        CoreConfig;
+  PORT_INFO     *pPortInfo;
+  PORT          NativePortId;
+  GPP_CFG_INFO  *pGppCfgInfoTable;
+
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  CoreConfig  = PcieLibGetCoreConfiguration (CoreId, pConfig);
+  switch (PcieLibGetCoreAddress (CoreId, pConfig)) {
+  case  GPP1_CORE:
+  case  GPP2_CORE:
+    pPortInfo = &pGfxPortFullA;
+    if (CoreConfig == GFX_CONFIG_AABB) {
+      if (PortId == 3 || PortId == 12) {
+        pPortInfo = &pGfxPortB;
+      } else {
+        pPortInfo = &pGfxPortA;
+      }
+    }
+    break;
+  case  SB_CORE:
+  case  GPP3b_CORE:
+    pPortInfo = &pGpp420000[0];
+    break;
+  case  GPP3a_CORE:
+    pGppCfgInfoTable = (GPP_CFG_INFO*)FIX_PTR_ADDR (&GppCfgInfoTable[CoreConfig - 1], NULL);
+    NativePortId = PcieLibNativePortId (PortId, pConfig);
+    if (NativePortId == 0xf) {
+      return NULL;
+    }
+    pPortInfo = &pGppCfgInfoTable->PortInfoPtr[NativePortId - 4];
+    break;
+  default:
+    return NULL;
+  }
+  return (PORT_INFO*)FIX_PTR_ADDR (pPortInfo, NULL);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Pointer to static port info
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+PORT_STATIC_INFO*
+PcieLibGetStaticPortInfo (
+  IN       PORT              PortId,
+  IN OUT   AMD_NB_CONFIG     *pConfig
+  )
+{
+  PORT_STATIC_INFO  *pPortStaticInfo;
+
+  pPortStaticInfo = (PORT_STATIC_INFO*)FIX_PTR_ADDR (&PortInfoTable[PortId - MIN_PORT_ID], NULL);
+  return pPortStaticInfo ;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Native Port Id.
+ *  Native Port Id can be different from Port ID only on GPPSB core ports.
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+PORT
+PcieLibNativePortId (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  CORE          CoreId;
+  GPP_CFG_INFO  *pGppCfgInfoTable;
+
+  CoreId = PcieLibGetCoreId (PortId, pConfig);
+  if (PcieLibGetCoreAddress (CoreId, pConfig) == GPP3a_CORE) {
+    UINT32 CoreConfig;
+    CoreConfig = PcieLibGetCoreConfiguration (CoreId, pConfig);
+    pGppCfgInfoTable = (GPP_CFG_INFO*)FIX_PTR_ADDR (&GppCfgInfoTable[CoreConfig - 1], NULL);
+    return (pGppCfgInfoTable->PortIdMap >> ((PortId - 4) * 4)) & 0xF;
+  } else {
+    return PortId;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get pointer to Core info structure.
+ *
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+CORE_INFO*
+PcieLibGetCoreInfo (
+  IN      CORE             CoreId,
+  IN      AMD_NB_CONFIG    *pConfig
+  )
+{
+  return (CORE_INFO*)FIX_PTR_ADDR (&CoreInfoTable[CoreId], NULL);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Reset Device in slot.
+ *    Check if slot has controlled by GPI reset. If support toggle reset for 10us.
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+AGESA_STATUS
+PcieLibResetSlot (
+  IN      PORT             PortId,
+  IN      AMD_NB_CONFIG    *pConfig
+  )
+{
+ AGESA_STATUS Status;
+
+  Status = LibNbCallBack (PHCB_AmdPortResetSupported, (UINTN) (1 << PortId), pConfig);
+  if (Status == AGESA_SUCCESS) {
+    LibNbCallBack (PHCB_AmdPortResetAssert, (UINTN) (1 << PortId), pConfig);
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 10, 0);
+    LibNbCallBack (PHCB_AmdPortResetDeassert, (UINTN) (1 << PortId), pConfig);
+  }
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Secondary level interface to check if Gen2 disabled.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+BOOLEAN
+PcieLibCheckGen2Disabled (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  SCRATCH_1 Scratch;
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+  if ((Scratch.PortGen2Disable & (1 << (PortId - 2))) != 0) {
+    return FALSE;
+  } else {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Force Gen2 Disable\n"));
+    return TRUE;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Request Gen 2 disabled on next boot.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+VOID
+PcieLibSetGen2Disabled (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *pConfig
+  )
+{
+  SCRATCH_1 Scratch;
+
+  LibNbPciIndexRead (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+  Scratch.PortGen2Disable &= (~(1 << (PortId - 2)));
+  LibNbPciIndexWrite (pConfig->NbPciAddress.AddressValue | NB_HTIU_INDEX, NB_HTIU_REG15, AccessS3SaveWidth32, (UINT32*)&Scratch, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Force link to compliance mode
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieLibSetLinkCompliance (
+  IN       PORT              PortId,
+  IN       AMD_NB_CONFIG     *pConfig
+  )
+{
+  PCI_ADDR    Port;
+  PCIE_CONFIG *pPcieConfig;
+
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  if (pPcieConfig->PortConfiguration[PortId].PortLinkMode == PcieLinkModeGen1) {
+    LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGC0, AccessWidth32, (UINT32)~BIT13, BIT13, pConfig);
+  } else {
+    LibNbPciRMW (Port.AddressValue | NB_PCIP_REG88, AccessWidth8, (UINT32)~BIT4, BIT4, pConfig);
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCIe device type
+ *
+ *
+ *
+ * @param[in] Device    PCI address of device.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ * @retval    PCIe device type (see PCIE_DEVICE_TYPE)
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+PCIE_DEVICE_TYPE
+PcieGetDeviceType (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT8       PcieCapPtr;
+  UINT8       Value;
+
+  PcieCapPtr = LibNbFindPciCapability (Device.AddressValue, PCIE_CAP_ID, pConfig);
+  if (PcieCapPtr != 0) {
+    LibNbPciRead (Device.AddressValue | (PcieCapPtr + 0x2) , AccessWidth8, &Value, pConfig);
+    return Value >> 4;
+  }
+  return PcieNotPcieDevice;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get bitmap of cores that have active or potentially active ports
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ * @retval    Bitmap of cores
+ */
+ /*----------------------------------------------------------------------------------------*/
+
+UINT8
+PcieLibGetActiveCoreMap (
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PORT        PortId;
+  CORE        CoreId;
+  UINT8       ActiveCoreMap;
+  PCIE_CONFIG *pPcieConfig;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  ActiveCoreMap = 0;
+  //Check through Ports
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON && PcieLibIsValidPortId (PortId, pConfig)) {
+      if (pPcieConfig->PortConfiguration[PortId].PortCompliance == ON ||
+        pPcieConfig->PortConfiguration[PortId].PortDetected == ON ||
+        pPcieConfig->PortConfiguration[PortId].PortHotplug != OFF) {
+        CoreId = PcieLibGetCoreId (PortId, pConfig);
+        ActiveCoreMap |= (1 << CoreId);
+      }
+    }
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Active Core Map  = %x\n", ActiveCoreMap));
+  return ActiveCoreMap;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c
new file mode 100644
index 0000000..ec3ec80
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.c
@@ -0,0 +1,160 @@
+/**
+ * @file
+ *
+ * PCIe link width control.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Set Pcie Link Width
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] LinkWidth New Link Width
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+AGESA_STATUS
+PcieLibSetLinkWidth (
+  IN      PORT             PortId,
+  IN      PCIE_LINK_WIDTH  LinkWidth,
+  IN      AMD_NB_CONFIG    *pConfig
+  )
+{
+  AGESA_STATUS    Status;
+  PCIE_LINK_WIDTH NewLinkWidth;
+  PCIE_LINK_WIDTH CurrentLinkWidth;
+
+  Status = AGESA_SUCCESS;
+  NewLinkWidth = LinkWidth;
+  CurrentLinkWidth = PcieLibGetLinkWidth (PortId, pConfig);
+  if (NewLinkWidth == 0 || NewLinkWidth > CurrentLinkWidth) {
+    NewLinkWidth = CurrentLinkWidth;
+  }
+  if (NewLinkWidth == PcieLinkWidth_x12) {
+    NewLinkWidth = PcieLinkWidth_x8;
+  }
+  if (NewLinkWidth < CurrentLinkWidth) {
+    CORE      CoreId;
+    UINT32    Value;
+    UINT32    CoreAddress;
+    BOOLEAN   PoolPortStatus;
+    PCI_ADDR  Port;
+
+    CoreId = PcieLibGetCoreId (PortId, pConfig);
+    CoreAddress = PcieLibGetCoreAddress (CoreId, pConfig);
+    PoolPortStatus = TRUE;
+    Port = PcieLibGetPortPciAddress (PortId, pConfig);
+    LibNbPciIndexRMW (NB_SBDFO | NB_BIF_INDEX, NB_BIFNB_REG40 | CoreAddress, AccessWidth32, (UINT32)~BIT0, BIT0, pConfig);
+    LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, 0xfffffff8, (NewLinkWidth) | BIT8 | BIT7, pConfig);
+    while (PoolPortStatus) {
+      LibNbPciRead (Port.AddressValue | NB_PCIP_REG6A, AccessWidth16, &Value, pConfig);
+      if ((Value & BIT11) == 0) {
+        LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, pConfig);
+        if ((Value & BIT8) == 0) {
+          LibNbPciRead (Port.AddressValue | NB_PCIP_REG12A, AccessWidth16, &Value, pConfig);
+          if ((Value & BIT1) == 0) {
+            PoolPortStatus = FALSE;
+          }
+        }
+      }
+    }
+    LibNbPciIndexRMW (NB_SBDFO | NB_BIF_INDEX, NB_BIFNB_REG40 | CoreAddress, AccessWidth32, (UINT32)~BIT0, 0 , pConfig);
+    LibNbPciIndexRMW (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, (UINT32)~BIT7, 0, pConfig);
+  }
+  return  Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Return link with
+ *
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+PCIE_LINK_WIDTH
+PcieLibGetLinkWidth (
+  IN      PORT               PortId,
+  IN      AMD_NB_CONFIG      *pConfig
+  )
+{
+  PCIE_LINK_WIDTH LinkWidth;
+  UINT32          Value;
+  PCI_ADDR        Port;
+
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+//  Read current link State
+  LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA5, AccessWidth32, &Value, pConfig);
+  if ((Value & 0x3f) == 0x10) {
+  //Read current link width
+    LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, pConfig);
+    LinkWidth = (Value >> 4) & 0xf;
+  } else {
+  //Link not in L0
+    LinkWidth = PcieLinkWidth_x0;
+  }
+  return  LinkWidth;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.h b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.h
new file mode 100644
index 0000000..8eab541
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieLinkWidth.h
@@ -0,0 +1,60 @@
+/**
+ * @file
+ *
+ * PCIe link width control.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIELINKWIDTH_H_
+#define _NBPCIELINKWIDTH_H_
+
+AGESA_STATUS
+PcieLibSetLinkWidth (
+  IN       PORT             PortId,
+  IN       PCIE_LINK_WIDTH  LinkWidth,
+  IN       AMD_NB_CONFIG    *pConfig
+  );
+
+PCIE_LINK_WIDTH
+PcieLibGetLinkWidth (
+  IN       PORT             PortId,
+  IN       AMD_NB_CONFIG    *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
new file mode 100644
index 0000000..ec2206b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.c
@@ -0,0 +1,193 @@
+/**
+ * @file
+ *
+ *  PCIe Port device number remapping.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+SCAN_STATUS
+PciePllOffCheckFunction (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Function
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if EP allowed exit latency allowed PLL in L1 to be disabled on non hotplug ports.
+ *
+ *
+ * @param[in] CoreId    CoreId
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+BOOLEAN
+PciePllOffComatibilityTest (
+  IN      CORE              CoreId,
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  PLLOFF_WORKSPACE  PllOffWorkspace;
+  PORT              PortId;
+  BOOLEAN           Result;
+  PCIE_CONFIG       *pPcieConfig;
+  BOOLEAN           IsHotplugPorst;
+  BOOLEAN           IsNonHotplugPorts;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePllOffInL1ComatibilityTest Enter Core [%d]\n", CoreId));
+  LibAmdMemFill (&PllOffWorkspace, 0, sizeof (PllOffWorkspace), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+  PllOffWorkspace.ScanPciePort.pConfig = pConfig;
+  PllOffWorkspace.ScanPciePort.ScanBus = LibNbScanPciBus;
+  PllOffWorkspace.ScanPciePort.ScanDevice = LibNbScanPciDevice;
+  PllOffWorkspace.ScanPciePort.ScanFunction = PciePllOffCheckFunction;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig) && PcieLibGetCoreId (PortId, pConfig) == CoreId) {
+      if (pPcieConfig->PortConfiguration[PortId].PortHotplug == ON) {
+        IsHotplugPorst = TRUE;
+        continue;     // Skip hotplug ports . Will make decision later.
+      }
+      if (pPcieConfig->PortConfiguration[PortId].PortDetected == ON) {
+        PCI_ADDR  Port;
+        IsNonHotplugPorts = TRUE;
+        Port = PcieLibGetPortPciAddress (PortId, pConfig);
+        PllOffWorkspace.ScanPciePort.ScanFunction (&PllOffWorkspace.ScanPciePort, Port);
+      }
+    }
+  }
+  if (PllOffWorkspace.MaxL1Latency != 0 && PllOffWorkspace.MaxL1Latency < 34) {
+    Result = FALSE;
+  } else {
+    Result = TRUE;
+  }
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePllOffInL1ComatibilityTest Exit [%d]\n", Result));
+  return  Result;
+}
+
+/**----------------------------------------------------------------------------------------*/
+/**
+ * Scan PCIe topology
+ *
+ *
+ *
+ * @param[in] This          Pointer to instance of scan protocol
+ * @param[in] Function      PCI address of found device/function.
+ *
+ * @retval    SCAN_FINISHED Scan for device finished.
+ */
+ /*----------------------------------------------------------------------------------------*/
+SCAN_STATUS
+PciePllOffCheckFunction (
+  IN      PCI_SCAN_PROTOCOL   *This,
+  IN      PCI_ADDR            Function
+  )
+{
+  PLLOFF_WORKSPACE  *WorkspacePtr;
+  PCIE_DEVICE_TYPE  DeviceType;
+  UINT8             SecondaryBus;
+  PCI_ADDR  Port;
+
+  WorkspacePtr = (PLLOFF_WORKSPACE*) This;
+  DeviceType = PcieGetDeviceType (Function, This->pConfig);
+  if (DeviceType == PcieDeviceRootComplex || DeviceType == PcieDeviceDownstreamPort) {
+    WorkspacePtr->LinkCount++;
+    //Lets enable Common clock
+    LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
+    if (SecondaryBus == 0) {
+      return  SCAN_FINISHED;
+    }
+    Port.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    This->ScanBus (This, Port);
+    WorkspacePtr->LinkCount--;
+  } else if (DeviceType == PcieDeviceUpstreamPort ) {
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Reached upstream port\n"));
+    LibNbPciRead (Function.AddressValue | 0x19, AccessWidth8, &SecondaryBus, This->pConfig);
+    if (SecondaryBus == 0) {
+      return  SCAN_FINISHED;
+    }
+    Port.AddressValue = MAKE_SBDFO (0, SecondaryBus, 0, 0, 0);
+    This->ScanBus (This, Port);
+  } else if (DeviceType <= PcieDeviceLegacyEndPoint) {
+    // We reach end of the link
+    UINT8       PcieCapPtr;
+    UINT32      Value;
+    UINT8       L1AcceptableLatency;
+    PcieCapPtr = LibNbFindPciCapability (Function.AddressValue, PCIE_CAP_ID, This->pConfig);
+    if (PcieCapPtr != 0) {
+      LibNbPciRead (Function.AddressValue | (PcieCapPtr + 0x0D) , AccessWidth8, &Value, This->pConfig);
+      if (((Value >> 2) & ASPM_L1) != 0) {
+        LibNbPciRead ((Function.AddressValue | (PcieCapPtr + 4)), AccessWidth32, &Value, This->pConfig);
+        L1AcceptableLatency = ((UINT8) (1 << ((Value >> 9) & 0x7)) & 0x7F);
+        if (WorkspacePtr->LinkCount > 1) {
+          L1AcceptableLatency = L1AcceptableLatency + WorkspacePtr->LinkCount;
+        }
+        if (WorkspacePtr->MaxL1Latency <  L1AcceptableLatency) {
+          WorkspacePtr->MaxL1Latency = L1AcceptableLatency;
+        }
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (This->pConfig), CIMX_NBPCIE_TRACE), "    Reached end of link at 0x%x with Acceptable Exit Latency %dus \n", Function.AddressValue, L1AcceptableLatency));
+      }
+    }
+  }
+  return  SCAN_FINISHED;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePllControl.h b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.h
new file mode 100644
index 0000000..44193a5
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePllControl.h
@@ -0,0 +1,63 @@
+/**
+ * @file
+ *
+ * PLL off in L1 support.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _NBPLLCONTROL_H_
+#define _NBPLLCONTROL_H_
+
+BOOLEAN
+PciePllOffComatibilityTest (
+  IN      CORE              CoreId,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+
+#pragma pack (push, 1)
+/// Framework for testing for ability to diable PLL in L1
+typedef struct  {
+  PCI_SCAN_PROTOCOL ScanPciePort;   ///< PCI scan protocol
+  PCI_ADDR          DownstreamPort; ///< Downstream port to enable ASPM
+  UINT8             MaxL1Latency;   ///< TBD
+  UINT8             LinkCount;      ///< TBD
+} PLLOFF_WORKSPACE;
+
+#pragma pack (pop)
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
new file mode 100644
index 0000000..639f149
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.c
@@ -0,0 +1,182 @@
+/**
+ * @file
+ *
+ *  PCIe Port device number remapping.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+PORT
+STATIC
+PciePortRemapAllocateDeviceId (
+  IN      UINT8           *UnusedPortMap
+);
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Remap PCIe ports device number.
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+AGESA_STATUS
+PciePortRemapInit (
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  PORT          FinalDeviceIdList[MAX_PORT_ID + 1];
+  UINT8         UsedDeviceIdMap[MAX_PORT_ID + 1];
+  BOOLEAN       IsDeviceRemapEnabled;
+  PORT          PortId;
+  PCIE_CONFIG   *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Enter \n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  Status = AGESA_SUCCESS;
+  IsDeviceRemapEnabled = FALSE;
+  // Remap Device
+  LibAmdMemFill (&UsedDeviceIdMap, 0, sizeof (UsedDeviceIdMap), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+  LibAmdMemFill (&FinalDeviceIdList, 0, sizeof (FinalDeviceIdList), (AMD_CONFIG_PARAMS *)&(pConfig->sHeader));
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (PcieLibIsValidPortId (PortId, pConfig)) {
+      PORT  NativePortId = PcieLibNativePortId (PortId, pConfig);
+      if (pPcieConfig->PortConfiguration[PortId].PortPresent) {
+        //FinalDeviceIdList[PortId] = PortId;
+        if (pPcieConfig->ExtPortConfiguration[PortId].PortMapping != 0) {
+          if (pPcieConfig->ExtPortConfiguration[PortId].PortMapping < MIN_PORT_ID ||
+              pPcieConfig->ExtPortConfiguration[PortId].PortMapping > MAX_PORT_ID ||
+              pPcieConfig->ExtPortConfiguration[PortId].PortMapping == 8) {
+            return AGESA_ERROR;
+          }
+          FinalDeviceIdList[NativePortId] = pPcieConfig->ExtPortConfiguration[PortId].PortMapping;
+          IsDeviceRemapEnabled = TRUE;
+        } else {
+          FinalDeviceIdList[NativePortId] = PortId;
+        }
+        CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Requested Port Mapping %d -> %d\n", PortId, FinalDeviceIdList[PortId]));
+        if (UsedDeviceIdMap[FinalDeviceIdList[NativePortId]] == 0 ) {
+          UsedDeviceIdMap[FinalDeviceIdList[NativePortId]] = 1;
+        } else {
+          return AGESA_ERROR;
+        }
+      }
+    }
+  }
+  if (!IsDeviceRemapEnabled) {
+    return Status;
+  }
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    PORT_STATIC_INFO *pStaticPortInfo;
+    pStaticPortInfo = PcieLibGetStaticPortInfo (PortId, pConfig);
+    if (pStaticPortInfo->MappingAddress == 0xFF) {
+      continue;
+    }
+    if (FinalDeviceIdList[PortId] == 0) {
+      FinalDeviceIdList[PortId] = PciePortRemapAllocateDeviceId (&UsedDeviceIdMap[0]);
+    }
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "   Port Mapping %d -> %d\n", PortId, FinalDeviceIdList[PortId]));
+    LibNbPciIndexRMW (
+      NB_SBDFO | NB_MISC_INDEX,
+      (PortId > 9)?NB_MISC_REG21:NB_MISC_REG20,
+      AccessWidth32,
+      0xffffffff,
+      FinalDeviceIdList [PortId] << pStaticPortInfo->MappingAddress,
+      pConfig
+      );
+
+  }
+  LibNbPciIndexRMW (NB_SBDFO | NB_MISC_INDEX, NB_MISC_REG20, AccessWidth32, 0xffffffff, 0x3, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PciePortDeviceNumberRemap Exit [0x%x] \n", Status));
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Allocate Device number from unused port array.
+ *
+ *
+ *
+ * @param[in] UnusedPortMap   Unused port array.
+ */
+
+PORT
+STATIC
+PciePortRemapAllocateDeviceId (
+  IN      UINT8           *UnusedPortMap
+  )
+{
+  PORT  PortId;
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (UnusedPortMap[PortId] == 0) {
+      UnusedPortMap[PortId] = 1;
+      break;
+    }
+  }
+  return PortId;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.h b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.h
new file mode 100644
index 0000000..32236f0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPciePortRemap.h
@@ -0,0 +1,52 @@
+/**
+ * @file
+ *
+*  PCIe Port device number remapping.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIEPORTREMAP_H_
+#define _NBPCIEPORTREMAP_H_
+
+AGESA_STATUS
+PciePortRemapInit (
+  IN    AMD_NB_CONFIG   *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c b/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c
new file mode 100644
index 0000000..918fbd4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieRecovery.c
@@ -0,0 +1,753 @@
+/**
+ * @file
+ *
+ * PCIe in recovery support
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+PcieRecoveryCoreInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+VOID
+PcieRecoveryPortTraining (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  );
+
+VOID
+PcieRecoveryCommonPortInit (
+  IN       PORT            PortId,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+VOID
+PcieRecoveryCommonCoreInit (
+  IN       CORE            CoreId,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+UINT32
+PcieRecoveryGetCoreAddress (
+  IN       CORE             CoreId,
+  IN       AMD_NB_CONFIG    *NbConfigPtr
+  );
+
+PCI_ADDR
+PcieRecoveryGetPortPciAddress (
+  IN       PORT             PortId,
+  IN       AMD_NB_CONFIG    *NbConfigPtr
+  );
+
+VOID
+PcieRecoveryPcieCheckPorts (
+  IN       PORT            PortId,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+VOID
+PcieRecoveryReleaseTraining (
+  IN       PORT            PortId,
+  IN       AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+PORT
+PcieRecoveryNativePortId (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIE Recovery Init. Basic programming / EP training.
+ *    After this call EP are fully operational.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+AGESA_STATUS
+AmdPcieEarlyInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+#ifdef PCIE_RECOVERY_SUPPORT
+  PcieRecoveryCoreInit (ConfigPtr);
+  PcieRecoveryPortTraining (ConfigPtr);
+#endif
+  return AGESA_SUCCESS;
+}
+
+
+#ifdef  PCIE_RECOVERY_SUPPORT
+
+INDIRECT_REG_ENTRY
+STATIC
+PcieRecoveryMiscInitTable[] = {
+  {
+    NB_MISC_REG0C,
+    (UINT32)~0x001f00FC,
+    0x00000000
+  },
+  {
+    NB_MISC_REG20,
+    (UINT32)~BIT1,
+    0x0
+  }, //enable static device remapping by default
+  {
+    NB_MISC_REG22,
+    0xffffffff,
+    BIT27
+  }, //[10]CMGOOD_OVERRIDE for all 5 pcie cores.
+  {
+    NB_MISC_REG6B,
+    0xffffffff,
+    (UINT32) (0x1f << 27)
+  }, //[13][12]Turn Off Offset Cancellation
+  {
+    NB_MISC_REG37,
+    (UINT32)~(BIT11 + BIT12 + BIT13),
+    0x0
+  }, //[14][13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG67,
+    (UINT32)~(BIT26 + BIT10 + BIT11),
+    BIT11
+  }, //[13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG2C,
+    (UINT32)~(BIT10),
+    0x0
+  }, //[13]Disables Rx Clock gating in CDR
+  {
+    NB_MISC_REG2A,
+    (UINT32)~(BIT17 + BIT16),
+    BIT17
+  }, //[16]Sets Electrical l Idle Threshold
+  {
+    NB_MISC_REG32,
+    (UINT32)~(0x3F << 20),
+    (UINT32) (0x2A << 20)
+  }, //[17][16]Sets Electrical Idle Threshold
+  {
+    NB_MISC_REG28,
+    0xffffff00,
+    0x0
+  },
+  {
+    NB_MISC_REG27,
+    0x3fffffff,
+    0x0
+  },
+  {
+    NB_MISC_REG2D,
+    (UINT32)~(BIT5),
+    0x0
+  }
+};
+
+//                                             2  3  4  5  6  7  8  9  A  B  C  D
+UINT8 PortToCoreMappingTable[] = { 0xff, 0xff, 0, 0, 3, 3, 3, 3, 4, 3, 3, 1, 1, 3 };
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Minimum core initialization
+ *
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+VOID
+PcieRecoveryCoreInit (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  CORE          CoreId;
+  PORT          PortId;
+  AMD_NB_CONFIG *NbConfigPtr;
+  PCIE_CONFIG   *pPcieConfig;
+
+  NbConfigPtr = &ConfigPtr->Northbridges[0];
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+//Init Misc registers
+  LibNbIndirectTableInit (
+    NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieRecoveryMiscInitTable[0],NULL),
+    (sizeof (PcieRecoveryMiscInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    NbConfigPtr
+    );
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON) {
+      pPcieConfig->CoreSetting[PortToCoreMappingTable[PortId]].CoreDisabled = OFF;
+    }
+  }
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    if (pPcieConfig->CoreSetting[CoreId].CoreDisabled == OFF) {
+      //Init core registers and configuration
+      PcieRecoveryCommonCoreInit (CoreId, NbConfigPtr);
+    }
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Port link training initialization
+ *
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+VOID
+PcieRecoveryPortTraining (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  PORT          PortId;
+  UINT32        PortToHideMap;
+  AMD_NB_CONFIG *NbConfigPtr;
+  PCIE_CONFIG   *pPcieConfig;
+
+  PortToHideMap = 0;
+  NbConfigPtr = &ConfigPtr->Northbridges[0];
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON) {
+      PcieRecoveryCommonPortInit (PortId, NbConfigPtr);
+      if (LibNbCallBack (PHCB_AmdPortResetDeassert, 1 << PortId, NbConfigPtr) == AGESA_SUCCESS) {
+        STALL (GET_BLOCK_CONFIG_PTR (NbConfigPtr), pPcieConfig->ResetToTrainingDelay, 0);
+      }
+      if (PortId != 8) {
+        PcieRecoveryReleaseTraining (PortId, NbConfigPtr);
+      }
+    }
+  }
+  STALL (GET_BLOCK_CONFIG_PTR (pConfig), pPcieConfig->ReceiverDetectionPooling, 0);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    PCI_ADDR Port;
+    Port = PcieRecoveryGetPortPciAddress (PortId, NbConfigPtr);
+    if (pPcieConfig->PortConfiguration[PortId].PortPresent == ON && PortId != 8) {
+      PcieRecoveryPcieCheckPorts (PortId, NbConfigPtr);
+
+      pPcieConfig->PortConfiguration[PortId].PortLinkMode = PcieLinkModeGen1;
+
+      LibNbPciIndexWrite (
+        Port.AddressValue | NB_BIF_INDEX,
+        NB_BIFNBP_REG01,
+        AccessWidth32,
+        (UINT32*)&pPcieConfig->PortConfiguration[PortId],
+        NbConfigPtr
+        );
+    }
+    if (pPcieConfig->PortConfiguration[PortId].PortDetected == OFF) {
+      PortToHideMap |= (1 << PortId);
+    }
+  }
+  LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG0C, AccessWidth32, 0xffffffff, (PortToHideMap & 0xFC) | ((PortToHideMap & 0x3E00) << 7), NbConfigPtr);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check link training Status
+ *
+ *
+ *
+ *
+ * @param[in] Config   Northbridges configuration structure pointer.
+ *
+ */
+VOID
+PcieRecoveryPcieCheckPorts (
+  IN      PORT            PortId,
+  IN      AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  PCI_ADDR    Port;
+  UINT32      LinkState;
+  UINT32      LinkStatePooling;
+  UINT32      Value;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  Port = PcieRecoveryGetPortPciAddress (PortId, NbConfigPtr);
+  LinkStatePooling = pPcieConfig->ReceiverDetectionPooling;
+  do {
+    LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA5, AccessWidth32, &LinkState, NbConfigPtr);
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieRecoveryCoreInit PortId = %d LinkState 0x%x\n", PortId,  LinkState));
+    LinkState &= 0x3F;
+    if (LinkState == 0x10) {
+      UINT16  VcoStatus;
+      BOOLEAN VcoNotCompleted;
+      UINT32  VcoPooling;
+      VcoNotCompleted = TRUE;
+      VcoPooling = 6000;
+      do {
+        LibNbPciRead (Port.AddressValue | NB_PCIP_REG12A, AccessWidth16, &VcoStatus, NbConfigPtr);
+        if (VcoStatus & BIT1) {
+          LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, NbConfigPtr);
+          Value = (Value & 0xfffffe80) | ((Value & 0x70) >> 4) | BIT8;
+          LibNbPciIndexWrite (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA2, AccessWidth32, &Value, NbConfigPtr);
+          STALL (GET_BLOCK_CONFIG_PTR (NbConfigPtr), 5000, 0);
+        } else {
+          VcoNotCompleted = FALSE;
+        }
+      } while (VcoNotCompleted || --VcoPooling != 0);
+      if (!VcoNotCompleted) {
+        pPcieConfig->PortConfiguration[PortId].PortDetected = ON;
+      }
+    } else {
+      STALL (GET_BLOCK_CONFIG_PTR (NbConfigPtr), 1000, 0);
+    }
+  } while (LinkState != 0x10 && --LinkStatePooling != 0);
+}
+
+
+UINT8 PortTrainingOffset[] = {
+  4,  5, 21, 22, 23, 24, 20, 25, 26, 6, 7 , 4
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check link training Status
+ *
+ *
+ *
+ *
+ * @param[in] Config   Northbridges configuration structure pointer.
+ *
+ */
+VOID
+PcieRecoveryReleaseTraining (
+  IN        PORT            PortId,
+  IN        AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PORT NativePortId;
+
+  NativePortId  = PcieRecoveryNativePortId (PortId, NbConfigPtr);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieRecoveryReleaseTraining PortId = %d NativeId %d BitOfset %d\n",
+    PortId, NativePortId, ((UINT8*)FIX_PTR_ADDR (&PortTrainingOffset[0], NULL))[NativePortId - MIN_PORT_ID]));
+  LibNbPciIndexRMW (
+    NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    (PortId == 13)? NB_MISC_REG2A:NB_MISC_REG08,
+    AccessWidth32,
+    ~(1 << ((UINT8*)FIX_PTR_ADDR (&PortTrainingOffset[0], NULL))[NativePortId - MIN_PORT_ID]),
+    0,
+    NbConfigPtr
+    );
+}
+
+INDIRECT_REG_ENTRY  PcieRecoveryPortInitTable[] = {
+  {
+    NB_BIFNBP_REG02,
+    (UINT32)~(BIT15),
+    BIT15
+  },
+  {
+    NB_BIFNBP_REGA1,
+    (UINT32)~(BIT24),
+    BIT11
+  },
+  {
+    NB_BIFNBP_REGB1,
+    0xffffffff,
+    BIT28 + BIT23 + BIT19 + BIT20
+  },
+  {
+    NB_BIFNBP_REGA4,
+    (UINT32)~(BIT0),
+    0x0
+  },
+  {
+    NB_BIFNBP_REGA2,
+    (UINT32)~(BIT13),
+    BIT13
+  },
+  {
+    NB_BIFNBP_REGA3,
+    (UINT32)~(BIT9),
+    BIT9
+  },
+  {
+    NB_BIFNBP_REGA0,
+    0xffff00ff,
+    0x6130
+  },
+  {
+    NB_BIFNBP_REG70,
+    (UINT32)~(BIT16 + BIT17 + BIT18),
+    BIT16 + BIT18
+  },
+  // Set Link for Gen1
+  {
+    NB_BIFNBP_REGC0,
+    (UINT32)~(BIT15),
+    BIT15
+  },
+  {
+    NB_BIFNBP_REGA2,
+    (UINT32)~(BIT13),
+    BIT13
+  },
+  {
+    NB_BIFNBP_REGA4,
+    (UINT32)~(BIT0 + BIT29),
+    0x0
+  }
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Port basic register init
+ *
+ *
+ *
+ *
+ * @param[in] Config   Northbridges configuration structure pointer.
+ *
+ */
+
+VOID
+PcieRecoveryCommonPortInit (
+  IN        PORT            PortId,
+  IN        AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCI_ADDR Port;
+
+  Port = PcieRecoveryGetPortPciAddress (PortId, NbConfigPtr);
+  LibNbIndirectTableInit (
+    Port.AddressValue | NB_BIF_INDEX,
+    0x0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieRecoveryPortInitTable[0],NULL),
+    (sizeof (PcieRecoveryPortInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    NbConfigPtr
+    );
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG80, AccessWidth8, 0xF0, 0x6, NbConfigPtr);
+  LibNbPciRMW (Port.AddressValue | NB_PCIP_REG88, AccessWidth8, 0xF0, 0x0, NbConfigPtr);
+}
+
+
+UINT8 GppConfigTable[] = {
+  0x0, 0x1, 0x2, 0xC, 0xA, 0x4, 0xB
+};
+
+INDIRECT_REG_ENTRY  PcieRecoveryCoreInitTable[] = {
+  {
+    NB_BIFNB_REG10,
+    (UINT32)~(BIT10 + BIT11 + BIT12),
+    BIT12
+  },
+  {
+    NB_BIFNB_REG20,
+    (UINT32)~(BIT8 + BIT9),
+    BIT9
+  },
+  {
+    NB_BIFNB_REG02,
+    (UINT32)~(BIT0),
+    BIT0
+  },
+  {
+    NB_BIFNB_REG40,
+    (UINT32)~(BIT14 + BIT15),
+    BIT15
+  },
+  {
+    NB_BIFNB_REGC1,
+    (UINT32)~(BIT0),
+    (BIT0 + BIT1 + BIT2)
+  },
+  {
+    NB_BIFNB_REG1C,
+    0x0,
+    (4 << 6) + (4 << 1) + 1
+  }
+};
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Core basic register init
+ *
+ *
+ *
+ *
+ * @param[in] Config   Northbridges configuration structure pointer.
+ *
+ */
+
+VOID
+PcieRecoveryCommonCoreInit (
+  IN        CORE            CoreId,
+  IN        AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32      CoreAddress;
+  PCIE_CONFIG *pPcieConfig;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieRecoveryCommonCoreInit CoreID = %d Enter\n", CoreId));
+  CoreAddress = PcieRecoveryGetCoreAddress (CoreId, NbConfigPtr);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  //Setup GPP1 core configuration
+  if (CoreAddress == GPP1_CORE && (pPcieConfig->CoreConfiguration[0] == GFX_CONFIG_AABB || NbConfigPtr->pPcieConfig->PortConfiguration[3].PortPresent == ON)) {
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08 , AccessWidth32, 0xffffffff, BIT15, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT28, BIT28, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, 0xffffffff, BIT8, NbConfigPtr);
+    STALL (GET_BLOCK_CONFIG_PTR (NbConfigPtr), 2000, 0);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT28, 0x0, NbConfigPtr);
+  }
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08 , AccessWidth32, (UINT32)~BIT15, 0x0, NbConfigPtr);
+  //Setup GPP2 core configuration
+  if (CoreAddress == GPP2_CORE && (pPcieConfig->CoreConfiguration[1] == GFX_CONFIG_AABB || NbConfigPtr->pPcieConfig->PortConfiguration[12].PortPresent == ON)) {
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08 , AccessWidth32, 0xffffffff, BIT13, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT28, BIT29, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, 0xffffffff, BIT9, NbConfigPtr);
+    STALL (GET_BLOCK_CONFIG_PTR (NbConfigPtr), 2000, 0);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT29, 0x0, NbConfigPtr);
+  }
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08 , AccessWidth32, (UINT32)~BIT13, 0x0, NbConfigPtr);
+  //Setup GPP core configuration
+  if (CoreAddress == GPP3a_CORE) {
+    UINT32  Mux;
+    UINT8 *pGppConfigTable;
+    Mux = 0;
+    pGppConfigTable = (UINT8*)FIX_PTR_ADDR (&GppConfigTable[0], NULL);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, 0xffffffff, BIT31, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT30, BIT30, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG67, AccessWidth32,  0xfffffff0, (UINT32)pGppConfigTable[pPcieConfig->CoreConfiguration[CoreId]], NbConfigPtr);
+    switch (pPcieConfig->CoreConfiguration[CoreId]) {
+    case  GPP_CONFIG_GPP420000:
+      Mux = (pPcieConfig->PortConfiguration[6].PortReversed == ON)?0xF05BA00:0x055B000;
+      break;
+    case  GPP_CONFIG_GPP411000:
+      Mux = 0x215B400;
+      break;
+    case  GPP_CONFIG_GPP222000:
+    case  GPP_CONFIG_GPP211110:
+      Mux = (pPcieConfig->PortConfiguration[4].PortReversed == ON)?0xFFF0AAA:0xFF0BAA0;
+      break;
+    case  GPP_CONFIG_GPP221100:
+      Mux = 0x215B400;
+      break;
+    case  GPP_CONFIG_GPP111111:
+      Mux = 0x2AA3554;
+      break;
+    }
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, 0xf0000000, Mux, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG26, AccessWidth32, (UINT32)~BIT30, 0x0, NbConfigPtr);
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG08, AccessWidth32, (UINT32)~BIT31, 0x0, NbConfigPtr);
+  }
+  if (CoreAddress == GPP3b_CORE) {
+    LibNbPciIndexRMW (NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG2A, AccessWidth32, (UINT32)~BIT15, 0, NbConfigPtr);
+  }
+  LibNbIndirectTableInit (
+    NbConfigPtr->NbPciAddress.AddressValue | NB_BIF_INDEX,
+    CoreAddress,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&PcieRecoveryCoreInitTable[0],NULL),
+    (sizeof (PcieRecoveryCoreInitTable) / sizeof (INDIRECT_REG_ENTRY)),
+    NbConfigPtr
+    );
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieRecoveryCommonCoreInit Exitr\n"));
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Core register selector.
+ * Function return selector to access BIFNB register space for selected core
+ *
+ *
+ * @param[in] CoreId    PCI Express Core ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+UINT32
+PcieRecoveryGetCoreAddress (
+  IN       CORE             CoreId,
+  IN       AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  UINT32  CoreAddress;
+  CoreAddress = GPP1_CORE;
+  switch (CoreId) {
+  case 0x0:
+    CoreAddress = GPP1_CORE;
+    break;
+  case 0x1:
+    CoreAddress = GPP2_CORE;
+    break;
+  case 0x2:
+    CoreAddress = GPP3a_CORE;
+    break;
+  case 0x3:
+    CoreAddress = GPP3b_CORE;
+    break;
+  case 0x4:
+    CoreAddress = SB_CORE;
+    break;
+  default:
+    CIMX_ASSERT (FALSE);
+  }
+  return  CoreAddress;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get PCI address of Port.
+ * Function return pcie Address based on port mapping and core configuration.
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+PCI_ADDR
+PcieRecoveryGetPortPciAddress (
+  IN      PORT             PortId,
+  IN      AMD_NB_CONFIG    *NbConfigPtr
+  )
+{
+  PCI_ADDR Port;
+  Port = NbConfigPtr->NbPciAddress;
+  Port.Address.Device = PortId;
+  return  Port;
+}
+
+UINT32 GppNativeIdTable[] = {
+  0xff50fff4,
+  0xf650fff4,
+  0xff60f5f4,
+  0xf760f5f4,
+  0xf87065f4,
+  0xf9807654
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Native Port Id.
+ *  Native Port Id can be different from Port ID only on GPPSB core ports.
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+
+PORT
+PcieRecoveryNativePortId (
+  IN       PORT            PortId,
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  UINT32 GppNativeIdMap;
+  if (PortId > 3 && PortId < 11) {
+    GppNativeIdMap = ((UINT32*)FIX_PTR_ADDR (&GppNativeIdTable[0], NULL))[NbConfigPtr->pPcieConfig->CoreConfiguration[0x2] - 1];
+    return (GppNativeIdMap >> ((PortId - 4)*4)) & 0xF;
+  } else {
+    return PortId;
+  }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize default PCIE_CONFIG setting
+ *
+ *
+ *
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+PcieRecoveryInitializer (
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  CORE        CoreId;
+  pPcieConfig = GET_PCIE_CONFIG_PTR (NbConfigPtr);
+  if (pPcieConfig == NULL) {
+    return  AGESA_FATAL;
+  }
+  LibAmdMemFill (pPcieConfig, 0, sizeof (PCIE_CONFIG), (AMD_CONFIG_PARAMS *)NbConfigPtr);
+  pPcieConfig->ReceiverDetectionPooling = 120;
+  pPcieConfig->ResetToTrainingDelay = 4;
+  for (CoreId = 0; CoreId <= MAX_CORE_ID; CoreId++) {
+    pPcieConfig->CoreSetting[CoreId].CoreDisabled = ON;
+  }
+  return  AGESA_SUCCESS;
+}
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieSb.c b/src/vendorcode/amd/cimx/rd890/nbPcieSb.c
new file mode 100644
index 0000000..3ef6094
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieSb.c
@@ -0,0 +1,195 @@
+/**
+ * @file
+ *
+ * PCIe support for misc Southbridges.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Set up NB-SB virtual channel for audio traffic
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Set up NB-SB virtual channel for audio traffic
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+PcieSbSetupVc (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT16        AlinkPort;
+
+  Status = PcieSbAgetAlinkIoAddress (&AlinkPort, pConfig);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+
+  LibNbIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0,  0x80000124, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffff01, 0, pConfig);
+  LibNbIoRMW (AlinkPort, AccessS3SaveWidth32 , 0x0, 0x80000130, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, (UINT32)~(BIT24 + BIT25 + BIT26), 0xFE + BIT24, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffffff, BIT31, pConfig);
+  return AGESA_SUCCESS;
+}
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Set up NB-SB virtual channel for audio traffic
+ *
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+VOID
+PcieSbEnableVc (
+  IN     AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT16        AlinkPort;
+  Status = PcieSbAgetAlinkIoAddress (&AlinkPort, pConfig);
+  if (Status != AGESA_SUCCESS) {
+    return;
+  }
+  LibNbIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0xC0000050, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffffff, BIT3, pConfig);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init SB ASPM.
+ * Enable ASPM states on SB
+ *
+ *
+ * @param[in] Lx       Lx ASPM bitmap. Lx[0] - L0s enable. Lx[1] - L1 enable.
+ * @param[in] pConfig  Northbridge configuration structure pointer.
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieSbInitAspm (
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT16        AlinkPort;
+
+  Status = PcieSbAgetAlinkIoAddress (&AlinkPort, pConfig);
+  if (Status != AGESA_SUCCESS) {
+    return Status;
+  }
+  LibNbIoRMW (AlinkPort, AccessS3SaveWidth32, 0x0, 0x40000038, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0x0, 0xA0, pConfig);
+  LibNbIoRMW (AlinkPort  , AccessS3SaveWidth32, 0x0, 0x4000003c, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffff00ff, 0x6900, pConfig );
+  LibNbIoRMW (AlinkPort  , AccessS3SaveWidth32, 0x0, 0x80000068, pConfig);
+  LibNbIoRMW (AlinkPort + 4, AccessS3SaveWidth32, 0xffffffff, Lx, pConfig);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Get Alink config address
+ *
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+AGESA_STATUS
+PcieSbAgetAlinkIoAddress (
+     OUT   UINT16         *AlinkPort,
+  IN       AMD_NB_CONFIG  *pConfig
+  )
+{
+  SB_INFO SbInfo;
+  SbInfo = LibAmdSbGetRevisionInfo ((pConfig == NULL)?NULL:GET_BLOCK_CONFIG_PTR (pConfig));
+  if (SbInfo.Type == SB_UNKNOWN) {
+    return AGESA_UNSUPPORTED;
+  }
+  if (SbInfo.Type == SB_SB700) {
+    LibNbPciRead (MAKE_SBDFO (0, 0, 0x14, 0, 0xf0), AccessWidth16, AlinkPort, pConfig);
+  } else {
+    LibAmdSbPmioRead (0xE0, AccessWidth16, AlinkPort, NULL);
+  }
+  if (*AlinkPort == 0) {
+    return AGESA_UNSUPPORTED;
+  }
+  return  AGESA_SUCCESS;
+}
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieSb.h b/src/vendorcode/amd/cimx/rd890/nbPcieSb.h
new file mode 100644
index 0000000..2b0914c
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieSb.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ *
+ * PCIe support for misc Southbridges.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIESB_H_
+#define _NBPCIESB_H_
+
+
+AGESA_STATUS
+PcieSbInitAspm (
+  IN      UINT8           Lx,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+AGESA_STATUS
+PcieSbSetupVc (
+  IN     AMD_NB_CONFIG   *pConfig
+ );
+
+VOID
+PcieSbEnableVc (
+  IN     AMD_NB_CONFIG   *pConfig
+ );
+
+
+AGESA_STATUS
+PcieSbAgetAlinkIoAddress (
+     OUT   UINT16                  *AlinkPort,
+  IN       AMD_NB_CONFIG           *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c
new file mode 100644
index 0000000..771c489
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.c
@@ -0,0 +1,436 @@
+/**
+ * @file
+ *
+ * Routines to support misc PCIe workarounds.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdSbLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR          Port,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR          Port,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+ AGESA_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR          Device,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+AGESA_STATUS
+PcieNvWorkaround (
+  IN      PCI_ADDR          Device,
+  IN      AMD_NB_CONFIG     *pConfig
+  );
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16            DeviceId
+  );
+
+ /*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc GFX Card Workaround
+ *  RV3780/RV380 desk workaround. NV43 lost SSID workaround.
+ *
+ *
+ *
+ * @param[in] PortId    PCI Express Port ID
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+AGESA_STATUS
+PcieGfxWorkarounds (
+  IN      PORT            PortId,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  AGESA_STATUS  Status;
+  UINT32        Count;
+  UINT16        DeviceId;
+  UINT16        VendorId;
+  UINT8         DevClassCode;
+  PCI_ADDR      Port;
+  PCI_ADDR      Ep;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieGfxWorkarounds PortId %d Enter\n", PortId));
+  Status = AGESA_SUCCESS;
+  Port = PcieLibGetPortPciAddress (PortId, pConfig);
+  Ep.AddressValue = MAKE_SBDFO (0, Port.Address.Bus + 5, 0, 0, 0);
+  if (PcieConfigureBridgeResources (Port, pConfig) != AGESA_SUCCESS) {
+    return AGESA_SUCCESS;
+  }
+  for (Count = 0; Count <= 5000; Count++) {
+    LibNbPciRead (Ep.AddressValue | 0x02, AccessWidth16, &DeviceId, pConfig);
+    CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "    Endpoint Device ID %x\n", DeviceId));
+    if (DeviceId != 0xffff) {
+      break;
+    };
+    STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, 0);
+  }
+  if (Count >= 5000) {
+    PcieLibRequestPciReset (pConfig);
+    return  AGESA_WARNING;
+  }
+  LibNbPciRead (Ep.AddressValue | 0x02, AccessWidth16, &DeviceId, pConfig);
+  LibNbPciRead (Ep.AddressValue, AccessWidth16, &VendorId, pConfig);
+  if (VendorId == 0xffff) {
+    PcieLibRequestPciReset (pConfig);
+    return  AGESA_WARNING;
+  }
+  LibNbPciRead (Ep.AddressValue | 0x0B , AccessWidth8, &DevClassCode, pConfig);
+  if (DevClassCode == 3) {
+    if (VendorId == 0x1002 && PcieIsDeskewCardDetected (DeviceId)) {
+      Status = PcieDeskewWorkaround (Ep, pConfig);
+    } else {
+      if (VendorId == 0x10DE) {
+        Status = PcieNvWorkaround (Ep, pConfig);
+      }
+    }
+  }
+  PcieFreeBridgeResources (Port, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieGfxWorkarounds Exit [Status = 0x%x]\n", Status));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RV370/RV380 Deskew workaround
+ *
+ *
+ *
+ * @param[in] Device    Pcie Address of ATI RV370/RV380 card.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+AGESA_STATUS
+PcieDeskewWorkaround (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  UINTN       MmioBase;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieDeskewWorkaround Enter\n"));
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  MmioBase = pPcieConfig->TempMmioBaseAddress << 20;
+  if (MmioBase == 0) {
+    return AGESA_SUCCESS;
+  }
+  LibNbPciWrite (Device.AddressValue | 0x18, AccessWidth32, &MmioBase, pConfig);
+  LibNbPciRMW (Device.AddressValue | 0x04, AccessWidth8 , (UINT32)~BIT1, BIT1, pConfig);
+  *(UINT16*)(MmioBase + 0x120) = 0xb700;
+  if (*(UINT16*) (MmioBase + 0x120) == 0xb700) {
+    *(UINT32*)(MmioBase + 0x124) = 0x13;
+    if (*(UINT32*) (MmioBase + 0x124) == 0x13) {
+      if (*(UINT32*) (MmioBase + 0x12C) & BIT8) {
+//    TRACE((DMSG_PCIE_MISC,"Deskew ERROR Generate Reset\n"));
+        PcieLibRequestPciReset (pConfig);
+        return AGESA_WARNING;
+      }
+    }
+  }
+  LibNbPciRMW (Device.AddressValue | 0x04, AccessWidth8, (UINT32)~BIT1, 0x0, pConfig);
+  LibNbPciRMW (Device.AddressValue | 0x18, AccessWidth32, 0x0, 0x0, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieDeskewWorkaround Exit\n"));
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  NV43 card workaround (lost SSID)
+ *
+ *
+ *
+ * @param[in] Device    Pcie Address of NV43 card.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+AGESA_STATUS
+PcieNvWorkaround (
+  IN      PCI_ADDR        Device,
+  IN      AMD_NB_CONFIG   *pConfig
+  )
+{
+  UINT32      DeviceSSID;
+  PCIE_CONFIG *pPcieConfig;
+  UINTN       MmioBase;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieNvWorkaround Enter\n"));
+  LibNbPciIndexRMW (pConfig->NbPciAddress.AddressValue | NB_MISC_INDEX, NB_MISC_REG0B, AccessS3SaveWidth32, 0xffffffff, BIT2 + BIT1, pConfig);
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  MmioBase = pPcieConfig->TempMmioBaseAddress << 20;
+  if (MmioBase == 0) {
+    return AGESA_SUCCESS;
+  }
+  LibNbPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, ((UINT32)MmioBase) | 1, pConfig);
+  LibNbPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x2, pConfig);
+  LibNbPciRead (Device.AddressValue | 0x2c, AccessWidth32, &DeviceSSID, pConfig);
+  if (DeviceSSID != *(UINT32*) (MmioBase + 0x54)) {
+    LibNbPciRMW (Device.AddressValue | 0x40, AccessWidth32, 0x0, *(UINT32*) (MmioBase + 0x54), pConfig);
+  }
+  LibNbPciRMW (Device.AddressValue | 0x30, AccessWidth32, 0x0, 0x0, pConfig);
+  LibNbPciRMW (Device.AddressValue | 0x4, AccessWidth8, 0x0, 0x0, pConfig);
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (pConfig), CIMX_NBPCIE_TRACE), "[NBPCIE]PcieNvWorkaround Exit\n"));
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Allocate temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port      Pci Address of Port to initialize.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+AGESA_STATUS
+PcieConfigureBridgeResources (
+  IN      PCI_ADDR          Port,
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  PCIE_CONFIG *pPcieConfig;
+  UINT32      Value;
+  UINT32      MmioBase;
+
+  pPcieConfig = GET_PCIE_CONFIG_PTR (pConfig);
+  MmioBase = pPcieConfig->TempMmioBaseAddress << 20;
+  if (MmioBase == 0) {
+    return AGESA_WARNING;
+  }
+  Value = Port.Address.Bus + ((Port.Address.Bus + 5) << 8) + ((Port.Address.Bus + 5) << 16);
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG18, AccessWidth32, &Value, pConfig);
+  Value = MmioBase + (MmioBase >> 16);
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG20, AccessWidth32, &Value, pConfig);
+  Value = 0x000fff0;
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG24, AccessWidth32, &Value, pConfig);
+  Value = 0x2;
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG04, AccessWidth8, &Value, pConfig);
+  return AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ *  Free temporary resources for Pcie P2P bridge
+ *
+ *
+ *
+ * @param[in] Port      Pci Address of Port to clear resource allocation.
+ * @param[in] pConfig   Northbridge configuration structure pointer.
+ */
+VOID
+PcieFreeBridgeResources (
+  IN      PCI_ADDR          Port,
+  IN      AMD_NB_CONFIG     *pConfig
+  )
+{
+  UINT32 Value;
+
+  Value = 0;
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG04, AccessWidth8, &Value, pConfig);
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG18, AccessWidth32, &Value, pConfig);
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG20, AccessWidth32, &Value, pConfig);
+  LibNbPciWrite (Port.AddressValue | NB_PCIP_REG24, AccessWidth32, &Value, pConfig);
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/*
+ * Check if card required test for deskew workaround
+ *
+ *
+ *
+ *
+ *
+ */
+
+BOOLEAN
+PcieIsDeskewCardDetected (
+  IN      UINT16    DeviceId
+  )
+{
+  if ((DeviceId >= 0x3150 && DeviceId <= 0x3152) || (DeviceId == 0x3154) ||
+     (DeviceId == 0x3E50) || (DeviceId == 0x3E54) ||
+     ((DeviceId & 0xfff8) == 0x5460) || ((DeviceId & 0xfff8)  == 0x5B60)) {
+    return TRUE;
+  }
+  return FALSE;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Check if we can accsee to EP. Wait for up to 1 sec if EP requred extra time to initialize.
+ *
+ *
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+PcieEpReadyWorkaround (
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  PORT  PortId;
+  UINT8 TempBus;
+  PCI_ADDR  Device;
+  TempBus = (UINT8) (pConfig->NbPciAddress.Address.Bus + 5);
+  Device.AddressValue = MAKE_SBDFO (0, TempBus, 0, 0, 0);
+  for (PortId = MIN_PORT_ID; PortId <= MAX_PORT_ID; PortId++) {
+    PCI_ADDR  Port;
+    Port.AddressValue = MAKE_SBDFO (0, pConfig->NbPciAddress.Address.Bus , PortId, 0, 0);
+    if (LibNbIsDevicePresent (Port, pConfig)) {
+      UINT32  LinkState;
+      LibNbPciIndexRead (Port.AddressValue | NB_BIF_INDEX, NB_BIFNBP_REGA5, AccessWidth32, &LinkState, pConfig);
+      LinkState &= 0x3F;
+      if (LinkState == 0x10) {
+        BOOLEAN   IsDevicePresent;
+        UINT32    PortBusConfiguration;
+        UINT32    Count;
+        Count = 1000;
+        LibNbPciRead (Port.AddressValue | 0x18, AccessWidth32, &PortBusConfiguration, pConfig);
+        LibNbPciRMW (Port.AddressValue | 0x18, AccessWidth32, 0x0, (TempBus << 8) | (TempBus << 16), pConfig);
+        do {
+          IsDevicePresent = LibNbIsDevicePresent (Device, pConfig);
+          STALL (GET_BLOCK_CONFIG_PTR (pConfig), 1000, CIMX_S3_SAVE);
+        } while (IsDevicePresent == FALSE && Count-- != 0 );
+        LibNbPciWrite (Port.AddressValue | 0x18, AccessWidth32, &PortBusConfiguration, pConfig);
+      }
+    }
+  }
+}
+
+UINT16  AspmBrDeviceTable[] = {
+ 0x1002, 0x9441, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10B5, 0xFFFF, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0402, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0193, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0422, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0292, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x00F9, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0141, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0092, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D0, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D1, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D2, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D3, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D5, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D7, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01D8, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01DC, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01DE, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x01DF, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x016A, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x10DE, 0x0392, (UINT16)~(ASPM_L1 | ASPM_L0s),
+ 0x168C, 0xFFFF, (UINT16)~(ASPM_L0s)
+};
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Misc PCIe ASPM workarounds
+ *
+ *  @param[in] AspmLinkInfoPtr  Pointer to link ASPM info.
+ *  @param[in] pConfig          Northbridge configuration structure pointer.
+ *
+ */
+/*----------------------------------------------------------------------------------------*/
+VOID
+PcieAspmWorkarounds (
+  IN OUT   ASPM_LINK_INFO     *AspmLinkInfoPtr,
+  IN       AMD_NB_CONFIG      *pConfig
+  )
+{
+  UINT32  UpstreamDeviceId;
+  UINT32  DownstreamDeviceId;
+  UINTN   i;
+  LibNbPciRead (AspmLinkInfoPtr->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, pConfig);
+  LibNbPciRead (AspmLinkInfoPtr->UpstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, pConfig);
+  for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
+    UINT32 DeviceId;
+    UINT32 VendorId;
+    VendorId = AspmBrDeviceTable[i];
+    DeviceId = AspmBrDeviceTable[i + 1];
+    if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
+      if (DeviceId == 0xFFFF || DeviceId == (UpstreamDeviceId >> 16) || DeviceId == (DownstreamDeviceId >> 16)) {
+        AspmLinkInfoPtr->UpstreamLx &= AspmBrDeviceTable[i + 2];
+        AspmLinkInfoPtr->DownstreamLx &= AspmBrDeviceTable[i + 2];
+      }
+    }
+  }
+  if ((UINT16)UpstreamDeviceId == 0x168c) {
+    // Atheros (Ignore dev capability enable L1 if requested)
+    AspmLinkInfoPtr->UpstreamLx = AspmLinkInfoPtr->RequestedLx & ASPM_L1;
+    AspmLinkInfoPtr->DownstreamLx = AspmLinkInfoPtr->UpstreamLx;
+    LibNbPciRMW (AspmLinkInfoPtr->UpstreamPort.AddressValue | 0x70C, AccessS3SaveWidth32, 0x0, 0x0F003F01, pConfig);
+  }
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.h b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.h
new file mode 100644
index 0000000..4d72386
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPcieWorkarounds.h
@@ -0,0 +1,65 @@
+/**
+ * @file
+ *
+ * PCIe support for misc Southbridges.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBPCIEWORKAROUNDS_H_
+#define _NBPCIEWORKAROUNDS_H_
+
+
+AGESA_STATUS
+PcieGfxWorkarounds (
+  IN      PORT            PortId,
+  IN      AMD_NB_CONFIG   *pConfig
+  );
+
+VOID
+PcieEpReadyWorkaround (
+  IN       AMD_NB_CONFIG      *pConfig
+  );
+
+VOID
+PcieAspmWorkarounds (
+  IN OUT  ASPM_LINK_INFO      *AspmLinkInfoPtr,
+  IN      AMD_NB_CONFIG       *pConfig
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c b/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c
new file mode 100644
index 0000000..cde7d06
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbPowerOnReset.c
@@ -0,0 +1,383 @@
+/**
+ * @file
+ *
+ * Power on Reset register initialization.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+#include "amdDebugOutLib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+NbPorInitValidateInput (
+  IN      AMD_NB_CONFIG *pConfig
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/// PCI registers init table
+CONST REGISTER_ENTRY NbPorPciTable[] = {
+  {NB_PCI_REG04, 0xFD, 0x02},
+//Reg84h[4]=1 (EV6MODE) to allow decode of 640k-1MB
+  {NB_PCI_REG84, 0xEF, 0x10},
+//Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+//Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
+  {NB_PCI_REG4C, 0x00, 0x42},
+//Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
+//Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge
+  {NB_PCI_REG4E, 0xFF, 0x05},
+//Set temporary NB TOM to 0xE0000000
+  {NB_PCI_REG90 + 3, 0x00, 0xE0}
+};
+
+/// MISCIND registers init table
+CONST INDIRECT_REG_ENTRY NbPorMiscTable[] = {
+// NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
+// Block non-snoop DMA request if PMArbDis is set.
+// Set BMSetDis
+  {
+    NB_MISC_REG0B,
+    0xFFFF0000,
+    0x00000180
+  },
+// NBCFG (NBMISCIND 0x0): NB_CNTL -
+//   HIDE_NB_AGP_CAP  ([0], default=1)HIDE
+//   HIDE_P2P_AGP_CAP ([1], default=1)HIDE
+//   HIDE_NB_GART_BAR ([2], default=1)HIDE
+//   HIDE_MMCFG_BAR   ([3], default=1)HIDE
+//   AGPMODE30        ([4], default=0)DISABLE
+//   AGP30ENCHANCED   ([5], default=0)DISABLE
+//   HIDE_AGP_CAP     ([8], default=1)ENABLE
+  {
+    NB_MISC_REG00,
+    0xFFFF0000,
+    0x0000010e
+  },
+//NBMISIND:0x01 Bit[8]=1 IOC will forward the byte-enable (BE), which is 16'b0 for zero-byte reads, of the PCIE DMA request upstream to HTIU.
+//NBMISIND:0x01 Bit[9]=1 zero-byte reads.
+  {
+    NB_MISC_REG01,
+    0xFFFFFFFF,
+    0x00000310
+  },
+//NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow PWM features to work.
+  {
+    NB_MISC_REG40,
+    0xffffffff,
+    0x00000500
+  },
+//Enable slot power message
+  {
+    NB_MISC_REG51,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG53,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG55,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG57,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG59,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG5B,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG5D,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG5F,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG61,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG63,
+    0x00000000,
+    0x00100106
+  },
+  {
+    NB_MISC_REG1F,
+    0x00000000,
+    0x00100106
+  },
+//NBMISCIND:0x0C[13]= 1 Enables GSM Mode.
+  {
+    NB_MISC_REG0C,
+    0xffffffff,
+    BIT13 + BIT20
+  },
+//NBMISCIND:0x12[16]= 1 ReqID for GPP1 and GPP2
+//NBMISCIND:0x12[17]= 1 ReqID for  GPP3a, GPP3b, SB
+//NBMISCIND:0x12[18]= 0 ReqID override for SB
+//NBMISCIND:0x12[19]= 1 Enable INT accumulators
+//NBMISCIND:0x12[20, 21, 23]= 1 4103, 4125, 4155 4186 (A21).
+//NBMISCIND:0x12[22]=0  Prevent spurious DR of UMA request (RPR 5.9.3)
+  {
+    NB_MISC_REG12,
+    (UINT32)~(BIT18 + BIT22),
+    0xBB0000
+  },
+//NBMISCIND:0x75[15.13,16..18,21..19,24..22,25..25] = 0x4  Enable AER
+//NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message.
+  {
+    NB_MISC_REG75,
+    (UINT32)~BIT28,
+    (4 << 13) | (4 << 16) | (4 << 19) | (4 << 22) | (4 << 25) | BIT29
+  },
+//PCIe CDR setting
+  {
+    NB_MISC_REG38,
+    0xffffffff,
+    BIT6 + BIT7 + BIT14 + BIT15 + BIT22 + BIT23
+  },
+  {
+    NB_MISC_REG67,
+    0xffffffff,
+    BIT21 + BIT22
+  },
+  {
+    NB_MISC_REG2C,
+    (UINT32)~(BIT0 + BIT1 + BIT19),
+    BIT0 + BIT1
+  },
+  {
+    NB_MISC_REG6C,
+    (UINT32)~(BIT10),
+    0x0
+  },
+  {
+    NB_MISC_REG34,
+    (UINT32)~(BIT7 + BIT15 + BIT23),
+    0x0
+  },
+  {
+    NB_MISC_REG37,
+    (UINT32)~(0xffful << 20),
+    (0xdddul << 20)
+  },
+  {
+    NB_MISC_REG68,
+    (UINT32)~(0xful << 16),
+    (0xd << 16)
+    },
+  {
+    NB_MISC_REG2B,
+    (UINT32)~(0xful << 24 ),
+    (0xd << 24)
+  },
+  // Enable ACS capability
+  {
+    NB_MISC_REG6A,
+    0xffffffff,
+    BIT2
+  }
+};
+
+/// HTIUIND registers init table
+CONST INDIRECT_REG_ENTRY NbPorHtiuTable[] = {
+//HTIU x 05 [8] = 0x0 Enables PC checking for FCB release.
+//HTIU x 05 [13,13,3,14,10,12,17,18,15,4,6,19] = 0x1 Misc (A21)
+  {NB_HTIU_REG05, 0xFFFFFEFF,  BIT8 + BIT16 + BIT13 + BIT3 + BIT14 + BIT10 + BIT12 + BIT17 + BIT18 + BIT15 +
+                               BIT4 + BIT6 + BIT19 },
+  //HTIU x 06 [0] = 0x0 Enables writes to pass in-progress reads
+//HTIU x 06 [1] = 0x1 Enables streaming of CPU writes
+//HTIU x 06 [9] = 0x1 Enables extended write buffer for CPU writes
+//HTIU x 06 [13] = 0x1 Enables additional response buffers
+//HTIU x 06 [17] = 0x1 Enables special reads to pass writes
+//HTIU x 06 [16:15] = 0x3 Enables decoding of C1e/C3 and FID cycles
+//HTIU x 06 [25] = 0x1 Enables HTIU-display handshake bypass.
+//HTIU x 06 [30] = 0x1 Enables tagging fix
+  {NB_HTIU_REG06, 0xFFFFFFFE,  0x04203A202},
+//HTIU x 07 [0] = 0x1 Enables byte-write optimization for IOC requests
+//HTIU x 07 [1] = 0x0 Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
+//HTIU x 07 [2] = 0x0 Disables upstream system-management delay
+  {NB_HTIU_REG07, 0xFFFFFFF9,  0x0001     },
+//HTIU x 1C [31:17]=0xfff i.e. 0001 1111 1111 111 or 1FFE Enables all traffic to be detected as GSM traffic.
+  {NB_HTIU_REG1C, 0xFFFFFFFF,  0x1ffe0000 },
+//HTIU x 15 [27]=0x1 Powers down the chipset DLLs in the LS2 state.
+  {NB_HTIU_REG15, 0xFFFFFFFF,  BIT27      },
+//Enable transmit PHY to reinitialize in HT1 mode when tristate is enabled
+//HTIU x 16 [10]=0x1 enable proper DLL reset sequence.
+  {NB_HTIU_REG16, 0xFFFFFFFF,  BIT11 + BIT10},
+//HTIU x 2A [1:0]=0x1 Optimize chipset HT transmitter drive strength
+  {NB_HTIU_REG2A, 0xfffffffc, 0x00000001  }
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Amd Power on Reset Initialization for all NB.
+ *
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+
+AGESA_STATUS
+AmdPowerOnResetInit (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+
+  Status = LibNbApiCall (NbPowerOnResetInit, ConfigPtr);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * NB Power on Reset Initialization.
+ *    Basic registers initialization.
+ *
+ *
+ *
+ * @param[in] NbConfigPtr   Northbridge configuration structure pointer.
+ *
+ */
+
+
+AGESA_STATUS
+NbPowerOnResetInit (
+  IN      AMD_NB_CONFIG *NbConfigPtr
+  )
+{
+  AGESA_STATUS    Status;
+  REGISTER_ENTRY  *pTable;
+  UINTN           i;
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPOR_TRACE), "[NBPOR]NbPowerOnResetInit Enter\n"));
+  Status = NbPorInitValidateInput (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    REPORT_EVENT (AGESA_FATAL, GENERAL_ERROR_BAD_CONFIGURATION, 0, 0, 0, 0, NbConfigPtr);
+    CIMX_ASSERT (FALSE);
+    return  Status;
+  }
+  //Init Pci Registers
+  pTable = (REGISTER_ENTRY*)FIX_PTR_ADDR (&NbPorPciTable[0], NULL);
+  for (i = 0; i < (sizeof (NbPorPciTable) / sizeof (REGISTER_ENTRY)); i++) {
+    LibNbPciRMW (NbConfigPtr->NbPciAddress.AddressValue | pTable->Register, AccessWidth8, pTable->Mask, pTable->Data, NbConfigPtr);
+    ++pTable;
+  }
+  //Init Misc registers
+  LibNbIndirectTableInit (
+    NbConfigPtr->NbPciAddress.AddressValue | NB_MISC_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&NbPorMiscTable[0], NULL),
+    (sizeof (NbPorMiscTable) / sizeof (INDIRECT_REG_ENTRY)),
+    NbConfigPtr
+    );
+
+   //Init Htiu registers
+  LibNbIndirectTableInit (
+    NbConfigPtr->NbPciAddress.AddressValue | NB_HTIU_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&NbPorHtiuTable[0],NULL),
+    (sizeof (NbPorHtiuTable) / sizeof (INDIRECT_REG_ENTRY)),
+    NbConfigPtr
+    );
+
+  CIMX_TRACE ((TRACE_DATA (GET_BLOCK_CONFIG_PTR (NbConfigPtr), CIMX_NBPOR_TRACE), "[NBPOR]NbPowerOnResetInit Exit\n"));
+  return Status;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Validate input parameters
+ *
+ *
+ *
+ *
+ *  @param[in] pConfig  Northbridge configuration structure pointer.
+ */
+
+
+AGESA_STATUS
+NbPorInitValidateInput (
+  IN      AMD_NB_CONFIG *pConfig
+  )
+{
+  return (LibNbGetRevisionInfo (pConfig).Type == NB_UNKNOWN)?AGESA_FATAL:AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecovery.c b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
new file mode 100644
index 0000000..71c6959
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbRecovery.c
@@ -0,0 +1,192 @@
+/**
+ * @file
+ *
+ * Recovery support
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+/// PCI registers init table
+CONST REGISTER_ENTRY NbRecoveryPorPciTable[] = {
+  {NB_PCI_REG04,0xFD,0x02},
+//Reg84h[4]=1 (EV6MODE) to allow decode of 640k-1MB
+  {NB_PCI_REG84,0xEF,0x10},
+//Reg4Ch[1]=1 (APIC_ENABLE) force cpu request with address 0xFECx_xxxx to south-bridge
+//Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
+  {NB_PCI_REG4C,0x00,0x42},
+//Reg4Ch[16]=1 (WakeC2En) enable Wake_from_C2 message generation.
+//Reg4Ch[18]=1 (P4IntEnable) Enable north-bridge to accept MSI with address 0xFEEx_xxxx from south-bridge
+  {NB_PCI_REG4E,0xFF,0x05},
+//Set temporary NB TOM to 0xE0000000
+  {NB_PCI_REG90 + 3, 0x00, 0xE0}
+};
+
+/// MISCIND registers init table
+CONST INDIRECT_REG_ENTRY NbRecoveryPorMiscTable[] = {
+// NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
+// Block non-snoop DMA request if PMArbDis is set.
+// Set BMSetDis
+  {NB_MISC_REG0B, 0xFFFF0000, 0x00000180},
+// NBCFG (NBMISCIND 0x0): NB_CNTL -
+//   HIDE_NB_AGP_CAP  ([0], default=1)HIDE
+//   HIDE_P2P_AGP_CAP ([1], default=1)HIDE
+//   HIDE_NB_GART_BAR ([2], default=1)HIDE
+//   HIDE_MMCFG_BAR   ([3], default=1)HIDE
+//   AGPMODE30        ([4], default=0)DISABLE
+//   AGP30ENCHANCED   ([5], default=0)DISABLE
+//   HIDE_AGP_CAP     ([8], default=1)ENABLE
+  {NB_MISC_REG00, 0xFFFF0000, 0x0000010e},
+  {NB_MISC_REG01, 0xFFFFFFFF, 0x00000010},
+  {NB_MISC_REG0C, 0xFFFFFFFF, 0x001f00FC},
+//NBMISIND:0x40 Bit[8]=1 and Bit[10]=1 following bits are required to set in order to allow PWM features to work.
+  {NB_MISC_REG40, 0xffffffff, 0x00000500},
+};
+
+/// HTIUIND registers init table
+INDIRECT_REG_ENTRY NbRecoveryPorHtiuTable[] = {
+//HTIU x 06 [0] = 0x0  Enables writes to pass in-progress reads
+//HTIU x 06 [1] = 0x1  Enables streaming of CPU writes
+//HTIU x 06 [9] = 0x1  Enables extended write buffer for CPU writes
+//HTIU x 06 [13] = 0x1 Enables additional response buffers
+//HTIU x 06 [17] = 0x1 Enables special reads to pass writes
+//HTIU x 06 [16:15] = 0x3  Enables decoding of C1e/C3 and FID cycles
+//HTIU x 06 [25] = 0x1 Enables HTIU-display handshake bypass.
+//HTIU x 06 [30] = 0x1 Enables tagging fix
+  {NB_HTIU_REG06, 0xFFFFFFFE,  0x04203A202},
+//HTIU x 07 [0] = 0x1  Enables byte-write optimization for IOC requests
+//HTIU x 07 [1] = 0x0  Disables delaying STPCLK de-assert during FID sequence. Needed when enhanced UMA arbitration is used.
+//HTIU x 07 [2] = 0x0  Disables upstream system-management delay
+  {NB_HTIU_REG07, 0xFFFFFFF9,  0x0001     },
+//HTIU x 1C [31:17]=0xfff i.e. 0001 1111 1111 111 or 1FFE  Enables all traffic to be detected as GSM traffic.
+  {NB_HTIU_REG1C, 0xFFFFFFFF,  0x1ffe0000 },    //vsj-2007-09-04
+//Enable transmit PHY to reinitialize in HT1 mode when tristate is enabled
+  {NB_HTIU_REG16, 0xFFFFFFFF,  BIT11      },
+//HTIU x 2A [1:0]=0x1 Optimize chipset HT transmitter drive strength
+  {NB_HTIU_REG2A, 0xfffffffc, 0x00000001  }
+};
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Northbridge Power on Reset Initialization for all NB in system.
+ *
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+
+AGESA_STATUS
+AmdPowerOnResetInit (
+  IN      AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  REGISTER_ENTRY  *pTable;
+  AMD_NB_CONFIG   *pConfig;
+  UINTN           i;
+
+  pConfig = &ConfigPtr->Northbridges[0];
+  pTable = (REGISTER_ENTRY*)FIX_PTR_ADDR (&NbRecoveryPorPciTable[0], NULL);
+  for (i = 0; i < (sizeof (NbRecoveryPorPciTable) / sizeof (REGISTER_ENTRY)); i++) {
+    LibNbPciRMW (pConfig->NbPciAddress.AddressValue | pTable->Register, AccessWidth8, pTable->Mask, pTable->Data, pConfig);
+    ++pTable;
+  }
+  //Init Misc registers
+  LibNbIndirectTableInit (
+    ConfigPtr->Northbridges[0].NbPciAddress.AddressValue | NB_MISC_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&NbRecoveryPorMiscTable[0],NULL),
+    (sizeof (NbRecoveryPorMiscTable) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+
+   //Init Htiu registers
+  LibNbIndirectTableInit (
+    ConfigPtr->Northbridges[0].NbPciAddress.AddressValue  | NB_HTIU_INDEX,
+    0,
+    (INDIRECT_REG_ENTRY*)FIX_PTR_ADDR (&NbRecoveryPorHtiuTable[0], NULL),
+    (sizeof (NbRecoveryPorHtiuTable) / sizeof (INDIRECT_REG_ENTRY)),
+    pConfig
+    );
+
+  return AGESA_SUCCESS;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Initialize misc setting
+ *
+ *
+ *
+ * @param[in] NbConfigPtr   Northbridge configuration structure pointer.
+ *
+ */
+
+AGESA_STATUS
+MiscRecoveryInitializer (
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecovery.h b/src/vendorcode/amd/cimx/rd890/nbRecovery.h
new file mode 100644
index 0000000..e6b04c0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbRecovery.h
@@ -0,0 +1,53 @@
+/**
+ * @file
+ *
+ * NB definitions
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBRECOVERY_H_
+#define _NBRECOVERY_H_
+
+
+AGESA_STATUS
+MiscRecoveryInitializer (
+  IN OUT   AMD_NB_CONFIG   *NbConfigPtr
+  );
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c b/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c
new file mode 100644
index 0000000..f9b6132
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbRecoveryInitializer.c
@@ -0,0 +1,98 @@
+/**
+ * @file
+ *
+ * Recovery support
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "NbPlatform.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AMD structures initializer for recovery.
+ *
+ *
+ *
+ * @param[in] ConfigPtr   Northbridges configuration block pointer.
+ *
+ */
+
+AGESA_STATUS
+AmdInitializer (
+  IN OUT   AMD_NB_CONFIG_BLOCK *ConfigPtr
+  )
+{
+  AGESA_STATUS  Status;
+  AMD_NB_CONFIG *NbConfigPtr;
+  NbConfigPtr = &ConfigPtr->Northbridges[0];
+  Status = MiscRecoveryInitializer (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    return  Status;
+  }
+#ifdef PCIE_RECOVERY_SUPPORT
+  Status = PcieRecoveryInitializer (NbConfigPtr);
+  if (Status == AGESA_FATAL) {
+    return  Status;
+  }
+#endif
+  return Status;
+
+}
diff --git a/src/vendorcode/amd/cimx/rd890/nbRegisters.h b/src/vendorcode/amd/cimx/rd890/nbRegisters.h
new file mode 100644
index 0000000..621f1e9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbRegisters.h
@@ -0,0 +1,420 @@
+/**
+ * @file
+ *
+ *  Registers definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBREGISTERS_H_
+#define _NBREGISTERS_H_
+
+#define NB_PCI_REG04   0x04
+#define NB_PCI_REG1C   0x1C
+#define NB_PCI_REG44   0x44
+#define NB_PCI_REG4C   0x4C
+#define NB_PCI_REG4E   0x4E
+#define NB_PCI_REG50   0x50
+#define NB_PCI_REG54   0x54
+#define NB_PCI_REG58   0x58
+#define NB_PCI_REG5C   0x5c
+#define NB_PCI_REG60   0x60
+#define NB_PCI_REG78   0x78
+#define NB_PCI_REG7C   0x7C
+#define NB_PCI_REG7F   0x7f
+#define NB_PCI_REG95   0x95
+#define NB_PCI_REG97   0x97
+#define NB_PCI_REG80   0x80
+#define NB_PCI_REG84   0x84
+#define NB_PCI_REG8C   0x8C
+#define NB_PCI_REG8D   0x8D
+#define NB_PCI_REG90   0x90
+#define NB_PCI_REG94   0x94
+#define NB_PCI_REG98   0x98
+#define NB_PCI_REG9C   0x9C
+#define NB_PCI_REGA0   0xA0
+#define NB_PCI_REGA4   0xA4
+#define NB_PCI_REGA6   0xA6
+#define NB_PCI_REGA7   0xA7
+#define NB_PCI_REGA8   0xA8
+#define NB_PCI_REGAC   0xAC
+#define NB_PCI_REGC8   0xC8
+#define NB_PCI_REGCB   0xCB
+#define NB_PCI_REGD1   0xD1
+#define NB_PCI_REGD2   0xD2
+#define NB_PCI_REGE0   0xE0
+#define NB_PCI_REGE8   0xE8
+#define NB_PCI_REGF8   0xF8
+#define NB_PCI_REGFC   0xFC
+
+#define NB_APC_REG04   0x04
+#define NB_APC_REG18   0x18
+
+/******************************************************************************************
+; PCIE Port PCI config registers
+;******************************************************************************************/
+
+#define NB_PCIP_REG04   0x04
+#define NB_PCIP_REG18   0x18
+#define NB_PCIP_REG19   0x19
+#define NB_PCIP_REG20   0x20
+#define NB_PCIP_REG24   0x24
+#define NB_PCIP_REG3D   0x3D
+#define NB_PCIP_REG5A   0x5A
+#define NB_PCIP_REG64   0x64
+#define NB_PCIP_REG68   0x68
+#define NB_PCIP_REG6A   0x6A
+#define NB_PCIP_REG6B   0x6b
+#define NB_PCIP_REG6C   0x6c
+#define NB_PCIP_REG70   0x70
+#define NB_PCIP_REG72   0x72
+#define NB_PCIP_REG80   0x80
+#define NB_PCIP_REG88   0x88
+#define NB_PCIP_REGE0   0xE0
+#define NB_PCIP_REG108  0x108
+#define NB_PCIP_REG124  0x124
+#define NB_PCIP_REG12A  0x12A
+#define NB_PCIP_REG130  0x130
+#define NB_PCIP_REG134  0x134
+
+
+/******************************************************************************************
+; HTIUNBIND register definition
+;******************************************************************************************/
+
+#define NB_HTIU_INDEX   NB_PCI_REG94
+#define HTIU_WRITE      0x100
+
+#define NB_HTIU_REG05   (0x05 | HTIU_WRITE)
+#define NB_HTIU_REG06   (0x06 | HTIU_WRITE)
+#define NB_HTIU_REG07   (0x07 | HTIU_WRITE)
+#define NB_HTIU_REG0C   (0x0C | HTIU_WRITE)
+#define NB_HTIU_REG12   (0x12 | HTIU_WRITE)
+#define NB_HTIU_REG15   (0x15 | HTIU_WRITE)
+#define NB_HTIU_REG16   (0x16 | HTIU_WRITE)
+#define NB_HTIU_REG17   (0x17 | HTIU_WRITE)
+#define NB_HTIU_REG19   (0x19 | HTIU_WRITE)
+#define NB_HTIU_REG1A   (0x1A | HTIU_WRITE)
+#define NB_HTIU_REG1C   (0x1C | HTIU_WRITE)
+#define NB_HTIU_REG1D   (0x1D | HTIU_WRITE)
+#define NB_HTIU_REG1E   (0x1E | HTIU_WRITE)
+#define NB_HTIU_REG2A   (0x2A | HTIU_WRITE)
+#define NB_HTIU_REG2D   (0x2D | HTIU_WRITE)
+#define NB_HTIU_REG30   (0x30 | HTIU_WRITE)
+#define NB_HTIU_REG31   (0x31 | HTIU_WRITE)
+#define NB_HTIU_REG32   (0x32 | HTIU_WRITE)
+#define NB_HTIU_REG34   (0x34 | HTIU_WRITE)
+#define NB_HTIU_REG37   (0x37 | HTIU_WRITE)
+#define NB_HTIU_REG3A   (0x3A | HTIU_WRITE)
+#define NB_HTIU_REG3B   (0x3B | HTIU_WRITE)
+#define NB_HTIU_REG3C   (0x3C | HTIU_WRITE)
+#define NB_HTIU_REG46   (0x46 | HTIU_WRITE)
+#define NB_HTIU_REG4B   (0x4B | HTIU_WRITE)
+#define NB_HTIU_REG50   (0x50 | HTIU_WRITE)
+#define NB_HTIU_REG55   (0x55 | HTIU_WRITE)
+#define NB_HTIU_REG56   (0x56 | HTIU_WRITE)
+#define NB_HTIU_REG57   (0x57 | HTIU_WRITE)
+#define NB_HTIU_REG58   (0x58 | HTIU_WRITE)
+#define NB_HTIU_REG59   (0x59 | HTIU_WRITE)
+#define NB_HTIU_REG5A   (0x5A | HTIU_WRITE)
+#define NB_HTIU_REG5C   (0x5C | HTIU_WRITE)
+#define NB_HTIU_REG5D   (0x5D | HTIU_WRITE)
+#define NB_HTIU_REG5E   (0x5E | HTIU_WRITE)
+#define NB_HTIU_REG5F   (0x5F | HTIU_WRITE)
+#define NB_HTIU_REG60   (0x60 | HTIU_WRITE)
+#define NB_HTIU_REG61   (0x61 | HTIU_WRITE)
+#define NB_HTIU_REG62   (0x62 | HTIU_WRITE)
+#define NB_HTIU_REG63   (0x63 | HTIU_WRITE)
+#define NB_HTIU_REG64   (0x64 | HTIU_WRITE)
+#define NB_HTIU_REG65   (0x65 | HTIU_WRITE)
+#define NB_HTIU_REG66   (0x66 | HTIU_WRITE)
+#define NB_HTIU_REG68   (0x68 | HTIU_WRITE)
+#define NB_HTIU_REG6B   (0x6B | HTIU_WRITE)
+#define NB_HTIU_REG6D   (0x6D | HTIU_WRITE)
+#define NB_HTIU_REG70   (0x70 | HTIU_WRITE)
+#define NB_HTIU_REG71   (0x71 | HTIU_WRITE)
+#define NB_HTIU_REG72   (0x72 | HTIU_WRITE)
+#define NB_HTIU_REG73   (0x73 | HTIU_WRITE)
+#define NB_HTIU_REG74   (0x74 | HTIU_WRITE)
+#define NB_HTIU_REG75   (0x75 | HTIU_WRITE)
+#define NB_HTIU_REG87   (0x87 | HTIU_WRITE)
+#define NB_HTIU_REG88   (0x88 | HTIU_WRITE)
+#define NB_HTIU_REGA8   (0xA8 | HTIU_WRITE)
+#define NB_HTIU_REGA9   (0xA9 | HTIU_WRITE)
+
+/******************************************************************************************
+; Clock Configuration register
+;******************************************************************************************/
+#define NB_CLK_REG48    0x48
+#define NB_CLK_REG4C    0x4C
+#define NB_CLK_REG5C    0x5C
+#define NB_CLK_REG60    0x60
+#define NB_CLK_REG78    0x78
+#define NB_CLK_REG84    0x84
+#define NB_CLK_REG8C    0x8C
+#define NB_CLK_REG90    0x90
+#define NB_CLK_REG94    0x94
+#define NB_CLK_REGB0    0xB0
+#define NB_CLK_REGB4    0xB4
+#define NB_CLK_REGCC    0xCC
+#define NB_CLK_REGD4    0xD4
+#define NB_CLK_REGD5    0xD5
+#define NB_CLK_REGD6    0xD6
+#define NB_CLK_REGD8    0xD8
+#define NB_CLK_REGE0    0xE0
+#define NB_CLK_REGE4    0xE4
+#define NB_CLK_REGE8    0xE8
+#define NB_CLK_REGF0    0xF0
+#define NB_CLK_REGF4    0xF4
+#define NB_CLK_REGF8    0xF8
+#define NB_CLK_REGF9    0xF9
+#define NB_CLK_REGFA    0xFA
+#define NB_CLK_REGFB    0xFB
+
+/******************************************************************************************
+; MISCIND/NBCFG register definition
+;******************************************************************************************/
+#define NB_MISC_INDEX   NB_PCI_REG60
+#define MISC_WRITE      0x80
+
+#define NB_MISC_REG00   (0x00 | MISC_WRITE)
+#define NB_MISC_REG01   (0x01 | MISC_WRITE)
+#define NB_MISC_REG07   (0x07 | MISC_WRITE)
+#define NB_MISC_REG08   (0x08 | MISC_WRITE)
+#define NB_MISC_REG0B   (0x0B | MISC_WRITE)
+#define NB_MISC_REG0C   (0x0C | MISC_WRITE)
+#define NB_MISC_REG12   (0x12 | MISC_WRITE)
+#define NB_MISC_REG1E   (0x1E | MISC_WRITE)
+#define NB_MISC_REG1F   (0x1F | MISC_WRITE)
+#define NB_MISC_REG20   (0x20 | MISC_WRITE)
+#define NB_MISC_REG21   (0x21 | MISC_WRITE)
+#define NB_MISC_REG22   (0x22 | MISC_WRITE)
+#define NB_MISC_REG23   (0x23 | MISC_WRITE)
+#define NB_MISC_REG24   (0x24 | MISC_WRITE)
+#define NB_MISC_REG26   (0x26 | MISC_WRITE)
+#define NB_MISC_REG27   (0x27 | MISC_WRITE)
+#define NB_MISC_REG28   (0x28 | MISC_WRITE)
+#define NB_MISC_REG29   (0x29 | MISC_WRITE)
+#define NB_MISC_REG2A   (0x2A | MISC_WRITE)
+#define NB_MISC_REG2B   (0x2B | MISC_WRITE)
+#define NB_MISC_REG2C   (0x2C | MISC_WRITE)
+#define NB_MISC_REG2D   (0x2D | MISC_WRITE)
+#define NB_MISC_REG2E   (0x2E | MISC_WRITE)
+#define NB_MISC_REG2F   (0x2F | MISC_WRITE)
+#define NB_MISC_REG32   (0x32 | MISC_WRITE)
+#define NB_MISC_REG33   (0x33 | MISC_WRITE)
+#define NB_MISC_REG34   (0x34 | MISC_WRITE)
+#define NB_MISC_REG35   (0x35 | MISC_WRITE)
+#define NB_MISC_REG36   (0x36 | MISC_WRITE)
+#define NB_MISC_REG37   (0x37 | MISC_WRITE)
+#define NB_MISC_REG38   (0x38 | MISC_WRITE)
+#define NB_MISC_REG39   (0x39 | MISC_WRITE)
+#define NB_MISC_REG3A   (0x3A | MISC_WRITE)
+#define NB_MISC_REG3B   (0x3B | MISC_WRITE)
+#define NB_MISC_REG3C   (0x3C | MISC_WRITE)
+#define NB_MISC_REG40   (0x40 | MISC_WRITE)
+#define NB_MISC_REG48   (0x48 | MISC_WRITE)
+#define NB_MISC_REG49   (0x49 | MISC_WRITE)
+#define NB_MISC_REG4A   (0x4A | MISC_WRITE)
+#define NB_MISC_REG4B   (0x4B | MISC_WRITE)
+#define NB_MISC_REG4E   (0x4E | MISC_WRITE)
+#define NB_MISC_REG4F   (0x4F | MISC_WRITE)
+#define NB_MISC_REG51   (0x51 | MISC_WRITE)
+#define NB_MISC_REG53   (0x53 | MISC_WRITE)
+#define NB_MISC_REG55   (0x55 | MISC_WRITE)
+#define NB_MISC_REG57   (0x57 | MISC_WRITE)
+#define NB_MISC_REG59   (0x59 | MISC_WRITE)
+#define NB_MISC_REG5B   (0x5B | MISC_WRITE)
+#define NB_MISC_REG5D   (0x5D | MISC_WRITE)
+#define NB_MISC_REG5F   (0x5F | MISC_WRITE)
+#define NB_MISC_REG61   (0x61 | MISC_WRITE)
+#define NB_MISC_REG63   (0x63 | MISC_WRITE)
+#define NB_MISC_REG66   (0x66 | MISC_WRITE)
+#define NB_MISC_REG67   (0x67 | MISC_WRITE)
+#define NB_MISC_REG68   (0x68 | MISC_WRITE)
+#define NB_MISC_REG69   (0x69 | MISC_WRITE)
+#define NB_MISC_REG6A   (0x6A | MISC_WRITE)
+#define NB_MISC_REG6B   (0x6B | MISC_WRITE)
+#define NB_MISC_REG6C   (0x6C | MISC_WRITE)
+#define NB_MISC_REG6F   (0x6f | MISC_WRITE)
+#define NB_MISC_REG74   (0x74 | MISC_WRITE)
+#define NB_MISC_REG75   (0x75 | MISC_WRITE)
+#define NB_MISC_REG76   (0x76 | MISC_WRITE)
+#define NB_MISC_REG7D   (0x7D | MISC_WRITE)
+
+/******************************************************************************************
+; MISCIND/NBCFG register definition
+;******************************************************************************************/
+#define NB_MC_INDEX    NB_PCI_REGE8
+#define MC_WRITE       0x200
+
+#define NB_MC_REG01    (0x01 | MC_WRITE)
+#define NB_MC_REG02    (0x02 | MC_WRITE)
+#define NB_MC_REG04    (0x04 | MC_WRITE)
+#define NB_MC_REG05    (0x05 | MC_WRITE)
+#define NB_MC_REG06    (0x06 | MC_WRITE)
+#define NB_MC_REG07    (0x07 | MC_WRITE)
+#define NB_MC_REG08    (0x08 | MC_WRITE)
+#define NB_MC_REG09    (0x09 | MC_WRITE)
+#define NB_MC_REG0B    (0x0B | MC_WRITE)
+#define NB_MC_REG0C    (0x0C | MC_WRITE)
+#define NB_MC_REG0D    (0x0D | MC_WRITE)
+#define NB_MC_REG0E    (0x0E | MC_WRITE)
+#define NB_MC_REG0F    (0x0F | MC_WRITE)
+#define NB_MC_REG10    (0x10 | MC_WRITE)
+#define NB_MC_REG11    (0x11 | MC_WRITE)
+#define NB_MC_REG12    (0x12 | MC_WRITE)
+#define NB_MC_REG13    (0x13 | MC_WRITE)
+#define NB_MC_REG14    (0x14 | MC_WRITE)
+#define NB_MC_REG16    (0x16 | MC_WRITE)
+#define NB_MC_REG23    (0x23 | MC_WRITE)
+#define NB_MC_REG25    (0x25 | MC_WRITE)
+#define NB_MC_REG29    (0x29 | MC_WRITE)
+#define NB_MC_REG2A    (0x2A | MC_WRITE)
+#define NB_MC_REG2C    (0x2C | MC_WRITE)
+#define NB_MC_REG30    (0x30 | MC_WRITE)
+#define NB_MC_REG3C    (0x3C | MC_WRITE)
+#define NB_MC_REG3D    (0x3D | MC_WRITE)
+#define NB_MC_REG49    (0x49 | MC_WRITE)
+#define NB_MC_REG4A    (0x4A | MC_WRITE)
+#define NB_MC_REG4B    (0x4B | MC_WRITE)
+#define NB_MC_REG4C    (0x4C | MC_WRITE)
+#define NB_MC_REG4D    (0x4D | MC_WRITE)
+#define NB_MC_REGA0    (0xA0 | MC_WRITE)
+#define NB_MC_REGA1    (0xA1 | MC_WRITE)
+#define NB_MC_REGA2    (0xA2 | MC_WRITE)
+#define NB_MC_REGA3    (0xA3 | MC_WRITE)
+#define NB_MC_REGA4    (0xA4 | MC_WRITE)
+#define NB_MC_REGA5    (0xA5 | MC_WRITE)
+#define NB_MC_REGA6    (0xA6 | MC_WRITE)
+#define NB_MC_REGA7    (0xA7 | MC_WRITE)
+#define NB_MC_REGA8    (0xA8 | MC_WRITE)
+#define NB_MC_REGAA    (0xAA | MC_WRITE)
+#define NB_MC_REGAF    (0xAF | MC_WRITE)
+#define NB_MC_REGB0    (0xB0 | MC_WRITE)
+#define NB_MC_REGB2    (0xB2 | MC_WRITE)
+#define NB_MC_REGB1    (0xB1 | MC_WRITE)
+#define NB_MC_REGB4    (0xB4 | MC_WRITE)
+#define NB_MC_REGB5    (0xB5 | MC_WRITE)
+#define NB_MC_REGB6    (0xB6 | MC_WRITE)
+#define NB_MC_REGB7    (0xB7 | MC_WRITE)
+#define NB_MC_REGB8    (0xB8 | MC_WRITE)
+#define NB_MC_REGB9    (0xB9 | MC_WRITE)
+#define NB_MC_REGBA    (0xBA | MC_WRITE)
+#define NB_MC_REGC1    (0xC1 | MC_WRITE)
+#define NB_MC_REGC2    (0xC2 | MC_WRITE)
+#define NB_MC_REGC3    (0xC3 | MC_WRITE)
+#define NB_MC_REGC4    (0xC4 | MC_WRITE)
+#define NB_MC_REGC5    (0xC5 | MC_WRITE)
+#define NB_MC_REGC8    (0xC8 | MC_WRITE)
+#define NB_MC_REGC9    (0xC9 | MC_WRITE)
+#define NB_MC_REGCA    (0xCA | MC_WRITE)
+#define NB_MC_REGCB    (0xCB | MC_WRITE)
+#define NB_MC_REGCC    (0xCC | MC_WRITE)
+#define NB_MC_REGCE    (0xCE | MC_WRITE)
+#define NB_MC_REGD0    (0xD0 | MC_WRITE)
+#define NB_MC_REGD2    (0xD2 | MC_WRITE)
+#define NB_MC_REGD3    (0xD3 | MC_WRITE)
+#define NB_MC_REGD6    (0xD6 | MC_WRITE)
+#define NB_MC_REGD7    (0xD7 | MC_WRITE)
+#define NB_MC_REGD8    (0xD8 | MC_WRITE)
+#define NB_MC_REGD9    (0xD9 | MC_WRITE)
+#define NB_MC_REGE0    (0xE0 | MC_WRITE)
+#define NB_MC_REGE1    (0xE1 | MC_WRITE)
+#define NB_MC_REGE8    (0xE8 | MC_WRITE)
+#define NB_MC_REGE9    (0xE9 | MC_WRITE)
+#define NB_MC_REGF0    (0xF0 | MC_WRITE)
+
+/******************************************************************************************
+; PCIEIND_P(BIFNBP) register definition
+;******************************************************************************************/
+#define NB_BIF_INDEX   NB_PCI_REGE0
+
+#define NB_BIFNBP_REG01   0x01
+#define NB_BIFNBP_REG02   0x02
+#define NB_BIFNBP_REG10   0x10
+#define NB_BIFNBP_REG20   0x20
+#define NB_BIFNBP_REG40   0x40
+#define NB_BIFNBP_REG50   0x50
+#define NB_BIFNBP_REG70   0x70
+#define NB_BIFNBP_REGA0   0xA0
+#define NB_BIFNBP_REGA1   0xA1
+#define NB_BIFNBP_REGA2   0xA2
+#define NB_BIFNBP_REGA3   0xA3
+#define NB_BIFNBP_REGA4   0xA4
+#define NB_BIFNBP_REGA5   0xA5
+#define NB_BIFNBP_REGB1   0xB1
+#define NB_BIFNBP_REGC0   0xC0
+#define NB_BIFNBP_REGC1   0xC1
+
+/******************************************************************************************
+; PCIEIND(BIFNB) register definition
+;******************************************************************************************/
+#define NB_BIFNB_REG01   0x01
+#define NB_BIFNB_REG02   0x02
+#define NB_BIFNB_REG10   0x10
+#define NB_BIFNB_REG11   0x11
+#define NB_BIFNB_REG1C   0x1C
+#define NB_BIFNB_REG20   0x20
+#define NB_BIFNB_REG40   0x40
+#define NB_BIFNB_REG65   0x65
+#define NB_BIFNB_REGC1   0xC1
+#define NB_BIFNB_REGC2   0xC2
+#define NB_BIFNB_REGF9   0xF9
+
+
+#define MC_CLK_INDEX     0x60
+
+/******************************************************************************************
+; IOAPICCFG register definition
+;******************************************************************************************/
+#define NB_IOAPICCFG_INDEX    NB_PCI_REGF8
+
+#define NB_IOAPICCFG_REG00   0x00
+#define NB_IOAPICCFG_REG01   0x01
+#define NB_IOAPICCFG_REG02   0x02
+#define NB_IOAPICCFG_REG03   0x03
+#define NB_IOAPICCFG_REG04   0x04
+#define NB_IOAPICCFG_REG05   0x05
+#define NB_IOAPICCFG_REG06   0x06
+#define NB_IOAPICCFG_REG07   0x07
+#define NB_IOAPICCFG_REG08   0x08
+#define NB_IOAPICCFG_REG09   0x09
+#define NB_IOAPICCFG_REG0A   0x0A
+
+#endif
diff --git a/src/vendorcode/amd/cimx/rd890/nbType.h b/src/vendorcode/amd/cimx/rd890/nbType.h
new file mode 100644
index 0000000..ef224c3
--- /dev/null
+++ b/src/vendorcode/amd/cimx/rd890/nbType.h
@@ -0,0 +1,1075 @@
+/*
+ * @file
+ *
+ * Misc definitions.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-NB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _NBTYPE_H_
+#define _NBTYPE_H_
+
+//#pragma pack(push, 1) //GCC ERROR
+
+#define CIMX_NB_REVISION  "1.0.1.7"
+#define CIMX_NB_ID        "SR5690"
+
+#ifndef MAX_NB_COUNT
+  //#define MAX_NB_COUNT    4
+  #error hi, MAX_NB_COUNT not define
+#endif
+
+#define MAX_PORT_ID       13
+#define MIN_PORT_ID       2
+
+#define MAX_CORE_ID       4
+
+
+typedef  UINT32  PORT;
+typedef  UINT32  CORE;
+
+
+
+/// The HT Path to Northbridge
+typedef  struct {
+  UINT8                     NodeID;                 ///< Node ID
+  UINT8                     LinkID;                 /**< HT Link ID
+                                                      *   @par
+                                                      *   LinkID[3:0]- Link Id
+                                                      *   @li <b>0</b> - Link 0
+                                                      *   @li <b>1</b> - Link 1
+                                                      *   @li <b>2</b> - Link 2
+                                                      *   @li <b>3</b> - Link 3
+                                                      *   @par
+                                                      *    LinkID[7:4]- Sublink Id
+                                                      *   @li <b>1</b> - Sublink 0
+                                                      *   @li <b>2</b> - Sublink 1
+                                                      *
+                                                      *  @PlatformDependant
+                                                      */
+} HT_PATH;
+
+/// The configuration structure common header.
+typedef  struct {
+  UINT16                    Version;                ///< Version of this structure
+  UINT16                    Reserved;               ///< Reserved for future use
+  UINT32                    InitializerID;          ///< Signature of initializer
+} AMD_COMMON_STRUCT_HEADER;
+
+/// The PCIE configuration parameters
+typedef  struct {
+  AMD_COMMON_STRUCT_HEADER  sHeader;                  ///< Standard structure header
+  PCIE_MISC_CONFIG          PcieConfiguration;        ///< General configuration option
+  UINT32                    ExtPcieConfiguration;     ///< Extended General configuration option (Reserved for future use)
+  UINT32                    CoreConfiguration[5];      /**< Core configuration
+                                                       *  @li <b>CoreConfiguration[0]</b> - GPP1 Core Configuration
+                                                       *  <TABLE border="0">
+                                                       *     <TR><TD class="indexkey" width=120> Dual Port 2x8 </TD><TD class="indexvalue">if CoreConfiguration[0] == 0 && PortConfiguration[3].PortPresent == 1 </TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Dual Port 2x8 </TD><TD class="indexvalue">CoreConfiguration[0] == 0x02020101</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Single Port 1x16 </TD><TD class="indexvalue">if CoreConfiguration[0] == 0 && PortConfiguration[3].PortPresent == 0</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Single Port 1x16 </TD><TD class="indexvalue">CoreConfiguration[0] == 0x01010101</TD></TR>
+                                                       *  </TABLE>
+                                                       *  @li <b>CoreConfiguration[1]</b> - GPP2 Core Configuration
+                                                       *  <TABLE border="0">
+                                                       *     <TR><TD class="indexkey" width=120> Dual Port 2x8 </TD><TD class="indexvalue">if CoreConfiguration[1] == 0 && PortConfiguration[12].PortPresent == 1 </TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Dual Port 2x8 </TD><TD class="indexvalue">CoreConfiguration[1] == 0x02020101</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Single Port 1x16 </TD><TD class="indexvalue">if CoreConfiguration[1] == 0 && PortConfiguration[12].PortPresent == 0</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> Single Port 1x16 </TD><TD class="indexvalue">CoreConfiguration[1] == 0x01010101</TD></TR>
+                                                       *  </TABLE>
+                                                       *  @li <b>CoreConfiguration[2]</b> - GPP3a Core Configuration
+                                                       *  <TABLE border="0">
+                                                       *     <TR><TD class="indexkey" width=120> 4:2:0:0:0:0 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x1 </TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> 4:1:1:0:0:0 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x2</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> 2:2:2:0:0:0 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x3</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> 2:2:1:1:0:0 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x4</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> 2:1:1:1:1:0 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x5</TD></TR>
+                                                       *     <TR><TD class="indexkey" width=120> 1:1:1:1:1:1 </TD><TD class="indexvalue">CoreConfiguration[2] == 0x6</TD></TR>
+                                                       *  </TABLE>
+                                                       *  @li <b>CoreConfiguration[3]</b> - Reserved
+                                                       *  @li <b>CoreConfiguration[4]</b> - Reserved
+
+                                                       *  @PlatformDependant
+                                                       */
+  PCIE_CORE_SETTING         CoreSetting[5];            /**< Core setting
+                                                       *  see PCIE_CORE_SETTING for details
+                                                       *  @li <b>CoreSetting[0]</b> - GPP1 Core Settings
+                                                       *  @li <b>CoreSetting[1]</b> - GPP2 Core Settings
+                                                       *  @li <b>CoreSetting[2]</b> - GPP3a Core Settings
+                                                       *  @li <b>CoreSetting[3]</b> - GPP3b Core Settings
+                                                       *  @li <b>CoreSetting[4]</b> - SB Core setting
+                                                       */
+  PCIE_PORT_CONFIG          PortConfiguration[15];    /**< Port configuration
+                                                       *   see PCIE_PORT_CONFIG for details
+                                                       *   @li <b>PortConfiguration[0]</b> - Reserved
+                                                       *   @li <b>PortConfiguration[1]</b> - Reserved
+                                                       *   @li <b>PortConfiguration[2]</b> - PCIE Port Device 2 configuration
+                                                       *   @li <b>PortConfiguration[3]</b> - PCIE Port Device 3 configuration
+                                                       *   @li ...
+                                                       *   @li <b>PortConfiguration[13]</b> - PCIE Port Device 13 configuration
+                                                       *
+                                                       *  @PlatformDependant
+                                                       */
+  PCIE_EXT_PORT_CONFIG      ExtPortConfiguration[15];  /**<  Extended Port configuration
+                                                       *   see  PCIE_EXT_PORT_CONFIG for details.
+                                                       *   @li <b>ExtPortConfiguration[0]</b> - Reserved
+                                                       *   @li <b>ExtPortConfiguration[1]</b> - Reserved
+                                                       *   @li <b>ExtPortConfiguration[2]</b> - PCIE Port Device 2 configuration
+                                                       *   @li <b>ExtPortConfiguration[3]</b> - PCIE Port Device 3 configuration
+                                                       *   @li ...
+                                                       *   @li <b>ExtPortConfiguration[13]</b> - PCIE Port Device 13 configuration
+                                                       *
+                                                       *  @PlatformDependant
+                                                       */
+
+  UINT16                    PcieMmioBaseAddress;       /**< PCIE Extended MMIO base address in 1MB Unit.
+                                                       *  If PcieMmioBaseAddress == 0  assume MMIO setup already done.
+                                                       *  PCIE MMIO range should be programmed in CPU F1x[BC:80] Memory Mapped IO Base/Limit Registers as Non Posted if enabled in NB.
+                                                       *  <b>IMPORTANT!!! </b>Platform which use Rev10 and later CPU family should use PCIE MMIO functionality provided by CPU See "Configuration Space" in "BIOS and Kernel Developer's Guide For AMD Family 10h"
+                                                       *
+                                                       *  @PlatformDependant
+                                                       */
+
+  UINT16                    PcieMmioSize;              /**< PCIE Extended MMIO size in 1MB Unit.
+                                                       *   if PcieMmioBaseAddress != 0 and PcieMmioSize == 0  ignore both parameters and assume MMIO setup already done
+                                                       *   if PcieMmioBaseAddress == 0 and PcieMmioSize != 0  ignore both parameters and assume MMIO setup already done
+                                                       *   PCIE MMIO range should be programmed in CPU F1x[BC:80] Memory Mapped IO Base/Limit Registers as Non Posted if enabled in NB.
+                                                       *   <b>IMPORTANT!!!</b>Platform which use Rev10 and later CPU family should use PCIE MMIO functionality provided by CPU See "Configuration Space" in "BIOS and Kernel Developer's Guide For AMD Family 10h"
+                                                       *
+                                                       *   @PlatformDependant
+                                                       */
+  UINT16                    TempMmioBaseAddress;      /**< Temporary MMIO base in 1MB Unit
+                                                        *  MMIO base address for temporary 256MB MMIO range.
+                                                        *  Range should be programmed in CPU F1x[BC:80] Memory Mapped IO Base/Limit Registers as Posted
+                                                        *
+                                                        *  @PlatformDependant
+                                                        */
+  UINT16                    DeviceInitMaskS1;          ///< Bit mask of ports to be initialized at stage 1
+  UINT16                    DeviceInitMaskS2;          ///< Bit mask of ports to be initialized at stage 2
+  UINT16                    ResetToTrainingDelay;      ///< Delay (in 1ms) after reset deassert before training started
+  UINT16                    TrainingToLinkTestDelay;   ///< Delay (in 1ms) after training started but before pooling link state
+  UINT16                    ReceiverDetectionPooling;  ///< Total amount time (in 1ms of pooling for passing receiver detection stage
+  UINT32                    Reserved12[16];            ///< Reserved for internal use.
+} PCIE_CONFIG;
+
+
+
+/// The NB/IOMMU  configuration
+typedef  struct {
+  AMD_COMMON_STRUCT_HEADER  sHeader;                  ///< Standard structure header
+  UINT8                     UnitIdClumping;           /**< Unit ID clamping.
+                                                        *  UnitId clamping configuration base on PCIE port 3/12 presence.
+                                                        *  @li <b>0</b> - Disable
+                                                        *  @li <b>1</b> - Dev3
+                                                        *  @li <b>2</b> - Dev12
+                                                        *  @li <b>3</b> - Dev3 & Dev12
+
+                                                        *  @FilledByInitializer
+                                                        */
+  UINT8                     P2PMode;                  /**< Peer-To-Peer (p2p) Modes
+                                                        * Peep-To-Peer mode selection
+                                                        *  @li <b>0</b> - Default
+                                                        *  @li <b>1</b> - Mode 1
+                                                        *  @li <b>2</b> - Mode 2
+                                                        *  @li <b>0x8x</b> - Skip Initialization
+
+                                                        *  @FilledByInitializer
+                                                        */
+  UINT8                     Reserved2[2];             ///< Reserved for internal use.
+  UINT16                    SysMemoryTomBelow4G;      /**< Top of System memory below 4G in 1MB unit
+                                                       *  Top of physical memory including all reserved system memory etc.
+                                                       *  @PlatformDependant
+                                                       */
+  UINT32                    SysMemoryTomAbove4G;      /**< Top of System memory above 4G in 1MB unit
+                                                       *  Top of physical memory including all reserved system memory etc.
+                                                       *  @PlatformDependant
+                                                       */
+  UINT16                    Reserved;                 ///< Used for internally to save APIC ID of Core 0.
+  UINT64                    IommuBaseAddress;         /**< IOMMU base address.
+                                                        * 16kb aligned base address for IOMMU control registers
+                                                        * @PlatformDependant
+                                                        */
+  UINT64                    BroadcastBaseAddress;      /**< PCIE Broadcast MMIO base address.
+                                                       *  This feature can be utilized broadcast address aware driver (AMD GFX driver)
+                                                       *   If BroadcastBaseAddress == 0  MMIO will not be enabled
+                                                       *   @PlatformDependant
+                                                       */
+  UINT16                    BroadcastSize;            /**< PCIE Broadcast MMIO size in MB.
+                                                       *   If BroadcastSize == 0  MMIO will not be enabled
+                                                       *   @PlatformDependant
+                                                       */
+  UINT16                    Reserved3;                ///< Reserved for internal use.
+  UINT64                    IoApicBaseAddress;        /**< NB IO APIC Base address.
+                                                       *   If IoApicBaseAddress == 0  IOAPIC will not be enabled
+                                                       *   @PlatformDependant
+                                                       */
+  UINT32                    SSID;                     ///< NB Subsystem/Subvendor ID
+  UINT32                    IommuTpologyInfo;         ///< For intrernal use only
+  UINT32                    Reserved4[8];             ///< Reserved for internal use.
+} NB_CONFIG;
+
+
+/// The  NB Buffer Allocation/request parameters
+typedef struct {
+  IN  UINTN                 BufferLength;               ///< Buffer length
+  IN  UINT32                BufferHandle;               ///< Buffer handle
+  OUT VOID*                 BufferPtr;                  ///< Pointer to the buffer
+} NB_BUFFER_PARAMS;
+
+
+/// The  IOMMU exclusion range
+typedef struct {
+  UINT64                    Start;                      ///< Range Start  address
+  UINT64                    Length;                     ///< Range length
+} IOMMU_EXCLUSIONRANGE;
+
+//#pragma warning (push)
+//#pragma warning (disable: 4200)
+
+/// The  IOMMU exclusion table
+typedef struct {
+  UINTN                     TableLength;                ///< Exclusion table length
+  IOMMU_EXCLUSIONRANGE      ExclusionRange[];           ///< Array of exclusion range entries.
+} IOMMU_EXCLUSIONTABLE;
+//#pragma warning (pop)
+
+/// The  HT configuration structure
+typedef  struct {
+  AMD_COMMON_STRUCT_HEADER  sHeader;                     ///< Standard structure header
+  UINT8                     LSx;                         /**< HT link LS state enable
+                                                         *  @li <b>0</b> - LS0
+                                                         *  @li <b>1</b> - LS1
+                                                         *  @li <b>2</b> - LS2
+                                                         *  @li <b>3</b> - LS3
+                                                         *  @li <b>4</b> - Same as CPU (use CPU setting setup by AGESA)
+                                                         *  @li <b>0x8x</b> - Skip Setting
+
+                                                         *  @FilledByInitializer
+                                                         */
+  UINT8                     Reserved;                    ///< Reserved for internal use.
+  UINT8                     LinkBufferOptimization;      /**< CPU - NB HT link optimization.
+                                                          *  @li <b>0</b> - Disabled
+                                                          *  @li <b>1</b> - Enable
+                                                          *  @li <b>2..7</b> - Reserved
+                                                          */
+  UINT8                     HtExtendedAddressSupport;    /**<Extended HT Address Support
+                                                          *  @li <b>0</b> - Disable
+                                                          *  @li <b>1</b> - Enable
+                                                          *  @li <b>0x8x</b> - Skip setting
+
+                                                          *  @FilledByInitializer
+                                                          */
+  UINT8                     HtLinkTriState;              /**< HT Link  tristate control
+                                                          *  @li <b>1</b> - Disable
+                                                          *  @li <b>2</b> - CAD/CTL
+                                                          *  @li <b>3</b> - CAD/CTL/CLK
+                                                          *  @li <b>0x8x</b> - Skip setting
+
+                                                          *  @FilledByInitializer
+                                                          */
+  UINT8                     NbTransmitterDeemphasis;     /**< NB deemphasis level
+                                                          * @li <b>0</b> - Disabled
+                                                          * @li <b>1</b> - 1.32dB (0 to 4.5" trace length)
+                                                          * @li <b>2</b> - 2.08dB (4.5" to 8" trace length)
+                                                          * @li <b>3</b> - 3.10dB (8" to 11" trace length)
+                                                          * @li <b>4</b> - 4.22dB (11" to 14" trace length)
+                                                          * @li <b>5</b> - 5.50dB (14" to 18" trace length)
+                                                          * @li <b>6</b> - 7.05dB (18+" trace length)
+
+                                                          * @PlatformDependant
+                                                          */
+  UINT16                    HtReferenceClock;            /**< HT Reference clock.
+                                                          *
+                                                          *  @FilledByInitializer
+                                                          */
+  UINT32                    Reserved1[10];               ///< Reserved
+} HT_CONFIG;
+
+
+/// The  NB configuration structure
+struct _AMD_NB_CONFIG_BLOCK;
+typedef  struct _AMD_NB_CONFIG_BLOCK AMD_NB_CONFIG_BLOCK;
+
+/// The  NB configuration structure
+typedef  struct {
+  AMD_COMMON_STRUCT_HEADER  sHeader;                  ///< Standard structure header
+  PCI_ADDR                  NbPciAddress;             /**<PCI address of NB
+                                                        * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
+                                                        * Always 0:0:0 on single NB platform.
+                                                        * @PlatformDependant
+                                                        */
+  HT_PATH                   NbHtPath;                 /**< HT path to NB.
+                                                       *  Path to NB CPU->Ht Link Number->NB
+                                                       *  @PlatformDependant
+                                                       */
+  UINT16                    Reserved21;               ///< Reserved for internal use.
+  NB_CONFIG                 *pNbConfig;               ///< Pointer to NB configuration structure
+  HT_CONFIG                 *pHtConfig;               ///< Pointer to HT configuration structure
+  PCIE_CONFIG               *pPcieConfig;             ///< Pointer to PCIE configuration structure
+  AMD_NB_CONFIG_BLOCK       **ConfigPtr;              ///< Pointer to main config block structure
+  VOID                      *ReservedPtr;             ///< Reserved for internal use.
+} AMD_NB_CONFIG;
+
+
+/// The  configuration block for all NB in system.
+struct _AMD_NB_CONFIG_BLOCK {
+  AMD_CONFIG_PARAMS         StandardHeader;             ///< Standard structure header
+  UINT8                     NumberOfNorthbridges;       /**< Number of AMD_NB_CONFIG configuration structures
+                                                         *  @li <b>0</b> - One NB.
+                                                         *  @li <b>1</b> - Two NB.
+                                                         *  @li <b>2</b> - Three NB.
+                                                         *  @li <b>3</b> - Four NB.
+
+                                                         *  @PlatformDependant
+                                                         */
+  UINT8                     Scratch;                    /**< Variable for internal use
+                                                        *  @li <b>Bit[0]</b> = 0 Enable DebugOut, = 1 Disable DebugOut(only applicable for DebugOut enabled binaries).
+                                                        */
+  UINT8                     PlatformType;               /**< Platform Type (Server/Desktop).
+                                                         *  @li<b>0</b> - Unknown
+                                                         *  @li<b>1</b> - Desktop
+                                                         *  @li<b>2</b> - Server
+
+                                                         *  @PlatformDependant
+                                                         */
+  UINT8                     CurrentNorthbridge;         /**< Northbridge ID which currently being initialized.
+                                                         *  Variable filled by CIMx and can be used during callback
+                                                         *  to identify to which NB callback belongs.
+                                                         */
+  AMD_NB_CONFIG             Northbridges[MAX_NB_COUNT]; ///< Array of configuration structures for one or more NB in system
+};
+
+/// The IO APIC Interrupt Mapping Info
+typedef struct {
+  UINT8                     Group;                      /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
+                                                             @li <b>0</b> - mapped to Grp 0 (pin 0..3   of IO APIC)
+                                                             @li <b>1</b> - mapped to Grp 1 (pin 4..7   of IO APIC)
+                                                             @li ...
+                                                             @li <b>7</b> - mapped to Grp 7 (pin 28..31 of IO APIC)
+                                                        */
+  UINT8                     Swizzle;                    /**< Swizzle interrupt in the Group.
+                                                             @li <b>0</b> - ABCD
+                                                             @li <b>1</b> - BCDA
+                                                             @li <b>2</b> - CDAB
+                                                             @li <b>3</b> - DABC
+                                                        */
+  UINT8                     Pin;                        /**<Interrupt pin for PCIE bridge
+                                                             @li <b>0</b>  - Pin 0  of IO APIC
+                                                             @li <b>1</b>  - Pin 1  of IO APIC
+                                                             @li ...
+                                                             @li <b>31</b> - Pin 31 of IO APIC
+                                                        */
+} APIC_DEVICE_INFO;
+
+typedef AGESA_STATUS (*SYSTEM_API) (AMD_NB_CONFIG_BLOCK  *ConfigPtr);
+typedef AGESA_STATUS (*NB_API) (AMD_NB_CONFIG  *NbConfigPtr);
+
+/// Northbridge info
+typedef  struct {
+  UINT8                     Type;                         ///< NB Model (RS780/RD790/RD890...)
+  UINT8                     Revision;                     ///< NB Revision ID
+} NB_INFO;
+
+/// API workspace
+typedef struct {
+  AMD_NB_CONFIG_BLOCK       *ConfigPtr;                   ///< NB congiguration
+  AGESA_STATUS              Status;                       ///< return status
+} API_WORKSPACE;
+
+/// Indirect register entry
+typedef struct {
+  UINT32  Register;                                       ///< register
+  UINT32  Mask;                                           ///< AND mask
+  UINT32  Data;                                           ///< data
+} INDIRECT_REG_ENTRY;
+
+/// Register entry
+typedef struct {
+  UINT8  Register;                                        ///< register
+  UINT8  Mask;                                            ///< AND mask
+  UINT8  Data;                                            ///< data
+} REGISTER_ENTRY;
+
+/// Scratchpad
+typedef  struct {
+  UINT32                    ResetCount          :4;       ///< PCIe reset count
+  UINT32                    PortGen2Disable     :12;      ///< PCIe Gen 2 disable
+  UINT32                    MaskMemoryInit      :1;       ///< Mask memory init complete
+} SCRATCH_1;
+
+/// Scratchpad
+typedef  struct {
+  UINT32                    GlobalInterruptBase :8;       ///< TBD
+} SCRATCH_4;
+
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page LegacyInterfaceCalls  Legacy Interface Calls
+ *  <TD>@subpage PH_Initializer_Page "PH_Initializer"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdPowerOnResetInit_Page "PH_AmdPowerOnResetInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdNbHtInit_Page "PH_AmdNbHtInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdPcieEarlyInit_Page "PH_AmdPcieEarlyInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdEarlyPostInit_Page "PH_AmdEarlyPostInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdMidPostInit_Page "PH_AmdMidPostInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdLatePostInit_Page "PH_AmdLatePostInit"</TD><TD></TD>
+ *  <TD>@subpage PH_AmdS3Init_Page "PH_AmdS3Init"</TD><TD></TD>
+ *
+*/
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page PH_Initializer_Page PH_AmdNbInitializer
+ *  @section PH_Initializer PH_AmdNbInitializer Interface Call
+ *  Initialize structure referenced by AMD_NB_CONFIG::pHtConfig, AMD_NB_CONFIG::pPcieConfig and AMD_NB_CONFIG::pNbConfig to default recommended value.(Except platform dependant parameters See @ref PlatformDependParam "Platform Dependant Parameters" )
+ *  @subsection PH_Initializer_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_Initializer_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_Initializer_Page_Initializer Initializer
+ *  @par
+ *     Not Applicable
+ *  @subsection PH_Initializer_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::NumberOfNorthbridges </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbPciAddress </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdInitializer                 0x100
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ *  @page PH_AmdPowerOnResetInit_Page PH_AmdPowerOnResetInit
+ *  @section PH_AmdPowerOnResetInit PH_AmdPowerOnResetInit Interface Call
+ *  Initialize Northbridge registers on power-on reset.
+ *  @subsection PH_AmdPowerOnResetInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdPowerOnResetInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdPowerOnResetInit_Initializer Initializer
+ *  @par
+ *     Not Required
+ *  @subsection PH_AmdPowerOnResetInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::NumberOfNorthbridges </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbPciAddress </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdPowerOnResetInit            0x00
+/**
+ *  @page PH_AmdNbHtInit_Page PH_AmdNbHtInit
+ *  @section PH_AmdNbHtInit PH_AmdNbHtInit Interface Call
+ *  Initialize NB HT subsystem.
+ *  @subsection PH_AmdNbHtInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdNbHtInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdNbHtInit_Initializer Initializer
+ *  @par
+ *     Required (see @ref PH_Initializer_Page "PH_Initializer")
+ *  @subsection PH_AmdNbHtInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::NumberOfNorthbridges </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbPciAddress </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbHtPath  </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::pHtConfig </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdNbHtInit                    0x10
+/**
+ *  @page PH_AmdEarlyPostInit_Page PH_AmdEarlyPostInit
+ *  @section PH_AmdEarlyPostInit PH_AmdEarlyPostInit Interface Call
+ *   Initialize misc Northbridge feature at Early Post.
+ *  @subsection PH_AmdEarlyPostInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdEarlyPostInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey"  width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+  *  @subsection PH_AmdEarlyPostInit_Initializer Initializer
+ *  @par
+ *     Required. (see @ref PH_Initializer_Page)
+ *     PH_AmdEarlyPostInit/PH_AmdMidPostInit/PH_AmdLatePostInit/PH_AmdS3Init
+ *     must use same copy of AMD_NB_CONFIG_BLOCK
+ *  @subsection PH_AmdEarlyPostInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::NumberOfNorthbridges </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbPciAddress </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbHtPath  </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::pNbConfig </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::pPcieConfig </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> NB_CONFIG::SysMemoryTomBelow4G </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> NB_CONFIG::SysMemoryTomAbove4G </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdEarlyPostInit               0x30
+/**
+ *  @page PH_AmdMidPostInit_Page PH_AmdMidPostInit
+ *  @section PH_AmdMidPostInit PH_AmdMidPostInit Interface Call
+ *   Initialize misc Northbridge feature at Mid Post.
+ *  @subsection PH_AmdMidPostInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdMidPostInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdUpdateApicInterruptMapping_Page "PHCB_AmdUpdateApicInterruptMapping"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdAllocateBuffer_Page "PHCB_AmdAllocateBuffer "</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdGetExclusionTable_Page "PHCB_AmdGetExclusionTable "</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdMidPostInit_Initializer Initializer
+ *  @par
+ *     PH_AmdEarlyPostInit/PH_AmdMidPostInit/PH_AmdLatePostInit/PH_AmdS3Init must use same copy of AMD_NB_CONFIG_BLOCK structure.
+ *  @subsection PH_AmdMidPostInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> NB_CONFIG::IommuBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> NB_CONFIG::IoApicBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdMidPostInit                  0x40
+/**
+ *  @page PH_AmdLatePostInit_Page PH_AmdLatePostInit
+ *  @section PH_AmdLatePostInit PH_AmdLatePostInit Interface Call
+ *  Initialize misc Northbridge feature at Late Post.
+ *  @subsection PH_AmdLatePostInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdLatePostInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPcieAsmpInfo "PHCB_AmdPcieAsmpInfo"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdLatePostInit_Initializer Initializer
+ *  @par
+ *     PH_AmdEarlyPostInit/PH_AmdMidPostInit/PH_AmdLatePostInit/PH_AmdS3Init must use same copy of AMD_NB_CONFIG_BLOCK structure.
+ *  @subsection PH_AmdLatePostInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader</TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdLatePostInit                0x50
+
+ /**
+ *  @page PH_AmdPcieEarlyInit_Page PH_AmdPcieEarlyInit
+ *  @section PH_AmdPcieEarlyInit PH_AmdPcieEarlyInit Interface Call
+ *  Init PCI Express Subsystem. Train link on all enabled Ports. Initialize hotplug.
+ *  @subsection PH_AmdPcieEarlyInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdPcieEarlyInit_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPortTrainingCompleted_Page "PHCB_AmdPortTrainingCompleted"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPortResetSupported_Page "PHCB_AmdPortResetSupported"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPortResetAssert_Page "PHCB_AmdPortResetAssert"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPortResetDeassert_Page "PHCB_AmdPortResetDeassert"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdPcieEarlyInit_Initializer Initializer
+ *  @par
+ *     Required.
+ *  @subsection PH_AmdPcieEarlyInit_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::NumberOfNorthbridges </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::NbPciAddress </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG::pPcieConfig </TD><TD class="indexvalue"><B>Required</B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdPcieEarlyInit               0x20
+/**
+ *  @page PH_AmdS3Init_Page  PH_AmdS3Init
+ *  @section PH_AmdS3Init PH_AmdS3Init Interface Call
+ *  Init misc. feature PCI Express Subsystem. Enable power management  feature. Power off unused lanes/PLL etc.
+ *  @subsection PH_AmdPcieLateInit_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(ImageEntryPtr)(AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdS3Init_Callback Callback`s
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdUpdateApicInterruptMapping_Page "PHCB_AmdUpdateApicInterruptMapping"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdReportEvent_Page "PHCB_AmdReportEvent"</TD></TR>
+ *     <TR><TD class="indexkey" width=380> @ref PHCB_AmdPcieAsmpInfo "PHCB_AmdPcieAsmpInfo"</TD></TR>
+ *  </TABLE>
+ *  @subsection PH_AmdS3Init_Initializer Initializer
+ *  @par
+ *     PH_AmdEarlyPostInit/PH_AmdMidPostInit/PH_AmdLatePostInit/PH_AmdS3Init must use same copy of AMD_NB_CONFIG_BLOCK structure.
+ *  @subsection PH_AmdS3Init_Data Configuration Data.
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=380> AMD_NB_CONFIG_BLOCK::StandardHeader </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PH_AmdS3Init                      0x60
+
+/*
+  Secondary level interface function
+*/
+#define  PH_AmdPcieS3Init                  0x61
+#define  PH_AmdNbS3Init                    0x62
+#define  PH_AmdPcieLateInit                0x51
+#define  PH_AmdNbLateInit                  0x52
+
+/**
+ *This function PH_AmdPcieValidatePortState must be called
+ *  after the PH_AmdPcieEarlyInit and before PH_AmdLatePostInit
+ */
+#define  PH_AmdPcieValidatePortState       0x70
+
+
+/**
+ *  @page PHCB_AmdPortTrainingCompleted_Page PHCB_AmdPortTrainingCompleted
+ *  @section PHCB_AmdPortTrainingCompleted PHCB_AmdPortTrainingCompleted Callback
+ *  PCIE Port Initialization Completed endpoint detected.
+ *  @subsection PHCB_AmdPortTrainingCompleted_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, UINTN PortId, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PH_AmdS3Init_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8000</TD></TR>
+ *     <TR><TD class="indexkey" width=160>PortId</TD><TD class="indexvalue" width=500>PCI Express Port Id</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdPortTrainingCompleted_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback  not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_ERROR</TD><TD class="indexvalue" width=500>Disable Port</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdPortTrainingCompleted     0x8000
+/**
+ *  @page PHCB_AmdPortResetDeassert_Page PHCB_AmdPortResetDeassert
+ *  @section PHCB_AmdPortResetDeassert PHCB_AmdPortResetDeassert Callback
+ *  Deassert reset for device or slot connected to PCIE Port.
+ *  @subsection PHCB_AmdPortResetDeassert_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, UINTN PortIdBitMap, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdPortTrainingCompleted_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500> 0x8001</TD></TR>
+ *     <TR><TD class="indexkey" width=160>PortId</TD><TD class="indexvalue" width=500>bitmap of port id to deassert reset (0x4 - PortId 2, 0x8 PortId 3, ...)</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdPortTrainingCompleted_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback  not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Reset successfully deasserted</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdPortResetDeassert         0x8001
+/**
+ *  @page PHCB_AmdPortResetAssert_Page PHCB_AmdPortResetAssert
+ *  @section PHCB_AmdPortResetAssert PHCB_AmdPortResetAssert Callback
+ *  Assert reset for device connected to PCIE Port.
+ *  @subsection PHCB_AmdPortResetDeassert_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, UINTN PortIdBitMap, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdPortResetAssert_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8002</TD></TR>
+ *     <TR><TD class="indexkey" width=160>PortIdBitMap</TD><TD class="indexvalue" width=500>Bitmap of port id to assert reset (0x4 - PortId 2, 0x8 PortId 3, ...)</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdPortResetAssert_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback  not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Reset successfully asserted</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdPortResetAssert           0x8002
+/**
+ *  @page PHCB_AmdPortResetSupported_Page PHCB_AmdPortResetSupported
+ *  @section PHCB_AmdPortResetSupported PHCB_AmdPortResetSupported Callback
+ *  Test if controllable reset logic present for PCIE Port.
+ *  @subsection PHCB_AmdPortResetSupported_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, UINTN PortId, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdPortResetSupported_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8003</TD></TR>
+ *     <TR><TD class="indexkey" width=160>PortId</TD><TD class="indexvalue" width=500> Port ID to check GPIO controlled reset logic present for slot or endpoint connected to this port</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdPortResetSupported_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback  not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Slot/Device connected to port has GPIO controlled reset logic</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdPortResetSupported        0x8003
+
+
+/**
+ *  @page PHCB_AmdGeneratePciReset_Page PHCB_AmdGeneratePciReset
+ *  @section PHCB_AmdPortResetSupported PHCB_AmdGeneratePciReset Callback
+ *  Request PCI reset generation.
+ *  @subsection PHCB_AmdGeneratePciReset_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, UINTN ResetType, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdGeneratePciReset_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8004</TD></TR>
+ *     <TR><TD class="indexkey" width=160>PortId</TD><TD class="indexvalue" width=500> Reset type. 0x01 - Warm Reset,  0x02 - Cold Reset</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdGeneratePciReset_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>"Any"</TD><TD class="indexvalue" width=500>CIMx will generate reset by writing port 0xCF9</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Debug feature to completely avoid reset generation</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdGeneratePciReset          0x8004
+
+/**
+ *  @page PHCB_AmdGetExclusionTable_Page PHCB_AmdGetExclusionTable
+ *  @section PHCB_AmdGetExclusionTable PHCB_AmdGetExclusionTable Callback
+ *  Return the IOMMU exclusion table related to the current configuration block
+ *  @subsection PHCB_AmdGetExclusionTable_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, IOMMU_EXCLUSIONTABLE *ExclusionTable, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdGetExclusionTable_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8005</TD></TR>
+ *     <TR><TD class="indexkey" width=160>ExclusionTable</TD><TD class="indexvalue" width=500>Pointer to IOMMU exclusion table</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdGetExclusionTable_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Valid table returned</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdGetExclusionTable           0x8005
+
+/**
+ *  @page PHCB_AmdAllocateBuffer_Page PHCB_AmdAllocateBuffer
+ *  @section PHCB_AmdAllocateBuffer PHCB_AmdAllocateBuffer Callback
+ *  Return the address of a memory buffer (size in bytes).
+ *
+ *  ACPI handles used:
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>'SRVI'</TD><TD class="indexvalue" width=500>IO virtualization table</TD></TR>
+ *  </TABLE>
+ *  @par
+ *  Usage: Buffer can be be allocated via PMM function 0 with handle and size specified in BufferParamsPtr, and
+ *         the address must be returned in BufferParamsPtr.
+ *  @par
+ *  <b>Important Note:</b>  Allocation for ACPI table will be requested during AmdEarlyPostInit or AmdMidPostInit and must be linked to
+ *          ACPI table structure prior AmdLatePostInit interface call.
+ *  @subsection PHCB_AmdAllocateBuffer_Callin Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, NB_BUFFER_PARAMS *BufferParamPtr, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdAllocateBuffer_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8006</TD></TR>
+ *     <TR><TD class="indexkey" width=160>BufferParamPtr</TD><TD class="indexvalue" width=500>Pointer to buffer parameters</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdAllocateBuffer_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Buffer returned</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdAllocateBuffer               0x8006
+
+/**
+ *  @page PHCB_AmdUpdateApicInterruptMapping_Page PHCB_AmdUpdateApicInterruptMapping
+ *  @section PHCB_AmdUpdateApicInterruptMapping PHCB_AmdUpdateApicInterruptMapping Callback
+ *  Provide pointer to default IOAPIC interrupt mapping table
+ *  @subsection PHCB_AmdUpdateApicInterruptMapping_Callin Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, APIC_DEVICE_INFO *pApicPortInfo, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdUpdateApicInterruptMapping_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8007</TD></TR>
+ *     <TR><TD class="indexkey" width=160>pApicPortInfo</TD><TD class="indexvalue" width=500>Pointer to array of structures containing default IO APIC interrupt mapping info. For default interrupt mapping info see \ref gDefaultApicDeviceInfoTable</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdUpdateApicInterruptMapping_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Interrupt mapping configuration completed</TD></TR>
+ *  </TABLE>
+ *
+ */
+
+#define  PHCB_AmdUpdateApicInterruptMapping     0x8007
+
+/**
+ *  @page PHCB_AmdFreeBuffer_Page PHCB_AmdFreeBuffer
+ *  @section PHCB_AmdFreeBuffer PHCB_AmdFreeBuffer Callback
+ *  Free a specific memory buffer by handle.
+ *
+ *  ACPI handles used:
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>'SRVI'</TD><TD class="indexvalue" width=500>IO virtualization table</TD></TR>
+ *  </TABLE>
+ *  @par
+ *  <b>Important Note:</b> ACPI tables  as listed above will not be explicitly freed and must be linked into the system ACPI table structure.
+ *
+ *  @subsection PHCB_AmdFreeBuffer_Callin Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, NB_BUFFER_PARAMS *BufferParamPtr, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdFreeBuffer_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8008</TD></TR>
+ *     <TR><TD class="indexkey" width=160>BufferParamPtr</TD><TD class="indexvalue" width=500>Pointer to buffer parameters</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdFreeBuffer_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Buffer freed</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdFreeBuffer                       0x8008
+
+/**
+ *  @page PHCB_AmdLocateBuffer_Page PHCB_AmdLocateBuffer
+ *  @section PHCB_AmdLocateBuffer PHCB_AmdLocateBuffer Callback
+ *  Locate a specific memory buffer by handle (See also @ref PHCB_AmdAllocateBuffer_Page "PHCB_AmdAllocateBuffer").
+ *
+ *  @subsection PHCB_AmdLocateBuffer_Callin Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, NB_BUFFER_PARAMS *BufferParamPtr, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdLocateBuffer_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8009</TD></TR>
+ *     <TR><TD class="indexkey" width=160>BufferParamPtr</TD><TD class="indexvalue" width=500>Pointer to buffer parameters</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdLocateBuffer_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Buffer Located</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdLocateBuffer                     0x8009
+
+/**
+ *  @page PHCB_AmdReportEvent_Page PHCB_AmdReportEvent
+ *  @section PHCB_AmdReportEvent PHCB_AmdReportEvent Callback
+ *  Report event to platform firmware
+ *  To exclude an entry, set the value of DeviceId to 0xFFFF
+ *
+ *  @subsection PHCB_AmdReportEvent_Callin Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, AGESA_EVENT *Event, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdReportEvent_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> CallBackId</TD><TD class="indexvalue" width=500>0x8010</TD></TR>
+ *     <TR><TD class="indexkey" width=160> Event</TD><TD class="indexvalue" width=500>pointer to event structure</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdReportEvent_Events Events
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> Event Class</TD><TD class="indexkey">Event Info </TD><TD class="indexkey">Description</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_ERROR</TD><TD class="indexvalue">0x20010100</TD><TD class="indexvalue" >Hotplug controller firmware initialization fail</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_ERROR</TD><TD class="indexvalue">0x20010200</TD><TD class="indexvalue">Link training fail</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_ERROR</TD><TD class="indexvalue">0x20010300</TD><TD class="indexvalue">Incorrect PCIE Core COnfiguration requested</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_WARNING</TD><TD class="indexvalue">0x20010400</TD><TD class="indexvalue">Link width downgraded </TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_WARNING</TD><TD class="indexvalue">0x20010500</TD><TD class="indexvalue">Link speed forced to Gen1.</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_WARNING</TD><TD class="indexvalue">0x20010600</TD><TD class="indexvalue">VCO negotiation fail.</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_WARNING</TD><TD class="indexvalue">0x20010700</TD><TD class="indexvalue">Incorrect port device number remapping configuration</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_FATAL</TD><TD class="indexvalue">0x20000100</TD><TD class="indexvalue" >Invalid configuration structure</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_WARRNING</TD><TD class="indexvalue">0x20000200</TD><TD class="indexvalue">NB not present</TD></TR>
+ *     <TR><TD class="indexvalue" width=160> AGESA_ERROR</TD><TD class="indexvalue">0x20000300</TD><TD class="indexvalue">Can not locate ACPI table</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdReportEvent_Return Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>AGESA_UNSUPPORTED</TD><TD class="indexvalue" width=500>Callback not supported</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AGESA_SUCCESS</TD><TD class="indexvalue" width=500>Event successfully logged</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define PHCB_AmdReportEvent                    0x8010
+/**
+ *  @page PHCB_AmdPcieAsmpInfo_Page PHCB_AmdPcieAsmpInfo
+ *  @section PHCB_AmdPcieAsmpInfo PHCB_AmdPcieAsmpInfo Callback
+ *  Give platform chance to update PCIe link ASPM setting.
+ *  @subsection PHCB_AmdPcieAsmpInfo_CallIn Call Prototype
+ *  @par
+ *     AGESA_STATUS *(CallBackPtr)(UINT32 CallBackId, ASPM_LINK_INFO *AspmLinkInfoPtr, AMD_NB_CONFIG_BLOCK *ConfigPtr)
+ *  @subsection PHCB_AmdPcieAsmpInfo_Parameters Parameters
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>CallBackId</TD><TD class="indexvalue" width=500>0x8011</TD></TR>
+ *     <TR><TD class="indexkey" width=160>AspmLinkInfoPtr</TD><TD class="indexvalue" width=500> ASPM link info see ASPM_LINK_INFO for details.</TD></TR>
+ *  </TABLE>
+ *  @subsection PHCB_AmdPcieAsmpInfo_Retrun Return Value
+ *  @par
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160>"Any"</TD><TD class="indexvalue" width=500>CIMx will use content on ASPM_LINK_INFO to enable ASPM</TD></TR>
+ *  </TABLE>
+ *
+ */
+#define  PHCB_AmdPcieAsmpInfo                   0x8011
+
+
+#define CB_AmdSetNbPorConfig                    0x9000
+#define CB_AmdSetHtConfig                       0x9001
+#define CB_AmdSetPcieEarlyConfig                0x9002
+#define CB_AmdSetEarlyPostConfig                0x9003
+#define CB_AmdSetMidPostConfig                  0x9004
+#define CB_AmdSetLatePostConfig                 0x9005
+#define CB_AmdSetRecoveryConfig                 0x9006
+
+#define ON                                      0x1
+#define OFF                                     0x0
+
+#define NB_RD890TV                              0x00
+#define NB_RD780                                0x01
+#define NB_RX780                                0x02
+#define NB_SR5690                               0x10
+#define NB_SR5670                               0x15
+#define NB_SR5650                               0x20
+#define NB_RD890                                0x25
+#define NB_990FX                                0x25        //990FX= RD890
+#define NB_990X                                 0x30        //990X= SR5650
+#define NB_970                                  0x35
+
+#define NB_UNKNOWN                              0xff
+
+#define NB_REV_A11                              0x00
+#define NB_REV_A12                              0x02
+
+#define DEV3_CLUMPING                           1
+#define DEV12_CLUMPING                          2
+
+#define INITIALIZED_BY_INITIALIZER              0xAA
+
+#define CPU_FAMILY_NPT                          0x00000000
+#define CPU_FAMILY_GH                           0x00100000
+
+#define GET_NB_CONFIG_PTR(x)                    x->pNbConfig
+#define GET_HT_CONFIG_PTR(x)                    x->pHtConfig
+#define GET_PCIE_CONFIG_PTR(x)                  x->pPcieConfig
+#define GET_BLOCK_CONFIG_PTR(x)                 (*(x->ConfigPtr))
+#define NB_SBDFO                                pConfig->NbPciAddress.AddressValue
+
+#define ABCD                                    0
+#define BCDA                                    1
+#define CDAB                                    2
+#define DABC                                    3
+
+/// Platform Type
+typedef enum {
+  DetectPlatform,                           ///< Autodetect platform type based on NB skew
+  DesktopPlatform,                          ///< Desktop platform
+  ServerPlatform                            ///< Server platform
+} PLATFORM_TYPE;
+
+/// APIC register info
+typedef struct {
+  UINT8 EpRoutingOffset;                    ///< Ep routing offset
+  UINT8 EpRoutingRegister;                  ///< Ep routing reg
+  UINT8 RcRoutingOffset;                    ///< Rc routing offset
+  UINT8 RcRoutingRegister;                  ///< Rc routing reg
+} APIC_REGISTER_INFO;
+
+
+#define PortInterruptPinMap(Pin, Port) (Pin << Port)
+
+#define HtPinMapOffset                        0
+#define IommuPinMapOffset                     8
+
+
+#define CIMX_MIN(x, y) (((x) > (y)) ? (y) : (x))
+#define CIMX_MAX(x, y) (((x) > (y)) ? (x) : (y))
+//#pragma pack(pop)
+
+#endif


From gerrit at coreboot.org  Fri Jan 20 06:44:43 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:43 +0100
Subject: [coreboot] New patch to review for coreboot: c52e62d RD890: pci_ids
	update
References: <I30c62c5802279ff2ee8da1cae41395e6899339bb+0@gerrit.coreboot.org>
Message-ID: <I30c62c5802279ff2ee8da1cae41395e6899339bb+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/558

-gerrit

commit c52e62de11ca8c0bc92677794fbfe2f0fb331ea8
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:58:53 2012 +0800

    RD890: pci_ids update
    
    RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX
    chipsets, add their pci device id respectively.
    
    Change-Id: I30c62c5802279ff2ee8da1cae41395e6899339bb
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/include/device/pci_ids.h |   11 ++++++++---
 1 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d16f85e..fcd31c0 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -394,9 +394,14 @@
 #define PCI_DEVICE_ID_ATI_RS785MC_INT_GFX	0x9713
 #define PCI_DEVICE_ID_ATI_RS785D_INT_GFX	0x9714
 
-#define PCI_DEVICE_ID_AMD_SR5650_HT            0x5A13
-#define PCI_DEVICE_ID_AMD_SR5670_HT            0x5A12
-#define PCI_DEVICE_ID_AMD_SR5690_HT            0x5A10
+#define PCI_DEVICE_ID_AMD_RD890TV_HT		0x5956
+#define PCI_DEVICE_ID_AMD_RX780_HT		0x5957
+#define PCI_DEVICE_ID_AMD_RD780_HT		0x5958
+#define PCI_DEVICE_ID_AMD_SR5690_HT		0x5A10
+#define PCI_DEVICE_ID_AMD_RD890_HT		0x5A11
+#define PCI_DEVICE_ID_AMD_SR5670_HT		0x5A12
+#define PCI_DEVICE_ID_AMD_SR5650_HT		0x5A13
+#define PCI_DEVICE_ID_AMD_990FX_HT		0x5A14
 #define PCI_DEVICE_ID_AMD_SR5650_PCIE          0x5A12
 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV2     0x5A16
 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV3     0x5A17


From gerrit at coreboot.org  Fri Jan 20 06:44:45 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:45 +0100
Subject: [coreboot] New patch to review for coreboot: 6b4f1c7 RD890: AMD
	RD890/SR56X0 CIMX wrapper
References: <I39dc5fc316fbb465808bac48a13a49b7d867f04f+0@gerrit.coreboot.org>
Message-ID: <I39dc5fc316fbb465808bac48a13a49b7d867f04f+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559

-gerrit

commit 6b4f1c7a51bfe2854cf720df838d92e3890dfee6
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:01 2012 +0800

    RD890: AMD RD890/SR56X0 CIMX wrapper
    
    Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
    RD890 and 990FX chipsets.
    
    Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/northbridge/amd/Kconfig                 |    1 +
 src/northbridge/amd/Makefile.inc            |    1 +
 src/northbridge/amd/cimx/Kconfig            |   24 ++
 src/northbridge/amd/cimx/Makefile.inc       |   20 ++
 src/northbridge/amd/cimx/rd890/Kconfig      |   33 +++
 src/northbridge/amd/cimx/rd890/Makefile.inc |   26 ++
 src/northbridge/amd/cimx/rd890/NbPlatform.h |  147 ++++++++++
 src/northbridge/amd/cimx/rd890/amd.h        |  385 +++++++++++++++++++++++++++
 src/northbridge/amd/cimx/rd890/cbtypes.h    |   71 +++++
 src/northbridge/amd/cimx/rd890/chip.h       |   38 +++
 src/northbridge/amd/cimx/rd890/early.c      |  113 ++++++++
 src/northbridge/amd/cimx/rd890/late.c       |  269 +++++++++++++++++++
 src/northbridge/amd/cimx/rd890/nb_cimx.h    |   44 +++
 13 files changed, 1172 insertions(+), 0 deletions(-)

diff --git a/src/northbridge/amd/Kconfig b/src/northbridge/amd/Kconfig
index 4a120ca..33e19c2 100644
--- a/src/northbridge/amd/Kconfig
+++ b/src/northbridge/amd/Kconfig
@@ -4,6 +4,7 @@ source src/northbridge/amd/gx2/Kconfig
 source src/northbridge/amd/amdfam10/Kconfig
 source src/northbridge/amd/lx/Kconfig
 source src/northbridge/amd/agesa/Kconfig
+source src/northbridge/amd/cimx/Kconfig
 menu "HyperTransport setup"
 	#could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8)
 	depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index bf96b80..c438473 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -5,3 +5,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
 
 subdirs-$(CONFIG_AMD_AGESA) += agesa
+subdirs-$(CONFIG_AMD_NB_CIMX) += cimx
diff --git a/src/northbridge/amd/cimx/Kconfig b/src/northbridge/amd/cimx/Kconfig
new file mode 100644
index 0000000..6751bd4
--- /dev/null
+++ b/src/northbridge/amd/cimx/Kconfig
@@ -0,0 +1,24 @@
+#
+# This file is part of the coreboot project.
+#
+#Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config AMD_NB_CIMX
+	bool
+	default n
+
+source src/northbridge/amd/cimx/rd890/Kconfig
diff --git a/src/northbridge/amd/cimx/Makefile.inc b/src/northbridge/amd/cimx/Makefile.inc
new file mode 100644
index 0000000..80844c8
--- /dev/null
+++ b/src/northbridge/amd/cimx/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
diff --git a/src/northbridge/amd/cimx/rd890/Kconfig b/src/northbridge/amd/cimx/rd890/Kconfig
new file mode 100644
index 0000000..6731b60
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/Kconfig
@@ -0,0 +1,33 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_CIMX_RD890
+	bool
+	default n
+	select AMD_NB_CIMX
+
+config REDIRECT_NBCIMX_TRACE_TO_SERIAL
+	bool "Redirect AMD Northbridge CIMX Trace to serial console"
+	default n
+	depends on NORTHBRIDGE_AMD_CIMX_RD890
+	help
+	  This Option allows you to redirect the AMD Northbridge CIMX
+	  Trace debug information to the serial console.
+
+          Warning: Only enable this option when debuging or tracing AMD CIMX code.
diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc
new file mode 100644
index 0000000..c3a5084
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/Makefile.inc
@@ -0,0 +1,26 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += ../../../../../src/vendorcode/amd/cimx/rd890
+
+# RD890 Platform Files
+romstage-y += early.c
+
+ramstage-y += late.c
+
diff --git a/src/northbridge/amd/cimx/rd890/NbPlatform.h b/src/northbridge/amd/cimx/rd890/NbPlatform.h
new file mode 100644
index 0000000..824057a
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/NbPlatform.h
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _NB_PLATFORM_H_
+#define _NB_PLATFORM_H_
+
+#define SERIAL_OUT_SUPPORT //enable serial output
+#define CIMX_DEBUG
+
+#ifdef  CIMX_DEBUG
+#define CIMX_TRACE_SUPPORT
+#define CIMX_ASSERT_SUPPORT
+#endif
+
+#ifdef  CIMX_TRACE_SUPPORT
+	#define CIMX_INIT_TRACE(Arguments)
+	#if CONFIG_REDIRECT_NBCIMX_TRACE_TO_SERIAL
+		#define TRACE_DATA(Ptr, Level) BIOS_DEBUG //always enable
+		#define CIMX_TRACE(Argument) do {do_printk Argument;} while (0)
+	#else
+		#define TRACE_DATA(Ptr, Level)
+		#define CIMX_TRACE(Argument)
+	#endif
+#else
+	#define CIMX_TRACE(Argument)
+	#define CIMX_INIT_TRACE(Arguments)
+#endif
+
+#ifdef CIMX_ASSERT_SUPPORT
+	#ifdef ASSERT
+		#undef ASSERT
+		#define ASSERT CIMX_ASSERT
+	#endif
+	#ifdef CIMX_TRACE_SUPPORT
+		#define CIMX_ASSERT(x)  if(!(x)) {\
+			LibAmdTraceDebug (CIMX_TRACE_ALL, (CHAR8 *)"ASSERT !!! "__FILE__" - line %d\n", __LINE__); \
+			/*__asm {jmp $}; */\
+		}
+	//#define IDS_HDT_CONSOLE(s, args...) do_printk(BIOS_DEBUG, s, ##args)
+	#else
+		#define CIMX_ASSERT(x) if(!(x)) {\
+			/*__asm {jmp $}; */\
+		}
+	#endif
+#else
+	#define CIMX_ASSERT(x)
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs)
+#define STALL(Ptr, TimeUs, Flag) LibAmdSbStall(TimeUs, Ptr)
+
+#ifdef  B2_IMAGE
+#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr) LibNbEventLog(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
+#else
+#define REPORT_EVENT(Class, Info, Param1, Param2, Param3, Param4, CfgPtr)
+#endif
+
+
+
+// CIMX configuration parameters
+//#define CIMX_B2_IMAGE_BASE_ADDRESS      0xFFF40000
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef  MOVE_PCIEBAR_TO_F0000000
+#define PCIEX_BASE_ADDRESS           0xF7000000
+#else
+#define PCIEX_BASE_ADDRESS           CONFIG_MMCONF_BASE_ADDRESS
+#endif
+
+
+
+#define CIMX_S3_SAVE 1
+#include "cbtypes.h"
+#include <console/console.h>
+
+#include "amd.h" //cimx typedef
+#include <amdlib.h>
+#include "amdAcpiLib.h"
+#include "amdAcpiMadt.h"
+#include "amdAcpiIvrs.h"
+#include "amdSbLib.h"
+#include "nbPcie.h"
+
+//must put before the nbType.h
+#include "platform_cfg.h" /*platform dependented configuration */
+#include "nbType.h"
+
+#include "nbLib.h"
+#include "nbDef.h"
+#include "nbInit.h"
+#include "nbHtInit.h"
+#include "nbIommu.h"
+#include "nbEventLog.h"
+#include "nbRegisters.h"
+#include "nbPcieAspm.h"
+#include "nbPcieLinkWidth.h"
+#include "nbPcieHotplug.h"
+#include "nbPciePortRemap.h"
+#include "nbPcieWorkarounds.h"
+#include "nbPcieCplBuffers.h"
+#include "nbPciePllControl.h"
+#include "nbMiscInit.h"
+#include "nbIoApic.h"
+#include "nbPcieSb.h"
+#include "nbRecovery.h"
+#include "nbMaskedMemoryInit.h"
+
+
+#define FIX_PTR_ADDR(x, y) x
+
+#define TRACE_ALWAYS  0xffffffff
+
+#define AmdNbDispatcher NULL
+
+#define CIMX_TRACE_ALL    0xFFFFFFFF
+#define CIMX_NBPOR_TRACE  0xFFFFFFFF
+#define CIMX_NBHT_TRACE   0xFFFFFFFF
+#define CIMX_NBPCIE_TRACE 0xFFFFFFFF
+#define CIMX_NB_TRACE     0xFFFFFFFF
+#define CIMX_NBPCIE_MISC  0xFFFFFFFF
+
+#endif
+
diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h
new file mode 100644
index 0000000..d99f90f
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/amd.h
@@ -0,0 +1,385 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#include "cbtypes.h"
+
+
+#define VOLATILE  volatile
+#define CALLCONV
+#define ROMDATA
+#define CIMXAPI   EFIAPI
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+#ifndef NULL
+  #define NULL 0
+#endif
+
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+#define IMAGE_SIGNATURE 'DMA$'
+
+typedef UINTN AGESA_STATUS;
+
+
+#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+
+// AGESA Structures
+/// The standard header AMD NB UEFI drivers
+typedef struct _AMD_CONFIG_PARAMS {
+  VOID            **PeiServices;              ///< Pointer to PEI service table
+  VOID            *StallPpi;                  ///< Pointer to Stall PPI
+//  UINT32          Func;
+  VOID            *PcieBasePtr;               ///< TBD
+  CALLOUT_ENTRY   CalloutPtr;                 ///<pointer to local driver callback function
+  CALLOUT_ENTRY   InterfaceCalloutPtr;        ///<pointer to external interface driver callback function
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlockPtr;   ///< Next module header link
+} AMD_MODULE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct _CPUID_DATA {
+  IN  OUT UINT32          EAX_Reg;                ///< CPUID instruction result in EAX
+  IN  OUT UINT32          EBX_Reg;                ///< CPUID instruction result in EBX
+  IN  OUT UINT32          ECX_Reg;                ///< CPUID instruction result in ECX
+  IN  OUT UINT32          EDX_Reg;                ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+#define WARM_RESET 1
+#define COLD_RESET 2
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#ifdef  ASSERT
+  #undef  ASSERT
+  #define ASSERT(x)
+#endif
+
+#endif
diff --git a/src/northbridge/amd/cimx/rd890/cbtypes.h b/src/northbridge/amd/cimx/rd890/cbtypes.h
new file mode 100644
index 0000000..ade55d7
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/cbtypes.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+/*
+typedef int64_t __int64;
+typedef void VOID;
+typedef uint32_t UINTN;//
+typedef int8_t CHAR8;
+typedef uint8_t UINT8;
+typedef uint16_t UINT16;
+typedef uint32_t UINT32;
+typedef uint64_t UINT64;
+*/
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;//
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef signed int INT32;
+typedef unsigned long long UINT64;
+
+#define TRUE  1
+#define FALSE 0
+typedef unsigned char BOOLEAN;
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+//porting.h
+#ifndef CONST
+#define CONST const
+#endif
+#ifndef STATIC
+#define STATIC static
+#endif
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#endif
diff --git a/src/northbridge/amd/cimx/rd890/chip.h b/src/northbridge/amd/cimx/rd890/chip.h
new file mode 100644
index 0000000..c2f985b
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/chip.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _CIMX_RD890_CHIP_H_
+#define _CIMX_RD890_CHIP_H_
+
+extern struct chip_operations northbridge_amd_cimx_rd890_ops;
+
+/**
+ * RD890 specific device configuration
+ */
+struct northbridge_amd_cimx_rd890_config
+{
+	u8 gpp1_configuration;
+	u8 gpp2_configuration;
+	u8 gpp3a_configuration;
+	u16 port_enable;
+};
+
+#endif /* _CIMX_RD890_CHIP_H_ */
+
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c
new file mode 100644
index 0000000..8008223
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/early.c
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "NbPlatform.h"
+#include "rd890_cfg.h"
+#include "nb_cimx.h"
+
+
+/**
+ * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
+ *
+ * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+ * Disable all Pcie Bridges to work around It.
+ */
+void sr56x0_rd890_disable_pcie_bridge(void)
+{
+	u32			nb_dev;
+	u32			mask;
+	u32			val;
+	AMD_NB_CONFIG_BLOCK	cfg_block;
+	AMD_NB_CONFIG_BLOCK	*cfg_ptr = &cfg_block;
+	AMD_NB_CONFIG		*nb_cfg  = &(cfg_block.Northbridges[0]);
+
+        nb_cfg->ConfigPtr = &cfg_ptr;
+	nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+	val = (1 << 2) | (1 << 3); /*GPP1*/
+	val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
+	val |= (1 << 18) | (1 << 19); /*GPP2*/
+	val |= (1 << 20); /*GPP3b*/
+	mask = ~val;
+	LibNbPciIndexRMW(nb_dev | NB_MISC_INDEX, NB_MISC_REG0C,
+			AccessS3SaveWidth32,
+			mask,
+			val,
+			nb_cfg);
+}
+
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ *  wrapper of AmdPowerOnResetInit entry point.
+ */
+void nb_Poweron_Init(void)
+{
+	NB_CONFIG nb_cfg[MAX_NB_COUNT];
+	HT_CONFIG ht_cfg[MAX_NB_COUNT];
+	PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
+	AMD_NB_CONFIG_BLOCK gConfig;
+	AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
+	AGESA_STATUS status;
+
+	printk(BIOS_DEBUG, "cimx/rd890 early.c %s() Start\n", __func__);
+	CIMX_INIT_TRACE();
+	CIMX_TRACE((BIOS_DEBUG, "NbPowerOnResetInit entry\n"));
+	rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
+
+	if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
+		ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetNbPorConfig, 0, &gConfig);
+	}
+
+	status = AmdPowerOnResetInit(&gConfig);
+	printk(BIOS_DEBUG, "cimx/rd890 early.c %s() End. return status=%x\n", __func__, status);
+}
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ *  wrapper of AmdHtInit entry point.
+ */
+void nb_Ht_Init(void)
+{
+	AGESA_STATUS status;
+	NB_CONFIG nb_cfg[MAX_NB_COUNT];
+	HT_CONFIG ht_cfg[MAX_NB_COUNT];
+	PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
+	AMD_NB_CONFIG_BLOCK gConfig;
+	AMD_NB_CONFIG_BLOCK *ConfigPtr = &gConfig;
+	u32 i;
+
+	rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
+
+	//Initialize HT structure
+	LibSystemApiCall(AmdHtInitializer, &gConfig);
+	for (i = 0; i < MAX_NB_COUNT; i ++) {
+		if (ConfigPtr->StandardHeader.CalloutPtr != NULL) {
+			ConfigPtr->StandardHeader.CalloutPtr(CB_AmdSetHtConfig, 0, (VOID*)&(gConfig.Northbridges[i]));
+		}
+	}
+
+	status = LibSystemApiCall(AmdHtInit, &gConfig);
+	printk(BIOS_DEBUG, "AmdHtInit status: %x\n", status);
+}
+
+void nb_S3_Init(void)
+{
+	//TODO
+}
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
new file mode 100644
index 0000000..62a842a
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -0,0 +1,269 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "NbPlatform.h"
+#include "nb_cimx.h"
+#include "rd890_cfg.h"
+
+
+/**
+ * Global RD890 CIMX Configuration structure
+ */
+static NB_CONFIG nb_cfg[MAX_NB_COUNT];
+static HT_CONFIG ht_cfg[MAX_NB_COUNT];
+static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT];
+static AMD_NB_CONFIG_BLOCK gConfig;
+
+
+/**
+ * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
+ * After this call EP are fully operational on particular NB
+ */
+void nb_Pcie_Early_Init(void)
+{
+	LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig);
+}
+
+void nb_Pcie_Late_Init(void)
+{
+	LibSystemApiCall(AmdPcieLateInit, &gConfig);
+}
+
+void nb_Early_Post_Init(void)
+{
+	LibSystemApiCall(AmdEarlyPostInit, &gConfig);
+}
+
+void nb_Mid_Post_Init(void)
+{
+	LibSystemApiCall(AmdMidPostInit, &gConfig);
+}
+
+void nb_Late_Post_Init(void)
+{
+	LibSystemApiCall(AmdLatePostInit, &gConfig);
+}
+
+static void rd890_enable(device_t dev)
+{
+	u32 address = 0;
+	u32 mask;
+	u32 val;
+	u32 devfn;
+	u32 port;
+	AMD_NB_CONFIG *NbConfigPtr = NULL;
+
+	u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */
+	address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+	NbConfigPtr = &(gConfig.Northbridges[nb_index]);
+
+	devfn = dev->path.pci.devfn;
+	port = devfn >> 3;
+	printk(BIOS_INFO, "rd890_enable  ");
+	printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n",
+			0, (devfn >> 3), (devfn & 0x07), dev->enabled);
+	if (port != 0) {
+		if (dev->enabled) {
+			NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF;
+		} else {
+			NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON;
+		}
+	}
+
+	switch (port) {
+		case 0x0: /* Root Complex, and ClkConfig */
+
+			if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */
+				break;
+			}
+
+			/* CIMX configuration defualt initialize */
+			rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]);
+			if (gConfig.StandardHeader.CalloutPtr != NULL) {
+				/* NOTE: not use LibNbCallBack */
+				gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr);
+			}
+			/* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree
+			 * After this call EP are fully operational on particular NB
+			 */
+			nb_Pcie_Early_Init();
+			break;
+
+		case 0x2: /* Gpp1 Port0 */
+		case 0x3: /* Gpp1 Port1 */
+			mask = ~(1 << port);
+			val = (dev->enabled ? 0 : 1) << port;
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+			break;
+
+		case 0x4: /* Gpp3a Port0 */
+		case 0x5: /* Gpp3a Port1 */
+		case 0x6: /* Gpp3a Port2 */
+		case 0x7: /* Gpp3a Port3 */
+			mask = ~(1 << port);
+			val = (dev->enabled ? 0 : 1) << port;
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+			break;
+
+		case 0x8: /* SB ALink */
+			mask = ~(1 << 6);
+			val = (dev->enabled ? 1 : 0) << 6;
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+			break;
+
+		case 0x9: /* Gpp3a Port4 */
+		case 0xa: /* Gpp3a Port5 */
+			mask = ~(1 << (7 + port));
+			val = (dev->enabled ? 0 : 1) << (7 + port);
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+			break;
+
+		case 0xb: /* Gpp2 Port0 */
+		case 0xc: /* Gpp2 Port1 */
+			mask = ~(1 << (7 + port));
+			val = (dev->enabled ? 0 : 1) << (7 + port);
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+			break;
+
+		case 0xd: /* Gpp3b */
+			mask = ~(1 << (7 + port));
+			val = (dev->enabled ? 0 : 1) << (7 + port);
+			LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr);
+
+			/* Init NB at Early Post */
+			if (gConfig.StandardHeader.CalloutPtr != NULL) {
+				gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr);
+			}
+			nb_Early_Post_Init();//
+			if (gConfig.StandardHeader.CalloutPtr != NULL) {
+				gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr);
+			}
+			nb_Mid_Post_Init();
+			nb_Pcie_Late_Init();
+			if (gConfig.StandardHeader.CalloutPtr != NULL) {
+				gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr);
+			}
+			nb_Late_Post_Init();
+			break;
+
+		default:
+			printk(BIOS_INFO, "Buggy Device Tree\n");
+			break;
+	}
+}
+
+struct chip_operations northbridge_amd_cimx_rd890_ops = {
+	CHIP_NAME("ATI rd890")
+	.enable_dev = rd890_enable,
+};
+
+
+static void ioapic_init(struct device *dev)
+{
+	u32 ioapic_base;
+
+	pci_write_config32(dev, 0xF8, 0x1);
+	ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+	setup_ioapic(ioapic_base, 1);
+}
+
+static void rd890_read_resource(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+	/* rpr6.2.(1). Write the Base Address Register (BAR) */
+	pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+	pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */
+
+	compact_resources(dev);
+}
+
+/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
+static void rd890_set_resources(struct device *dev)
+{
+	pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */
+	pci_dev_set_resources(dev);
+}
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static struct device_operations ht_ops = {
+	.read_resources = rd890_read_resource,
+	.set_resources = rd890_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = ioapic_init,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver ht_driver_sr5690 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_SR5690_HT,
+};
+
+static const struct pci_driver ht_driver_sr5670 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_SR5670_HT,
+};
+
+static const struct pci_driver ht_driver_sr5650 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_SR5650_HT,
+};
+
+static const struct pci_driver ht_driver_rd890tv __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_RD890TV_HT,
+};
+
+static const struct pci_driver ht_driver_rx780 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_RX780_HT,
+};
+
+static const struct pci_driver ht_driver_rd780 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_RD780_HT,
+};
+
+static const struct pci_driver ht_driver_rd890 __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_RD890_HT,
+};
+
+static const struct pci_driver ht_driver_990fx __pci_driver = {
+	.ops = &ht_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_AMD_990FX_HT,
+};
diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h
new file mode 100644
index 0000000..a6f77db
--- /dev/null
+++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _NB_CIMX_H_
+#define _NB_CIMX_H_
+
+/**
+ * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
+ *
+ * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+ * Disable all Pcie Bridges to work around It.
+ */
+void sr56x0_rd890_disable_pcie_bridge(void);
+
+/**
+ * Northbridge CIMX entries point
+ */
+void nb_Poweron_Init(void);
+void nb_Ht_Init(void);
+void nb_S3_Init(void);
+void nb_Early_Post_Init(void);
+void nb_Mid_Post_Init(void);
+void nb_Late_Post_Init(void);
+void nb_Pcie_Early_Init(void);
+void nb_Pcie_Late_Init(void);
+
+#endif//_RD890_EARLY_H_
+


From gerrit at coreboot.org  Fri Jan 20 06:44:46 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:46 +0100
Subject: [coreboot] New patch to review for coreboot: 7a4a599 SB700
	southbridge: AMD SB700/SP5100 southbridge CIMX code
References: <I0955abf7f48a79483f624b46a61b22711315f888+0@gerrit.coreboot.org>
Message-ID: <I0955abf7f48a79483f624b46a61b22711315f888+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/560

-gerrit

commit 7a4a5996620bed4f40efd8eb2e0785b7e20d3319
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:10 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
    
    Support AMD SB700 and SP5100 chipsets.
    
    Change-Id: I0955abf7f48a79483f624b46a61b22711315f888
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/cimx/Makefile.inc       |    1 +
 src/vendorcode/amd/cimx/sb700/ACPILIB.c    |  120 ++++
 src/vendorcode/amd/cimx/sb700/ACPILIB.h    |   61 ++
 src/vendorcode/amd/cimx/sb700/AMDLIB.c     |  434 ++++++++++++
 src/vendorcode/amd/cimx/sb700/AMDSBLIB.c   |  276 ++++++++
 src/vendorcode/amd/cimx/sb700/AZALIA.c     |  304 ++++++++
 src/vendorcode/amd/cimx/sb700/DEBUG.c      |  169 +++++
 src/vendorcode/amd/cimx/sb700/DISPATCHER.c |  208 ++++++
 src/vendorcode/amd/cimx/sb700/EC.c         |  132 ++++
 src/vendorcode/amd/cimx/sb700/FLASH.c      |   58 ++
 src/vendorcode/amd/cimx/sb700/LEGACY.c     |   38 +
 src/vendorcode/amd/cimx/sb700/Makefile.inc |   77 ++
 src/vendorcode/amd/cimx/sb700/OEM.h        |   87 +++
 src/vendorcode/amd/cimx/sb700/SATA.c       |  453 ++++++++++++
 src/vendorcode/amd/cimx/sb700/SB700.h      | 1028 ++++++++++++++++++++++++++++
 src/vendorcode/amd/cimx/sb700/SBCMN.c      |  572 ++++++++++++++++
 src/vendorcode/amd/cimx/sb700/SBCMNLIB.c   |  108 +++
 src/vendorcode/amd/cimx/sb700/SBCMNLIB.h   |   89 +++
 src/vendorcode/amd/cimx/sb700/SBDEF.h      |  166 +++++
 src/vendorcode/amd/cimx/sb700/SBMAIN.c     |  289 ++++++++
 src/vendorcode/amd/cimx/sb700/SBPOR.c      |  441 ++++++++++++
 src/vendorcode/amd/cimx/sb700/SBTYPE.h     |  249 +++++++
 src/vendorcode/amd/cimx/sb700/SMM.c        |   91 +++
 src/vendorcode/amd/cimx/sb700/USB.c        |  187 +++++
 src/vendorcode/amd/cimx/sb700/sbAMDLIB.h   |  196 ++++++
 25 files changed, 5834 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc
index 3622312..7051ea2 100644
--- a/src/vendorcode/amd/cimx/Makefile.inc
+++ b/src/vendorcode/amd/cimx/Makefile.inc
@@ -1,3 +1,4 @@
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.c b/src/vendorcode/amd/cimx/sb700/ACPILIB.c
new file mode 100644
index 0000000..807b166
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.c
@@ -0,0 +1,120 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+/*++
+
+Routine Description:
+
+  Locate ACPI table
+
+Arguments:
+
+  Signature - table signature
+
+Returns:
+
+  pointer to ACPI table
+
+--*/
+void* ACPI_LocateTable(
+	UINT32 Signature
+)
+{
+	UINT32	i;
+	UINT32* RsdPtr = (UINT32*)0xe0000;
+	UINT32* Rsdt = NULL;
+	DESCRIPTION_HEADER* CurrentTable;
+	do{
+//		if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){
+		if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){
+			Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress;
+			break;
+		}
+		RsdPtr+=4;
+	}while (RsdPtr <= (UINT32*)0xffff0);
+	if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){
+		for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){
+			CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4);
+			if (CurrentTable->Signature == Signature) return CurrentTable;
+		}
+	}
+	return NULL;
+}
+
+/*++
+
+Routine Description:
+
+  Update table checksum
+
+Arguments:
+
+  TablePtr - table pointer
+
+Returns:
+
+  none
+
+--*/
+void  ACPI_SetTableChecksum(
+	void* TablePtr
+)
+{
+	UINT8 Checksum = 0;
+	((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+	Checksum = ACPI_GetTableChecksum(TablePtr);
+	((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum;
+}
+
+/*++
+
+Routine Description:
+
+  Get table checksum
+
+Arguments:
+
+  TablePtr - table pointer
+
+Returns:
+
+  none
+
+--*/
+UINT8  ACPI_GetTableChecksum(
+	void* TablePtr
+)
+{
+	return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/ACPILIB.h b/src/vendorcode/amd/cimx/sb700/ACPILIB.h
new file mode 100644
index 0000000..5f2734f
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/ACPILIB.h
@@ -0,0 +1,61 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_ACPILIB_H_
+#define _AMD_ACPILIB_H_
+
+typedef struct _RSDP{
+	UINT64	Signature;
+	UINT8	Checksum;
+	UINT8	OEMID[6];
+	UINT8	Revision;
+	UINT32	RsdtAddress;
+	UINT32	Length;
+	UINT64	XsdtAddress;
+	UINT8	ExtendedChecksum;
+	UINT8	Reserved[3];
+}RSDP;
+
+typedef struct _DESCRIPTION_HEADER{
+	UINT32	Signature;
+	UINT32	Length;
+	UINT8	Revision;
+	UINT8	Checksum;
+	UINT8	OEMID[6];
+	UINT8	OEMTableID[8];
+	UINT32	OEMRevision;
+	UINT32	CreatorID;
+	UINT32	CreatorRevision;
+}DESCRIPTION_HEADER;
+
+void* ACPI_LocateTable(UINT32 Signature);
+void  ACPI_SetTableChecksum(void* TablePtr);
+UINT8 ACPI_GetTableChecksum(void* TablePtr);
+
+#endif	//ifndef _AMD_ACPILIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/AMDLIB.c b/src/vendorcode/amd/cimx/sb700/AMDLIB.c
new file mode 100644
index 0000000..b233259
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AMDLIB.c
@@ -0,0 +1,434 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include "Platform.h"
+
+VOID
+ReadIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8:
+    *(UINT8*)Value = ReadIo8 (Address);
+    break;
+  case AccWidthUint16:
+    *(UINT16*)Value = ReadIo16 (Address);
+    break;
+  case AccWidthUint32:
+    *(UINT32*)Value = ReadIo32 (Address);
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+WriteIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  switch ( OpFlag ) {
+  case AccWidthUint8:
+    WriteIo8 (Address, *(UINT8*)Value);
+    break;
+  case AccWidthUint16:
+    WriteIo16 (Address, *(UINT16*)Value);
+    break;
+  case AccWidthUint32:
+    WriteIo32 (Address, *(UINT32*)Value);
+    break;
+  default:
+    break;
+  }
+}
+
+VOID
+RWIO (
+  IN       UINT16 Address,
+  IN       UINT8 OpFlag,
+  IN       UINT32 Mask,
+  IN       UINT32 Data
+  )
+{
+  UINT32 Result;
+  ReadIO (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WriteIO (Address, OpFlag, &Result);
+}
+
+
+VOID
+ReadPCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+
+  if ( (UINT16)Address < 0xff ) {
+    //Normal Config Access
+    UINT32 AddrCf8;
+    AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+    ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+  }
+}
+
+VOID
+WritePCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       VOID* Value
+  )
+{
+  OpFlag = OpFlag & 0x7f;
+  if ( (UINT16)Address < 0xff ) {
+    //Normal Config Access
+    UINT32 AddrCf8;
+    AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+    WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+    WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+  }
+}
+
+VOID
+RWPCI (
+  IN       UINT32 Address,
+  IN       UINT8 OpFlag,
+  IN       UINT32 Mask,
+  IN       UINT32 Data
+  )
+{
+  UINT32 Result;
+  Result = 0;
+  OpFlag = OpFlag & 0x7f;
+  ReadPCI (Address, OpFlag, &Result);
+  Result = (Result & Mask) | Data;
+  WritePCI (Address, OpFlag, &Result);
+}
+
+void
+ReadIndexPCI32	(
+UINT32	PciAddress,
+UINT32	IndexAddress,
+void*	Value
+)
+{
+	WritePCI(PciAddress,AccWidthUint32,&IndexAddress);
+	ReadPCI(PciAddress+4,AccWidthUint32,Value);
+}
+
+void
+WriteIndexPCI32	(
+UINT32	PciAddress,
+UINT32	IndexAddress,
+UINT8	OpFlag,
+void*	Value
+)
+{
+
+	WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress);
+	WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value);
+}
+
+void
+RWIndexPCI32	(
+UINT32	PciAddress,
+UINT32	IndexAddress,
+UINT8	OpFlag,
+UINT32	Mask,
+UINT32	Data
+)
+{
+	UINT32 Result;
+	ReadIndexPCI32(PciAddress,IndexAddress,&Result);
+	Result = (Result & Mask)| Data;
+	WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result);
+
+}
+
+void
+ReadMEM	(
+UINT32	Address,
+UINT8	OpFlag,
+void*	Value
+)
+{
+	OpFlag = OpFlag & 0x7f;
+	switch	(OpFlag){
+		case	AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break;
+		case	AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break;
+		case	AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break;
+	}
+}
+
+void
+WriteMEM	(
+UINT32	Address,
+UINT8	OpFlag,
+void*	Value
+)
+{
+	OpFlag = OpFlag & 0x7f;
+	switch	(OpFlag){
+		case	AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break;
+		case	AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break;
+		case	AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break;
+	}
+}
+
+void
+RWMEM	(
+UINT32	Address,
+UINT8	OpFlag,
+UINT32	Mask,
+UINT32	Data
+)
+{
+	UINT32 Result;
+	ReadMEM(Address,OpFlag,&Result);
+	Result = (Result & Mask)| Data;
+	WriteMEM(Address,OpFlag,&Result);
+}
+
+
+void
+RWMSR(
+UINT32	Address,
+UINT64	Mask,
+UINT64	Value
+)
+{
+	MsrWrite(Address,(MsrRead(Address)& Mask)|Value);
+}
+
+UINT32
+IsFamily10()
+{
+	CPUID_DATA Cpuid;
+	CpuidRead(0x1,(CPUID_DATA *)&Cpuid);
+
+	return Cpuid.REG_EAX & 0xff00000;
+}
+
+
+UINT8 GetNumberOfCpuCores(void)
+{
+	UINT8 Result=1;
+        Result=ReadNumberOfCpuCores();
+	return Result;
+}
+
+
+void
+Stall(
+UINT32	uSec
+)
+{
+	UINT16	timerAddr;
+	UINT32	startTime, elapsedTime;
+	ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr);
+
+	if (timerAddr ==0){
+		uSec = uSec/2;
+		while	(uSec!=0){
+		ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime));
+		uSec--;
+		}
+	}
+	else{
+		ReadIO(timerAddr, AccWidthUint32,&startTime);
+		while (1){
+			ReadIO(timerAddr, AccWidthUint32,&elapsedTime);
+			if (elapsedTime < startTime)
+				elapsedTime = elapsedTime+0xFFFFFFFF-startTime;
+			else
+				elapsedTime = elapsedTime-startTime;
+			if ((elapsedTime*28/100)>uSec)
+				break;
+		}
+	}
+}
+
+
+void
+Reset(
+)
+{
+	RWIO(0xcf9,AccWidthUint8,0x0,0x06);
+}
+
+
+CIM_STATUS
+RWSMBUSBlock(
+UINT8 Controller,
+UINT8 Address,
+UINT8 Offset,
+UINT8  BufferSize,
+UINT8* BufferPrt
+)
+{
+	UINT16 SmbusPort;
+	UINT8  i;
+	UINT8  Status;
+	ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort);
+	SmbusPort &= 0xfffe;
+	RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff);
+	RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address);
+	RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset);
+	RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14);
+	RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize);
+	if(!(Address & 0x1)){
+		for (i = 0 ;i < BufferSize;i++){
+			WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+		}
+	}
+	RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54);
+	do{
+		ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+		if (Status & 0x1C) return CIM_ERROR;
+		if (Status & 0x02) break;
+	}while(!(Status & 0x1));
+
+	do{
+		ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+	}while(Status & 0x1);
+
+	if(Address & 0x1){
+		for (i = 0 ;i < BufferSize;i++){
+			ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+		}
+	}
+	return CIM_SUCCESS;
+}
+
+
+
+void outPort80(UINT32 pcode)
+{
+	WriteIO(0x80, AccWidthUint8, &pcode);
+	return;
+}
+
+
+UINT8
+GetByteSum(
+	void*   pData,
+	UINT32	Length
+)
+{
+	UINT32	i;
+	UINT8 Checksum = 0;
+	for (i = 0;i < Length;i++){
+		Checksum += *((UINT8*)pData+i);
+	}
+	return Checksum;
+}
+
+
+UINT32
+readAlink(
+	UINT32	Index
+){
+	UINT32	Data;
+	WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+	ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+	//Clear Index
+	Index=0;
+	WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+	return Data;
+}
+
+
+void
+writeAlink(
+	UINT32	Index,
+	UINT32	Data
+){
+	WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+	WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+	//Clear Index
+	Index=0;
+	WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+
+}
+
+
+/**
+ *
+ * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server)
+ *
+ * A SP5100 is determined when both following two items are true:
+ *    1) Revision >= A14;
+ *    2) A server north bridge chipset is detected;
+ *
+ * A list of server north bridge chipset:
+ *
+ *      Family    DeviceID
+ *     ----------------------
+ *      SR5690     0x5A10
+ *      SR5670     0x5A12
+ *      SR5650     0x5A13
+ *
+ */
+UINT8
+IsServer (void){
+  UINT16     DevID;
+
+  if (getRevisionID () < SB700_A14) {
+    return 0;
+  }
+  ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID);
+  return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0;
+}
+
+/**
+ *
+ * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge.
+ *
+ */
+UINT8
+IsLs2Mode (void)
+{
+  UINT32     HT3LinkTraining0;
+
+  ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0);
+  return ( HT3LinkTraining0 & 0x100 )? 1: 0;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c
new file mode 100644
index 0000000..bf4f06a
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AMDSBLIB.c
@@ -0,0 +1,276 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+void
+ReadPMIO        (
+UINT8   Address,
+UINT8   OpFlag,
+void* Value
+)
+{
+        UINT8   i;
+
+        OpFlag = OpFlag & 0x7f;
+        if (OpFlag == 0x02) OpFlag = 0x03;
+        for (i=0;i<=OpFlag;i++){
+                WriteIO(0xCD6, AccWidthUint8, &Address);                // SB_IOMAP_REGCD6
+                Address++;
+                ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i);                 // SB_IOMAP_REGCD7
+        }
+}
+
+
+void
+WritePMIO       (
+UINT8   Address,
+UINT8   OpFlag,
+void* Value
+)
+{
+        UINT8   i;
+
+        OpFlag = OpFlag & 0x7f;
+        if (OpFlag == 0x02) OpFlag = 0x03;
+        for (i=0;i<=OpFlag;i++){
+                WriteIO(0xCD6, AccWidthUint8, &Address);                // SB_IOMAP_REGCD6
+                Address++;
+                WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i);                        // SB_IOMAP_REGCD7
+        }
+}
+
+
+void
+RWPMIO  (
+UINT8 Address,
+UINT8   OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+        UINT32 Result;
+
+        OpFlag = OpFlag & 0x7f;
+        ReadPMIO(Address,OpFlag,&Result);
+        Result = (Result & AndMask)| OrMask;
+        WritePMIO(Address,OpFlag,&Result);
+}
+
+
+void
+ReadPMIO2       (
+UINT8   Address,
+UINT8   OpFlag,
+void* Value
+)
+{
+        UINT8   i;
+
+        OpFlag = OpFlag & 0x7f;
+        if (OpFlag == 0x02) OpFlag = 0x03;
+        for (i=0;i<=OpFlag;i++){
+                WriteIO(0xCD0, AccWidthUint8, &Address);                // SB_IOMAP_REGCD0
+                Address++;
+                ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i);                 // SB_IOMAP_REGCD1
+        }
+}
+
+
+void
+WritePMIO2      (
+UINT8   Address,
+UINT8   OpFlag,
+void* Value
+)
+{
+        UINT8   i;
+
+        OpFlag = OpFlag & 0x7f;
+        if (OpFlag == 0x02) OpFlag = 0x03;
+        for (i=0;i<=OpFlag;i++){
+                WriteIO(0xCD0, AccWidthUint8, &Address);                // SB_IOMAP_REGCD0
+                Address++;
+                WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i);                        // SB_IOMAP_REGCD1
+        }
+}
+
+
+void
+RWPMIO2 (
+UINT8 Address,
+UINT8   OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+        UINT32 Result;
+
+        OpFlag = OpFlag & 0x7f;
+        ReadPMIO2(Address,OpFlag,&Result);
+        Result = (Result & AndMask)| OrMask;
+        WritePMIO2(Address,OpFlag,&Result);
+}
+
+
+void
+EnterEcConfig()
+{
+        UINT16  dwEcIndexPort;
+
+        ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+        dwEcIndexPort &= ~(UINT16)(BIT0);
+        RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
+}
+
+void
+ExitEcConfig()
+{
+        UINT16  dwEcIndexPort;
+
+        ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+        dwEcIndexPort &= ~(UINT16)(BIT0);
+        RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
+}
+
+
+void
+ReadEC8 (
+UINT8 Address,
+UINT8* Value
+)
+{
+        UINT16  dwEcIndexPort;
+
+        ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+        dwEcIndexPort &= ~(UINT16)(BIT0);
+        WriteIO(dwEcIndexPort, AccWidthUint8, &Address);                // SB_IOMAP_REGCD6
+        ReadIO(dwEcIndexPort+1, AccWidthUint8, Value);                  // SB_IOMAP_REGCD7
+}
+
+
+void
+WriteEC8        (
+UINT8 Address,
+UINT8* Value
+)
+{
+        UINT16  dwEcIndexPort;
+
+        ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+        dwEcIndexPort &= ~(UINT16)(BIT0);
+        WriteIO(dwEcIndexPort, AccWidthUint8, &Address);                // SB_IOMAP_REGCD6
+        WriteIO(dwEcIndexPort+1, AccWidthUint8, Value);                 // SB_IOMAP_REGCD7
+}
+
+
+void
+RWEC8   (
+UINT8 Address,
+UINT8 AndMask,
+UINT8 OrMask
+)
+{
+        UINT8 Result;
+        ReadEC8(Address,&Result);
+        Result = (Result & AndMask)| OrMask;
+        WriteEC8(Address, &Result);
+}
+
+
+void
+programPciByteTable     (
+REG8MASK* pPciByteTable,
+UINT16 dwTableSize
+)
+{
+        UINT8   i, dbBusNo, dbDevFnNo;
+        UINT32  ddBDFR;
+
+        dbBusNo = pPciByteTable->bRegIndex;
+        dbDevFnNo = pPciByteTable->bANDMask;
+        pPciByteTable++;
+        for (i = 1; i < dwTableSize; i++){
+                if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){
+                        pPciByteTable++;
+                        dbBusNo = pPciByteTable->bRegIndex;
+                        dbDevFnNo = pPciByteTable->bANDMask;
+                }
+                else{
+                        ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
+                        TRACE((DMSG_SB_TRACE, "PFA=%X  AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
+                        RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
+                        pPciByteTable++;
+                }
+        }
+}
+
+
+void
+programPmioByteTable    (
+REG8MASK* pPmioByteTable,
+UINT16 dwTableSize
+)
+{
+        UINT8   i;
+        for (i = 0; i < dwTableSize; i++){
+                TRACE((DMSG_SB_TRACE, "PMIO Reg = %X   AndMask = %X  OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask));
+                RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask);
+                pPmioByteTable++;
+        }
+}
+
+
+UINT8
+getClockMode    (
+void
+)
+{
+        UINT8 dbTemp=0;
+
+        RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+        ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp);
+        return(dbTemp&BIT4);
+}
+
+
+UINT16
+readStrapStatus (
+void
+)
+{
+        UINT16 dwTemp=0;
+
+        RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+        ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp);
+        return(dwTemp);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/AZALIA.c b/src/vendorcode/amd/cimx/sb700/AZALIA.c
new file mode 100644
index 0000000..cc72858
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/AZALIA.c
@@ -0,0 +1,304 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include	"Platform.h"
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum);
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0);
+
+//Pin Config for ALC880, ALC882 and ALC883:
+CODECENTRY AzaliaCodecAlc882Table[] = {
+	{0x14, 0x01014010},
+	{0x15, 0x01011012},
+	{0x16, 0x01016011},
+	{0x17, 0x01012014},
+	{0x18, 0x01A19030},
+	{0x19, 0x411111F0},
+	{0x1a, 0x01813080},
+	{0x1b, 0x411111F0},
+	{0x1C, 0x411111F0},
+	{0x1d, 0x411111F0},
+	{0x1e, 0x01441150},
+	{0x1f, 0x01C46160},
+	{0xff, 0xffffffff}
+};
+
+
+//Pin Config for ALC262
+CODECENTRY AzaliaCodecAlc262Table[] = {
+	  {0x14, 0x01014010},
+	  {0x15, 0x411111F0},
+	  {0x16, 0x411111F0},
+//	  {0x17, 0x01012014},
+	  {0x18, 0x01A19830},
+	  {0x19, 0x02A19C40},
+	  {0x1a, 0x01813031},
+	  {0x1b, 0x02014C20},
+	  {0x1c, 0x411111F0},
+	  {0x1d, 0x411111F0},
+	  {0x1e, 0x0144111E},
+	  {0x1f, 0x01C46150},
+	  {0xff, 0xffffffff}
+};
+
+//Pin Config for  ALC0861:
+CODECENTRY AzaliaCodecAlc861Table[] = {
+	  {0x01, 0x8086C601},
+	  {0x0B, 0x01014110},
+	  {0x0C, 0x01813140},
+	  {0x0D, 0x01A19941},
+	  {0x0E, 0x411111F0},
+	  {0x0F, 0x02214420},
+	  {0x10, 0x02A1994E},
+	  {0x11, 0x99330142},
+	  {0x12, 0x01451130},
+	  {0x1F, 0x411111F0},
+	  {0x20, 0x411111F0},
+	  {0x23, 0x411111F0},
+	  {0xff, 0xffffffff}
+};
+
+//Pin Config for  ADI1984:
+CODECENTRY AzaliaCodecAd1984Table[] = {
+	  {0x11, 0x0221401F},
+	  {0x12, 0x90170110},
+	  {0x13, 0x511301F0},
+	  {0x14, 0x02A15020},
+	  {0x15, 0x50A301F0},
+	  {0x16, 0x593301F0},
+	  {0x17, 0x55A601F0},
+	  {0x18, 0x55A601F0},
+	  {0x1A, 0x91F311F0},
+	  {0x1B, 0x014511A0},
+	  {0x1C, 0x599301F0},
+	  {0xff, 0xffffffff}
+};
+
+
+CODECENTRY FrontPanelAzaliaCodecTableList[] = {
+	  {0x19, 0x02A19040},
+	  {0x1b, 0x02214020},
+	  {0xff, 0xffffffff}
+};
+
+
+CODECTBLLIST azaliaCodecTableList[] = {
+	 {0x010ec0880, &AzaliaCodecAlc882Table[0]},
+	 {0x010ec0882, &AzaliaCodecAlc882Table[0]},
+	 {0x010ec0883, &AzaliaCodecAlc882Table[0]},
+	 {0x010ec0885, &AzaliaCodecAlc882Table[0]},
+	 {0x010ec0262, &AzaliaCodecAlc262Table[0]},
+	 {0x010ec0861, &AzaliaCodecAlc861Table[0]},
+	 {0x011d41984, &AzaliaCodecAd1984Table[0]},
+	 {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF}
+};
+
+
+/*-------------------------------------------------------------------------------
+; Procedure:	azaliaInitAfterPciEnum
+;
+; Description:	This routine detects Azalia and, if present, initializes Azalia
+;		This routine is called from atiSbAfterPciInit
+;
+;
+; Exit:		None
+;
+; Modified:	None
+;
+;-----------------------------------------------------------------------------
+*/
+void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
+	UINT8	i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0;
+	UINT16	dwTempVariable = 0;
+	UINT32	ddBAR0, ddTempVariable = 0;
+
+	if	(pConfig->AzaliaController == 1) return;
+
+	if	(pConfig->AzaliaController != 1){
+		RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1);
+		ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
+
+		if (ddBAR0 != 0){		//Keep the flag as disabled if BAR is 0 or all "F"s.
+			if (ddBAR0 != 0xFFFFFFFF){
+				ddBAR0 &=  ~(0x03FFF);
+				dbEnableAzalia = 1;
+				TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+			}
+		}
+	}
+
+	if (dbEnableAzalia){		//if Azalia is enabled
+		//Get SDIN Configuration
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable);
+		ddTempVariable |= (pConfig->AzaliaSdin3 << 6);
+		ddTempVariable |= (pConfig->AzaliaSdin2 << 4);
+		ddTempVariable |= (pConfig->AzaliaSdin1 << 2);
+		ddTempVariable |= pConfig->AzaliaSdin0;
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF));
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+
+		i=11;
+		do{
+			ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+			dbTempVariable |= BIT0;
+			WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+			Stall(1000);
+			ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+			i--;
+		}	while ( (!(dbTempVariable & BIT0)) && (i > 0) );
+
+		if (i==0){
+			TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
+			return;
+		}
+
+		Stall(1000);
+		ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
+		if (dwTempVariable & 0x0F){
+			TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n"));
+			//atleast one azalia codec found
+			ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting);
+			do{
+				if	( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) )
+					configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum);
+				dbPinRouting >>= 2;
+				dbChannelNum++;
+			}	while (dbChannelNum != 4);
+		}
+		else{
+			TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+			//No Azalia codec found
+			if	(pConfig->AzaliaController != 2)
+				dbEnableAzalia = 0;		//set flag to disable Azalia
+		}
+	}
+
+	if (dbEnableAzalia){
+		//redo clear reset
+		do{
+			dwTempVariable = 0;
+			WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
+			ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+			dbTempVariable &= ~(UINT8)(BIT0);
+			WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+			ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+		}	while (dbTempVariable & BIT0);
+
+		if	(pConfig->AzaliaSnoop == 1)
+			RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+	}
+	else{
+		//disable Azalia controller
+		RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
+		RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
+	}
+}
+
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){
+	UINT32	ddTempVariable, ddChannelNum;
+	CODECTBLLIST*	ptempAzaliaOemCodecTablePtr;
+	CODECENTRY*	tempAzaliaCodecEntryPtr;
+
+	if ((pConfig->AzaliaPinCfg) != 1)
+		return;
+
+	ddChannelNum = dbChannelNum << 28;
+	ddTempVariable = 0xF0000;
+	ddTempVariable |= ddChannelNum;
+	WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+	Stall(60);
+	ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+	if	( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+		ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]);
+	else
+		ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr;
+
+	TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr));
+
+	while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+		if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable)
+			break;
+		else
+			++ptempAzaliaOemCodecTablePtr;
+	}
+
+	if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+		TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+		tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
+		TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr));
+
+		if	( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+			tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr);
+
+		configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+		if	 (pConfig->AzaliaFrontPanel != 1){
+			if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){
+				if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF))
+					tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]);
+				else
+					tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr;
+				configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+			}
+		}
+	}
+}
+
+
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){
+	UINT8 dbtemp1,dbtemp2, i;
+	UINT32 ddtemp=0,ddtemp2=0;
+
+	while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){
+		dbtemp1=0x20;
+		if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
+			dbtemp1=0x24;
+		ddtemp =  tempAzaliaCodecEntryPtr->Nid;
+		ddtemp &= 0xff;
+		ddtemp <<= 20;
+		ddtemp |= ddChannelNum;
+		ddtemp |= (0x700 << 8);
+		for(i=4; i>0; i--){
+			do{
+				ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
+			} while (ddtemp2 & BIT0);
+			dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
+			ddtemp =  (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
+			WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
+			Stall(60);
+		}
+		++tempAzaliaCodecEntryPtr;
+	}
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/DEBUG.c b/src/vendorcode/amd/cimx/sb700/DEBUG.c
new file mode 100644
index 0000000..f40682e
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/DEBUG.c
@@ -0,0 +1,169 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#define	COM_BASE_ADDRESS	0x3f8
+#define DIVISOR			115200
+#define LF			0x0a
+#define CR			0x0d
+
+
+#ifdef CIM_DEBUG
+  #ifndef CIM_DEBUG_LEVEL
+  #define CIM_DEBUG_LEVEL       0xf
+#endif
+
+void
+TraceCode( UINT32 Level, UINT32 Code){
+
+	if (!(Level & CIM_DEBUG_LEVEL)){
+		return;
+	}
+#if CIM_DEBUG & 1
+	if	(Code != 0xFF){
+		WriteIO(0x80,AccWidthUint8,&Code);
+	}
+#endif
+
+}
+
+
+void
+TraceDebug( UINT32 Level, CHAR8 *Format, ...){
+	CHAR8	temp[16];
+	va_list	ArgList;
+
+	if (!(Level & CIM_DEBUG_LEVEL)){
+		return;
+	}
+
+#if CIM_DEBUG & 2
+	ArgList = va_start(ArgList,Format);
+	Format= (CHAR8*) FIXUP_PTR(Format);
+	while	(1){
+		if (*Format == 0) break;
+		if (*Format == '%'){
+			int Radix = 0;
+			if(*(Format+1)=='s'||*(Format+1)=='S'){
+				SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*)));
+				Format+=2;
+				continue;
+			}
+
+			if(*(Format+1)=='d'||*(Format+1)=='D'){
+				Radix = 10;
+			}
+		    if(*(Format+1)=='x'||*(Format+1)=='X'){
+				Radix = 16;
+			}
+			if	(Radix){
+				ItoA(va_arg(ArgList,int),Radix,temp);
+				SendStringPort(temp);
+				Format+=2;
+				continue;
+			}
+		}
+		SendBytePort(*Format);
+		if(*(Format)==0x0a) SendBytePort(0x0d);
+		Format++;
+	}
+	va_end(ArgList);
+#endif
+}
+
+
+void
+ItoA( UINT32 Value, int Radix, char* pstr)
+{
+	char* tsptr = pstr;
+	char* rsptr = pstr;
+	char  ch1,ch2;
+	unsigned int  Reminder;
+//Create String
+	do{
+		Reminder = Value%Radix;
+		Value = Value/Radix;
+		if (Reminder<0xa) *tsptr=Reminder+'0';
+		else *tsptr=Reminder-0xa+'a';
+		tsptr++;
+	} while(Value);
+//Reverse String
+	*tsptr = 0;
+	tsptr--;
+	while(tsptr>rsptr){
+		ch1	= *tsptr;
+		ch2 = *rsptr;
+		*rsptr = ch1;
+		*tsptr = ch2;
+		tsptr--;
+		rsptr++;
+	}
+}
+
+void
+InitSerialOut(){
+	UINT8	Data;
+	UINT16	Divisor;
+	Data = 0x87;
+	WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+	Divisor = 115200 / DIVISOR;
+	Data = Divisor & 0xFF;
+	WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+	Data = Divisor >> 8;
+	WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data);
+	Data = 0x07;
+	WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+}
+
+
+void
+SendStringPort(char* pstr){
+
+	while (*pstr!=0){
+		SendBytePort(*pstr);
+		pstr++;
+	}
+}
+
+void
+SendBytePort(UINT8 Data)
+{
+	int   Count = 80;
+	UINT8 Status;
+	do {
+		ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status);
+		if(Status == 0xff) break;
+	// Loop  port is ready
+	} while ( (Status & 0x20) == 0 && (--Count) != 0);
+	WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+}
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/DISPATCHER.c b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c
new file mode 100644
index 0000000..ae5f9b8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/DISPATCHER.c
@@ -0,0 +1,208 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+void DispatcherEntry(void *pConfig){
+
+#ifdef  B1_IMAGE
+        void    *pB2ImagePtr = NULL;
+        CIM_IMAGE_ENTRY pB2ImageEntry;
+#endif
+
+//#if CIM_DEBUG
+//        InitSerialOut();
+//#endif
+
+        TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n"));
+
+#ifdef  B1_IMAGE
+        if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){
+                if (((STDCFG*)pConfig)->pB2ImageBase)
+                        pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase);
+                if (pB2ImagePtr == NULL)
+                        pB2ImagePtr = LocateImage('007S');
+                if (pB2ImagePtr!=NULL){
+                        TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n"));
+                        ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr;
+                        pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr);
+                        (*pB2ImageEntry)(pConfig);
+                        return;
+                }
+        }
+#endif
+        saveConfigPointer(pConfig);
+
+        if      (((STDCFG*)pConfig)->Func == SB_POWERON_INIT)
+                sbPowerOnInit((AMDSBCFG*)pConfig);
+
+#ifndef B1_IMAGE
+        if      (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT)
+                sbBeforePciInit((AMDSBCFG*)pConfig);
+        if      (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT)
+                sbAfterPciInit((AMDSBCFG*)pConfig);
+        if      (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT)
+                sbLatePost((AMDSBCFG*)pConfig);
+        if      (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT)
+                sbBeforePciRestoreInit((AMDSBCFG*)pConfig);
+        if      (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT)
+                sbAfterPciRestoreInit((AMDSBCFG*)pConfig);
+        if      (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE)
+        {
+                // sbSmmService((AMDSBCFG*)pConfig);
+        }
+        if      (((STDCFG*)pConfig)->Func == SB_SMM_ACPION)
+                sbSmmAcpiOn((AMDSBCFG*)pConfig);
+#endif
+        TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
+}
+
+
+void* LocateImage(UINT32 Signature){
+        void    *Result;
+        UINT8   *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1));
+        while   ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){
+                Result = CheckImage(Signature,(void*)ImagePtr);
+                if (Result != NULL)
+                        return Result;
+                ImagePtr -= IMAGE_ALIGN;
+        }
+        return NULL;
+}
+
+
+void* CheckImage(UINT32 Signature, void* ImagePtr){
+        UINT8   *TempImagePtr;
+        UINT8   Sum = 0;
+        UINT32  i;
+//        if      ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+        if      ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+                //GetImage Image size
+                TempImagePtr = (UINT8*)ImagePtr;
+                for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){
+                        Sum += *TempImagePtr;
+                        TempImagePtr++;
+                }
+                if      (Sum == 0)
+                        return ImagePtr;
+        }
+        return NULL;
+}
+
+
+UINT32 GetPciebase(){
+        AMDSBCFG* Result;
+        Result = getConfigPointer();
+        return Result->StdHeader.pPcieBase;
+}
+
+
+void saveConfigPointer(AMDSBCFG* pConfig){
+        UINT8   dbReg, i;
+        UINT32  ddValue;
+
+        ddValue =  ((UINT32) pConfig);
+        dbReg = SB_ECMOS_REG08;
+
+        for (i=0; i<=3; i++){
+                WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+                WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue);
+                ddValue >>= 8;
+                dbReg++;
+        }
+}
+
+
+AMDSBCFG* getConfigPointer(){
+        UINT8   dbReg, dbValue, i;
+        UINT32  ddValue=0;
+
+        dbReg = SB_ECMOS_REG08;
+        for (i=0; i<=3; i++){
+                WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+                ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue);
+                ddValue |= (dbValue<<(i*8));
+                dbReg++;
+        }
+        return( (AMDSBCFG*) ddValue);
+}
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+AmdSbDispatcher (
+  IN       VOID *pConfig
+  )
+{
+  AGESA_STATUS Status = AGESA_SUCCESS;
+
+  saveConfigPointer (pConfig);
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
+    sbPowerOnInit ((AMDSBCFG*) pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
+    sbBeforePciInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
+    sbAfterPciInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
+    sbLatePost ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
+    sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
+    sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
+    sbSmmService ((AMDSBCFG*)pConfig);
+  }
+
+  if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
+    sbSmmAcpiOn ((AMDSBCFG*)pConfig);
+  }
+
+  return Status;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/EC.c b/src/vendorcode/amd/cimx/sb700/EC.c
new file mode 100644
index 0000000..3ad15e1
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/EC.c
@@ -0,0 +1,132 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+#ifndef	NO_EC_SUPPORT
+
+REG8MASK sb710PorInitPciTable[] = {
+	// SMBUS Device(Bus 0, Dev 20, Func 0)
+	{0x00, SMBUS_BUS_DEV_FUN, 0},
+	{SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00},			//Make some hidden registers of smbus visible.
+	{SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D},
+	{SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 },
+	{SB_SMBUS_REGE1, 0xFF, BIT1},
+	{SB_SMBUS_REG43, 0xFF, BIT3},			//Make some hidden registers of smbus invisible.
+	{0xFF, 0xFF, 0xFF},
+
+	// LPC Device(Bus 0, Dev 20, Func 3)
+	{0x00, LPC_BUS_DEV_FUN, 0},
+	{SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2},
+	{0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sb710PorPmioInitTbl[]={
+	// index		andmask		ormask
+	{SB_PMIO_REGD7, 0xFF, BIT5},
+	{SB_PMIO_REGBB, 0xFF, BIT5},
+};
+
+
+void	ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){
+	UINT8	dbVar0, i=0;
+
+	if (!(isEcPresent()))
+		return;				//return if EC is not enabled
+
+	for(i=0;i<0xFF;i++){
+		ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0);
+		if ( dbVar0 & BIT7 ) break;	//break if EC is ready
+		Stall(500); //wait for EC to become ready
+	}
+
+	if (getRevisionID() >= SB700_A14){
+		programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) );
+		programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) );
+	}
+
+	RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2);	//Enable SPI Prefetch in EC
+
+	//Enable config mode
+	EnterEcConfig();
+
+	//Do settings for mailbox - logical device 0x09
+	RWEC8(0x07, 0x00, 0x09);					//switch to device 9 (Mailbox)
+	RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8));		//set MSB of Mailbox port
+	RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF));	//set LSB of Mailbox port
+	RWEC8(0x30, 0x00, 0x01);					//;Enable Mailbox Registers Interface, bit0=1
+
+	if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){
+		RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3);
+		//Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+		RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0);
+		//Disable LPC Decoding of port 60/64
+		RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0);
+		//Enable logical device 0x07 (Keyboard controller)
+		RWEC8(0x07, 0x00, 0x07);
+		RWEC8(0x30, 0x00, 0x01);
+	}
+
+	if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){
+		//Logical device 0x08
+		RWEC8(0x07, 0x00, 0x08);
+		RWEC8(0x60, 0x00, 0x00);
+		RWEC8(0x61, 0x00, 0x62);
+		RWEC8(0x30, 0x00, 0x01);				//;Enable Device 8
+	}
+	//Logical device 0x05
+	RWEC8(0x07, 0x00, 0x05);			//Select logical device 05, IR controller
+	RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8);
+	RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF));
+	RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq));			//Set IRQ to 05h
+	RWEC8(0x30, 0x00, 0x01);			//Enable logical device 5, IR controller
+
+	RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS
+	ExitEcConfig();
+}
+
+
+void	ecInitBeforePciEnum(AMDSBCFG* pConfig){
+	if (!(isEcPresent()))
+		return;				//return if EC is not enabled
+}
+
+
+void	ecInitLatePost(AMDSBCFG* pConfig){
+	if (!(isEcPresent()) )
+		return;				//return if EC is not enabled
+	//Enable config mode
+	EnterEcConfig();					//Enable config mode
+	//for future use
+	ExitEcConfig();
+}
+
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/FLASH.c b/src/vendorcode/amd/cimx/sb700/FLASH.c
new file mode 100644
index 0000000..0d84245
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/FLASH.c
@@ -0,0 +1,58 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+void fcInitBeforePciEnum(AMDSBCFG* pConfig){
+
+	TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n"));
+	RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00);
+
+	//Enable IDE and disable flash
+		//Enable IDE and disable flash
+	RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0);
+	RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0);	//Configure GPIO3 as IDE_RST# and release RST
+	if (pConfig->IdeController){
+		//Disabling IDE controller
+		RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+	}
+	else{
+		//Enable IDE controller
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+	}
+
+	//RPR 8.2	Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled
+	RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2);
+	//Slowdown the clock to FC if FC is not enabled, this is a power savings feature
+	RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4);
+	RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/LEGACY.c b/src/vendorcode/amd/cimx/sb700/LEGACY.c
new file mode 100644
index 0000000..c904d59
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/LEGACY.c
@@ -0,0 +1,38 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+UINT32 GetFixUp(){
+	 STDCFG* Result;
+	 Result = (STDCFG*) getConfigPointer();
+	 return Result->pImageBase;
+}
diff --git a/src/vendorcode/amd/cimx/sb700/Makefile.inc b/src/vendorcode/amd/cimx/sb700/Makefile.inc
new file mode 100644
index 0000000..8954133
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/Makefile.inc
@@ -0,0 +1,77 @@
+#*****************************************************************************
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in the
+#       documentation and/or other materials provided with the distribution.
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+#       its contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#*****************************************************************************
+
+# CIMX Root directory
+CIMX_ROOT = $(src)/vendorcode/amd/cimx
+
+SB_CIMX_INC  = -I$(src)/mainboard/$(MAINBOARDDIR)
+SB_CIMX_INC  += -I$(src)/southbridge/amd/cimx/sb700
+SB_CIMX_INC  += -I$(CIMX_ROOT)/sb700
+
+romstage-y += ACPILIB.c
+romstage-y += AMDLIB.c
+romstage-y += AMDSBLIB.c
+romstage-y += AZALIA.c
+romstage-y += DEBUG.c
+romstage-y += DISPATCHER.c
+romstage-y += EC.c
+romstage-y += FLASH.c
+romstage-y += SATA.c
+romstage-y += SBCMN.c
+romstage-y += SBCMNLIB.c
+romstage-y += SBMAIN.c
+romstage-y += SBPOR.c
+romstage-y += SMM.c
+romstage-y += USB.c
+
+ramstage-y += ACPILIB.c
+ramstage-y += AMDLIB.c
+ramstage-y += AMDSBLIB.c
+ramstage-y += AZALIA.c
+ramstage-y += DEBUG.c
+ramstage-y += DISPATCHER.c
+ramstage-y += EC.c
+ramstage-y += FLASH.c
+ramstage-y += SATA.c
+ramstage-y += SBCMN.c
+ramstage-y += SBCMNLIB.c
+ramstage-y += SBMAIN.c
+ramstage-y += SBPOR.c
+ramstage-y += SMM.c
+ramstage-y += USB.c
+ramstage-y += LEGACY.c
+
+SB_CIMX_CFLAGS =
+export CIMX_ROOT
+export SB_CIMX_INC
+export SB_CIMX_CFLAGS
+CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC)
+
+#######################################################################
+
diff --git a/src/vendorcode/amd/cimx/sb700/OEM.h b/src/vendorcode/amd/cimx/sb700/OEM.h
new file mode 100644
index 0000000..74604c0
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/OEM.h
@@ -0,0 +1,87 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+#ifndef _AMD_SB_CIMx_OEM_H_
+#define _AMD_SB_CIMx_OEM_H_
+
+#define BIOS_SIZE					0x04	//04 - 1MB
+#define	LEGACY_FREE					0x00
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef  MOVE_PCIEBAR_TO_F0000000
+  #define PCIEX_BASE_ADDRESS           0xF7000000
+#else
+  #define PCIEX_BASE_ADDRESS           0xE0000000
+#endif
+
+
+#define SMBUS0_BASE_ADDRESS			0xB00
+#define SMBUS1_BASE_ADDRESS			0xB20
+#define	SIO_PME_BASE_ADDRESS		0xE00
+#define	SPI_BASE_ADDRESS			0xFEC10000
+
+#define	WATCHDOG_TIMER_BASE_ADDRESS	0xFEC000F0			// Watchdog Timer Base Address
+#define	HPET_BASE_ADDRESS			0xFED00000			// HPET Base address
+
+#define PM1_EVT_BLK_ADDRESS			0x800				//	AcpiPm1EvtBlkAddr;
+#define	PM1_CNT_BLK_ADDRESS			0x804				//	AcpiPm1CntBlkAddr;
+#define	PM1_TMR_BLK_ADDRESS			0x808				//	AcpiPmTmrBlkAddr;
+#define	CPU_CNT_BLK_ADDRESS			0x810				//	CpuControlBlkAddr;
+#define	GPE0_BLK_ADDRESS			0x820				//  AcpiGpe0BlkAddr;
+#define	SMI_CMD_PORT				0xB0				//	SmiCmdPortAddr;
+#define ACPI_PMA_CNT_BLK_ADDRESS	0xFE00				//	AcpiPmaCntBlkAddr;
+
+#define	EC_LDN5_MAILBOX_ADDRESS		0x550
+#define	EC_LDN5_IRQ					0x05
+#define	EC_LDN9_MAILBOX_ADDRESS		0x3E
+
+#define	SATA_IDE_MODE_SSID			0x43901002
+#define SATA_RAID_MODE_SSID			0x43921002
+#define	SATA_RAID5_MODE_SSID		0x43931002
+#define SATA_AHCI_SSID				0x43911002
+#define OHCI0_SSID					0x43971002
+#define OHCI1_SSID					0x43981002
+#define EHCI0_SSID					0x43961002
+#define OHCI2_SSID					0x43971002
+#define OHCI3_SSID					0x43981002
+#define EHCI1_SSID					0x43961002
+#define OHCI4_SSID					0x43991002
+
+#define SMBUS_SSID					0x43851002
+#define IDE_SSID					0x439C1002
+#define AZALIA_SSID					0x43831002
+#define LPC_SSID					0x439D1002
+#define P2P_SSID					0x43841002
+
+#define RESERVED_VALUE				0x00
+
+#endif //ifndef _AMD_SB_CIMx_OEM_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SATA.c b/src/vendorcode/amd/cimx/sb700/SATA.c
new file mode 100644
index 0000000..09d4923
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SATA.c
@@ -0,0 +1,453 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+//Table for class code of SATA Controller in different modes
+UINT32 sataIfCodeTable[] = {
+	0x01018f00,	//sata class ID of IDE
+	0x01040000,	//sata class ID of RAID
+	0x01060100,	//sata class ID of AHCI
+	0x01018a00,	//sata class ID of Legacy IDE
+	0x01018f00,	//sata class ID of IDE to AHCI mode
+	0x01060100,	//sata class ID of AMD-AHCI mode
+	0x01018f00	//sata class ID of IDE to AMD-AHCI mode
+};
+
+//Table for device id of SATA Controller in different modes
+UINT16 sataDeviceIDTable[] = {
+	0x4390,	//sata device ID of IDE
+	0x4392,	//sata device ID of RAID
+	0x4391,	//sata class ID of AHCI
+	0x4390,	//sata device ID of Legacy IDE
+	0x4390,	//sata device ID of IDE->AHCI mode
+	0x4394,	//sata device ID for AMD-AHCI mode
+	0x4390	//sata device ID of IDE->AMDAHCI mode
+};
+
+
+void sataInitBeforePciEnum(AMDSBCFG*	pConfig){
+	UINT32	ddValue, *tempptr;
+	UINT16	*pDeviceIdptr, dwDeviceId;
+	UINT8	dbValue, dbOrMask, dbAndMask;
+
+
+	dbAndMask=0;
+	dbOrMask=0;
+	// Enable/Disable Combined mode & do primary/secondary selections, enable/disable
+	if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) 		dbAndMask= BIT3;		//Clear BIT3
+	if (pConfig->SataIdeCombMdPriSecOpt == 1) 	dbOrMask = BIT4;		//Set BIT4
+	if (pConfig->SataSmbus == 0)	dbOrMask = BIT1;
+
+	RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask);
+
+	if (pConfig->SataController == 0){
+		// SATA Controller Disabled & set Power Saving mode to disabled
+		RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1);
+		return;
+	}
+
+	restrictSataCapabilities(pConfig);
+
+	//	Get the appropriate class code from the table and write it to PCI register 08h-0Bh
+	//	Set the appropriate SATA class based on the input parameters
+	dbValue=pConfig->SataClass;
+	tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
+	ddValue=tempptr[dbValue];
+
+	// BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0
+	// BIT4:disable fast boot
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0);
+
+	// Write the class code to SATA PCI register 08h-0Bh
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+
+	if	(pConfig->SataClass == LEGACY_IDE_MODE)		//SATA = Legacy IDE
+		//Set PATA controller to native mode
+		RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
+
+	//Change the appropriate device id
+	if (pConfig->SataClass == AMD_AHCI_MODE)	{
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+	}
+	pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
+
+	ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+	if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){
+		//if not (SB750 & RAID mode), then program the device id
+		dwDeviceId=pDeviceIdptr[dbValue];
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
+	}
+
+	if (pConfig->AcpiS1Supported)
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability
+	else
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability
+
+	if (getRevisionID() >= SB700_A13){
+		//Enable test/enhancement mode for A13
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00);
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80);
+	}
+
+	if (getRevisionID() >= SB700_A14){
+		//Fix for TT SB01352 -  LED Stays On When ODD Attached To Slave Port In IDE Mode
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6);
+	}
+
+	// Disable write access to PCI header
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+	// RPR 6.5 SATA PHY Programming Sequence
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+
+	CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig);
+}
+
+void sataInitAfterPciEnum(AMDSBCFG* pConfig){
+	UINT32	ddAndMask=0, ddOrMask=0, ddBar5=0;
+	UINT8	dbVar, dbPortNum;
+
+	if (pConfig->SataController == 0) return;		//return if SATA controller is disabled.
+
+	//Enable write access to pci header, pm capabilities
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+        //Disable AHCI enhancement function (RPR 7.2)
+        RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+	restrictSataCapabilities(pConfig);
+
+	ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+	if	( (ddBar5 == 0) || (ddBar5 == -1) ) {
+		//assign temporary BAR5
+		if	( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+			ddBar5 = 0xFEC01000;
+		else
+			ddBar5=pConfig->TempMMIO;
+
+		WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+	}
+
+	ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+	RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03);	//memory and io access enable
+
+	ddBar5 &= 0xFFFFFC00;			//Clear Bits 9:0
+	if (!pConfig->SataPortMultCap)
+		ddAndMask |= BIT12;
+	if (!pConfig->SataAggrLinkPmCap)
+		ddAndMask |= BIT11;
+	if (pConfig->SataSscPscCap)
+		ddOrMask |= BIT1;
+
+	RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
+
+
+	//Clear HPCP and ESP by default
+	RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0);
+
+	if	(pConfig->SataHpcpButNonESP !=0) {
+		RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP);
+	}
+
+	// SATA ESP port setting
+	// These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+	// support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+	// not enable power management(HIPM & DIPM) for these ports.
+	if	(pConfig->SataEspPort !=0) {
+		RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20);
+		RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
+		RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12));
+	}
+
+	if	( ((pConfig->SataClass) != NATIVE_IDE_MODE)  && ((pConfig->SataClass) != LEGACY_IDE_MODE) )
+		RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages
+
+	if	( ((pConfig->SataClass) != NATIVE_IDE_MODE)  && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){
+		RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0);
+		RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
+	}
+
+	for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+		if (pConfig->SataPortMode & (1 << dbPortNum)){
+			//downgrade to GEN1
+			RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
+			RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+			Stall(1000);
+			RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+		}
+	}
+
+	//If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
+	if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE)  && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) )
+		sataDriveDetection(pConfig, ddBar5);
+
+	if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) )
+		sataPhyWorkaround(pConfig, ddBar5);
+
+	// Set the handshake bit for IDE driver to detect the disabled IDE channel correctly.
+	// Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled.
+	if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED)
+		RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) );
+
+	WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+
+	//Disable write access to pci header, pm capabilities
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+}
+
+
+void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
+	UINT32	ddVar0;
+	UINT8	dbPortNum, dbVar0;
+	UINT16	dwIoBase, dwVar0;
+
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
+	TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
+
+	if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
+		for (dbPortNum=0;dbPortNum<4;dbPortNum++){
+			ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+			if ( ( ddVar0 & 0x0F ) == 0x03){
+				if ( dbPortNum & BIT0)
+					//this port belongs to secondary channel
+					ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+				else
+					//this port belongs to primary channel
+					ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+
+				//if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+				if (pConfig->SataClass == LEGACY_IDE_MODE)
+					dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
+
+				if ( dbPortNum & BIT1)
+					//this port is slave
+					dbVar0=0xB0;
+				else
+					//this port is master
+					dbVar0=0xA0;
+				dwIoBase &= 0xFFF8;
+				WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
+
+				//Wait in loop for 30s for the drive to become ready
+				for (dwVar0=0;dwVar0<3000;dwVar0++){
+					ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
+					if ( (dbVar0 & 0x88) == 0)
+						break;
+					Stall(10000);
+				}
+			}	//end of if ( ( ddVar0 & 0x0F ) == 0x03)
+		}	//for (dbPortNum=0;dbPortNum<4;dbPortNum++)
+	}	//if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
+}
+
+
+//This patch is to workaround the SATA PHY logic hardware issue in the SB700.
+//Internally this workaround is called as 7NewA
+void	sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){
+
+	UINT8	dbPortNum, dbVar0;
+
+	if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){
+		for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+			ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0);
+			if ( (dbVar0 & 0xF0) == 0x10){
+				RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum));
+			}
+
+		}
+	}
+
+	RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);//	set SATA PCI_CFG 0x86[7:0] = 0x40  //after the reset is done, perform this to turn on the diff clock path into SATA PHY
+	Stall(2000);//	Wait for 2ms
+	RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13.	set PMIO_D0[4:3] = 00b
+	Stall(20000);//	Wait 20ms
+	forceOOB(ddBar5);//	Force OOB
+
+	RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00);
+}
+
+
+void	forceOOB(UINT32	ddBar5){
+	UINT8 dbPortNum;
+	for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+		RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+	Stall(2000);
+	for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+		RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+	Stall(2000);//	Wait for 2ms
+}
+
+/*++
+
+Routine Description:
+
+  SATA Late Configuration
+
+  if the mode is selected as IDE->AHCI
+  { 1. Set class ID to AHCI
+    2. Enable AHCI interrupt
+  }
+
+Arguments:
+
+  pConfig - SBconfiguration
+
+Returns:
+
+  void
+
+--*/
+void sataInitLatePost(AMDSBCFG* pConfig){
+	UINT32	ddBar5;
+	UINT8	dbVar;
+
+	//Return immediately is sata controller is not enabled
+	if (pConfig->SataController == 0) return;
+
+	restrictSataCapabilities(pConfig);
+
+	//Get BAR5 value
+	ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+	//Assign temporary BAR if is not already assigned
+	if	( (ddBar5 == 0) || (ddBar5 == -1) ){
+		//assign temporary BAR5
+		if	( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+			ddBar5 = 0xFEC01000;
+		else
+			ddBar5=pConfig->TempMMIO;
+		WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+	}
+
+	ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+	//Enable memory and io access
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
+	//Enable write access to pci header, pm capabilities
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+
+	shutdownUnconnectedSataPortClock(pConfig, ddBar5);
+
+	if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+		//program the AHCI class code
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
+		//Set interrupt enable bit
+		RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1);
+		//program the correct device id for AHCI mode
+		RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
+
+		if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)
+			//program the correct device id for AMD-AHCI mode
+			RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+	}
+
+	//Disable write access to pci header and pm capabilities
+	RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+	//Clear error status
+	RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+	RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+	RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+	RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+	//Restore memory and io access bits
+	WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
+}
+
+
+void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){
+	UINT8	dbPortNum, dbPortSataStatus, NumOfPorts=0;
+	UINT8	UnusedPortBitMap;
+	UINT8	SataType;
+	UINT8   ClockOffEnabled ;
+
+	UnusedPortBitMap = 0;
+
+	// First scan for all unused SATA ports
+	for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) {
+	  ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
+	  if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) {
+	    UnusedPortBitMap |= (1 << dbPortNum);
+	  }
+        }
+
+	// Decide if we need to shutdown the clock for all unused ports
+	SataType = pConfig->SataClass;
+	ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \
+	                                                (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \
+			  (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE)));
+
+	if (ClockOffEnabled) {
+	  //Shutdown the clock for the port and do the necessary port reporting changes.
+	  TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap));
+	  RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap);
+	  RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00);
+	}
+
+	// If all ports are in disabled state, report at least one
+	ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+	if ( (dbPortSataStatus & 0x3F) == 0) {
+	  dbPortSataStatus = 1;
+	  RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus);
+	}
+
+	// Decide if we need to hide unused ports from being seen by OS (this saves OS startup time)
+	if (pConfig->SataHideUnusedPort && ClockOffEnabled) {
+	  dbPortSataStatus &= ~UnusedPortBitMap;    // Mask off unused ports
+	  for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) {
+	    if (dbPortSataStatus & (1 << dbPortNum))
+	      NumOfPorts++;
+	    }
+	  if (NumOfPorts == 0 ) {
+		NumOfPorts = 0x01;
+	    }
+	  RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
+	}
+}
+
+
+void	restrictSataCapabilities(AMDSBCFG* pConfig){
+	//Restrict capabilities
+	if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
+		((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE))  || \
+		((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){
+			pConfig->SataClass = NATIVE_IDE_MODE;
+		}
+}
diff --git a/src/vendorcode/amd/cimx/sb700/SB700.h b/src/vendorcode/amd/cimx/sb700/SB700.h
new file mode 100644
index 0000000..f9e71e8
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SB700.h
@@ -0,0 +1,1028 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SB700_H_
+#define _AMD_SB700_H_
+
+#pragma pack(push,1)
+
+#define CIMx_Version                    0x0660
+#define RC_Information                  0x00
+#define Additional_Changes_Indicator    0x00
+
+#define SB_POWERON_INIT                 0x001
+#define OUTDEBUG_PORT                   0x002
+#define SB_BEFORE_PCI_INIT              0x010
+#define SB_AFTER_PCI_INIT               0x020
+#define SB_LATE_POST_INIT               0x030
+#define SB_BEFORE_PCI_RESTORE_INIT      0x040
+#define SB_AFTER_PCI_RESTORE_INIT       0x050
+#define SB_SMM_SERVICE                  0x060
+#define SB_SMM_ACPION                   0x061
+
+#ifndef OEM_CALLBACK_BASE
+  #define       OEM_CALLBACK_BASE       0x100
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING            OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS      OEM_CALLBACK_BASE + 0x20
+
+#define CFG_ADDR_PORT                   0xCF8
+#define CFG_DATA_PORT                   0xCFC
+#define ATI_AZALIA_ExtBlk_Addr          0x0F8
+#define ATI_AZALIA_ExtBlk_DATA          0x0FC
+
+#define ALINK_ACCESS_INDEX              0x0CD8
+#define ALINK_ACCESS_DATA               ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT                      0x0E0
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+#define SB7XX_DEVICE_ID                 0x4385
+
+#define SB700_A11                       0x39
+#define SB700_A12                       0x3A
+#define SB700_A13                       0x3B
+#define SB700_A14                       0x3C
+#define SB700_A15                       0x3D
+
+#define SATA_BUS_DEV_FUN                ((0x11 << 3) + 0)
+#define FC_BUS_DEV_FUN                  ((0x11 << 3) + 1)
+#define USB1_OHCI0_BUS_DEV_FUN          ((0x12 << 3) + 0)
+#define USB1_OHCI1_BUS_DEV_FUN          ((0x12 << 3) + 1)
+#define USB2_OHCI0_BUS_DEV_FUN          ((0x13 << 3) + 0)
+#define USB2_OHCI1_BUS_DEV_FUN          ((0x13 << 3) + 1)
+#define USB3_OHCI_BUS_DEV_FUN           ((0x14 << 3) + 5)
+#define USB1_EHCI_BUS_DEV_FUN           ((0x12 << 3) + 2)
+#define USB2_EHCI_BUS_DEV_FUN           ((0x13 << 3) + 2)
+
+#define SMBUS_BUS_DEV_FUN               ((0x14 << 3) + 0)
+#define IDE_BUS_DEV_FUN                 ((0x14 << 3) + 1)
+#define AZALIA_BUS_DEV_FUN              ((0x14 << 3) + 2)
+#define LPC_BUS_DEV_FUN                 ((0x14 << 3) + 3)
+#define SBP2P_BUS_DEV_FUN               ((0x14 << 3) + 4)
+#define NB_BDF                          ((0 << 3) + 0)
+#define HT_LINK_BUS_DEV_FUN       ((0x18 << 3) + 0)
+#define DCT1_BUS_DEV_FUN          ((0x18 << 3) + 2)
+#define DCT2_BUS_DEV_FUN          ((0x19 << 3) + 2)
+#define DCT3_BUS_DEV_FUN          ((0x1A << 3) + 2)
+#define DCT4_BUS_DEV_FUN          ((0x1B << 3) + 2)
+
+
+//Sata Controller Mode
+#define NATIVE_IDE_MODE                 0
+#define RAID_MODE                       1
+#define AHCI_MODE                       2
+#define LEGACY_IDE_MODE                 3
+#define IDE_TO_AHCI_MODE                4
+#define AMD_AHCI_MODE                   5
+#define IDE_TO_AMD_AHCI_MODE            6
+
+//Sata Port Configuration
+#define SIX_PORTS                       0
+#define FOUR_PORTS                      1
+
+#define SB750_SATA_DEFAULT_DEVICE_ID    0x4393
+
+#define SB_AX_INDXC_REG30               0x30
+#define SB_AX_DATAC_REG34               0x34
+#define SB_AX_INDXP_REG38               0x38
+#define SB_AX_DATAP_REG3C               0x3C
+
+#define AX_INDXC                        0
+#define AX_INDXP                        1
+#define AXCFG                           2
+#define ABCFG                           3
+
+#define SB_AB_REG02                     0x02
+#define SB_AB_REG04                     0x04
+#define SB_AB_REG40                     0x40            //
+#define SB_AB_REG54                     0x54            //;miscCtr54
+#define SB_AB_REG58                     0x58            //;RAB Control - RW - 32 bits - [RegAddr:58]
+#define SB_AB_REG60                     0x60            //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60]
+#define SB_AB_REG64                     0x64            //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64]
+#define SB_AB_REG6C                     0x6C            //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C]
+#define SB_AB_REG80                     0x80            //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80]
+#define SB_AB_REG88                     0x88            //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88]
+#define SB_AB_REG8C                     0x8C            //;AB Enhancement - RW - 16 bits - [RegAddr:88]
+#define SB_AB_REG90                     0x90            //;BIF Control - RW - 32 bits - [RegAddr:90]
+#define SB_AB_REG94                     0x94            //;MSI Control - RW - 32 bits
+#define SB_AB_REG98                     0x98            //;BIF Control 1 - RW - 32 bits
+#define SB_AB_REG9C                     0x9C            //;
+#define SB_AB_REG10050                  BIT16+0x50
+#define SB_AB_REG10054                  BIT16+0x54      //;AL_Arb_Ctl, AL_Clk_Ctl
+#define SB_AB_REG10060                  BIT16+0x60      //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060]
+#define SB_AB_REG10064                  BIT16+0x64      //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64]
+#define SB_AB_REG10090                  BIT16+0x90      //;
+#define SB_AB_REG1009C                  BIT16+0x9C              //;
+
+
+#define SB_PMIO_REG00                   0x000   // MiscControl
+#define SB_PMIO_REG01                   0x001   // MiscStatus
+#define SB_PMIO_REG02                   0x002   // SmiWakeUpEventEnable1
+#define SB_PMIO_REG03                   0x003   // SmiWakeUpEventEnable2
+#define SB_PMIO_REG04                   0x004   // SmiWakeUpEventEnable3
+#define SB_PMIO_REG05                   0x005   // SmiWakeUpEventStatus1
+#define SB_PMIO_REG06                   0x006   // SmiWakeUpEventStatus2
+#define SB_PMIO_REG07                   0x007   // SmiWakeUpEventStatus3
+#define SB_PMIO_REG08                   0x008   // InactiveTmrEventEnable1
+#define SB_PMIO_REG09                   0x009   // InactiveTmrEventEnable2
+#define SB_PMIO_REG0A                   0x00A   // InactiveTmrEventEnable3
+#define SB_PMIO_REG0B                   0x00B   // PmTmr1InitValue
+#define SB_PMIO_REG0C                   0x00C   // PmTmr1CurValue
+#define SB_PMIO_REG0D                   0x00D   // PwrLedExtEvent
+#define SB_PMIO_REG0E                   0x00E   // AcpiControl
+#define SB_PMIO_REG0F                   0x00F   // AcpiStatus
+#define SB_PMIO_REG10                   0x010   // AcpiEn
+#define SB_PMIO_REG11                   0x011   // S1AgpStpEn
+#define SB_PMIO_REG12                   0x012   // PmTmr2InitValue
+#define SB_PMIO_REG13                   0x013   // PmTmr2CurValue
+#define SB_PMIO_REG14                   0x014   // Programlo0RangeLo
+#define SB_PMIO_REG15                   0x015   // ProgramIo0Rangei
+#define SB_PMIO_REG16                   0x016   // ProgramIo1RangeLo
+#define SB_PMIO_REG17                   0x017   // ProgramIo1Rangei
+#define SB_PMIO_REG18                   0x018   // ProgramIo2RangeLo
+#define SB_PMIO_REG19                   0x019   // ProgramIo2Rangei
+#define SB_PMIO_REG1A                   0x01A   // ProgramIo3RangeLo
+#define SB_PMIO_REG1B                   0x01B   // ProgramIo3Rangei
+#define SB_PMIO_REG1C                   0x01C   // ProgramIoEnable
+#define SB_PMIO_REG1D                   0x01D   // IOMonitorStatus
+#define SB_PMIO_REG1E                   0x01E   // InactiveTmrEventEnable4
+#define SB_PMIO_REG20                   0x020   // AcpiPm1EvtBlkLo
+#define SB_PMIO_REG21                   0x021   // AcpiPm1EvtBlki
+#define SB_PMIO_REG22                   0x022   // AcpiPm1CntBlkLo
+#define SB_PMIO_REG23                   0x023   // AcpiPm1CntBlki
+#define SB_PMIO_REG24                   0x024   // AcpiPmTmrBlkLo
+#define SB_PMIO_REG25                   0x025   // AcpiPmTmrBlki
+#define SB_PMIO_REG26                   0x026   // CpuControlLo
+#define SB_PMIO_REG27                   0x027   // CpuControli
+#define SB_PMIO_REG28                   0x028   // AcpiGpe0BlkLo
+#define SB_PMIO_REG29                   0x029   // AcpiGpe0Blki
+#define SB_PMIO_REG2A                   0x02A   // AcpiSmiCmdLo
+#define SB_PMIO_REG2B                   0x02B   // AcpiSmiCmdi
+#define SB_PMIO_REG2C                   0x02C   // AcpiPmaCntBlkLo
+#define SB_PMIO_REG2D                   0x02D   // AcpiPmaCntBlki
+#define SB_PMIO_REG2E                   0x02E   // AcpiSsCntBlkLo
+#define SB_PMIO_REG2F                   0x02F   // AcpiSsCntBlki
+#define SB_PMIO_REG30                   0x030   // GEvtConfig0
+#define SB_PMIO_REG31                   0x031   // GEvtConfig1
+#define SB_PMIO_REG32                   0x032   // GPMConfig0
+#define SB_PMIO_REG33                   0x033   // GPMConfig1
+#define SB_PMIO_REG34                   0x034   // GPMConfig2
+#define SB_PMIO_REG35                   0x035   // GPMConfig3
+#define SB_PMIO_REG36                   0x036   // GEvtLevelConfig
+#define SB_PMIO_REG37                   0x037   // GPMLevelConfig0
+#define SB_PMIO_REG38                   0x038   // GPMLevelConfig1
+#define SB_PMIO_REG39                   0x039   // GEvtStatus
+#define SB_PMIO_REG3A                   0x03A   // PMEStatus0
+#define SB_PMIO_REG3B                   0x03B   // PMEStatus1
+#define SB_PMIO_REG3C                   0x03C   // OtersConfig
+#define SB_PMIO_REG3E                   0x03E   // VRT_T1
+#define SB_PMIO_REG3F                   0x03F   // VRT_T2
+#define SB_PMIO_REG40                   0x040   // Fan0DutyCycle
+#define SB_PMIO_REG41                   0x041   // Fan0Control
+#define SB_PMIO_REG42                   0x042   // Fan1DutyCycle
+#define SB_PMIO_REG43                   0x043   // Reserved for internal use
+#define SB_PMIO_REG50                   0x050   // PM_Enable
+#define SB_PMIO_REG51                   0x051   // TPRESET1
+#define SB_PMIO_REG52                   0x052   // TPRESET2
+#define SB_PMIO_REG53                   0x053   // TESTENABLE
+#define SB_PMIO_REG54                   0x054   // PWRBTTN_CLR
+#define SB_PMIO_REG55                   0x055   // SoftPciRst
+#define SB_PMIO_REG56                   0x056   // Reserved
+#define SB_PMIO_REG59                   0x059   // Ac97Mask
+#define SB_PMIO_REG60                   0x060   // Options_0
+#define SB_PMIO_REG61                   0x061   // Options_1
+#define SB_PMIO_REG62                   0x062   // Sadow_SCI
+#define SB_PMIO_REG63                   0x063   // SwitcVoltageTime
+#define SB_PMIO_REG64                   0x064   // SwitchGI_Time
+#define SB_PMIO_REG65                   0x065   // UsbPMControl
+#define SB_PMIO_REG66                   0x066   // MiscEnable66
+#define SB_PMIO_REG67                   0x067   // MiscEnable67
+#define SB_PMIO_REG68                   0x068   // MiscEnable68
+#define SB_PMIO_REG69                   0x069   // WatcDogTimerControl
+#define SB_PMIO_REG6C                   0x06C   // WatcDogTimerBase0
+#define SB_PMIO_REG6D                   0x06D   // WatcDogTimerBase1
+#define SB_PMIO_REG6E                   0x06E   // WatcDogTimerBase2
+#define SB_PMIO_REG6F                   0x06F   // WatcDogTimerBase3
+#define SB_PMIO_REG70                   0x070   //  S_LdtStartTime
+#define SB_PMIO_REG71                   0x071   // FidVidOption
+#define SB_PMIO_REG72                   0x072   // Spare4
+#define SB_PMIO_REG73                   0x073   // Spare5
+#define SB_PMIO_REG74                   0x074   // PwrFailSadow
+#define SB_PMIO_REG75                   0x075   // Tpreset1b
+#define SB_PMIO_REG76                   0x076   // S0S3ToS5Enable0
+#define SB_PMIO_REG77                   0x077   // S0S3ToS5Enable1
+#define SB_PMIO_REG78                   0x078   // S0S3ToS5Enable2
+#define SB_PMIO_REG79                   0x079   // S0S3ToS5Enable3
+#define SB_PMIO_REG7A                   0x07A   // NoStatusControl0
+#define SB_PMIO_REG7B                   0x07B   // NoStatusControl1
+#define SB_PMIO_REG7C                   0x07C   // MiscEnable7C
+#define SB_PMIO_REG80                   0x080   // SMAF0
+#define SB_PMIO_REG81                   0x081   // SMAF1
+#define SB_PMIO_REG82                   0x082   // SMAF2
+#define SB_PMIO_REG83                   0x083   // SMAF3
+#define SB_PMIO_REG84                   0x084   // WakePinCntl
+#define SB_PMIO_REG85                   0x085   // CF9Rst
+#define SB_PMIO_REG86                   0x086   // ThermTrotCntl
+#define SB_PMIO_REG87                   0x087   // LdtStpCmd
+#define SB_PMIO_REG88                   0x088   // LdtStartTime
+#define SB_PMIO_REG89                   0x089   // AgpStartTime
+#define SB_PMIO_REG8A                   0x08A   // LdtAgpTimeCntl
+#define SB_PMIO_REG8B                   0x08B   // StutterTime
+#define SB_PMIO_REG8C                   0x08C   // StpClkDlyTime
+#define SB_PMIO_REG8D                   0x08D   // AbPmeCntl
+#define SB_PMIO_REG8E                   0x08E   // FakeAsr
+#define SB_PMIO_REG8F                   0x08F   // FakeAsrEn
+#define SB_PMIO_REG90                   0x090   // GEVENTOUT
+#define SB_PMIO_REG91                   0x091   // GEVENTEnable
+#define SB_PMIO_REG92                   0x092   // GEVENTIN
+#define SB_PMIO_REG95                   0x095   // GPM98EN
+#define SB_PMIO_REG9A                   0x09A   // EnanceControl
+#define SB_PMIO_REG9E                   0x09E   // EnanceControl
+#define SB_PMIO_REG9F                   0x09F   // EnanceControl
+#define SB_PMIO_REGA0                   0x0A0   // Programlo4RangeLo
+#define SB_PMIO_REGA1                   0x0A1   // ProgramIo4Rangei
+#define SB_PMIO_REGA2                   0x0A2   // Programlo5RangeLo
+#define SB_PMIO_REGA3                   0x0A3   // ProgramIo5Rangei
+#define SB_PMIO_REGA4                   0x0A4   // Programlo6RangeLo
+#define SB_PMIO_REGA5                   0x0A5   // ProgramIo6Rangei
+#define SB_PMIO_REGA6                   0x0A6   // Programlo7RangeLo
+#define SB_PMIO_REGA7                   0x0A7   // ProgramIo7Rangei
+#define SB_PMIO_REGA8                   0x0A8   // PIO7654Enable
+#define SB_PMIO_REGA9                   0x0A9   // PIO7654Status
+#define SB_PMIO_REGB0                   0x0B0
+#define SB_PMIO_REGB1                   0x0B1
+#define SB_PMIO_REGB2                   0x0B2   // MiscControl3
+#define SB_PMIO_REGB4                   0x0B4   // HPET BAR
+#define SB_PMIO_REGB6                   0x0B6
+#define SB_PMIO_REGB7                   0x0B7
+#define SB_PMIO_REGBB                   0x0BB   // IMC_ACPI_Enable
+#define SB_PMIO_REGBC                   0x0BC   //
+#define SB_PMIO_REGBD                   0x0BD   //
+#define SB_PMIO_REGC9                   0x0C9   // MultiK8Control
+#define SB_PMIO_REGCA                   0x0CA   //
+#define SB_PMIO_REGCB                   0x0CB   //
+#define SB_PMIO_REGCC                   0x0CC   //
+#define SB_PMIO_REGCD                   0x0CD   //
+#define SB_PMIO_REGD0                   0x0D0   //
+#define SB_PMIO_REGD2                   0x0D2   //
+#define SB_PMIO_REGD4                   0x0D4   //
+#define SB_PMIO_REGD7                   0x0D7   //
+
+
+#define SB_RTC_REG00                    0x00            // Seconds - RW
+#define SB_RTC_REG01                    0x01            // Seconds Alarm - RW
+#define SB_RTC_REG02                    0x02            // Minutes - RW
+#define SB_RTC_REG03                    0x03            // Minutes Alarm - RW
+#define SB_RTC_REG04                    0x04            // ours - RW
+#define SB_RTC_REG05                    0x05            // ours Alarm- RW
+#define SB_RTC_REG06                    0x06            // Day of Week - RW
+#define SB_RTC_REG07                    0x07            // Date of Mont - RW
+#define SB_RTC_REG08                    0x08            // Mont - RW
+#define SB_RTC_REG09                    0x09            // Year - RW
+#define SB_RTC_REG0A                    0x0A            // Register A - RW
+#define SB_RTC_REG0B                    0x0B            // Register B - RW
+#define SB_RTC_REG0C                    0x0C            // Register C - R
+#define SB_RTC_REG0D                    0x0D            // DateAlarm - RW
+#define SB_RTC_REG32                    0x32            // AltCentury - RW
+#define SB_RTC_REG48                    0x48            // Century - RW
+#define SB_RTC_REG50                    0x50            // Extended RAM Address Port - RW
+#define SB_RTC_REG53                    0x53            // Extended RAM Data Port - RW
+#define SB_RTC_REG7E                    0x7E            // RTC Time Clear - RW
+#define SB_RTC_REG7F                    0x7F            // RTC RAM Enable - RW
+
+#define B_ECMOS_REG00                   0x00            // scratc-reg
+                                                        //;BIT0=0       AsicDebug is enabled
+                                                        //;BIT1=0       SLT S3 runs
+#define SB_ECMOS_REG01                  0x01
+#define SB_ECMOS_REG02                  0x02
+#define SB_ECMOS_REG03                  0x03
+#define SB_ECMOS_REG04                  0x04
+#define SB_ECMOS_REG05                  0x05
+#define SB_ECMOS_REG06                  0x06
+#define SB_ECMOS_REG07                  0x07
+#define SB_ECMOS_REG08                  0x08            // save 32BIT Pysical address of Config structure
+#define SB_ECMOS_REG09                  0x09
+#define SB_ECMOS_REG0A                  0x0A
+#define SB_ECMOS_REG0B                  0x0B
+
+#define SB_ECMOS_REG0C                  0x0C            //;save MODULE_ID
+#define SB_ECMOS_REG0D                  0x0D            //;Reserve for NB
+
+#define SB_IOMAP_REG00                  0x000   // Dma_C 0
+#define SB_IOMAP_REG02                  0x002   // Dma_C 1
+#define SB_IOMAP_REG04                  0x004   // Dma_C 2
+#define SB_IOMAP_REG06                  0x006   // Dma_C 3
+#define SB_IOMAP_REG08                  0x008   // Dma_Status
+#define SB_IOMAP_REG09                  0x009   // Dma_WriteRest
+#define SB_IOMAP_REG0A                  0x00A   // Dma_WriteMask
+#define SB_IOMAP_REG0B                  0x00B   // Dma_WriteMode
+#define SB_IOMAP_REG0C                  0x00C   // Dma_Clear
+#define SB_IOMAP_REG0D                  0x00D   // Dma_MasterClr
+#define SB_IOMAP_REG0E                  0x00E   // Dma_ClrMask
+#define SB_IOMAP_REG0F                  0x00F   // Dma_AllMask
+#define SB_IOMAP_REG20                  0x020   // IntrCntrlReg1
+#define SB_IOMAP_REG21                  0x021   // IntrCntrlReg2
+#define SB_IOMAP_REG40                  0x040   // TimerC0
+#define SB_IOMAP_REG41                  0x041   // TimerC1
+#define SB_IOMAP_REG42                  0x042   // TimerC2
+#define SB_IOMAP_REG43                  0x043   // Tmr1CntrlWord
+#define SB_IOMAP_REG61                  0x061   // Nmi_Status
+#define SB_IOMAP_REG70                  0x070   // Nmi_Enable
+#define SB_IOMAP_REG71                  0x071   // RtcDataPort
+#define SB_IOMAP_REG72                  0x072   // AlternatRtcAddrPort
+#define SB_IOMAP_REG73                  0x073   // AlternatRtcDataPort
+#define SB_IOMAP_REG80                  0x080   // Dma_Page_Reserved0
+#define SB_IOMAP_REG81                  0x081   // Dma_PageC2
+#define SB_IOMAP_REG82                  0x082   // Dma_PageC3
+#define SB_IOMAP_REG83                  0x083   // Dma_PageC1
+#define SB_IOMAP_REG84                  0x084   // Dma_Page_Reserved1
+#define SB_IOMAP_REG85                  0x085   // Dma_Page_Reserved2
+#define SB_IOMAP_REG86                  0x086   // Dma_Page_Reserved3
+#define SB_IOMAP_REG87                  0x087   // Dma_PageC0
+#define SB_IOMAP_REG88                  0x088   // Dma_Page_Reserved4
+#define SB_IOMAP_REG89                  0x089   // Dma_PageC6
+#define SB_IOMAP_REG8A                  0x08A   // Dma_PageC7
+#define SB_IOMAP_REG8B                  0x08B   // Dma_PageC5
+#define SB_IOMAP_REG8C                  0x08C   // Dma_Page_Reserved5
+#define SB_IOMAP_REG8D                  0x08D   // Dma_Page_Reserved6
+#define SB_IOMAP_REG8E                  0x08E   // Dma_Page_Reserved7
+#define SB_IOMAP_REG8F                  0x08F   // Dma_Refres
+#define SB_IOMAP_REG92                  0x092   // FastInit
+#define SB_IOMAP_REGA0                  0x0A0   // IntrCntrl2Reg1
+#define SB_IOMAP_REGA1                  0x0A1   // IntrCntrl2Reg2
+#define SB_IOMAP_REGC0                  0x0C0   // Dma2_C4Addr
+#define SB_IOMAP_REGC2                  0x0C2   // Dma2_C4Cnt
+#define SB_IOMAP_REGC4                  0x0C4   // Dma2_C5Addr
+#define SB_IOMAP_REGC6                  0x0C6   // Dma2_C5Cnt
+#define SB_IOMAP_REGC8                  0x0C8   // Dma2_C6Addr
+#define SB_IOMAP_REGCA                  0x0CA   // Dma2_C6Cnt
+#define SB_IOMAP_REGCC                  0x0CC   // Dma2_C7Addr
+#define SB_IOMAP_REGCE                  0x0CE   // Dma2_C7Cnt
+#define SB_IOMAP_REGD0                  0x0D0   // Dma_Status
+#define SB_IOMAP_REGD2                  0x0D2   // Dma_WriteRest
+#define SB_IOMAP_REGD4                  0x0D4   // Dma_WriteMask
+#define SB_IOMAP_REGD6                  0x0D6   // Dma_WriteMode
+#define SB_IOMAP_REGD8                  0x0D8   // Dma_Clear
+#define SB_IOMAP_REGDA                  0x0DA   // Dma_Clear
+#define SB_IOMAP_REGDC                  0x0DC   // Dma_ClrMask
+#define SB_IOMAP_REGDE                  0x0DE   // Dma_ClrMask
+#define SB_IOMAP_REGF0                  0x0F0   // NCP_Error
+#define SB_IOMAP_REG40B                 0x040B  // DMA1_Extend
+#define SB_IOMAP_REG4D0                 0x04D0  // IntrEdgeControl
+#define SB_IOMAP_REG4D6                 0x04D6  // DMA2_Extend
+#define SB_IOMAP_REGC00                 0x0C00  // Pci_Intr_Index
+#define SB_IOMAP_REGC01                 0x0C01  // Pci_Intr_Data
+#define SB_IOMAP_REGC14                 0x0C14  // Pci_Error
+#define SB_IOMAP_REGC50                 0x0C50  // CMIndex
+#define SB_IOMAP_REGC51                 0x0C51  // CMData
+#define SB_IOMAP_REGC52                 0x0C52  // GpmPort
+#define SB_IOMAP_REGC6F                 0x0C6F  // Isa_Misc
+#define SB_IOMAP_REGCD0                 0x0CD0  // PMio2_Index
+#define SB_IOMAP_REGCD1                 0x0CD1  // PMio2_Data
+#define SB_IOMAP_REGCD4                 0x0CD4  // BIOSRAM_Index
+#define SB_IOMAP_REGCD5                 0x0CD5  // BIOSRAM_Data
+#define SB_IOMAP_REGCD6                 0x0CD6  // PM_Index
+#define SB_IOMAP_REGCD7                 0x0CD7  // PM_Data
+#define SB_IOMAP_REGCF9                 0x0CF9          // CF9Rst reg
+
+
+#define SB_CM_REG02                     0x002   // TempStatus (via SB_IOMAP_REGC50)
+#define SB_CM_REG03                     0x003   // TempInterrupt (via SB_IOMAP_REGC50)
+
+#define SB_SATA_REG00                   0x000   // Vendor ID - R- 16 bits
+#define SB_SATA_REG02                   0x002   // Device ID - RW -16 bits
+#define SB_SATA_REG04                   0x004   // PCI Command - RW - 16 bits
+#define SB_SATA_REG06                   0x006   // PCI Status - RW - 16 bits
+#define SB_SATA_REG08                   0x008   // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define SB_SATA_REG0C                   0x00C   // Cace Line Size - R/W - 8bits
+#define SB_SATA_REG0D                   0x00D   // Latency Timer - RW - 8 bits
+#define SB_SATA_REG0E                   0x00E   // eader Type - R - 8 bits
+#define SB_SATA_REG0F                   0x00F   // BIST - R - 8 bits
+#define SB_SATA_REG10                   0x010   // Base Address Register 0 - RW - 32 bits
+#define SB_SATA_REG14                   0x014   // Base Address Register 1 - RW- 32 bits
+#define SB_SATA_REG18                   0x018   // Base Address Register 2 - RW - 32 bits
+#define SB_SATA_REG1C                   0x01C   // Base Address Register 3 - RW - 32 bits
+#define SB_SATA_REG20                   0x020   // Base Address Register 4 - RW - 32 bits
+#define SB_SATA_REG24                   0x024   // Base Address Register 5 - RW - 32 bits
+#define SB_SATA_REG2C                   0x02C   // Subsystem Vendor ID - R - 16 bits
+#define SB_SATA_REG2D                   0x02D   // Subsystem ID - R - 16 bits
+#define SB_SATA_REG30                   0x030   // Expansion ROM Base Address - 32 bits
+#define SB_SATA_REG34                   0x034   // Capabilities Pointer - R - 32 bits
+#define SB_SATA_REG3C                   0x03C   // Interrupt Line - RW - 8 bits
+#define SB_SATA_REG3D                   0x03D   // Interrupt Pin - R - 8 bits
+#define SB_SATA_REG3E                   0x03E   // Min Grant - R - 8 bits
+#define SB_SATA_REG3F                   0x03F   // Max Latency - R - 8 bits
+#define SB_SATA_REG40                   0x040   // Configuration - RW - 32 bits
+#define SB_SATA_REG44                   0x044   // Software Data Register - RW - 32 bits
+#define SB_SATA_REG48                   0x048
+#define SB_SATA_REG50                   0x050   // Message Capability - R - 16 bits
+#define SB_SATA_REG52                   0x052   // Message Control - R/W - 16 bits
+#define SB_SATA_REG54                   0x054   // Message Address - R/W - 32 bits
+#define SB_SATA_REG58                   0x058   // Message Data - R/W - 16 bits
+#define SB_SATA_REG5C                   0x05C   // RAMBIST Control Register - R/W - 8 bits
+#define SB_SATA_REG5D                   0x05D   // RAMBIST Status0 Register - R - 8 bits
+#define SB_SATA_REG5E                   0x05E   // RAMBIST Status1 Register - R - 8 bits
+#define SB_SATA_REG60                   0x060   // Power Management Capabilities - R - 32 bits
+#define SB_SATA_REG64                   0x064   // Power Management Control + Status - RW - 32 bits
+#define SB_SATA_REG68                   0x068   // MSI Program Weigt - R/W - 8 bits
+#define SB_SATA_REG69                   0x069   // PCI Burst Timer - R/W - 8 bits
+#define SB_SATA_REG70                   0x070   // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_REG74                   0x074   // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_REG78                   0x078   // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_REG7C                   0x07C   // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_REG80                   0x080   // Data Transfer Mode - IDE0 - RW - 32 bits
+#define SB_SATA_REG84                   0x084   // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_REG86                   0x086   // PY Global Control
+#define SB_SATA_REG87                   0x087
+#define SB_SATA_REG88                   0x088   // PHY Port0 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG8A                   0x08A
+#define SB_SATA_REG8C                   0x08C   // PHY Port1 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG8E                   0x08E
+#define SB_SATA_REG90                   0x090   // PHY Port2 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG92                   0x092
+#define SB_SATA_REG94                   0x094   // PHY Port3 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG96                   0x096
+#define SB_SATA_REG98                   0x098   // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_REG9C                   0x09C   // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_REGA0                   0x0A0   //
+#define SB_SATA_REGA4                   0x0A4   //
+#define SB_SATA_REGA5                   0x0A5   //;
+#define SB_SATA_REGA8                   0x0A8   //
+#define SB_SATA_REGAD                   0x0AD   //;
+#define SB_SATA_REGB0                   0x0B0   // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_REGB5                   0x0B5   //;
+#define SB_SATA_REGBD                   0x0BD   //;
+#define SB_SATA_REGC0                   0x0C0   // BA5 Indirect Address - RW - 32 bits
+#define SB_SATA_REGC4                   0x0C4   // BA5 Indirect Access - RW - 32 bits
+
+#define SB_SATA_BAR5_REG00              0x000   // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG04              0x004   // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG08              0x008   // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG0C              0x00C   // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG10              0x010   // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG18              0x018   // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG20              0x020   // PRD Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG24              0x024   // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define SB_SATA_BAR5_REG28              0x028   // PRD Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG2C              0x02C   // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG40              0x040   // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG44              0x044   // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG48              0x048   // System Configuration Status - Command - RW - 32 bits
+#define SB_SATA_BAR5_REG4C              0x04C   // System Software Data Register - RW - 32 bits
+#define SB_SATA_BAR5_REG50              0x050   // FLAS Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG54              0x054   // FLAS Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG58              0x058   // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG5C              0x05C   // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG60              0x060   // FIFO Port - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG68              0x068   // FIFO Pointers1- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG6C              0x06C   // FIFO Pointers2- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG70              0x070   // FIFO Port - IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG78              0x078   // FIFO Pointers1- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG7C              0x07C   // FIFO Pointers2- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG80              0x080   // IDE0 Task File Register 0- RW - 32 bits
+#define SB_SATA_BAR5_REG84              0x084   // IDE0 Task File Register 1- RW - 32 bits
+#define SB_SATA_BAR5_REG88              0x088   // IDE0 Task File Register 2- RW - 32 bits
+#define SB_SATA_BAR5_REG8C              0x08C   // IDE0 Read Aead Data - RW - 32 bits
+#define SB_SATA_BAR5_REG90              0x090   // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG94              0x094   // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG9C              0x09C   // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGA0              0x0A0   // IDE0 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGB4              0x0B4   // Data Transfer Mode -IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC0              0x0C0   // IDE1 Task File Register 0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC4              0x0C4   // IDE1 Task File Register 1 - RW - 32 bits
+#define SB_SATA_BAR5_REGC8              0x0C8   // IDE1 Task File Register 2 - RW - 32 bits
+#define SB_SATA_BAR5_REGCC              0x0CC   //  Read/Write Aead Data - RW - 32 bits
+#define SB_SATA_BAR5_REGD0              0x0D0   // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGD4              0x0D4   // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGDC              0x0DC   // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGE0              0x0E0   // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGF4              0x0F4   // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REGF8              0x0F8   // PORT Configuration
+#define SB_SATA_BAR5_REGFC              0x0FC
+
+#define SB_SATA_BAR5_REG100             0x0100  //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define SB_SATA_BAR5_REG104             0x0104  //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define SB_SATA_BAR5_REG108             0x0108  //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define SB_SATA_BAR5_REG10C             0x010C  //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define SB_SATA_BAR5_REG110             0x0110  // Port-N Interrupt Status
+#define SB_SATA_BAR5_REG144             0x0144  //;Serial ATA PY Configuration - RW - 32 bits
+#define SB_SATA_BAR5_REG148             0x0148  //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define SB_SATA_BAR5_REG14C             0x014C  //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define SB_SATA_BAR5_REG120             0x0120  // Port Task Fike Data
+#define SB_SATA_BAR5_REG128             0x0128  // Port Serial ATA Status
+#define SB_SATA_BAR5_REG12C             0x012C  // Port Serial ATA Control
+
+#define SB_SATA_BAR5_REG130             0x0130
+#define SB_SATA_BAR5_REG1B0             0x01B0
+#define SB_SATA_BAR5_REG230             0x0230
+#define SB_SATA_BAR5_REG2B0             0x02B0
+
+#define SB_FC_REG00                     0x00            // Device/Vendor ID - R
+#define SB_FC_REG04                     0x04            // Command - RW
+#define SB_FC_REG10                     0x10            // BAR
+
+#define SB_FC_MMIO_REG70                0x070
+#define SB_FC_MMIO_REG200               0x200
+
+#define SB_OHCI_REG00                   0x00            // Device/Vendor ID - R
+#define SB_OHCI_REG04                   0x04            // Command - RW
+#define SB_OHCI_REG06                   0x06            // Status - R
+#define SB_OHCI_REG08                   0x08            // Revision ID/Class Code - R
+#define SB_OHCI_REG0C                   0x0C            // Miscellaneous - RW
+#define SB_OHCI_REG10                   0x10            // Bar_OCI - RW
+#define SB_OHCI_REG2C                   0x2C            // Subsystem Vendor ID/ Subsystem ID - RW
+#define SB_OHCI_REG34                   0x34            // Capability Pointer - R
+#define SB_OHCI_REG3C                   0x3C            // Interrupt Line - RW
+#define SB_OHCI_REG3D                   0x3D            // Interrupt Line - RW
+
+#define SB_OHCI_REG40                   0x40            // Config Timers - RW
+#define SB_OHCI_REG4C                   0x4C            // MSI Weigt - RW
+#define SB_OHCI_REG50                   0x50            // ATI Misc Control - RW
+#define SB_OHCI_REG51                   0x51
+#define SB_OHCI_REG58                   0x58            // Over Current Control - RW
+#define SB_OHCI_REG5C                   0x5C            // Over Current Control - RW
+#define SB_OHCI_REG60                   0x60            // Serial Bus Release Number - R
+#define SB_OHCI_REG68                   0x68            // Over Current Enable - RW
+#define SB_OHCI_REGD0                   0x0D0   // MSI Control - RW
+#define SB_OHCI_REGD4                   0x0D4   // MSI Address - RW
+#define SB_OHCI_REGD8                   0x0D8   // MSI Data - RW
+#define SB_OHCI_BAR_REG00               0x00            // cRevision - R
+#define SB_OHCI_BAR_REG04               0x04            // cControl
+#define SB_OHCI_BAR_REG08               0x08            // cCommandStatus
+#define SB_OHCI_BAR_REG0C               0x0C            // cInterruptStatus  RW
+#define SB_OHCI_BAR_REG10               0x10            // cInterruptEnable
+#define SB_OHCI_BAR_REG14               0x14            // cInterruptDisable
+#define SB_OHCI_BAR_REG18               0x18            // HcCCA
+#define SB_OHCI_BAR_REG1C               0x1C            // cPeriodCurrentED
+#define SB_OHCI_BAR_REG20               0x20            // HcControleadED
+#define SB_OHCI_BAR_REG24               0x24            // cControlCurrentED  RW
+#define SB_OHCI_BAR_REG28               0x28            // HcBulkeadED
+#define SB_OHCI_BAR_REG2C               0x2C            // cBulkCurrentED- RW
+#define SB_OHCI_BAR_REG30               0x30            // HcDoneead
+#define SB_OHCI_BAR_REG34               0x34            // cFmInterval
+#define SB_OHCI_BAR_REG38               0x38            // cFmRemaining
+#define SB_OHCI_BAR_REG3C               0x3C            // cFmNumber
+#define SB_OHCI_BAR_REG40               0x40            // cPeriodicStart
+#define SB_OHCI_BAR_REG44               0x44            // HcLSThresold
+#define SB_OHCI_BAR_REG48               0x48            // HcRDescriptorA
+#define SB_OHCI_BAR_REG4C               0x4C            // HcRDescriptorB
+#define SB_OHCI_BAR_REG50               0x50            // HcRStatus
+#define SB_OHCI_BAR_REG160              0x160
+
+#define SB_EHCI_REG00                   0x00            // DEVICE/VENDOR ID - R
+#define SB_EHCI_REG04                   0x04            // Command - RW
+#define SB_EHCI_REG06                   0x06            // Status - R
+#define SB_EHCI_REG08                   0x08            // Revision ID/Class Code - R
+#define SB_EHCI_REG0C                   0x0C            // Miscellaneous - RW
+#define SB_EHCI_REG10                   0x10            // BAR - RW
+#define SB_EHCI_REG2C                   0x2C            // Subsystem ID/Subsystem Vendor ID - RW
+#define SB_EHCI_REG34                   0x34            // Capability Pointer - R
+#define SB_EHCI_REG3C                   0x3C            // Interrupt Line - RW
+#define SB_EHCI_REG3D                   0x3D            // Interrupt Line - RW
+#define SB_EHCI_REG40                   0x40            // Config Timers - RW
+#define SB_EHCI_REG4C                   0x4C            // MSI Weigt - RW
+#define SB_EHCI_REG50                   0x50            // ATI Misc Control - RW
+#define SB_EHCI_REG54                   0x54            // ATI Misc Control - RW
+#define SB_EHCI_REG58                   0x58            // Over Current Control - R
+#define SB_EHCI_REG60                   0x60            // SBRN - R
+#define SB_EHCI_REG61                   0x61            // FLADJ - RW
+#define SB_EHCI_REG62                   0x62            // PORTWAKECAP - RW
+#define SB_EHCI_REGD0                   0x0D0   // MSI Control - RW
+#define SB_EHCI_REGD4                   0x0D4   // MSI Address - RW
+#define SB_EHCI_REGD8                   0x0D8   // MSI Data - RW
+#define SB_EHCI_REGDC                   0x0DC   // PME Control - RW
+#define SB_EHCI_REGE0                   0x0E0   // PME Data / Status - RW
+#define SB_EHCI_BAR_REG00               0x00            // CAPLENGT - R
+#define SB_EHCI_BAR_REG02               0x002           // CIVERSION- R
+#define SB_EHCI_BAR_REG04               0x004           // CSPARAMS - R
+#define SB_EHCI_BAR_REG08               0x008           // CCPARAMS - R
+#define SB_EHCI_BAR_REG0C               0x00C           // CSP-PORTROUTE - R
+#define SB_EHCI_BAR_REG20               0x020   // USBCMD - RW - 32 bits
+#define SB_EHCI_BAR_REG24               0x024   // USBSTS - RW - 32 bits
+#define SB_EHCI_BAR_REG28               0x028   // USBINTR -RW - 32 bits
+#define SB_EHCI_BAR_REG2C               0x02C   // FRINDEX -RW - 32 bits
+#define SB_EHCI_BAR_REG30               0x030   // CTRLDSSEGMENT -RW - 32 bits
+#define SB_EHCI_BAR_REG34               0x034   // PERIODICLISTBASE -RW - 32 bits
+#define SB_EHCI_BAR_REG38               0x038   // ASYNCLISTADDR -RW - 32 bits
+#define SB_EHCI_BAR_REG60               0x060   // CONFIGFLAG -RW - 32 bits
+#define SB_EHCI_BAR_REG64               0x064   // PORTSC(1-N_PORTS) -RW - 32 bits
+#define SB_EHCI_BAR_REG84               0x084   // Packet Buffer Thresold Values - RW - 32 bits
+#define SB_EHCI_BAR_REG88               0x088   // Packet Buffer Dept Value - RW - 32 bits
+#define SB_EHCI_BAR_REG94               0x094   // UTMI Control and Status - RW - 32 bits
+#define SB_EHCI_BAR_REG98               0x098   // Bist Control - RW - 32 bits
+#define SB_EHCI_BAR_REG9C               0x09C   // ATI EOR Control - RW - 32 bits
+#define SB_EHCI_BAR_REGA4               0x0A4   // USB IN/OUT FIFO Thresold Setting
+#define SB_EHCI_BAR_REGBC               0x0BC   // ECI misc Setting
+#define SB_EHCI_BAR_REGC0               0x0C0   // USB PHY Auto Calibration Setting
+
+#define SB_SMBUS_REG00                  0x000   //;VendorID - R
+#define SB_SMBUS_REG02                  0x002   //;DeviceID - R
+#define SB_SMBUS_REG04                  0x004   // Command- RW
+#define SB_SMBUS_REG05                  0x005   // Command- RW
+#define SB_SMBUS_REG06                  0x006   // STATUS- RW
+#define SB_SMBUS_REG08                  0x008   // Revision ID/Class Code- R
+#define SB_SMBUS_REG0A                  0x00A   //;
+#define SB_SMBUS_REG0B                  0x00B   //;
+#define SB_SMBUS_REG0C                  0x00C   // Cace Line Size- R
+#define SB_SMBUS_REG0D                  0x00D   // Latency Timer- R
+#define SB_SMBUS_REG0E                  0x00E   // eader Type- R
+#define SB_SMBUS_REG0F                  0x00F   // BIST- R
+#define SB_SMBUS_REG10                  0x010   // Base Address 0- R
+#define SB_SMBUS_REG11                  0x011   //;
+#define SB_SMBUS_REG12                  0x012   //;
+#define SB_SMBUS_REG13                  0x013   //;
+#define SB_SMBUS_REG14                  0x014   // Base Address 1- R
+#define SB_SMBUS_REG18                  0x018   // Base Address 2- R
+#define SB_SMBUS_REG1C                  0x01C   // Base Address 3- R
+#define SB_SMBUS_REG20                  0x020   // Base Address 4- R
+#define SB_SMBUS_REG24                  0x024   // Base Address 5- R
+#define SB_SMBUS_REG28                  0x028   // Cardbus CIS Pointer- R
+#define SB_SMBUS_REG2C                  0x02C   // Subsystem Vendor ID- W
+#define SB_SMBUS_REG2E                  0x02E   // Subsystem ID- W
+#define SB_SMBUS_REG30                  0x030   // Expansion ROM Base Address - R
+#define SB_SMBUS_REG34                  0x034   // Capability Pointer - R
+#define SB_SMBUS_REG38                  0x038
+#define SB_SMBUS_REG3C                  0x03C   // Interrupt Line - R
+#define SB_SMBUS_REG3D                  0x03D   // Interrupt Pin - R
+#define SB_SMBUS_REG3E                  0x03E   // Min_Gnt - R
+#define SB_SMBUS_REG3F                  0x03F   // Max_Lat - R
+#define SB_SMBUS_REG40                  0x040   // PCI Control- RW
+#define SB_SMBUS_REG41                  0x041   // MiscFunction- RW
+#define SB_SMBUS_REG42                  0x042   // DmaLimit- RW
+#define SB_SMBUS_REG43                  0x043   // DmaEnanceEnable RW
+#define SB_SMBUS_REG48                  0x048   // ISA Address Decode Control Register #1- RW
+#define SB_SMBUS_REG49                  0x049   // ISA Address Decode Control Register #2- RW
+#define SB_SMBUS_REG4A                  0x04A   // Scratc Pad- RW
+#define SB_SMBUS_REG50                  0x050   // PciGpioOutControl- RW
+#define SB_SMBUS_REG54                  0x054   // PciGpioConfig- RW
+#define SB_SMBUS_REG58                  0x058   // ASFSMBusIoBase
+#define SB_SMBUS_REG59                  0x059   //;
+#define SB_SMBUS_REG5C                  0x05C   // Smart Power Control1
+#define SB_SMBUS_REG60                  0x060   // MiscEnable- RW
+#define SB_SMBUS_REG64                  0x064   // Features Enable- RW
+#define SB_SMBUS_REG68                  0x068   // UsbEnable - RW
+#define SB_SMBUS_REG6C                  0x06C   // TestMode- RW
+#define SB_SMBUS_REG70                  0x070   // RunTimeTest- R
+#define SB_SMBUS_REG74                  0x074   // IoApic_Conf- RW
+#define SB_SMBUS_REG78                  0x078   // IoAddrEnable - R/W
+#define SB_SMBUS_REG79                  0x079   //;
+#define SB_SMBUS_REG7C                  0x07C   // RTC Control  ;VSJ-2005-06-16
+#define SB_SMBUS_REG80                  0x080   // GPIO_Out_Cntrl - RW
+#define SB_SMBUS_REG81                  0x081   // GPIO_Status - R
+#define SB_SMBUS_REG90                  0x090   // Smbus Base Address - R
+#define SB_SMBUS_REG94                  0x094   // Reserved - R
+#define SB_SMBUS_REG98                  0x098   //
+#define SB_SMBUS_REGA0                  0x0A0   // MoreGPIOIn +C R
+#define SB_SMBUS_REGA4                  0x0A4   // MoreGPIOIn +C R
+#define SB_SMBUS_REGA8                  0x0A8   // GPIOControl +C RW
+#define SB_SMBUS_REGAC                  0x0AC   // MiscUsbEt - RW
+#define SB_SMBUS_REGAD                  0x0AD   // MiscSata
+#define SB_SMBUS_REGAE                  0x0AE
+#define SB_SMBUS_REGAF                  0x0AF   // SataIntMap - RW
+#define SB_SMBUS_REGB0                  0x0B0   // MSI Mapping Capability - R
+#define SB_SMBUS_REGB4                  0x0B4   //HPET BASE Address
+#define SB_SMBUS_REGBC                  0x0BC   // PciIntGpio - RW
+#define SB_SMBUS_REGBE                  0x0BE   // UsbIntMap - RW
+#define SB_SMBUS_REGC0                  0x0C0   // IokHiDrvSt - RW
+#define SB_SMBUS_REGD0                  0x0D0   //
+#define SB_SMBUS_REGD2                  0x0D2   // I2CbusConfig - RW
+#define SB_SMBUS_REGD3                  0x0D3   // I2CCommand - RW
+#define SB_SMBUS_REGD4                  0x0D4   // I2CSadow1- RW
+#define SB_SMBUS_REGD5                  0x0D5   // I2Csadow2- RW
+#define SB_SMBUS_REGD6                  0x0D6   // I2CBusRevision - RW
+#define SB_SMBUS_REGE0                  0x0E0   // MSI_Weigt
+#define SB_SMBUS_REGE1                  0x0E1   // MSI_Weigt
+#define SB_SMBUS_REGF0                  0x0F0   // AB_REG_BAR - RW
+#define SB_SMBUS_REGF1                  0x0F1
+#define SB_SMBUS_REGF4                  0x0F4   // WakeIoAddr- RW
+#define SB_SMBUS_REGF8                  0x0F8   // ExtendedAddrPort- RW
+#define SB_SMBUS_REGFC                  0x0FC   // ExtendedDataPort- RW
+
+
+#define SB_IDE_REG00                    0x00            // Vendor ID
+#define SB_IDE_REG02                    0x02            // Device ID
+#define SB_IDE_REG04                    0x04            // Command
+#define SB_IDE_REG06                    0x06            // Status
+#define SB_IDE_REG08                    0x08            // Revision ID/Class Code
+#define SB_IDE_REG09                    0x09            // Class Code
+#define SB_IDE_REG0A                    0x0A
+#define SB_IDE_REG0C                    0x0C            // Cace Link Size
+#define SB_IDE_REG0D                    0x0D            // Master Latency Timer
+#define SB_IDE_REG0E                    0x0E            // eader Type
+#define SB_IDE_REG0F                    0x0F            // BIST Mode Type
+#define SB_IDE_REG10                    0x10            // Base Address 0
+#define SB_IDE_REG14                    0x14            // Base Address 1
+#define SB_IDE_REG18                    0x18            // Base Address 2
+#define SB_IDE_REG1C                    0x1C            // Base Address 3
+#define SB_IDE_REG20                    0x20            // Bus Master Interface Base Address
+#define SB_IDE_REG2C                    0x2C            // Subsystem ID and Subsystem Vendor ID
+#define SB_IDE_REG34                    0x34            // MSI Capabilities Pointer
+#define SB_IDE_REG3C                    0x3C            // Interrupt Line
+#define SB_IDE_REG3D                    0x3D            // Interrupt Pin
+#define SB_IDE_REG3E                    0x3E            // Min_gnt
+#define SB_IDE_REG3F                    0x3F            // Max_latency
+#define SB_IDE_REG40                    0x40            // IDE PIO Timing
+#define SB_IDE_REG44                    0x44            // IDE Legacy DMA (Multi-words DMA) Timing Modes
+#define SB_IDE_REG48                    0x48            // IDE PIO Control
+#define SB_IDE_REG4A                    0x4A            // IDE PIO Mode
+#define SB_IDE_REG4C                    0x4C            // IDE Status
+#define SB_IDE_REG54                    0x54            // IDE Ultra DMAControl
+#define SB_IDE_REG55                    0x55            // IDE Ultra DMA Status
+#define SB_IDE_REG56                    0x56            // IDE Ultra DMA Mode
+#define SB_IDE_REG60                    0x60            // IDE PCI Retry Timing Counter
+#define SB_IDE_REG61                    0x61            // PCI Error Control
+#define SB_IDE_REG62                    0x62            // IDE Internal Control
+#define SB_IDE_REG63                    0x63            // IDE Internal Control
+#define SB_IDE_REG64                    0x64            // IDE PLL Control
+#define SB_IDE_REG68                    0x68            // IDE MSI Programmable Weigt
+#define SB_IDE_REG6C                    0x6C            // IDE Dynamic Clocking
+#define SB_IDE_REG70                    0x70            // IDE MSI Control
+#define SB_IDE_REG74                    0x74            // IDE MSI Address Register
+#define SB_IDE_REG78                    0x78            // IDE MSI Data Register
+
+
+#define SB_AZ_REG00                     0x00            // Vendor ID - R
+#define SB_AZ_REG02                     0x02            // Device ID - R/W
+#define SB_AZ_REG04                     0x04            // PCI Command
+#define SB_AZ_REG06                     0x06            // PCI Status - R/W
+#define SB_AZ_REG08                     0x08            // Revision ID
+#define SB_AZ_REG09                     0x09            // Programming Interface
+#define SB_AZ_REG0A                     0x0A            // Sub Class Code
+#define SB_AZ_REG0B                     0x0B            // Base Class Code
+#define SB_AZ_REG0C                     0x0C            // Cace Line Size - R/W
+#define SB_AZ_REG0D                     0x0D            // Latency Timer
+#define SB_AZ_REG0E                     0x0E            // eader Type
+#define SB_AZ_REG0F                     0x0F            // BIST
+#define SB_AZ_REG10                     0x10            // Lower Base Address Register
+#define SB_AZ_REG14                     0x14            // Upper Base Address Register
+#define SB_AZ_REG2C                     0x2C            // Subsystem Vendor ID
+#define SB_AZ_REG2D                     0x2D            // Subsystem ID
+#define SB_AZ_REG34                     0x34            // Capabilities Pointer
+#define SB_AZ_REG3C                     0x3C            // Interrupt Line
+#define SB_AZ_REG3D                     0x3D            // Interrupt Pin
+#define SB_AZ_REG3E                     0x3E            // Minimum Grant
+#define SB_AZ_REG3F                     0x3F            // Maximum Latency
+#define SB_AZ_REG40                     0x40            // Misc Control 1
+#define SB_AZ_REG42                     0x42            // Misc Control 2 Register
+#define SB_AZ_REG43                     0x43            // Misc Control 3 Register
+#define SB_AZ_REG44                     0x44            // Interrupt Pin Control Register
+#define SB_AZ_REG46                     0x46            // Debug Control Register
+#define SB_AZ_REG4C                     0x4C
+#define SB_AZ_REG50                     0x50            // Power Management Capability ID
+#define SB_AZ_REG52                     0x52            // Power Management Capabilities
+#define SB_AZ_REG54                     0x54            // Power Management Control/Status
+#define SB_AZ_REG60                     0x60            // MSI Capability ID
+#define SB_AZ_REG62                     0x62            // MSI Message Control
+#define SB_AZ_REG64                     0x64            // MSI Message Lower Address
+#define SB_AZ_REG68                     0x68            // MSI Message Upper Address
+#define SB_AZ_REG6C                     0x6C            // MSI Message Data
+
+#define SB_AZ_BAR_REG00                 0x00            // Global Capabilities - R
+#define SB_AZ_BAR_REG02                 0x02            // Minor Version - R
+#define SB_AZ_BAR_REG03                 0x03            // Major Version - R
+#define SB_AZ_BAR_REG04                 0x04            // Output Payload Capability - R
+#define SB_AZ_BAR_REG06                 0x06            // Input Payload Capability - R
+#define SB_AZ_BAR_REG08                 0x08            // Global Control - R/W
+#define SB_AZ_BAR_REG0C                 0x0C            // Wake Enable - R/W
+#define SB_AZ_BAR_REG0E                 0x0E            // State Cange Status - R/W
+#define SB_AZ_BAR_REG10                 0x10            // Global Status - R/W
+#define SB_AZ_BAR_REG18                 0x18            // Output Stream Payload Capability - R
+#define SB_AZ_BAR_REG1A                 0x1A            // Input Stream Payload Capability - R
+#define SB_AZ_BAR_REG20                 0x20            // Interrupt Control - R/W
+#define SB_AZ_BAR_REG24                 0x24            // Interrupt Status - R/W
+#define SB_AZ_BAR_REG30                 0x30            // Wall Clock Counter - R
+#define SB_AZ_BAR_REG38                 0x38            // Stream Syncronization - R/W
+#define SB_AZ_BAR_REG40                 0x40            // CORB Lower Base Address - R/W
+#define SB_AZ_BAR_REG44                 0x44            // CORB Upper Base Address - RW
+#define SB_AZ_BAR_REG48                 0x48            // CORB Write Pointer - R/W
+#define SB_AZ_BAR_REG4A                 0x4A            // CORB Read Pointer - R/W
+#define SB_AZ_BAR_REG4C                 0x4C            // CORB Control - R/W
+#define SB_AZ_BAR_REG4D                 0x4D            // CORB Status - R/W
+#define SB_AZ_BAR_REG4E                 0x4E            // CORB Size - R/W
+#define SB_AZ_BAR_REG50                 0x50            // RIRB Lower Base Address - RW
+#define SB_AZ_BAR_REG54                 0x54            // RIRB Upper Address - RW
+#define SB_AZ_BAR_REG58                 0x58            // RIRB Write Pointer - RW
+#define SB_AZ_BAR_REG5A                 0x5A            // RIRB Response Interrupt Count - R/W
+#define SB_AZ_BAR_REG5C                 0x5C            // RIRB Control - R/W
+#define SB_AZ_BAR_REG5D                 0x5D            // RIRB Status - R/W
+#define SB_AZ_BAR_REG5E                 0x5E            // RIRB Size - R/W
+#define SB_AZ_BAR_REG60                 0x60            // Immediate Command Output Interface - R/W
+#define SB_AZ_BAR_REG64                 0x64            // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG68                 0x68            // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG70                 0x70            // DMA Position Lower Base Address - R/W
+#define SB_AZ_BAR_REG74                 0x74            // DMA Position Upper Base Address - R/W
+#define SB_AZ_BAR_REG2030               0x2030          // Wall Clock Counter Alias - R
+
+
+#define SB_LPC_REG00                    0x00            // VID- R
+#define SB_LPC_REG02                    0x02            // DID- R
+#define SB_LPC_REG04                    0x04            // CMD- RW
+#define SB_LPC_REG06                    0x06            // STATUS- RW
+#define SB_LPC_REG08                    0x08            // Revision  ID/Class Code - R
+#define SB_LPC_REG0C                    0x0C            // Cace Line Size - R
+#define SB_LPC_REG0D                    0x0D            // Latency Timer - R
+#define SB_LPC_REG0E                    0x0E            // eader Type - R
+#define SB_LPC_REG0F                    0x0F            // BIST- R
+#define SB_LPC_REG10                    0x10            // Base Address Reg 0- RW*
+#define SB_LPC_REG2C                    0x2C            // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define SB_LPC_REG34                    0x34            // Capabilities Pointer - Ro
+#define SB_LPC_REG40                    0x40            // PCI Control - RW
+#define SB_LPC_REG44                    0x44            // IO Port Decode Enable Register 1- RW
+#define SB_LPC_REG45                    0x45            // IO Port Decode Enable Register 2- RW
+#define SB_LPC_REG46                    0x46            // IO Port Decode Enable Register 3- RW
+#define SB_LPC_REG47                    0x47            // IO Port Decode Enable Register 4- RW
+#define SB_LPC_REG48                    0x48            // IO/Mem Port Decode Enable Register 5- RW
+#define SB_LPC_REG49                    0x49            // LPC Sync Timeout Count - RW
+#define SB_LPC_REG4A                    0x4A            // IO/Mem Port Decode Enable Register 6- RW
+#define SB_LPC_REG4C                    0x4C            // Memory Range Register - RW
+#define SB_LPC_REG50                    0x50            // Rom Protect 0 - RW
+#define SB_LPC_REG54                    0x54            // Rom Protect 1 - RW
+#define SB_LPC_REG58                    0x58            // Rom Protect 2 - RW
+#define SB_LPC_REG5C                    0x5C            // Rom Protect 3 - RW
+#define SB_LPC_REG60                    0x60            // PCI Memory Start Address of LPC Target Cycles -
+#define SB_LPC_REG62                    0x62            // PCI Memory End Address of LPC Target Cycles -
+#define SB_LPC_REG64                    0x64            // PCI IO base Address of Wide Generic Port - RW
+#define SB_LPC_REG65                    0x65
+#define SB_LPC_REG66                    0x66
+#define SB_LPC_REG67                    0x67
+#define SB_LPC_REG68                    0x68            // LPC ROM Address Range 1 (Start Address) - RW
+#define SB_LPC_REG69                    0x69
+#define SB_LPC_REG6A                    0x6A            // LPC ROM Address Range 1 (End Address) - RW
+#define SB_LPC_REG6B                    0x6B
+#define SB_LPC_REG6C                    0x6C            // LPC ROM Address Range 2 (Start Address)- RW
+#define SB_LPC_REG6D                    0x6D
+#define SB_LPC_REG6E                    0x6E            // LPC ROM Address Range 2 (End Address) - RW
+#define SB_LPC_REG6F                    0x6F
+#define SB_LPC_REG70                    0x70            // Firmware ub Select - RW*
+#define SB_LPC_REG71                    0x71
+#define SB_LPC_REG72                    0x72
+#define SB_LPC_REG73                    0x73
+#define SB_LPC_REG74                    0x74            // Alternative Wide IO Range Enable- W/R
+#define SB_LPC_REG78                    0x78            // Miscellaneous Control Bits- W/R
+#define SB_LPC_REG7C                    0x7C            // TPM (trusted plant form module) reg- W/R
+#define SB_LPC_REG9C                    0x9C
+#define SB_LPC_REG80                    0x80            // MSI Capability Register- R
+#define SB_LPC_REG8C                    0x8C
+#define SB_LPC_REGA0                    0x0A0           // SPI base address
+#define SB_LPC_REGA1                    0x0A1           // SPI base address
+#define SB_LPC_REGA2                    0x0A2           // SPI base address
+#define SB_LPC_REGA3                    0x0A3           // SPI base address
+#define SB_LPC_REGA4                    0x0A4
+#define SB_LPC_REGB8                    0x0B8
+#define SB_LPC_REGBA                    0x0BA           // EcControl
+#define SB_LPC_REGBB                    0x0BB           // HostControl
+
+
+#define SB_P2P_REG00                    0x00            // VID - R
+#define SB_P2P_REG02                    0x02            // DID - R
+#define SB_P2P_REG04                    0x04            // CMD- RW
+#define SB_P2P_REG06                    0x06            // STATUS- RW
+#define SB_P2P_REG08                    0x08            // Revision ID/Class Code- R
+#define SB_P2P_REG0C                    0x0C            // CSIZE- RW
+#define SB_P2P_REG0D                    0x0D            // LTIMER- RW
+#define SB_P2P_REG0E                    0x0E            // TYPE- R
+#define SB_P2P_REG18                    0x18            // PBN- RW
+#define SB_P2P_REG19                    0x19            // SBN- RW
+#define SB_P2P_REG1A                    0x1A            // SUBBN- RW
+#define SB_P2P_REG1B                    0x1B            // SLTIMER- RW
+#define SB_P2P_REG1C                    0x1C            // IOBASE- RW
+#define SB_P2P_REG1D                    0x1D            // IOLMT- RW
+#define SB_P2P_REG1E                    0x1E            // SSTATUS- RW
+#define SB_P2P_REG20                    0x20            // MBASE- RW
+#define SB_P2P_REG21                    0x21
+#define SB_P2P_REG22                    0x22            // MLMT- RW
+#define SB_P2P_REG23                    0x23
+#define SB_P2P_REG24                    0x24            // PMBASE- RW
+#define SB_P2P_REG25                    0x25
+#define SB_P2P_REG26                    0x26            // PMLMT- RW
+#define SB_P2P_REG27                    0x27
+#define SB_P2P_REG30                    0x30            // IOBU16- RW
+#define SB_P2P_REG32                    0x32            // IOLU16- RW
+#define SB_P2P_REG34                    0x34            // ECP_PTR- R
+#define SB_P2P_REG3C                    0x3C            // INTLN- RW
+#define SB_P2P_REG3D                    0x3D            // INTPN- R
+#define SB_P2P_REG3E                    0x3E            // BCTRL- RW
+#define SB_P2P_REG40                    0x40            // CPCTRL- R/W
+#define SB_P2P_REG41                    0x41            // DCTRL- RW
+#define SB_P2P_REG42                    0x42            // CLKCTRL- R/W
+#define SB_P2P_REG43                    0x43            // ARCTRL- RW
+#define SB_P2P_REG44                    0x44            // SMLT_PERF- RW
+#define SB_P2P_REG46                    0x46            // PMLT_PERF- RW
+#define SB_P2P_REG48                    0x48            // PCDMA- RW
+#define SB_P2P_REG49                    0x49            // Additional Priority- Bits RW
+#define SB_P2P_REG4A                    0x4A            // PCICLK Enable- Bits RW
+#define SB_P2P_REG4B                    0x4B            // Misc Control RW
+#define SB_P2P_REG4C                    0x4C            // AutoClockRun control RW
+#define SB_P2P_REG50                    0x50            // Dual Address Cycle Enable and PCIB_CLK_Stop
+#define SB_P2P_REG54                    0x54            // MSI Mapping Capability
+#define SB_P2P_REG58                    0x58            // Signature Register of Microsoft Rework
+#define SB_P2P_REG64                    0x64            // Misc Control Register
+#define SB_P2P_REG65                    0x65            // Misc Control Register
+
+#define SB_PMIO2_REG00                  0x00
+#define SB_PMIO2_REG01                  0x01
+#define SB_PMIO2_REG31                  0x31
+#define SB_PMIO2_REG32                  0x32
+#define SB_PMIO2_REG33                  0x33
+#define SB_PMIO2_REG34                  0x34
+#define SB_PMIO2_REG35                  0x35
+#define SB_PMIO2_REG36                  0x36
+#define SB_PMIO2_REG37                  0x37
+#define SB_PMIO2_REG38                  0x38
+#define SB_PMIO2_REG39                  0x39
+#define SB_PMIO2_REG3A                  0x3A
+#define SB_PMIO2_REG3B                  0x3B
+#define SB_PMIO2_REG3C                  0x3C
+#define SB_PMIO2_REG3D                  0x3D
+#define SB_PMIO2_REG3E                  0x3E
+#define SB_PMIO2_REG3F                  0x3F
+#define SB_PMIO2_REG40                  0x40
+#define SB_PMIO2_REG41                  0x41
+#define SB_PMIO2_REG42                  0x42
+#define SB_PMIO2_REG43                  0x43
+#define SB_PMIO2_REG44                  0x44
+#define SB_PMIO2_REG45                  0x45
+#define SB_PMIO2_REG46                  0x46
+#define SB_PMIO2_REG47                  0x47
+#define SB_PMIO2_REG48                  0x48
+#define SB_PMIO2_REG49                  0x49
+#define SB_PMIO2_REG54                  0x54
+#define SB_PMIO2_REG58                  0x58
+#define SB_PMIO2_REG59                  0x59
+#define SB_PMIO2_REG5A                  0x5A
+#define SB_PMIO2_REG5B                  0x5B
+#define SB_PMIO2_REG5C                  0x5C
+#define SB_PMIO2_REG70                  0x70
+#define SB_PMIO2_REGE5                  0xE5
+
+#define SB_SPI_MMIO_REG0C               0x0C            //SPI_Cntrl1 Register
+
+
+//Bus 0 Device 0x18 Function 0  HyperTransfer
+//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits.
+#define HT_LINK_REG89           0x89
+#define HT_LINK_REGA9           0xA9
+#define HT_LINK_REGC9           0xC9
+#define HT_LINK_REGE9           0xE9
+
+//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits.
+#define HT_LINK_REG98           0x98
+#define HT_LINK_REGB8           0xB8
+#define HT_LINK_REGD8           0xD8
+#define HT_LINK_REGF8           0xF8
+
+//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits.
+#define HT_LINK_REG9C           0x9C
+#define HT_LINK_REGBC           0xBC
+#define HT_LINK_REGDC           0xDC
+#define HT_LINK_REGFC           0xFC
+
+//DRAM CS Base Address Register D18F2x40/x48/x50/x58
+#define DCT_REG40           0x40
+#define DCT_REG48           0x48
+#define DCT_REG50           0x50
+#define DCT_REG58           0x58
+
+//DRAM Configuration Low Register D18F2x90/x91/x92/x93
+#define DCT_REG90           0x90
+#define DCT_REG91           0x91
+#define DCT_REG92           0x92
+#define DCT_REG93           0x93
+
+#pragma pack(pop)
+
+#endif          //#ifndef _AMD_SB700_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
new file mode 100644
index 0000000..7d5b4f4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c
@@ -0,0 +1,572 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include        "Platform.h"
+
+
+REG8MASK sbEarlyPostByteInitTable[]={
+        // SMBUS Device(Bus 0, Dev 20, Func 0)
+        {0x00, SMBUS_BUS_DEV_FUN, 0},
+        {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00},                  //Make BAR registers of smbus visible.
+        {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)},  //Program the version information
+        {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)},
+        {SB_SMBUS_REG24+2, 0x00, RC_Information},
+        {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator},
+        {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3},                  //Make BAR registers of smbus invisible.
+        {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5},  //Disable Timer IRQ enhancement for proper operation of the 8254 timer.
+                                                        // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts
+        {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3},    // Initialize SATA to default values, SATA Enabled,
+                                                                // Combined mode enabled, SATA as primary, power saving enable
+        {SB_SMBUS_REGAF, 0xE3, 6 << 2},                 // Set SATA Interrupt to INTG#
+        {SB_SMBUS_REG68, BIT3, 0 },                             //      First disable all usb controllers and then enable then according to setup selection
+        {0xFF, 0xFF, 0xFF},
+
+        // IDE Device(Bus 0, Dev 20, Func 1)
+        {0x00, IDE_BUS_DEV_FUN, 0},
+        {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5},                  // Enabling IDE Explicit Pre-Fetch  IDE PCI Config 0x62[8]=0
+                                                        // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
+        {0xFF, 0xFF, 0xFF},
+
+        // Azalia Device(Bus 0, Dev 20, Func 2)
+        {0x00, AZALIA_BUS_DEV_FUN, 0},
+        {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0},
+        {0xFF, 0xFF, 0xFF},
+
+        // LPC Device(Bus 0, Dev 20, Func 3)
+        {0x00, LPC_BUS_DEV_FUN, 0},
+
+        {SB_LPC_REG40, ~(UINT8)BIT2, BIT2},            // Enabling LPC DMA Function  0x40[2]
+        {SB_LPC_REG78, ~(UINT8)BIT1, 00},                      // Disables MSI capability
+        {0xFF, 0xFF, 0xFF},
+
+        // P2P Bridge(Bus 0, Dev 20, Func 4)
+        {0x00, SBP2P_BUS_DEV_FUN, 0},
+
+        {SB_P2P_REG64+1, 0xFF, BIT7+BIT6},      //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01
+                                                                                //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01
+        {SB_P2P_REG64+2, 0xFF, BIT4},   //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+
+        {SB_P2P_REG0D, 0x00, 0x40},             //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+        {SB_P2P_REG1B, 0x00, 0x40},             // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+
+        {0xFF, 0xFF, 0xFF},
+
+        // SATA Device(Bus 0, Dev 17, Func 0)
+        {0x00, SATA_BUS_DEV_FUN, 0},
+        {SB_SATA_REG44, 0xff, BIT0},    // Enables the SATA watchdog timer register prior to the SATA BIOS post
+        {SB_SATA_REG40+3, 0xff, BIT5},  // RPR setting: Disable the testing/enhancement mode    SATA_PCI_config 0x40 [29] = 1
+        {SB_SATA_REG48+2, 0xff, BIT5},  // RPR setting: Disable the testing/enhancement mode    SATA_PCI_config 0x48 [24] = 1, [21] = 1
+        {SB_SATA_REG48+3, 0xff, BIT0},
+        {SB_SATA_REG44 + 2, 0, 0x10},   // Program watchdog timer with 16 retries before timer time-out.
+        {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbEarlyPostPmioInitTbl[]={
+        // index                andmask ormask
+        {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b
+        {SB_PMIO_REG01, 0xff, BIT1},
+        {SB_PMIO_REG0E, 0xff, BIT2 + BIT3},
+        {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)},   // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn
+        {SB_PMIO_REG61, 0xFF, 0x40},            // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB
+        {SB_PMIO_REG59, 0xFC, 0x00 },           // Clear the flash controller bits BIT1:0
+        {SB_PMIO_REG01, 0xFF, 0x97 },           // Clear all the status
+        {SB_PMIO_REG05, 0xFF, 0xFF },
+        {SB_PMIO_REG06, 0xFF, 0xFF },
+        {SB_PMIO_REG07, 0xFF, 0xFF },
+        {SB_PMIO_REG0F, 0xFF, 0x1F },
+        {SB_PMIO_REG1D, 0xFF, 0xFF },
+        {SB_PMIO_REG39, 0xFF, 0xFF },
+        {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2},          //Turn on BLink LED
+        {SB_PMIO_REG67, 0xFF, 0x06},            // C State enable, must be set in order to exercise C state
+        {SB_PMIO_REG68, 0x38, 0x84},
+        {SB_PMIO_REG8D, 0xFF, 0x01},            // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure
+        {SB_PMIO_REG84, 0xFD, BIT3+BIT0},
+        {SB_PMIO_REG53, 0xFF, BIT7+BIT6},       //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock
+                                                                                //is either 25 or 100Mhz and so the default acpi clock is actually
+                                                                                //running at 12.5Mhz and so the system time will run slow.  We have
+                                                                                //generated another internal clock which runs at 14.318Mhz which is the
+                                                                                //correct frequency.  We should set this bit to turn on this feature PMIO_REG53[6]=1
+                                                                                //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period
+                                                                                //increase to 30.8 ns.
+        {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1},  //USB Advanced Sleep Control, Enables USB EHCI controller
+                                                                                                        //to sleep for 6 uframes in stead of the standard 10us to
+                                                                                                        //improve power saving.
+        {SB_PMIO_REGD7, 0xFF, BIT6+BIT1},
+
+};
+
+
+// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also
+void    commonInitEarlyBoot(AMDSBCFG* pConfig) {
+        UINT16       dwTempVar;
+        CPUID_DATA   CpuId;
+        CPUID_DATA   CpuId_Brand;
+        UINT8        dbValue;
+        UINT32       ddValue;
+  UINT8        Family, Model, Stepping;
+
+        TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+        CpuidRead (0x01, &CpuId);
+        CpuidRead (0x80000001, &CpuId_Brand);           //BrandID
+
+        //Early post initialization of pci config space
+        programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) );
+
+        // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
+        RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
+
+
+        #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+        //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
+        //changing it.
+        ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
+        if ( (dwTempVar == 0x08) || (dwTempVar == 0x00))
+                RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF
+        #endif
+
+        if      (pConfig->AzaliaController == 1)
+                RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+        else
+                RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+
+        //Disable or Enable PCI Clks based on input
+        RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
+        RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) );
+        ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar);    // Read Arbiter address, Arbiter address is in PMIO 2Ch
+        RWIO(dwTempVar, AccWidthUint8, 0, 0);                   // Write 0 to enable the arbiter
+
+        abLinkInitBeforePciEnum(pConfig);                       // Set ABCFG registers
+        // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package
+        ddValue = CpuId.REG_EAX & 0x00FF00F0;
+    dbValue = 1;
+
+        if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) {
+                if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+                        //Orochi processor G34/C32, set to 10us
+                        dbValue = 10;
+                }
+                else {
+                        // Orochi processor AM3, set to 5us
+                        dbValue = 5;
+                }
+        }
+
+        if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) {
+        //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us
+          dbValue = 10;
+        }
+
+
+        RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue);
+
+        // Enable/Disable watchdog timer
+        RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable));
+
+        // Per SB700/SP5100 RPR 2.5
+        //
+        // Enable C1e stutter timer for any system with chip revision >= A14
+        // Set SMBUS:0x5c[22:16] = 16  -- Set amount of idle time to 16ms
+        //
+
+        if (getRevisionID() >= SB700_A14) {
+          dwTempVar = 0x0010;
+
+    // Set PMIO:0xcb[5] = 1  -- AutoStutterTimerEn, set 1 to enable
+    // Set PMIO:0xcb[6] = 1  -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment
+          RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5);
+
+      Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16);
+      Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4);
+      Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f);
+
+    // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled:
+    // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah
+    // Set SMBUS:0x5c[22:16] = 20  -- Set amount of idle time to 20ms
+          if (IsLs2Mode() && (Family == 0x10)) {
+        switch( Model ){
+          case 0x4:
+          case 0x5:
+                     if( Stepping >= 3 )  dwTempVar = 0x14;
+                     break;
+          case 0x6:
+                     if( Stepping >= 2 )  dwTempVar = 0x14;
+                     break;
+          case 0x8:
+                     if( Stepping >= 1 )  dwTempVar = 0x14;
+                     break;
+          case 0x9:
+                     if( Stepping >= 1 )  dwTempVar = 0x14;
+                     break;
+          case 0xA:
+                     dwTempVar = 0x14;
+                     break;
+        }
+          }
+          // Set SMBUS:0x5c[7] = 1       -- CheckC3, set 1 to check for C3 state
+          RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7);
+        }
+
+        //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor.
+        ddValue = CpuId.REG_EAX;
+        if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) {
+          //
+          // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a
+          // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically
+          // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the
+          // BM_STS bit to be set and therefore causing the C state logic to exit.
+          //
+          // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic
+          // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3
+          RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5);
+
+          // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT#
+          RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2);
+
+          // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e
+          // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry
+          RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4);
+
+
+          // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER
+          // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic.
+          // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the
+          // HALT_EXIT message as a break event.
+          //
+          // Set ServerCEn
+          RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+          // Enable counting HALT
+          // PMIO:0xc9[4]   = CountHaltMsgEn
+          // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message
+          RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1);
+        }
+
+        c3PopupSetting(pConfig);
+
+        TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+}
+
+
+void    commonInitEarlyPost(AMDSBCFG* pConfig){
+        //early post initialization of pmio space
+        programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) );
+        CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
+}
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblEntry600[]={
+        // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1
+        // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of
+        // SMI# and IO is important for the IO trap to work properly.
+        {ABCFG,SB_AB_REG10090           ,BIT16+BIT8             ,BIT16+BIT8                     },
+        // Enabling UpStream DMA Access AXCFG: 0x04[2]=1
+        {AXCFG,SB_AB_REG04              ,BIT2                   ,BIT2                   },
+        // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1
+        {ABCFG,SB_AB_REG80              ,BIT17+BIT18            ,BIT17+BIT18    },
+        // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions)
+        // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation
+        // Enabling Additional Address Bits Checking in Downstream Register Programming
+        // ABCFG 0x9C[1] = 1
+        {ABCFG,SB_AB_REG9C              ,BIT8+BIT1+BIT0                 ,BIT8+BIT1+BIT0 },
+        // Enabling IDE/PCIB Prefetch for Performance Enhancement
+        // IDE prefetch    ABCFG 0x10060 [17] = 1   ABCFG 0x10064 [17] = 1
+        // PCIB prefetch   ABCFG 0x10060 [20] = 1   ABCFG 0x10064 [20] = 1
+        {ABCFG,SB_AB_REG10060   ,BIT17+BIT20            ,BIT17+BIT20            },      //  IDE+PCIB prefetch enable
+        {ABCFG,SB_AB_REG10064   ,BIT17+BIT20            ,BIT17+BIT20            },      //  IDE+PCIB prefetch enable
+        // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+        // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+        {ABCFG,SB_AB_REG94              ,BIT20                  ,BIT20+0x00FEE                  },
+        // Programming cycle delay for AB and BIF clock gating
+        // Enabling AB and BIF Clock Gating
+        // Enabling AB Int_Arbiter Enhancement
+        // Enabling Requester ID
+        {ABCFG,SB_AB_REG10054,  0x00FFFFFF      , 0x010407FF    },
+        {ABCFG,SB_AB_REG98      ,       0xFFFF00FF      , 0x00014700    },      // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1
+//      {ABCFG,SB_AB_REG54      ,       0x00FF0000      , 0x01040000    },
+        {ABCFG,SB_AB_REG54      ,       0x00FF0000      , 0x00040000    },
+
+        {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+        {-1, -1, -1, -1                                                                         },
+};
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblForA15[]={
+
+        //SMI Reordering fix
+        {ABCFG, SB_AB_REG90             ,BIT21                  , BIT21 },
+        {ABCFG, SB_AB_REG9C             ,BIT15+BIT9+BIT5        ,BIT15+BIT9+BIT5},
+
+        //Posted pass NP Downstream feature
+        {AX_INDXC,      SB_AB_REG02,    BIT9            ,BIT9           },
+        {ABCFG,         SB_AB_REG9C,    BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6},
+        {ABCFG,         SB_AB_REG1009C, BIT5+BIT4       , BIT5+BIT4},
+
+        //Posted pass NP upstream feature
+        {ABCFG,         SB_AB_REG58,    BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11},
+
+        //64 bit Non-posted memory write support
+        {AX_INDXC,      SB_AB_REG02,    BIT10           ,BIT10          },
+
+        {ABCFG,         SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9  , BIT12+BIT11+BIT10+BIT9},
+
+        {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+        {-1, -1, -1, -1                                                                         },
+};
+
+
+// abLinkInitBeforePciEnum - Set ABCFG registers
+void    abLinkInitBeforePciEnum(AMDSBCFG* pConfig){
+        ABTBLENTRY      *pAbTblPtr;
+
+        // disable PMIO decoding when AB is set
+        RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0);
+
+        pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]);
+        abcfgTbl(pAbTblPtr);
+
+        if (getRevisionID() > SB700_A11){
+                //Enable OHCI Prefetch
+                writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0);
+                //Register bit to maintain correct ordering of SMI and IO write completion
+                writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8);
+        }
+
+        if (getRevisionID() >= SB700_A14){
+                //Enable fix for TT SB01345
+                writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17);
+                //Disable IO Write and SMI ordering enhancement
+                writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF));
+        }
+
+        if (getRevisionID() >= SB700_A15) {
+                pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]);
+                abcfgTbl(pAbTblPtr);
+        }
+
+
+        // enable pmio decoding after ab is configured
+        // or   BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2
+        RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+}
+
+
+void    abcfgTbl(ABTBLENTRY* pABTbl){
+        UINT32  ddValue;
+
+        while ((pABTbl->regType) != 0xFF){
+                TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+                if (pABTbl->regType > AX_INDXP){
+                        ddValue = pABTbl->regIndex | (pABTbl->regType << 30);
+                        writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+                }
+                else{
+                        ddValue = 0x30 | (pABTbl->regType << 30);
+                        writeAlink(ddValue, pABTbl->regIndex);
+                        ddValue = 0x34 | (pABTbl->regType << 30);
+                        writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+                }
+                ++pABTbl;
+        }
+
+        //Clear ALink Access Index
+        ddValue = 0;
+        WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
+        TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
+}
+
+
+// programSubSystemIDs - Config Subsystem ID for all SB devices.
+void    programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM       *pStaticOptions){
+        UINT32  ddTempVar;
+        UINT16  dwDeviceId;
+
+        RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid);
+        RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid);
+        RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid);
+        RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid);
+        RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid);
+
+        RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid);
+        RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid);
+
+        RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid);
+        RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid);
+        RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid);
+        RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid);
+
+        ddTempVar = pStaticOptions->SataIDESsid;
+        if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) )
+                ddTempVar = pStaticOptions->SataAHCISsid;
+
+        ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+        if ((pConfig->SataClass) == RAID_MODE){
+                ddTempVar = pStaticOptions->SataRAIDSsid;
+                if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID)
+                        ddTempVar = pStaticOptions->SataRAID5Ssid;
+        }
+
+        if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) {
+                ddTempVar = pStaticOptions->SataAHCISsid;
+        }
+        RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
+}
+
+void    commonInitLateBoot(AMDSBCFG* pConfig){
+        UINT8   dbValue;
+        UINT32  ddVar;
+
+        // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+        // programmed during early post.
+        // RPR 4.5 Master Latency Timer
+        // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40
+        // Enables the PCIB to retain ownership of the bus on the
+        // Primary side and on the Secondary side when GNT# is deasserted.
+        //mov   BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h
+        //mov   BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h
+        dbValue = 0x40;
+        WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue);
+        WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue);
+
+        //SB P2P AutoClock control settings.
+        ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
+        WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar);
+        ddVar = (pConfig->PcibClkStopOverride);
+        RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
+
+        if (pConfig->MobilePowerSavings){
+                //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to
+                //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off.
+                RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4);
+                if (!getClockMode()){
+                        if  (!(pConfig->UsbIntClock) ){
+                                //If the external clock is used, the second PLL should be shut down
+                                RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0);
+                                // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting  PMIO 0xD4[7]=1
+                                RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7);
+                                //Disable unused clocks
+                                RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E);
+                        }
+                }
+                writeAlink(0x30, SB_AB_REG40);
+                writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A);
+
+        }
+        else{
+                //Don't shutoff RTC clock
+                RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0);
+                //Dont disable second PLL
+                RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0);
+                //Enable the 25Mhz oscillator
+                RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0);
+                RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00);
+        }
+}
+
+
+void
+hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions)
+{
+  DESCRIPTION_HEADER*   pHpetTable;
+
+  if (pConfig->HpetTimer == 1) {
+    UINT8      dbTemp;
+
+    RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7);
+    // Program the HPET BAR address
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase);
+
+    // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1
+    // Enable HPET MSI support only when HpetMsiDis == 0
+    dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4;
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp);
+    // Program HPET default clock period
+    if (getRevisionID() >= SB700_A13) {
+      RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E);
+    }
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+    // Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+  }
+  else {
+    if (!(pConfig->S3Resume)) {
+//      pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH');
+      pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H'));
+      if (pHpetTable != NULL) {
+//        pHpetTable->Signature = 'HPET';
+        pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H');
+      }
+    }
+  }
+}
+
+
+void c3PopupSetting(AMDSBCFG* pConfig){
+        UINT8   dbTemp;
+        CPUID_DATA   CpuId;
+
+        CpuidRead (0x01, &CpuId);
+        //RPR 2.3 C-State and VID/FID Change
+        dbTemp = GetNumberOfCpuCores();
+        if (dbTemp > 1){
+                //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+                //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+                //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
+                                                   //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+                RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2);
+        }
+
+        //SB700 needs to changed for RD790 support
+        //PM_IO 0x8F [4] = 0 for system with RS690
+        //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+        //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+        //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB
+        RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5);
+
+        //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+        //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+        //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+        //link is disconnected.
+    //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same
+    dbTemp = (IsServer())? 0x14 : 0x10;
+        RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp);
+
+        //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+        //delay will allow USB DMA to go on in a continous manner
+        RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10);
+
+        //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time
+        RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7);
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c
new file mode 100644
index 0000000..130dbc4
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.c
@@ -0,0 +1,108 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+UINT8	isEcPresent(){
+	UINT8	dbFlag;
+	UINT16	dwVar0;
+
+	//Read the EC configuration register base address from LPCCfg_A4[15:1]
+	//Write 0x5A to the EC config index register to unlock the access
+	//Write 0x20 to the EC config index register to select the device ID register
+	//Read the value of device ID register from the EC config data register
+	//If the value read is 0xB7, then EC is enabled.
+	//Write 0xA5 to re-lock the EC config index register if EC is enabled.
+
+	ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0);
+	dwVar0 &= 0xFFFE;
+	RWIO(dwVar0, AccWidthUint8, 0, 0x5A);
+	RWIO(dwVar0, AccWidthUint8, 0, 0x20);
+	ReadIO(dwVar0+1, AccWidthUint8, &dbFlag);
+	RWIO(dwVar0, AccWidthUint8, 0, 0xA5);
+
+	return ( dbFlag == 0xB7);
+}
+
+void
+getSbInformation	(
+SB_INFORMATION *sbInfo){
+	UINT16 dwDevId;
+	UINT8	dbRev;
+
+	ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId);
+	ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev);
+	sbInfo->sbModelMask = SB_MODEL_UNKNOWN;
+	if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){
+		sbInfo->sbModelMask |= SB_MODEL_SB700;
+		sbInfo->sbModelMask |= SB_MODEL_SR5690;
+		sbInfo->sbRev = dbRev;
+		ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev);
+		if (dbRev & 01)
+			sbInfo->sbModelMask |= SB_MODEL_SB750;
+		if (isEcPresent())
+			sbInfo->sbModelMask |= SB_MODEL_SB710;
+		return;
+		}
+}
+
+
+SB_CAPABILITY_SETTING
+getSbCapability	(
+SB_CAPABILITY_ITEM sbCapabilityItem
+)
+{
+	SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN;
+	UINT32 ddTemp0;
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+	ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+
+	if (sbCapabilityItem < Sb_Unknown_Capability)
+		sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03);
+
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+	return sbCapSetting;
+}
+
+
+void
+setSbCapability	(
+SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting
+)
+{
+	UINT32 ddTemp0;
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+	ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+	if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) )
+		ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1));
+	WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+}
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h
new file mode 100644
index 0000000..e737bc9
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBCMNLIB.h
@@ -0,0 +1,89 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBLIB_H_
+#define _AMD_SBLIB_H_
+
+//SB7xx Family
+#define	SB7xx_DEVICE_ID	0x4385
+#define	SB700	0x00
+#define	SB750	0x01
+#define	SB710	0x02
+
+//SB800 Family
+#define	SB800	0x10
+
+#define SB_UNKNOWN	0xFF
+
+//SB700 Revision IDs
+#define	SB700_A11	0x39
+#define	SB700_A12	0x3A
+#define	SB700_A13	0x3B
+#define	SB700_A14	0x3C
+
+#define	SB_Rev_Sb7xx_A11	0x39
+#define	SB_Rev_Sb7xx_A12	0x3A
+#define	SB_Rev_Sb7xx_A13	0x3B
+#define	SB_Rev_Sb7xx_A14	0x3C
+
+
+typedef enum {
+  Sb_Raid0_1_Capability,                 ///
+  Sb_Raid5_Capability,                   ///
+  Sb_Ahci_Capability,                   ///
+  Sb_Unknown_Capability
+} SB_CAPABILITY_ITEM;
+
+
+typedef enum {
+  Sb_Cap_Setting_Auto,
+  Sb_Cap_Setting_Enabled,
+  Sb_Cap_Setting_Disabled,
+  Sb_Cap_Setting_Unknown
+} SB_CAPABILITY_SETTING;
+
+
+#define SB_MODEL_SB700	BIT0
+#define SB_MODEL_SB750	BIT1
+#define SB_MODEL_SB710	BIT2
+#define SB_MODEL_SR5690	BIT3
+#define SB_MODEL_UNKNOWN BIT31
+
+typedef struct
+{
+	UINT32	sbModelMask;
+	UINT8	sbRev;
+}SB_INFORMATION;
+
+
+void getSbInformation	(SB_INFORMATION *sbInfo);
+SB_CAPABILITY_SETTING getSbCapability	(SB_CAPABILITY_ITEM sbCapabilityItem);
+void setSbCapability	(SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting);
+
+#endif	//#ifndef _AMD_SBLIB_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SBDEF.h b/src/vendorcode/amd/cimx/sb700/SBDEF.h
new file mode 100644
index 0000000..01fc1b5
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBDEF.h
@@ -0,0 +1,166 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBDEF_H_
+#define _AMD_SBDEF_H_
+
+//AMD Library Routines
+
+UINT64
+MsrRead (
+  IN       UINT32 MsrAddress
+  );
+
+VOID
+MsrWrite (
+  IN       UINT32 MsrAddress,
+  IN			 UINT64 Value
+  );
+
+void	ReadIO(UINT16	Address, UINT8	OpFlag, void *Value);
+void	WriteIO(UINT16	Address, UINT8	OpFlag, void *Value);
+void	ReadPCI(UINT32	Address, UINT8	OpFlag, void *Value);
+void	WritePCI(UINT32 Address,UINT8	OpFlag, void *Value);
+void	RWPCI(UINT32 Address,UINT8	OpFlag,UINT32 Mask,UINT32	Data);
+void	ReadIndexPCI32(UINT32	PciAddress,UINT32 IndexAddress,void* Value);
+void	WriteIndexPCI32(UINT32	PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value);
+void	RWIndexPCI32(UINT32	PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32	Mask,UINT32	Data);
+void	RWIO (UINT16	Address, UINT8	OpFlag, UINT32	Mask, UINT32 Data);
+void	ReadMEM(UINT32	Address,UINT8 OpFlag, void*	Value);
+void	WriteMEM(UINT32	Address,UINT8 OpFlag, void*	Value);
+void    RWMEM(UINT32	Address,UINT8	OpFlag,UINT32	Mask,UINT32 Data);
+UINT32	IsFamily10(void);
+UINT64	ReadMSR(UINT32	Address);
+void	WriteMSR(UINT32	Address,UINT64	Value);
+void	RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value);
+void*	LocateImage(UINT32 Signature);
+void*	CheckImage(	UINT32	Signature, void*	ImagePtr);
+void	Stall(UINT32	uSec);
+void	Reset(void);
+CIM_STATUS	RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8  BufferSize, UINT8* BufferPrt);
+void	InitSerialOut(void);
+void	ReadPMIO(UINT8 Address, UINT8	OpFlag, void* Value);
+void	WritePMIO(UINT8 Address, UINT8	OpFlag, void* Value);
+void	RWPMIO(UINT8 Address, UINT8	OpFlag, UINT32 AndMask, UINT32 OrMask);
+void	ReadPMIO2(UINT8 Address, UINT8	OpFlag, void* Value);
+void	WritePMIO2(UINT8 Address, UINT8	OpFlag, void* Value);
+void	RWPMIO2(UINT8 Address, UINT8	OpFlag, UINT32 AndMask, UINT32 OrMask);
+void	outPort80(UINT32 pcode);
+UINT8	GetNumberOfCpuCores(void);
+UINT8	ReadNumberOfCpuCores(void);
+UINT8	GetByteSum(void* pData, UINT32	Length);
+UINT32	readAlink(UINT32 Index);
+void	writeAlink(UINT32 Index,UINT32	Data);
+
+//----------------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------------
+void	azaliaInitAfterPciEnum (AMDSBCFG* pConfig);
+
+void	SendBytePort(UINT8 Data);
+void	SendStringPort(char* pstr);
+void	ItoA(UINT32 Value,int Radix,char* pstr);
+AMDSBCFG* getConfigPointer(void);
+void	saveConfigPointer(AMDSBCFG* pConfig);
+
+
+UINT32	GetFixUp(void);
+
+void	sataInitAfterPciEnum(AMDSBCFG*	pConfig);
+void	sataInitBeforePciEnum(AMDSBCFG*	pConfig);
+void	sataInitLatePost(AMDSBCFG*	pConfig);
+void	sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5);
+void	sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5);
+void	forceOOB(UINT32	ddBar5);
+void	shutdownUnconnectedSataPortClock(AMDSBCFG*	pConfig, UINT32 ddBar5);
+void	restrictSataCapabilities(AMDSBCFG* pConfig);
+
+
+void	commonInitEarlyBoot(AMDSBCFG* pConfig);
+void	commonInitEarlyPost(AMDSBCFG* pConfig);
+void	setRevisionID(void);
+UINT8	getRevisionID(void);
+UINT8	IsServer (void);
+UINT8	IsLs2Mode (void);
+void	abLinkInitBeforePciEnum(AMDSBCFG* pConfig);
+void	abcfgTbl(ABTBLENTRY* pABTbl);
+void	programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM	*pStaticOptions);
+void	commonInitLateBoot(AMDSBCFG* pConfig);
+void	hpetInit(AMDSBCFG* pConfig, BUILDPARAM	*pStaticOptions);
+void	c3PopupSetting(AMDSBCFG* pConfig);
+
+void	sbBeforePciInit (AMDSBCFG* pConfig);
+void	sbAfterPciInit(AMDSBCFG* pConfig);
+void	sbLatePost(AMDSBCFG* pConfig);
+void	sbBeforePciRestoreInit(AMDSBCFG* pConfig);
+void	sbAfterPciRestoreInit(AMDSBCFG* pConfig);
+void	sbSmmAcpiOn(AMDSBCFG* pConfig);
+UINT32	GetPciebase(void);
+UINT32	CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig);
+void	sbSmmService(AMDSBCFG* pConfig);
+void	softwareSMIservice(void);
+
+void	sbPowerOnInit (AMDSBCFG *pConfig);
+void	programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize);
+void	programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize);
+UINT8	getClockMode(void);
+UINT16	readStrapStatus	(void);
+
+void	usbInitBeforePciEnum(AMDSBCFG* pConfig);
+void	usbInitAfterPciInit(AMDSBCFG* pConfig);
+void	usbInitMidPost(AMDSBCFG* pConfig);
+void	programOhciMmioForEmulation(void);
+
+void	fcInitBeforePciEnum(AMDSBCFG* pConfig);
+
+unsigned char ReadIo8 (IN unsigned short Address);
+unsigned short ReadIo16 (IN unsigned short Address);
+unsigned int ReadIo32 (IN unsigned short Address);
+void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
+void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
+void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
+unsigned long long  ReadTSC (void);
+void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data);
+
+#ifndef	NO_EC_SUPPORT
+void	EnterEcConfig(void);
+void	ExitEcConfig(void);
+void	ReadEC8(UINT8 Address, UINT8* Value);
+void	WriteEC8(UINT8 Address, UINT8* Value);
+void	RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask);
+void	ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig);
+void	ecInitBeforePciEnum(AMDSBCFG* pConfig);
+void	ecInitLatePost(AMDSBCFG* pConfig);
+#endif
+UINT8	isEcPresent(void);
+
+void DispatcherEntry(void *pConfig);
+AGESA_STATUS AmdSbDispatcher(void *pConfig);
+void AMDFamily15CpuLdtStopReq(void);
+
+#endif	//#ifndef _AMD_SBDEF_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SBMAIN.c b/src/vendorcode/amd/cimx/sb700/SBMAIN.c
new file mode 100644
index 0000000..7468eb2
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBMAIN.c
@@ -0,0 +1,289 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+#ifndef	B1_IMAGE
+
+BUILDPARAM	DfltStaticOptions={
+	BIOS_SIZE,							// BIOS Size
+	LEGACY_FREE,						// Legacy Free Option
+	0x00,								// Dummy space holder
+
+	0x00,								// ECKbd disable/enable
+	0x00,								// EcChannel0 disable/enable
+	0x00,								// Dummy space holder1
+
+	SMBUS0_BASE_ADDRESS,				// Smbus Base Address;
+	SMBUS1_BASE_ADDRESS,				// Smbus Base Address;
+	SIO_PME_BASE_ADDRESS,				// SIO PME Base Address
+	WATCHDOG_TIMER_BASE_ADDRESS,		// Watchdog Timer Base Address
+	SPI_BASE_ADDRESS,
+
+	PM1_EVT_BLK_ADDRESS,				//	AcpiPm1EvtBlkAddr;
+	PM1_CNT_BLK_ADDRESS,				//	AcpiPm1CntBlkAddr;
+	PM1_TMR_BLK_ADDRESS,				//	AcpiPmTmrBlkAddr;
+	CPU_CNT_BLK_ADDRESS,				//	CpuControlBlkAddr;
+	GPE0_BLK_ADDRESS,					//  AcpiGpe0BlkAddr;
+	SMI_CMD_PORT,						//	SmiCmdPortAddr;
+	ACPI_PMA_CNT_BLK_ADDRESS,			//	AcpiPmaCntBlkAddr;
+
+	EC_LDN5_MAILBOX_ADDRESS,
+	EC_LDN5_IRQ,
+	EC_LDN9_MAILBOX_ADDRESS,			//	EC LDN9 Mailbox address
+	RESERVED_VALUE,
+	RESERVED_VALUE,
+	RESERVED_VALUE,
+	RESERVED_VALUE,
+
+	HPET_BASE_ADDRESS,					// HPET Base address
+
+	SATA_IDE_MODE_SSID,
+	SATA_RAID_MODE_SSID,
+	SATA_RAID5_MODE_SSID,
+	SATA_AHCI_SSID,
+
+	OHCI0_SSID,
+	OHCI1_SSID,
+	EHCI0_SSID,
+	OHCI2_SSID,
+	OHCI3_SSID,
+	EHCI1_SSID,
+	OHCI4_SSID,
+	SMBUS_SSID,
+	IDE_SSID,
+	AZALIA_SSID,
+	LPC_SSID,
+	P2P_SSID,
+};
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB Before PCI INIT
+*
+* Arguments:
+*
+*   pConfig - SBconfiguration
+*
+* Returns:
+*
+*   void
+*
+**********************************************************************************/
+void	sbBeforePciInit (AMDSBCFG* pConfig){
+	BUILDPARAM	*pStaticOptions;
+
+	pStaticOptions = &pConfig->BuildParameters;
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+	commonInitEarlyBoot(pConfig);
+	commonInitEarlyPost(pConfig);
+#ifndef	NO_EC_SUPPORT
+	ecInitBeforePciEnum(pConfig);
+#endif
+	usbInitBeforePciEnum(pConfig);				// USB POST TIME Only
+	fcInitBeforePciEnum(pConfig);				// Preinit flash controller
+	sataInitBeforePciEnum(pConfig);						// Init SATA class code and PHY
+	programSubSystemIDs(pConfig, pStaticOptions);		// Set subsystem/vendor ID
+
+	TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description:	Config SB After PCI INIT
+*
+* Arguments:
+*
+*   pConfig - SBconfiguration
+*
+* Returns:	void
+*
+*  Reference:	atiSbAfterPciInit
+*
+**********************************************************************************/
+void	sbAfterPciInit(AMDSBCFG* pConfig){
+	BUILDPARAM	*pStaticOptions;
+
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+
+	pStaticOptions = &pConfig->BuildParameters;
+	usbInitMidPost(pConfig);				//usb initialization which is required only during post
+	usbInitAfterPciInit(pConfig);			// Init USB MMIO
+	sataInitAfterPciEnum(pConfig);			// SATA port enumeration
+	azaliaInitAfterPciEnum(pConfig);		// Detect and configure High Definition Audio
+
+	TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description:	Config SB during late POST
+*
+* Arguments:
+*
+*   pConfig - SBconfiguration
+*
+* Returns:	void
+*
+*  Reference:	atiSbLatePost
+*
+**********************************************************************************/
+void	sbLatePost(AMDSBCFG* pConfig){
+	UINT16	dwVar;
+	BUILDPARAM	*pStaticOptions;
+	pStaticOptions = &pConfig->BuildParameters;
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+	ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
+	if (dwVar != SB7XX_DEVICE_ID){
+		// Display message that the SB is wrong and stop the system
+		TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n"));
+		for(;;);
+	}
+	commonInitLateBoot(pConfig);
+	sataInitLatePost(pConfig);
+	hpetInit(pConfig, pStaticOptions);		// SB Configure HPET base and enable bit
+#ifndef	NO_EC_SUPPORT
+	ecInitLatePost(pConfig);
+#endif
+}
+
+/*********************************************************************************
+*
+* Routine Description:	Config SB before ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+*   pConfig - SBconfiguration
+*
+* Returns:	void
+*
+*  Reference:	AtiSbBfPciRestore
+*
+**********************************************************************************/
+void	sbBeforePciRestoreInit(AMDSBCFG* pConfig){
+	BUILDPARAM	*pStaticOptions;
+
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+
+	pConfig->S3Resume = 1;
+
+	pStaticOptions = &pConfig->BuildParameters;
+	commonInitEarlyBoot(pConfig);				// set /SMBUS/ACPI/IDE/LPC/PCIB
+	abLinkInitBeforePciEnum(pConfig);			// Set ABCFG registers
+	usbInitBeforePciEnum(pConfig);				// USB POST TIME Only
+	fcInitBeforePciEnum(pConfig);				// Preinit flash controller
+	sataInitBeforePciEnum(pConfig);
+	programSubSystemIDs(pConfig, pStaticOptions);				// Set subsystem/vendor ID
+}
+
+
+/*********************************************************************************
+*
+* Routine Description:	Config SB after ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+*   pConfig - SBconfiguration
+*
+* Returns:	void
+*
+*  Reference:	AtiSbAfPciRestore
+*
+**********************************************************************************/
+void	sbAfterPciRestoreInit(AMDSBCFG* pConfig){
+	BUILDPARAM	*pStaticOptions;
+
+	pConfig->S3Resume = 1;
+
+	pStaticOptions = &pConfig->BuildParameters;
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+
+	commonInitLateBoot(pConfig);
+	sataInitAfterPciEnum(pConfig);
+	azaliaInitAfterPciEnum(pConfig); 			// Detect and configure High Definition Audio
+	hpetInit(pConfig, pStaticOptions);       	// SB Configure HPET base and enable bit
+	sataInitLatePost(pConfig);
+	sbSmmAcpiOn(pConfig);
+}
+
+
+/*++
+
+Routine Description:
+
+  SB config hook during ACPI_ON
+
+Arguments:
+
+  pConfig - SBconfiguration
+
+Returns:
+
+  void
+
+--*/
+
+void	sbSmmAcpiOn(AMDSBCFG* pConfig){
+	UINT32     ddBar5;
+	UINT8      dbPort;
+
+	//RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+	if (getRevisionID() >= SB700_A13)
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);		//Enable Legacy DMA prefetch enhancement
+
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+	RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0);
+	programOhciMmioForEmulation();
+
+	// For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports
+	ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+	if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+	  for (dbPort = 0; dbPort <= 5; dbPort++) {
+	    RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF);
+	  }
+	}
+}
+
+
+UINT32	CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){
+	UINT32 Result=0;
+	TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data));
+	if	(pConfig->StdHeader.pCallBack==NULL)
+		return Result;
+	Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig);
+	TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result));
+	return Result;
+}
+
+#endif
diff --git a/src/vendorcode/amd/cimx/sb700/SBPOR.c b/src/vendorcode/amd/cimx/sb700/SBPOR.c
new file mode 100644
index 0000000..6c5740b
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBPOR.c
@@ -0,0 +1,441 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+REG8MASK sbPorInitPciTable[] = {
+  // SMBUS Device(Bus 0, Dev 20, Func 0)
+  {0x00, SMBUS_BUS_DEV_FUN, 0},
+  {SB_SMBUS_REGD0+2, 0x00, 0x01},
+  {SB_SMBUS_REG40, 0x00, 0x44},
+  {SB_SMBUS_REG40+1, 0xFF, 0xE9},   //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
+  {SB_SMBUS_REG64, 0x00, 0xBF},   //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
+  {SB_SMBUS_REG64+1, 0x00, 0x78},
+  {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
+  {SB_SMBUS_REG64+3, 0x0F, 0x02},
+  {SB_SMBUS_REG68+1, 0x00, 0x90},
+  {SB_SMBUS_REG6C, 0x00, 0x20},
+  {SB_SMBUS_REG78, 0x00, 0xFF},
+  {SB_SMBUS_REG04, 0x00, 0x07},
+  {SB_SMBUS_REG04+1, 0x00, 0x04},
+  {SB_SMBUS_REGE1, 0x00, 0x99},   //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
+  {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
+  {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24},  // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
+                  // can request SMI# to be sent out early before IO completion.
+                  // Some applications may have problems with this feature. The BIOS should set this bit
+                  // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
+  {0xFF, 0xFF, 0xFF},
+
+  // LPC Device(Bus 0, Dev 20, Func 3)
+  {0x00, LPC_BUS_DEV_FUN, 0},
+  {SB_LPC_REG40, 0x00, 0x04},
+  {SB_LPC_REG48, 0x00, 0x07},
+  {SB_LPC_REG4A, 0x00, 0x20},	// Port Enable for IO Port 80h.
+  {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
+  {SB_LPC_REG7C, 0x00, 0x05},
+  {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0},  //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
+  {0xFF, 0xFF, 0xFF},
+
+  // P2P Bridge(Bus 0, Dev 20, Func 4)
+  {0x00, SBP2P_BUS_DEV_FUN, 0},
+  {SB_P2P_REG40, 0x00, 0x26},       // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
+  {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
+  {SB_P2P_REG1C, 0x00, 0x11},
+  {SB_P2P_REG1D, 0x00, 0x11},
+  {SB_P2P_REG04, 0x00, 0x21},
+  {SB_P2P_REG50, 0x02, 0x01},       // PCI Bridge upstream dual address window
+  {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA13PorInitPciTable[] = {
+  // SMBUS Device(Bus 0, Dev 20, Func 0)
+  {0x00, SMBUS_BUS_DEV_FUN, 0},
+  {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00},      //Make some hidden registers of smbus visible.
+  {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
+  {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0},     //Enable SATA test/enhancement mode
+  {SB_SMBUS_REG43, 0xFF, BIT3},     //Make some hidden registers of smbus invisible.
+  {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA14PorInitPciTable[] = {
+  // LPC Device(Bus 0, Dev 20, Func 3)
+  {0x00, LPC_BUS_DEV_FUN, 0},
+  {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
+  {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sbPorPmioInitTbl[] = {
+  // index    andmask ormask
+  {SB_PMIO_REG67, 0xFF, 0x02},
+  {SB_PMIO_REG37, 0xFF, 0x04},    // Configure pciepme as rising edge
+  {SB_PMIO_REG50, 0x00, 0xE0},    // Enable CPU_STP (except S5) & PCI_STP
+  {SB_PMIO_REG60, 0xFF, 0x20},    // Enable Speaker
+  {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
+  {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07},   // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
+  {SB_PMIO_REG66, 0xFF, BIT5},    // Configure keyboard reset to generate pci reset
+  {SB_PMIO_REGB2, 0xFF, BIT7},
+  {SB_PMIO_REG0E, 0xFF, BIT3},    // Enable ACPI IO decoding
+  {SB_PMIO_REGD7, 0xF6, 0x80},
+  {SB_PMIO_REG7C, 0xFF, BIT4},    // enable RTC AltCentury register
+
+  {SB_PMIO_REG75, 0xC0, 0x05},    // PME_TURN_OFF_MSG during ASF shutdown
+  {SB_PMIO_REG52, 0xC0, 0x08},
+
+  {SB_PMIO_REG8B, 0x00, 0x10},
+  {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
+};
+
+REG8MASK sbA13PorPmioInitTbl[]={
+  // index    andmask   ormask
+  {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
+  {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5},  //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
+                                          // Always clear [7] to begin with SP5100 C1e disabled
+
+//  {SB_PMIO_REG65, 0xFF, BIT7},
+//  {SB_PMIO_REG75, 0xC0, 0x01},    // PME_TURN_OFF_MSG during ASF shutdown
+//  {SB_PMIO_REG52, 0xC0, 0x02},
+
+};
+
+
+void  sbPowerOnInit (AMDSBCFG *pConfig){
+  UINT8   dbVar0, dbVar1, dbValue;
+  UINT16    dwTempVar;
+  BUILDPARAM  *pBuildOptPtr;
+
+  TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+  setRevisionID();
+  ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
+  if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
+    RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
+
+  // Set A-Link bridge access address. This address is set at device 14h, function 0,
+  // register 0f0h.   This is an I/O address. The I/O address must be on 16-byte boundry.
+  RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+
+  writeAlink(0x80000004, 0x04);   // RPR 3.3 Enabling upstream DMA Access
+  writeAlink(0x30, 0x10);       //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+  writeAlink(0x34, readAlink(0x34) | BIT9);
+
+  if (!(pConfig->ResetCpuOnSyncFlood)){
+    //Enable reset on sync flood
+    writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
+				(UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
+  }
+
+  pBuildOptPtr = &(pConfig->BuildParameters);
+
+  WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
+
+        dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
+        if( dwTempVar != 0 ){
+            RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
+            // Disable ASF Slave controller on SB700 rev A15.
+            if (getRevisionID() == SB700_A15) {
+                RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
+            }
+        }
+
+  WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
+  RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
+
+  WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
+  WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
+  WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
+  WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
+  WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
+  WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
+  WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
+  RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
+  WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
+
+  //Program power on pci init table
+  programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
+  //Program power on pmio init table
+  programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
+
+        dbValue = 0x00;
+        ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+        dbValue &= 0xF3;
+        WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+
+        dbValue = 0x0A;
+        WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+        ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+        dbValue &= 0xEF;
+        WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+
+  if (getRevisionID() >= SB700_A13){
+    programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
+    programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
+  }
+
+  if ((getRevisionID() >= SB700_A14) )
+    programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
+
+  if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
+    ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
+    if (!(dbVar1 & BIT6)){
+      RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
+      pConfig->RebootRequired=1;
+    }
+  }
+
+  if (getRevisionID() > SB700_A11) {
+    if (pConfig->PciClk5 == 1)
+      RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1);    // Enabled PCICLK5 for A12
+  }
+
+  dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
+  if (dbVar0 > 4) {
+    dbVar0 = 0;
+  }
+  //KZ [061811]-It's used wrong BIOS SIZE for Coreboot.  RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+
+  if (pConfig->Spi33Mhz)
+    //spi reg0c[13:12] to 01h  to run spi 33Mhz in system bios
+    RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
+
+  //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
+  //from the existing value.
+  ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
+  if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
+    pConfig->RebootRequired = 1;
+  if (pConfig->SpreadSpectrum)
+    RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
+  else
+    RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
+
+  if  ( !(pConfig->S3Resume) ){
+    //To detect whether internal clock chip is used, do the following procedure
+    //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
+    //if it is 0, we are using clock chip on board.
+    RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+
+    //Do the following programming only for SB700-A11.
+    //1.  Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
+    //2.  Set PMIO_B2 [7]=0
+    //3.  Write the saved values from step 1, back to B0 and B1.
+    //4.  Set PMIO_B2 [6]=1.
+    ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+    if (getRevisionID() == SB700_A11){
+      RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
+      WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+      RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
+    }
+
+    if  (!(dwTempVar & BIT4)){
+      RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
+
+      //we are in external clock chip on the board
+      if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+        //Configure usb clock to come from internal PLL
+        RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
+        RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4);  //Tell USB PHY to use internal 48Mhz clock from PLL2
+      }
+      else{
+        //Configure usb clock to come from external clock
+        RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0);   //Tell USB PHY to use external 48Mhz clock from PLL2
+        RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00);  //Disable 48Mhz clock from PLL2
+      }
+    }
+    else{
+      //we are using internal clock chip on this board
+      if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+        //Configure usb clock to come from internal PLL
+        RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0);   //Enable 48Mhz clock from PLL2
+        RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4);  //Tell USB PHY to use internal 48Mhz clock from PLL2
+      }
+      else{
+        //Configure usb clock to come from external clock
+        RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0);   //Tell USB PHY to use external 48Mhz clock from PLL2
+        RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3);  //Disable 48Mhz clock from PLL2
+      }
+    }
+
+    ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
+    RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
+    //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
+    if  ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) )  pConfig->RebootRequired = 1;
+  }
+
+  if  (pBuildOptPtr->LegacyFree)        //if LEGACY FREE system
+    RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+  else
+    RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+
+  if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
+    RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
+    RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
+    RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
+  }
+
+  if (getRevisionID() >= SB700_A15) {
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+    //Enable unconditional shutdown fix in A15
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
+  }
+
+  // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
+  if (isEcPresent()) {
+    RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
+  }
+
+  //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+  // to program VID/FID LDTSTP# duration selection register
+  AMDFamily15CpuLdtStopReq();
+
+#ifndef NO_EC_SUPPORT
+  ecPowerOnInit(pBuildOptPtr, pConfig);
+#endif
+}
+
+
+void  setRevisionID(void){
+  UINT8 dbVar0, dbVar1;
+
+  ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+  ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
+  if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
+    RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
+    RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
+    RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
+  }
+  ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+}
+
+
+UINT8 getRevisionID(void){
+  UINT8 dbVar0;
+
+  ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+  return  dbVar0;
+}
+
+
+void AMDFamily15CpuLdtStopReq(void) {
+  CPUID_DATA   CpuId;
+  CPUID_DATA   CpuId_Brand;
+  UINT8   dbVar0, dbVar1, dbVar2;
+
+  //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+  //to program VID/FID LDTSTP# duration selection register
+  //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
+  // 1. Any link in the system operating at a Gen 1 Frequency.
+  // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+
+  CpuidRead (0x01, &CpuId);
+  CpuidRead (0x80000001, &CpuId_Brand);   //BrandID, to read socket type
+  if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
+
+    //Program to Gen 3 default value - 001b
+    RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10);   //set [6:4]=001b
+
+    //Any link in the system operating at a Gen 1 Frequency.
+    //Check Link 0 - Link connected regsister
+    ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
+    dbVar2 = dbVar2 & 0x01;
+
+    if(dbVar2 == 0x01) {
+      //Check Link 0 - Link Frequency Freq[4:0]
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
+      dbVar0 = dbVar0 & 0x0F;       //Freq[3:0]
+      dbVar1 = dbVar1 & 0x01;       //Freq[4]
+      dbVar0 = (dbVar1 << 4) | dbVar0;  //Freq[4:0]
+      //Value 6 or less indicate Gen1
+      if(dbVar0 <= 0x6) {
+        RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40);   //set [6:4]=100b
+      }
+    }
+
+    //Check Link 1 - Link connected regsister
+    ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
+    dbVar2 = dbVar2 & 0x01;
+    if(dbVar2 == 0x01) {
+      //Check Link 1 - Link Frequency Freq[4:0]
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
+      dbVar0 = dbVar0 & 0x0F;       //Freq[3:0]
+      dbVar1 = dbVar1 & 0x01;       //Freq[4]
+      dbVar0 = (dbVar1 << 4) | dbVar0;  //Freq[4:0]
+      //Value 6 or less indicate Gen1
+      if(dbVar0 <= 0x6) {
+        RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40);   //set [6:4]=100b
+      }
+    }
+
+    //Check Link 2 - Link connected regsister
+    ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
+    dbVar2 = dbVar2 & 0x01;
+    if(dbVar2 == 0x01) {
+      //Check Link 2 - Link Frequency Freq[4:0]
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
+      dbVar0 = dbVar0 & 0x0F;       //Freq[3:0]
+      dbVar1 = dbVar1 & 0x01;       //Freq[4]
+      dbVar0 = (dbVar1 << 4) | dbVar0;  //Freq[4:0]
+      //Value 6 or less indicate Gen1
+      if(dbVar0 <= 0x6) {
+        RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40);   //set [6:4]=100b
+      }
+    }
+
+    //Check Link 3 - Link connected regsister
+    ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
+    dbVar2 = dbVar2 & 0x01;
+    if(dbVar2 == 0x01) {
+      //Check Link 3 - Link Frequency Freq[4:0]
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
+      ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
+      dbVar0 = dbVar0 & 0x0F;       //Freq[3:0]
+      dbVar1 = dbVar1 & 0x01;       //Freq[4]
+      dbVar0 = ((dbVar1 << 4) | dbVar0);  //Freq[4:0]
+      //Value 6 or less indicate Gen1
+      if(dbVar0 <= 0x6) {
+        RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40);   //set [6:4]=100b
+      }
+    }
+
+    // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+    if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+      RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40);   //set [6:4]=100b
+    }
+  }
+
+}
+
diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h
new file mode 100644
index 0000000..faeae5d
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h
@@ -0,0 +1,249 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBTYPE_H_
+#define _AMD_SBTYPE_H_
+
+#pragma pack(push,1)
+
+typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig);
+typedef void (*SMM_SERVICE_ROUTINE) (void);
+
+typedef struct _STDCFG{
+        UINT32                  pImageBase;
+        UINT32                  pPcieBase;
+        UINT8                   Func;
+        CIM_HOOK_ENTRY          pCallBack;
+        UINT32                  pB2ImageBase;
+}STDCFG;                        //Size of stdcfg is 17 bytes
+
+typedef struct _BUILDPARAM
+{
+        UINT16  BiosSize:3;             //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved
+        UINT16  LegacyFree:1;
+        UINT16  Dummy0:12;
+
+        UINT16  EcKbd:1;
+        UINT16  EcChannel0:1;
+        UINT16  Dummy1:14;
+
+        UINT32  Smbus0BaseAddress;
+        UINT16  Smbus1BaseAddress;
+        UINT32  SioPmeBaseAddress;
+        UINT32  WatchDogTimerBase;
+        UINT32  SpiRomBaseAddress;
+
+        UINT16  AcpiPm1EvtBlkAddr;
+        UINT16  AcpiPm1CntBlkAddr;
+        UINT16  AcpiPmTmrBlkAddr;
+        UINT16  CpuControlBlkAddr;
+        UINT16  AcpiGpe0BlkAddr;
+        UINT16  SmiCmdPortAddr;
+        UINT16  AcpiPmaCntBlkAddr;
+
+        UINT16  EcLdn5MailBoxAddr;
+        UINT8   EcLdn5Irq;
+        UINT16  EcLdn9MailBoxAddr;
+        UINT32  ReservedDword0;
+        UINT32  ReservedDword1;
+        UINT32  ReservedDword2;
+        UINT32  ReservedDword3;
+
+        UINT32  HpetBase;                       //HPET Base address
+
+        UINT32  SataIDESsid;
+        UINT32  SataRAIDSsid;
+        UINT32  SataRAID5Ssid;
+        UINT32  SataAHCISsid;
+
+        UINT32  Ohci0Ssid;
+        UINT32  Ohci1Ssid;
+        UINT32  Ehci0Ssid;
+        UINT32  Ohci2Ssid;
+        UINT32  Ohci3Ssid;
+        UINT32  Ehci1Ssid;
+        UINT32  Ohci4Ssid;
+        UINT32  SmbusSsid;
+        UINT32  IdeSsid;
+        UINT32  AzaliaSsid;
+        UINT32  LpcSsid;
+        UINT32  P2PSsid;
+}BUILDPARAM;
+
+typedef struct _CODECENTRY{
+        UINT8 Nid;
+        UINT32 Byte40;
+}CODECENTRY;
+
+typedef struct _CODECTBLLIST{
+        UINT32  CodecID;
+        CODECENTRY* CodecTablePtr;
+}CODECTBLLIST;
+
+typedef struct _AMDSBCFG
+{
+        STDCFG  StdHeader;                              //offset 0:16 - 17 bytes
+        //UINT32        MsgXchgBiosCimx;                //offset 17:20 - 4 bytes
+        UINT32  S3Resume:1;
+        UINT32  RebootRequired:1;
+        UINT32  Spi33Mhz:1;
+        UINT32  SpreadSpectrum:1;
+        UINT32  UsbIntClock:1;                          //0:Use external clock, 1:Use internal clock
+        UINT32  PciClk5:1;                              //0:disable, 1:enable
+        UINT32  TimerClockSource:2;                     //0:100Mhz PCIE Reference clock (same as SB700-A12,
+                                                        //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz
+                                                        //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100
+        UINT32  ResetCpuOnSyncFlood:1;                  //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood
+        UINT32  MsgXchgBiosCimxDummyBB:23;
+
+        /** BuildParameters - The STATIC platform information for CIMx Module. */
+        BUILDPARAM BuildParameters;
+
+        //SATA Configuration
+        UINT32  SataController  :1;                     //0, 0:disable  1:enable*       //offset 25:28 - 4 bytes
+        UINT32  SataClass       :3;                     //1, 0:IDE* 1:RAID      2:AHCI  3:Legacy IDE    4:IDE->AHCI     5:AMD_AHCI, 6:IDE->AMD_AHCI
+        UINT32  SataSmbus       :1;                     //4, 0:disable  1:enable*
+        UINT32  SataAggrLinkPmCap:1;                    //5, 0:OFF   1:ON
+        UINT32  SataPortMultCap :1;                     //6, 0:OFF   1:ON
+        UINT32  SataReserved    :2;                     //8:7, Reserved
+        UINT32  SataClkAutoOff  :1;                     //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled
+        UINT32  SataIdeCombinedMode     :1;             //10, SataIDECombinedMode 0:Disabled, 1:Enabled
+        UINT32  SataIdeCombMdPriSecOpt:1;               //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary
+        UINT32  SataReserved1   :6;                     //17:12, Not used currently
+        UINT32  SataEspPort     :6;                     //23:18 SATA port is external accessiable on a signal only connector (eSATA:)
+        UINT32  SataClkAutoOffAhciMode:1;               //24: Sata Auto clock off for AHCI mode
+        UINT32  SataHpcpButNonESP:6;                    //25:30 Hotplug capable but not e-sata port
+        UINT32  SataHideUnusedPort:1;                   //31, 0:Disabled   1:Enabled
+
+        //Flash Configuration                           //offset 29:30 - 2 bytes
+        UINT16  FlashController :1;                     //0, 0:disable FC & enable IDE  1:enable FC & disable IDE
+        UINT16  FlashControllerMode:1;                  //1, 0:Flash behind SATA        1:Flash as standalone
+        UINT16  FlashHcCrc:1;                           //2,
+        UINT16  FlashErrorMode:1;                       //3
+        UINT16  FlashNumOfBankMode:1;                   //4
+        UINT16  FlashDummy:11;                          //5:15
+
+        //USB Configuration                             //offset 31:32 - 2 bytes
+        UINT16  Usb1Ohci0       :1;                     //0, 0:disable  1:enable*       Bus 0 Dev 18 Func0
+        UINT16  Usb1Ohci1       :1;                     //1, 0:disable  1:enable*       Bus 0 Dev 18 Func1
+        UINT16  Usb1Ehci        :1;                     //2, 0:disable  1:enable*       Bus 0 Dev 18 Func2
+        UINT16  Usb2Ohci0       :1;                     //3, 0:disable  1:enable*       Bus 0 Dev 19 Func0
+        UINT16  Usb2Ohci1       :1;                     //4, 0:disable  1:enable*       Bus 0 Dev 19 Func1
+        UINT16  Usb2Ehci        :1;                     //5, 0:disable  1:enable*       Bus 0 Dev 19 Func2
+        UINT16  Usb3Ohci        :1;                     //6, 0:disable  1:enable*       Bus 0 Dev 20 Func5
+        UINT16  UsbOhciLegacyEmulation:1;               //7, 0:Enabled, 1:Disabled
+        UINT16  UsbDummy        :8;                     //8:15
+
+        //Azalia Configuration                          //offset 33:36 - 4 bytes
+        UINT32  AzaliaController:2;                     //0, 0:AUTO, 1:disable, 2:enable
+        UINT32  AzaliaPinCfg    :1;                     //2, 0:disable, 1:enable
+        UINT32  AzaliaFrontPanel:2;                     //3, 0:AUTO, 1:disable, 2:enable
+        UINT32  FrontPanelDetected:1;                   //5, 0:Not detected, 1:detected
+        UINT32  AzaliaSdin0     :2;                     //6
+        UINT32  AzaliaSdin1     :2;                     //8
+        UINT32  AzaliaSdin2     :2;                     //10
+        UINT32  AzaliaSdin3     :2;                     //12
+        UINT32  AzaliaDummy     :18;                    //14:31
+
+        CODECTBLLIST*   pAzaliaOemCodecTablePtr;        //offset 37:40 - 4 bytes
+        UINT32  pAzaliaOemFpCodecTableptr;              //offset 41:44 - 4 bytes
+
+        //Miscellaneous Configuration                   //offset 45:48 - 4 bytes
+        UINT32  MiscReserved0:1;                        //0
+        UINT32  HpetTimer:1;                            //1, 0:disable  1:enable
+        UINT32  PciClks:5;                              //2:6, 0:disable, 1:enable
+        UINT32  MiscReserved1:3;                        //9:7, Reserved
+        UINT32  IdeController:1;                        //10, 0:Enable, 1:Disabled
+        UINT32  MobilePowerSavings:1;                   //11, 0:Disable, 1:Enable       Power saving features especially for Mobile platform
+        UINT32  ExternalRTCClock:1;                     //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
+        UINT32  AcpiS1Supported:1;                      //13, 0:S1 not supported, 1:S1 supported
+        UINT32  AnyHT200MhzLink:1;                      //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform
+        UINT32  WatchDogTimerEnable:1;                  //15, [0]: WDT disabled; 1: WDT enabled
+        UINT32  MTC1e:1;                                //16, Message Triggered C1e - 0:Disabled*, 1:Enabled
+        UINT32  HpetMsiDis:1;                           //17, HPET MSI - 0:Enable HPET MSI, 1:Disable
+                UINT32  EhciDataCacheDis:1;                     //18, 0:Date Cache Enabled, 1:Date Cache Disabled    /** EHCI Async Data Cache Disable */
+        UINT32  MiscDummy:13;
+
+        UINT32  AsmAslInfoExchange0;                    //offset 49:52 - 4 bytes
+        UINT32  AsmAslInfoExchange1;                    //offset 53:56
+
+        //DebugOptions_1                                //offset 57:60
+        UINT32  FlashPinConfig  :1;                     //0, 0:desktop mode     1:mobile mode
+        UINT32  UsbPhyPowerDown :1;                     //1
+        UINT32  PcibClkStopOverride     :10;            //11:2
+        UINT32  Debug1Reserved0:4;                      //15:11
+        UINT32  AzaliaSnoop:1;                          //16 0:Disable, 1:Enable
+        UINT32  SataSscPscCap:1;                        //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability
+        UINT32  SataPortMode:6;                         //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1
+        UINT32  SataPhyWorkaround:2;                    //25:24, 0:AUTO, 1:Enable, 2:Disable
+        UINT32  Gen1DeviceShutdownDuringPhyWrknd:2;     //27:26, 0:AUTO, 1:YES, 2:NO
+        UINT32  OhciIsoOutPrefetchDis:1;                //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable
+        UINT32  Debug1Dummy:3;                          //
+
+        //DebugOptions_2
+        UINT32  PcibAutoClkCtrlLow:16;
+        UINT32  PcibAutoClkCtrlHigh:16;
+
+        //TempMMIO
+        UINT32  TempMMIO:32;
+
+}AMDSBCFG;
+
+typedef struct  _SMMSERVICESTRUC
+{
+        UINT8   enableRegNum;
+        UINT8   enableBit;
+        UINT8   statusRegNum;
+        UINT8   statusBit;
+        CHAR8   *debugMessage;
+        SMM_SERVICE_ROUTINE     serviceRoutine;
+}SMMSERVICESTRUC;
+
+typedef struct _ABTblEntry
+{
+        UINT8   regType;
+        UINT32  regIndex;
+        UINT32  regMask;
+        UINT32  regData;
+}ABTBLENTRY;
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+typedef UINT32  CIM_STATUS;
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR       0x80000000
+#define CIM_UNSUPPORTED 0x80000001
+
+#pragma pack(pop)
+
+#define CIMX_OPTION_DISABLED	0
+#define CIMX_OPTION_ENABLED	1
+
+#endif // _AMD_SBTYPE_H_
diff --git a/src/vendorcode/amd/cimx/sb700/SMM.c b/src/vendorcode/amd/cimx/sb700/SMM.c
new file mode 100644
index 0000000..0d752fb
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/SMM.c
@@ -0,0 +1,91 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+SMMSERVICESTRUC	smmItemsTable[]={
+	{SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice},
+	{SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL},
+	{SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL},
+	{SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL},
+	{SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL},
+	{SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL},
+	{SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL},
+};
+
+
+/*++
+
+Routine Description:
+
+  SB SMI service
+
+Arguments:
+
+  pConfig - SBconfiguration
+
+Returns:
+
+  void
+
+--*/
+
+void sbSmmService(AMDSBCFG* pConfig){
+	UINT8	i, dbEnableValue, dbStatusValue;
+	SMMSERVICESTRUC	*pSmmItems;
+	SMM_SERVICE_ROUTINE	serviceRoutine;
+
+	pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]);
+	TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
+	for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){
+		dbEnableValue = pSmmItems->enableRegNum;
+		ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue);
+		ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue);
+		if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){
+			TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage));
+			TRACE((DMSG_SB_TRACE, "Enable Reg:%d   Value:%d\n", pSmmItems->enableRegNum, dbEnableValue));
+			TRACE((DMSG_SB_TRACE, "Status Reg:%d   Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue));
+			if ( (pSmmItems->serviceRoutine)!= NULL){
+				serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine);
+				serviceRoutine();
+			}
+		}
+	}
+	TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
+}
+
+
+void softwareSMIservice(void){
+		UINT16	dwSmiCmdPort, dwVar;
+		ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort);
+		ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar);
+		TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
+}
diff --git a/src/vendorcode/amd/cimx/sb700/USB.c b/src/vendorcode/amd/cimx/sb700/USB.c
new file mode 100644
index 0000000..9c5e7b3
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/USB.c
@@ -0,0 +1,187 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include	"Platform.h"
+
+
+void usbInitBeforePciEnum(AMDSBCFG* pConfig){
+	UINT8	dbVar=0;
+
+	TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
+	if (pConfig->Usb1Ohci0){
+		dbVar = (pConfig->Usb1Ehci << 2);
+		dbVar |= ((pConfig->Usb1Ohci0) << 0);
+		dbVar |= ((pConfig->Usb1Ohci1) << 1);
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar );
+	}
+	if (pConfig->Usb2Ohci0){
+		dbVar = (pConfig->Usb2Ehci << 6) ;
+		dbVar |= ((pConfig->Usb2Ohci0) << 4);
+		dbVar |= ((pConfig->Usb2Ohci1) << 5);
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar );
+	}
+	if (pConfig->Usb3Ohci)
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) );
+
+	RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4);
+}
+
+
+void usbInitAfterPciInit(AMDSBCFG* pConfig){
+	UINT32	ddBarAddress, ddVar;
+
+	ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+	if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+		//Enable Memory access
+		RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+		//USB Common PHY CAL & Control Register setting
+		ddVar = 0x00020F00;
+		WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+		//RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+		//EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40	//OUT threshold bits[23:16]=0x40
+		RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+		//RPR - EHCI dynamic clock gating feature
+		//EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+		// Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+		RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+	}
+
+	ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+	if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+		//Enable Memory access
+		RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+		//USB Common PHY CAL & Control Register setting
+		ddVar = 0x00020F00;
+		WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+		//RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+		//EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40	//OUT threshold bits[23:16]=0x40
+		RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+		//RPR - EHCI dynamic clock gating feature
+		//EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+		// Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+		RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+	}
+
+	if (pConfig->UsbPhyPowerDown)
+		RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0);
+	else
+		RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+	// Disable the MSI capability of USB host controllers
+	RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+	RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+	RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+	//RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE"
+	//Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux.
+	//Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
+	//RPR recommended setting "EHCI Async Park Mode"
+	//Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support"
+	// RPR recommended setting "EHCI Advance PHY Power Savings"
+	// Set EHCI_pci_configx50[31]='1' if SB700 A12 & above
+	// Fix for EHCI controller driver  yellow sign issue under device manager
+	// when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
+	RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+	RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+
+	//RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
+	//OHCI 0_PCI_Config 0x50[16] = 1
+	RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+	RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+	RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+	if (getRevisionID() >= SB700_A14){
+		RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+		RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+
+		RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+		RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+		RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25);
+	}
+
+	if (getRevisionID() >= SB700_A15) {
+		//USB PID Error checking
+		RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+		RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+	}
+
+	// RPR 6.25 - Optionally disable OHCI isochronous out prefetch
+	if (pConfig->OhciIsoOutPrefetchDis) {
+	  RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+	  RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+	  RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+	}
+
+	if ( pConfig->EhciDataCacheDis ) {
+      // Disable Async Data Cache, EHCI_pci_configx50[26]='1'
+      RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+	  RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+    }
+}
+
+
+void	usbInitMidPost(AMDSBCFG* pConfig){
+	if (pConfig->UsbOhciLegacyEmulation == 0){
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+		RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+	}
+	else{
+		programOhciMmioForEmulation();
+	}
+}
+
+
+void programOhciMmioForEmulation(void){
+	UINT32	ddBarAddress;
+
+	ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+	ddBarAddress &= 0xFFFFF000;
+	if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+		//Enable Memory access
+		RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+		RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+	}
+
+	ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+	ddBarAddress &= 0xFFFFF000;
+	if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+		//Enable Memory access
+		RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+		RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+	}
+
+	ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+	if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+		//Enable Memory access
+		RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+		RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+	}
+}
diff --git a/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h
new file mode 100644
index 0000000..e8f6b38
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb700/sbAMDLIB.h
@@ -0,0 +1,196 @@
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_AMDLIB_H_
+#define _AMD_AMDLIB_H_
+
+typedef CHAR8   *va_list;
+#ifndef _INTSIZEOF
+	#define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+#define va_start(ap,v)  ( ap = (va_list)&(v) + _INTSIZEOF(v) )
+#endif
+#define va_arg(ap,t)    ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#define va_end(ap)      ( ap = (va_list)0 )
+
+#ifndef	CIMx_DEBUG
+	#define	CIMx_DEBUG	0
+#endif
+
+
+#pragma pack(push,1)
+
+#define	IMAGE_ALIGN		32*1024
+#define	NUM_IMAGE_LOCATION	32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY)(void* pConfig);
+
+//Hook Call
+
+typedef struct _Reg8Mask
+{
+	UINT8	bRegIndex;
+	UINT8	bANDMask;
+	UINT8	bORMask;
+}REG8MASK;
+
+
+typedef struct _CIMFILEHEADER{
+	UINT32	AtiLogo;
+	UINT32	EntryPoint;
+	UINT32	ModuleLogo;
+	UINT32	ImageSize;
+	UINT16	Version;
+	UINT8	CheckSum;
+	UINT8	Reserved1;
+	UINT32  Reserved2;
+}CIMFILEHEADER;
+
+typedef struct _CPUID_DATA{
+	UINT32	REG_EAX;
+	UINT32	REG_EBX;
+	UINT32	REG_ECX;
+	UINT32	REG_EDX;
+}CPUID_DATA;
+
+#ifndef BIT0
+	#define	BIT0					(1 << 0)
+#endif
+#ifndef BIT1
+	#define	BIT1					(1 << 1)
+#endif
+#ifndef BIT2
+	#define	BIT2					(1 << 2)
+#endif
+#ifndef BIT3
+	#define	BIT3					(1 << 3)
+#endif
+#ifndef BIT4
+	#define	BIT4					(1 << 4)
+#endif
+#ifndef BIT5
+	#define	BIT5					(1 << 5)
+#endif
+#ifndef BIT6
+	#define	BIT6					(1 << 6)
+#endif
+#ifndef BIT7
+	#define	BIT7					(1 << 7)
+#endif
+#ifndef BIT8
+	#define	BIT8					(1 << 8)
+#endif
+#ifndef BIT9
+	#define	BIT9					(1 << 9)
+#endif
+#ifndef BIT10
+	#define	BIT10					(1 << 10)
+#endif
+#ifndef BIT11
+	#define	BIT11					(1 << 11)
+#endif
+#ifndef BIT12
+	#define	BIT12					(1 << 12)
+#endif
+#ifndef BIT13
+	#define	BIT13					(1 << 13)
+#endif
+#ifndef BIT14
+	#define	BIT14					(1 << 14)
+#endif
+#ifndef BIT15
+	#define	BIT15					(1 << 15)
+#endif
+#ifndef BIT16
+	#define	BIT16					(1 << 16)
+#endif
+#ifndef BIT17
+	#define	BIT17					(1 << 17)
+#endif
+#ifndef BIT18
+	#define	BIT18					(1 << 18)
+#endif
+#ifndef BIT19
+	#define	BIT19					(1 << 19)
+#endif
+#ifndef BIT20
+	#define	BIT20					(1 << 20)
+#endif
+#ifndef BIT21
+	#define	BIT21					(1 << 21)
+#endif
+#ifndef BIT22
+	#define	BIT22					(1 << 22)
+#endif
+#ifndef BIT23
+	#define	BIT23					(1 << 23)
+#endif
+#ifndef BIT24
+	#define	BIT24					(1 << 24)
+#endif
+#ifndef BIT25
+	#define	BIT25					(1 << 25)
+#endif
+#ifndef BIT26
+	#define	BIT26					(1 << 26)
+#endif
+#ifndef BIT27
+	#define	BIT27					(1 << 27)
+#endif
+#ifndef BIT28
+	#define	BIT28					(1 << 28)
+#endif
+#ifndef BIT29
+	#define	BIT29					(1 << 29)
+#endif
+#ifndef BIT30
+	#define	BIT30					(1 << 30)
+#endif
+#ifndef BIT31
+	#define	BIT31					(1 << 31)
+#endif
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#pragma pack(pop)
+
+typedef enum {
+  AccWidthUint8 = 0,
+  AccWidthUint16,
+  AccWidthUint32,
+} ACC_WIDTH;
+
+#define	S3_SAVE 					0x80
+
+#endif	//#ifndef _AMD_AMDLIB_H_


From gerrit at coreboot.org  Fri Jan 20 06:44:47 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:47 +0100
Subject: [coreboot] New patch to review for coreboot: c19f20d SB700
	southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
References: <If924b7eb176e7d3d82fa394929b653b1ced3a743+0@gerrit.coreboot.org>
Message-ID: <If924b7eb176e7d3d82fa394929b653b1ced3a743+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561

-gerrit

commit c19f20dbd77e1c99ead37b41fc70239d97c26631
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:18 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
    
    Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/southbridge/amd/Makefile.inc            |    1 +
 src/southbridge/amd/cimx/Kconfig            |    3 +-
 src/southbridge/amd/cimx/Makefile.inc       |    3 +-
 src/southbridge/amd/cimx/sb700/Amd.h        |  363 +++++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb700/AmdSbLib.h   |  181 +++++++++++++
 src/southbridge/amd/cimx/sb700/Kconfig      |   63 +++++
 src/southbridge/amd/cimx/sb700/Makefile.inc |   32 +++
 src/southbridge/amd/cimx/sb700/Platform.h   |   87 +++++++
 src/southbridge/amd/cimx/sb700/bootblock.c  |   97 +++++++
 src/southbridge/amd/cimx/sb700/cbtypes.h    |   53 ++++
 src/southbridge/amd/cimx/sb700/chip.h       |   42 +++
 src/southbridge/amd/cimx/sb700/chip_name.c  |   25 ++
 src/southbridge/amd/cimx/sb700/early.c      |   75 ++++++
 src/southbridge/amd/cimx/sb700/late.c       |  329 ++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb700/lpc.c        |  195 ++++++++++++++
 src/southbridge/amd/cimx/sb700/lpc.h        |   30 +++
 src/southbridge/amd/cimx/sb700/sb_cimx.h    |   49 ++++
 src/southbridge/amd/cimx/sb700/smbus.c      |  270 ++++++++++++++++++++
 src/southbridge/amd/cimx/sb700/smbus.h      |   82 ++++++
 19 files changed, 1978 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 406a0b3..54245f2 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
@@ -12,6 +12,7 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx
 
diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
index 8f12b90..f61b75a 100644
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -21,5 +21,6 @@ config AMD_SB_CIMX
 	bool
 	default n
 
+source src/southbridge/amd/cimx/sb700/Kconfig
 source src/southbridge/amd/cimx/sb800/Kconfig
 source src/southbridge/amd/cimx/sb900/Kconfig
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index 421a11c..80c6378 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,5 +16,6 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h
new file mode 100644
index 0000000..fbd5531
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Amd.h
@@ -0,0 +1,363 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+// AGESA Types and Definitions
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define LAST_ENTRY 0xFFFFFFFF
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+#define IN
+#define OUT
+
+#ifndef Int16FromChar
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#endif
+#ifndef Int32FromChar
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#endif
+
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+
+typedef unsigned int AGESA_STATUS;
+
+#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
+#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
+#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
+#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
+#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
+#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
+#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
+
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+	PreMemHeap = 0,                                           ///< Create heap in cache.
+	PostMemDram,                                              ///< Create heap in memory.
+	ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+	AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+	AccessWidth16,                                            ///< Access width is 16 bits.
+	AccessWidth32,                                            ///< Access width is 32 bits.
+	AccessWidth64,                                            ///< Access width is 64 bits.
+
+	AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+	AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+	AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+	AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+typedef struct _AMD_CONFIG_PARAMS {
+	IN       unsigned int          ImageBasePtr;     ///< The AGESA Image base address.
+	IN       unsigned int          Func;             ///< The service desired, @sa dispatch.h.
+	IN       unsigned int          AltImageBasePtr;  ///< Alternate Image location
+	IN       unsigned int          PcieBasePtr;      ///< PCIe MMIO Base address, if configured.
+	union {                                    ///< Callback pointer
+		IN       unsigned long long          PlaceHolder;    ///< Place holder
+		IN       CALLOUT_ENTRY   CalloutPtr;     ///< For Callout from AGESA
+	} CALLBACK;
+	IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// AGESA Binary module header structure
+typedef struct _AMD_IMAGE_HEADER {
+	IN       unsigned int  Signature;                          ///< Binary Signature
+	IN       signed char   CreatorID[8];                       ///< 8 characters ID
+	IN       signed char   Version[12];                        ///< 12 characters version
+	IN       unsigned int  ModuleInfoOffset;                   ///< Offset of module
+	IN       unsigned int  EntryPointAddress;                  ///< Entry address
+	IN       unsigned int  ImageBase;                          ///< Image base
+	IN       unsigned int  RelocTableOffset;                   ///< Relocate Table offset
+	IN       unsigned int  ImageSize;                          ///< Size
+	IN       unsigned short  Checksum;                           ///< Checksum
+	IN       unsigned char   ImageType;                          ///< Type
+	IN       unsigned char   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+	IN       unsigned int          ModuleHeaderSignature;      ///< Module signature
+	IN       signed char           ModuleIdentifier[8];        ///< 8 characters ID
+	IN       signed char           ModuleVersion[12];          ///< 12 characters version
+	IN       MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
+	IN       struct _AMD_MODULE_HEADER  *NextBlockPtr;    ///< Next module header link
+} AMD_MODULE_HEADER;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function (3-bits)
+//   11:00   Offset  (12-bits)
+
+#if 0
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
+		(((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+#endif
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct _SB_CPUID_DATA {
+	IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
+	IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
+	IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
+	IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
+} SB_CPUID_DATA;
+
+#define WARM_RESET 1
+#define COLD_RESET 2      // Cold reset
+#define RESET_CPU  4      // Triggers a CPU reset
+
+/// HT frequency for external callbacks
+typedef enum {
+	HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+	HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+	HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+	HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+	HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+	HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+	HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+	HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+	HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+	HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+	HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+	HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+	HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+	HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+	HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+	HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
+} HT_FREQUENCIES;
+
+#ifndef BIT0
+#define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+#define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+#define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+#define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+#define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+#define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+#define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+#define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+#define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+#define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+#define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+#define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+#define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+#define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+#define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+#define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+#define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+#define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+#define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+#define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+#define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+#define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+#define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+#define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+#define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+#define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+#define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+#define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+#define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+#define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+#define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+#define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+#define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+#define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+#define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+#define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+#define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+#define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+#define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+#define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+#define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+#define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+#define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+#define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+#define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+#define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+#define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+#define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+#define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+#define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+#define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+#define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+#define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+#define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+#define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+#define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+#define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+#define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+#define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+#define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+#define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+#define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+#define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+#define BIT63       0x8000000000000000ull
+#endif
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h
new file mode 100644
index 0000000..2812605
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/AmdSbLib.h
@@ -0,0 +1,181 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_SB_LIB_H_
+#define _AMD_SB_LIB_H_
+
+typedef signed char  *va_list;
+#ifndef _INTSIZEOF
+  #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+  #define va_start(ap, v)  ( ap = (va_list)&(v) + _INTSIZEOF (v) )
+#endif
+#define va_arg(ap, t)    ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
+#define va_end(ap)      ( ap = (va_list)0 )
+
+
+#pragma pack (push, 1)
+
+#define IMAGE_ALIGN          32*1024
+#define NUM_IMAGE_LOCATION   32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
+
+//Hook Call
+
+typedef struct _CIMFILEHEADER
+{
+	unsigned int  AMDLogo;
+	unsigned long long  CreatorID;
+	unsigned int  Version1;
+	unsigned int  Version2;
+	unsigned int  Version3;
+	unsigned int  ModuleInfoOffset;
+	unsigned int  EntryPoint;
+	unsigned int  ImageBase;
+	unsigned int  RelocTableOffset;
+	unsigned int  ImageSize;
+	unsigned short  CheckSum;
+	unsigned char ImageType;
+	unsigned char Reserved2;
+} CIMFILEHEADER;
+
+#ifndef BIT0
+  #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+  #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+  #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+  #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+  #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+  #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+  #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+  #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+  #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+  #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+  #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+  #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+  #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+  #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+  #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+  #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+  #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+  #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+  #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+  #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+  #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+  #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+  #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+  #define BIT23 (1 << 23)
+#endif
+#ifndef  BIT24
+  #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+  #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+  #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+  #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+  #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+  #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+  #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+  #define BIT31 (1 << 31)
+#endif
+
+#pragma pack (pop)
+
+typedef enum
+{
+	AccWidthUint8 = 0,
+	AccWidthUint16,
+	AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE  0x80
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS  AmdSbDispatcher (IN void *pConfig);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
new file mode 100644
index 0000000..27338fc
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Kconfig
@@ -0,0 +1,63 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_CIMX_SB700
+	bool
+	select IOAPIC
+	select AMD_SB_CIMX
+
+if SOUTHBRIDGE_AMD_CIMX_SB700
+config SATA_CONTROLLER_MODE
+	hex
+	default 0x0
+	help
+		0x0 = Native IDE mode.
+		0x1 = RAID mode.
+		0x2 = AHCI mode.
+		0x3 = Legacy IDE mode.
+		0x4 = IDE->AHCI mode.
+		0x5 = AHCI mode as 7804 ID (AMD driver).
+		0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
+
+config PCIB_ENABLE
+	bool
+	default n
+	help
+		n = Disable PCI Bridge Device 14 Function 4.
+		y = Enable PCI Bridge Device 14 Function 4.
+
+config ACPI_SCI_IRQ
+	hex
+	default 0x9
+	help
+		Set SCI IRQ to 9.
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/amd/cimx/sb700/bootblock.c"
+
+config REDIRECT_SBCIMX_TRACE_TO_SERIAL
+	bool "Redirect AMD Southbridge CIMX Trace to serial console"
+	default n
+	help
+	  This Option allows you to redirect the AMD Southbridge CIMX Trace
+	  debug information to the serial console.
+
+	  Warning: Only enable this option when debuging or tracing AMD CIMX code.
+endif #SOUTHBRIDGE_AMD_CIMX_SB700
+
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
new file mode 100644
index 0000000..3bb8397
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Makefile.inc
@@ -0,0 +1,32 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += ../../../../../src/vendorcode/amd/cimx/sb700
+
+# SB700 Platform Files
+
+romstage-y += early.c
+romstage-y += smbus.c
+
+ramstage-y += late.c
+
+driver-y   += smbus.c
+driver-y   += lpc.c
+
+
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
new file mode 100644
index 0000000..15e5b07
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_SB_CIMx_PLATFORM_H_
+#define _AMD_SB_CIMx_PLATFORM_H_
+
+#pragma pack(push,1)
+
+#include "cbtypes.h"
+#include <console/console.h>
+#include <console/loglevel.h>
+#ifdef NULL
+#undef NULL
+#endif
+#define NULL            0
+
+typedef struct _EXT_PCI_ADDR{
+	UINT32                  Reg :16;
+	UINT32                  Func:3;
+	UINT32                  Dev :5;
+	UINT32                  Bus :8;
+}EXT_PCI_ADDR;
+
+
+typedef union _PCI_ADDR{
+	UINT32                  ADDR;
+	EXT_PCI_ADDR            Addr;
+}PCI_ADDR;
+
+
+#ifdef CIM_DEBUG
+
+#if   CIM_DEBUG & 2
+void    TraceDebug( UINT32 Level, CHAR8 *Format, ...);
+#define TRACE(Arguments) TraceDebug Arguments
+#else
+#define TRACE(Arguments)
+#endif
+
+#if   CIM_DEBUG & 1
+void    TraceCode ( UINT32 Level, UINT32 Code);
+#define TRACECODE(Arguments) TraceCode Arguments
+#else
+#define TRACECODE(Arguments)
+#endif
+#else
+	#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
+		#define TRACE(Arguments) printk Arguments
+	#else
+		#define TRACE(Arguments) do {} while(0)
+	#endif
+	#define TRACECODE(Arguments)
+#endif
+
+#define FIXUP_PTR(ptr)  ptr
+
+#pragma pack(pop)
+
+#include "OEM.h"
+#include "Amd.h"
+#include "ACPILIB.h"
+#include "SBTYPE.h"
+#include "sbAMDLIB.h"
+#include "SBCMNLIB.h"
+#include "SB700.h"
+#include "SBDEF.h"
+
+#define DMSG_SB_TRACE   0x02
+
+#endif  //#ifndef _AMD_SB_CIMx_PLATFORM_H_
+
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
new file mode 100644
index 0000000..401c039
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -0,0 +1,97 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+
+#if CONFIG_CONSOLE_POST == 1
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+#define CONFIG_TTYS0_DIV	(115200/CONFIG_TTYS0_BAUD)
+#endif // CONFIG_TTYS0_DIV
+
+#define UART_LCS	CONFIG_TTYS0_LCS
+
+#endif // CONFIG_CONSOLE_POST == 1
+
+
+static void sb700_enable_rom(void)
+{
+	u32 word;
+	u32 dword;
+	device_t dev;
+
+	dev = PCI_DEV(0, 0x14, 0x03);
+	/* SB700 LPC Bridge 0:20:3:44h.
+	 * BIT6: Port Enable for serial port 0x3f8-0x3ff
+	 * BIT29: Port Enable for KBC port 0x60 and 0x64
+	 * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+	 */
+	dword = pci_io_read_config32(dev, 0x44);
+	//dword |= (1<<6) | (1<<29) | (1<<30) ;
+	/*Turn on all of LPC IO Port decode enable */
+	dword = 0xffffffff;
+	pci_io_write_config32(dev, 0x44, dword);
+
+	/* SB700 LPC Bridge 0:20:3:48h.
+	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
+	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
+	 * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+	 * BIT6: Port Enable for RTC IO 0x70-0x73
+	 * BIT21: Port Enable for Port 0x80
+	 */
+	dword = pci_io_read_config32(dev, 0x48);
+	dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+	pci_io_write_config32(dev, 0x48, dword);
+
+	/* Enable 4MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+	/* Set the 4MB enable bits */
+	word = pci_io_read_config16(dev, 0x6c);
+	word = 0xFFC0;
+	pci_io_write_config16(dev, 0x6c, word);
+}
+
+static void bootblock_southbridge_init(void)
+{
+	/* Setup the rom access for 2M */
+	sb700_enable_rom();
+}
diff --git a/src/southbridge/amd/cimx/sb700/cbtypes.h b/src/southbridge/amd/cimx/sb700/cbtypes.h
new file mode 100644
index 0000000..d37e1e3
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/cbtypes.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+
+#ifndef TRUE
+#define TRUE  1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+typedef unsigned char BOOLEAN;
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h
new file mode 100644
index 0000000..ef294f4
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/chip.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _CIMX_SB700_CHIP_H_
+#define _CIMX_SB700_CHIP_H_
+
+extern struct chip_operations southbridge_amd_cimx_sb700_ops;
+
+/*
+ * configuration set in mainboard/devicetree.cb
+ *  boot_switch_sata_ide:
+ *   0 -set SATA as primary, PATA(IDE) as secondary.
+ *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
+ *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
+ *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
+ *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
+ *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+struct southbridge_amd_cimx_sb700_config
+{
+	u32 boot_switch_sata_ide : 1;
+	u8  gpp_configuration;
+};
+
+#endif /* _CIMX_SB700_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx/sb700/chip_name.c b/src/southbridge/amd/cimx/sb700/chip_name.c
new file mode 100644
index 0000000..13d2276
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/chip_name.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations southbridge_amd_cimx_sb700_ops = {
+	CHIP_NAME("AMD South Bridge  SB700")
+};
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
new file mode 100644
index 0000000..bc3d944
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+//#include <config.h>
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>            /* inl, outl */
+#include <arch/romcc_io.h>      /* device_t */
+#include "Platform.h"
+#include "sb_cimx.h"
+#include "sb700_cfg.h"                /*sb700_cimx_config*/
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "smbus.h"
+
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
+ * @brief Get SouthBridge device number
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus)
+{
+	device_t dev;
+
+	printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - Start.\n");
+	//dev = PCI_DEV(bus, 0x14, 0);
+	dev = pci_locate_device_on_bus(
+			PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM),
+			bus);
+
+	printk(BIOS_DEBUG, "SB700 - Early.c - get_sbdn - End.\n");
+	return (dev >> 15) & 0x1f;
+}
+#endif
+
+/**
+ * @brief Enable A-Link Express Configuration DMA Access.
+ */
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ *        wrapper of sbPowerOnInit entry point.
+ */
+void sb_Poweron_Init(void)
+{
+	AMDSBCFG sb_early_cfg;
+
+	printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() Start:\n", __func__);
+	/* Enable A-Link Base Address */
+	//sb_enable_alink ();
+
+	sb700_cimx_config(&sb_early_cfg);
+	sbPowerOnInit(&sb_early_cfg);
+	printk(BIOS_DEBUG, "cimx/sb700 early.c, %s() End\n", __func__);
+}
+
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
new file mode 100644
index 0000000..8d13cd8
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -0,0 +1,329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <device/device.h>      /* device_t */
+#include <device/pci.h>         /* device_operations */
+#include <device/pci_ids.h>
+#include <arch/ioapic.h>
+#include <device/smbus.h>       /* smbus_bus_operations */
+#include <console/console.h>    /* printk */
+#include "lpc.h"                /* lpc_read_resources */
+#include "Platform.h"   /* Platfrom Specific Definitions */
+#include "sb_cimx.h"
+#include "sb700_cfg.h"                /* sb700 Cimx configuration */
+#include "chip.h"               /* struct southbridge_amd_cimx_sb700_config */
+
+
+/*implement in mainboard.c*/
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config
+static AMDSBCFG *sb_config = &sb_late_cfg;
+
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func      Southbridge CIMx Function ID.
+ * @param[in] data      Southbridge Input Data.
+ * @param[in] sb_config Southbridge configuration structure pointer.
+ *
+ */
+u32 sb700_callout_entry(u32 func, u32 data, void* config)
+{
+	u32 ret = 0;
+
+	printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n");
+	printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n");
+	return ret;
+}
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem = pci_dev_set_subsystem,
+};
+
+static void lpc_enable_resources(device_t dev)
+{
+
+	printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - Start.\n");
+	pci_dev_enable_resources(dev);
+	lpc_enable_childrens_resources(dev);
+	printk(BIOS_DEBUG, "SB700 - Late.c - lpc_enable_resources - End.\n");
+}
+
+static struct device_operations lpc_ops = {
+	.read_resources = lpc_read_resources,
+	.set_resources = lpc_set_resources,
+	.enable_resources = lpc_enable_resources,
+	.init = 0,
+	.scan_bus = scan_static_bus,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+	.ops = &lpc_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_LPC,
+};
+
+
+static struct device_operations sata_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+	.ops = &sata_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390
+};
+
+#if CONFIG_USBDEBUG
+static void usb_set_resources(struct device *dev)
+{
+	struct resource *res;
+	u32 base;
+	u32 old_debug;
+
+	printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - Start.\n");
+	old_debug = get_ehci_debug();
+	set_ehci_debug(0);
+
+	pci_dev_set_resources(dev);
+
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(old_debug);
+	if (!res)
+		return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+	printk(BIOS_DEBUG, "SB700 - Late.c - usb_set_resources - End.\n");
+}
+#endif
+
+
+static struct device_operations usb_ops = {
+	.read_resources = pci_dev_read_resources,
+#if CONFIG_USBDEBUG
+	.set_resources = usb_set_resources,
+#else
+	.set_resources = pci_dev_set_resources,
+#endif
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+/*
+ * The pci id of usb ctrl 0 and 1 are the same.
+ */
+static const struct pci_driver usb_ohci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci3_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
+};
+
+static const struct pci_driver usb_ehci123_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci4_driver __pci_driver = {
+	.ops = &usb_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver azalia_driver __pci_driver = {
+	.ops = &azalia_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_HDA,
+};
+
+#ifdef UNUSED_CODE
+static struct device_operations gec_ops = {
+	.read_resources = pci_dev_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init = 0,
+	.scan_bus = 0,
+	.ops_pci = &lops_pci,
+};
+#endif
+
+static struct device_operations pci_ops = {
+	.read_resources = pci_bus_read_resources,
+	.set_resources = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init = 0,
+	.scan_bus = pci_scan_bridge,
+	.reset_bus = pci_bus_reset,
+	.ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+	.ops = &pci_ops,
+	.vendor = PCI_VENDOR_ID_ATI,
+	.device = PCI_DEVICE_ID_ATI_SB700_PCI,
+};
+
+
+static void sb700_enable(device_t dev)
+{
+	struct southbridge_amd_cimx_sb700_config *sb_chip =
+		(struct southbridge_amd_cimx_sb700_config *)(dev->chip_info);
+
+	printk(BIOS_DEBUG, "sb700_enable() ");
+	switch (dev->path.pci.devfn) {
+		case (0x11 << 3) | 0: /* 0:11.0  SATA */
+			sb700_cimx_config(sb_config);
+			if (dev->enabled) {
+				sb_config->SataController = CIMX_OPTION_ENABLED;
+				if (1 == sb_chip->boot_switch_sata_ide)
+					sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
+				else if (0 == sb_chip->boot_switch_sata_ide)
+					sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
+			} else {
+				sb_config->SataController = CIMX_OPTION_DISABLED;
+			}
+			break;
+
+		case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+		case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+		case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+		case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+			break;
+
+		case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+			{
+#if 1
+				u32 ioapic_base;
+				printk(BIOS_DEBUG, "sm_init().\n");
+				ioapic_base = IO_APIC_ADDR;
+				clear_ioapic(ioapic_base);
+				/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
+#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
+				/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
+				setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+#elif (CONFIG_APIC_ID_OFFSET > 0)
+				/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+				setup_ioapic(ioapic_base, 0);
+#else
+#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
+#endif
+#endif
+			}
+			break;
+
+		case (0x14 << 3) | 1: /* 0:14:1 IDE */
+			break;
+
+		case (0x14 << 3) | 2: /* 0:14:2 HDA */
+			if (dev->enabled) {
+				if (AZALIA_DISABLE == sb_config->AzaliaController) {
+					sb_config->AzaliaController = AZALIA_AUTO;
+				}
+				printk(BIOS_DEBUG, "hda enabled\n");
+			} else {
+				sb_config->AzaliaController = AZALIA_DISABLE;
+				printk(BIOS_DEBUG, "hda disabled\n");
+			}
+			break;
+
+
+		case (0x14 << 3) | 3: /* 0:14:3 LPC */
+			break;
+
+		case (0x14 << 3) | 4: /* 0:14:4 PCI */
+			break;
+
+		case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+			/* call CIMX entry after last device enable */
+			sb_Before_Pci_Init();
+			break;
+
+		default:
+			break;
+	}
+}
+
+struct chip_operations southbridge_amd_cimx_sb700_ops = {
+	CHIP_NAME("ATI SB700")
+	.enable_dev = sb700_enable,
+};
+
+/**
+ * @brief SB Cimx entry point sbBeforePciInit wrapper
+ */
+void sb_Before_Pci_Init(void)
+{
+	printk(BIOS_DEBUG, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbBeforePciInit(sb_config);
+	printk(BIOS_DEBUG, "sb700 %s End\n", __func__);
+}
+
+void sb_After_Pci_Init(void)
+{
+	printk(BIOS_DEBUG, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbAfterPciInit(sb_config);
+	printk(BIOS_DEBUG, "sb700 %s End\n", __func__);
+}
+
+void sb_Late_Post(void)
+{
+	printk(BIOS_DEBUG, "sb700 %s Start\n", __func__);
+	/* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
+	//sb_config->StdHeader.Func = SB_LATE_POST_INIT;
+	//AmdSbDispatcher(sb_config);
+	sbLatePost(sb_config);
+	printk(BIOS_DEBUG, "sb700 %s End\n", __func__);
+}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
new file mode 100644
index 0000000..5d551cc
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/pci.h>
+#include "lpc.h"
+#include <bitops.h>
+#include <arch/io.h>
+#include <console/console.h>	/* printk */
+#include <cbmem.h>
+
+#define BIOSRAM_INDEX   0xcd4
+#define BIOSRAM_DATA    0xcd5
+
+void set_cbmem_toc(struct cbmem_entry *toc)
+{
+	u32 dword = (u32) toc;
+	int nvram_pos = 0xfc, i;
+	for (i = 0; i<4; i++) {
+		outb(nvram_pos, BIOSRAM_INDEX);
+		outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+		nvram_pos++;
+	}
+}
+
+void lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - Start.\n");
+	/* Get the normal pci resources of this device */
+	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
+
+	pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = 0xfec00000;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	compact_resources(dev);
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_read_resources - End.\n");
+}
+
+void lpc_set_resources(struct device *dev)
+{
+	struct resource *res;
+
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - Start.\n");
+	pci_dev_set_resources(dev);
+
+	/* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+	res = find_resource(dev, SPIROM_BASE_ADDRESS);
+	pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_set_resources - End.\n");
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+void lpc_enable_childrens_resources(device_t dev)
+{
+	struct bus *link;
+	u32 reg, reg_x;
+	int var_num = 0;
+	u16 reg_var[3];
+
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
+	reg = pci_read_config32(dev, 0x44);
+	reg_x = pci_read_config32(dev, 0x48);
+
+	for (link = dev->link_list; link; link = link->next) {
+		device_t child;
+		for (child = link->children; child;
+		     child = child->sibling) {
+			if (child->enabled
+			    && (child->path.type == DEVICE_PATH_PNP)) {
+				struct resource *res;
+				for (res = child->resource_list; res; res = res->next) {
+					u32 base, end;	/*  don't need long long */
+					if (!(res->flags & IORESOURCE_IO))
+						continue;
+					base = res->base;
+					end = resource_end(res);
+/*
+					printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+					     dev_path(child), base, end);
+*/
+					switch (base) {
+					case 0x60:	/*  KB */
+					case 0x64:	/*  MS */
+						reg |= (1 << 29);
+						break;
+					case 0x3f8:	/*  COM1 */
+						reg |= (1 << 6);
+						break;
+					case 0x2f8:	/*  COM2 */
+						reg |= (1 << 7);
+						break;
+					case 0x378:	/*  Parallal 1 */
+						reg |= (1 << 0);
+						break;
+					case 0x3f0:	/*  FD0 */
+						reg |= (1 << 26);
+						break;
+					case 0x220:	/*  Aduio 0 */
+						reg |= (1 << 8);
+						break;
+					case 0x300:	/*  Midi 0 */
+						reg |= (1 << 18);
+						break;
+					case 0x400:
+						reg_x |= (1 << 16);
+						break;
+					case 0x480:
+						reg_x |= (1 << 17);
+						break;
+					case 0x500:
+						reg_x |= (1 << 18);
+						break;
+					case 0x580:
+						reg_x |= (1 << 19);
+						break;
+					case 0x4700:
+						reg_x |= (1 << 22);
+						break;
+					case 0xfd60:
+						reg_x |= (1 << 23);
+						break;
+					default:
+						if (var_num >= 3)
+							continue;	/* only 3 var ; compact them ? */
+						switch (var_num) {
+						case 0:
+							reg_x |= (1 << 2);
+							break;
+						case 1:
+							reg_x |= (1 << 24);
+							break;
+						case 2:
+							reg_x |= (1 << 25);
+							break;
+						}
+						reg_var[var_num++] =
+						    base & 0xffff;
+					}
+				}
+			}
+		}
+	}
+	pci_write_config32(dev, 0x44, reg);
+	pci_write_config32(dev, 0x48, reg_x);
+	/* Set WideIO for as many IOs found (fall through is on purpose) */
+	switch (var_num) {
+	case 2:
+		pci_write_config16(dev, 0x90, reg_var[2]);
+	case 1:
+		pci_write_config16(dev, 0x66, reg_var[1]);
+	case 0:
+		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
+		break;
+	}
+	printk(BIOS_DEBUG, "SB700 - Lpc.c - lpc_enable_childrens_resources - End.\n");
+}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h
new file mode 100644
index 0000000..edb13f8
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/lpc.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB700_LPC_H_
+#define _SB700_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS	0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
new file mode 100644
index 0000000..84fe4d0
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _CIMX_H_
+#define _CIMX_H_
+
+#define PM_INDEX	0xcd6
+#define PM_DATA		0xcd7
+
+#define REV_SB700_A11	0x11
+#define REV_SB700_A12	0x12
+
+
+/**
+ * AMD South Bridge CIMx entry point wrapper
+ */
+void sb_Poweron_Init(void);
+void sb_Before_Pci_Init(void);
+void sb_After_Pci_Init(void);
+void sb_Mid_Post_Init(void);
+void sb_Late_Post(void);
+
+
+#if CONFIG_RAMINIT_SYSINFO == 1
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+#endif
+#endif
diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c
new file mode 100644
index 0000000..58dd012
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/smbus.c
@@ -0,0 +1,270 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include "smbus.h"
+#include <console/console.h>	/* printk */
+
+static inline void smbus_delay(void)
+{
+	outb(inb(0x80), 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;
+		if (val == 0) {	/* ready now */
+			return 0;
+		}
+		outb(val, smbus_io_base + SMBHSTSTAT);
+	} while (--loops);
+
+	return -2;		/* time out */
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+	u32 loops;
+
+	loops = SMBUS_TIMEOUT;
+	do {
+		u8 val;
+
+		val = inb(smbus_io_base + SMBHSTSTAT);
+		val &= 0x1f;	/* mask off reserved bits */
+		if (val & 0x1c) {
+			return -5;	/* error */
+		}
+		if (val == 0x02) {
+			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
+			return 0;
+		}
+	} while (--loops);
+
+	return -3;		/* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n");
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTCMD);
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n");
+	return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n");
+	/* set the command... */
+	outb(val, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n");
+	return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n");
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	/* read results of transaction */
+	byte = inb(smbus_io_base + SMBHSTDAT0);
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n");
+	return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+{
+	u8 byte;
+
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
+		printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
+		return -2;	/* not ready */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n");
+	/* set the command/address... */
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+	/* set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+	/* output value */
+	outb(val, smbus_io_base + SMBHSTDAT0);
+
+	byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte &= 0xe3;		/* Clear [4:2] */
+	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
+	outb(byte, smbus_io_base + SMBHSTCTRL);
+
+	/* poll for transaction completion */
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
+		return -3;	/* timeout or error */
+	}
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n");
+	return 0;
+}
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n");
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
+	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n");
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n");
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+	tmp = inl(AB_DATA);
+	/* rpr 4.2
+	 * For certain revisions of the chip, the ABCFG registers,
+	 * with an address of 0x100NN (where 'N' is any hexadecimal
+	 * number), require an extra programming step.*/
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we dont have to do it again. */
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n");
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+{
+	u32 tmp;
+
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n");
+	/* read axindc to tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	tmp = inl(AB_DATA);
+	outl(0, AB_INDX);
+
+	tmp &= ~mask;
+	tmp |= val;
+
+	/* write tmp */
+	outl(space << 29 | space << 3 | 0x30, AB_INDX);
+	outl(axindc, AB_DATA);
+	outl(0, AB_INDX);
+	outl(space << 29 | space << 3 | 0x34, AB_INDX);
+	outl(tmp, AB_DATA);
+	outl(0, AB_INDX);
+	printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n");
+}
+
diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h
new file mode 100644
index 0000000..10e0874
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb700/smbus.h
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _SB700_SMBUS_H_
+#define _SB700_SMBUS_H_
+
+//#include <stdint.h>
+#include <Platform.h> /* SMBUS0_BASE_ADDRESS */
+#ifndef SMBUS0_BASE_ADDRESS
+#error SMBUS0_BASE_ADDRESS not define
+#endif
+#define SMBUS_IO_BASE	SMBUS0_BASE_ADDRESS
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD  0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+/*//SB00.H
+#define AX_INDXC  0
+#define AX_INDXP  2
+#define AXCFG     4
+#define ABCFG     6
+#define RC_INDXC  1
+#define RC_INDXP  3
+*/
+
+#define AB_INDX   0xCD8
+#define AB_DATA   (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)		\
+	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif //_SB700_SMBUS_H_


From gerrit at coreboot.org  Fri Jan 20 06:44:48 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:48 +0100
Subject: [coreboot] New patch to review for coreboot: d7b21e0 SIO: Add
	smsc/sch4037 superio support
References: <I3b113a27541b8efd096f3bd44e6621344ec916a5+0@gerrit.coreboot.org>
Message-ID: <I3b113a27541b8efd096f3bd44e6621344ec916a5+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562

-gerrit

commit d7b21e02ea6e2642053f447a539b38751dff2ffa
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:26 2012 +0800

    SIO: Add smsc/sch4037 superio support
    
    Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/superio/smsc/Kconfig                      |    3 +
 src/superio/smsc/Makefile.inc                 |    2 +
 src/superio/smsc/sch4037/Makefile.inc         |   20 +++
 src/superio/smsc/sch4037/chip.h               |   34 ++++
 src/superio/smsc/sch4037/sch4037.h            |  227 +++++++++++++++++++++++++
 src/superio/smsc/sch4037/sch4037_early_init.c |   71 ++++++++
 src/superio/smsc/sch4037/superio.c            |  123 +++++++++++++
 7 files changed, 480 insertions(+), 0 deletions(-)

diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index 7378d18..ddd5b96 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100
 	bool
 config SUPERIO_SMSC_SMSCSUPERIO
 	bool
+config SUPERIO_SMSC_SCH4037
+	bool
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index 68d4d56..bfdc68e 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -28,3 +29,4 @@ subdirs-y += lpc47n227
 subdirs-y += sio10n268
 subdirs-y += kbc1100
 subdirs-y += smscsuperio
+subdirs-y += sch4037
diff --git a/src/superio/smsc/sch4037/Makefile.inc b/src/superio/smsc/sch4037/Makefile.inc
new file mode 100644
index 0000000..8f36f2a
--- /dev/null
+++ b/src/superio/smsc/sch4037/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c
diff --git a/src/superio/smsc/sch4037/chip.h b/src/superio/smsc/sch4037/chip.h
new file mode 100644
index 0000000..3223750
--- /dev/null
+++ b/src/superio/smsc/sch4037/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SCH_4037_CHIP_H
+#define SUPERIO_SCH_4037_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_sch4037_ops;
+
+struct superio_smsc_sch4037_config {
+
+	struct pc_keyboard keyboard;
+};
+
+#endif //SUPERIO_SCH_4037_CHIP_H
\ No newline at end of file
diff --git a/src/superio/smsc/sch4037/sch4037.h b/src/superio/smsc/sch4037/sch4037.h
new file mode 100644
index 0000000..f429723
--- /dev/null
+++ b/src/superio/smsc/sch4037/sch4037.h
@@ -0,0 +1,227 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SCH_4037_H
+#define SUPERIO_SCH_4037_H
+
+/* BITS Define */
+#ifndef BIT0
+#define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+#define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+#define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+#define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+#define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+#define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+#define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+#define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+#define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+#define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+#define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+#define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+#define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+#define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+#define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+#define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+#define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+#define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+#define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+#define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+#define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+#define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+#define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+#define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+#define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+#define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+#define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+#define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+#define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+#define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+#define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+#define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+#define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+#define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+#define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+#define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+#define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+#define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+#define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+#define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+#define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+#define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+#define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+#define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+#define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+#define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+#define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+#define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+#define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+#define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+#define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+#define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+#define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+#define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+#define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+#define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+#define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+#define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+#define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+#define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+#define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+#define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+#define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+#define BIT63       0x8000000000000000ull
+#endif
+
+#define SCH4037_FDD              0            /* FDD */
+#define SCH4037_LPT              3            /* LPT */
+#define SMSCSUPERIO_SP1          4            /* Com1 */
+#define SMSCSUPERIO_SP2          5            /* Com2 */
+#define SCH4037_RTC              6            /* RTC */
+#define SCH4037_KBC              7            /* KBC */
+#define SCH4037_HWM              8            /* HWM */
+#define SCH4037_RUNTIME          0x0A         /* Runtime */
+#define SCH4037_XBUS             0x0B         /* X-BUS */
+
+#endif //SUPERIO_SCH_4037_H
diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c
new file mode 100644
index 0000000..1ff7aba
--- /dev/null
+++ b/src/superio/smsc/sch4037/sch4037_early_init.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "sch4037.h"
+
+static inline void pnp_enter_conf_state(device_t dev)
+{
+	unsigned port = dev>>8;
+	outb(0x55, port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	unsigned port = dev>>8;
+	outb(0xaa, port);
+}
+
+static inline void sch4037_early_init(unsigned port)
+{
+	device_t dev;
+
+	dev = PNP_DEV (port, SMSCSUPERIO_SP1);
+	pnp_enter_conf_state(dev);
+
+	/*Auto power management*/
+	pnp_write_config (dev, 0x22, BIT3+BIT4+BIT5 );
+	pnp_write_config (dev, 0x23, 0 );
+
+	/* Enable SMSC UART 0 */
+	dev = PNP_DEV (port, SMSCSUPERIO_SP1);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+
+	pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
+	pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
+
+	/* Enabled High speed, disabled MIDI support. */
+	pnp_write_config (dev, 0xF0, 0x02);
+	pnp_set_enable(dev, 1);
+
+	/* Enable keyboard */
+	dev = PNP_DEV (port, SCH4037_KBC);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_irq(dev, 0x70, 1);   /* IRQ 1 */
+	pnp_set_irq(dev, 0x72, 12);   /* IRQ 12 */
+	pnp_set_enable(dev, 1);
+
+	pnp_exit_conf_state(dev);
+
+}
+
diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c
new file mode 100644
index 0000000..af4040f
--- /dev/null
+++ b/src/superio/smsc/sch4037/superio.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "sch4037.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void sch4037_pnp_set_resources(device_t dev);
+static void sch4037_pnp_enable_resources(device_t dev);
+static void sch4037_pnp_enable(device_t dev);
+static void sch4037_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_sch4037_ops = {
+	CHIP_NAME("SMSC SCH4037 Super I/O")
+		.enable_dev = enable_dev,
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = sch4037_pnp_set_resources,
+	.enable_resources = sch4037_pnp_enable_resources,
+	.enable           = sch4037_pnp_enable,
+	.init             = sch4037_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, SCH4037_KBC,  PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+};
+
+static void enable_dev(device_t dev)
+{
+	printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
+	pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void sch4037_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void sch4037_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void sch4037_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+
+	if(dev->enabled) {
+		pnp_set_enable(dev, 1);
+	}
+	else {
+		pnp_set_enable(dev, 0);
+	}
+	pnp_exit_conf_state(dev);
+}
+
+static void sch4037_init(device_t dev)
+{
+	struct superio_smsc_sch4037_config *conf = dev->chip_info;
+	struct resource *res0, *res1;
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	switch(dev->path.pnp.device) {
+
+		case SCH4037_KBC:
+			res0 = find_resource(dev, PNP_IDX_IO0);
+			res1 = find_resource(dev, PNP_IDX_IO1);
+			pc_keyboard_init(&conf->keyboard);
+			break;
+	}
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}


From gerrit at coreboot.org  Fri Jan 20 06:44:49 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:49 +0100
Subject: [coreboot] New patch to review for coreboot: baea69c SIO: Add smsc
	sio1036 superio
References: <Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9+0@gerrit.coreboot.org>
Message-ID: <Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563

-gerrit

commit baea69c7c73861459c239bb285623079a201b321
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:35 2012 +0800

    SIO: Add smsc sio1036 superio
    
    Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/superio/smsc/Kconfig                      |    2 +
 src/superio/smsc/Makefile.inc                 |    1 +
 src/superio/smsc/sio1036/Makefile.inc         |   21 ++++
 src/superio/smsc/sio1036/chip.h               |   34 +++++++
 src/superio/smsc/sio1036/sio1036.h            |   25 +++++
 src/superio/smsc/sio1036/sio1036_early_init.c |  101 ++++++++++++++++++++
 src/superio/smsc/sio1036/superio.c            |  122 +++++++++++++++++++++++++
 7 files changed, 306 insertions(+), 0 deletions(-)

diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index ddd5b96..d4f07ec 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100
 	bool
 config SUPERIO_SMSC_SMSCSUPERIO
 	bool
+config SUPERIO_SMSC_SIO1036
+	bool
 config SUPERIO_SMSC_SCH4037
 	bool
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index bfdc68e..d07afea 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -29,4 +29,5 @@ subdirs-y += lpc47n227
 subdirs-y += sio10n268
 subdirs-y += kbc1100
 subdirs-y += smscsuperio
+subdirs-y += sio1036
 subdirs-y += sch4037
diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc
new file mode 100644
index 0000000..4e48899
--- /dev/null
+++ b/src/superio/smsc/sio1036/Makefile.inc
@@ -0,0 +1,21 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += superio.c
+
diff --git a/src/superio/smsc/sio1036/chip.h b/src/superio/smsc/sio1036/chip.h
new file mode 100644
index 0000000..abed430
--- /dev/null
+++ b/src/superio/smsc/sio1036/chip.h
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_SMSC_SIO1036_CHIP_H
+#define SUPERIO_SMSC_SIO1036_CHIP_H
+
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_kbc1100_ops;
+
+struct superio_smsc_sio1036_config {
+	struct uart8250 com1;
+};
+
+#endif //SUPERIO_SMSC_SIO1036_CHIP_H
+
diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h
new file mode 100644
index 0000000..cdd5a8b
--- /dev/null
+++ b/src/superio/smsc/sio1036/sio1036.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define SIO1036_SP1		0 /* Com1 */
+
+#define UART_POWER_DOWN		(1 << 7)
+#define LPT_POWER_DOWN		(1 << 2)
+#define IR_OUPUT_MUX		(1 << 6)
+
diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c
new file mode 100644
index 0000000..980e8c5
--- /dev/null
+++ b/src/superio/smsc/sio1036/sio1036_early_init.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/romcc_io.h>
+#include "sio1036.h"
+
+#ifndef CONFIG_TTYS0_BASE
+#define CONFIG_TTYS0_BASE 0x3F8
+#endif
+static inline void sio1036_enter_conf_state(device_t dev)
+{
+	unsigned port = dev>>8;
+	outb(0x55, port);
+}
+
+static inline void sio1036_exit_conf_state(device_t dev)
+{
+	unsigned port = dev>>8;
+	outb(0xaa, port);
+}
+
+static u8 detect_sio1036_chip(unsigned port)
+{
+	device_t dev;
+	dev = PNP_DEV (port, SIO1036_SP1);
+	unsigned data;
+	sio1036_enter_conf_state (dev);
+	data = pnp_read_config (dev, 0x0D);
+	sio1036_exit_conf_state(dev);
+	/* detect smsc sio1036 chip */
+	if (data == 0x82) {
+		/* Found SMSC SIO1036 chip */
+		return 0;
+	}
+	else {
+		return -1;
+	};
+}
+
+static inline void sio1036_early_init(unsigned port)
+{
+	device_t dev;
+	dev = PNP_DEV (port, SIO1036_SP1);
+
+	if (detect_sio1036_chip(port) != 0) {
+		/* Not found SMSC SIO1036 */
+		return;
+	}
+	sio1036_enter_conf_state (dev);
+
+	/* Enable SMSC UART 0 */
+	/* Valid configuration cycle */
+	pnp_write_config (dev, 0x00, 0x28);
+
+	/* PP power/mode/cr lock */
+	pnp_write_config (dev, 0x01, 0x98 | LPT_POWER_DOWN);
+	pnp_write_config (dev, 0x02, 0x08 | UART_POWER_DOWN);
+
+	/*Auto power management*/
+	pnp_write_config (dev, 0x07, 0x00 );
+
+	/*ECP FIFO threhod */
+	pnp_write_config (dev, 0x0A, 0x00 | IR_OUPUT_MUX);
+
+	/*GPIO direction register 2 */
+	pnp_write_config (dev, 0x033, 0x00);
+
+	/*UART Mode */
+	pnp_write_config (dev, 0x0C, 0x02);
+
+	/* GPIO polarity regisgter 2 */
+	pnp_write_config (dev, 0x034, 0x00);
+
+	/* Enable SMSC UART 0 */
+	/*Set base io address */
+	pnp_write_config (dev, 0x25, (u8)((u16)CONFIG_TTYS0_BASE >> 2));
+
+	/* Set UART IRQ onto 0x04 */
+	pnp_write_config (dev, 0x28, 0x04);
+
+	sio1036_exit_conf_state(dev);
+}
+
diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c
new file mode 100644
index 0000000..2522d92
--- /dev/null
+++ b/src/superio/smsc/sio1036/superio.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC SIO1036 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "sio1036.h"
+
+/* Forward declarations */
+static void enable_dev(device_t dev);
+static void sio1036_pnp_set_resources(device_t dev);
+static void sio1036_pnp_enable_resources(device_t dev);
+static void sio1036_pnp_enable(device_t dev);
+static void sio1036_init(device_t dev);
+
+static void pnp_enter_conf_state(device_t dev);
+static void pnp_exit_conf_state(device_t dev);
+
+struct chip_operations superio_smsc_sio1036_ops = {
+	CHIP_NAME("SMSC SIO1036 Super I/O")
+		.enable_dev = enable_dev
+};
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = sio1036_pnp_set_resources,
+	.enable_resources = sio1036_pnp_enable_resources,
+	.enable           = sio1036_pnp_enable,
+	.init             = sio1036_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{},
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+static void sio1036_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void sio1036_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void sio1036_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+
+	if(dev->enabled) {
+		pnp_set_enable(dev, 1);
+	}
+	else {
+		pnp_set_enable(dev, 0);
+	}
+	pnp_exit_conf_state(dev);
+}
+
+static void sio1036_init(device_t dev)
+{
+	struct superio_smsc_sio1036_config *conf = dev->chip_info;
+	struct resource *res0, *res1;
+
+
+
+	if (!dev->enabled) {
+		return;
+	}
+
+	switch(dev->path.pnp.device) {
+
+		default:
+			break;
+	}
+}
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+


From gerrit at coreboot.org  Fri Jan 20 06:44:50 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:50 +0100
Subject: [coreboot] New patch to review for coreboot: c662766 Mainboard: Add
	AMD dinar mainboard.
References: <Id97d35e7bca9f0d422841e23f4b762f1ed101ea0+0@gerrit.coreboot.org>
Message-ID: <Id97d35e7bca9f0d422841e23f4b762f1ed101ea0+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564

-gerrit

commit c6627666bb8e1b78394a777bc3739458fbbd4c64
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:46 2012 +0800

    Mainboard: Add AMD dinar mainboard.
    
    Dinar mainboard is an AMD evaluation board for
    Orochi Platform family15 model 00-0f processor.
    
    The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
    16 cores InterLagos Opteron processor are supported.
    Windows 7 are verified on this platform.
    
    Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/amd/Kconfig                        |    3 +
 src/mainboard/amd/dinar/BiosCallOuts.c           |  563 ++++++
 src/mainboard/amd/dinar/BiosCallOuts.h           |   79 +
 src/mainboard/amd/dinar/Kconfig                  |  211 ++
 src/mainboard/amd/dinar/Makefile.inc             |   40 +
 src/mainboard/amd/dinar/Oem.h                    |   79 +
 src/mainboard/amd/dinar/OptionsIds.h             |   64 +
 src/mainboard/amd/dinar/PlatformGnbPcie.c        |  176 ++
 src/mainboard/amd/dinar/PlatformGnbPcieComplex.h |   72 +
 src/mainboard/amd/dinar/acpi/cpstate.asl         |   75 +
 src/mainboard/amd/dinar/acpi/ide.asl             |  244 +++
 src/mainboard/amd/dinar/acpi/routing.asl         |  311 +++
 src/mainboard/amd/dinar/acpi/sata.asl            |  149 ++
 src/mainboard/amd/dinar/acpi/usb.asl             |   20 +
 src/mainboard/amd/dinar/acpi_tables.c            |  320 +++
 src/mainboard/amd/dinar/agesawrapper.c           |  628 ++++++
 src/mainboard/amd/dinar/agesawrapper.h           |  329 +++
 src/mainboard/amd/dinar/buildOpts.c              |  483 +++++
 src/mainboard/amd/dinar/chip.h                   |   23 +
 src/mainboard/amd/dinar/cmos.layout              |  118 ++
 src/mainboard/amd/dinar/devicetree.cb            |  104 +
 src/mainboard/amd/dinar/dimmSpd.c                |  333 +++
 src/mainboard/amd/dinar/dsdt.asl                 | 1157 +++++++++++
 src/mainboard/amd/dinar/fadt.c                   |  173 ++
 src/mainboard/amd/dinar/get_bus_conf.c           |  156 ++
 src/mainboard/amd/dinar/gpio.c                   |  482 +++++
 src/mainboard/amd/dinar/gpio.h                   | 2329 ++++++++++++++++++++++
 src/mainboard/amd/dinar/irq_tables.c             |  122 ++
 src/mainboard/amd/dinar/mainboard.c              |  138 ++
 src/mainboard/amd/dinar/mptable.c                |  196 ++
 src/mainboard/amd/dinar/platform_cfg.h           |   54 +
 src/mainboard/amd/dinar/rd890_cfg.c              |  274 +++
 src/mainboard/amd/dinar/rd890_cfg.h              |  175 ++
 src/mainboard/amd/dinar/reset.c                  |   66 +
 src/mainboard/amd/dinar/romstage.c               |  157 ++
 src/mainboard/amd/dinar/sb700_cfg.c              |  142 ++
 src/mainboard/amd/dinar/sb700_cfg.h              |  237 +++
 37 files changed, 10282 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/amd/Kconfig b/src/mainboard/amd/Kconfig
index 62ae584..c6de048 100644
--- a/src/mainboard/amd/Kconfig
+++ b/src/mainboard/amd/Kconfig
@@ -7,6 +7,8 @@ config BOARD_AMD_DB800
 	bool "DB800 (Salsa)"
 config BOARD_AMD_DBM690T
 	bool "DBM690T (Herring)"
+config BOARD_AMD_DINAR
+	bool "Dinar"
 config BOARD_AMD_MAHOGANY
 	bool "Mahogany"
 config BOARD_AMD_MAHOGANY_FAM10
@@ -39,6 +41,7 @@ endchoice
 
 source "src/mainboard/amd/db800/Kconfig"
 source "src/mainboard/amd/dbm690t/Kconfig"
+source "src/mainboard/amd/dinar/Kconfig"
 source "src/mainboard/amd/mahogany/Kconfig"
 source "src/mainboard/amd/mahogany_fam10/Kconfig"
 source "src/mainboard/amd/norwich/Kconfig"
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c
new file mode 100644
index 0000000..39e1d13
--- /dev/null
+++ b/src/mainboard/amd/dinar/BiosCallOuts.c
@@ -0,0 +1,563 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "agesawrapper.h"
+#include "amdlib.h"
+#include "BiosCallOuts.h"
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "SB700.h"
+
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01   1
+#endif
+
+#ifndef SB_GPIO_REG24
+#define SB_GPIO_REG24   24
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27   27
+#endif
+
+STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_ALLOCATE_BUFFER,
+		BiosAllocateBuffer
+	},
+
+	{AGESA_DEALLOCATE_BUFFER,
+		BiosDeallocateBuffer
+	},
+
+	{AGESA_DO_RESET,
+		BiosReset
+	},
+
+	{AGESA_LOCATE_BUFFER,
+		BiosLocateBuffer
+	},
+
+	{AGESA_READ_SPD,
+		BiosReadSpd
+	},
+
+	{AGESA_READ_SPD_RECOVERY,
+		BiosDefaultRet
+	},
+
+	{AGESA_RUNFUNC_ONAP,
+		BiosRunFuncOnAp
+	},
+
+	{AGESA_GNB_PCIE_SLOT_RESET,
+		BiosGnbPcieSlotReset
+	},
+
+	{AGESA_GET_IDS_INIT_DATA,
+		BiosGetIdsInitData
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT,
+		BiosHookBeforeDramInit
+	},
+
+	{AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,
+		BiosHookBeforeDramInitRecovery
+	},
+
+	{AGESA_HOOKBEFORE_DQS_TRAINING,
+		BiosHookBeforeDQSTraining
+	},
+
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF,
+		BiosHookBeforeExitSelfRefresh
+	},
+};
+
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINTN i;
+	AGESA_STATUS CalloutStatus;
+	UINTN CallOutCount = sizeof (BiosCallouts) / sizeof (BiosCallouts [0]);
+
+	for (i = 0; i < CallOutCount; i++)
+	{
+		if (BiosCallouts[i].CalloutName == Func)
+		{
+			break;
+		}
+	}
+
+	if(i >= CallOutCount)
+	{
+		return AGESA_UNSUPPORTED;
+	}
+
+	CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+
+	return CalloutStatus;
+}
+
+
+CONST IDS_NV_ITEM IdsData[] =
+{
+	/*{
+	  AGESA_IDS_NV_MAIN_PLL_CON,
+	  0x1
+	  },
+	  {
+	  AGESA_IDS_NV_MAIN_PLL_FID_EN,
+	  0x1
+	  },
+	  {
+	  AGESA_IDS_NV_MAIN_PLL_FID,
+	  0x8
+	  },
+
+	  {
+	  AGESA_IDS_NV_CUSTOM_NB_PSTATE,
+	  },
+	  {
+	  AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL,
+	  },
+	  {
+	  AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL,
+	  },
+	  {
+	  AGESA_IDS_NV_FORCE_NB_PSTATE,
+	  },
+	  */
+	{
+		0xFFFF,
+			0xFFFF
+	}
+};
+
+#define   NUM_IDS_ENTRIES    (sizeof (IdsData) / sizeof (IDS_NV_ITEM))
+
+
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINTN   i;
+	IDS_NV_ITEM *IdsPtr;
+
+	IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
+
+	if (Data == IDS_CALLOUT_INIT) {
+		for (i = 0; i < NUM_IDS_ENTRIES; i++) {
+			IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue;
+			IdsPtr[i].IdsNvId = IdsData[i].IdsNvId;
+		}
+	}
+	return AGESA_SUCCESS;
+}
+
+
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINT32              AvailableHeapSize;
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              CurrNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              BestFitNodeOffset;
+	UINT32              BestFitPrevNodeOffset;
+	UINT32              NextFreeOffset;
+	BIOS_BUFFER_NODE   *CurrNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *BestFitNodePtr;
+	BIOS_BUFFER_NODE   *BestFitPrevNodePtr;
+	BIOS_BUFFER_NODE   *NextFreePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr);
+	AllocParams->BufferPointer = NULL;
+
+	AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER);
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
+		/* First allocation */
+		CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER);
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
+		CurrNodePtr->BufferSize = AllocParams->BufferLength;
+		CurrNodePtr->NextNodeOffset = 0;
+		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE);
+
+		/* Update the remaining free space */
+		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE);
+		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize;
+		FreedNodePtr->NextNodeOffset = 0;
+
+		/* Update the offsets for Allocated and Freed nodes */
+		BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset;
+		BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset;
+	} else {
+		/* Find out whether BufferHandle has been allocated on the heap. */
+		/* If it has, return AGESA_BOUNDS_CHK */
+		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+
+		while (CurrNodeOffset != 0) {
+			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
+				return AGESA_BOUNDS_CHK;
+			}
+			CurrNodeOffset = CurrNodePtr->NextNodeOffset;
+			/* If BufferHandle has not been allocated on the heap, CurrNodePtr here points
+			   to the end of the allocated nodes list.
+			   */
+
+		}
+		/* Find the node that best fits the requested buffer size */
+		FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+		PrevNodeOffset = FreedNodeOffset;
+		BestFitNodeOffset = 0;
+		BestFitPrevNodeOffset = 0;
+		while (FreedNodeOffset != 0) {
+			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				if (BestFitNodeOffset == 0) {
+					/* First node that fits the requested buffer size */
+					BestFitNodeOffset = FreedNodeOffset;
+					BestFitPrevNodeOffset = PrevNodeOffset;
+				} else {
+					/* Find out whether current node is a better fit than the previous nodes */
+					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
+						BestFitNodeOffset = FreedNodeOffset;
+						BestFitPrevNodeOffset = PrevNodeOffset;
+					}
+				}
+			}
+			PrevNodeOffset = FreedNodeOffset;
+			FreedNodeOffset = FreedNodePtr->NextNodeOffset;
+		} /* end of while loop */
+
+
+		if (BestFitNodeOffset == 0) {
+			/* If we could not find a node that fits the requested buffer */
+			/* size, return AGESA_BOUNDS_CHK */
+			return AGESA_BOUNDS_CHK;
+		} else {
+			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+
+			/* If BestFitNode is larger than the requested buffer, fragment the node further */
+			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) {
+				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE);
+
+				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE));
+				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
+			} else {
+				/* Otherwise, next free node is NextNodeOffset of BestFitNode */
+				NextFreeOffset = BestFitNodePtr->NextNodeOffset;
+			}
+
+			/* If BestFitNode is the first buffer in the list, then update
+			   StartOfFreedNodes to reflect the new free node
+			   */
+			if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) {
+				BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset;
+			} else {
+				BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset;
+			}
+
+			/* Add BestFitNode to the list of Allocated nodes */
+			CurrNodePtr->NextNodeOffset = BestFitNodeOffset;
+			BestFitNodePtr->BufferSize = AllocParams->BufferLength;
+			BestFitNodePtr->BufferHandle = AllocParams->BufferHandle;
+			BestFitNodePtr->NextNodeOffset = 0;
+
+			/* Remove BestFitNode from list of Freed nodes */
+			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE);
+		}
+	}
+
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+
+	UINT8               *BiosHeapBaseAddr;
+	UINT32              AllocNodeOffset;
+	UINT32              PrevNodeOffset;
+	UINT32              NextNodeOffset;
+	UINT32              FreedNodeOffset;
+	UINT32              EndNodeOffset;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_BUFFER_NODE   *PrevNodePtr;
+	BIOS_BUFFER_NODE   *FreedNodePtr;
+	BIOS_BUFFER_NODE   *NextNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	/* Find target node to deallocate in list of allocated nodes.
+	   Return AGESA_BOUNDS_CHK if the BufferHandle is not found
+	   */
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	PrevNodeOffset = AllocNodeOffset;
+
+	while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			return AGESA_BOUNDS_CHK;
+		}
+		PrevNodeOffset = AllocNodeOffset;
+		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	}
+
+	/* Remove target node from list of allocated nodes */
+	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+
+	/* Zero out the buffer, and clear the BufferHandle */
+	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	AllocNodePtr->BufferHandle = 0;
+	AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE);
+
+	/* Add deallocated node in order to the list of freed nodes */
+	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
+	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+
+	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize;
+
+	if (AllocNodeOffset < FreedNodeOffset) {
+		/* Add to the start of the freed list */
+		if (EndNodeOffset == FreedNodeOffset) {
+			/* If the freed node is adjacent to the first node in the list, concatenate both nodes */
+			AllocNodePtr->BufferSize += FreedNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset;
+
+			/* Clear the BufferSize and NextNodeOffset of the previous first node */
+			FreedNodePtr->BufferSize = 0;
+			FreedNodePtr->NextNodeOffset = 0;
+
+		} else {
+			/* Otherwise, add freed node to the start of the list
+			   Update NextNodeOffset and BufferSize to include the
+			   size of BIOS_BUFFER_NODE
+			   */
+			AllocNodePtr->NextNodeOffset = FreedNodeOffset;
+		}
+		/* Update StartOfFreedNodes to the new first node */
+		BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset;
+	} else {
+		/* Traverse list of freed nodes to find where the deallocated node
+		   should be place
+		   */
+		NextNodeOffset = FreedNodeOffset;
+		NextNodePtr = FreedNodePtr;
+		while (AllocNodeOffset > NextNodeOffset) {
+			PrevNodeOffset = NextNodeOffset;
+			if (NextNodePtr->NextNodeOffset == 0) {
+				break;
+			}
+			NextNodeOffset = NextNodePtr->NextNodeOffset;
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+		}
+
+		/* If deallocated node is adjacent to the next node,
+		   concatenate both nodes
+		   */
+		if (NextNodeOffset == EndNodeOffset) {
+			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			AllocNodePtr->BufferSize += NextNodePtr->BufferSize;
+			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
+
+			NextNodePtr->BufferSize = 0;
+			NextNodePtr->NextNodeOffset = 0;
+		} else {
+			/*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */
+			AllocNodePtr->NextNodeOffset = NextNodeOffset;
+		}
+		/* If deallocated node is adjacent to the previous node,
+		   concatenate both nodes
+		   */
+		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize;
+		if (AllocNodeOffset == EndNodeOffset) {
+			PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
+			PrevNodePtr->BufferSize += AllocNodePtr->BufferSize;
+
+			AllocNodePtr->BufferSize = 0;
+			AllocNodePtr->NextNodeOffset = 0;
+		} else {
+			PrevNodePtr->NextNodeOffset = AllocNodeOffset;
+		}
+	}
+	return AGESA_SUCCESS;
+}
+
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	UINT32              AllocNodeOffset;
+	UINT8               *BiosHeapBaseAddr;
+	BIOS_BUFFER_NODE   *AllocNodePtr;
+	BIOS_HEAP_MANAGER  *BiosHeapBasePtr;
+	AGESA_BUFFER_PARAMS *AllocParams;
+
+	AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr;
+
+	BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS;
+	BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS;
+
+	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
+	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+
+	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
+		if (AllocNodePtr->NextNodeOffset == 0) {
+			AllocParams->BufferPointer = NULL;
+			AllocParams->BufferLength = 0;
+			return AGESA_BOUNDS_CHK;
+		} else {
+			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
+			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		}
+	}
+
+	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE));
+	AllocParams->BufferLength = AllocNodePtr->BufferSize;
+
+	return AGESA_SUCCESS;
+
+}
+
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS        Status;
+
+	Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr);
+	return Status;
+}
+
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS        Status;
+	UINT8                 Value;
+	UINTN               ResetType;
+	AMD_CONFIG_PARAMS   *StdHeader;
+
+	ResetType = Data;
+	StdHeader = ConfigPtr;
+
+	//
+	// Perform the RESET based upon the ResetType. In case of
+	// WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to
+	// AmdResetManager. During the critical condition, where reset is required
+	// immediately, the reset will be invoked directly by writing 0x04 to port
+	// 0xCF9 (Reset Port).
+	//
+	switch (ResetType) {
+		case WARM_RESET_WHENEVER:
+		case COLD_RESET_WHENEVER:
+			break;
+
+		case WARM_RESET_IMMEDIATELY:
+		case COLD_RESET_IMMEDIATELY:
+			Value = 0x06;
+			LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+			break;
+
+		default:
+			break;
+	}
+
+	Status = 0;
+	return Status;
+}
+
+AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS Status;
+	Status = AmdMemoryReadSPD (Func, Data, (AGESA_READ_SPD_PARAMS *)ConfigPtr);
+
+	return Status;
+}
+
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_UNSUPPORTED;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS      Status;
+	UINTN             FcnData;
+	MEM_DATA_STRUCT   *MemData;
+	UINT32            AcpiMmioAddr;
+	UINT32            GpioMmioAddr;
+	UINT8             Data8;
+	UINT16            Data16;
+	UINT8             TempData8;
+
+	FcnData = Data;
+	MemData = ConfigPtr;
+
+	Status  = AGESA_SUCCESS;
+	/* Get SB MMIO Base (AcpiMmioAddr) */
+	WriteIo8 (0xCD6, 0x27);
+	Data8   = ReadIo8(0xCD7);
+	Data16  = Data8<<8;
+	WriteIo8 (0xCD6, 0x26);
+	Data8   = ReadIo8(0xCD7);
+	Data16  |= Data8;
+	AcpiMmioAddr = (UINT32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	Status = AGESA_SUCCESS;
+	return Status;
+}
+
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	return AGESA_SUCCESS;
+}
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS Status;
+
+	Status = AGESA_SUCCESS;
+	return  Status;
+}
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.h b/src/mainboard/amd/dinar/BiosCallOuts.h
new file mode 100644
index 0000000..22451aa
--- /dev/null
+++ b/src/mainboard/amd/dinar/BiosCallOuts.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _BIOS_CALLOUT_H_
+#define _BIOS_CALLOUT_H_
+
+#include "Porting.h"
+#include "AGESA.h"
+
+#define BIOS_HEAP_START_ADDRESS  0x00010000
+#define BIOS_HEAP_SIZE       0x20000   /* 64MB */
+
+typedef struct _BIOS_HEAP_MANAGER {
+	//UINT32 AvailableSize;
+	UINT32 StartOfAllocatedNodes;
+	UINT32 StartOfFreedNodes;
+} BIOS_HEAP_MANAGER;
+
+typedef struct _BIOS_BUFFER_NODE {
+	UINT32 BufferHandle;
+	UINT32 BufferSize;
+	UINT32 NextNodeOffset;
+} BIOS_BUFFER_NODE;
+/*
+ * CALLOUTS
+ */
+AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* REQUIRED CALLOUTS
+ * AGESA ADVANCED CALLOUTS - CPU
+ */
+AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/* AGESA ADVANCED CALLOUTS - MEMORY */
+AGESA_STATUS BiosReadSpd (UINT32  Func,UINT32  Data,VOID *ConfigPtr);
+
+/* BIOS DEFAULT RET */
+AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeDramInitRecovery (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/*  Call the host environment interface to provide a user hook opportunity. */
+AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+/* PCIE slot reset control */
+AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
+#define SB_GPIO_REG02   2
+#define SB_GPIO_REG09   9
+#define SB_GPIO_REG10   10
+#define SB_GPIO_REG15   15
+#define SB_GPIO_REG17   17
+#define SB_GPIO_REG21   21
+#define SB_GPIO_REG25   25
+#define SB_GPIO_REG28   28
+#endif //_BIOS_CALLOUT_H_
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig
new file mode 100644
index 0000000..dcb4c52
--- /dev/null
+++ b/src/mainboard/amd/dinar/Kconfig
@@ -0,0 +1,211 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+if BOARD_AMD_DINAR
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_AMD_AGESA_FAMILY15
+	select CPU_AMD_SOCKET_G34
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15
+	select NORTHBRIDGE_AMD_CIMX_RD890
+	select SOUTHBRIDGE_AMD_CIMX_SB700
+	select SUPERIO_SMSC_SCH4037
+	select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+	select LIFT_BSP_APIC_ID
+	select SERIAL_CPU_INIT
+	select BOARD_ROMSIZE_KB_2048
+	select BOARD_HAS_FADT
+	select HAVE_BUS_CONFIG
+	select HAVE_OPTION_TABLE
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_MAINBOARD_RESOURCES
+	select HAVE_HARD_RESET
+	select HAVE_ACPI_TABLES
+	select HAVE_ACPI_RESUME
+	select ENABLE_APIC_EXT_ID
+	select TINY_BOOTBLOCK
+	select GFXUMA
+
+config MAINBOARD_DIR
+	string
+	default amd/dinar
+
+config APIC_ID_OFFSET
+	hex
+	default 0x0
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Dinar"
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x200000
+
+config MAX_CPUS
+	int
+	default 64
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 16
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config RAMTOP
+	hex
+	default 0x1000000
+
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+config STACK_SIZE
+	hex
+	default 0x10000
+
+config ACPI_SSDTX_NUM
+	int
+	default 0
+
+config RAMBASE
+	hex
+	default 0x200000
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff00000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+
+config SIO_PORT
+	hex
+	default 0x2e
+
+config DRIVERS_PS2_KEYBOARD
+	bool
+	default y
+
+config WARNINGS_ARE_ERRORS
+	bool
+	default n
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config VGA_BIOS
+	bool
+	default n
+
+config VGA_BIOS_ID
+	depends on VGA_BIOS
+	default "1002,515e"
+
+config AHCI_BIOS
+	bool
+	default y
+
+config AHCI_BIOS_FILE
+	string "AHCI ROM path and filename"
+	depends on AHCI_BIOS
+	default "site-local/ahci/sb700.bin"
+
+config AHCI_BIOS_ID
+	string "AHCI device PCI IDs"
+	depends on AHCI_BIOS
+	default "1002,4391"
+
+config XHC_BIOS
+	bool
+	default n
+
+config XHC_BIOS_FILE
+	string "XHC BIOS path and filename"
+	depends on XHC_BIOS
+	default "site-local/xhc/Xhc.rom"
+
+config XHC_BIOS_ID
+	string "XHC device PCI IDs"
+	depends on XHC_BIOS
+	default "1022,7812"
+
+config CONSOLE_POST
+	bool
+	depends on !NO_POST
+	default n
+
+config SATA_CONTROLLER_MODE
+	hex
+	default 0x0
+	depends on SOUTHBRIDGE_AMD_CIMX_SB700
+
+config ONBOARD_LAN
+	bool
+	default y
+
+config ONBOARD_1394
+	bool
+	default y
+
+config ONBOARD_USB30
+	bool
+	default n
+
+config ONBOARD_BLUETOOTH
+	bool
+	default y
+
+config ONBOARD_WEBCAM
+	bool
+	default y
+
+config ONBOARD_TRAVIS
+	bool
+	default y
+
+config ONBOARD_LIGHTSENSOR
+	bool
+	default n
+
+config PCI_ROM_RUN
+	bool
+	default n
+
+config UDELAY_IO
+	bool
+	default n
+
+config REDIRECT_CIMX_TRACE_TO_SERIAL
+	bool "Redirect CIMX Trace to serial console"
+	default y
+
+endif # BOARD_AMD_DINAR
diff --git a/src/mainboard/amd/dinar/Makefile.inc b/src/mainboard/amd/dinar/Makefile.inc
new file mode 100644
index 0000000..89e6d42
--- /dev/null
+++ b/src/mainboard/amd/dinar/Makefile.inc
@@ -0,0 +1,40 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+romstage-y += buildOpts.c
+romstage-y += agesawrapper.c
+romstage-y += dimmSpd.c
+romstage-y += BiosCallOuts.c
+romstage-y += sb700_cfg.c
+romstage-y += rd890_cfg.c
+#romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += agesawrapper.c
+ramstage-y += dimmSpd.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += sb700_cfg.c
+ramstage-y += rd890_cfg.c
+#ramstage-y += PlatformGnbPcie.c
+
+ramstage-y += reset.c
+
+AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
+AGESA_ROOT ?= $(AGESA_PREFIX)/$(if $(CONFIG_CPU_AMD_AGESA_FAMILY15),f15,\
+		echo `wrong configuration`)
diff --git a/src/mainboard/amd/dinar/Oem.h b/src/mainboard/amd/dinar/Oem.h
new file mode 100644
index 0000000..67b1314
--- /dev/null
+++ b/src/mainboard/amd/dinar/Oem.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _AMD_SB_CIMx_OEM_H_
+#define _AMD_SB_CIMx_OEM_H_
+
+#define MOVE_PCIEBAR_TO_F0000000
+
+#define LEGACY_FREE                                     0x00
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option]     MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef  MOVE_PCIEBAR_TO_F0000000
+#define PCIEX_BASE_ADDRESS           0xF8000000
+#else
+#define PCIEX_BASE_ADDRESS           0xE0000000
+#endif
+
+
+#define SMBUS0_BASE_ADDRESS                     0xB00
+#define SMBUS1_BASE_ADDRESS                     0xB20
+#define SIO_PME_BASE_ADDRESS            0xE00
+#define SPI_BASE_ADDRESS                        0xFEC10000
+
+#define WATCHDOG_TIMER_BASE_ADDRESS     0xFEC000F0                      // Watchdog Timer Base Address
+#define HPET_BASE_ADDRESS                       0xFED00000                      // HPET Base address
+
+#define PM1_EVT_BLK_ADDRESS                     0x800                           //      AcpiPm1EvtBlkAddr;
+#define PM1_CNT_BLK_ADDRESS                     0x804                           //      AcpiPm1CntBlkAddr;
+#define PM1_TMR_BLK_ADDRESS                     0x808                           //      AcpiPmTmrBlkAddr;
+#define CPU_CNT_BLK_ADDRESS                     0x810                           //      CpuControlBlkAddr;
+#define GPE0_BLK_ADDRESS                        0x820                           //  AcpiGpe0BlkAddr;
+#define SMI_CMD_PORT                            0xB0                            //      SmiCmdPortAddr;
+#define ACPI_PMA_CNT_BLK_ADDRESS        0xFE00                          //      AcpiPmaCntBlkAddr;
+
+#define EC_LDN5_MAILBOX_ADDRESS         0x550
+#define EC_LDN5_IRQ                                     0x05
+#define EC_LDN9_MAILBOX_ADDRESS         0x3E
+
+#define SATA_IDE_MODE_SSID                      0x43901002
+#define SATA_RAID_MODE_SSID                     0x43921002
+#define SATA_RAID5_MODE_SSID            0x43931002
+#define SATA_AHCI_SSID                          0x43911002
+#define OHCI0_SSID                                      0x43971002
+#define OHCI1_SSID                                      0x43981002
+#define EHCI0_SSID                                      0x43961002
+#define OHCI2_SSID                                      0x43971002
+#define OHCI3_SSID                                      0x43981002
+#define EHCI1_SSID                                      0x43961002
+#define OHCI4_SSID                                      0x43991002
+
+#define SMBUS_SSID                                      0x43851002
+#define IDE_SSID                                        0x439C1002
+#define AZALIA_SSID                                     0x43831002
+#define LPC_SSID                                        0x439D1002
+#define P2P_SSID                                        0x43841002
+
+#define RESERVED_VALUE                          0x00
+
+#endif //ifndef _AMD_SB_CIMx_OEM_H_
diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h
new file mode 100644
index 0000000..e1d397e
--- /dev/null
+++ b/src/mainboard/amd/dinar/OptionsIds.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 12067 $   @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $
+ */
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ *  This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ *    IDSOPT_IDS_ENABLED
+ *    IDSOPT_ERROR_TRAP_ENABLED
+ *    IDSOPT_CONTROL_ENABLED
+ *    IDSOPT_TRACING_ENABLED
+ *    IDSOPT_PERF_ANALYSIS
+ *    IDSOPT_ASSERT_ENABLED
+ *    IDS_DEBUG_PORT
+ *    IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ *
+ **/
+
+//#define IDSOPT_IDS_ENABLED     TRUE
+//#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_ASSERT_ENABLED  TRUE
+
+//#define IDSOPT_DEBUG_ENABLED  FALSE
+//#undef IDSOPT_HOST_SIMNOW
+//#define IDSOPT_HOST_SIMNOW    FALSE
+//#undef IDSOPT_HOST_HDT
+//#define IDSOPT_HOST_HDT       FALSE
+//#define IDS_DEBUG_PORT    0x80
+
+#endif
diff --git a/src/mainboard/amd/dinar/PlatformGnbPcie.c b/src/mainboard/amd/dinar/PlatformGnbPcie.c
new file mode 100644
index 0000000..277d247
--- /dev/null
+++ b/src/mainboard/amd/dinar/PlatformGnbPcie.c
@@ -0,0 +1,176 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "heapManager.h"
+#include "PlatformGnbPcieComplex.h"
+#include "Filecode.h"
+
+#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
+
+PCIe_PORT_DESCRIPTOR PortList [] = {
+	// Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+	{
+		0,   //Descriptor flags
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+	{
+		0,   //Descriptor flags
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
+	{
+		0, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+	},
+	// Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
+		PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+	}
+	// Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
+	//			{
+	//			  DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+	//			  PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
+	//			  PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+	//			}
+};
+
+PCIe_DDI_DESCRIPTOR DdiList [] = {
+	// Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
+	{
+		0,   //Descriptor flags
+		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+	},
+	// Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
+	{
+		DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+		PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+		PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
+	}
+};
+
+PCIe_COMPLEX_DESCRIPTOR Llano = {
+	DESCRIPTOR_TERMINATE_LIST,
+	0,
+	&PortList[0],
+	&DdiList[0]
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the binary block
+ *    interface (call-out port) to provide a user hook opportunity
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID
+OemCustomizeInitEarly (
+		IN  OUT AMD_EARLY_PARAMS    *InitEarly
+		)
+{
+	AGESA_STATUS         Status;
+	VOID                 *LlanoPcieComplexListPtr;
+	VOID                 *LlanoPciePortPtr;
+	VOID                 *LlanoPcieDdiPtr;
+
+	ALLOCATE_HEAP_PARAMS AllocHeapParams;
+
+	// GNB PCIe topology Porting
+
+	//
+	// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+	//
+	AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR)  +
+			sizeof (PCIe_PORT_DESCRIPTOR) * 7 +
+			sizeof (PCIe_DDI_DESCRIPTOR)) * 6;
+
+	AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
+	AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
+	Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
+	if ( Status!= AGESA_SUCCESS) {
+		// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
+		ASSERT(FALSE);
+		return Status;
+	}
+
+	LlanoPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
+	LlanoPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
+
+	AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 7;
+	LlanoPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
+
+	LibAmdMemFill (LlanoPcieComplexListPtr,
+			0,
+			sizeof (PCIe_COMPLEX_DESCRIPTOR),
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (LlanoPciePortPtr,
+			0,
+			sizeof (PCIe_PORT_DESCRIPTOR) * 7,
+			&InitEarly->StdHeader);
+
+	LibAmdMemFill (LlanoPcieDdiPtr,
+			0,
+			sizeof (PCIe_DDI_DESCRIPTOR) * 6,
+			&InitEarly->StdHeader);
+
+	LibAmdMemCopy  (LlanoPcieComplexListPtr, &Llano, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader);
+	LibAmdMemCopy  (LlanoPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader);
+	LibAmdMemCopy  (LlanoPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader);
+
+
+	((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
+	((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
+
+	InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
+	InitEarly->GnbConfig.PsppPolicy      = 0;
+}
+
diff --git a/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..c10d251
--- /dev/null
+++ b/src/mainboard/amd/dinar/PlatformGnbPcieComplex.h
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
+#define _PLATFORM_GNB_PCIE_COMPLEX_H
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+//GNB GPP Port4
+#define GNB_GPP_PORT4_PORT_PRESENT      1  //0:Disable 1:Enable
+#define GNB_GPP_PORT4_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT4_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT4_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT4_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port5
+#define GNB_GPP_PORT5_PORT_PRESENT      1  //0:Disable 1:Enable
+#define GNB_GPP_PORT5_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT5_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT5_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT5_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port6
+#define GNB_GPP_PORT6_PORT_PRESENT      1  //0:Disable 1:Enable
+#define GNB_GPP_PORT6_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT6_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT6_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT6_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port7
+#define GNB_GPP_PORT7_PORT_PRESENT      1  //0:Disable 1:Enable
+#define GNB_GPP_PORT7_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT7_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT7_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT7_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+//GNB GPP Port8
+#define GNB_GPP_PORT8_PORT_PRESENT      1  //0:Disable 1:Enable
+#define GNB_GPP_PORT8_SPEED_MODE        2  //0:Auto 1:GEN1 2:GEN2
+#define GNB_GPP_PORT8_LINK_ASPM         3  //0:Disable 1:L0s 2:L1 3:L0s+L1
+#define GNB_GPP_PORT8_CHANNEL_TYPE      4  //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+                                           //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
+#define GNB_GPP_PORT8_HOTPLUG_SUPPORT   0  //0:Disable 1:Basic 3:Enhanced
+
+VOID
+OemCustomizeInitEarly (
+  IN  OUT AMD_EARLY_PARAMS    *InitEarly
+  );
+
+#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
diff --git a/src/mainboard/amd/dinar/acpi/cpstate.asl b/src/mainboard/amd/dinar/acpi/cpstate.asl
new file mode 100644
index 0000000..ea670a3
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi/cpstate.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system.  It is included into the DSDT for each
+ * core.  It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+	{
+		Scope (\_PR) {
+		Processor(CPU0,0,0x808,0x06) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU1,1,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU2,2,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+		Processor(CPU3,3,0x0,0x0) {
+			#include "cpstate.asl"
+		}
+	}
+*/
+	/* P-state support: The maximum number of P-states supported by the */
+	/* CPUs we'll use is 6. */
+	/* Get from AMI BIOS. */
+	Name(_PSS, Package(){
+		Package ()
+		{
+		    0x00000AF0,
+		    0x0000BF81,
+		    0x00000002,
+		    0x00000002,
+		    0x00000000,
+		    0x00000000
+		},
+
+		Package ()
+		{
+		    0x00000578,
+		    0x000076F2,
+		    0x00000002,
+		    0x00000002,
+		    0x00000001,
+		    0x00000001
+		}
+	})
+
+	Name(_PCT, Package(){
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+		ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+	})
+
+	Method(_PPC, 0){
+		Return(0)
+	}
diff --git a/src/mainboard/amd/dinar/acpi/ide.asl b/src/mainboard/amd/dinar/acpi/ide.asl
new file mode 100644
index 0000000..765a67e
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi/ide.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(IDEC) {
+			Name(_ADR, 0x00140001)
+			#include "ide.asl"
+		}
+	}
+}
+*/
+
+/* Some timing tables */
+Name(UDTT, Package(){ /* Udma timing table */
+	120, 90, 60, 45, 30, 20, 15, 0	/* UDMA modes 0 -> 6 */
+})
+
+Name(MDTT, Package(){ /* MWDma timing table */
+	480, 150, 120, 0	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(POTT, Package(){ /* Pio timing table */
+	600, 390, 270, 180, 120, 0	/* PIO modes 0 -> 4 */
+})
+
+/* Some timing register value tables */
+Name(MDRT, Package(){ /* MWDma timing register table */
+	0x77, 0x21, 0x20, 0xFF	/* Legacy DMA modes 0 -> 2 */
+})
+
+Name(PORT, Package(){
+	0x99, 0x47, 0x34, 0x22, 0x20, 0x99	/* PIO modes 0 -> 4 */
+})
+
+OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */
+	Field(ICRG, AnyAcc, NoLock, Preserve)
+{
+	PPTS, 8,	/* Primary PIO Slave Timing */
+	PPTM, 8,	/* Primary PIO Master Timing */
+	OFFSET(0x04), PMTS, 8,	/* Primary MWDMA Slave Timing */
+	PMTM, 8,	/* Primary MWDMA Master Timing */
+	OFFSET(0x08), PPCR, 8,	/* Primary PIO Control */
+	OFFSET(0x0A), PPMM, 4,	/* Primary PIO master Mode */
+	PPSM, 4,	/* Primary PIO slave Mode */
+	OFFSET(0x14), PDCR, 2,	/* Primary UDMA Control */
+	OFFSET(0x16), PDMM, 4,	/* Primary UltraDMA Mode */
+	PDSM, 4,	/* Primary UltraDMA Mode */
+}
+
+Method(GTTM, 1) /* get total time*/
+{
+	Store(And(Arg0, 0x0F), Local0)	/* Recovery Width */
+	Increment(Local0)
+	Store(ShiftRight(Arg0, 4), Local1)	/* Command Width */
+	Increment(Local1)
+	Return(Multiply(30, Add(Local0, Local1)))
+}
+
+Device(PRID)
+{
+	Name (_ADR, Zero)
+	Method(_GTM, 0)
+	{
+		NAME(OTBF, Buffer(20) { /* out buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(OTBF, 0, PSD0)   /* PIO spd0 */
+		CreateDwordField(OTBF, 4, DSD0)   /* DMA spd0 */
+		CreateDwordField(OTBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(OTBF, 16, BFFG) /* buffer flags */
+
+		/* Just return if the channel is disabled */
+		If(And(PPCR, 0x01)) { /* primary PIO control */
+			Return(OTBF)
+		}
+
+		/* Always tell them independent timing available and IOChannelReady used on both drives */
+		Or(BFFG, 0x1A, BFFG)
+
+		Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming  to PIO spd0 */
+		Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing  to PIO spd1 */
+
+		If(And(PDCR, 0x01)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x01, BFFG)
+			Store(DerefOf(Index(UDTT, PDMM)), DSD0)
+		}
+		Else {
+			Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing,  DmaSpd0 */
+		}
+
+		If(And(PDCR, 0x02)) {	/* It's under UDMA mode */
+			Or(BFFG, 0x04, BFFG)
+			Store(DerefOf(Index(UDTT, PDSM)), DSD1)
+		}
+		Else {
+			Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing,  DmaSpd0 */
+		}
+
+		Return(OTBF) /* out buffer */
+	}				/* End Method(_GTM) */
+
+	Method(_STM, 3, NotSerialized)
+	{
+		NAME(INBF, Buffer(20) { /* in buffer */
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF,
+			0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00
+		})
+
+		CreateDwordField(INBF, 0, PSD0)    /* PIO spd0 */
+		CreateDwordField(INBF, 4, DSD0)   /* PIO spd0 */
+		CreateDwordField(INBF, 8, PSD1)   /* PIO spd1 */
+		CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */
+		CreateDwordField(INBF, 16, BFFG) /*buffer flag */
+
+		Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0)
+		Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */
+		Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1)
+		Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */
+
+		Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */
+		Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */
+
+		If(And(BFFG, 0x01)) {	/* Drive 0 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDMM,)
+			Or(PDCR, 0x01, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD0, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTM)
+			}
+		}
+
+		If(And(BFFG, 0x04)) {	/* Drive 1 is under UDMA mode */
+			Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0)
+			Divide(Local0, 7, PDSM,)
+			Or(PDCR, 0x02, PDCR)
+		}
+		Else {
+			If(LNotEqual(DSD1, 0xFFFFFFFF)) {
+				Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0)
+				Store(DerefOf(Index(MDRT, Local0)), PMTS)
+			}
+		}
+		/* Return(INBF) */
+	}		/*End Method(_STM) */
+	Device(MST)
+	{
+		Name(_ADR, 0)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xA0, CMDA)
+			Store(0xA0, CMDB)
+			Store(0xA0, CMDC)
+
+			Or(PPMM, 0x08, POMD)
+
+			If(And(PDCR, 0x01)) {
+				Or(PDMM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTM),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}		/* End Device(MST) */
+
+	Device(SLAV)
+	{
+		Name(_ADR, 1)
+		Method(_GTF) {
+			Name(CMBF, Buffer(21) {
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,
+				0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5
+			})
+			CreateByteField(CMBF, 1, POMD)
+			CreateByteField(CMBF, 8, DMMD)
+			CreateByteField(CMBF, 5, CMDA)
+			CreateByteField(CMBF, 12, CMDB)
+			CreateByteField(CMBF, 19, CMDC)
+
+			Store(0xB0, CMDA)
+			Store(0xB0, CMDB)
+			Store(0xB0, CMDC)
+
+			Or(PPSM, 0x08, POMD)
+
+			If(And(PDCR, 0x02)) {
+				Or(PDSM, 0x40, DMMD)
+			}
+			Else {
+				Store(Match
+				      (MDTT, MLE, GTTM(PMTS),
+				       MTR, 0, 0), Local0)
+				If(LLess(Local0, 3)) {
+					Or(0x20, Local0, DMMD)
+				}
+			}
+			Return(CMBF)
+		}
+	}			/* End Device(SLAV) */
+}
diff --git a/src/mainboard/amd/dinar/acpi/routing.asl b/src/mainboard/amd/dinar/acpi/routing.asl
new file mode 100644
index 0000000..c7a9165
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi/routing.asl
@@ -0,0 +1,311 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
+		)
+	{
+		#include "routing.asl"
+	}
+*/
+
+/* Routing is in System Bus scope */
+Scope(\_SB) {
+	Name(PR0, Package(){
+		/* NB devices */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, INTC, 0 },
+		Package(){0x0001FFFF, 1, INTD, 0 },
+		/* Bus 0, Dev 2 - */
+		Package(){0x0002FFFF, 0, INTC, 0 },
+		Package(){0x0002FFFF, 1, INTD, 0 },
+		Package(){0x0002FFFF, 2, INTA, 0 },
+		Package(){0x0002FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 3 - */
+		Package(){0x0003FFFF, 0, INTD, 0 },
+		Package(){0x0003FFFF, 1, INTA, 0 },
+		Package(){0x0003FFFF, 2, INTB, 0 },
+		Package(){0x0003FFFF, 3, INTC, 0 },
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, INTA, 0 },
+		Package(){0x0004FFFF, 1, INTB, 0 },
+		Package(){0x0004FFFF, 2, INTC, 0 },
+		Package(){0x0004FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, INTB, 0 },
+		Package(){0x0005FFFF, 1, INTC, 0 },
+		Package(){0x0005FFFF, 2, INTD, 0 },
+		Package(){0x0005FFFF, 3, INTA, 0 },
+		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+		Package(){0x0006FFFF, 0, INTC, 0 },
+		Package(){0x0006FFFF, 1, INTD, 0 },
+		Package(){0x0006FFFF, 2, INTA, 0 },
+		Package(){0x0006FFFF, 3, INTB, 0 },
+		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0007FFFF, 0, INTD, 0 },
+		Package(){0x0007FFFF, 1, INTA, 0 },
+		Package(){0x0007FFFF, 2, INTB, 0 },
+		Package(){0x0007FFFF, 3, INTC, 0 },
+
+		/* SB devices */
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+		Package(){0x0014FFFF, 0, INTA, 0 },
+		Package(){0x0014FFFF, 1, INTB, 0 },
+		Package(){0x0014FFFF, 2, INTC, 0 },
+		Package(){0x0014FFFF, 3, INTD, 0 },
+		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI */
+		Package(){0x0012FFFF, 0, INTC, 0 },
+		Package(){0x0012FFFF, 1, INTB, 0 },
+		Package(){0x0013FFFF, 0, INTC, 0 },
+		Package(){0x0013FFFF, 1, INTB, 0 },
+		Package(){0x0016FFFF, 0, INTC, 0 },
+		Package(){0x0016FFFF, 1, INTB, 0 },
+		Package(){0x0010FFFF, 0, INTC, 0 },
+		Package(){0x0010FFFF, 1, INTB, 0 },
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		Package(){0x0011FFFF, 0, INTD, 0 },
+		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0015FFFF, 0, INTA, 0 },
+		Package(){0x0015FFFF, 1, INTB, 0 },
+		Package(){0x0015FFFF, 2, INTC, 0 },
+		Package(){0x0015FFFF, 3, INTD, 0 },
+	})
+
+	Name(APR0, Package(){
+		/* NB devices in APIC mode */
+		/* Bus 0, Dev 0 - RS780 Host Controller */
+		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
+		Package(){0x0001FFFF, 0, 0, 18 },
+		Package(){0x0001FFFF, 1, 0, 19 },
+		/* Bus 0, Dev 2 */
+		Package(){0x0002FFFF, 0, 0, 18 },
+		Package(){0x0002FFFF, 1, 0, 19 },
+		Package(){0x0002FFFF, 2, 0, 16 },
+		Package(){0x0002FFFF, 3, 0, 17 },
+		/* Bus 0, Dev 3 */
+		Package(){0x0003FFFF, 0, 0, 19 },
+		Package(){0x0003FFFF, 1, 0, 16 },
+		Package(){0x0003FFFF, 2, 0, 17 },
+		Package(){0x0003FFFF, 3, 0, 18 },
+		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
+		Package(){0x0004FFFF, 0, 0, 16 },
+		Package(){0x0004FFFF, 1, 0, 17 },
+		Package(){0x0004FFFF, 2, 0, 18 },
+		Package(){0x0004FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+		Package(){0x0005FFFF, 0, 0, 17 },
+		Package(){0x0005FFFF, 1, 0, 18 },
+		Package(){0x0005FFFF, 2, 0, 19 },
+		Package(){0x0005FFFF, 3, 0, 16 },
+		/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+		Package(){0x0006FFFF, 0, 0, 18 },
+		Package(){0x0006FFFF, 1, 0, 19 },
+		Package(){0x0006FFFF, 2, 0, 16 },
+		Package(){0x0006FFFF, 3, 0, 17 },
+		/* Bus 0, Dev 7 - PCIe Bridge for network card */
+		Package(){0x0007FFFF, 0, 0, 19 },
+		Package(){0x0007FFFF, 1, 0, 16 },
+		Package(){0x0007FFFF, 2, 0, 17 },
+		Package(){0x0007FFFF, 3, 0, 18 },
+
+		/* SB devices in APIC mode */
+		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+		Package(){0x0014FFFF, 0, 0, 16 },
+		Package(){0x0014FFFF, 1, 0, 17 },
+		Package(){0x0014FFFF, 2, 0, 18 },
+		Package(){0x0014FFFF, 3, 0, 19 },
+		/* Bus 0, Dev 18,19,22 - USB: OHCI,EHCI*/
+		Package(){0x0012FFFF, 0, 0, 18 },
+		Package(){0x0012FFFF, 1, 0, 17 },
+		Package(){0x0013FFFF, 0, 0, 18 },
+		Package(){0x0013FFFF, 1, 0, 17 },
+		Package(){0x0016FFFF, 0, 0, 18 },
+		Package(){0x0016FFFF, 1, 0, 17 },
+		Package(){0x0010FFFF, 0, 0, 18 },
+		Package(){0x0010FFFF, 1, 0, 17 },
+		/* Bus 0, Dev 17 - SATA controller #2 */
+		Package(){0x0011FFFF, 0, 0, 19 },
+		/* Bus 0, Dev 21 - PCIe Bridge for x1 PCIe Slot */
+		Package(){0x0015FFFF, 0, 0, 16 },
+		Package(){0x0015FFFF, 1, 0, 17 },
+		Package(){0x0015FFFF, 2, 0, 18 },
+		Package(){0x0015FFFF, 3, 0, 19 },
+	})
+
+	Name(PS2, Package(){
+		/* For Device(PBR2) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS2, Package(){
+		/* For Device(PBR2) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS3, Package(){
+		/* For Device(PBR3) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS3, Package(){
+		/* For Device(PBR3) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PS4, Package(){
+		/* For Device(PBR4) PIC mode*/
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APS4, Package(){
+		/* For Device(PBR4) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PS5, Package(){
+		/* For Device(PBR5) PIC mode*/
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APS5, Package(){
+		/* For Device(PBR5) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PS6, Package(){
+		/* For Device(PBR6) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APS6, Package(){
+		/* For Device(PBR6) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PS7, Package(){
+		/* For Device(PBR7) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APS7, Package(){
+		/* For Device(PBR7) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+
+	Name(PE0, Package(){
+		/* For Device(PE20) PIC mode*/
+		Package(){0x0000FFFF, 0, INTA, 0 },
+		Package(){0x0000FFFF, 1, INTB, 0 },
+		Package(){0x0000FFFF, 2, INTC, 0 },
+		Package(){0x0000FFFF, 3, INTD, 0 },
+	})
+
+	Name(APE0, Package(){
+		/* For Device(PE20) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 16 },
+		Package(){0x0000FFFF, 1, 0, 17 },
+		Package(){0x0000FFFF, 2, 0, 18 },
+		Package(){0x0000FFFF, 3, 0, 19 },
+	})
+
+	Name(PE1, Package(){
+		/* For Device(PE21) PIC mode*/
+		Package(){0x0000FFFF, 0, INTB, 0 },
+		Package(){0x0000FFFF, 1, INTC, 0 },
+		Package(){0x0000FFFF, 2, INTD, 0 },
+		Package(){0x0000FFFF, 3, INTA, 0 },
+	})
+
+	Name(APE1, Package(){
+		/* For Device(PE21) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 17 },
+		Package(){0x0000FFFF, 1, 0, 18 },
+		Package(){0x0000FFFF, 2, 0, 19 },
+		Package(){0x0000FFFF, 3, 0, 16 },
+	})
+
+	Name(PE2, Package(){
+		/* For Device(PE22) PIC mode*/
+		Package(){0x0000FFFF, 0, INTC, 0 },
+		Package(){0x0000FFFF, 1, INTD, 0 },
+		Package(){0x0000FFFF, 2, INTA, 0 },
+		Package(){0x0000FFFF, 3, INTB, 0 },
+	})
+
+	Name(APE2, Package(){
+		/* For Device(PE22) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 18 },
+		Package(){0x0000FFFF, 1, 0, 19 },
+		Package(){0x0000FFFF, 2, 0, 16 },
+		Package(){0x0000FFFF, 3, 0, 17 },
+	})
+
+	Name(PE3, Package(){
+		/* For Device(PE23) PIC mode*/
+		Package(){0x0000FFFF, 0, INTD, 0 },
+		Package(){0x0000FFFF, 1, INTA, 0 },
+		Package(){0x0000FFFF, 2, INTB, 0 },
+		Package(){0x0000FFFF, 3, INTC, 0 },
+	})
+
+	Name(APE3, Package(){
+		/* For Device(PE23) APIC mode*/
+		Package(){0x0000FFFF, 0, 0, 19 },
+		Package(){0x0000FFFF, 1, 0, 16 },
+		Package(){0x0000FFFF, 2, 0, 17 },
+		Package(){0x0000FFFF, 3, 0, 18 },
+	})
+}
diff --git a/src/mainboard/amd/dinar/acpi/sata.asl b/src/mainboard/amd/dinar/acpi/sata.asl
new file mode 100644
index 0000000..32b9cd9
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi/sata.asl
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* simple name description */
+
+/*
+Scope (_SB) {
+	Device(PCI0) {
+		Device(SATA) {
+			Name(_ADR, 0x00110000)
+			#include "sata.asl"
+		}
+	}
+}
+*/
+
+Name(STTM, Buffer(20) {
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
+	0x1f, 0x00, 0x00, 0x00
+})
+
+/* Start by clearing the PhyRdyChg bits */
+Method(_INI) {
+	\_GPE._L1F()
+}
+
+Device(PMRY)
+{
+	Name(_ADR, 0)
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(PMST) {
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P0IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return  (0x00) /* sata is missing */
+			}
+		}
+	}/* end of PMST */
+
+	Device(PSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P1IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	}	/* end of PSLA */
+}   /* end of PMRY */
+
+
+Device(SEDY)
+{
+	Name(_ADR, 1)		/* IDE Scondary Channel */
+	Method(_GTM, 0x0, NotSerialized) {
+		Return(STTM)
+	}
+	Method(_STM, 0x3, NotSerialized) {}
+
+	Device(SMST)
+	{
+		Name(_ADR, 0)
+		Method(_STA,0) {
+			if (LGreater(P2IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SMST */
+
+	Device(SSLA)
+	{
+		Name(_ADR, 1)
+		Method(_STA,0) {
+			if (LGreater(P3IS,0)) {
+				return (0x0F) /* sata is visible */
+			}
+			else {
+				return (0x00) /* sata is missing */
+			}
+		}
+	} /* end of SSLA */
+}   /* end of SEDY */
+
+/* SATA Hot Plug Support */
+Scope(\_GPE) {
+	Method(_L1F,0x0,NotSerialized) {
+		if (\_SB.P0PR) {
+			if (LGreater(\_SB.P0IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P0PR)
+		}
+
+		if (\_SB.P1PR) {
+			if (LGreater(\_SB.P1IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P1PR)
+		}
+
+		if (\_SB.P2PR) {
+			if (LGreater(\_SB.P2IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P2PR)
+		}
+
+		if (\_SB.P3PR) {
+			if (LGreater(\_SB.P3IS,0)) {
+				sleep(32)
+			}
+			Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
+			store(one, \_SB.P3PR)
+		}
+	}
+}
diff --git a/src/mainboard/amd/dinar/acpi/usb.asl b/src/mainboard/amd/dinar/acpi/usb.asl
new file mode 100644
index 0000000..8a87ace
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi/usb.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c
new file mode 100644
index 0000000..ee00e81
--- /dev/null
+++ b/src/mainboard/amd/dinar/acpi_tables.c
@@ -0,0 +1,320 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+
+#include "agesawrapper.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(u32 start, u32 end)
+{
+
+	u32 i;
+	print_debug("dump_mem:");
+	for (i = start; i < end; i++) {
+		if ((i & 0xf) == 0) {
+			printk(BIOS_DEBUG, "\n%08x:", i);
+		}
+		printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
+	}
+	print_debug("\n");
+}
+#endif
+
+extern const unsigned char AmlCode[];
+
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Just a dummy */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	device_t dev;
+	u32 dword;
+	u32 gsi_base = 0;
+	u32 apicid_sb700;
+	u32 apicid_rd890;
+
+	/*
+	 * AGESA v5 Apply apic enumeration rules
+	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+	 * put the local-APICs at m..z
+	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
+	 * put the IO-APICs at (n + 1)..z
+	 */
+#if CONFIG_MAX_CPUS >= 16
+	apicid_sb700 = 0x0;
+#else
+	apicid_sb700 = CONFIG_MAX_CPUS + 1
+#endif
+		apicid_rd890 = apicid_sb700 + 1;
+
+	/* create all subtables for processors */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write sb700 IOAPIC, only one */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+			apicid_sb700,
+			IO_APIC_ADDR,
+			0
+			);
+
+	/* IOAPIC on rs5690 */
+	gsi_base += IO_APIC_INTERRUPTS;  /* sb700 has 24 IOAPIC entries. */
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (dev) {
+		pci_write_config32(dev, 0xF8, 0x1);
+		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				apicid_rd890,
+				dword,
+				gsi_base
+				);
+	}
+
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
+			0, //BUS
+			0, //SOURCE
+			2, //gsirq
+			0  //flags
+			);
+
+	/* 0: mean bus 0--->ISA */
+	/* 0: PIC 0 */
+	/* 2: APIC 2 */
+	/* 5 mean: 0101 --> Edige-triggered, Active high */
+
+	/* create all subtables for processors */
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1);
+	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1);
+	/* 1: LINT1 connect to NMI */
+
+	return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	//acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_srat_t *srat;
+	acpi_slit_t *slit;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_header_t *dsdt;
+	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
+
+	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
+
+	/* Align ACPI tables to 16 bytes */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* clear all table memory */
+	memset((void *)start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, NULL);
+	acpi_write_rsdt(rsdt);
+
+	/* FACS */
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	/* DSDT */
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *)current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n", dsdt, dsdt->length);
+	/* FADT */
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * HPET at %lx\n", current);
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+#endif
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * MADT at %lx\n",current);
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdp, madt);
+
+	/* SRAT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
+	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
+	if (srat != NULL) {
+		memcpy((void *)current, srat, srat->header.length);
+		srat = (acpi_srat_t *) current;
+		//acpi_create_srat(srat);
+		current += srat->header.length;
+		acpi_add_table(rsdp, srat);
+	}
+
+	/* SLIT */
+	current   = ( current + 0x07) & -0x08;
+	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
+	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
+	if (slit != NULL) {
+		memcpy((void *)current, slit, slit->header.length);
+		slit = (acpi_slit_t *) current;
+		//acpi_create_slit(slit);
+		current += slit->header.length;
+		acpi_add_table(rsdp, slit);
+	}
+
+	/* SSDT */
+	current	 = (current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
+		ssdt = (acpi_header_t *) current;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	} else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
+	}
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
+		ssdt = (acpi_header_t *) current;
+		current += ssdt->length;
+	} else {
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
+	}
+	acpi_add_table(rsdp,ssdt);
+#endif
+
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
+
+#if DUMP_ACPI_TABLES == 1
+	printk(BIOS_DEBUG, "rsdp\n");
+	dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+	printk(BIOS_DEBUG, "rsdt\n");
+	dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+	printk(BIOS_DEBUG, "madt\n");
+	dump_mem(madt, ((void *)madt) + madt->header.length);
+
+	printk(BIOS_DEBUG, "srat\n");
+	dump_mem(srat, ((void *)srat) + srat->header.length);
+
+	printk(BIOS_DEBUG, "slit\n");
+	dump_mem(slit, ((void *)slit) + slit->header.length);
+
+	printk(BIOS_DEBUG, "ssdt\n");
+	dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+	printk(BIOS_DEBUG, "fadt\n");
+	dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c
new file mode 100644
index 0000000..afbf108
--- /dev/null
+++ b/src/mainboard/amd/dinar/agesawrapper.c
@@ -0,0 +1,628 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include "agesawrapper.h"
+#include "BiosCallOuts.h"
+#include "cpuRegisters.h"
+#include "cpuCacheInit.h"
+#include "cpuApicUtilities.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "Dispatcher.h"
+#include "cpuCacheInit.h"
+#include "amdlib.h"
+#include "PlatformGnbPcieComplex.h"
+#include "heapManager.h"
+#include "Filecode.h"
+#include <arch/io.h>
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* ACPI table pointers returned by AmdInitLate */
+VOID *DmiTable    = NULL;
+VOID *AcpiPstate  = NULL;
+VOID *AcpiSrat    = NULL;
+VOID *AcpiSlit    = NULL;
+
+VOID *AcpiWheaMce = NULL;
+VOID *AcpiWheaCmc = NULL;
+VOID *AcpiAlib    = NULL;
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/
+/*
+BusRange: bus range identifier. Read-write. Reset: X. This specifies the number of buses in the
+MMIO configuration space range. The size of the MMIO configuration space range varies with this
+field as follows: the size is 1 Mbyte times the number of buses. This field is encoded as follows:
+Bits    Buses  Bits    Buses
+0h      1       5h      32
+1h      2       6h      64
+2h      4       7h      128
+3h      8       8h      256
+4h      16      Fh-9h   Reserved
+*/
+UINT8
+GetEndBusNum (
+		VOID
+	     )
+{
+	UINT64  BusNum;
+	UINT8   Index;
+	for (Index = 1; Index <= 8; Index ++ ) {
+		BusNum = CONFIG_MMCONF_BUS_NUMBER >> Index;
+		if (BusNum == 1 ) {
+			break;
+		}
+	}
+	return Index;
+}
+
+UINT32
+agesawrapper_amdinitcpuio (
+		VOID
+		)
+{
+	AGESA_STATUS                  Status;
+	UINT64                        MsrReg;
+	UINT32                        PciData;
+	PCI_ADDR                      PciAddress;
+	AMD_CONFIG_PARAMS             StdHeader;
+	UINT32                        TopMem;
+	UINT32                        NodeCnt;
+	UINT32                        Node;
+	UINT32                        SbLink;
+	UINT32                        Index;
+
+	/* get the number of coherent nodes in the system */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x60);
+	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	NodeCnt = ((PciData >> 4) & 7) + 1; //NodeCnt[6:4]
+	/* Find out the Link ID of Node0 that connects to the
+	 * Southbridge (system IO hub). e.g. family10 MCM Processor,
+	 * SbLink is Processor0 Link2, internal Node0 Link3
+	 */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0, 0x64);
+	LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	SbLink = (PciData >> 8) & 3; //assume ganged
+	/* Enable MMIO on AMD CPU Address Map Controller for all nodes */
+	for (Node = 0; Node < NodeCnt; Node ++) {
+		/* clear all MMIO Mapped Base/Limit Registers */
+		for (Index = 0; Index < 8; Index ++) {
+			PciData = 0x00000000;
+			PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x80 + Index * 8);
+			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+			PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0x84 + Index * 8);
+			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		}
+		/* clear all IO Space Base/Limit Registers */
+		for (Index = 0; Index < 4; Index ++) {
+			PciData = 0x00000000;
+			PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC0 + Index * 8);
+			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+			PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18 + Node, 1, 0xC4 + Index * 8);
+			LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		}
+
+		/* Enable MMIO on AMD CPU Address Map Controller */
+
+		/* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x80);
+		PciData = (0xA0000 >> 8) |3;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x84);
+		PciData = 0xB0000 >> 8;
+		PciData &= (~0xFF);
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+		/* Set UMA MMIO. */
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x88);
+		LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+		TopMem = (UINT32)MsrReg;
+		MsrReg = (MsrReg >> 8) | 3;
+		PciData = (UINT32)MsrReg;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x8c);
+		if (TopMem <= CONFIG_MMCONF_BASE_ADDRESS) {
+			PciData = (CONFIG_MMCONF_BASE_ADDRESS  - 1) >> 8;
+		}
+		else {
+			PciData = (0x100000000ull  - 1) >> 8;
+		}
+		PciData &= (~0xFF);
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+		/* Set PCIE MMIO. */
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x90);
+		PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x94);
+		PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) & (~0xFF);
+		PciData &= (~0xFF);
+		PciData |= MMIO_NP_BIT;
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+		/* Set XAPIC MMIO. 24K */
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x98);
+		PciData = (0xFEC00000 >> 8) |3;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0x9c);
+		PciData = ((0xFEC00000 + 6 * 4096 - 1) >> 8);
+		PciData &= (~0xFF);
+		PciData |= MMIO_NP_BIT;
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+		/* Set Local APIC MMIO. 4K*4= 16K, Llano CPU are 4 cores */
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA0);
+		PciData = (0xFEE00000 >> 8) |3;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xA8);
+		PciData = (0xFEE00000 + 4 * 4096 - 1) >> 8;
+		PciData &= (~0xFF);
+		PciData |= MMIO_NP_BIT;
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+		/* Set PCIO: 0x0 - 0xFFF000  and enabled VGA IO*/
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC0);
+		PciData = 0x13;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+		PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18 + Node, 1, 0xC4);
+		PciData = 0x00FFF000;
+		PciData &= (~0x7F);
+		PciData |= SbLink << 4;
+		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+	}
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitmmio (
+		VOID
+		)
+{
+	AGESA_STATUS                  Status;
+	UINT64                        MsrReg;
+	UINT32                        PciData;
+	PCI_ADDR                      PciAddress;
+	AMD_CONFIG_PARAMS             StdHeader;
+
+	/*
+	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
+	   Address MSR register.
+	   */
+	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (GetEndBusNum () << 2) | 1;
+	LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
+
+	/*
+	   Set the NB_CFG MSR register. Enable CF8 extended configuration cycles.
+	   */
+	LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader);
+	MsrReg = MsrReg | BIT46;
+	LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader);
+
+	/* Set PCIE MMIO. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x90);
+
+	PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) |3;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x94);
+	PciData = (( CONFIG_MMCONF_BASE_ADDRESS + CONFIG_MMCONF_BUS_NUMBER * 4096 *256 - 1) >> 8) | MMIO_NP_BIT;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+
+	/* Enable memory access */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+	PciData |= BIT1;
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0x04);
+	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
+
+	/* Set ROM cache onto WP to decrease post time */
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
+	LibAmdMsrWrite (0x20E, &MsrReg, &StdHeader);
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
+	LibAmdMsrWrite (0x20F, &MsrReg, &StdHeader);
+
+	Status = AGESA_SUCCESS;
+	return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdinitreset (
+		VOID
+		)
+{
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_RESET_PARAMS AmdResetParams;
+
+	LibAmdMemFill (&AmdParamStruct,
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
+
+
+	LibAmdMemFill (&AmdResetParams,
+			0,
+			sizeof (AMD_RESET_PARAMS),
+			&(AmdResetParams.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
+	AmdParamStruct.AllocationMethod = ByHost;
+	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
+	AmdParamStruct.NewStructPtr = &AmdResetParams;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = NULL;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	AmdResetParams.HtConfig.Depth = 0;
+#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE)
+	status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr);
+#endif
+
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+	return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitearly (
+		VOID
+		)
+{
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_EARLY_PARAMS     *AmdEarlyParamsPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+
+	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
+	OemCustomizeInitEarly (AmdEarlyParamsPtr);
+
+	status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  OemCustomizeInitEarly
+ *
+ *  Description:
+ *    This is the stub function will call the host environment through the binary block
+ *    interface (call-out port) to provide a user hook opportunity
+ *
+ *  Parameters:
+ *    @param[in]      **PeiServices
+ *    @param[in]      *InitEarly
+ *
+ *    @retval         VOID
+ *
+ **/
+/*---------------------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
+{
+	//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
+}
+
+VOID
+OemCustomizeInitPost (
+		IN  AMD_POST_PARAMS     *InitPost
+		)
+{
+	InitPost->MemConfig.UmaMode = UMA_AUTO;
+	InitPost->MemConfig.BottomIo = 0xE0;
+	InitPost->MemConfig.UmaSize = 0xE0-0xC0;
+}
+
+UINT32
+agesawrapper_amdinitpost (
+		VOID
+		)
+{
+	AGESA_STATUS status;
+	UINT16                  i;
+	UINT32          *HeadPtr;
+	AMD_INTERFACE_PARAMS  AmdParamStruct;
+	BIOS_HEAP_MANAGER    *BiosManagerPtr;
+
+	LibAmdMemFill (&AmdParamStruct,
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
+	AmdParamStruct.AllocationMethod = PreMemHeap;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+
+	/* OEM Should Customize the defaults through this hook */
+	OemCustomizeInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+
+	status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	/* Initialize heap space */
+	BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS;
+
+	HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof (BIOS_HEAP_MANAGER));
+	for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof (BIOS_HEAP_MANAGER)/4)); i++)
+	{
+		*HeadPtr = 0x00000000;
+		HeadPtr++;
+	}
+	BiosManagerPtr->StartOfAllocatedNodes = 0;
+	BiosManagerPtr->StartOfFreedNodes = 0;
+
+	return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitenv (
+		VOID
+		)
+{
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+	PCI_ADDR             PciAddress;
+	UINT32               PciValue;
+
+	LibAmdMemFill (&AmdParamStruct,
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdCreateStruct (&AmdParamStruct);
+	status = AmdInitEnv ((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
+}
+
+VOID *
+agesawrapper_getlateinitptr (
+		int pick
+		)
+{
+	switch (pick) {
+		case PICK_DMI:
+			return DmiTable;
+
+		case PICK_PSTATE:
+			return AcpiPstate;
+
+		case PICK_SRAT:
+			return AcpiSrat;
+
+		case PICK_SLIT:
+			return AcpiSlit;
+		case PICK_WHEA_MCE:
+			return AcpiWheaMce;
+		case PICK_WHEA_CMC:
+			return AcpiWheaCmc;
+		case PICK_ALIB:
+			return AcpiAlib;
+		default:
+			return NULL;
+	}
+}
+
+UINT32
+agesawrapper_amdinitmid (
+		VOID
+		)
+{
+	AGESA_STATUS status;
+	AMD_INTERFACE_PARAMS AmdParamStruct;
+
+	printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
+	/* Enable MMIO on AMD CPU Address Map Controller */
+	agesawrapper_amdinitcpuio ();
+
+	LibAmdMemFill (&AmdParamStruct,
+			0,
+			sizeof (AMD_INTERFACE_PARAMS),
+			&(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+
+	AmdCreateStruct (&AmdParamStruct);
+
+	status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
+	if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();
+	AmdReleaseStruct (&AmdParamStruct);
+
+	return (UINT32)status;
+}
+
+UINT32
+agesawrapper_amdinitlate(VOID)
+{
+	AGESA_STATUS		Status;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	AMD_LATE_PARAMS		*AmdLateParamsPtr;
+
+	LibAmdMemFill(&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
+
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
+	AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate(AmdLateParamsPtr);
+	if (Status != AGESA_SUCCESS) {
+		//agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
+
+	return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdlaterunaptask (
+		UINT32 Data,
+		VOID *ConfigPtr
+		)
+{
+	AGESA_STATUS Status;
+	AMD_LATE_PARAMS AmdLateParams;
+
+	LibAmdMemFill (&AmdLateParams,
+			0,
+			sizeof (AMD_LATE_PARAMS),
+			&(AmdLateParams.StdHeader));
+
+	AmdLateParams.StdHeader.AltImageBasePtr = 0;
+	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdLateParams.StdHeader.Func = 0;
+	AmdLateParams.StdHeader.ImageBasePtr = 0;
+
+	Status = AmdLateRunApTask (&AmdLateParams);
+	if (Status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog();
+		ASSERT(Status == AGESA_SUCCESS);
+	}
+
+	return (UINT32)Status;
+}
+
+UINT32
+agesawrapper_amdreadeventlog (
+		VOID
+		)
+{
+	AGESA_STATUS Status;
+	EVENT_PARAMS AmdEventParams;
+
+	LibAmdMemFill (&AmdEventParams,
+			0,
+			sizeof (EVENT_PARAMS),
+			&(AmdEventParams.StdHeader));
+
+	AmdEventParams.StdHeader.AltImageBasePtr = 0;
+	AmdEventParams.StdHeader.CalloutPtr = NULL;
+	AmdEventParams.StdHeader.Func = 0;
+	AmdEventParams.StdHeader.ImageBasePtr = 0;
+	Status = AmdReadEventLog (&AmdEventParams);
+	while (AmdEventParams.EventClass != 0) {
+		printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo);
+		printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2);
+		printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4);
+		Status = AmdReadEventLog (&AmdEventParams);
+	}
+
+	return (UINT32)Status;
+}
diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h
new file mode 100644
index 0000000..400e0c0
--- /dev/null
+++ b/src/mainboard/amd/dinar/agesawrapper.h
@@ -0,0 +1,329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _AGESAWRAPPER_H_
+#define _AGESAWRAPPER_H_
+
+#include <stdint.h>
+#include "Porting.h"
+#include "AGESA.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/* BITS Define */
+#ifndef BIT0
+#define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+#define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+#define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+#define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+#define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+#define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+#define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+#define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+#define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+#define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+#define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+#define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+#define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+#define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+#define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+#define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+#define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+#define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+#define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+#define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+#define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+#define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+#define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+#define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+#define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+#define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+#define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+#define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+#define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+#define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+#define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+#define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+#define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+#define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+#define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+#define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+#define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+#define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+#define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+#define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+#define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+#define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+#define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+#define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+#define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+#define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+#define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+#define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+#define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+#define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+#define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+#define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+#define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+#define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+#define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+#define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+#define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+#define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+#define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+#define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+#define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+#define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+#define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+#define BIT63       0x8000000000000000ull
+#endif
+/* Define AMD Ontario APPU SSID/SVID */
+#define AMD_APU_SVID    0x1022
+#define AMD_APU_SSID    0x1234
+#define PCIE_BASE_ADDRESS   CONFIG_MMCONF_BASE_ADDRESS
+#define MMIO_NP_BIT         BIT7
+
+/* Hudson-2 ACPI PmIO Space Define */
+#define SB_ACPI_BASE_ADDRESS              0x0400
+#define ACPI_MMIO_BASE  0xFED80000
+#define SB_CFG_BASE     0x000   // DWORD
+#define GPIO_BASE       0x100   // BYTE
+#define SMI_BASE        0x200   // DWORD
+#define PMIO_BASE       0x300   // DWORD
+#define PMIO2_BASE      0x400   // BYTE
+#define BIOS_RAM_BASE   0x500   // BYTE
+#define CMOS_RAM_BASE   0x600   // BYTE
+#define CMOS_BASE       0x700   // BYTE
+#define ASF_BASE        0x900   // DWORD
+#define SMBUS_BASE      0xA00   // DWORD
+#define WATCHDOG_BASE   0xB00   // ??
+#define HPET_BASE       0xC00   // DWORD
+#define IOMUX_BASE      0xD00   // BYTE
+#define MISC_BASE       0xE00
+#define SERIAL_DEBUG_BASE  0x1000
+#define GFX_DAC_BASE       0x1400
+#define CEC_BASE           0x1800
+#define XHCI_BASE          0x1C00
+#define ACPI_SMI_DATA_PORT                0xB1
+#define R_SB_ACPI_PM1_STATUS              0x00
+#define R_SB_ACPI_PM1_ENABLE              0x02
+#define R_SB_ACPI_PM_CONTROL              0x04
+#define R_SB_ACPI_EVENT_STATUS            0x20
+#define R_SB_ACPI_EVENT_ENABLE            0x24
+#define   B_PWR_BTN_STATUS                BIT8
+#define   B_WAKEUP_STATUS                 BIT15
+#define   B_SCI_EN                        BIT0
+#define SB_PM_INDEX_PORT                  0xCD6
+#define SB_PM_DATA_PORT                   0xCD7
+#define SB_PMIOA_REG24          0x24        //  AcpiMmioEn
+#define MmioAddress( BaseAddr, Register ) \
+	( (UINTN)BaseAddr + \
+	  (UINTN)(Register) \
+	)
+#define Mmio32Ptr( BaseAddr, Register ) \
+	( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+#define Mmio32( BaseAddr, Register ) \
+	*Mmio32Ptr( BaseAddr, Register )
+
+enum {
+	PICK_DMI,       /* DMI Interface */
+	PICK_PSTATE,    /* Acpi Pstate SSDT Table */
+	PICK_SRAT,      /* SRAT Table */
+	PICK_SLIT,      /* SLIT Table */
+	PICK_WHEA_MCE,  /* WHEA MCE table */
+	PICK_WHEA_CMC,  /* WHEA CMV table */
+	PICK_ALIB,      /* SACPI SSDT table with ALIB implementation */
+};
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef struct {
+	UINT32 CalloutName;
+	AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
+} BIOS_CALLOUT_STRUCT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+//void brazos_platform_stage(void);
+UINT32 agesawrapper_amdinitreset (void);
+UINT32 agesawrapper_amdinitearly (void);
+UINT32 agesawrapper_amdinitenv (void);
+UINT32 agesawrapper_amdinitlate (void);
+UINT32 agesawrapper_amdinitpost (void);
+UINT32 agesawrapper_amdinitmid (void);
+void sb_After_Pci_Init (void);
+void sb_Mid_Post_Init (void);
+void sb_Late_Post (void);
+UINT32 agesawrapper_amdreadeventlog (void);
+UINT32 agesawrapper_amdinitmmio (void);
+void *agesawrapper_getlateinitptr (int pick);
+
+#endif
diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c
new file mode 100644
index 0000000..fd0464d
--- /dev/null
+++ b/src/mainboard/amd/dinar/buildOpts.c
@@ -0,0 +1,483 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/**
+ * @file
+ *
+ * AMD User options selection for a Sabine/Lynx platform solution system
+ *
+ * This file is placed in the user's platform directory and contains the
+ * build option selections desired for that platform.
+ *
+ * For Information about this file, see @ref platforminstall.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 6049 $   @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $
+ */
+#include  "AGESA.h"
+#include  "CommonReturns.h"
+#include "Filecode.h"
+#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
+
+
+/*  Select the cpu family.  */
+
+
+/*  Select the cpu socket type.  */
+#define INSTALL_G34_SOCKET_SUPPORT  TURE
+#define INSTALL_C32_SOCKET_SUPPORT  FALSE
+#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
+#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
+#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
+#define INSTALL_FS1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FM1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FP1_SOCKET_SUPPORT  FALSE
+#define INSTALL_FT1_SOCKET_SUPPORT  FALSE
+#define INSTALL_AM3_SOCKET_SUPPORT  FALSE
+
+/*
+ * Agesa optional capabilities selection.
+ * Uncomment and mark FALSE those features you wish to include in the build.
+ * Comment out or mark TRUE those features you want to REMOVE from the build.
+ */
+
+/* User makes option selections here
+ * Comment out the items wanted to be included in the build.
+ * Uncomment those items you with to REMOVE from the build.
+ */
+//#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
+//#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
+//#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
+//#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
+//#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
+//#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
+#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
+//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
+//#define BLDOPT_REMOVE_DDR3_SUPPORT             TRUE
+//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
+//#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
+//#define BLDOPT_REMOVE_SRAT                     TRUE
+//#define BLDOPT_REMOVE_SLIT                     TRUE
+#define BLDOPT_REMOVE_WHEA                     TRUE
+//#define BLDOPT_REMOVE_DMI                      TRUE
+#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
+//#define BLDOPT_REMOVE_FAMILY_15_SUPPORT          TRUE
+/* Build configuration values here.
+*/
+#define BLDCFG_VRM_CURRENT_LIMIT                 120000
+#define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
+#define BLDCFG_PLAT_NUM_IO_APICS                 2
+#define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
+#define BLDCFG_MEM_INIT_PSTATE                   0
+#define BLDCFG_AMD_PSTATE_CAP_VALUE              0
+
+#define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
+
+#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1600_FREQUENCY
+#define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
+#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
+#define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
+#define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
+#define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
+#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
+#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    TRUE
+#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
+#define BLDCFG_MEMORY_POWER_DOWN                  TRUE
+#define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT  //FALSE
+#define BLDCFG_ONLINE_SPARE                       TRUE
+#define BLDCFG_MEMORY_PARITY_ENABLE               TRUE
+#define BLDCFG_BANK_SWIZZLE                       TRUE
+#define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
+#define BLDCFG_DQS_TRAINING_CONTROL               TRUE
+#define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
+#define BLDCFG_USE_BURST_MODE                     FALSE
+#define BLDCFG_MEMORY_ALL_CLOCKS_ON               TRUE
+#define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
+#define BLDCFG_ECC_REDIRECTION                    TRUE
+#define BLDCFG_SCRUB_IC_RATE                      0
+#define BLDCFG_ECC_SYNC_FLOOD                     TRUE
+#define BLDCFG_ECC_SYMBOL_SIZE                    0
+#define BLDCFG_1GB_ALIGN                          FALSE
+#define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
+#define BLDCFG_PLATFORM_C1E_OPDATA                0x2000
+//#define BLDCFG_USE_ATM_MODE                       TRUE
+
+#define BLDCFG_PLATFORM_CSTATE_MODE               CStateModeC6
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS    0xCB0
+#define BLDCFG_PLATFORM_POWER_POLICY_MODE	  Performance  //BatteryLife
+//#define BLDCFG_PLATFORM_CSTATE_MODE                  CStateModeMsgBasedC1e
+//#define BLDCFG_PLATFORM_CSTATE_OPDATA                0x2000
+
+//#define IDSOPT_IDS_ENABLED                        TRUE
+#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
+#define BLDOPT_REMOVE_LOW_PWR_PSTATE_FOR_PROCHOT	TRUE
+#define BLDCFG_PSTATE_HPC_MODE                    FALSE
+
+#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
+/*
+ * Agesa entry points used in this implementation.
+ */
+/*  Process the options...
+ * This file include MUST occur AFTER the user option selection settings
+ */
+#define AGESA_ENTRY_INIT_RESET                    TRUE//FALSE
+#define AGESA_ENTRY_INIT_RECOVERY                 FALSE
+#define AGESA_ENTRY_INIT_EARLY                    TRUE
+#define AGESA_ENTRY_INIT_POST                     TRUE
+#define AGESA_ENTRY_INIT_ENV                      TRUE
+#define AGESA_ENTRY_INIT_MID                      TRUE
+#define AGESA_ENTRY_INIT_LATE                     TRUE
+#define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+#define AGESA_ENTRY_INIT_RESUME                   TRUE
+#define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+#define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+#define AGESA_ENTRY_LATE_RUN_AP_TASK              TRUE
+
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+// This is the delivery package title, "MarG34PI"
+// This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+// This is the release version number of the AGESA component
+// This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '0', '.', '0', '.', '9', '.', '0', ' ', ' ', ' ', ' '}
+
+// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
+#define INSTALL_G34_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_10_SUPPORT            TRUE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+#undef INSTALL_FAMILY_10_SUPPORT
+#define INSTALL_FAMILY_10_SUPPORT     FALSE
+#endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+#undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
+#endif
+#endif
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+/*  Process the options...
+ * This file include MUST occur
+ AFTER the user option selection settings
+ */
+CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
+{
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+	0, 0,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF
+};
+
+#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList
+
+// And another platform specific one ...
+//CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[2] =
+//{
+//  HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+//  HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
+//  HT_LIST_TERMINAL
+//};
+
+CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] =
+{
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+	HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK,
+	HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
+	HT_LIST_TERMINAL
+};
+
+#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
+
+// A performance-per-watt optimization.
+CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF,
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF,
+	HT_LIST_TERMINAL,
+};
+
+// uncomment the line below to make Perf-per-watt enabled by default.
+#define BLDCFG_LINK_SKIP_REGANG_LIST &PerfPerWatt
+
+
+CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] =
+{
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M,
+	HT_LIST_TERMINAL
+};
+
+#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList
+
+CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] =
+{
+	// Source Socket, Link (4-7 are sublink 1), Target Socket
+	{0, 0, 1},
+	{0, 1, 1},
+	{0, 3, 1},
+	{0, 4, 1},
+	{0, 5, 1},
+	{0, 7, 1},
+};
+
+#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &DinarPhysicalSocketMap
+
+/*
+ *  PCI Bus numbers for Drachma/Peso board
+ */
+CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] =
+{
+	// Socket, Link, SecBus, SubBus
+	0, 2, 0x00, 0xBF,		// RD890 of Dinar
+	1, 0, 0xC0, 0xFF,		// HTX
+	HT_LIST_TERMINAL
+};
+
+#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers
+
+CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] =
+{
+	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone},
+	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3},
+	{ HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6},
+	0xFF
+};
+
+#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList
+/*
+   CONST SKIP_REGANG ROMDATA DinarSkipRegangMap[] =
+   {
+// {socketA, linkA, socketB, linkB}
+{0, 0, 1, 1},
+};
+
+#define BLDCFG_LINK_SKIP_REGANG_LIST &DinarSkipRegangMap
+*/
+
+/*
+ *  Device Capabilities Override for disabling ID Clumping
+ */
+CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] =
+{
+	HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
+	0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0},
+	HT_LIST_TERMINAL
+};
+
+#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap
+
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+#include "PlatformInstall.h"
+
+/*----------------------------------------------------------------------------------------
+ *                        CUSTOMER OVERIDES MEMORY TABLE
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+ *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
+ *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
+ *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
+ *  use its default conservative settings.
+ */
+CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
+	//
+	// The following macros are supported (use comma to separate macros):
+	//
+	// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
+	//      The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
+	//      AGESA will base on this value to disable unused MemClk to save power.
+	//      Example:
+	//      BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
+	//           Bit AM3/S1g3 pin name
+	//           0   M[B,A]_CLK_H/L[0]
+	//           1   M[B,A]_CLK_H/L[1]
+	//           2   M[B,A]_CLK_H/L[2]
+	//           3   M[B,A]_CLK_H/L[3]
+	//           4   M[B,A]_CLK_H/L[4]
+	//           5   M[B,A]_CLK_H/L[5]
+	//           6   M[B,A]_CLK_H/L[6]
+	//           7   M[B,A]_CLK_H/L[7]
+	//      And platform has the following routing:
+	//           CS0   M[B,A]_CLK_H/L[4]
+	//           CS1   M[B,A]_CLK_H/L[2]
+	//           CS2   M[B,A]_CLK_H/L[3]
+	//           CS3   M[B,A]_CLK_H/L[5]
+	//      Then platform can specify the following macro:
+	//      MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
+	//
+	// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
+	//      The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
+	//      AGESA will base on this value to tristate unused CKE to save power.
+	//
+	// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
+	//      The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
+	//      AGESA will base on this value to tristate unused ODT pins to save power.
+	//
+	// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
+	//      The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
+	//      AGESA will base on this value to tristate unused Chip select to save power.
+	//
+	// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
+	//      Specifies the number of DIMM slots per channel.
+	//
+	// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
+	//      Specifies the number of channels per socket.
+	//
+
+	//      Dinar has the following routing:
+	//           CS0   M[B,A]_CLK_H/L[0]
+	//           CS1   M[B,A]_CLK_H/L[2]
+	//           CS2   M[B,A]_CLK_H/L[1]
+	//           CS3   M[B,A]_CLK_H/L[3]
+	MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x01, 0x04, 0x02, 0x08, 0x00, 0x00),
+	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
+	PSO_END
+};
+
+/*
+ * These tables are optional and may be used to adjust memory timing settings
+ */
+#include "mm.h"
+#include "mn.h"
+
+//HY Customer table
+UINT8 AGESA_MEM_TABLE_HY[][sizeof(MEM_TABLE_ALIAS)] =
+{
+	// Hardcoded Memory Training Values
+
+	// The following macro should be used to override training values for your platform
+	//
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
+	//
+	//   NOTE:
+	//   The following training hardcode values are example values that were taken from a tilapia motherboard
+	//   with a particular DIMM configuration.  To harcode your own values, uncomment the appropriate line in
+	//   the table and replace the byte lane values with your own.
+	//
+	//                                                                               ------------------ BYTE LANES ----------------------
+	//                                                                                BL0   BL1   BL2   BL3   BL4   BL5   BL6   Bl7   ECC
+	// Write Data Timing
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
+	// DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
+
+	// DQS Receiver Enable
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
+	// DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
+
+	// Write DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
+
+	// Read DQS Delays
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
+	// DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
+	//--------------------------------------------------------------------------------------------------------------------------------------------------
+	// TABLE END
+	NBACCESS (MTEnd, 0,  0, 0, 0, 0),      // End of Table
+};
+UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]);
+/* ***************************************************************************
+ *   Optional User code to be included into the AGESA build
+ *    These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+//  IN        UINTN                 FcnData,
+//  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+//  )
+//{
+//  /* platform code to read an SPD...  */
+//  return Status;
+//}
+
+/* ***************************************************************************
+ *   Optional User code to be included into the AGESA build
+ *    These may be 32-bit call-out routines...
+ */
+//AGESA_STATUS
+//AgesaReadSpd (
+//  IN        UINTN                 FcnData,
+//  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+//  )
+//{
+//  /* platform code to read an SPD...  */
+//  return Status;
+//}
+
+
diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h
new file mode 100644
index 0000000..42630fa
--- /dev/null
+++ b/src/mainboard/amd/dinar/chip.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {};
diff --git a/src/mainboard/amd/dinar/cmos.layout b/src/mainboard/amd/dinar/cmos.layout
new file mode 100644
index 0000000..5178430
--- /dev/null
+++ b/src/mainboard/amd/dinar/cmos.layout
@@ -0,0 +1,118 @@
+#*****************************************************************************
+# 
+#  This file is part of the coreboot project.
+# 
+#  Copyright (C) 2012 Advanced Micro Devices, Inc.
+# 
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; version 2 of the License.
+# 
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+# 
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#*****************************************************************************
+
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+#96         288       r       0        temporary_filler
+0          384       r       0        reserved_memory
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+386          1       e       1        ECC_memory
+388          4       r       0        reboot_bits
+392          3       e       5        baud_rate
+395          1       e       1        hw_scrubber
+396          1       e       1        interleave_chip_selects
+397          2       e       8        max_mem_clock
+399          1       e       2        multi_core
+400          1       e       1        power_on_after_fail
+412          4       e       6        debug_level
+416          4       e       7        boot_first
+420          4       e       7        boot_second
+424          4       e       7        boot_third
+428          4       h       0        boot_index
+432          8       h       0        boot_countdown
+440          4       e       9        slow_cpu
+444          1       e       1        nmi
+445          1       e       1        iommu
+728        256       h       0        user_data
+984         16       h       0        check_sum
+# Reserve the extended AMD configuration registers
+1000        24       r       0        amd_reserved
+
+
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Network
+7     1     HDD
+7     2     Floppy
+7     8     Fallback_Network
+7     9     Fallback_HDD
+7     10    Fallback_Floppy
+#7     3     ROM
+8     0     400Mhz
+8     1     333Mhz
+8     2     266Mhz
+8     3     200Mhz
+9     0     off
+9     1     87.5%
+9     2     75.0%
+9     3     62.5%
+9     4     50.0%
+9     5     37.5%
+9     6     25.0%
+9     7     12.5%
+
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb
new file mode 100644
index 0000000..92fe521
--- /dev/null
+++ b/src/mainboard/amd/dinar/devicetree.cb
@@ -0,0 +1,104 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+chip northbridge/amd/agesa/family15/root_complex
+	device lapic_cluster 0 on
+		chip cpu/amd/agesa/family15
+		device lapic 0x20 on end
+		end
+	end
+	device pci_domain 0 on
+		subsystemid 0x1022 0x1705 inherit
+		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
+			device pci 18.0 on end # Link 0
+			device pci 18.0 on     # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
+				chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
+					device pci 0.0 on  end # HT Root Complex
+					device pci 0.1 off end # CLKCONFIG
+					device pci 2.0 on  end # GPP1 Port0
+					device pci 3.0 off end # GPP1 Port1
+					device pci 4.0 off end # GPP3a Port0
+					device pci 5.0 off end # GPP3a Port1
+					device pci 6.0 off end # GPP3a Port2
+					device pci 7.0 off end # GPP3a Port3
+					device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
+					device pci 9.0 off end # GPP3a Port4
+					device pci a.0 off end # GPP3a Port5
+					device pci b.0 off end # GPP2 Port0 (Not for sr5650)
+					device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
+					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
+					register "gpp1_configuration" = "0"   # Configuration 16:0 default
+					register "gpp2_configuration" = "1"   # Configuration 8:8
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
+					register "port_enable" = "0x2104"
+				end # northbridge/amd/cimx/rd890
+				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus
+					device pci 11.0 on end # SATA
+					device pci 12.0 on end # USB1
+					device pci 12.1 on end # USB1
+					device pci 12.2 on end # USB1
+					device pci 13.0 on end # USB2
+					device pci 13.1 on end # USB2
+					device pci 13.2 on end # USB2
+					device pci 14.0 on # SM
+					end # SM
+					device pci 14.1 off end # IDE  0x439c
+					device pci 14.2 off end # HDA  0x4383
+					device pci 14.3 on # LPC
+						chip superio/smsc/sch4037  # SIO SMSC SCH4037
+							device pnp 2e.0 on # Floppy
+							io 0x60 = 0x3f0
+							irq 0x70 = 6
+							irq 0x74 = 2
+						end
+						device pnp 2e.3 on	# Parallel port
+							io 0x60 = 0x378
+							irq 0x70 = 7
+							irq 0x74 = 4
+						end
+						device pnp 2e.4 on	# COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 2e.5 on	# COM2 / IR
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 2e.7 on	# PS/2 keyboard / mouse
+							io 0x60 = 0x60
+							io 0x62 = 0x64
+							irq 0x70 = 1	# PS/2 keyboard interrupt
+							irq 0x72 = 12	# PS/2 mouse interrupt
+						end
+					end #SIO SMSC307
+				end #LPC
+				device pci 14.4 on end # PCI bridge, 0x4384
+					device pci 14.5 on end # USB 3
+					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
+				end #southbridge/amd/cimx/sb700
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+			device pci 18.5 on end
+		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
+	end #pci_domain
+end #northbridge/amd/agesa/family15/root_complex
+
diff --git a/src/mainboard/amd/dinar/dimmSpd.c b/src/mainboard/amd/dinar/dimmSpd.c
new file mode 100644
index 0000000..f26ec20
--- /dev/null
+++ b/src/mainboard/amd/dinar/dimmSpd.c
@@ -0,0 +1,333 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define SMBUS_BASE_ADDR  0xB00
+#define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+#define LTC4305_SMBUS_ADDR       0x94
+
+typedef struct _DIMM_INFO_SMBUS{
+	UINT8   SocketId;
+	UINT8   MemChannelId;
+	UINT8   DimmId;
+	UINT8   SmbusAddress;
+} DIMM_INFO_SMBUS;
+/*
+ * SPD address table - porting required
+ */
+STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] =
+{
+	/* Socket, Channel, Dimm, Smbus */
+	{0, 0, 0, 0xAC},
+	{0, 0, 1, 0xAE},
+	{0, 1, 0, 0xA8},
+	{0, 1, 1, 0xAA},
+	{0, 2, 0, 0xA4},
+	{0, 2, 1, 0xA6},
+	{0, 3, 0, 0xA0},
+	{0, 3, 1, 0xA2},
+	{1, 0, 0, 0xAC},
+	{1, 0, 1, 0xAE},
+	{1, 1, 0, 0xA8},
+	{1, 1, 1, 0xAA},
+	{1, 2, 0, 0xA4},
+	{1, 2, 1, 0xA6},
+	{1, 3, 0, 0xA0},
+	{1, 3, 1, 0xA2}
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+		IN UINT32 Func,
+		IN UINT32 Data,
+		IN OUT AGESA_READ_SPD_PARAMS *SpdData
+		);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+STATIC
+VOID
+WritePmReg (
+		IN UINT8 Reg,
+		IN UINT8 Data
+	   )
+{
+	__outbyte (0xCD6, Reg);
+	__outbyte (0xCD7, Data);
+}
+STATIC
+VOID
+SetupFch (
+		IN UINT16
+		IN IoBase
+	 )
+{
+
+	AMD_CONFIG_PARAMS         StdHeader;
+	UINT32                    PciData32;
+	UINT8                     PciData8;
+	PCI_ADDR                  PciAddress;
+
+	/* Set SMBUS MMIO. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
+	PciData32 = (SMBUS_BASE_ADDR & 0xFFFFFFF0) | BIT0;
+	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
+
+	/* Enable SMBUS MMIO. */
+	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
+	LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader); ;
+	PciData8 |= BIT0;
+	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
+	/* set SMBus clock to 400 KHz */
+	__outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
+}
+
+/*
+ *
+ * ReadSmbusByteData - read a single SPD byte from any offset
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByteData (
+		IN UINT16 Iobase,
+		IN UINT8  Address,
+		OUT UINT8 *ByteData,
+		IN UINTN  Offset
+		)
+{
+	UINTN  Status;
+	UINT64 Limit;
+
+	Address |= 1; 																// set read bit
+
+	__outbyte (Iobase + 0, 0xFF);                // clear error status
+	__outbyte (Iobase + 1, 0x1F);                // clear error status
+	__outbyte (Iobase + 3, Offset);              // offset in eeprom
+	__outbyte (Iobase + 4, Address);             // slave address and read bit
+	__outbyte (Iobase + 2, 0x48);                // read byte command
+
+	/* time limit to avoid hanging for unexpected error status (should never happen) */
+	Limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		Status = __inbyte (Iobase);
+		if (__rdtsc () > Limit) break;
+		if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	*ByteData = __inbyte (Iobase + 5);
+	if (Status == 2) Status = 0;                      // check for done with no errors
+	return Status;
+}
+/*
+ *
+ * WriteSmbusByteData - Write a single SPD byte onto any offset
+ *
+ */
+STATIC
+AGESA_STATUS
+WriteSmbusByteData (
+		IN UINT16 Iobase,
+		IN UINT8  Address,
+		IN UINT8  ByteData,
+		IN UINTN  Offset
+		)
+{
+	UINTN  Status;
+	UINT64 Limit;
+	Address &= 0xFE; 														// set write bit
+
+	__outbyte (Iobase + 0, 0xFF);                // clear error status
+	__outbyte (Iobase + 1, 0x1F);                // clear error status
+	__outbyte (Iobase + 3, Offset);              // offset in eeprom
+	__outbyte (Iobase + 4, Address);   					// slave address and write bit
+	__outbyte (Iobase + 5, ByteData);            // offset in byte data                                             //
+	__outbyte (Iobase + 2, 0x48);                // write byte command
+	/* time limit to avoid hanging for unexpected error status (should never happen) */
+	Limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		Status = __inbyte (Iobase);
+		if (__rdtsc () > Limit) break;
+		if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+	if (Status == 2) Status = 0;                      // check for done with no errors
+	return Status;
+}
+
+/*
+ *
+ * ReadSmbusByte - read a single SPD byte from the default offset
+ *                 this function is faster function readSmbusByteData
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSmbusByte (
+		IN UINT16 Iobase,
+		IN UINT8  Address,
+		OUT UINT8 *Buffer
+	      )
+{
+	UINTN   Status;
+	UINT64  Limit;
+
+	__outbyte (Iobase + 0, 0xFF);                // clear error status
+	__outbyte (Iobase + 1, 0x1F);                // clear error status
+	__outbyte (Iobase + 2, 0x44);                // read command
+
+	// time limit to avoid hanging for unexpected error status
+	Limit = __rdtsc () + 2000000000 / 10;
+	for (;;) {
+		Status = __inbyte (Iobase);
+		if (__rdtsc () > Limit) break;
+		if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
+		if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
+		break;
+	}
+
+	Buffer [0] = __inbyte (Iobase + 5);
+	if (Status == 2) Status = 0;                      // check for done with no errors
+	return Status;
+}
+
+/*
+ *
+ * ReadSpd - Read one or more SPD bytes from a DIMM.
+ *           Start with offset zero and read sequentially.
+ *           Optimization relies on autoincrement to avoid
+ *           sending offset for every byte.
+ *           Reads 128 bytes in 7-8 ms at 400 KHz.
+ *
+ */
+
+STATIC
+AGESA_STATUS
+ReadSpd (
+		IN UINT16 IoBase,
+		IN UINT8  SmbusSlaveAddress,
+		OUT UINT8 *Buffer,
+		IN UINTN  Count
+	)
+{
+	UINTN Index, Status;
+
+	/* read the first byte using offset zero */
+	Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
+	if (Status) return Status;
+
+	/* read the remaining bytes using auto-increment for speed */
+	for (Index = 1; Index < Count; Index++){
+		Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
+		if (Status) return Status;
+	}
+	return 0;
+}
+
+AGESA_STATUS
+AmdMemoryReadSPD (
+		IN UINT32 Func,
+		IN UINT32 Data,
+		IN OUT AGESA_READ_SPD_PARAMS *SpdData
+		)
+{
+	AGESA_STATUS Status;
+	UINT8  SmBusAddress = 0;
+	UINTN  Index;
+	UINTN  MaxSocket = DIMENSION (SpdAddrLookup);
+
+	for (Index = 0; Index < MaxSocket; Index ++){
+		if ((SpdData->SocketId     == SpdAddrLookup[Index].SocketId)     &&
+				(SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) &&
+				(SpdData->DimmId       == SpdAddrLookup[Index].DimmId)) {
+			SmBusAddress = SpdAddrLookup[Index].SmbusAddress;
+			break;
+		}
+	}
+
+
+	if (SmBusAddress == 0) return AGESA_ERROR;
+
+	SetupFch (SMBUS_BASE_ADDR);
+
+	Status = WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03);
+
+	switch (SpdData->SocketId) {
+		case 0:
+			/* Switch onto the  First CPU Socket SMBUS */
+			WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x80, 0x03);
+			break;
+		case 1:
+			/* Switch onto the  Second CPU Socket SMBUS */
+			WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x40, 0x03);
+			break;
+		default:
+			/* Switch off two CPU Sockets SMBUS */
+			WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03);
+			break;
+	}
+	Status =  ReadSpd (SMBUS_BASE_ADDR, SmBusAddress, SpdData->Buffer, 256);
+
+	/*Output SPD Debug Message*/
+	printk(BIOS_EMERG, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
+	printk(BIOS_DEBUG, " Status = %d\n",Status);
+	printk(BIOS_DEBUG, "SocketId MemChannelId SpdData->DimmId SmBusAddress Buffer\n");
+	printk(BIOS_DEBUG, "%x, %x, %x, %x, %x\n", SpdData->SocketId, SpdData->MemChannelId, SpdData->DimmId, SmBusAddress, SpdData->Buffer);
+
+	/* Switch off two CPU Sockets SMBUS */
+	WriteSmbusByteData (SMBUS_BASE_ADDR, LTC4305_SMBUS_ADDR, 0x00, 0x03);
+	return Status;
+}
diff --git a/src/mainboard/amd/dinar/dsdt.asl b/src/mainboard/amd/dinar/dsdt.asl
new file mode 100644
index 0000000..0cbffb7
--- /dev/null
+++ b/src/mainboard/amd/dinar/dsdt.asl
@@ -0,0 +1,1157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+        "DSDT.AML",           /* Output filename */
+        "DSDT",                 /* Signature */
+        0x02,           /* DSDT Revision, needs to be 2 for 64bit */
+	"AMD   ",               /* OEMID */
+        "DINAR   ",          /* TABLE ID */
+        0x00010001      /* OEM Revision */
+        )
+{       /* Start of ASL file */
+        /* #include "../../../arch/x86/acpi/debug.asl" */       /* Include global debug methods if needed */
+
+        /* Data to be patched by the BIOS during POST */
+        /* FIXME the patching is not done yet! */
+        /* Memory related values */
+        Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+        Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+        Name(PBLN, 0x0) /* Length of BIOS area */
+
+        Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)  /* Base address of PCIe config space */
+        Name(HPBA, 0xFED00000)  /* Base address of HPET table */
+
+        Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+        /* Some global data */
+        Name(OSV, Ones) /* Assume nothing */
+        Name(GPIC, 0x1) /* Assume PIC */
+
+        /*
+         * Processor Object
+         *
+         */
+        Scope (\_PR) {          /* define processor scope */
+                Processor(
+                        CPU0,           /* name space name */
+                        0,              /* Unique number for this processor */
+                        0x810,          /* PBLK system I/O address !hardcoded! */
+                        0x06            /* PBLKLEN for boot processor */
+                        ) {
+                        #include "acpi/cpstate.asl"
+                }
+                Processor(
+                        CPU1,           /* name space name */
+                        1,              /* Unique number for this processor */
+                        0x0000,         /* PBLK system I/O address !hardcoded! */
+                        0x00            /* PBLKLEN for boot processor */
+                        ) {
+                        #include "acpi/cpstate.asl"
+                }
+                Processor(
+                        CPU2,           /* name space name */
+                        2,              /* Unique number for this processor */
+                        0x0000,         /* PBLK system I/O address !hardcoded! */
+                        0x00            /* PBLKLEN for boot processor */
+                        ) {
+                        #include "acpi/cpstate.asl"
+                }
+                Processor(
+                        CPU3,           /* name space name */
+                        3,              /* Unique number for this processor */
+                        0x0000,         /* PBLK system I/O address !hardcoded! */
+                        0x00            /* PBLKLEN for boot processor */
+                        ) {
+                        #include "acpi/cpstate.asl"
+                }
+        } /* End _PR scope */
+
+        /* PIC IRQ mapping registers, C00h-C01h. */
+        OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002)
+                Field(PIRQ, ByteAcc, NoLock, Preserve) {
+                PIDX, 0x00000008,
+                PDAT, 0x00000008,  /* Offset: 1h */
+        }
+        IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) {
+                PIRA, 0x00000008,       /* Index 0 */
+                PIRB, 0x00000008,       /* Index 1 */
+                PIRC, 0x00000008,       /* Index 2 */
+                PIRD, 0x00000008,       /* Index 3 */
+                PIRE, 0x00000008,       /* Index 4 */
+                PIRF, 0x00000008,       /* Index 5 */
+                PIRG, 0x00000008,       /* Index 6 */
+                PIRH, 0x00000008,       /* Index 7 */
+                Offset(0x10),
+                PIRS, 0x00000008,
+                Offset(0x13),
+                HDAD, 0x00000008,
+                , 0x00000008,
+                GEC,  0x00000008,
+                Offset(0x30),
+                USB1, 0x00000008,
+                USB2, 0x00000008,
+                USB3, 0x00000008,
+                USB4, 0x00000008,
+                USB5, 0x00000008,
+                USB6, 0x00000008,
+                USB7, 0x00000008,
+                Offset(0x40),
+                IDE,  0x00000008,
+                SATA, 0x00000008,
+                Offset(0x50),
+                GPP0, 0x00000008,
+                GPP1, 0x00000008,
+                GPP2, 0x00000008,
+                GPP3, 0x00000008
+        }
+
+        /* PCI Error control register */
+        OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
+                Field(PERC, ByteAcc, NoLock, Preserve) {
+                SENS, 0x00000001,
+                PENS, 0x00000001,
+                SENE, 0x00000001,
+                PENE, 0x00000001,
+        }
+
+        /* Client Management index/data registers */
+        OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
+                Field(CMT, ByteAcc, NoLock, Preserve) {
+                CMTI,      8,
+                /* Client Management Data register */
+                G64E,   1,
+                G64O,      1,
+                G32O,      2,
+                ,       2,
+                GPSL,     2,
+        }
+
+        /* GPM Port register */
+        OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
+                Field(GPT, ByteAcc, NoLock, Preserve) {
+                GPB0,1,
+                GPB1,1,
+                GPB2,1,
+                GPB3,1,
+                GPB4,1,
+                GPB5,1,
+                GPB6,1,
+                GPB7,1,
+        }
+
+        /* Flash ROM program enable register */
+        OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
+                Field(FRE, ByteAcc, NoLock, Preserve) {
+                ,     0x00000006,
+                FLRE, 0x00000001,
+        }
+
+        /* PM2 index/data registers */
+        OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
+                Field(PM2R, ByteAcc, NoLock, Preserve) {
+                PM2I, 0x00000008,
+                PM2D, 0x00000008,
+        }
+
+        /* Power Management I/O registers, TODO:PMIO is quite different in SB700. */
+        OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002)
+                Field(PMRG, ByteAcc, NoLock, Preserve) {
+                PMRI, 0x00000008,
+                PMRD, 0x00000008,
+        }
+        IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) {
+                Offset(0x24),
+                MMSO,32,
+                Offset(0x37),   /* GPMLevelConfig0 */
+                , 3,
+                PLC0, 1,
+                PLC1, 1,
+                PLC2, 1,
+                PLC3, 1,
+                PLC8, 1,
+                Offset(0x38),   /* GPMLevelConfig1 */
+                , 1,
+                 PLC4, 1,
+                 PLC5, 1,
+                , 1,
+                 PLC6, 1,
+                 PLC7, 1,
+                Offset(0x50),
+                HPAD,32,
+                Offset(0x60),
+                P1EB,16,
+                Offset(0x65),   /* UsbPMControl */
+                , 4,
+                URRE, 1,
+                Offset(0x96),   /* GPM98IN */
+                G8IS, 1,
+                G9IS, 1,
+                Offset(0x9A),   /* EnhanceControl */
+                ,7,
+                HPDE, 1,
+                Offset(0xC8),
+                ,2,
+                SPRE,1,
+                TPDE,1,
+                Offset(0xF0),
+                ,3,
+                RSTU,1
+        }
+
+        /* PM1 Event Block
+        * First word is PM1_Status, Second word is PM1_Enable
+        */
+        OperationRegion(P1E0, SystemIO, P1EB, 0x04)
+                Field(P1E0, ByteAcc, NoLock, Preserve) {
+                ,14,
+                PEWS,1,
+                WSTA,1,
+                ,14,
+                PEWD,1
+        }
+
+    OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+    Field (GRAM, ByteAcc, Lock, Preserve)
+    {
+        Offset (0x10),
+        FLG0,   8
+    }
+
+        Scope(\_SB) {
+                /* PCIe Configuration Space for 16 busses */
+                OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
+                        Field(PCFG, ByteAcc, NoLock, Preserve) {
+                        /* Byte offsets are computed using the following technique:
+                         * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
+                         * The 8 comes from 8 functions per device, and 4096 bytes per function config space
+                        */
+                        Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
+                        STB5, 32,
+                        Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
+                        PT0D, 1,
+                        PT1D, 1,
+                        PT2D, 1,
+                        PT3D, 1,
+                        PT4D, 1,
+                        PT5D, 1,
+                        PT6D, 1,
+                        PT7D, 1,
+                        PT8D, 1,
+                        PT9D, 1,
+                        Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
+                        SBIE, 1,
+                        SBME, 1,
+                        Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
+                        SBRI, 8,
+                        Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
+                        SBB1, 32,
+                        Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
+                        ,14,
+                        P92E, 1,                /* Port92 decode enable */
+                }
+
+                OperationRegion(SB5, SystemMemory, STB5, 0x1000)
+                        Field(SB5, AnyAcc, NoLock, Preserve){
+                        /* Port 0 */
+                        Offset(0x120),          /* Port 0 Task file status */
+                        P0ER, 1,
+                        , 2,
+                        P0DQ, 1,
+                        , 3,
+                        P0BY, 1,
+                        Offset(0x128),          /* Port 0 Serial ATA status */
+                        P0DD, 4,
+                        , 4,
+                        P0IS, 4,
+                        Offset(0x12C),          /* Port 0 Serial ATA control */
+                        P0DI, 4,
+                        Offset(0x130),          /* Port 0 Serial ATA error */
+                        , 16,
+                        P0PR, 1,
+
+                        /* Port 1 */
+                        offset(0x1A0),          /* Port 1 Task file status */
+                        P1ER, 1,
+                        , 2,
+                        P1DQ, 1,
+                        , 3,
+                        P1BY, 1,
+                        Offset(0x1A8),          /* Port 1 Serial ATA status */
+                        P1DD, 4,
+                        , 4,
+                        P1IS, 4,
+                        Offset(0x1AC),          /* Port 1 Serial ATA control */
+                        P1DI, 4,
+                        Offset(0x1B0),          /* Port 1 Serial ATA error */
+                        , 16,
+                        P1PR, 1,
+
+                        /* Port 2 */
+                        Offset(0x220),          /* Port 2 Task file status */
+                        P2ER, 1,
+                        , 2,
+                        P2DQ, 1,
+                        , 3,
+                        P2BY, 1,
+                        Offset(0x228),          /* Port 2 Serial ATA status */
+                        P2DD, 4,
+                        , 4,
+                        P2IS, 4,
+                        Offset(0x22C),          /* Port 2 Serial ATA control */
+                        P2DI, 4,
+                        Offset(0x230),          /* Port 2 Serial ATA error */
+                        , 16,
+                        P2PR, 1,
+
+                        /* Port 3 */
+                        Offset(0x2A0),          /* Port 3 Task file status */
+                        P3ER, 1,
+                        , 2,
+                        P3DQ, 1,
+                        , 3,
+                        P3BY, 1,
+                        Offset(0x2A8),          /* Port 3 Serial ATA status */
+                        P3DD, 4,
+                        , 4,
+                        P3IS, 4,
+                        Offset(0x2AC),          /* Port 3 Serial ATA control */
+                        P3DI, 4,
+                        Offset(0x2B0),          /* Port 3 Serial ATA error */
+                        , 16,
+                        P3PR, 1,
+                }
+        }
+
+
+        #include "acpi/routing.asl"
+
+        Scope(\_SB) {
+
+                /* Debug Port registers, 80h. */
+                OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001)
+                        Field(DBBG, ByteAcc, NoLock, Preserve) {
+                        DBG8, 0x00000008,
+                }
+
+                Method(_PIC, 1) {
+                        Store(Arg0, GPIC)
+                        If (GPIC) {
+                                Store(0xAA, \_SB.DBG8)
+                                \_SB.DSPI()
+                        } else {
+                                Store(0xAC, \_SB.DBG8)
+                        }
+                }
+
+                Method(DSPI, 0) {
+                        \_SB.GRUA(0x1F)
+                        \_SB.GRUB(0x1F)
+                        \_SB.GRUC(0x1F)
+                        \_SB.GRUD(0x1F)
+                        Store(0x1F, PIRE)
+                        Store(0x1F, PIRF)
+                        Store(0x1F, PIRG)
+                        Store(0x1F, PIRH)
+                }
+
+                Method(GRUA, 1) {
+                        Store(Arg0, PIRA)
+                        Store(Arg0, HDAD)
+                        Store(Arg0, GEC)
+                        Store(Arg0, GPP0)
+                        Store(Arg0, GPP0)
+                }
+
+                Method(GRUB, 1) {
+                        Store(Arg0, PIRB)
+                        Store(Arg0, USB2)
+                        Store(Arg0, USB4)
+                        Store(Arg0, USB6)
+                        Store(Arg0, GPP1)
+                        Store(Arg0, IDE)
+                }
+
+                Method(GRUC, 1) {
+                        Store(Arg0, PIRC)
+                        Store(Arg0, USB1)
+                        Store(Arg0, USB3)
+                        Store(Arg0, USB5)
+                        Store(Arg0, USB7)
+                        Store(Arg0, GPP2)
+                }
+
+                Method(GRUD, 1) {
+                        Store(Arg0, PIRD)
+                        Store(Arg0, SATA)
+                        Store(Arg0, GPP3)
+                }
+
+                Name(IRQB, ResourceTemplate() {
+                        IRQ(Level, ActiveLow, Shared) {
+                                15
+                }})
+
+                Name(IRQP, ResourceTemplate() {
+                        IRQ(Level, ActiveLow, Shared) {
+                                3, 4, 5, 7, 10, 11, 12, 14, 15
+                }})
+
+                Device(INTA) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 1)
+                        Method(_STA, 0) {
+                                if (PIRA) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                \_SB.GRUA(0x1F)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRA, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                \_SB.GRUA(Local0)
+                        }
+                }
+
+                Device(INTB) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 2)
+                        Method(_STA, 0) {
+                                if (PIRB) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                \_SB.GRUB(0x1F)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRB, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                \_SB.GRUB(Local0)
+                        }
+                }
+
+                Device(INTC) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 3)
+                        Method(_STA, 0) {
+                                if (PIRC) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                \_SB.GRUC(0x1F)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRC, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                \_SB.GRUC(Local0)
+                        }
+                }
+
+                Device(INTD) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 4)
+                        Method(_STA, 0) {
+                                if (PIRD) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                \_SB.GRUD(0x1F)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRD, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                \_SB.GRUD(Local0)
+                        }
+                }
+
+                Device(INTE) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 5)
+                        Method(_STA, 0) {
+                                if (PIRE) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                Store(0x1F, PIRE)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRE, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                Store(Local0, PIRE)
+                        }
+                }
+
+                Device(INTF) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 6)
+                        Method(_STA, 0) {
+                                if (PIRF) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                Store(0x1F, PIRF)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRF, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                Store(Local0, PIRF)
+                        }
+                }
+
+                Device(INTG) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 7)
+                        Method(_STA, 0) {
+                                if (PIRG) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                Store(0x1F, PIRG)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRG, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                Store(Local0, PIRG)
+                        }
+                }
+
+                Device(INTH) {
+                        Name(_HID, EISAID("PNP0C0F"))
+                        Name(_UID, 8)
+                        Method(_STA, 0) {
+                                if (PIRH) {
+                                        Return(0x0B)
+                                } else {
+                                        Return(0x09)
+                                }
+                        }
+                        Method(_DIS ,0) {
+                                Store(0x1F, PIRH)
+                        }
+                        Method(_PRS ,0) {
+                                Return(IRQP)
+                        }
+                        Method(_CRS ,0) {
+                                CreateWordField(IRQB, 1, IRQN)
+                                ShiftLeft(1, PIRH, IRQN)
+                                Return(IRQB)
+                        }
+                        Method(_SRS, 1) {
+                                CreateWordField(Arg0, 1, IRQM)
+                                FindSetRightBit(IRQM, Local0)
+                                Decrement(Local0)
+                                Store(Local0, PIRH)
+                        }
+                }
+        }   /* End Scope(_SB)  */
+
+
+        /* Supported sleep states: */
+        Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
+
+        If (LAnd(SSFG, 0x01)) {
+                Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
+        }
+        If (LAnd(SSFG, 0x02)) {
+                Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
+        }
+        If (LAnd(SSFG, 0x04)) {
+                Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
+        }
+        If (LAnd(SSFG, 0x08)) {
+                Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
+        }
+
+        Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
+
+        Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
+        Name(CSMS, 0)                   /* Current System State */
+
+        /* Wake status package */
+        Name(WKST,Package(){Zero, Zero})
+
+        /*
+        * \_PTS - Prepare to Sleep method
+        *
+        *       Entry:
+        *               Arg0=The value of the sleeping state S1=1, S2=2, etc
+        *
+        * Exit:
+        *               -none-
+        *
+        * The _PTS control method is executed at the beginning of the sleep process
+        * for S1-S5. The sleeping value is passed to the _PTS control method.   This
+        * control method may be executed a relatively long time before entering the
+        * sleep state and the OS may abort      the operation without notification to
+        * the ACPI driver.  This method cannot modify the configuration or power
+        * state of any device in the system.
+        */
+        Method(\_PTS, 1) {
+                /* DBGO("\\_PTS\n") */
+                /* DBGO("From S0 to S") */
+                /* DBGO(Arg0) */
+                /* DBGO("\n") */
+
+                /* Don't allow PCIRST# to reset USB */
+                if (LEqual(Arg0,3)){
+                        Store(0,URRE)
+                }
+
+                /* Clear sleep SMI status flag and enable sleep SMI trap. */
+                /*Store(One, CSSM)
+                Store(One, SSEN)*/
+
+                /* On older chips, clear PciExpWakeDisEn */
+                /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+                *       Store(0,\_SB.PWDE)
+                *}
+                */
+
+                /* Clear wake status structure. */
+                Store(0, Index(WKST,0))
+                Store(0, Index(WKST,1))
+        } /* End Method(\_PTS) */
+
+        /*
+        *  The following method results in a "not a valid reserved NameSeg"
+        *  warning so I have commented it out for the duration.  It isn't
+        *  used, so it could be removed.
+        *
+        *
+        *       \_GTS OEM Going To Sleep method
+        *
+        *       Entry:
+        *               Arg0=The value of the sleeping state S1=1, S2=2
+        *
+        *       Exit:
+        *               -none-
+        *
+        *  Method(\_GTS, 1) {
+        *  DBGO("\\_GTS\n")
+        *  DBGO("From S0 to S")
+        *  DBGO(Arg0)
+        *  DBGO("\n")
+        *  }
+        */
+
+        /*
+        *       \_BFS OEM Back From Sleep method
+        *
+        *       Entry:
+        *               Arg0=The value of the sleeping state S1=1, S2=2
+        *
+        *       Exit:
+        *               -none-
+        */
+        Method(\_BFS, 1) {
+                /* DBGO("\\_BFS\n") */
+                /* DBGO("From S") */
+                /* DBGO(Arg0) */
+                /* DBGO(" to S0\n") */
+        }
+
+        /*
+        *  \_WAK System Wake method
+        *
+        *       Entry:
+        *               Arg0=The value of the sleeping state S1=1, S2=2
+        *
+        *       Exit:
+        *               Return package of 2 DWords
+        *               Dword 1 - Status
+        *                       0x00000000      wake succeeded
+        *                       0x00000001      Wake was signaled but failed due to lack of power
+        *                       0x00000002      Wake was signaled but failed due to thermal condition
+        *               Dword 2 - Power Supply state
+        *                       if non-zero the effective S-state the power supply entered
+        */
+        Method(\_WAK, 1) {
+                /* DBGO("\\_WAK\n") */
+                /* DBGO("From S") */
+                /* DBGO(Arg0) */
+                /* DBGO(" to S0\n") */
+
+                /* Re-enable HPET */
+                Store(1,HPDE)
+
+                /* Restore PCIRST# so it resets USB */
+                if (LEqual(Arg0,3)){
+                        Store(1,URRE)
+                }
+
+                /* Arbitrarily clear PciExpWakeStatus */
+                Store(PEWS, PEWS)
+
+                /* if(DeRefOf(Index(WKST,0))) {
+                *       Store(0, Index(WKST,1))
+                * } else {
+                *       Store(Arg0, Index(WKST,1))
+                * }
+                */
+                Return(WKST)
+        } /* End Method(\_WAK) */
+
+        Scope(\_GPE) {  /* Start Scope GPE */
+        }       /* End Scope GPE */
+
+        /* South Bridge */
+        Scope(\_SB) { /* Start \_SB scope */
+                #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
+
+                /*  _SB.PCI0 */
+                /* Note: Only need HID on Primary Bus */
+                Device(PCI0) {
+                        External (TOM1)
+                        External (TOM2)
+                        External (TOM3)
+                        External (TOM4)
+                        Name(_HID, EISAID("PNP0A03"))
+                        Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
+                        Method(_BBN, 0) { /* Bus number = 0 */
+                                Return(0)
+                        }
+                        Method(_STA, 0) {
+                                /* DBGO("\\_SB\\PCI0\\_STA\n") */
+                                Return(0x0B)     /* Status is visible */
+                        }
+                        Method(_PRT,0) {
+                                If(GPIC){ Return(APR0) }   /* APIC mode */
+                                Return (PR0)                  /* PIC Mode */
+                        } /* end _PRT */
+
+                        /* Describe the Northbridge devices */
+                        Device(AMRT) {
+                                Name(_ADR, 0x00000000)
+                        } /* end AMRT */
+
+                        /* The internal GFX bridge */
+                        Device(AGPB) {
+                                Name(_ADR, 0x00010000)
+                                Method(_STA,0) {
+                                        Return(0x0F)
+                                }
+                        }  /* end AGPB */
+
+                        /* The external GFX bridge */
+                        Device(PBR2) {
+                                Name(_ADR, 0x00020000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS2) }   /* APIC mode */
+                                        Return (PS2)               /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR2 */
+
+                        /* The external GFX bridge */
+                        Device(PBR3) {
+                                Name(_ADR, 0x00030000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS3) }   /* APIC mode */
+                                        Return (PS3)               /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR3 */
+
+                        Device(PBR4) {
+                                Name(_ADR, 0x00040000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS4) }   /* APIC mode */
+                                        Return (PS4)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR4 */
+
+                        Device(PBR5) {
+                                Name(_ADR, 0x00050000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS5) }   /* APIC mode */
+                                        Return (PS5)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR5 */
+
+                        Device(PBR6) {
+                                Name(_ADR, 0x00060000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS6) }   /* APIC mode */
+                                        Return (PS6)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR6 */
+
+                        /* The onboard EtherNet chip */
+                        Device(PBR7) {
+                                Name(_ADR, 0x00070000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APS7) }   /* APIC mode */
+                                        Return (PS7)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PBR7 */
+
+                        Device(PE20) {
+                                Name(_ADR, 0x00150000)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APE0) }   /* APIC mode */
+                                        Return (PE0)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PE20 */
+                        Device(PE21) {
+                                Name(_ADR, 0x00150001)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APE1) }   /* APIC mode */
+                                        Return (PE1)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PE21 */
+                        Device(PE22) {
+                                Name(_ADR, 0x00150002)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APE2) }   /* APIC mode */
+                                        Return (APE2)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PE22 */
+                        Device(PE23) {
+                                Name(_ADR, 0x00150003)
+                                Method(_PRT,0) {
+                                        If(GPIC){ Return(APE3) }   /* APIC mode */
+                                        Return (PE3)                  /* PIC Mode */
+                                } /* end _PRT */
+                        } /* end PE23 */
+
+                        /* Describe the Southbridge devices */
+                        Device(AZHD) {
+                                Name(_ADR, 0x00140002)
+                                OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
+                                        Field(AZPD, AnyAcc, NoLock, Preserve) {
+                                        offset (0x42),
+                                        NSDI, 1,
+                                        NSDO, 1,
+                                        NSEN, 1,
+                                }
+                        } /* end AZHD */
+
+                        Device(GEC) {
+                                Name(_ADR, 0x00140006)
+                        } /* end GEC */
+
+                        Device(UOH1) {
+                                Name(_ADR, 0x00120000)
+                                #include "acpi/usb.asl"
+                        } /* end UOH1 */
+
+                        Device(UOH3) {
+                                Name(_ADR, 0x00130000)
+                                #include "acpi/usb.asl"
+                        } /* end UOH3 */
+
+                        Device(UOH5) {
+                                Name(_ADR, 0x00160000)
+                                #include "acpi/usb.asl"
+                        } /* end UOH5 */
+
+                        Device(UEH1) {
+                                Name(_ADR, 0x00140005)
+                                #include "acpi/usb.asl"
+                        } /* end UEH1 */
+
+                        Device(UOH2) {
+                                Name(_ADR, 0x00120002)
+                                #include "acpi/usb.asl"
+                        } /* end UOH2 */
+
+                        Device(UOH4) {
+                                Name(_ADR, 0x00130002)
+                                #include "acpi/usb.asl"
+                        } /* end UOH4 */
+
+                        Device(UOH6) {
+                                Name(_ADR, 0x00160002)
+                                #include "acpi/usb.asl"
+                        } /* end UOH5 */
+
+                        Device(XHC0) {
+                                Name(_ADR, 0x00100000)
+                                #include "acpi/usb.asl"
+                        } /* end XHC0 */
+
+                        Device(XHC1) {
+                                Name(_ADR, 0x00100001)
+                                #include "acpi/usb.asl"
+                        } /* end XHC1 */
+
+                        Device(SBUS) {
+                                Name(_ADR, 0x00140000)
+                        } /* end SBUS */
+
+                        Device(LIBR) {
+                                Name(_ADR, 0x00140003)
+                                /* Real Time Clock Device */
+                                Device(RTC0) {
+                                        Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
+                                        Name(BUF0, ResourceTemplate() {
+                                                IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
+                                        })
+                                        Name(BUF1, ResourceTemplate() {
+                                                IRQNoFlags() {8}
+                                                IO(Decode16, 0x0070, 0x0070, 0x01, 0x02)
+                                        })
+                                        Method(_CRS, 0) {
+                                                If(LAnd(HPAD, 0xFFFFFF00)) {
+                                                        Return(BUF0)
+                                                }
+                                                Return(BUF1)
+                                        }
+                                } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
+
+                                Device(TMR) {   /* Timer */
+                                        Name(_HID,EISAID("PNP0100"))    /* System Timer */
+                                        Name(BUF0, ResourceTemplate() {
+                                                IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
+                                        })
+                                        Name(BUF1, ResourceTemplate() {
+                                                IRQNoFlags() {0}
+                                                IO(Decode16, 0x0040, 0x0040, 0x01, 0x04)
+                                        })
+                                        Method(_CRS, 0) {
+                                                If(LAnd(HPAD, 0xFFFFFF00)) {
+                                                        Return(BUF0)
+                                                }
+                                                Return(BUF1)
+                                        }
+                                } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
+
+                                Device(SPKR) {  /* Speaker */
+                                        Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
+                                        Name(_CRS, ResourceTemplate() {
+                                                IO(Decode16, 0x0061, 0x0061, 0, 1)
+                                        })
+                                } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
+
+                                Device(PIC) {
+                                        Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
+                                        Name(_CRS, ResourceTemplate() {
+                                                IRQNoFlags(){2}
+                                                IO(Decode16,0x0020, 0x0020, 0, 2)
+                                                IO(Decode16,0x00A0, 0x00A0, 0, 2)
+                                                /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
+                                                /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
+                                        })
+                                } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
+
+                                Device(MAD) { /* 8257 DMA */
+                                        Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
+                                        Name(_CRS, ResourceTemplate() {
+                                                DMA(Compatibility,BusMaster,Transfer8){4}
+                                                IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
+                                                IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
+                                                IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
+                                                IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
+                                                IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
+                                                IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
+                                        }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
+                                } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
+
+                                Device(COPR) {
+                                        Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
+                                        Name(_CRS, ResourceTemplate() {
+                                                IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
+                                                IRQNoFlags(){13}
+                                        })
+                                } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
+
+                                Device (PS2M) {
+                                        Name (_HID, EisaId ("PNP0F13"))
+                                        Name (_CRS, ResourceTemplate () {
+                                                IRQNoFlags () {12}
+                                        })
+                                        Method (_STA, 0)        {
+                                                And (FLG0, 0x04, Local0)
+                                                If (LEqual (Local0, 0x04)) {
+                                                        Return (0x0F)
+                                                } Else {
+                                                        Return (0x00)
+                                                }
+                                        }
+                                }
+
+                                Device (PS2K) {
+                                        Name (_HID, EisaId ("PNP0303"))
+                                        Name (_CRS, ResourceTemplate () {
+                                                IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+                                                IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+                                                IRQNoFlags () {1}
+                                        })
+                                }
+                        } /* end LIBR */
+
+                        Device(STCR) {
+                                Name(_ADR, 0x00110000)
+                                #include "acpi/sata.asl"
+                        } /* end STCR */
+
+                        /* Primary (and only) IDE channel */
+                        Device(IDEC) {
+                                Name(_ADR, 0x00140001)
+                                #include "acpi/ide.asl"
+                        } /* end IDEC */
+
+                        Device(HPET) {
+                                Name(_HID,EISAID("PNP0103"))
+                                Name(CRS, ResourceTemplate() {
+                                        IRQNoFlags() {0}
+                                        IRQNoFlags() {8}
+                                        Memory32Fixed(ReadOnly, 0xFED00000, 0x00000400)
+                                })
+                                Method(_STA, 0) {
+                                        If(LAnd(HPAD, 0xFFFFFF00)) {
+                                                Return(0x0F)
+                                        }
+                                        Return(0x0)
+                                }
+                                Method(_CRS, 0) {
+                                        CreateDWordField(CRS, 0x0A, HPEB)
+                                        Store(HPAD, Local0)
+                                        And(Local0, 0xFFFFFFC0, HPEB)
+                                        Return(CRS)
+                                }
+                        } /* End Device(_SB.PCI0.HPET) */
+
+                        Name(CRES, ResourceTemplate() {
+                                IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
+
+                                WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                                        0x0000,                 /* address granularity */
+                                        0x0000,                 /* range minimum */
+                                        0x0CF7,                 /* range maximum */
+                                        0x0000,                 /* translation */
+                                        0x0CF8                  /* length */
+                                )
+
+                                WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                                        0x0000,                 /* address granularity */
+                                        0x0D00,                 /* range minimum */
+                                        0xFFFF,                 /* range maximum */
+                                        0x0000,                 /* translation */
+                                        0xF300                  /* length */
+                                )
+
+                                /* memory space for PCI BARs below 4GB */
+                                Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+                        }) /* End Name(_SB.PCI0.CRES) */
+
+                        Method(_CRS, 0) {
+                                /* DBGO("\\_SB\\PCI0\\_CRS\n") */
+                                CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+                                CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+                                Store(\_SB.PCI0.TOM1, MM1B)
+                                Subtract(PCBA, MM1B, MM1L)
+
+                                Return(CRES) /* note to change the Name buffer */
+                        } /* end of Method(_SB.PCI0._CRS) */
+                } /* End Device(PCI0)  */
+
+                Device(PWRB) {  /* Start Power button device */
+                        Name(_HID, EISAID("PNP0C0C"))
+                        Name(_UID, 0xAA)
+                        Name(_STA, 0x0B) /* sata is invisible */
+                }
+        } /* End \_SB scope */
+}
+/* End of ASL file */
diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c
new file mode 100644
index 0000000..baf0328
--- /dev/null
+++ b/src/mainboard/amd/dinar/fadt.c
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ */
+
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include "Platform.h" /*sb700 platform header*/
+
+#ifndef ACPI_BLK_BASE
+#define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
+#endif
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = 244;
+	header->revision = 1;
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32) facs;
+	fadt->dsdt = (u32) dsdt;
+	/* 3=Workstation,4=Enterprise Server, 7=Performance Server */
+	fadt->preferred_pm_profile = 0x03;
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0: */
+	fadt->smi_cmd = 0;
+	fadt->acpi_enable = 0xf0;
+	fadt->acpi_disable = 0xf1;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0xe2;
+
+	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
+	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
+	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+
+	fadt->cst_cnt = 0xe3;
+	fadt->p_lvl2_lat = 101;
+	fadt->p_lvl3_lat = 1001;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;
+	fadt->day_alrm = 0;	/* 0x7d these have to be */
+	fadt->mon_alrm = 0;	/* 0x7e added to cmos.layout */
+	fadt->century = 0;	/* 0x7f to make rtc alrm work */
+	fadt->iapc_boot_arch = 0x3;	/* See table 5-11 */
+	fadt->flags = 0x0001c1a5;/* 0x25; */
+
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (u32) facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (u32) dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}
diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c
new file mode 100644
index 0000000..f66e92c
--- /dev/null
+++ b/src/mainboard/amd/dinar/get_bus_conf.c
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/amd/amdfam15.h>
+#include "agesawrapper.h"
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
+
+
+/* Global variables for MB layouts and these will be shared by irqtable mptable
+ * and acpi_tables busnum is default.
+ */
+u8 bus_isa;
+u8 bus_sb700[2];
+u8 bus_rd890[14];
+
+/*
+ * Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ * You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
+u32 pci1234x[] = {
+	0x0000ff0,
+};
+
+/*
+ * HT Chain device num, actually it is unit id base of every ht device in chain,
+ * assume every chain only have 4 ht device at most
+ */
+u32 hcdnx[] = {
+	0x20202020,
+};
+
+u32 bus_type[256];
+
+u32 sbdn_sb700;
+u32 sbdn_rd890;
+
+static u32 get_bus_conf_done = 0;
+
+
+
+
+void get_bus_conf(void)
+{
+	u32 status;
+
+	device_t dev;
+	int i, j;
+
+	if (get_bus_conf_done == 1)
+		return;   /* do it only once */
+
+	get_bus_conf_done = 1;
+
+	printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
+	/*
+	 * This is the call to AmdInitLate.  It is really in the wrong place, conceptually,
+	 * but functionally within the coreboot model, this is the best place to make the
+	 * call.  The logically correct place to call AmdInitLate is after PCI scan is done,
+	 * after the decision about S3 resume is made, and before the system tables are
+	 * written into RAM.  The routine that is responsible for writing the tables is
+	 * "write_tables", called near the end of "hardwaremain".  There is no platform
+	 * specific entry point between the S3 resume decision point and the call to
+	 * "write_tables", and the next platform specific entry points are the calls to
+	 * the ACPI table write functions.  The first of ose would seem to be the right
+	 * place, but other table write functions, e.g. the PIRQ table write function, are
+	 * called before the ACPI tables are written.  This routine is called at the beginning
+	 * of each of the write functions called prior to the ACPI write functions, so this
+	 * becomes the best place for this call.
+	 */
+	status = agesawrapper_amdinitlate();
+	if(status) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
+
+	sbdn_sb700 = 0;
+
+	for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) {
+		bus_sb700[i] = 0;
+	}
+	for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) {
+		bus_rd890[i] = 0;
+	}
+
+	for (i = 0; i < 256; i++) {
+		bus_type[i] = 0; /* default ISA bus. */
+	}
+
+
+	bus_type[0] = 1;  /* pci */
+
+	bus_rd890[0] = (pci1234x[0] >> 16) & 0xff;
+	bus_sb700[0] = bus_rd890[0];
+
+	/* sb700 */
+	dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
+
+
+
+	if (dev) {
+		bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+		bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+		bus_isa++;
+		for (j = bus_sb700[1]; j < bus_isa; j++)
+			bus_type[j] = 1;
+	}
+
+	/* rd890 */
+	for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) {
+		dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0));
+		if (dev) {
+			bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+			if(255 != bus_rd890[i]) {
+				bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+				bus_isa++;
+				bus_type[bus_rd890[i]] = 1; /* PCI bus. */
+			}
+		}
+	}
+
+
+	/* I/O APICs:   APIC ID Version State   Address */
+	bus_isa = 10;
+
+#if CONFIG_AMD_SB_CIMX
+//	sb_After_Pci_Init();
+//	sb_Late_Post();
+#endif
+	printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
+}
diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c
new file mode 100644
index 0000000..f18c09d
--- /dev/null
+++ b/src/mainboard/amd/dinar/gpio.c
@@ -0,0 +1,482 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "Filecode.h"
+#include "Hudson-2.h"
+#include "AmdSbLib.h"
+#include "gpio.h"
+
+#define FILECODE UNASSIGNED_FILE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef SB_GPIO_REG01
+#define SB_GPIO_REG01   1
+#endif
+
+#ifndef SB_GPIO_REG07
+#define SB_GPIO_REG07   7
+#endif
+
+#ifndef SB_GPIO_REG25
+#define SB_GPIO_REG25   25
+#endif
+
+#ifndef SB_GPIO_REG26
+#define SB_GPIO_REG26   26
+#endif
+
+#ifndef SB_GPIO_REG27
+#define SB_GPIO_REG27   27
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+void gpioEarlyInit (void);
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+void
+gpioEarlyInit(
+		void
+	     )
+{
+	u8  Flags;
+	u8	Data8 = 0;
+	u8	StripInfo = 0;
+	u8	BoardType = 1;
+	u8	RegIndex8 = 0;
+	u8	boardRevC = 0x2;
+	u16	Data16 = 0;
+	u32	Index = 0;
+	u32	AcpiMmioAddr = 0;
+	u32	GpioMmioAddr = 0;
+	u32	IoMuxMmioAddr = 0;
+	u32	MiscMmioAddr = 0;
+	u32	SmiMmioAddr = 0;
+	u32	andMask32 = 0;
+
+	// Enable HUDSON MMIO Base (AcpiMmioAddr)
+	ReadPMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+	Data8 |= BIT0;
+	WritePMIO (SB_PMIOA_REG24, AccWidthUint8, &Data8);
+	// Get HUDSON MMIO Base (AcpiMmioAddr)
+	ReadPMIO (SB_PMIOA_REG24 + 3, AccWidthUint8, &Data8);
+	Data16 = Data8 << 8;
+	ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint8, &Data8);
+	Data16 |= Data8;
+	AcpiMmioAddr = (u32)Data16 << 16;
+	GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
+	IoMuxMmioAddr = AcpiMmioAddr + IOMUX_BASE;
+	MiscMmioAddr =  AcpiMmioAddr + MISC_BASE;
+	Data8 = Mmio8_G (MiscMmioAddr, SB_MISC_REG80);
+	if ((Data8 & BIT4) == 0) {
+		BoardType = 0; // external clock board
+	}
+	Data8 = Mmio8_G (GpioMmioAddr, GPIO_30);
+	StripInfo = (Data8 & BIT7) >> 7;
+	Data8 = Mmio8_G (GpioMmioAddr, GPIO_31);
+	StripInfo |= (Data8 & BIT7) >> 6;
+	if (StripInfo < boardRevC) { 		// for old board. Rev B
+		Mmio8_And_Or (IoMuxMmioAddr, GPIO_111, 0x00, 3);		// function 3
+		Mmio8_And_Or (IoMuxMmioAddr, GPIO_113, 0x00, 0);		// function 0
+	}
+	for (Index = 0; Index < MAX_GPIO_NO; Index++) {
+		if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) {
+			if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) {
+				// Configure multi-funtion
+				Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio));
+			}
+			// Configure GPIO
+			if(!((gpio_table[Index].NonGpioGevent & NonGpio))) {
+				Mmio8_And_Or (GpioMmioAddr, Index, 0xDF, gpio_table[Index].type);
+				Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value);
+			}
+			if (Index == GPIO_65) {
+				if ( BoardType == 0 ) {
+					Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3);		// function 3
+				}
+			}
+		}
+		// Configure GEVENT
+		if ((Index >= GEVENT_00) && (Index <= GEVENT_23) && ((gevent_table[Index - GEVENT_00].EventEnable))) {
+			SmiMmioAddr = AcpiMmioAddr + SMI_BASE;
+
+			andMask32 = ~(1 << (Index - GEVENT_00));
+
+			//EventEnable: 0-Disable, 1-Enable
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_EVENT_ENABLE, andMask32, (gevent_table[Index - GEVENT_00].EventEnable << (Index - GEVENT_00)));
+
+			//SciTrig: 0-Falling Edge, 1-Rising Edge
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCITRIG, andMask32, (gevent_table[Index - GEVENT_00].SciTrig << (Index - GEVENT_00)));
+
+			//SciLevl: 0-Edge trigger, 1-Level Trigger
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCILEVEL, andMask32, (gevent_table[Index - GEVENT_00].SciLevl << (Index - GEVENT_00)));
+
+			//SmiSciEn: 0-Not send SMI, 1-Send SMI
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMISCIEN, andMask32, (gevent_table[Index - GEVENT_00].SmiSciEn << (Index - GEVENT_00)));
+
+			//SciS0En: 0-Disable, 1-Enable
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIS0EN, andMask32, (gevent_table[Index - GEVENT_00].SciS0En << (Index - GEVENT_00)));
+
+			//SciMap: 00000b ~ 11111b
+			RegIndex8=(u8)((Index - GEVENT_00) >> 2);
+			Data8=(u8)(((Index - GEVENT_00) & 0x3) * 8);
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SCIMAP0+RegIndex8, ~(GEVENT_SCIMASK << Data8), (gevent_table[Index - GEVENT_00].SciMap << Data8));
+
+			//SmiTrig: 0-Active Low, 1-Active High
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMITRIG, ~(gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)), (gevent_table[Index - GEVENT_00].SmiTrig << (Index - GEVENT_00)));
+
+			//SmiControl: 0-Disable, 1-SMI, 2-NMI, 3-IRQ13
+			RegIndex8=(u8)((Index - GEVENT_00) >> 4);
+			Data8=(u8)(((Index - GEVENT_00) & 0xF) * 2);
+			Mmio32_And_Or     (SmiMmioAddr, SMIREG_SMICONTROL0+RegIndex8, ~(SMICONTROL_MASK << Data8), (gevent_table[Index - GEVENT_00].SmiControl << Data8));
+		}
+	}
+
+	//
+	// config MXM
+	//	GPIO9: Input for MXM_PRESENT2#
+	//	GPIO10: Input for MXM_PRESENT1#
+	//	GPIO28: Input for MXM_PWRGD
+	//	GPIO35: Output for MXM Reset
+	//	GPIO45: Output for MXM Power Enable, active HIGH
+	//	GPIO55: Output for MXM_PWR_EN, 1 - Enable, 0 - Disable
+	//	GPIO32: Output for PCIE_SW, 1 - MXM, 0 - LASSO
+	//
+	// set INTE#/GPIO32 as GPO for PCIE_SW
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG32, AccWidthUint8, 00, 0x1);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x03, 0);       // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG32, AccWidthUint8, 0x23, BIT3+BIT6);
+
+	// set SATA_IS4#/FANOUT3/GPIO55 as GPO for MXM_PWR_EN
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG55, AccWidthUint8, 00, 0x2);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x03, 0);       // GPO
+
+	// set AD9/GPIO9 as GPI for MXM_PRESENT2#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG09, AccWidthUint8, 00, 0x1);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x03, BIT5);    // GPI
+
+	// set AD10/GPIO10 as GPI for MXM_PRESENT1#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG10, AccWidthUint8, 00, 0x1);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x03, BIT5);    // GPI
+
+	// set GNT1#/GPIO44 as GPO for MXM Reset
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG44, AccWidthUint8, 00, 0x1);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x03, 0);       // GPO
+
+	// set GNT2#/SD_LED/GPO45 as GPO for MXM Power Enable
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG45, AccWidthUint8, 00, 0x2);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x03, 0);       // GPO
+
+	// set AD28/GPIO28 as GPI for MXM_PWRGD
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG28, AccWidthUint8, 00, 0x1);      // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x03, BIT5);    // GPI
+
+	// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=0 (Output LOW)
+	RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0x23, BIT3);
+	RWMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, 0x23, BIT3);
+	RWMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, 0x23, BIT3);
+	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0x23, BIT3);
+	RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0x23, BIT3);
+	RWMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, 0x23, BIT3);
+
+	//
+	// [GPIO] STRP_DATA: 1->RS880M VCC_NB 1.0V. 0->RS880M VCC_NB 1.1V (Default).
+	//
+	//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG42, (BLReadNBMISC_Dword (ATI_MISC_REG42) | BIT20));
+	//Fusion_Llano BLWriteNBMISC_Dword (ATI_MISC_REG40, (BLReadNBMISC_Dword (ATI_MISC_REG40) & (~BIT20)));
+
+	// check if there any GFX card
+	Flags = 0;
+	// Value32 = MmPci32 (0, SB_ISA_BUS, SB_ISA_DEV, SB_ISA_FUNC, R_SB_ISA_GPIO_CONTROL);
+	// Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG09);
+	ReadMEM (GpioMmioAddr + SB_GPIO_REG09, AccWidthUint8, &Data8);
+	if (!(Data8 & BIT7))
+	{
+		//Data8 = Mmio8 (GpioMmioAddr, SB_GPIO_REG10);
+		ReadMEM (GpioMmioAddr + SB_GPIO_REG10, AccWidthUint8, &Data8);
+		if (!(Data8 & BIT7))
+		{
+			Flags = 1;
+		}
+	}
+	if (  Flags )
+	{
+		// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 0 for reset, ENH164467
+		RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, 0);
+
+		// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
+		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xFF, BIT6);
+
+		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+		SbStall (10000);
+
+		// Write the GPIO55(MXM_PWR_EN) to enable the integrated power module
+		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xFF, BIT6);
+
+		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+		// WAIT POWER READY: GPIO28 (MXM_PWRGD)
+		//while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){}
+		ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+		while (!(Data8 && BIT7))
+		{
+			ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8);
+		}
+		// [GPIO] GPIO44: PE_GPIO0 MXM Reset set to 1 for reset
+		//	RWMEM (GpioMmioAddr + SB_GPIO_REG44, AccWidthUint8, 0xBF, BIT6);
+	}
+	else
+	{
+		// Write the GPIO55(MXM_PWR_EN) to disable the integrated power module
+		RWMEM (GpioMmioAddr + SB_GPIO_REG55, AccWidthUint8, 0xBF, 0);
+
+		//PeiStall (PeiServices, NULL, 100); //delay 100 ms (should be >1ms)
+		SbStall (10000);
+
+		// [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE down
+		RWMEM (GpioMmioAddr + SB_GPIO_REG45, AccWidthUint8, 0xBF, 0);
+	}
+
+	//
+	// APU GPP0: On board LAN
+	//	GPIO25: PCIE_RST#_LAN, LOW active
+	//	GPIO63: LAN_CLKREQ#
+	//	GPIO197: LOM_POWER, HIGH Active
+	//	Clock: GPP_CLK3
+	//
+	// Set EC_PWM0/EC_TIMER0/GPIO197 as GPO for LOM_POWER
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG197, AccWidthUint8, 00, 0x2);         // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, 0);          // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x03, BIT6);       // output HIGH
+	RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+	// Setup AD25/GPIO25 as GPO for PCIE_RST#_LAN:
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG25, AccWidthUint8, 00, 0x1);          // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, 0);           // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x03, BIT6);        // output HIGH
+	RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x63, BIT3);        // pullup DISABLE
+
+
+	// set CLK_REQ3#/SATA_IS1#/GPIO63 as CLK_REQ for LAN_CLKREQ#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG63, AccWidthUint8, 00, 0x0);          // CLK_REQ3#
+	RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0xF0);       // Enable GPP_CLK3
+
+	//
+	// APU GPP1: WUSB
+	//	GPIO1: MPCIE_RST2#, LOW active
+	//	GPIO13: WU_DISABLE#, LOW active
+	//	GPIO177: MPICE_PD2, 1 - DISABLE, 0 - ENABLE (Default)
+	//
+	// Setup VIN2/SATA1_1/GPIO177 as GPO for MPCIE_PD2#: wireless disable
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG177, AccWidthUint8, 00, 0x2);     // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x03, 0);      // output LOW
+	RWMEM (GpioMmioAddr + SB_GPIO_REG177, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
+
+	// Setup AD01/GPIO01 as GPO for MPCIE_RST2#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG01, AccWidthUint8, 00, 0x1);      // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, 0);       // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x03, BIT6);    // output LOW
+	RWMEM (GpioMmioAddr + SB_GPIO_REG01, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+	// Setup AD13/GPIO13 as GPO for WU_DISABLE#: disable WUSB
+	//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG13, AccWidthUint8, 00, 0x1);      // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, 0);       // GPO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x03, BIT6);    // output HIGH
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG13, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+	//
+	// APU GPP2: WWAN
+	//	GPIO0: MPCIE_RST1#, LOW active
+	//	GPIO14: WP_DISABLE#, LOW active
+	//	GPIO176: MPICE_PD1, 1 - DISABLE, 0 - ENABLE (Default)
+	//
+	// Set VIN1/GPIO176 as GPO for MPCIE_PD1# for wireless disable
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG176, AccWidthUint8, 00, 0x1);     // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x03, 0);      // output LOW
+	RWMEM (GpioMmioAddr + SB_GPIO_REG176, AccWidthUint8, 0x63, BIT3);   // pullup DISABLE
+
+	// Set AD00/GPIO00 as GPO for MPCIE_RST1#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG00, AccWidthUint8, 00, 0x1);      // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, 0);       // GPO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x03, BIT6);    // output LOW
+	RWMEM (GpioMmioAddr + SB_GPIO_REG00, AccWidthUint8, 0x63, BIT3);    // pullup DISABLE
+
+	// Set AD14/GPIO14 as GPO for WP_DISABLE#: disable WWAN
+	//		RWMEM (IoMuxMmioAddr + SB_GPIO_REG14, AccWidthUint8, 00, 0x1);      // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, 0);       // GPO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x03, BIT6);
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG14, AccWidthUint8, 0x63, BIT3);
+
+	//
+	// APU GPP3: 1394
+	//	GPIO59: Power control, HIGH active
+	//	GPIO27: PCIE_RST#_1394, LOW active
+	//	GPIO41: CLKREQ#
+	//	Clock: GPP_CLK8
+	//
+	// Setup SATA_IS5#/FANIN3/GPIO59 as GPO for 1394_ON:
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG59, AccWidthUint8, 00, 0x2);         // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, 0);          // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);       // output HIGH
+	RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+	// Setup AD27/GPIO27 as GPO for MPCIE_RST#_1394
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG27, AccWidthUint8, 00, 0x1);         // GPIO
+	//		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, 0);          // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);       // output HIGH
+	RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+
+	// set REQ2#/CLK_REQ2#/GPIO41 as CLK_REQ#
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG41, AccWidthUint8, 00, 0x1);         // CLK_REQ2#
+
+	// set AZ_SDIN3/GPIO170 as GPO for GPIO_GATE_C
+	RWMEM (IoMuxMmioAddr + SB_GPIO_REG170, AccWidthUint8, 00, 0x1);        // GPIO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, 0);         // GPO
+	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x03, BIT6);       // output HIGH
+	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0x63, BIT3);       // pullup DISABLE
+	//  To fix glitch issue
+	RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
+	//
+	// Enable/Disable OnBoard LAN
+	//
+	if (!CONFIG_ONBOARD_LAN)
+	{ // 1 - DISABLED
+		RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0xBF, 0);      // LOM_POWER off
+		RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG63, AccWidthUint8, 0xFF, BIT3);    // PULL UP - DISABLED
+		RWMEM (MiscMmioAddr + SB_MISC_REG00+1, AccWidthUint8, 0x0F, 0);     // Disable GPP_CLK3
+	}
+	//		else
+	//		{ // 0 - AUTO
+	//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable)
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG197, AccWidthUint8, 0x23, BIT3);
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG25, AccWidthUint8, 0x23, BIT3);
+	//		}
+
+
+	//
+	// Enable/Disable 1394
+	//
+	if (!CONFIG_ONBOARD_1394)
+	{ // 1 - DISABLED
+		//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, 0);      // set GPIO_GATE_C to LOW
+		RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0xBF, 0);       // 1394 power off
+		RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG41, AccWidthUint8, 0xFF, BIT3);    // pullup DISABLE
+		RWMEM (MiscMmioAddr + SB_MISC_REG04, AccWidthUint8, 0xF0, 0);       // DISABLE GPP_CLK8
+		//			RWMEM (GpioMmioAddr + SB_GPIO_REG170, AccWidthUint8, 0xBF, BIT6);   // set GPIO_GATE_C to HIGH
+	}
+	//		else
+	//		{ // 0 - AUTO
+	//			// set BIT3=1 (PULLUP disable), BIT4=0 (PULLDOWN Disable), BIT6=1 (output HIGH)
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x03, BIT6);
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG27, AccWidthUint8, 0x63, BIT3);
+	//
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x03, BIT6);
+	//			RWMEM (GpioMmioAddr + SB_GPIO_REG59, AccWidthUint8, 0x63, BIT3);
+	//		}
+
+	//
+	// external USB 3.0 control:
+	//    amdExternalUSBController: CMOS, 0 - AUTO, 1 - DISABLE
+	//                      GPIO26: PCIE_RST#_USB3.0
+	//                      GPIO46: PCIE_USB30_CLKREQ#
+	//                     GPIO200: NEC_USB30_PWR_EN, 0 - OFF, 1 - ON
+	//                       Clock: GPP_CLK7
+	//                     GPIO172 used as FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+	//	if ((Amd_SystemConfiguration.XhciSwitch == 1) || (SystemConfiguration.amdExternalUSBController == 1)) {
+	// disable Onboard NEC USB3.0 controller
+	if (!CONFIG_ONBOARD_USB30) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG200, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG26, AccWidthUint8, 0xBF, 0);
+		RWMEM (GpioMmioAddr + SB_GPIO_REG46, AccWidthUint8, 0xFF, BIT3);   // PULL_UP DISABLE
+		RWMEM (MiscMmioAddr + SB_MISC_REG00+3, AccWidthUint8, 0x0F, 0);    // DISABLE GPP_CLK7
+		RWMEM (GpioMmioAddr + SB_GPIO_REG172, AccWidthUint8, 0xBF, 0);  // FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+	}
+	//	}
+
+	//
+	// BlueTooth control: BT_ON
+	//    amdBlueTooth: CMOS, 0 - AUTO, 1 - DISABLE
+	//          GPIO07: BT_ON, 0 - OFF, 1 - ON
+	//
+	if (!CONFIG_ONBOARD_BLUETOOTH) {
+		//-	if (SystemConfiguration.amdBlueTooth == 1) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG07, AccWidthUint8, 0xBF, 0);
+		//-	}
+	}
+
+	//
+	// WebCam control:
+	//    amdWebCam: CMOS, 0 - AUTO, 1 - DISABLE
+	//       GPIO34: WEBCAM_ON#, 0 - ON, 1 - OFF
+	//
+	if (!CONFIG_ONBOARD_WEBCAM) {
+		//-	if (SystemConfiguration.amdWebCam == 1) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG34, AccWidthUint8, 0xBF, BIT6);
+		//-	}
+	}
+
+	//
+	// Travis enable:
+	//    amdTravisCtrl: CMOS, 0 - DISABLE, 1 - ENABLE
+	//           GPIO66: TRAVIS_EN#, 0 - ENABLE, 1 - DISABLE
+	//
+	if (!CONFIG_ONBOARD_TRAVIS) {
+		//-	if (SystemConfiguration.amdTravisCtrl == 0) {
+		RWMEM (GpioMmioAddr + SB_GPIO_REG66, AccWidthUint8, 0xBF, BIT6);
+		//-	}
+	}
+
+	//
+	// Disable Light Sensor if needed
+	//
+	if (CONFIG_ONBOARD_LIGHTSENSOR) {
+		//-    if (SystemConfiguration.amdLightSensor == 1) {
+		RWMEM (IoMuxMmioAddr + SB_GEVENT_REG12, AccWidthUint8, 0x00, 0x1);
+		//-    }
+	}
+
+}
+
+
diff --git a/src/mainboard/amd/dinar/gpio.h b/src/mainboard/amd/dinar/gpio.h
new file mode 100644
index 0000000..c936e50
--- /dev/null
+++ b/src/mainboard/amd/dinar/gpio.h
@@ -0,0 +1,2329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include <stdint.h>
+#include <cbtypes.h>
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define Mmio_Address( BaseAddr, Register ) \
+	( (UINTN)BaseAddr + \
+	  (UINTN)(Register) \
+	)
+
+#define Mmio32_Ptr( BaseAddr, Register ) \
+	( (volatile u32 *)Mmio_Address( BaseAddr, Register ) )
+
+#define Mmio32_G( BaseAddr, Register ) \
+	*Mmio32_Ptr( BaseAddr, Register )
+
+#define Mmio32_And_Or( BaseAddr, Register, AndData, OrData ) \
+	Mmio32_G( BaseAddr, Register ) = \
+(u32) ( \
+		( Mmio32_G( BaseAddr, Register ) & \
+		  (u32)(AndData) \
+		) | \
+		(u32)(OrData) \
+      )
+
+#define Mmio8_Ptr( BaseAddr, Register ) \
+	( (volatile u8 *)Mmio_Address( BaseAddr, Register ) )
+
+#define Mmio8_G( BaseAddr, Register ) \
+	*Mmio8_Ptr( BaseAddr, Register )
+
+#define Mmio8_And_Or( BaseAddr, Register, AndData, OrData ) \
+	Mmio8_G( BaseAddr, Register ) = \
+(u8) ( \
+		( Mmio8_G( BaseAddr, Register ) & \
+		  (u8)(AndData) \
+		) | \
+		(u8)(OrData) \
+     )
+
+#define SMIREG_EVENT_ENABLE 0x04
+#define SMIREG_SCITRIG      0x08
+#define SMIREG_SCILEVEL     0x0C
+#define SMIREG_SMISCIEN     0x14
+#define SMIREG_SCIS0EN      0x20
+#define SMIREG_SCIMAP0      0x40
+#define SMIREG_SCIMAP1      0x44
+#define SMIREG_SCIMAP2      0x48
+#define SMIREG_SCIMAP3      0x4C
+#define SMIREG_SCIMAP4      0x50
+#define SMIREG_SCIMAP5      0x54
+#define SMIREG_SCIMAP6      0x58
+#define SMIREG_SCIMAP7      0x5C
+#define SMIREG_SCIMAP8      0x60
+#define SMIREG_SCIMAP9      0x64
+#define SMIREG_SCIMAP10     0x68
+#define SMIREG_SCIMAP11     0x6C
+#define SMIREG_SCIMAP12     0x70
+#define SMIREG_SCIMAP13     0x74
+#define SMIREG_SCIMAP14     0x78
+#define SMIREG_SCIMAP15     0x7C
+#define SMIREG_SMITRIG      0x98
+#define SMIREG_SMICONTROL0  0xA0
+#define SMIREG_SMICONTROL1  0xA4
+
+#define FUNCTION0           0
+#define FUNCTION1           1
+#define FUNCTION2           2
+#define FUNCTION3           3
+#define NonGpio             0x80				// BIT7
+
+// S0-domain General Purpose I/O: GPIO 00~67
+#define GPIO_00_SELECT      FUNCTION1+NonGpio   // MPCIE_RST1# for J3703, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_01_SELECT      FUNCTION1+NonGpio   // MPCIE_RST2# for J3711, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_02_SELECT      FUNCTION1           // MPCIE_RST0# for J3700, LOW ACTIVE, HIGH DEFAULT
+#define GPIO_03_SELECT      FUNCTION1+NonGpio   // NOT USED
+#define GPIO_04_SELECT      FUNCTION1+NonGpio   // x1 gpp reset, for J3701, low active, HIGH DEFAULT
+#define GPIO_05_SELECT      FUNCTION1+NonGpio   // express card reset, for J2500,  low active, HIGH DEFAULT
+#define GPIO_06_SELECT      FUNCTION0+NonGpio   //NOT USED
+#define GPIO_07_SELECT      FUNCTION1           // BT_ON, 1: BT ON(DEFAULT); 0: BT OFF
+#define GPIO_08_SELECT      FUNCTION1           // PEX_STD_SW#, 1:Low Level Mode(default); 0:Standard(desktop) Swing Level
+#define GPIO_09_SELECT      FUNCTION1+NonGpio   // MXM_PRESENT2#, INPUT, LOW MEANS MXM IS INSTALLED
+#define GPIO_10_SELECT      FUNCTION1+NonGpio   // MXM_PRESENT1#, INPUT, LOW MEANS MXM IS INSTALLED
+#define GPIO_11_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_12_SELECT      FUNCTION1           // WL_DISABLE#, DISABLE THE WALN IN J3702
+#define GPIO_13_SELECT      FUNCTION1           // WU_DISABLE#, DISABLE THE WUSB IN J3711
+#define GPIO_14_SELECT      FUNCTION1           // WP_DISABLE, DISABLE THE WWAN IN J3703
+#define GPIO_15_SELECT      FUNCTION1+NonGpio   // NOT USED, //FUNCTION1, Reset_CEC# Low Active, High default
+#define GPIO_16_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_17_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_18_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_19_SELECT      FUNCTION1           // For LASSO_DET# detection when Gevent14# is asserted.
+#define GPIO_20_SELECT      FUNCTION1           // PX_MUX for DOCKING card, PX MUX selection in mux mode. dGPU enable with high(option)
+#define GPIO_21_SELECT      FUNCTION1           // DOCK_MUX for DCKING card, MUX selection output. Docking display enabled when high(option)
+#define GPIO_22_SELECT      FUNCTION1           // SB_PWR_LV, INDICATE TO THE MXM THE SYSTEM IS IN LOW BATTERY MODE
+//      1:BATTERY IS FINE(DEFAULT)
+//      0:BATTERY IS LOW
+#define GPIO_23_SELECT      FUNCTION1	        // CODEC_ON.1: CODEC ON (default)0: CODEC OFF
+#define GPIO_24_SELECT      FUNCTION1           // Travis reset,Low active High default
+#define GPIO_25_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for LAN (AND gate with PCIE_RST#); default high
+#define GPIO_26_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for USB3.0 (AND gate with PCIE_RST#); default high
+#define GPIO_27_SELECT      FUNCTION1+NonGpio   // PCIE_RST# for 1394 (AND gate with PCIE_RST#); default high
+#define GPIO_28_SELECT      FUNCTION1           // MXM PWRGD INDICATOR, INPUT
+#define GPIO_29_SELECT      FUNCTION1           // MEM HOT, LOW ACTIVE, OUTPUT
+#define GPIO_30_SELECT      FUNCTION1           // INPUT, DEFINE THE BOARD REVISION 0
+#define GPIO_31_SELECT      FUNCTION1           // INPUT, DEFINE THE BOARD REVISION 1
+//      00 - REVA
+//      01 - REVB
+//      10 - REVC
+//      11 - REVD
+#define GPIO_32_SELECT      FUNCTION1+NonGpio   // PCIE_SW - HIGH:MXM; LOW:LASSO
+#define GPIO_33_SELECT      FUNCTION1           // USB3.0 DETECT of Express Card:USB3.0_DET#, Low active.
+//      0:USB3.0 I/F in Express CARD
+//      1:PCIE I/F  in Express CARD detection
+#define GPIO_34_SELECT      FUNCTION1           // WEBCAM_ON#. 0: ON (default) 1: OFF
+#define GPIO_35_SELECT      FUNCTION1           // ODD_DA_INTH#
+#define GPIO_36_SELECT      FUNCTION0+NonGpio   // PCICLK FOR KBC
+#define GPIO_37_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_38_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_39_SELECT      FUNCTION0+NonGpio   // NOT USED
+#define GPIO_40_SELECT      FUNCTION1           // For DOCK# detection when Gevent14# is asserted.
+#define GPIO_41_SELECT      FUNCTION1+NonGpio   // 1394 CLK REQ#
+#define GPIO_42_SELECT      FUNCTION1+NonGpio   // X4 GPP CLK REQ#
+#define GPIO_43_SELECT      FUNCTION0+NonGpio   // SMBUS0, CLOCK
+#define GPIO_44_SELECT      FUNCTION1+NonGpio   // PEGPIO0, RESET THE MXM MODULE
+#define GPIO_45_SELECT      FUNCTION2+NonGpio   // PEGPIO1, 1:MXM IS POWER ON; 0:MXM IS OFF
+#define GPIO_46_SELECT      FUNCTION1+NonGpio   // USB3.0_CLKREQ#
+#define GPIO_47_SELECT      FUNCTION0+NonGpio   // SMBUS0, DATA
+#define GPIO_48_SELECT      FUNCTION0+NonGpio   // SERIRQ
+#define GPIO_49_SELECT      FUNCTION0+NonGpio   // LDRQ#1
+#define GPIO_50_SELECT      FUNCTION2           // SMARTVOLTAGE TO CONTROL THE 5V - 1:5V; 0:4.56V
+#define GPIO_51_SELECT      FUNCTION0+NonGpio   // back-up for SMARTVOLTAGE1
+#define GPIO_52_SELECT      FUNCTION0+NonGpio   // CPU FAN OUT
+#define GPIO_53_SELECT      FUNCTION1           // ODD POWER ENABLE, HIGH ACTIVE
+#define GPIO_54_SELECT      FUNCTION0+NonGpio   // SB_PROCHOT, OUTPUT, LOW ACTIVE
+#define GPIO_55_SELECT      FUNCTION2+NonGpio   // MXM POWER ENABLE(POWER ON MODULE)
+//      1:ENABLE; 0:DISABLE
+// DEFAULT VALUE DEPENDS ON GPIO 9 AND 10
+#define GPIO_56_SELECT      FUNCTION0+NonGpio   //HDD2_POWER/HDD0_POWER/CPU FAN ;CPU FAN
+#define GPIO_57_SELECT      FUNCTION1           // HDD0_POWER
+#define GPIO_58_SELECT      FUNCTION1           // HDD2_POWER
+#define GPIO_59_SELECT      FUNCTION2+NonGpio   // 1394 POWER, OUTPUT, HIGH ACTIVE
+#define GPIO_60_SELECT      FUNCTION0+NonGpio   // EXPCARD_CLKREQ#
+#define GPIO_61_SELECT      FUNCTION0+NonGpio   // PE0_CLKREQ#, FROM J3700
+#define GPIO_62_SELECT      FUNCTION0+NonGpio   // PE2_CLKREQ#, FROM J3711
+#define GPIO_63_SELECT      FUNCTION0+NonGpio   // LAN_CLKREQ#
+#define GPIO_64_SELECT      FUNCTION0+NonGpio   // PE1_CLKREQ#, FROM J3703
+#define GPIO_65_SELECT      FUNCTION0+NonGpio   // MXM CLK REQ#, FROM MXM
+#define GPIO_66_SELECT      FUNCTION1           // USED AS TRAVIS_EN#; 0:ENABLE as default
+#define GPIO_67_SELECT      FUNCTION0+NonGpio   // USED AS SATA_ACT#
+#define GPIO_68_SELECT      FUNCTION0+NonGpio
+#define GPIO_69_SELECT      FUNCTION0+NonGpio
+#define GPIO_70_SELECT      FUNCTION0+NonGpio
+#define GPIO_71_SELECT      FUNCTION0+NonGpio
+#define GPIO_72_SELECT      FUNCTION0+NonGpio
+#define GPIO_73_SELECT      FUNCTION0+NonGpio
+#define GPIO_74_SELECT      FUNCTION0+NonGpio
+#define GPIO_75_SELECT      FUNCTION0+NonGpio
+#define GPIO_76_SELECT      FUNCTION0+NonGpio
+#define GPIO_77_SELECT      FUNCTION0+NonGpio
+#define GPIO_78_SELECT      FUNCTION0+NonGpio
+#define GPIO_79_SELECT      FUNCTION0+NonGpio
+#define GPIO_80_SELECT      FUNCTION0+NonGpio
+#define GPIO_81_SELECT      FUNCTION0+NonGpio
+#define GPIO_82_SELECT      FUNCTION0+NonGpio
+#define GPIO_83_SELECT      FUNCTION0+NonGpio
+#define GPIO_84_SELECT      FUNCTION0+NonGpio
+#define GPIO_85_SELECT      FUNCTION0+NonGpio
+#define GPIO_86_SELECT      FUNCTION0+NonGpio
+#define GPIO_87_SELECT      FUNCTION0+NonGpio
+#define GPIO_88_SELECT      FUNCTION0+NonGpio
+#define GPIO_89_SELECT      FUNCTION0+NonGpio
+#define GPIO_90_SELECT      FUNCTION0+NonGpio
+#define GPIO_91_SELECT      FUNCTION0+NonGpio
+#define GPIO_92_SELECT      FUNCTION0+NonGpio
+#define GPIO_93_SELECT      FUNCTION0+NonGpio
+#define GPIO_94_SELECT      FUNCTION0+NonGpio
+#define GPIO_95_SELECT      FUNCTION0+NonGpio
+// GEVENT 00~23 are mapped to GPIO 96~119
+#define GPIO_96_SELECT      FUNCTION0           // GA20IN/GEVENT0#
+#define GPIO_97_SELECT      FUNCTION0           // KBRST#/GEVENT1#
+#define GPIO_98_SELECT      FUNCTION0           // THRMTRIP#/SMBALERT#/GEVENT2# -> APU_THERMTRIP
+#define GPIO_99_SELECT      FUNCTION1           // LPC_PME#/GEVENT3# -> EC_SCI#
+#define GPIO_100_SELECT     FUNCTION2           // PCIE_RST2#/PCI_PME#/GEVENT4# -> APU_MEMHOT#
+#define GPIO_101_SELECT     FUNCTION1           // LPC_PD#/GEVENT5# -> hotplug of express card, low active
+#define GPIO_102_SELECT     FUNCTION0+NonGpio   // USB_OC6#/IR_TX1/ GEVENT6# -> NOT USED,
+// there is a confliction to IR function when this pin is as a GEVENT.
+#define GPIO_103_SELECT     FUNCTION0+NonGpio   // DDR3_RST#/GEVENT7#/VGA_PD -> VGA_PD,
+// special pin difination for SB700 VGA OUTPUT, high active,
+// VGA power for Hudson-M2 will be down when it was asserted.
+#define GPIO_104_SELECT     FUNCTION0           // WAKE#/GEVENT8# -> WAKEUP, low active
+#define GPIO_105_SELECT     FUNCTION2           // SPI_HOLD/GBE_LED1/GEVENT9# - WF_RADIO (wireless radio)
+#define GPIO_106_SELECT     FUNCTION0           // GBE_LED2/GEVENT10# -> GBE_LED2
+#define GPIO_107_SELECT     FUNCTION0+NonGpio   // GBE_STAT0/GEVENT11# -> GBE_STAT0
+#define GPIO_108_SELECT     FUNCTION2           // USB_OC0#/TRST#/GEVENT12# -> SMBALERT# (Light Sensor), low active
+// [option for SPI_TPM_CS# in Hudson-M2 A12)]
+#define GPIO_109_SELECT     FUNCTION0           // USB_OC1#/TDI/GEVENT13# - USB OC for 0, 1,2,3 & USB_OC expresscard (usb4) &
+//  USB3.0 PORT0,1:low active,disable all usb ports and new card power at a same time
+#define GPIO_110_SELECT     FUNCTION2           // USB_OC2#/TCK/GEVENT14# -> Lasso detect or Dock detect,
+// plus judge GPIO40 and GPIO19 level,low is assert.
+//      LASSO_DET# :0 & GPIO19:0 -----> LASSO is present (default)
+//      DOCK#:0 & GPIO40:0 -----------> DOCK is present(option)
+#define GPIO_111_SELECT     FUNCTION1+NonGpio	// USB_OC3#/AC_PRES/TDO/GEVENT15# -> AC_PRES, high active
+#define GPIO_112_SELECT     FUNCTION2           // USB_OC4#/IR_RX0/GEVENT16# -> ODD_DA, ODD device attention,
+// low active, when it's low, BIOS will enbale ODD_PWR
+#define GPIO_113_SELECT     FUNCTION2			// USB_OC5#/IR_TX0/GEVENT17# -> use TWARN mapping to trigger GEVENT17#
+#define GPIO_114_SELECT     FUNCTION2           // BLINK/USB_OC7#/GEVENT18# -> BLINK
+#define GPIO_115_SELECT     FUNCTION0           // SYS_RESET#/GEVENT19# -> SYS_RST#
+#define GPIO_116_SELECT     FUNCTION0           // R_RX1/GEVENT20# -> IR INPUT
+#define GPIO_117_SELECT     FUNCTION1+NonGpio   // SPI_CS3#/GBE_STAT1/GEVENT21# -> GBE_STAT1
+#define GPIO_118_SELECT     FUNCTION1           // RI#/GEVENT22# -> LID_CLOSED#
+#define GPIO_119_SELECT     FUNCTION0           // LPC_SMI#/GEVENT23# -> EC_SMI
+#define GPIO_120_SELECT     FUNCTION0+NonGpio
+#define GPIO_121_SELECT     FUNCTION0+NonGpio
+#define GPIO_122_SELECT     FUNCTION0+NonGpio
+#define GPIO_123_SELECT     FUNCTION0+NonGpio
+#define GPIO_124_SELECT     FUNCTION0+NonGpio
+#define GPIO_125_SELECT     FUNCTION0+NonGpio
+#define GPIO_126_SELECT     FUNCTION0+NonGpio
+#define GPIO_127_SELECT     FUNCTION0+NonGpio
+#define GPIO_128_SELECT     FUNCTION0+NonGpio
+#define GPIO_129_SELECT     FUNCTION0+NonGpio
+#define GPIO_130_SELECT     FUNCTION0+NonGpio
+#define GPIO_131_SELECT     FUNCTION0+NonGpio
+#define GPIO_132_SELECT     FUNCTION0+NonGpio
+#define GPIO_133_SELECT     FUNCTION0+NonGpio
+#define GPIO_134_SELECT     FUNCTION0+NonGpio
+#define GPIO_135_SELECT     FUNCTION0+NonGpio
+#define GPIO_136_SELECT     FUNCTION0+NonGpio
+#define GPIO_137_SELECT     FUNCTION0+NonGpio
+#define GPIO_138_SELECT     FUNCTION0+NonGpio
+#define GPIO_139_SELECT     FUNCTION0+NonGpio
+#define GPIO_140_SELECT     FUNCTION0+NonGpio
+#define GPIO_141_SELECT     FUNCTION0+NonGpio
+#define GPIO_142_SELECT     FUNCTION0+NonGpio
+#define GPIO_143_SELECT     FUNCTION0+NonGpio
+#define GPIO_144_SELECT     FUNCTION0+NonGpio
+#define GPIO_145_SELECT     FUNCTION0+NonGpio
+#define GPIO_146_SELECT     FUNCTION0+NonGpio
+#define GPIO_147_SELECT     FUNCTION0+NonGpio
+#define GPIO_148_SELECT     FUNCTION0+NonGpio
+#define GPIO_149_SELECT     FUNCTION0+NonGpio
+#define GPIO_150_SELECT     FUNCTION0+NonGpio
+#define GPIO_151_SELECT     FUNCTION0+NonGpio
+#define GPIO_152_SELECT     FUNCTION0+NonGpio
+#define GPIO_153_SELECT     FUNCTION0+NonGpio
+#define GPIO_154_SELECT     FUNCTION0+NonGpio
+#define GPIO_155_SELECT     FUNCTION0+NonGpio
+#define GPIO_156_SELECT     FUNCTION0+NonGpio
+#define GPIO_157_SELECT     FUNCTION0+NonGpio
+#define GPIO_158_SELECT     FUNCTION0+NonGpio
+#define GPIO_159_SELECT     FUNCTION0+NonGpio
+#define GPIO_160_SELECT     FUNCTION0+NonGpio
+
+// S5-domain General Purpose I/O
+#define GPIO_161_SELECT     FUNCTION0+NonGpio   // ROM_RST#
+#define GPIO_162_SELECT     FUNCTION0+NonGpio   // SPI ROM
+#define GPIO_163_SELECT     FUNCTION0+NonGpio   // SPI ROM
+#define GPIO_164_SELECT     FUNCTION0+NonGpio   // SPI ROM
+#define GPIO_165_SELECT     FUNCTION0+NonGpio   // SPI ROM
+#define GPIO_166_SELECT     FUNCTION1+NonGpio   // GBE_STAT2
+#define GPIO_167_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN0
+#define GPIO_168_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN1
+#define GPIO_169_SELECT     FUNCTION0+NonGpio   // AZ_SDATA_IN2
+#define GPIO_170_SELECT     FUNCTION1+NonGpio   // gating the power control signal for ODD, see BIOS requirements doc for detail.
+#define GPIO_171_SELECT     FUNCTION0+NonGpio   // TEMPIN0,
+#define GPIO_172_SELECT     FUNCTION1           // used as FCH_USB3.0PORT_EN# - 0:ENABLE; 1:DISABLE
+#define GPIO_173_SELECT     FUNCTION0+NonGpio   // TEMPIN3
+#define GPIO_174_SELECT     FUNCTION1+NonGpio   // USED AS TALERT#
+#define GPIO_175_SELECT     FUNCTION1           // WLAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_176_SELECT     FUNCTION1+NonGpio   // WWAN, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_177_SELECT     FUNCTION2+NonGpio   // WUSB, WIRELESS DISABLE 1:DISABLE; 0:ENABLE
+#define GPIO_178_SELECT     FUNCTION2           // MEM_1V5
+#define GPIO_179_SELECT     FUNCTION2           // MEM_1V35
+#define GPIO_180_SELECT     FUNCTION0+NonGpio   // Use as VIN VDDIO
+#define GPIO_181_SELECT     FUNCTION0+NonGpio   // Use as VIN VDDR
+#define GPIO_182_SELECT     FUNCTION1+NonGpio   // GBE_LED3
+#define GPIO_183_SELECT     FUNCTION0+NonGpio   // GBE_LED0
+#define GPIO_184_SELECT     FUNCTION1+NonGpio   // USED AS LLB#
+#define GPIO_185_SELECT     FUNCTION0+NonGpio   // USED AS USB
+#define GPIO_186_SELECT     FUNCTION0+NonGpio   // USED AS USB
+#define GPIO_187_SELECT     FUNCTION2           // USED AS AC LED INDICATOR, LOW ACTIVE
+#define GPIO_188_SELECT     FUNCTION2           // default used AS BATT LED INDICATOR, LOW ACTIVE
+// option for HDMI CEC signal OW ACTIVE
+#define GPIO_189_SELECT     FUNCTION1           // USED AS AC_OK RECIEVER, INPUT, low active
+#define GPIO_190_SELECT     FUNCTION1           // USED TO MONITER INTERUPT FROM BATT CHARGER, INPUT
+#define GPIO_191_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, DATA
+#define GPIO_192_SELECT     FUNCTION0+NonGpio   // TOUCH PAD, CLK
+#define GPIO_193_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
+#define GPIO_194_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
+#define GPIO_195_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
+#define GPIO_196_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
+#define GPIO_197_SELECT     FUNCTION2+NonGpio   // Default GPIO for LOM_POWER, high active
+// RESERVED FOR LCD BACKLIGHT PWM
+#define GPIO_198_SELECT     FUNCTION0+NonGpio   // IMC SCROLL LED CONTROL
+#define GPIO_199_SELECT     FUNCTION3           // STRAP TO SELECT BOOT ROM - H:LPC ROM   L: SPI ROM
+#define GPIO_200_SELECT     FUNCTION2           // NEC USB3.0 POWER CONTROL 1:ON(DEFAULT); 0:OFF
+#define GPIO_201_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_202_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_203_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_204_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_205_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_206_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_207_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_208_SELECT     FUNCTION0+NonGpio   // KSI
+#define GPIO_209_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_210_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_211_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_212_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_213_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_214_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_215_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_216_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_217_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_218_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_219_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_220_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_221_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_222_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_223_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_224_SELECT     FUNCTION0+NonGpio   // KSO
+#define GPIO_225_SELECT     FUNCTION2+NonGpio   // KSO
+#define GPIO_226_SELECT     FUNCTION2+NonGpio   // KSO
+#define GPIO_227_SELECT     FUNCTION0+NonGpio   // SMBUS CLK,
+#define GPIO_228_SELECT     FUNCTION0+NonGpio   // SMBUS, DATA
+#define GPIO_229_SELECT     FUNCTION0+NonGpio   // DP1_HPD
+
+#define TYPE_GPI  (1<<5)
+#define TYPE_GPO  (0<<5)
+
+#define GPIO_00_TYPE        TYPE_GPO
+#define GPIO_01_TYPE        TYPE_GPO
+#define GPIO_02_TYPE        TYPE_GPO
+#define GPIO_03_TYPE        TYPE_GPO
+#define GPIO_04_TYPE        TYPE_GPO
+#define GPIO_05_TYPE        TYPE_GPO
+#define GPIO_06_TYPE        TYPE_GPO
+#define GPIO_07_TYPE        TYPE_GPO
+#define GPIO_08_TYPE        TYPE_GPO
+#define GPIO_09_TYPE        TYPE_GPI
+#define GPIO_10_TYPE        TYPE_GPI
+#define GPIO_11_TYPE        TYPE_GPO
+#define GPIO_12_TYPE        TYPE_GPO
+#define GPIO_13_TYPE        TYPE_GPO
+#define GPIO_14_TYPE        TYPE_GPO
+#define GPIO_15_TYPE        TYPE_GPO
+#define GPIO_16_TYPE        TYPE_GPO
+#define GPIO_17_TYPE        TYPE_GPO
+#define GPIO_18_TYPE        TYPE_GPO
+#define GPIO_19_TYPE        TYPE_GPO
+#define GPIO_20_TYPE        TYPE_GPO
+#define GPIO_21_TYPE        TYPE_GPO
+#define GPIO_22_TYPE        TYPE_GPO
+#define GPIO_23_TYPE        TYPE_GPO
+#define GPIO_24_TYPE        TYPE_GPO
+#define GPIO_25_TYPE        TYPE_GPO
+#define GPIO_26_TYPE        TYPE_GPO
+#define GPIO_27_TYPE        TYPE_GPO
+#define GPIO_28_TYPE        TYPE_GPI
+#define GPIO_29_TYPE        TYPE_GPO
+#define GPIO_30_TYPE        TYPE_GPI
+#define GPIO_31_TYPE        TYPE_GPI
+#define GPIO_32_TYPE        TYPE_GPO
+#define GPIO_33_TYPE        TYPE_GPI
+#define GPIO_34_TYPE        TYPE_GPO
+#define GPIO_35_TYPE        TYPE_GPO
+#define GPIO_36_TYPE        TYPE_GPO
+#define GPIO_37_TYPE        TYPE_GPO
+#define GPIO_38_TYPE        TYPE_GPO
+#define GPIO_39_TYPE        TYPE_GPO
+#define GPIO_40_TYPE        TYPE_GPO
+#define GPIO_41_TYPE        TYPE_GPI
+#define GPIO_42_TYPE        TYPE_GPI
+#define GPIO_43_TYPE        TYPE_GPO
+#define GPIO_44_TYPE        TYPE_GPO
+#define GPIO_45_TYPE        TYPE_GPO
+#define GPIO_46_TYPE        TYPE_GPI
+#define GPIO_47_TYPE        TYPE_GPO
+#define GPIO_48_TYPE        TYPE_GPO
+#define GPIO_49_TYPE        TYPE_GPO
+#define GPIO_50_TYPE        TYPE_GPO
+#define GPIO_51_TYPE        TYPE_GPO
+#define GPIO_52_TYPE        TYPE_GPO
+#define GPIO_53_TYPE        TYPE_GPO
+#define GPIO_54_TYPE        TYPE_GPO
+#define GPIO_55_TYPE        TYPE_GPO
+#define GPIO_56_TYPE        TYPE_GPI
+#define GPIO_57_TYPE        TYPE_GPO
+#define GPIO_58_TYPE        TYPE_GPO
+#define GPIO_59_TYPE        TYPE_GPO
+#define GPIO_60_TYPE        TYPE_GPI
+#define GPIO_61_TYPE        TYPE_GPI
+#define GPIO_62_TYPE        TYPE_GPI
+#define GPIO_63_TYPE        TYPE_GPI
+#define GPIO_64_TYPE        TYPE_GPI
+#define GPIO_65_TYPE        TYPE_GPI
+#define GPIO_66_TYPE        TYPE_GPO
+#define GPIO_67_TYPE        TYPE_GPO
+#define GPIO_68_TYPE        TYPE_GPO
+#define GPIO_69_TYPE        TYPE_GPO
+#define GPIO_70_TYPE        TYPE_GPO
+#define GPIO_71_TYPE        TYPE_GPO
+#define GPIO_72_TYPE        TYPE_GPO
+#define GPIO_73_TYPE        TYPE_GPO
+#define GPIO_74_TYPE        TYPE_GPO
+#define GPIO_75_TYPE        TYPE_GPO
+#define GPIO_76_TYPE        TYPE_GPO
+#define GPIO_77_TYPE        TYPE_GPO
+#define GPIO_78_TYPE        TYPE_GPO
+#define GPIO_79_TYPE        TYPE_GPO
+#define GPIO_80_TYPE        TYPE_GPO
+#define GPIO_81_TYPE        TYPE_GPO
+#define GPIO_82_TYPE        TYPE_GPO
+#define GPIO_83_TYPE        TYPE_GPO
+#define GPIO_84_TYPE        TYPE_GPO
+#define GPIO_85_TYPE        TYPE_GPO
+#define GPIO_86_TYPE        TYPE_GPO
+#define GPIO_87_TYPE        TYPE_GPO
+#define GPIO_88_TYPE        TYPE_GPO
+#define GPIO_89_TYPE        TYPE_GPO
+#define GPIO_90_TYPE        TYPE_GPO
+#define GPIO_91_TYPE        TYPE_GPO
+#define GPIO_92_TYPE        TYPE_GPO
+#define GPIO_93_TYPE        TYPE_GPO
+#define GPIO_94_TYPE        TYPE_GPO
+#define GPIO_95_TYPE        TYPE_GPO
+
+// GEVENT 00 ~ 23 are mapped to GPIO 96 ~ 119
+#define GPIO_96_TYPE        TYPE_GPI
+#define GPIO_97_TYPE        TYPE_GPI
+#define GPIO_98_TYPE        TYPE_GPI
+#define GPIO_99_TYPE        TYPE_GPI
+#define GPIO_100_TYPE       TYPE_GPI
+#define GPIO_101_TYPE       TYPE_GPI
+#define GPIO_102_TYPE       TYPE_GPO
+#define GPIO_103_TYPE       TYPE_GPO
+#define GPIO_104_TYPE       TYPE_GPI
+#define GPIO_105_TYPE       TYPE_GPI
+#define GPIO_106_TYPE       TYPE_GPO
+#define GPIO_107_TYPE       TYPE_GPI
+#define GPIO_108_TYPE       TYPE_GPI
+#define GPIO_109_TYPE       TYPE_GPI
+#define GPIO_110_TYPE       TYPE_GPI
+#define GPIO_111_TYPE       TYPE_GPI
+#define GPIO_112_TYPE       TYPE_GPI
+#define GPIO_113_TYPE       TYPE_GPI
+#define GPIO_114_TYPE       TYPE_GPO
+#define GPIO_115_TYPE       TYPE_GPI
+#define GPIO_116_TYPE       TYPE_GPI
+#define GPIO_117_TYPE       TYPE_GPI
+#define GPIO_118_TYPE       TYPE_GPI
+#define GPIO_119_TYPE       TYPE_GPI
+
+#define GPIO_120_TYPE       TYPE_GPO
+#define GPIO_121_TYPE       TYPE_GPO
+#define GPIO_122_TYPE       TYPE_GPO
+#define GPIO_123_TYPE       TYPE_GPO
+#define GPIO_124_TYPE       TYPE_GPO
+#define GPIO_125_TYPE       TYPE_GPO
+#define GPIO_126_TYPE       TYPE_GPO
+#define GPIO_127_TYPE       TYPE_GPO
+#define GPIO_128_TYPE       TYPE_GPO
+#define GPIO_129_TYPE       TYPE_GPO
+#define GPIO_130_TYPE       TYPE_GPO
+#define GPIO_131_TYPE       TYPE_GPO
+#define GPIO_132_TYPE       TYPE_GPO
+#define GPIO_133_TYPE       TYPE_GPO
+#define GPIO_134_TYPE       TYPE_GPO
+#define GPIO_135_TYPE       TYPE_GPO
+#define GPIO_136_TYPE       TYPE_GPO
+#define GPIO_137_TYPE       TYPE_GPO
+#define GPIO_138_TYPE       TYPE_GPO
+#define GPIO_139_TYPE       TYPE_GPO
+#define GPIO_140_TYPE       TYPE_GPO
+#define GPIO_141_TYPE       TYPE_GPO
+#define GPIO_142_TYPE       TYPE_GPO
+#define GPIO_143_TYPE       TYPE_GPO
+#define GPIO_144_TYPE       TYPE_GPO
+#define GPIO_145_TYPE       TYPE_GPO
+#define GPIO_146_TYPE       TYPE_GPO
+#define GPIO_147_TYPE       TYPE_GPO
+#define GPIO_148_TYPE       TYPE_GPO
+#define GPIO_149_TYPE       TYPE_GPO
+#define GPIO_150_TYPE       TYPE_GPO
+#define GPIO_151_TYPE       TYPE_GPO
+#define GPIO_152_TYPE       TYPE_GPO
+#define GPIO_153_TYPE       TYPE_GPO
+#define GPIO_154_TYPE       TYPE_GPO
+#define GPIO_155_TYPE       TYPE_GPO
+#define GPIO_156_TYPE       TYPE_GPO
+#define GPIO_157_TYPE       TYPE_GPO
+#define GPIO_158_TYPE       TYPE_GPO
+#define GPIO_159_TYPE       TYPE_GPO
+#define GPIO_160_TYPE       TYPE_GPO
+#define GPIO_161_TYPE       TYPE_GPO
+#define GPIO_162_TYPE       TYPE_GPO
+#define GPIO_163_TYPE       TYPE_GPO
+#define GPIO_164_TYPE       TYPE_GPI
+#define GPIO_165_TYPE       TYPE_GPO
+#define GPIO_166_TYPE       TYPE_GPI
+#define GPIO_167_TYPE       TYPE_GPI
+#define GPIO_168_TYPE       TYPE_GPI
+#define GPIO_169_TYPE       TYPE_GPI
+#define GPIO_170_TYPE       TYPE_GPO
+#define GPIO_171_TYPE       TYPE_GPI
+#define GPIO_172_TYPE       TYPE_GPO
+#define GPIO_173_TYPE       TYPE_GPI
+#define GPIO_174_TYPE       TYPE_GPI
+#define GPIO_175_TYPE       TYPE_GPO
+#define GPIO_176_TYPE       TYPE_GPO
+#define GPIO_177_TYPE       TYPE_GPO
+#define GPIO_178_TYPE       TYPE_GPO
+#define GPIO_179_TYPE       TYPE_GPO
+#define GPIO_180_TYPE       TYPE_GPO
+#define GPIO_181_TYPE       TYPE_GPO
+#define GPIO_182_TYPE       TYPE_GPO
+#define GPIO_183_TYPE       TYPE_GPO
+#define GPIO_184_TYPE       TYPE_GPI
+#define GPIO_185_TYPE       TYPE_GPO
+#define GPIO_186_TYPE       TYPE_GPO
+#define GPIO_187_TYPE       TYPE_GPO
+#define GPIO_188_TYPE       TYPE_GPO
+#define GPIO_189_TYPE       TYPE_GPI
+#define GPIO_190_TYPE       TYPE_GPI
+#define GPIO_191_TYPE       TYPE_GPO
+#define GPIO_192_TYPE       TYPE_GPO
+#define GPIO_193_TYPE       TYPE_GPO
+#define GPIO_194_TYPE       TYPE_GPO
+#define GPIO_195_TYPE       TYPE_GPO
+#define GPIO_196_TYPE       TYPE_GPO
+#define GPIO_197_TYPE       TYPE_GPO
+#define GPIO_198_TYPE       TYPE_GPO
+#define GPIO_199_TYPE       TYPE_GPI
+#define GPIO_200_TYPE       TYPE_GPO
+#define GPIO_201_TYPE       TYPE_GPI
+#define GPIO_202_TYPE       TYPE_GPI
+#define GPIO_203_TYPE       TYPE_GPI
+#define GPIO_204_TYPE       TYPE_GPI
+#define GPIO_205_TYPE       TYPE_GPI
+#define GPIO_206_TYPE       TYPE_GPI
+#define GPIO_207_TYPE       TYPE_GPI
+#define GPIO_208_TYPE       TYPE_GPI
+#define GPIO_209_TYPE       TYPE_GPO
+#define GPIO_210_TYPE       TYPE_GPO
+#define GPIO_211_TYPE       TYPE_GPO
+#define GPIO_212_TYPE       TYPE_GPO
+#define GPIO_213_TYPE       TYPE_GPO
+#define GPIO_214_TYPE       TYPE_GPO
+#define GPIO_215_TYPE       TYPE_GPO
+#define GPIO_216_TYPE       TYPE_GPO
+#define GPIO_217_TYPE       TYPE_GPO
+#define GPIO_218_TYPE       TYPE_GPO
+#define GPIO_219_TYPE       TYPE_GPO
+#define GPIO_220_TYPE       TYPE_GPO
+#define GPIO_221_TYPE       TYPE_GPO
+#define GPIO_222_TYPE       TYPE_GPO
+#define GPIO_223_TYPE       TYPE_GPO
+#define GPIO_224_TYPE       TYPE_GPO
+#define GPIO_225_TYPE       TYPE_GPO
+#define GPIO_226_TYPE       TYPE_GPO
+#define GPIO_227_TYPE       TYPE_GPO
+#define GPIO_228_TYPE       TYPE_GPO
+#define GPIO_229_TYPE       TYPE_GPO
+
+#define GPO_LOW   (0<<6)
+#define GPO_HI    (1<<6)
+
+#define GPO_00_LEVEL        GPO_HI
+#define GPO_01_LEVEL        GPO_HI
+#define GPO_02_LEVEL        GPO_HI
+#define GPO_03_LEVEL        GPO_HI
+#define GPO_04_LEVEL        GPO_HI
+#define GPO_05_LEVEL        GPO_HI
+#define GPO_06_LEVEL        GPO_HI
+#define GPO_07_LEVEL        GPO_HI
+#define GPO_08_LEVEL        GPO_HI
+#define GPO_09_LEVEL        GPO_LOW
+#define GPO_10_LEVEL        GPO_LOW
+#define GPO_11_LEVEL        GPO_HI
+#define GPO_12_LEVEL        GPO_HI
+#define GPO_13_LEVEL        GPO_HI
+#define GPO_14_LEVEL        GPO_HI
+#define GPO_15_LEVEL        GPO_HI
+#define GPO_16_LEVEL        GPO_HI
+#define GPO_17_LEVEL        GPO_HI
+#define GPO_18_LEVEL        GPO_HI
+#define GPO_19_LEVEL        GPO_LOW
+#define GPO_20_LEVEL        GPO_LOW
+#define GPO_21_LEVEL        GPO_LOW
+#define GPO_22_LEVEL        GPO_HI
+#define GPO_23_LEVEL        GPO_HI
+#define GPO_24_LEVEL        GPO_HI
+#define GPO_25_LEVEL        GPO_HI
+#define GPO_26_LEVEL        GPO_HI
+#define GPO_27_LEVEL        GPO_HI
+#define GPO_28_LEVEL        GPO_LOW
+#define GPO_29_LEVEL        GPO_HI
+#define GPO_30_LEVEL        GPO_LOW
+#define GPO_31_LEVEL        GPO_LOW
+#define GPO_32_LEVEL        GPO_HI
+#define GPO_33_LEVEL        GPO_LOW
+#define GPO_34_LEVEL        GPO_LOW
+#define GPO_35_LEVEL        GPO_LOW
+#define GPO_36_LEVEL        GPO_LOW
+#define GPO_37_LEVEL        GPO_HI
+#define GPO_38_LEVEL        GPO_HI
+#define GPO_39_LEVEL        GPO_HI
+#define GPO_40_LEVEL        GPO_LOW
+#define GPO_41_LEVEL        GPO_LOW
+#define GPO_42_LEVEL        GPO_LOW
+#define GPO_43_LEVEL        GPO_LOW
+#define GPO_44_LEVEL        GPO_HI
+#define GPO_45_LEVEL        GPO_HI
+#define GPO_46_LEVEL        GPO_LOW
+#define GPO_47_LEVEL        GPO_LOW
+#define GPO_48_LEVEL        GPO_LOW
+#define GPO_49_LEVEL        GPO_HI
+#define GPO_50_LEVEL        GPO_HI
+#define GPO_51_LEVEL        GPO_LOW
+#define GPO_52_LEVEL        GPO_HI
+#define GPO_53_LEVEL        GPO_HI
+#define GPO_54_LEVEL        GPO_LOW
+#define GPO_55_LEVEL        GPO_LOW
+#define GPO_56_LEVEL        GPO_LOW
+#define GPO_57_LEVEL        GPO_HI
+#define GPO_58_LEVEL        GPO_HI
+#define GPO_59_LEVEL        GPO_HI
+#define GPO_60_LEVEL        GPO_LOW
+#define GPO_61_LEVEL        GPO_LOW
+#define GPO_62_LEVEL        GPO_LOW
+#define GPO_63_LEVEL        GPO_LOW
+#define GPO_64_LEVEL        GPO_LOW
+#define GPO_65_LEVEL        GPO_LOW
+#define GPO_66_LEVEL        GPO_LOW
+#define GPO_67_LEVEL        GPO_LOW
+#define GPO_68_LEVEL        GPO_LOW
+#define GPO_69_LEVEL        GPO_LOW
+#define GPO_70_LEVEL        GPO_LOW
+#define GPO_71_LEVEL        GPO_LOW
+#define GPO_72_LEVEL        GPO_LOW
+#define GPO_73_LEVEL        GPO_LOW
+#define GPO_74_LEVEL        GPO_LOW
+#define GPO_75_LEVEL        GPO_LOW
+#define GPO_76_LEVEL        GPO_LOW
+#define GPO_77_LEVEL        GPO_LOW
+#define GPO_78_LEVEL        GPO_LOW
+#define GPO_79_LEVEL        GPO_LOW
+#define GPO_80_LEVEL        GPO_LOW
+#define GPO_81_LEVEL        GPO_LOW
+#define GPO_82_LEVEL        GPO_LOW
+#define GPO_83_LEVEL        GPO_LOW
+#define GPO_84_LEVEL        GPO_LOW
+#define GPO_85_LEVEL        GPO_LOW
+#define GPO_86_LEVEL        GPO_LOW
+#define GPO_87_LEVEL        GPO_LOW
+#define GPO_88_LEVEL        GPO_LOW
+#define GPO_89_LEVEL        GPO_LOW
+#define GPO_90_LEVEL        GPO_LOW
+#define GPO_91_LEVEL        GPO_LOW
+#define GPO_92_LEVEL        GPO_LOW
+#define GPO_93_LEVEL        GPO_LOW
+#define GPO_94_LEVEL        GPO_LOW
+#define GPO_95_LEVEL        GPO_LOW
+#define GPO_96_LEVEL        GPO_LOW
+#define GPO_97_LEVEL        GPO_LOW
+#define GPO_98_LEVEL        GPO_LOW
+#define GPO_99_LEVEL        GPO_LOW
+#define GPO_100_LEVEL       GPO_LOW
+#define GPO_101_LEVEL       GPO_LOW
+#define GPO_102_LEVEL       GPO_LOW
+#define GPO_103_LEVEL       GPO_LOW
+#define GPO_104_LEVEL       GPO_LOW
+#define GPO_105_LEVEL       GPO_LOW
+#define GPO_106_LEVEL       GPO_LOW
+#define GPO_107_LEVEL       GPO_LOW
+#define GPO_108_LEVEL       GPO_HI
+#define GPO_109_LEVEL       GPO_LOW
+#define GPO_110_LEVEL       GPO_HI
+#define GPO_111_LEVEL       GPO_HI
+#define GPO_112_LEVEL       GPO_HI
+#define GPO_113_LEVEL       GPO_LOW
+#define GPO_114_LEVEL       GPO_LOW
+#define GPO_115_LEVEL       GPO_LOW
+#define GPO_116_LEVEL       GPO_LOW
+#define GPO_117_LEVEL       GPO_LOW
+#define GPO_118_LEVEL       GPO_LOW
+#define GPO_119_LEVEL       GPO_LOW
+#define GPO_120_LEVEL       GPO_LOW
+#define GPO_121_LEVEL       GPO_LOW
+#define GPO_122_LEVEL       GPO_LOW
+#define GPO_123_LEVEL       GPO_LOW
+#define GPO_124_LEVEL       GPO_LOW
+#define GPO_125_LEVEL       GPO_LOW
+#define GPO_126_LEVEL       GPO_LOW
+#define GPO_127_LEVEL       GPO_LOW
+#define GPO_128_LEVEL       GPO_LOW
+#define GPO_129_LEVEL       GPO_LOW
+#define GPO_130_LEVEL       GPO_LOW
+#define GPO_131_LEVEL       GPO_LOW
+#define GPO_132_LEVEL       GPO_LOW
+#define GPO_133_LEVEL       GPO_LOW
+#define GPO_134_LEVEL       GPO_LOW
+#define GPO_135_LEVEL       GPO_LOW
+#define GPO_136_LEVEL       GPO_LOW
+#define GPO_137_LEVEL       GPO_LOW
+#define GPO_138_LEVEL       GPO_LOW
+#define GPO_139_LEVEL       GPO_LOW
+#define GPO_140_LEVEL       GPO_LOW
+#define GPO_141_LEVEL       GPO_LOW
+#define GPO_142_LEVEL       GPO_LOW
+#define GPO_143_LEVEL       GPO_LOW
+#define GPO_144_LEVEL       GPO_LOW
+#define GPO_145_LEVEL       GPO_LOW
+#define GPO_146_LEVEL       GPO_LOW
+#define GPO_147_LEVEL       GPO_LOW
+#define GPO_148_LEVEL       GPO_LOW
+#define GPO_149_LEVEL       GPO_LOW
+#define GPO_150_LEVEL       GPO_LOW
+#define GPO_151_LEVEL       GPO_LOW
+#define GPO_152_LEVEL       GPO_LOW
+#define GPO_153_LEVEL       GPO_LOW
+#define GPO_154_LEVEL       GPO_LOW
+#define GPO_155_LEVEL       GPO_LOW
+#define GPO_156_LEVEL       GPO_LOW
+#define GPO_157_LEVEL       GPO_LOW
+#define GPO_158_LEVEL       GPO_LOW
+#define GPO_159_LEVEL       GPO_LOW
+#define GPO_160_LEVEL       GPO_LOW
+#define GPO_161_LEVEL       GPO_LOW
+#define GPO_162_LEVEL       GPO_LOW
+#define GPO_163_LEVEL       GPO_LOW
+#define GPO_164_LEVEL       GPO_LOW
+#define GPO_165_LEVEL       GPO_LOW
+#define GPO_166_LEVEL       GPO_LOW
+#define GPO_167_LEVEL       GPO_LOW
+#define GPO_168_LEVEL       GPO_LOW
+#define GPO_169_LEVEL       GPO_LOW
+#define GPO_170_LEVEL       GPO_HI
+#define GPO_171_LEVEL       GPO_LOW
+#define GPO_172_LEVEL       GPO_HI		// FCH_USB3.0PORT_EN# 0:ENABLE; 1:DISABLE
+#define GPO_173_LEVEL       GPO_LOW
+#define GPO_174_LEVEL       GPO_LOW
+#define GPO_175_LEVEL       GPO_LOW
+#define GPO_176_LEVEL       GPO_LOW
+#define GPO_177_LEVEL       GPO_LOW
+#define GPO_178_LEVEL       GPO_HI      // AMD.SR BU to set VDDIO level to 1.5V for Barb BU
+#define GPO_179_LEVEL       GPO_HI
+#define GPO_180_LEVEL       GPO_HI
+#define GPO_181_LEVEL       GPO_LOW
+#define GPO_182_LEVEL       GPO_HI
+#define GPO_183_LEVEL       GPO_LOW
+#define GPO_184_LEVEL       GPO_LOW
+#define GPO_185_LEVEL       GPO_LOW
+#define GPO_186_LEVEL       GPO_LOW
+#define GPO_187_LEVEL       GPO_LOW
+#define GPO_188_LEVEL       GPO_LOW
+#define GPO_189_LEVEL       GPO_LOW
+#define GPO_190_LEVEL       GPO_LOW
+#define GPO_191_LEVEL       GPO_LOW
+#define GPO_192_LEVEL       GPO_LOW
+#define GPO_193_LEVEL       GPO_LOW
+#define GPO_194_LEVEL       GPO_LOW
+#define GPO_195_LEVEL       GPO_LOW
+#define GPO_196_LEVEL       GPO_LOW
+#define GPO_197_LEVEL       GPO_LOW
+#define GPO_198_LEVEL       GPO_LOW
+#define GPO_199_LEVEL       GPO_LOW
+#define GPO_200_LEVEL       GPO_HI
+#define GPO_201_LEVEL       GPO_LOW
+#define GPO_202_LEVEL       GPO_LOW
+#define GPO_203_LEVEL       GPO_LOW
+#define GPO_204_LEVEL       GPO_LOW
+#define GPO_205_LEVEL       GPO_LOW
+#define GPO_206_LEVEL       GPO_LOW
+#define GPO_207_LEVEL       GPO_LOW
+#define GPO_208_LEVEL       GPO_LOW
+#define GPO_209_LEVEL       GPO_LOW
+#define GPO_210_LEVEL       GPO_LOW
+#define GPO_211_LEVEL       GPO_LOW
+#define GPO_212_LEVEL       GPO_LOW
+#define GPO_213_LEVEL       GPO_LOW
+#define GPO_214_LEVEL       GPO_LOW
+#define GPO_215_LEVEL       GPO_LOW
+#define GPO_216_LEVEL       GPO_LOW
+#define GPO_217_LEVEL       GPO_LOW
+#define GPO_218_LEVEL       GPO_LOW
+#define GPO_219_LEVEL       GPO_LOW
+#define GPO_220_LEVEL       GPO_LOW
+#define GPO_221_LEVEL       GPO_LOW
+#define GPO_222_LEVEL       GPO_LOW
+#define GPO_223_LEVEL       GPO_LOW
+#define GPO_224_LEVEL       GPO_LOW
+#define GPO_225_LEVEL       GPO_LOW
+#define GPO_226_LEVEL       GPO_LOW
+#define GPO_227_LEVEL       GPO_LOW
+#define GPO_228_LEVEL       GPO_LOW
+#define GPO_229_LEVEL       GPO_LOW
+
+#define GPIO_NONSTICKY   (0<<2)
+#define GPIO_STICKY      (1<<2)
+
+#define GPIO_00_STICKY      GPIO_NONSTICKY
+#define GPIO_01_STICKY      GPIO_NONSTICKY
+#define GPIO_02_STICKY      GPIO_NONSTICKY
+#define GPIO_03_STICKY      GPIO_NONSTICKY
+#define GPIO_04_STICKY      GPIO_NONSTICKY
+#define GPIO_05_STICKY      GPIO_NONSTICKY
+#define GPIO_06_STICKY      GPIO_NONSTICKY
+#define GPIO_07_STICKY      GPIO_NONSTICKY
+#define GPIO_08_STICKY      GPIO_NONSTICKY
+#define GPIO_09_STICKY      GPIO_NONSTICKY
+#define GPIO_10_STICKY      GPIO_NONSTICKY
+#define GPIO_11_STICKY      GPIO_NONSTICKY
+#define GPIO_12_STICKY      GPIO_NONSTICKY
+#define GPIO_13_STICKY      GPIO_NONSTICKY
+#define GPIO_14_STICKY      GPIO_NONSTICKY
+#define GPIO_15_STICKY      GPIO_NONSTICKY
+#define GPIO_16_STICKY      GPIO_NONSTICKY
+#define GPIO_17_STICKY      GPIO_STICKY
+#define GPIO_18_STICKY      GPIO_NONSTICKY
+#define GPIO_19_STICKY      GPIO_NONSTICKY
+#define GPIO_20_STICKY      GPIO_NONSTICKY
+#define GPIO_21_STICKY      GPIO_NONSTICKY
+#define GPIO_22_STICKY      GPIO_NONSTICKY
+#define GPIO_23_STICKY      GPIO_NONSTICKY
+#define GPIO_24_STICKY      GPIO_NONSTICKY
+#define GPIO_25_STICKY      GPIO_NONSTICKY
+#define GPIO_26_STICKY      GPIO_NONSTICKY
+#define GPIO_27_STICKY      GPIO_NONSTICKY
+#define GPIO_28_STICKY      GPIO_NONSTICKY
+#define GPIO_29_STICKY      GPIO_NONSTICKY
+#define GPIO_30_STICKY      GPIO_NONSTICKY
+#define GPIO_31_STICKY      GPIO_NONSTICKY
+#define GPIO_32_STICKY      GPIO_NONSTICKY
+#define GPIO_33_STICKY      GPIO_NONSTICKY
+#define GPIO_34_STICKY      GPIO_NONSTICKY
+#define GPIO_35_STICKY      GPIO_NONSTICKY
+#define GPIO_36_STICKY      GPIO_NONSTICKY
+#define GPIO_37_STICKY      GPIO_NONSTICKY
+#define GPIO_38_STICKY      GPIO_NONSTICKY
+#define GPIO_39_STICKY      GPIO_NONSTICKY
+#define GPIO_40_STICKY      GPIO_NONSTICKY
+#define GPIO_41_STICKY      GPIO_NONSTICKY
+#define GPIO_42_STICKY      GPIO_NONSTICKY
+#define GPIO_43_STICKY      GPIO_NONSTICKY
+#define GPIO_44_STICKY      GPIO_NONSTICKY
+#define GPIO_45_STICKY      GPIO_NONSTICKY
+#define GPIO_46_STICKY      GPIO_NONSTICKY
+#define GPIO_47_STICKY      GPIO_NONSTICKY
+#define GPIO_48_STICKY      GPIO_NONSTICKY
+#define GPIO_49_STICKY      GPIO_NONSTICKY
+#define GPIO_50_STICKY      GPIO_NONSTICKY
+#define GPIO_51_STICKY      GPIO_NONSTICKY
+#define GPIO_52_STICKY      GPIO_NONSTICKY
+#define GPIO_53_STICKY      GPIO_NONSTICKY
+#define GPIO_54_STICKY      GPIO_NONSTICKY
+#define GPIO_55_STICKY      GPIO_NONSTICKY
+#define GPIO_56_STICKY      GPIO_NONSTICKY
+#define GPIO_57_STICKY      GPIO_NONSTICKY
+#define GPIO_58_STICKY      GPIO_NONSTICKY
+#define GPIO_59_STICKY      GPIO_NONSTICKY
+#define GPIO_60_STICKY      GPIO_NONSTICKY
+#define GPIO_61_STICKY      GPIO_NONSTICKY
+#define GPIO_62_STICKY      GPIO_NONSTICKY
+#define GPIO_63_STICKY      GPIO_NONSTICKY
+#define GPIO_64_STICKY      GPIO_NONSTICKY
+#define GPIO_65_STICKY      GPIO_NONSTICKY
+#define GPIO_66_STICKY      GPIO_NONSTICKY
+#define GPIO_67_STICKY      GPIO_NONSTICKY
+#define GPIO_68_STICKY      GPIO_NONSTICKY
+#define GPIO_69_STICKY      GPIO_NONSTICKY
+#define GPIO_70_STICKY      GPIO_NONSTICKY
+#define GPIO_71_STICKY      GPIO_NONSTICKY
+#define GPIO_72_STICKY      GPIO_NONSTICKY
+#define GPIO_73_STICKY      GPIO_NONSTICKY
+#define GPIO_74_STICKY      GPIO_NONSTICKY
+#define GPIO_75_STICKY      GPIO_NONSTICKY
+#define GPIO_76_STICKY      GPIO_NONSTICKY
+#define GPIO_77_STICKY      GPIO_NONSTICKY
+#define GPIO_78_STICKY      GPIO_NONSTICKY
+#define GPIO_79_STICKY      GPIO_NONSTICKY
+#define GPIO_80_STICKY      GPIO_NONSTICKY
+#define GPIO_81_STICKY      GPIO_NONSTICKY
+#define GPIO_82_STICKY      GPIO_NONSTICKY
+#define GPIO_83_STICKY      GPIO_NONSTICKY
+#define GPIO_84_STICKY      GPIO_NONSTICKY
+#define GPIO_85_STICKY      GPIO_NONSTICKY
+#define GPIO_86_STICKY      GPIO_NONSTICKY
+#define GPIO_87_STICKY      GPIO_NONSTICKY
+#define GPIO_88_STICKY      GPIO_NONSTICKY
+#define GPIO_89_STICKY      GPIO_NONSTICKY
+#define GPIO_90_STICKY      GPIO_NONSTICKY
+#define GPIO_91_STICKY      GPIO_NONSTICKY
+#define GPIO_92_STICKY      GPIO_NONSTICKY
+#define GPIO_93_STICKY      GPIO_NONSTICKY
+#define GPIO_94_STICKY      GPIO_NONSTICKY
+#define GPIO_95_STICKY      GPIO_NONSTICKY
+#define GPIO_96_STICKY      GPIO_NONSTICKY
+#define GPIO_97_STICKY      GPIO_NONSTICKY
+#define GPIO_98_STICKY      GPIO_NONSTICKY
+#define GPIO_99_STICKY      GPIO_NONSTICKY
+#define GPIO_100_STICKY     GPIO_NONSTICKY
+#define GPIO_101_STICKY     GPIO_NONSTICKY
+#define GPIO_102_STICKY     GPIO_STICKY
+#define GPIO_103_STICKY     GPIO_STICKY
+#define GPIO_104_STICKY     GPIO_NONSTICKY
+#define GPIO_105_STICKY     GPIO_NONSTICKY
+#define GPIO_106_STICKY     GPIO_NONSTICKY
+#define GPIO_107_STICKY     GPIO_NONSTICKY
+#define GPIO_108_STICKY     GPIO_STICKY
+#define GPIO_109_STICKY     GPIO_NONSTICKY
+#define GPIO_110_STICKY     GPIO_NONSTICKY
+#define GPIO_111_STICKY     GPIO_NONSTICKY
+#define GPIO_112_STICKY     GPIO_NONSTICKY
+#define GPIO_113_STICKY     GPIO_NONSTICKY
+#define GPIO_114_STICKY     GPIO_NONSTICKY
+#define GPIO_115_STICKY     GPIO_NONSTICKY
+#define GPIO_116_STICKY     GPIO_NONSTICKY
+#define GPIO_117_STICKY     GPIO_NONSTICKY
+#define GPIO_118_STICKY     GPIO_NONSTICKY
+#define GPIO_119_STICKY     GPIO_NONSTICKY
+#define GPIO_120_STICKY     GPIO_NONSTICKY
+#define GPIO_121_STICKY     GPIO_NONSTICKY
+#define GPIO_122_STICKY     GPIO_NONSTICKY
+#define GPIO_123_STICKY     GPIO_NONSTICKY
+#define GPIO_124_STICKY     GPIO_NONSTICKY
+#define GPIO_125_STICKY     GPIO_NONSTICKY
+#define GPIO_126_STICKY     GPIO_NONSTICKY
+#define GPIO_127_STICKY     GPIO_NONSTICKY
+#define GPIO_128_STICKY     GPIO_NONSTICKY
+#define GPIO_129_STICKY     GPIO_NONSTICKY
+#define GPIO_130_STICKY     GPIO_NONSTICKY
+#define GPIO_131_STICKY     GPIO_NONSTICKY
+#define GPIO_132_STICKY     GPIO_NONSTICKY
+#define GPIO_133_STICKY     GPIO_NONSTICKY
+#define GPIO_134_STICKY     GPIO_NONSTICKY
+#define GPIO_135_STICKY     GPIO_NONSTICKY
+#define GPIO_136_STICKY     GPIO_NONSTICKY
+#define GPIO_137_STICKY     GPIO_NONSTICKY
+#define GPIO_138_STICKY     GPIO_NONSTICKY
+#define GPIO_139_STICKY     GPIO_NONSTICKY
+#define GPIO_140_STICKY     GPIO_NONSTICKY
+#define GPIO_141_STICKY     GPIO_NONSTICKY
+#define GPIO_142_STICKY     GPIO_NONSTICKY
+#define GPIO_143_STICKY     GPIO_NONSTICKY
+#define GPIO_144_STICKY     GPIO_NONSTICKY
+#define GPIO_145_STICKY     GPIO_NONSTICKY
+#define GPIO_146_STICKY     GPIO_NONSTICKY
+#define GPIO_147_STICKY     GPIO_NONSTICKY
+#define GPIO_148_STICKY     GPIO_NONSTICKY
+#define GPIO_149_STICKY     GPIO_NONSTICKY
+#define GPIO_150_STICKY     GPIO_NONSTICKY
+#define GPIO_151_STICKY     GPIO_NONSTICKY
+#define GPIO_152_STICKY     GPIO_NONSTICKY
+#define GPIO_153_STICKY     GPIO_NONSTICKY
+#define GPIO_154_STICKY     GPIO_NONSTICKY
+#define GPIO_155_STICKY     GPIO_NONSTICKY
+#define GPIO_156_STICKY     GPIO_NONSTICKY
+#define GPIO_157_STICKY     GPIO_NONSTICKY
+#define GPIO_158_STICKY     GPIO_NONSTICKY
+#define GPIO_159_STICKY     GPIO_NONSTICKY
+#define GPIO_160_STICKY     GPIO_NONSTICKY
+#define GPIO_161_STICKY     GPIO_NONSTICKY
+#define GPIO_162_STICKY     GPIO_NONSTICKY
+#define GPIO_163_STICKY     GPIO_NONSTICKY
+#define GPIO_164_STICKY     GPIO_NONSTICKY
+#define GPIO_165_STICKY     GPIO_NONSTICKY
+#define GPIO_166_STICKY     GPIO_NONSTICKY
+#define GPIO_167_STICKY     GPIO_NONSTICKY
+#define GPIO_168_STICKY     GPIO_NONSTICKY
+#define GPIO_169_STICKY     GPIO_NONSTICKY
+#define GPIO_170_STICKY     GPIO_STICKY
+#define GPIO_171_STICKY     GPIO_NONSTICKY
+#define GPIO_172_STICKY     GPIO_STICKY
+#define GPIO_173_STICKY     GPIO_NONSTICKY
+#define GPIO_174_STICKY     GPIO_NONSTICKY
+#define GPIO_175_STICKY     GPIO_NONSTICKY
+#define GPIO_176_STICKY     GPIO_NONSTICKY
+#define GPIO_177_STICKY     GPIO_NONSTICKY
+#define GPIO_178_STICKY     GPIO_NONSTICKY
+#define GPIO_179_STICKY     GPIO_NONSTICKY
+#define GPIO_180_STICKY     GPIO_NONSTICKY
+#define GPIO_181_STICKY     GPIO_NONSTICKY
+#define GPIO_182_STICKY     GPIO_NONSTICKY
+#define GPIO_183_STICKY     GPIO_NONSTICKY
+#define GPIO_184_STICKY     GPIO_NONSTICKY
+#define GPIO_185_STICKY     GPIO_NONSTICKY
+#define GPIO_186_STICKY     GPIO_NONSTICKY
+#define GPIO_187_STICKY     GPIO_NONSTICKY
+#define GPIO_188_STICKY     GPIO_NONSTICKY
+#define GPIO_189_STICKY     GPIO_NONSTICKY
+#define GPIO_190_STICKY     GPIO_NONSTICKY
+#define GPIO_191_STICKY     GPIO_NONSTICKY
+#define GPIO_192_STICKY     GPIO_NONSTICKY
+#define GPIO_193_STICKY     GPIO_NONSTICKY
+#define GPIO_194_STICKY     GPIO_NONSTICKY
+#define GPIO_195_STICKY     GPIO_NONSTICKY
+#define GPIO_196_STICKY     GPIO_NONSTICKY
+#define GPIO_197_STICKY     GPIO_NONSTICKY
+#define GPIO_198_STICKY     GPIO_NONSTICKY
+#define GPIO_199_STICKY     GPIO_NONSTICKY
+#define GPIO_200_STICKY     GPIO_NONSTICKY
+#define GPIO_201_STICKY     GPIO_NONSTICKY
+#define GPIO_202_STICKY     GPIO_NONSTICKY
+#define GPIO_203_STICKY     GPIO_NONSTICKY
+#define GPIO_204_STICKY     GPIO_NONSTICKY
+#define GPIO_205_STICKY     GPIO_NONSTICKY
+#define GPIO_206_STICKY     GPIO_NONSTICKY
+#define GPIO_207_STICKY     GPIO_NONSTICKY
+#define GPIO_208_STICKY     GPIO_NONSTICKY
+#define GPIO_209_STICKY     GPIO_NONSTICKY
+#define GPIO_210_STICKY     GPIO_NONSTICKY
+#define GPIO_211_STICKY     GPIO_NONSTICKY
+#define GPIO_212_STICKY     GPIO_NONSTICKY
+#define GPIO_213_STICKY     GPIO_NONSTICKY
+#define GPIO_214_STICKY     GPIO_NONSTICKY
+#define GPIO_215_STICKY     GPIO_NONSTICKY
+#define GPIO_216_STICKY     GPIO_NONSTICKY
+#define GPIO_217_STICKY     GPIO_NONSTICKY
+#define GPIO_218_STICKY     GPIO_NONSTICKY
+#define GPIO_219_STICKY     GPIO_NONSTICKY
+#define GPIO_220_STICKY     GPIO_NONSTICKY
+#define GPIO_221_STICKY     GPIO_NONSTICKY
+#define GPIO_222_STICKY     GPIO_NONSTICKY
+#define GPIO_223_STICKY     GPIO_NONSTICKY
+#define GPIO_224_STICKY     GPIO_NONSTICKY
+#define GPIO_225_STICKY     GPIO_NONSTICKY
+#define GPIO_226_STICKY     GPIO_NONSTICKY
+#define GPIO_227_STICKY     GPIO_NONSTICKY
+#define GPIO_228_STICKY     GPIO_NONSTICKY
+#define GPIO_229_STICKY     GPIO_NONSTICKY
+
+#define PULLUP_ENABLE      (0<<3)
+#define PULLUP_DISABLE     (1<<3)
+
+#define GPIO_00_PULLUP      PULLUP_DISABLE
+#define GPIO_01_PULLUP      PULLUP_DISABLE
+#define GPIO_02_PULLUP      PULLUP_DISABLE
+#define GPIO_03_PULLUP      PULLUP_DISABLE
+#define GPIO_04_PULLUP      PULLUP_DISABLE
+#define GPIO_05_PULLUP      PULLUP_DISABLE
+#define GPIO_06_PULLUP      PULLUP_DISABLE
+#define GPIO_07_PULLUP      PULLUP_DISABLE
+#define GPIO_08_PULLUP      PULLUP_DISABLE
+#define GPIO_09_PULLUP      PULLUP_DISABLE
+#define GPIO_10_PULLUP      PULLUP_DISABLE
+#define GPIO_11_PULLUP      PULLUP_DISABLE
+#define GPIO_12_PULLUP      PULLUP_DISABLE
+#define GPIO_13_PULLUP      PULLUP_DISABLE
+#define GPIO_14_PULLUP      PULLUP_DISABLE
+#define GPIO_15_PULLUP      PULLUP_DISABLE
+#define GPIO_16_PULLUP      PULLUP_DISABLE
+#define GPIO_17_PULLUP      PULLUP_DISABLE
+#define GPIO_18_PULLUP      PULLUP_DISABLE
+#define GPIO_19_PULLUP      PULLUP_DISABLE
+#define GPIO_20_PULLUP      PULLUP_DISABLE
+#define GPIO_21_PULLUP      PULLUP_DISABLE
+#define GPIO_22_PULLUP      PULLUP_DISABLE
+#define GPIO_23_PULLUP      PULLUP_DISABLE
+#define GPIO_24_PULLUP      PULLUP_DISABLE
+#define GPIO_25_PULLUP      PULLUP_DISABLE
+#define GPIO_26_PULLUP      PULLUP_DISABLE
+#define GPIO_27_PULLUP      PULLUP_DISABLE
+#define GPIO_28_PULLUP      PULLUP_DISABLE
+#define GPIO_29_PULLUP      PULLUP_DISABLE
+#define GPIO_30_PULLUP      PULLUP_DISABLE
+#define GPIO_31_PULLUP      PULLUP_DISABLE
+#define GPIO_32_PULLUP      PULLUP_DISABLE
+#define GPIO_33_PULLUP      PULLUP_DISABLE
+#define GPIO_34_PULLUP      PULLUP_DISABLE
+#define GPIO_35_PULLUP      PULLUP_DISABLE
+#define GPIO_36_PULLUP      PULLUP_DISABLE
+#define GPIO_37_PULLUP      PULLUP_DISABLE
+#define GPIO_38_PULLUP      PULLUP_DISABLE
+#define GPIO_39_PULLUP      PULLUP_DISABLE
+#define GPIO_40_PULLUP      PULLUP_DISABLE
+#define GPIO_41_PULLUP      PULLUP_DISABLE
+#define GPIO_42_PULLUP      PULLUP_DISABLE
+#define GPIO_43_PULLUP      PULLUP_DISABLE
+#define GPIO_44_PULLUP      PULLUP_DISABLE
+#define GPIO_45_PULLUP      PULLUP_DISABLE
+#define GPIO_46_PULLUP      PULLUP_DISABLE
+#define GPIO_47_PULLUP      PULLUP_DISABLE
+#define GPIO_48_PULLUP      PULLUP_DISABLE
+#define GPIO_49_PULLUP      PULLUP_DISABLE
+#define GPIO_50_PULLUP      PULLUP_DISABLE
+#define GPIO_51_PULLUP      PULLUP_DISABLE
+#define GPIO_52_PULLUP      PULLUP_DISABLE
+#define GPIO_53_PULLUP      PULLUP_DISABLE
+#define GPIO_54_PULLUP      PULLUP_DISABLE
+#define GPIO_55_PULLUP      PULLUP_DISABLE
+#define GPIO_56_PULLUP      PULLUP_DISABLE
+#define GPIO_57_PULLUP      PULLUP_DISABLE
+#define GPIO_58_PULLUP      PULLUP_DISABLE
+#define GPIO_59_PULLUP      PULLUP_DISABLE
+#define GPIO_60_PULLUP      PULLUP_DISABLE
+#define GPIO_61_PULLUP      PULLUP_DISABLE
+#define GPIO_62_PULLUP      PULLUP_DISABLE
+#define GPIO_63_PULLUP      PULLUP_DISABLE
+#define GPIO_64_PULLUP      PULLUP_DISABLE
+#define GPIO_65_PULLUP      PULLUP_DISABLE
+#define GPIO_66_PULLUP      PULLUP_DISABLE
+#define GPIO_67_PULLUP      PULLUP_DISABLE
+#define GPIO_68_PULLUP      PULLUP_DISABLE
+#define GPIO_69_PULLUP      PULLUP_DISABLE
+#define GPIO_70_PULLUP      PULLUP_DISABLE
+#define GPIO_71_PULLUP      PULLUP_DISABLE
+#define GPIO_72_PULLUP      PULLUP_DISABLE
+#define GPIO_73_PULLUP      PULLUP_DISABLE
+#define GPIO_74_PULLUP      PULLUP_DISABLE
+#define GPIO_75_PULLUP      PULLUP_DISABLE
+#define GPIO_76_PULLUP      PULLUP_DISABLE
+#define GPIO_77_PULLUP      PULLUP_DISABLE
+#define GPIO_78_PULLUP      PULLUP_DISABLE
+#define GPIO_79_PULLUP      PULLUP_DISABLE
+#define GPIO_80_PULLUP      PULLUP_DISABLE
+#define GPIO_80_PULLUP      PULLUP_DISABLE
+#define GPIO_81_PULLUP      PULLUP_DISABLE
+#define GPIO_82_PULLUP      PULLUP_DISABLE
+#define GPIO_83_PULLUP      PULLUP_DISABLE
+#define GPIO_84_PULLUP      PULLUP_DISABLE
+#define GPIO_85_PULLUP      PULLUP_DISABLE
+#define GPIO_86_PULLUP      PULLUP_DISABLE
+#define GPIO_87_PULLUP      PULLUP_DISABLE
+#define GPIO_88_PULLUP      PULLUP_DISABLE
+#define GPIO_89_PULLUP      PULLUP_DISABLE
+#define GPIO_90_PULLUP      PULLUP_DISABLE
+#define GPIO_91_PULLUP      PULLUP_DISABLE
+#define GPIO_92_PULLUP      PULLUP_DISABLE
+#define GPIO_93_PULLUP      PULLUP_DISABLE
+#define GPIO_94_PULLUP      PULLUP_DISABLE
+#define GPIO_95_PULLUP      PULLUP_DISABLE
+#define GPIO_96_PULLUP      PULLUP_DISABLE
+#define GPIO_97_PULLUP      PULLUP_DISABLE
+#define GPIO_98_PULLUP      PULLUP_DISABLE
+#define GPIO_99_PULLUP      PULLUP_DISABLE
+#define GPIO_100_PULLUP     PULLUP_DISABLE
+#define GPIO_101_PULLUP     PULLUP_DISABLE
+#define GPIO_102_PULLUP     PULLUP_DISABLE
+#define GPIO_103_PULLUP     PULLUP_DISABLE
+#define GPIO_104_PULLUP     PULLUP_DISABLE
+#define GPIO_105_PULLUP     PULLUP_DISABLE
+#define GPIO_106_PULLUP     PULLUP_DISABLE
+#define GPIO_107_PULLUP     PULLUP_DISABLE
+#define GPIO_108_PULLUP     PULLUP_DISABLE
+#define GPIO_109_PULLUP     PULLUP_DISABLE
+#define GPIO_110_PULLUP     PULLUP_DISABLE
+#define GPIO_111_PULLUP     PULLUP_DISABLE
+#define GPIO_112_PULLUP     PULLUP_DISABLE
+#define GPIO_113_PULLUP     PULLUP_DISABLE
+#define GPIO_114_PULLUP     PULLUP_DISABLE
+#define GPIO_115_PULLUP     PULLUP_DISABLE
+#define GPIO_116_PULLUP     PULLUP_DISABLE
+#define GPIO_117_PULLUP     PULLUP_DISABLE
+#define GPIO_118_PULLUP     PULLUP_ENABLE
+#define GPIO_119_PULLUP     PULLUP_DISABLE
+#define GPIO_120_PULLUP     PULLUP_DISABLE
+#define GPIO_121_PULLUP     PULLUP_DISABLE
+#define GPIO_122_PULLUP     PULLUP_DISABLE
+#define GPIO_123_PULLUP     PULLUP_DISABLE
+#define GPIO_124_PULLUP     PULLUP_DISABLE
+#define GPIO_125_PULLUP     PULLUP_DISABLE
+#define GPIO_126_PULLUP     PULLUP_DISABLE
+#define GPIO_127_PULLUP     PULLUP_DISABLE
+#define GPIO_128_PULLUP     PULLUP_DISABLE
+#define GPIO_129_PULLUP     PULLUP_DISABLE
+#define GPIO_130_PULLUP     PULLUP_DISABLE
+#define GPIO_131_PULLUP     PULLUP_DISABLE
+#define GPIO_132_PULLUP     PULLUP_DISABLE
+#define GPIO_133_PULLUP     PULLUP_DISABLE
+#define GPIO_134_PULLUP     PULLUP_DISABLE
+#define GPIO_135_PULLUP     PULLUP_DISABLE
+#define GPIO_136_PULLUP     PULLUP_DISABLE
+#define GPIO_137_PULLUP     PULLUP_DISABLE
+#define GPIO_138_PULLUP     PULLUP_DISABLE
+#define GPIO_139_PULLUP     PULLUP_DISABLE
+#define GPIO_140_PULLUP     PULLUP_DISABLE
+#define GPIO_141_PULLUP     PULLUP_DISABLE
+#define GPIO_142_PULLUP     PULLUP_DISABLE
+#define GPIO_143_PULLUP     PULLUP_DISABLE
+#define GPIO_144_PULLUP     PULLUP_DISABLE
+#define GPIO_145_PULLUP     PULLUP_DISABLE
+#define GPIO_146_PULLUP     PULLUP_DISABLE
+#define GPIO_147_PULLUP     PULLUP_DISABLE
+#define GPIO_148_PULLUP     PULLUP_DISABLE
+#define GPIO_149_PULLUP     PULLUP_DISABLE
+#define GPIO_150_PULLUP     PULLUP_DISABLE
+#define GPIO_151_PULLUP     PULLUP_DISABLE
+#define GPIO_152_PULLUP     PULLUP_DISABLE
+#define GPIO_153_PULLUP     PULLUP_DISABLE
+#define GPIO_154_PULLUP     PULLUP_DISABLE
+#define GPIO_155_PULLUP     PULLUP_DISABLE
+#define GPIO_156_PULLUP     PULLUP_DISABLE
+#define GPIO_157_PULLUP     PULLUP_DISABLE
+#define GPIO_158_PULLUP     PULLUP_DISABLE
+#define GPIO_159_PULLUP     PULLUP_DISABLE
+#define GPIO_160_PULLUP     PULLUP_DISABLE
+#define GPIO_161_PULLUP     PULLUP_DISABLE
+#define GPIO_162_PULLUP     PULLUP_DISABLE
+#define GPIO_163_PULLUP     PULLUP_DISABLE
+#define GPIO_164_PULLUP     PULLUP_DISABLE
+#define GPIO_165_PULLUP     PULLUP_DISABLE
+#define GPIO_166_PULLUP     PULLUP_DISABLE
+#define GPIO_167_PULLUP     PULLUP_DISABLE
+#define GPIO_168_PULLUP     PULLUP_DISABLE
+#define GPIO_169_PULLUP     PULLUP_DISABLE
+#define GPIO_170_PULLUP     PULLUP_DISABLE
+#define GPIO_171_PULLUP     PULLUP_DISABLE
+#define GPIO_172_PULLUP     PULLUP_DISABLE
+#define GPIO_173_PULLUP     PULLUP_DISABLE
+#define GPIO_174_PULLUP     PULLUP_DISABLE
+#define GPIO_175_PULLUP     PULLUP_DISABLE
+#define GPIO_176_PULLUP     PULLUP_DISABLE
+#define GPIO_177_PULLUP     PULLUP_DISABLE
+#define GPIO_178_PULLUP     PULLUP_DISABLE
+#define GPIO_179_PULLUP     PULLUP_DISABLE
+#define GPIO_180_PULLUP     PULLUP_DISABLE
+#define GPIO_180_PULLUP     PULLUP_DISABLE
+#define GPIO_181_PULLUP     PULLUP_DISABLE
+#define GPIO_182_PULLUP     PULLUP_DISABLE
+#define GPIO_183_PULLUP     PULLUP_DISABLE
+#define GPIO_184_PULLUP     PULLUP_DISABLE
+#define GPIO_185_PULLUP     PULLUP_DISABLE
+#define GPIO_186_PULLUP     PULLUP_DISABLE
+#define GPIO_187_PULLUP     PULLUP_DISABLE
+#define GPIO_188_PULLUP     PULLUP_DISABLE
+#define GPIO_189_PULLUP     PULLUP_DISABLE
+#define GPIO_190_PULLUP     PULLUP_DISABLE
+#define GPIO_191_PULLUP     PULLUP_DISABLE
+#define GPIO_192_PULLUP     PULLUP_DISABLE
+#define GPIO_193_PULLUP     PULLUP_DISABLE
+#define GPIO_194_PULLUP     PULLUP_DISABLE
+#define GPIO_195_PULLUP     PULLUP_DISABLE
+#define GPIO_196_PULLUP     PULLUP_DISABLE
+#define GPIO_197_PULLUP     PULLUP_DISABLE
+#define GPIO_198_PULLUP     PULLUP_DISABLE
+#define GPIO_199_PULLUP     PULLUP_DISABLE
+#define GPIO_200_PULLUP     PULLUP_DISABLE
+#define GPIO_201_PULLUP     PULLUP_DISABLE
+#define GPIO_202_PULLUP     PULLUP_DISABLE
+#define GPIO_203_PULLUP     PULLUP_DISABLE
+#define GPIO_204_PULLUP     PULLUP_DISABLE
+#define GPIO_205_PULLUP     PULLUP_DISABLE
+#define GPIO_206_PULLUP     PULLUP_DISABLE
+#define GPIO_207_PULLUP     PULLUP_DISABLE
+#define GPIO_208_PULLUP     PULLUP_DISABLE
+#define GPIO_209_PULLUP     PULLUP_DISABLE
+#define GPIO_210_PULLUP     PULLUP_DISABLE
+#define GPIO_211_PULLUP     PULLUP_DISABLE
+#define GPIO_212_PULLUP     PULLUP_DISABLE
+#define GPIO_213_PULLUP     PULLUP_DISABLE
+#define GPIO_214_PULLUP     PULLUP_DISABLE
+#define GPIO_215_PULLUP     PULLUP_DISABLE
+#define GPIO_216_PULLUP     PULLUP_DISABLE
+#define GPIO_217_PULLUP     PULLUP_DISABLE
+#define GPIO_218_PULLUP     PULLUP_DISABLE
+#define GPIO_219_PULLUP     PULLUP_DISABLE
+#define GPIO_220_PULLUP     PULLUP_DISABLE
+#define GPIO_221_PULLUP     PULLUP_DISABLE
+#define GPIO_222_PULLUP     PULLUP_DISABLE
+#define GPIO_223_PULLUP     PULLUP_DISABLE
+#define GPIO_224_PULLUP     PULLUP_DISABLE
+#define GPIO_225_PULLUP     PULLUP_DISABLE
+#define GPIO_226_PULLUP     PULLUP_DISABLE
+#define GPIO_227_PULLUP     PULLUP_DISABLE
+#define GPIO_228_PULLUP     PULLUP_DISABLE
+#define GPIO_229_PULLUP     PULLUP_DISABLE
+
+#define PULLDOWN_ENABLE       (1<<4)
+#define PULLDOWN_DISABLE      (0<<4)
+
+#define GPIO_00_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_01_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_02_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_03_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_04_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_05_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_06_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_07_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_08_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_09_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_10_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_11_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_12_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_13_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_14_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_15_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_16_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_17_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_18_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_19_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_20_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_21_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_22_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_23_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_24_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_25_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_26_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_27_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_28_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_29_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_30_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_31_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_32_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_33_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_34_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_35_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_36_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_37_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_38_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_39_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_40_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_41_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_42_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_43_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_44_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_45_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_46_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_47_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_48_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_49_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_50_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_51_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_52_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_53_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_54_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_55_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_56_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_57_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_58_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_59_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_60_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_61_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_62_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_63_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_64_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_65_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_66_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_67_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_68_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_69_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_70_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_71_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_72_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_73_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_74_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_75_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_76_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_77_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_78_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_79_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_80_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_80_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_81_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_82_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_83_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_84_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_85_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_86_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_87_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_88_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_89_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_90_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_91_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_92_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_93_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_94_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_95_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_96_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_97_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_98_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_99_PULLDOWN    PULLDOWN_DISABLE
+#define GPIO_100_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_101_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_102_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_103_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_104_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_105_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_106_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_107_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_108_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_109_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_110_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_111_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_112_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_113_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_114_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_115_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_116_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_117_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_118_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_119_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_120_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_121_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_122_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_123_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_124_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_125_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_126_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_127_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_128_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_129_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_130_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_131_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_132_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_133_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_134_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_135_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_136_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_137_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_138_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_139_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_140_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_141_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_142_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_143_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_144_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_145_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_146_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_147_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_148_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_149_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_150_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_151_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_152_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_153_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_154_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_155_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_156_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_157_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_158_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_159_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_160_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_161_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_162_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_163_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_164_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_165_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_166_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_167_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_168_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_169_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_170_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_171_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_172_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_173_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_174_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_175_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_176_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_177_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_178_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_179_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_180_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_180_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_181_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_182_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_183_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_184_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_185_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_186_PULLDOWN   PULLDOWN_ENABLE
+#define GPIO_187_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_188_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_189_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_190_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_191_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_192_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_193_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_194_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_195_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_196_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_197_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_198_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_199_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_200_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_201_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_202_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_203_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_204_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_205_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_206_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_207_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_208_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_209_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_210_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_211_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_212_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_213_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_214_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_215_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_216_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_217_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_218_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_219_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_220_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_221_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_222_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_223_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_224_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_225_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_226_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_227_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_228_PULLDOWN   PULLDOWN_DISABLE
+#define GPIO_229_PULLDOWN   PULLDOWN_DISABLE
+
+#define EVENT_DISABLE           0
+#define EVENT_ENABLE            1
+
+#define GEVENT_00_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_01_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_02_EVENTENABLE   EVENT_ENABLE	// APU THERMTRIP#
+#define GEVENT_03_EVENTENABLE   EVENT_ENABLE    // EC_SCI#
+#define GEVENT_04_EVENTENABLE   EVENT_ENABLE    // APU_MEMHOT#
+#define GEVENT_05_EVENTENABLE   EVENT_ENABLE    // PCIE_EXPCARD_PWREN#
+#define GEVENT_06_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_07_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_08_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_09_EVENTENABLE   EVENT_ENABLE    // WF_RADIO
+#define GEVENT_10_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_11_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_12_EVENTENABLE   EVENT_ENABLE    // SMBALERT#
+#define GEVENT_13_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_14_EVENTENABLE   EVENT_ENABLE    // LASSO_DET#/DOCK#
+#define GEVENT_15_EVENTENABLE   EVENT_ENABLE    // ODD_PLUGIN#
+#define GEVENT_16_EVENTENABLE   EVENT_ENABLE    // ODD_DA
+#define GEVENT_17_EVENTENABLE   EVENT_ENABLE    // TWARN
+#define GEVENT_18_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_19_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_20_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_21_EVENTENABLE   EVENT_DISABLE
+#define GEVENT_22_EVENTENABLE   EVENT_ENABLE    // LID_CLOSE#
+#define GEVENT_23_EVENTENABLE   EVENT_DISABLE   // EC_SMI#
+
+#define SCITRIG_LOW             0
+#define SCITRIG_HI              1
+
+#define GEVENT_00_SCITRIG       SCITRIG_LOW
+#define GEVENT_01_SCITRIG       SCITRIG_LOW
+#define GEVENT_02_SCITRIG       SCITRIG_LOW
+#define GEVENT_03_SCITRIG       SCITRIG_LOW
+#define GEVENT_04_SCITRIG       SCITRIG_LOW
+#define GEVENT_05_SCITRIG       SCITRIG_LOW
+#define GEVENT_06_SCITRIG       SCITRIG_LOW
+#define GEVENT_07_SCITRIG       SCITRIG_LOW
+#define GEVENT_08_SCITRIG       SCITRIG_LOW
+#define GEVENT_09_SCITRIG       SCITRIG_LOW
+#define GEVENT_10_SCITRIG       SCITRIG_LOW
+#define GEVENT_11_SCITRIG       SCITRIG_LOW
+#define GEVENT_12_SCITRIG       SCITRIG_LOW
+#define GEVENT_13_SCITRIG       SCITRIG_LOW
+#define GEVENT_14_SCITRIG       SCITRIG_LOW
+#define GEVENT_15_SCITRIG       SCITRIG_LOW
+#define GEVENT_16_SCITRIG       SCITRIG_LOW
+#define GEVENT_17_SCITRIG       SCITRIG_HI
+#define GEVENT_18_SCITRIG       SCITRIG_LOW
+#define GEVENT_19_SCITRIG       SCITRIG_LOW
+#define GEVENT_20_SCITRIG       SCITRIG_LOW
+#define GEVENT_21_SCITRIG       SCITRIG_LOW
+#define GEVENT_22_SCITRIG       SCITRIG_LOW
+#define GEVENT_23_SCITRIG       SCITRIG_LOW
+
+#define SCILEVEL_EDGE           0
+#define SCILEVEL_LEVEL          1
+
+#define GEVENT_00_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_01_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_02_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_03_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_04_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_05_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_06_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_07_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_08_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_09_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_10_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_11_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_12_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_13_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_14_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_15_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_16_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_17_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_18_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_19_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_20_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_21_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_22_SCILEVEL      SCILEVEL_EDGE
+#define GEVENT_23_SCILEVEL      SCILEVEL_EDGE
+
+#define SMISCI_DISABLE          0
+#define SMISCI_ENABLE           1
+
+#define GEVENT_00_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_01_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_02_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_03_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_04_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_05_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_06_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_07_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_08_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_09_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_10_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_11_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_12_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_13_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_14_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_15_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_16_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_17_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_18_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_19_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_20_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_21_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_22_SMISCIEN      SMISCI_DISABLE
+#define GEVENT_23_SMISCIEN      SMISCI_DISABLE
+
+#define SCIS0_DISABLE           0
+#define SCIS0_ENABLE            1
+
+#define GEVENT_00_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_01_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_02_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_03_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_04_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_05_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_06_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_07_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_08_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_09_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_10_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_11_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_12_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_13_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_14_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_15_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_16_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_17_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_18_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_19_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_20_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_21_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_22_SCIS0EN       SCIS0_DISABLE
+#define GEVENT_23_SCIS0EN       SCIS0_DISABLE
+
+#define GEVENT_SCIMASK          0x1F
+#define GEVENT_00_SCIMAP        0
+#define GEVENT_01_SCIMAP        1
+#define GEVENT_02_SCIMAP        2
+#define GEVENT_03_SCIMAP        3
+#define GEVENT_04_SCIMAP        4
+#define GEVENT_05_SCIMAP        5
+#define GEVENT_06_SCIMAP        6
+#define GEVENT_07_SCIMAP        7
+#define GEVENT_08_SCIMAP        8
+#define GEVENT_09_SCIMAP        9
+#define GEVENT_10_SCIMAP        10
+#define GEVENT_11_SCIMAP        11
+#define GEVENT_12_SCIMAP        12
+#define GEVENT_13_SCIMAP        13
+#define GEVENT_14_SCIMAP        14
+#define GEVENT_15_SCIMAP        15
+#define GEVENT_16_SCIMAP        16
+#define GEVENT_17_SCIMAP        17
+#define GEVENT_18_SCIMAP        18
+#define GEVENT_19_SCIMAP        19
+#define GEVENT_20_SCIMAP        20
+#define GEVENT_21_SCIMAP        21
+#define GEVENT_22_SCIMAP        22
+#define GEVENT_23_SCIMAP        23
+
+#define SMITRIG_LOW             0
+#define SMITRIG_HI              1
+
+#define GEVENT_00_SMITRIG       SMITRIG_HI
+#define GEVENT_01_SMITRIG       SMITRIG_HI
+#define GEVENT_02_SMITRIG       SMITRIG_HI
+#define GEVENT_03_SMITRIG       SMITRIG_HI
+#define GEVENT_04_SMITRIG       SMITRIG_HI
+#define GEVENT_05_SMITRIG       SMITRIG_HI
+#define GEVENT_06_SMITRIG       SMITRIG_HI
+#define GEVENT_07_SMITRIG       SMITRIG_HI
+#define GEVENT_08_SMITRIG       SMITRIG_HI
+#define GEVENT_09_SMITRIG       SMITRIG_HI
+#define GEVENT_10_SMITRIG       SMITRIG_HI
+#define GEVENT_11_SMITRIG       SMITRIG_HI
+#define GEVENT_12_SMITRIG       SMITRIG_HI
+#define GEVENT_13_SMITRIG       SMITRIG_HI
+#define GEVENT_14_SMITRIG       SMITRIG_HI
+#define GEVENT_15_SMITRIG       SMITRIG_HI
+#define GEVENT_16_SMITRIG       SMITRIG_HI
+#define GEVENT_17_SMITRIG       SMITRIG_HI
+#define GEVENT_18_SMITRIG       SMITRIG_HI
+#define GEVENT_19_SMITRIG       SMITRIG_HI
+#define GEVENT_20_SMITRIG       SMITRIG_HI
+#define GEVENT_21_SMITRIG       SMITRIG_HI
+#define GEVENT_22_SMITRIG       SMITRIG_HI
+#define GEVENT_23_SMITRIG       SMITRIG_HI
+
+#define SMICONTROL_MASK         3
+#define SMICONTROL_DISABLE      0
+#define SMICONTROL_SMI          1
+#define SMICONTROL_NMI          2
+#define SMICONTROL_IRQ13        3
+
+#define GEVENT_00_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_01_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_02_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_03_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_04_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_05_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_06_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_07_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_08_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_09_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_10_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_11_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_12_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_13_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_14_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_15_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_16_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_17_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_18_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_19_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_20_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_21_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_22_SMICONTROL    SMICONTROL_DISABLE
+#define GEVENT_23_SMICONTROL    SMICONTROL_DISABLE
+
+#define GPIO_RSVD_ZONE0_S   GPIO_81
+#define GPIO_RSVD_ZONE0_E   GPIO_95
+#define GPIO_RSVD_ZONE1_S   GPIO_120
+#define GPIO_RSVD_ZONE1_E   GPIO_127
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+typedef enum _GPIO_COUNT
+{
+	GPIO_00=0,
+	GPIO_01,
+	GPIO_02,
+	GPIO_03,
+	GPIO_04,
+	GPIO_05,
+	GPIO_06,
+	GPIO_07,
+	GPIO_08,
+	GPIO_09,
+	GPIO_10,
+	GPIO_11,
+	GPIO_12,
+	GPIO_13,
+	GPIO_14,
+	GPIO_15,
+	GPIO_16,
+	GPIO_17,
+	GPIO_18,
+	GPIO_19,
+	GPIO_20,
+	GPIO_21,
+	GPIO_22,
+	GPIO_23,
+	GPIO_24,
+	GPIO_25,
+	GPIO_26,
+	GPIO_27,
+	GPIO_28,
+	GPIO_29,
+	GPIO_30,
+	GPIO_31,
+	GPIO_32,
+	GPIO_33,
+	GPIO_34,
+	GPIO_35,
+	GPIO_36,
+	GPIO_37,
+	GPIO_38,
+	GPIO_39,
+	GPIO_40,
+	GPIO_41,
+	GPIO_42,
+	GPIO_43,
+	GPIO_44,
+	GPIO_45,
+	GPIO_46,
+	GPIO_47,
+	GPIO_48,
+	GPIO_49,
+	GPIO_50,
+	GPIO_51,
+	GPIO_52,
+	GPIO_53,
+	GPIO_54,
+	GPIO_55,
+	GPIO_56,
+	GPIO_57,
+	GPIO_58,
+	GPIO_59,
+	GPIO_60,
+	GPIO_61,
+	GPIO_62,
+	GPIO_63,
+	GPIO_64,
+	GPIO_65,
+	GPIO_66,
+	GPIO_67,
+	GPIO_68,
+	GPIO_69,
+	GPIO_70,
+	GPIO_71,
+	GPIO_72,
+	GPIO_73,
+	GPIO_74,
+	GPIO_75,
+	GPIO_76,
+	GPIO_77,
+	GPIO_78,
+	GPIO_79,
+	GPIO_80,
+	GPIO_81,
+	GPIO_82,
+	GPIO_83,
+	GPIO_84,
+	GPIO_85,
+	GPIO_86,
+	GPIO_87,
+	GPIO_88,
+	GPIO_89,
+	GPIO_90,
+	GPIO_91,
+	GPIO_92,
+	GPIO_93,
+	GPIO_94,
+	GPIO_95,
+	GPIO_96,
+	GPIO_97,
+	GPIO_98,
+	GPIO_99,
+	GPIO_100,
+	GPIO_101,
+	GPIO_102,
+	GPIO_103,
+	GPIO_104,
+	GPIO_105,
+	GPIO_106,
+	GPIO_107,
+	GPIO_108,
+	GPIO_109,
+	GPIO_110,
+	GPIO_111,
+	GPIO_112,
+	GPIO_113,
+	GPIO_114,
+	GPIO_115,
+	GPIO_116,
+	GPIO_117,
+	GPIO_118,
+	GPIO_119,
+	GPIO_120,
+	GPIO_121,
+	GPIO_122,
+	GPIO_123,
+	GPIO_124,
+	GPIO_125,
+	GPIO_126,
+	GPIO_127,
+	GPIO_128,
+	GPIO_129,
+	GPIO_130,
+	GPIO_131,
+	GPIO_132,
+	GPIO_133,
+	GPIO_134,
+	GPIO_135,
+	GPIO_136,
+	GPIO_137,
+	GPIO_138,
+	GPIO_139,
+	GPIO_140,
+	GPIO_141,
+	GPIO_142,
+	GPIO_143,
+	GPIO_144,
+	GPIO_145,
+	GPIO_146,
+	GPIO_147,
+	GPIO_148,
+	GPIO_149,
+	GPIO_150,
+	GPIO_151,
+	GPIO_152,
+	GPIO_153,
+	GPIO_154,
+	GPIO_155,
+	GPIO_156,
+	GPIO_157,
+	GPIO_158,
+	GPIO_159,
+	GPIO_160,
+	GPIO_161,
+	GPIO_162,
+	GPIO_163,
+	GPIO_164,
+	GPIO_165,
+	GPIO_166,
+	GPIO_167,
+	GPIO_168,
+	GPIO_169,
+	GPIO_170,
+	GPIO_171,
+	GPIO_172,
+	GPIO_173,
+	GPIO_174,
+	GPIO_175,
+	GPIO_176,
+	GPIO_177,
+	GPIO_178,
+	GPIO_179,
+	GPIO_180,
+	GPIO_181,
+	GPIO_182,
+	GPIO_183,
+	GPIO_184,
+	GPIO_185,
+	GPIO_186,
+	GPIO_187,
+	GPIO_188,
+	GPIO_189,
+	GPIO_190,
+	GPIO_191,
+	GPIO_192,
+	GPIO_193,
+	GPIO_194,
+	GPIO_195,
+	GPIO_196,
+	GPIO_197,
+	GPIO_198,
+	GPIO_199,
+	GPIO_200,
+	GPIO_201,
+	GPIO_202,
+	GPIO_203,
+	GPIO_204,
+	GPIO_205,
+	GPIO_206,
+	GPIO_207,
+	GPIO_208,
+	GPIO_209,
+	GPIO_210,
+	GPIO_211,
+	GPIO_212,
+	GPIO_213,
+	GPIO_214,
+	GPIO_215,
+	GPIO_216,
+	GPIO_217,
+	GPIO_218,
+	GPIO_219,
+	GPIO_220,
+	GPIO_221,
+	GPIO_222,
+	GPIO_223,
+	GPIO_224,
+	GPIO_225,
+	GPIO_226,
+	GPIO_227,
+	GPIO_228,
+	GPIO_229,
+	MAX_GPIO_NO
+} GPIO_COUNT;
+
+typedef struct _GPIO_SETTINGS
+{
+	u8 select;
+	u8 type;
+	u8 value;
+	u8 NonGpioGevent;
+} GPIO_SETTINGS;
+
+GPIO_SETTINGS gpio_table[]=
+{
+	{GPIO_00_SELECT, GPIO_00_TYPE, GPO_00_LEVEL+GPIO_00_STICKY+GPIO_00_PULLUP+GPIO_00_PULLDOWN, GPIO_00_SELECT},
+	{GPIO_01_SELECT, GPIO_01_TYPE, GPO_01_LEVEL+GPIO_01_STICKY+GPIO_01_PULLUP+GPIO_01_PULLDOWN, GPIO_01_SELECT},
+	{GPIO_02_SELECT, GPIO_02_TYPE, GPO_02_LEVEL+GPIO_02_STICKY+GPIO_02_PULLUP+GPIO_02_PULLDOWN, GPIO_02_SELECT},
+	{GPIO_03_SELECT, GPIO_03_TYPE, GPO_03_LEVEL+GPIO_03_STICKY+GPIO_03_PULLUP+GPIO_03_PULLDOWN, GPIO_03_SELECT},
+	{GPIO_04_SELECT, GPIO_04_TYPE, GPO_04_LEVEL+GPIO_04_STICKY+GPIO_04_PULLUP+GPIO_04_PULLDOWN, GPIO_04_SELECT},
+	{GPIO_05_SELECT, GPIO_05_TYPE, GPO_05_LEVEL+GPIO_05_STICKY+GPIO_05_PULLUP+GPIO_05_PULLDOWN, GPIO_05_SELECT},
+	{GPIO_06_SELECT, GPIO_06_TYPE, GPO_06_LEVEL+GPIO_06_STICKY+GPIO_06_PULLUP+GPIO_06_PULLDOWN, GPIO_06_SELECT},
+	{GPIO_07_SELECT, GPIO_07_TYPE, GPO_07_LEVEL+GPIO_07_STICKY+GPIO_07_PULLUP+GPIO_07_PULLDOWN, GPIO_07_SELECT},
+	{GPIO_08_SELECT, GPIO_08_TYPE, GPO_08_LEVEL+GPIO_08_STICKY+GPIO_08_PULLUP+GPIO_08_PULLDOWN, GPIO_08_SELECT},
+	{GPIO_09_SELECT, GPIO_09_TYPE, GPO_09_LEVEL+GPIO_09_STICKY+GPIO_09_PULLUP+GPIO_09_PULLDOWN, GPIO_09_SELECT},
+	{GPIO_10_SELECT, GPIO_10_TYPE, GPO_10_LEVEL+GPIO_10_STICKY+GPIO_10_PULLUP+GPIO_10_PULLDOWN, GPIO_10_SELECT},
+	{GPIO_11_SELECT, GPIO_11_TYPE, GPO_11_LEVEL+GPIO_11_STICKY+GPIO_11_PULLUP+GPIO_11_PULLDOWN, GPIO_11_SELECT},
+	{GPIO_12_SELECT, GPIO_12_TYPE, GPO_12_LEVEL+GPIO_12_STICKY+GPIO_12_PULLUP+GPIO_12_PULLDOWN, GPIO_12_SELECT},
+	{GPIO_13_SELECT, GPIO_13_TYPE, GPO_13_LEVEL+GPIO_13_STICKY+GPIO_13_PULLUP+GPIO_13_PULLDOWN, GPIO_13_SELECT},
+	{GPIO_14_SELECT, GPIO_14_TYPE, GPO_14_LEVEL+GPIO_14_STICKY+GPIO_14_PULLUP+GPIO_14_PULLDOWN, GPIO_14_SELECT},
+	{GPIO_15_SELECT, GPIO_15_TYPE, GPO_15_LEVEL+GPIO_15_STICKY+GPIO_15_PULLUP+GPIO_15_PULLDOWN, GPIO_15_SELECT},
+	{GPIO_16_SELECT, GPIO_16_TYPE, GPO_16_LEVEL+GPIO_16_STICKY+GPIO_16_PULLUP+GPIO_16_PULLDOWN, GPIO_16_SELECT},
+	{GPIO_17_SELECT, GPIO_17_TYPE, GPO_17_LEVEL+GPIO_17_STICKY+GPIO_17_PULLUP+GPIO_17_PULLDOWN, GPIO_17_SELECT},
+	{GPIO_18_SELECT, GPIO_18_TYPE, GPO_18_LEVEL+GPIO_18_STICKY+GPIO_18_PULLUP+GPIO_18_PULLDOWN, GPIO_18_SELECT},
+	{GPIO_19_SELECT, GPIO_19_TYPE, GPO_19_LEVEL+GPIO_19_STICKY+GPIO_19_PULLUP+GPIO_19_PULLDOWN, GPIO_19_SELECT},
+	{GPIO_20_SELECT, GPIO_20_TYPE, GPO_20_LEVEL+GPIO_20_STICKY+GPIO_20_PULLUP+GPIO_20_PULLDOWN, GPIO_20_SELECT},
+	{GPIO_21_SELECT, GPIO_21_TYPE, GPO_21_LEVEL+GPIO_21_STICKY+GPIO_21_PULLUP+GPIO_21_PULLDOWN, GPIO_21_SELECT},
+	{GPIO_22_SELECT, GPIO_22_TYPE, GPO_22_LEVEL+GPIO_22_STICKY+GPIO_22_PULLUP+GPIO_22_PULLDOWN, GPIO_22_SELECT},
+	{GPIO_23_SELECT, GPIO_23_TYPE, GPO_23_LEVEL+GPIO_23_STICKY+GPIO_23_PULLUP+GPIO_23_PULLDOWN, GPIO_23_SELECT},
+	{GPIO_24_SELECT, GPIO_24_TYPE, GPO_24_LEVEL+GPIO_24_STICKY+GPIO_24_PULLUP+GPIO_24_PULLDOWN, GPIO_24_SELECT},
+	{GPIO_25_SELECT, GPIO_25_TYPE, GPO_25_LEVEL+GPIO_25_STICKY+GPIO_25_PULLUP+GPIO_25_PULLDOWN, GPIO_25_SELECT},
+	{GPIO_26_SELECT, GPIO_26_TYPE, GPO_26_LEVEL+GPIO_26_STICKY+GPIO_26_PULLUP+GPIO_26_PULLDOWN, GPIO_26_SELECT},
+	{GPIO_27_SELECT, GPIO_27_TYPE, GPO_27_LEVEL+GPIO_27_STICKY+GPIO_27_PULLUP+GPIO_27_PULLDOWN, GPIO_27_SELECT},
+	{GPIO_28_SELECT, GPIO_28_TYPE, GPO_28_LEVEL+GPIO_28_STICKY+GPIO_28_PULLUP+GPIO_28_PULLDOWN, GPIO_28_SELECT},
+	{GPIO_29_SELECT, GPIO_29_TYPE, GPO_29_LEVEL+GPIO_29_STICKY+GPIO_29_PULLUP+GPIO_29_PULLDOWN, GPIO_29_SELECT},
+	{GPIO_30_SELECT, GPIO_30_TYPE, GPO_30_LEVEL+GPIO_30_STICKY+GPIO_30_PULLUP+GPIO_30_PULLDOWN, GPIO_30_SELECT},
+	{GPIO_31_SELECT, GPIO_31_TYPE, GPO_31_LEVEL+GPIO_31_STICKY+GPIO_31_PULLUP+GPIO_31_PULLDOWN, GPIO_31_SELECT},
+	{GPIO_32_SELECT, GPIO_32_TYPE, GPO_32_LEVEL+GPIO_32_STICKY+GPIO_32_PULLUP+GPIO_32_PULLDOWN, GPIO_32_SELECT},
+	{GPIO_33_SELECT, GPIO_33_TYPE, GPO_33_LEVEL+GPIO_33_STICKY+GPIO_33_PULLUP+GPIO_33_PULLDOWN, GPIO_33_SELECT},
+	{GPIO_34_SELECT, GPIO_34_TYPE, GPO_34_LEVEL+GPIO_34_STICKY+GPIO_34_PULLUP+GPIO_34_PULLDOWN, GPIO_34_SELECT},
+	{GPIO_35_SELECT, GPIO_35_TYPE, GPO_35_LEVEL+GPIO_35_STICKY+GPIO_35_PULLUP+GPIO_35_PULLDOWN, GPIO_35_SELECT},
+	{GPIO_36_SELECT, GPIO_36_TYPE, GPO_36_LEVEL+GPIO_36_STICKY+GPIO_36_PULLUP+GPIO_36_PULLDOWN, GPIO_36_SELECT},
+	{GPIO_37_SELECT, GPIO_37_TYPE, GPO_37_LEVEL+GPIO_37_STICKY+GPIO_37_PULLUP+GPIO_37_PULLDOWN, GPIO_37_SELECT},
+	{GPIO_38_SELECT, GPIO_38_TYPE, GPO_38_LEVEL+GPIO_38_STICKY+GPIO_38_PULLUP+GPIO_38_PULLDOWN, GPIO_38_SELECT},
+	{GPIO_39_SELECT, GPIO_39_TYPE, GPO_39_LEVEL+GPIO_39_STICKY+GPIO_39_PULLUP+GPIO_39_PULLDOWN, GPIO_39_SELECT},
+	{GPIO_40_SELECT, GPIO_40_TYPE, GPO_40_LEVEL+GPIO_40_STICKY+GPIO_40_PULLUP+GPIO_40_PULLDOWN, GPIO_40_SELECT},
+	{GPIO_41_SELECT, GPIO_41_TYPE, GPO_41_LEVEL+GPIO_41_STICKY+GPIO_41_PULLUP+GPIO_41_PULLDOWN, GPIO_41_SELECT},
+	{GPIO_42_SELECT, GPIO_42_TYPE, GPO_42_LEVEL+GPIO_42_STICKY+GPIO_42_PULLUP+GPIO_42_PULLDOWN, GPIO_42_SELECT},
+	{GPIO_43_SELECT, GPIO_43_TYPE, GPO_43_LEVEL+GPIO_43_STICKY+GPIO_43_PULLUP+GPIO_43_PULLDOWN, GPIO_43_SELECT},
+	{GPIO_44_SELECT, GPIO_44_TYPE, GPO_44_LEVEL+GPIO_44_STICKY+GPIO_44_PULLUP+GPIO_44_PULLDOWN, GPIO_44_SELECT},
+	{GPIO_45_SELECT, GPIO_45_TYPE, GPO_45_LEVEL+GPIO_45_STICKY+GPIO_45_PULLUP+GPIO_45_PULLDOWN, GPIO_45_SELECT},
+	{GPIO_46_SELECT, GPIO_46_TYPE, GPO_46_LEVEL+GPIO_46_STICKY+GPIO_46_PULLUP+GPIO_46_PULLDOWN, GPIO_46_SELECT},
+	{GPIO_47_SELECT, GPIO_47_TYPE, GPO_47_LEVEL+GPIO_47_STICKY+GPIO_47_PULLUP+GPIO_47_PULLDOWN, GPIO_47_SELECT},
+	{GPIO_48_SELECT, GPIO_48_TYPE, GPO_48_LEVEL+GPIO_48_STICKY+GPIO_48_PULLUP+GPIO_48_PULLDOWN, GPIO_48_SELECT},
+	{GPIO_49_SELECT, GPIO_49_TYPE, GPO_49_LEVEL+GPIO_49_STICKY+GPIO_49_PULLUP+GPIO_49_PULLDOWN, GPIO_49_SELECT},
+	{GPIO_50_SELECT, GPIO_50_TYPE, GPO_50_LEVEL+GPIO_50_STICKY+GPIO_50_PULLUP+GPIO_50_PULLDOWN, GPIO_50_SELECT},
+	{GPIO_51_SELECT, GPIO_51_TYPE, GPO_51_LEVEL+GPIO_51_STICKY+GPIO_51_PULLUP+GPIO_51_PULLDOWN, GPIO_51_SELECT},
+	{GPIO_52_SELECT, GPIO_52_TYPE, GPO_52_LEVEL+GPIO_52_STICKY+GPIO_52_PULLUP+GPIO_52_PULLDOWN, GPIO_52_SELECT},
+	{GPIO_53_SELECT, GPIO_53_TYPE, GPO_53_LEVEL+GPIO_53_STICKY+GPIO_53_PULLUP+GPIO_53_PULLDOWN, GPIO_53_SELECT},
+	{GPIO_54_SELECT, GPIO_54_TYPE, GPO_54_LEVEL+GPIO_54_STICKY+GPIO_54_PULLUP+GPIO_54_PULLDOWN, GPIO_54_SELECT},
+	{GPIO_55_SELECT, GPIO_55_TYPE, GPO_55_LEVEL+GPIO_55_STICKY+GPIO_55_PULLUP+GPIO_55_PULLDOWN, GPIO_55_SELECT},
+	{GPIO_56_SELECT, GPIO_56_TYPE, GPO_56_LEVEL+GPIO_56_STICKY+GPIO_56_PULLUP+GPIO_56_PULLDOWN, GPIO_56_SELECT},
+	{GPIO_57_SELECT, GPIO_57_TYPE, GPO_57_LEVEL+GPIO_57_STICKY+GPIO_57_PULLUP+GPIO_57_PULLDOWN, GPIO_57_SELECT},
+	{GPIO_58_SELECT, GPIO_58_TYPE, GPO_58_LEVEL+GPIO_58_STICKY+GPIO_58_PULLUP+GPIO_58_PULLDOWN, GPIO_58_SELECT},
+	{GPIO_59_SELECT, GPIO_59_TYPE, GPO_59_LEVEL+GPIO_59_STICKY+GPIO_59_PULLUP+GPIO_59_PULLDOWN, GPIO_59_SELECT},
+	{GPIO_60_SELECT, GPIO_60_TYPE, GPO_60_LEVEL+GPIO_60_STICKY+GPIO_60_PULLUP+GPIO_60_PULLDOWN, GPIO_60_SELECT},
+	{GPIO_61_SELECT, GPIO_61_TYPE, GPO_61_LEVEL+GPIO_61_STICKY+GPIO_61_PULLUP+GPIO_61_PULLDOWN, GPIO_61_SELECT},
+	{GPIO_62_SELECT, GPIO_62_TYPE, GPO_62_LEVEL+GPIO_62_STICKY+GPIO_62_PULLUP+GPIO_62_PULLDOWN, GPIO_62_SELECT},
+	{GPIO_63_SELECT, GPIO_63_TYPE, GPO_63_LEVEL+GPIO_63_STICKY+GPIO_63_PULLUP+GPIO_63_PULLDOWN, GPIO_63_SELECT},
+	{GPIO_64_SELECT, GPIO_64_TYPE, GPO_64_LEVEL+GPIO_64_STICKY+GPIO_64_PULLUP+GPIO_64_PULLDOWN, GPIO_64_SELECT},
+	{GPIO_65_SELECT, GPIO_65_TYPE, GPO_65_LEVEL+GPIO_65_STICKY+GPIO_65_PULLUP+GPIO_65_PULLDOWN, GPIO_65_SELECT},
+	{GPIO_66_SELECT, GPIO_66_TYPE, GPO_66_LEVEL+GPIO_66_STICKY+GPIO_66_PULLUP+GPIO_66_PULLDOWN, GPIO_66_SELECT},
+	{GPIO_67_SELECT, GPIO_67_TYPE, GPO_67_LEVEL+GPIO_67_STICKY+GPIO_67_PULLUP+GPIO_67_PULLDOWN, GPIO_67_SELECT},
+	{GPIO_68_SELECT, GPIO_68_TYPE, GPO_68_LEVEL+GPIO_68_STICKY+GPIO_68_PULLUP+GPIO_68_PULLDOWN, GPIO_68_SELECT},
+	{GPIO_69_SELECT, GPIO_69_TYPE, GPO_69_LEVEL+GPIO_69_STICKY+GPIO_69_PULLUP+GPIO_69_PULLDOWN, GPIO_69_SELECT},
+	{GPIO_70_SELECT, GPIO_70_TYPE, GPO_70_LEVEL+GPIO_70_STICKY+GPIO_70_PULLUP+GPIO_70_PULLDOWN, GPIO_70_SELECT},
+	{GPIO_71_SELECT, GPIO_71_TYPE, GPO_71_LEVEL+GPIO_71_STICKY+GPIO_71_PULLUP+GPIO_71_PULLDOWN, GPIO_71_SELECT},
+	{GPIO_72_SELECT, GPIO_72_TYPE, GPO_72_LEVEL+GPIO_72_STICKY+GPIO_72_PULLUP+GPIO_72_PULLDOWN, GPIO_72_SELECT},
+	{GPIO_73_SELECT, GPIO_73_TYPE, GPO_73_LEVEL+GPIO_73_STICKY+GPIO_73_PULLUP+GPIO_73_PULLDOWN, GPIO_73_SELECT},
+	{GPIO_74_SELECT, GPIO_74_TYPE, GPO_74_LEVEL+GPIO_74_STICKY+GPIO_74_PULLUP+GPIO_74_PULLDOWN, GPIO_74_SELECT},
+	{GPIO_75_SELECT, GPIO_75_TYPE, GPO_75_LEVEL+GPIO_75_STICKY+GPIO_75_PULLUP+GPIO_75_PULLDOWN, GPIO_75_SELECT},
+	{GPIO_76_SELECT, GPIO_76_TYPE, GPO_76_LEVEL+GPIO_76_STICKY+GPIO_76_PULLUP+GPIO_76_PULLDOWN, GPIO_76_SELECT},
+	{GPIO_77_SELECT, GPIO_77_TYPE, GPO_77_LEVEL+GPIO_77_STICKY+GPIO_77_PULLUP+GPIO_77_PULLDOWN, GPIO_77_SELECT},
+	{GPIO_78_SELECT, GPIO_78_TYPE, GPO_78_LEVEL+GPIO_78_STICKY+GPIO_78_PULLUP+GPIO_78_PULLDOWN, GPIO_78_SELECT},
+	{GPIO_79_SELECT, GPIO_79_TYPE, GPO_79_LEVEL+GPIO_79_STICKY+GPIO_79_PULLUP+GPIO_79_PULLDOWN, GPIO_79_SELECT},
+	{GPIO_80_SELECT, GPIO_80_TYPE, GPO_80_LEVEL+GPIO_80_STICKY+GPIO_80_PULLUP+GPIO_80_PULLDOWN, GPIO_80_SELECT},
+	{GPIO_81_SELECT, GPIO_81_TYPE, GPO_81_LEVEL+GPIO_81_STICKY+GPIO_81_PULLUP+GPIO_81_PULLDOWN, GPIO_81_SELECT},
+	{GPIO_82_SELECT, GPIO_82_TYPE, GPO_82_LEVEL+GPIO_82_STICKY+GPIO_82_PULLUP+GPIO_82_PULLDOWN, GPIO_82_SELECT},
+	{GPIO_83_SELECT, GPIO_83_TYPE, GPO_83_LEVEL+GPIO_83_STICKY+GPIO_83_PULLUP+GPIO_83_PULLDOWN, GPIO_83_SELECT},
+	{GPIO_84_SELECT, GPIO_84_TYPE, GPO_84_LEVEL+GPIO_84_STICKY+GPIO_84_PULLUP+GPIO_84_PULLDOWN, GPIO_84_SELECT},
+	{GPIO_85_SELECT, GPIO_85_TYPE, GPO_85_LEVEL+GPIO_85_STICKY+GPIO_85_PULLUP+GPIO_85_PULLDOWN, GPIO_85_SELECT},
+	{GPIO_86_SELECT, GPIO_86_TYPE, GPO_86_LEVEL+GPIO_86_STICKY+GPIO_86_PULLUP+GPIO_86_PULLDOWN, GPIO_86_SELECT},
+	{GPIO_87_SELECT, GPIO_87_TYPE, GPO_87_LEVEL+GPIO_87_STICKY+GPIO_87_PULLUP+GPIO_87_PULLDOWN, GPIO_87_SELECT},
+	{GPIO_88_SELECT, GPIO_88_TYPE, GPO_88_LEVEL+GPIO_88_STICKY+GPIO_88_PULLUP+GPIO_88_PULLDOWN, GPIO_88_SELECT},
+	{GPIO_89_SELECT, GPIO_89_TYPE, GPO_89_LEVEL+GPIO_89_STICKY+GPIO_89_PULLUP+GPIO_89_PULLDOWN, GPIO_89_SELECT},
+	{GPIO_90_SELECT, GPIO_90_TYPE, GPO_90_LEVEL+GPIO_90_STICKY+GPIO_90_PULLUP+GPIO_90_PULLDOWN, GPIO_90_SELECT},
+	{GPIO_91_SELECT, GPIO_91_TYPE, GPO_91_LEVEL+GPIO_91_STICKY+GPIO_91_PULLUP+GPIO_91_PULLDOWN, GPIO_91_SELECT},
+	{GPIO_92_SELECT, GPIO_92_TYPE, GPO_92_LEVEL+GPIO_92_STICKY+GPIO_92_PULLUP+GPIO_92_PULLDOWN, GPIO_92_SELECT},
+	{GPIO_93_SELECT, GPIO_93_TYPE, GPO_93_LEVEL+GPIO_93_STICKY+GPIO_93_PULLUP+GPIO_93_PULLDOWN, GPIO_93_SELECT},
+	{GPIO_94_SELECT, GPIO_94_TYPE, GPO_94_LEVEL+GPIO_94_STICKY+GPIO_94_PULLUP+GPIO_94_PULLDOWN, GPIO_94_SELECT},
+	{GPIO_95_SELECT, GPIO_95_TYPE, GPO_95_LEVEL+GPIO_95_STICKY+GPIO_95_PULLUP+GPIO_95_PULLDOWN, GPIO_95_SELECT},
+	{GPIO_96_SELECT, GPIO_96_TYPE, GPO_96_LEVEL+GPIO_96_STICKY+GPIO_96_PULLUP+GPIO_96_PULLDOWN, GPIO_96_SELECT},
+	{GPIO_97_SELECT, GPIO_97_TYPE, GPO_97_LEVEL+GPIO_97_STICKY+GPIO_97_PULLUP+GPIO_97_PULLDOWN, GPIO_97_SELECT},
+	{GPIO_98_SELECT, GPIO_98_TYPE, GPO_98_LEVEL+GPIO_98_STICKY+GPIO_98_PULLUP+GPIO_98_PULLDOWN, GPIO_98_SELECT},
+	{GPIO_99_SELECT, GPIO_99_TYPE, GPO_99_LEVEL+GPIO_99_STICKY+GPIO_99_PULLUP+GPIO_99_PULLDOWN, GPIO_99_SELECT},
+	{GPIO_100_SELECT, GPIO_100_TYPE, GPO_100_LEVEL+GPIO_100_STICKY+GPIO_100_PULLUP+GPIO_100_PULLDOWN, GPIO_100_SELECT},
+	{GPIO_101_SELECT, GPIO_101_TYPE, GPO_101_LEVEL+GPIO_101_STICKY+GPIO_101_PULLUP+GPIO_101_PULLDOWN, GPIO_101_SELECT},
+	{GPIO_102_SELECT, GPIO_102_TYPE, GPO_102_LEVEL+GPIO_102_STICKY+GPIO_102_PULLUP+GPIO_102_PULLDOWN, GPIO_102_SELECT},
+	{GPIO_103_SELECT, GPIO_103_TYPE, GPO_103_LEVEL+GPIO_103_STICKY+GPIO_103_PULLUP+GPIO_103_PULLDOWN, GPIO_103_SELECT},
+	{GPIO_104_SELECT, GPIO_104_TYPE, GPO_104_LEVEL+GPIO_104_STICKY+GPIO_104_PULLUP+GPIO_104_PULLDOWN, GPIO_104_SELECT},
+	{GPIO_105_SELECT, GPIO_105_TYPE, GPO_105_LEVEL+GPIO_105_STICKY+GPIO_105_PULLUP+GPIO_105_PULLDOWN, GPIO_105_SELECT},
+	{GPIO_106_SELECT, GPIO_106_TYPE, GPO_106_LEVEL+GPIO_106_STICKY+GPIO_106_PULLUP+GPIO_106_PULLDOWN, GPIO_106_SELECT},
+	{GPIO_107_SELECT, GPIO_107_TYPE, GPO_107_LEVEL+GPIO_107_STICKY+GPIO_107_PULLUP+GPIO_107_PULLDOWN, GPIO_107_SELECT},
+	{GPIO_108_SELECT, GPIO_108_TYPE, GPO_108_LEVEL+GPIO_108_STICKY+GPIO_108_PULLUP+GPIO_108_PULLDOWN, GPIO_108_SELECT},
+	{GPIO_109_SELECT, GPIO_109_TYPE, GPO_109_LEVEL+GPIO_109_STICKY+GPIO_109_PULLUP+GPIO_109_PULLDOWN, GPIO_109_SELECT},
+	{GPIO_110_SELECT, GPIO_110_TYPE, GPO_110_LEVEL+GPIO_110_STICKY+GPIO_110_PULLUP+GPIO_110_PULLDOWN, GPIO_110_SELECT},
+	{GPIO_111_SELECT, GPIO_111_TYPE, GPO_111_LEVEL+GPIO_111_STICKY+GPIO_111_PULLUP+GPIO_111_PULLDOWN, GPIO_111_SELECT},
+	{GPIO_112_SELECT, GPIO_112_TYPE, GPO_112_LEVEL+GPIO_112_STICKY+GPIO_112_PULLUP+GPIO_112_PULLDOWN, GPIO_112_SELECT},
+	{GPIO_113_SELECT, GPIO_113_TYPE, GPO_113_LEVEL+GPIO_113_STICKY+GPIO_113_PULLUP+GPIO_113_PULLDOWN, GPIO_113_SELECT},
+	{GPIO_114_SELECT, GPIO_114_TYPE, GPO_114_LEVEL+GPIO_114_STICKY+GPIO_114_PULLUP+GPIO_114_PULLDOWN, GPIO_114_SELECT},
+	{GPIO_115_SELECT, GPIO_115_TYPE, GPO_115_LEVEL+GPIO_115_STICKY+GPIO_115_PULLUP+GPIO_115_PULLDOWN, GPIO_115_SELECT},
+	{GPIO_116_SELECT, GPIO_116_TYPE, GPO_116_LEVEL+GPIO_116_STICKY+GPIO_116_PULLUP+GPIO_116_PULLDOWN, GPIO_116_SELECT},
+	{GPIO_117_SELECT, GPIO_117_TYPE, GPO_117_LEVEL+GPIO_117_STICKY+GPIO_117_PULLUP+GPIO_117_PULLDOWN, GPIO_117_SELECT},
+	{GPIO_118_SELECT, GPIO_118_TYPE, GPO_118_LEVEL+GPIO_118_STICKY+GPIO_118_PULLUP+GPIO_118_PULLDOWN, GPIO_118_SELECT},
+	{GPIO_119_SELECT, GPIO_119_TYPE, GPO_119_LEVEL+GPIO_119_STICKY+GPIO_119_PULLUP+GPIO_119_PULLDOWN, GPIO_119_SELECT},
+	{GPIO_120_SELECT, GPIO_120_TYPE, GPO_120_LEVEL+GPIO_120_STICKY+GPIO_120_PULLUP+GPIO_120_PULLDOWN, GPIO_120_SELECT},
+	{GPIO_121_SELECT, GPIO_121_TYPE, GPO_121_LEVEL+GPIO_121_STICKY+GPIO_121_PULLUP+GPIO_121_PULLDOWN, GPIO_121_SELECT},
+	{GPIO_122_SELECT, GPIO_122_TYPE, GPO_122_LEVEL+GPIO_122_STICKY+GPIO_122_PULLUP+GPIO_122_PULLDOWN, GPIO_122_SELECT},
+	{GPIO_123_SELECT, GPIO_123_TYPE, GPO_123_LEVEL+GPIO_123_STICKY+GPIO_123_PULLUP+GPIO_123_PULLDOWN, GPIO_123_SELECT},
+	{GPIO_124_SELECT, GPIO_124_TYPE, GPO_124_LEVEL+GPIO_124_STICKY+GPIO_124_PULLUP+GPIO_124_PULLDOWN, GPIO_124_SELECT},
+	{GPIO_125_SELECT, GPIO_125_TYPE, GPO_125_LEVEL+GPIO_125_STICKY+GPIO_125_PULLUP+GPIO_125_PULLDOWN, GPIO_125_SELECT},
+	{GPIO_126_SELECT, GPIO_126_TYPE, GPO_126_LEVEL+GPIO_126_STICKY+GPIO_126_PULLUP+GPIO_126_PULLDOWN, GPIO_126_SELECT},
+	{GPIO_127_SELECT, GPIO_127_TYPE, GPO_127_LEVEL+GPIO_127_STICKY+GPIO_127_PULLUP+GPIO_127_PULLDOWN, GPIO_127_SELECT},
+	{GPIO_128_SELECT, GPIO_128_TYPE, GPO_128_LEVEL+GPIO_128_STICKY+GPIO_128_PULLUP+GPIO_128_PULLDOWN, GPIO_128_SELECT},
+	{GPIO_129_SELECT, GPIO_129_TYPE, GPO_129_LEVEL+GPIO_129_STICKY+GPIO_129_PULLUP+GPIO_129_PULLDOWN, GPIO_129_SELECT},
+	{GPIO_130_SELECT, GPIO_130_TYPE, GPO_130_LEVEL+GPIO_130_STICKY+GPIO_130_PULLUP+GPIO_130_PULLDOWN, GPIO_130_SELECT},
+	{GPIO_131_SELECT, GPIO_131_TYPE, GPO_131_LEVEL+GPIO_131_STICKY+GPIO_131_PULLUP+GPIO_131_PULLDOWN, GPIO_131_SELECT},
+	{GPIO_132_SELECT, GPIO_132_TYPE, GPO_132_LEVEL+GPIO_132_STICKY+GPIO_132_PULLUP+GPIO_132_PULLDOWN, GPIO_132_SELECT},
+	{GPIO_133_SELECT, GPIO_133_TYPE, GPO_133_LEVEL+GPIO_133_STICKY+GPIO_133_PULLUP+GPIO_133_PULLDOWN, GPIO_133_SELECT},
+	{GPIO_134_SELECT, GPIO_134_TYPE, GPO_134_LEVEL+GPIO_134_STICKY+GPIO_134_PULLUP+GPIO_134_PULLDOWN, GPIO_134_SELECT},
+	{GPIO_135_SELECT, GPIO_135_TYPE, GPO_135_LEVEL+GPIO_135_STICKY+GPIO_135_PULLUP+GPIO_135_PULLDOWN, GPIO_135_SELECT},
+	{GPIO_136_SELECT, GPIO_136_TYPE, GPO_136_LEVEL+GPIO_136_STICKY+GPIO_136_PULLUP+GPIO_136_PULLDOWN, GPIO_136_SELECT},
+	{GPIO_137_SELECT, GPIO_137_TYPE, GPO_137_LEVEL+GPIO_137_STICKY+GPIO_137_PULLUP+GPIO_137_PULLDOWN, GPIO_137_SELECT},
+	{GPIO_138_SELECT, GPIO_138_TYPE, GPO_138_LEVEL+GPIO_138_STICKY+GPIO_138_PULLUP+GPIO_138_PULLDOWN, GPIO_138_SELECT},
+	{GPIO_139_SELECT, GPIO_139_TYPE, GPO_139_LEVEL+GPIO_139_STICKY+GPIO_139_PULLUP+GPIO_139_PULLDOWN, GPIO_139_SELECT},
+	{GPIO_140_SELECT, GPIO_140_TYPE, GPO_140_LEVEL+GPIO_140_STICKY+GPIO_140_PULLUP+GPIO_140_PULLDOWN, GPIO_140_SELECT},
+	{GPIO_141_SELECT, GPIO_141_TYPE, GPO_141_LEVEL+GPIO_141_STICKY+GPIO_141_PULLUP+GPIO_141_PULLDOWN, GPIO_141_SELECT},
+	{GPIO_142_SELECT, GPIO_142_TYPE, GPO_142_LEVEL+GPIO_142_STICKY+GPIO_142_PULLUP+GPIO_142_PULLDOWN, GPIO_142_SELECT},
+	{GPIO_143_SELECT, GPIO_143_TYPE, GPO_143_LEVEL+GPIO_143_STICKY+GPIO_143_PULLUP+GPIO_143_PULLDOWN, GPIO_143_SELECT},
+	{GPIO_144_SELECT, GPIO_144_TYPE, GPO_144_LEVEL+GPIO_144_STICKY+GPIO_144_PULLUP+GPIO_144_PULLDOWN, GPIO_144_SELECT},
+	{GPIO_145_SELECT, GPIO_145_TYPE, GPO_145_LEVEL+GPIO_145_STICKY+GPIO_145_PULLUP+GPIO_145_PULLDOWN, GPIO_145_SELECT},
+	{GPIO_146_SELECT, GPIO_146_TYPE, GPO_146_LEVEL+GPIO_146_STICKY+GPIO_146_PULLUP+GPIO_146_PULLDOWN, GPIO_146_SELECT},
+	{GPIO_147_SELECT, GPIO_147_TYPE, GPO_147_LEVEL+GPIO_147_STICKY+GPIO_147_PULLUP+GPIO_147_PULLDOWN, GPIO_147_SELECT},
+	{GPIO_148_SELECT, GPIO_148_TYPE, GPO_148_LEVEL+GPIO_148_STICKY+GPIO_148_PULLUP+GPIO_148_PULLDOWN, GPIO_148_SELECT},
+	{GPIO_149_SELECT, GPIO_149_TYPE, GPO_149_LEVEL+GPIO_149_STICKY+GPIO_149_PULLUP+GPIO_149_PULLDOWN, GPIO_149_SELECT},
+	{GPIO_150_SELECT, GPIO_150_TYPE, GPO_150_LEVEL+GPIO_150_STICKY+GPIO_150_PULLUP+GPIO_150_PULLDOWN, GPIO_150_SELECT},
+	{GPIO_151_SELECT, GPIO_151_TYPE, GPO_151_LEVEL+GPIO_151_STICKY+GPIO_151_PULLUP+GPIO_151_PULLDOWN, GPIO_151_SELECT},
+	{GPIO_152_SELECT, GPIO_152_TYPE, GPO_152_LEVEL+GPIO_152_STICKY+GPIO_152_PULLUP+GPIO_152_PULLDOWN, GPIO_152_SELECT},
+	{GPIO_153_SELECT, GPIO_153_TYPE, GPO_153_LEVEL+GPIO_153_STICKY+GPIO_153_PULLUP+GPIO_153_PULLDOWN, GPIO_153_SELECT},
+	{GPIO_154_SELECT, GPIO_154_TYPE, GPO_154_LEVEL+GPIO_154_STICKY+GPIO_154_PULLUP+GPIO_154_PULLDOWN, GPIO_154_SELECT},
+	{GPIO_155_SELECT, GPIO_155_TYPE, GPO_155_LEVEL+GPIO_155_STICKY+GPIO_155_PULLUP+GPIO_155_PULLDOWN, GPIO_155_SELECT},
+	{GPIO_156_SELECT, GPIO_156_TYPE, GPO_156_LEVEL+GPIO_156_STICKY+GPIO_156_PULLUP+GPIO_156_PULLDOWN, GPIO_156_SELECT},
+	{GPIO_157_SELECT, GPIO_157_TYPE, GPO_157_LEVEL+GPIO_157_STICKY+GPIO_157_PULLUP+GPIO_157_PULLDOWN, GPIO_157_SELECT},
+	{GPIO_158_SELECT, GPIO_158_TYPE, GPO_158_LEVEL+GPIO_158_STICKY+GPIO_158_PULLUP+GPIO_158_PULLDOWN, GPIO_158_SELECT},
+	{GPIO_159_SELECT, GPIO_159_TYPE, GPO_159_LEVEL+GPIO_159_STICKY+GPIO_159_PULLUP+GPIO_159_PULLDOWN, GPIO_159_SELECT},
+	{GPIO_160_SELECT, GPIO_160_TYPE, GPO_160_LEVEL+GPIO_160_STICKY+GPIO_160_PULLUP+GPIO_160_PULLDOWN, GPIO_160_SELECT},
+	{GPIO_161_SELECT, GPIO_161_TYPE, GPO_161_LEVEL+GPIO_161_STICKY+GPIO_161_PULLUP+GPIO_161_PULLDOWN, GPIO_161_SELECT},
+	{GPIO_162_SELECT, GPIO_162_TYPE, GPO_162_LEVEL+GPIO_162_STICKY+GPIO_162_PULLUP+GPIO_162_PULLDOWN, GPIO_162_SELECT},
+	{GPIO_163_SELECT, GPIO_163_TYPE, GPO_163_LEVEL+GPIO_163_STICKY+GPIO_163_PULLUP+GPIO_163_PULLDOWN, GPIO_163_SELECT},
+	{GPIO_164_SELECT, GPIO_164_TYPE, GPO_164_LEVEL+GPIO_164_STICKY+GPIO_164_PULLUP+GPIO_164_PULLDOWN, GPIO_164_SELECT},
+	{GPIO_165_SELECT, GPIO_165_TYPE, GPO_165_LEVEL+GPIO_165_STICKY+GPIO_165_PULLUP+GPIO_165_PULLDOWN, GPIO_165_SELECT},
+	{GPIO_166_SELECT, GPIO_166_TYPE, GPO_166_LEVEL+GPIO_166_STICKY+GPIO_166_PULLUP+GPIO_166_PULLDOWN, GPIO_166_SELECT},
+	{GPIO_167_SELECT, GPIO_167_TYPE, GPO_167_LEVEL+GPIO_167_STICKY+GPIO_167_PULLUP+GPIO_167_PULLDOWN, GPIO_167_SELECT},
+	{GPIO_168_SELECT, GPIO_168_TYPE, GPO_168_LEVEL+GPIO_168_STICKY+GPIO_168_PULLUP+GPIO_168_PULLDOWN, GPIO_168_SELECT},
+	{GPIO_169_SELECT, GPIO_169_TYPE, GPO_169_LEVEL+GPIO_169_STICKY+GPIO_169_PULLUP+GPIO_169_PULLDOWN, GPIO_169_SELECT},
+	{GPIO_170_SELECT, GPIO_170_TYPE, GPO_170_LEVEL+GPIO_170_STICKY+GPIO_170_PULLUP+GPIO_170_PULLDOWN, GPIO_170_SELECT},
+	{GPIO_171_SELECT, GPIO_171_TYPE, GPO_171_LEVEL+GPIO_171_STICKY+GPIO_171_PULLUP+GPIO_171_PULLDOWN, GPIO_171_SELECT},
+	{GPIO_172_SELECT, GPIO_172_TYPE, GPO_172_LEVEL+GPIO_172_STICKY+GPIO_172_PULLUP+GPIO_172_PULLDOWN, GPIO_172_SELECT},
+	{GPIO_173_SELECT, GPIO_173_TYPE, GPO_173_LEVEL+GPIO_173_STICKY+GPIO_173_PULLUP+GPIO_173_PULLDOWN, GPIO_173_SELECT},
+	{GPIO_174_SELECT, GPIO_174_TYPE, GPO_174_LEVEL+GPIO_174_STICKY+GPIO_174_PULLUP+GPIO_174_PULLDOWN, GPIO_174_SELECT},
+	{GPIO_175_SELECT, GPIO_175_TYPE, GPO_175_LEVEL+GPIO_175_STICKY+GPIO_175_PULLUP+GPIO_175_PULLDOWN, GPIO_175_SELECT},
+	{GPIO_176_SELECT, GPIO_176_TYPE, GPO_176_LEVEL+GPIO_176_STICKY+GPIO_176_PULLUP+GPIO_176_PULLDOWN, GPIO_176_SELECT},
+	{GPIO_177_SELECT, GPIO_177_TYPE, GPO_177_LEVEL+GPIO_177_STICKY+GPIO_177_PULLUP+GPIO_177_PULLDOWN, GPIO_177_SELECT},
+	{GPIO_178_SELECT, GPIO_178_TYPE, GPO_178_LEVEL+GPIO_178_STICKY+GPIO_178_PULLUP+GPIO_178_PULLDOWN, GPIO_178_SELECT},
+	{GPIO_179_SELECT, GPIO_179_TYPE, GPO_179_LEVEL+GPIO_179_STICKY+GPIO_179_PULLUP+GPIO_179_PULLDOWN, GPIO_179_SELECT},
+	{GPIO_180_SELECT, GPIO_180_TYPE, GPO_180_LEVEL+GPIO_180_STICKY+GPIO_180_PULLUP+GPIO_180_PULLDOWN, GPIO_180_SELECT},
+	{GPIO_181_SELECT, GPIO_181_TYPE, GPO_181_LEVEL+GPIO_181_STICKY+GPIO_181_PULLUP+GPIO_181_PULLDOWN, GPIO_181_SELECT},
+	{GPIO_182_SELECT, GPIO_182_TYPE, GPO_182_LEVEL+GPIO_182_STICKY+GPIO_182_PULLUP+GPIO_182_PULLDOWN, GPIO_182_SELECT},
+	{GPIO_183_SELECT, GPIO_183_TYPE, GPO_183_LEVEL+GPIO_183_STICKY+GPIO_183_PULLUP+GPIO_183_PULLDOWN, GPIO_183_SELECT},
+	{GPIO_184_SELECT, GPIO_184_TYPE, GPO_184_LEVEL+GPIO_184_STICKY+GPIO_184_PULLUP+GPIO_184_PULLDOWN, GPIO_184_SELECT},
+	{GPIO_185_SELECT, GPIO_185_TYPE, GPO_185_LEVEL+GPIO_185_STICKY+GPIO_185_PULLUP+GPIO_185_PULLDOWN, GPIO_185_SELECT},
+	{GPIO_186_SELECT, GPIO_186_TYPE, GPO_186_LEVEL+GPIO_186_STICKY+GPIO_186_PULLUP+GPIO_186_PULLDOWN, GPIO_186_SELECT},
+	{GPIO_187_SELECT, GPIO_187_TYPE, GPO_187_LEVEL+GPIO_187_STICKY+GPIO_187_PULLUP+GPIO_187_PULLDOWN, GPIO_187_SELECT},
+	{GPIO_188_SELECT, GPIO_188_TYPE, GPO_188_LEVEL+GPIO_188_STICKY+GPIO_188_PULLUP+GPIO_188_PULLDOWN, GPIO_188_SELECT},
+	{GPIO_189_SELECT, GPIO_189_TYPE, GPO_189_LEVEL+GPIO_189_STICKY+GPIO_189_PULLUP+GPIO_189_PULLDOWN, GPIO_189_SELECT},
+	{GPIO_190_SELECT, GPIO_190_TYPE, GPO_190_LEVEL+GPIO_190_STICKY+GPIO_190_PULLUP+GPIO_190_PULLDOWN, GPIO_190_SELECT},
+	{GPIO_191_SELECT, GPIO_191_TYPE, GPO_191_LEVEL+GPIO_191_STICKY+GPIO_191_PULLUP+GPIO_191_PULLDOWN, GPIO_191_SELECT},
+	{GPIO_192_SELECT, GPIO_192_TYPE, GPO_192_LEVEL+GPIO_192_STICKY+GPIO_192_PULLUP+GPIO_192_PULLDOWN, GPIO_192_SELECT},
+	{GPIO_193_SELECT, GPIO_193_TYPE, GPO_193_LEVEL+GPIO_193_STICKY+GPIO_193_PULLUP+GPIO_193_PULLDOWN, GPIO_193_SELECT},
+	{GPIO_194_SELECT, GPIO_194_TYPE, GPO_194_LEVEL+GPIO_194_STICKY+GPIO_194_PULLUP+GPIO_194_PULLDOWN, GPIO_194_SELECT},
+	{GPIO_195_SELECT, GPIO_195_TYPE, GPO_195_LEVEL+GPIO_195_STICKY+GPIO_195_PULLUP+GPIO_195_PULLDOWN, GPIO_195_SELECT},
+	{GPIO_196_SELECT, GPIO_196_TYPE, GPO_196_LEVEL+GPIO_196_STICKY+GPIO_196_PULLUP+GPIO_196_PULLDOWN, GPIO_196_SELECT},
+	{GPIO_197_SELECT, GPIO_197_TYPE, GPO_197_LEVEL+GPIO_197_STICKY+GPIO_197_PULLUP+GPIO_197_PULLDOWN, GPIO_197_SELECT},
+	{GPIO_198_SELECT, GPIO_198_TYPE, GPO_198_LEVEL+GPIO_198_STICKY+GPIO_198_PULLUP+GPIO_198_PULLDOWN, GPIO_198_SELECT},
+	{GPIO_199_SELECT, GPIO_199_TYPE, GPO_199_LEVEL+GPIO_199_STICKY+GPIO_199_PULLUP+GPIO_199_PULLDOWN, GPIO_199_SELECT},
+	{GPIO_200_SELECT, GPIO_200_TYPE, GPO_200_LEVEL+GPIO_200_STICKY+GPIO_200_PULLUP+GPIO_200_PULLDOWN, GPIO_200_SELECT},
+	{GPIO_201_SELECT, GPIO_201_TYPE, GPO_201_LEVEL+GPIO_201_STICKY+GPIO_201_PULLUP+GPIO_201_PULLDOWN, GPIO_201_SELECT},
+	{GPIO_202_SELECT, GPIO_202_TYPE, GPO_202_LEVEL+GPIO_202_STICKY+GPIO_202_PULLUP+GPIO_202_PULLDOWN, GPIO_202_SELECT},
+	{GPIO_203_SELECT, GPIO_203_TYPE, GPO_203_LEVEL+GPIO_203_STICKY+GPIO_203_PULLUP+GPIO_203_PULLDOWN, GPIO_203_SELECT},
+	{GPIO_204_SELECT, GPIO_204_TYPE, GPO_204_LEVEL+GPIO_204_STICKY+GPIO_204_PULLUP+GPIO_204_PULLDOWN, GPIO_204_SELECT},
+	{GPIO_205_SELECT, GPIO_205_TYPE, GPO_205_LEVEL+GPIO_205_STICKY+GPIO_205_PULLUP+GPIO_205_PULLDOWN, GPIO_205_SELECT},
+	{GPIO_206_SELECT, GPIO_206_TYPE, GPO_206_LEVEL+GPIO_206_STICKY+GPIO_206_PULLUP+GPIO_206_PULLDOWN, GPIO_206_SELECT},
+	{GPIO_207_SELECT, GPIO_207_TYPE, GPO_207_LEVEL+GPIO_207_STICKY+GPIO_207_PULLUP+GPIO_207_PULLDOWN, GPIO_207_SELECT},
+	{GPIO_208_SELECT, GPIO_208_TYPE, GPO_208_LEVEL+GPIO_208_STICKY+GPIO_208_PULLUP+GPIO_208_PULLDOWN, GPIO_208_SELECT},
+	{GPIO_209_SELECT, GPIO_209_TYPE, GPO_209_LEVEL+GPIO_209_STICKY+GPIO_209_PULLUP+GPIO_209_PULLDOWN, GPIO_209_SELECT},
+	{GPIO_210_SELECT, GPIO_210_TYPE, GPO_210_LEVEL+GPIO_210_STICKY+GPIO_210_PULLUP+GPIO_210_PULLDOWN, GPIO_210_SELECT},
+	{GPIO_211_SELECT, GPIO_211_TYPE, GPO_211_LEVEL+GPIO_211_STICKY+GPIO_211_PULLUP+GPIO_211_PULLDOWN, GPIO_211_SELECT},
+	{GPIO_212_SELECT, GPIO_212_TYPE, GPO_212_LEVEL+GPIO_212_STICKY+GPIO_212_PULLUP+GPIO_212_PULLDOWN, GPIO_212_SELECT},
+	{GPIO_213_SELECT, GPIO_213_TYPE, GPO_213_LEVEL+GPIO_213_STICKY+GPIO_213_PULLUP+GPIO_213_PULLDOWN, GPIO_213_SELECT},
+	{GPIO_214_SELECT, GPIO_214_TYPE, GPO_214_LEVEL+GPIO_214_STICKY+GPIO_214_PULLUP+GPIO_214_PULLDOWN, GPIO_214_SELECT},
+	{GPIO_215_SELECT, GPIO_215_TYPE, GPO_215_LEVEL+GPIO_215_STICKY+GPIO_215_PULLUP+GPIO_215_PULLDOWN, GPIO_215_SELECT},
+	{GPIO_216_SELECT, GPIO_216_TYPE, GPO_216_LEVEL+GPIO_216_STICKY+GPIO_216_PULLUP+GPIO_216_PULLDOWN, GPIO_216_SELECT},
+	{GPIO_217_SELECT, GPIO_217_TYPE, GPO_217_LEVEL+GPIO_217_STICKY+GPIO_217_PULLUP+GPIO_217_PULLDOWN, GPIO_217_SELECT},
+	{GPIO_218_SELECT, GPIO_218_TYPE, GPO_218_LEVEL+GPIO_218_STICKY+GPIO_218_PULLUP+GPIO_218_PULLDOWN, GPIO_218_SELECT},
+	{GPIO_219_SELECT, GPIO_219_TYPE, GPO_219_LEVEL+GPIO_219_STICKY+GPIO_219_PULLUP+GPIO_219_PULLDOWN, GPIO_219_SELECT},
+	{GPIO_220_SELECT, GPIO_220_TYPE, GPO_220_LEVEL+GPIO_220_STICKY+GPIO_220_PULLUP+GPIO_220_PULLDOWN, GPIO_220_SELECT},
+	{GPIO_221_SELECT, GPIO_221_TYPE, GPO_221_LEVEL+GPIO_221_STICKY+GPIO_221_PULLUP+GPIO_221_PULLDOWN, GPIO_221_SELECT},
+	{GPIO_222_SELECT, GPIO_222_TYPE, GPO_222_LEVEL+GPIO_222_STICKY+GPIO_222_PULLUP+GPIO_222_PULLDOWN, GPIO_222_SELECT},
+	{GPIO_223_SELECT, GPIO_223_TYPE, GPO_223_LEVEL+GPIO_223_STICKY+GPIO_223_PULLUP+GPIO_223_PULLDOWN, GPIO_223_SELECT},
+	{GPIO_224_SELECT, GPIO_224_TYPE, GPO_224_LEVEL+GPIO_224_STICKY+GPIO_224_PULLUP+GPIO_224_PULLDOWN, GPIO_224_SELECT},
+	{GPIO_225_SELECT, GPIO_225_TYPE, GPO_225_LEVEL+GPIO_225_STICKY+GPIO_225_PULLUP+GPIO_225_PULLDOWN, GPIO_225_SELECT},
+	{GPIO_226_SELECT, GPIO_226_TYPE, GPO_226_LEVEL+GPIO_226_STICKY+GPIO_226_PULLUP+GPIO_226_PULLDOWN, GPIO_226_SELECT},
+	{GPIO_227_SELECT, GPIO_227_TYPE, GPO_227_LEVEL+GPIO_227_STICKY+GPIO_227_PULLUP+GPIO_227_PULLDOWN, GPIO_227_SELECT},
+	{GPIO_228_SELECT, GPIO_228_TYPE, GPO_228_LEVEL+GPIO_228_STICKY+GPIO_228_PULLUP+GPIO_228_PULLDOWN, GPIO_228_SELECT},
+	{GPIO_229_SELECT, GPIO_229_TYPE, GPO_229_LEVEL+GPIO_229_STICKY+GPIO_229_PULLUP+GPIO_229_PULLDOWN, GPIO_229_SELECT},
+};
+
+typedef enum _GEVENT_COUNT
+{
+	GEVENT_00=0x60,
+	GEVENT_01,
+	GEVENT_02,
+	GEVENT_03,
+	GEVENT_04,
+	GEVENT_05,
+	GEVENT_06,
+	GEVENT_07,
+	GEVENT_08,
+	GEVENT_09,
+	GEVENT_10,
+	GEVENT_11,
+	GEVENT_12,
+	GEVENT_13,
+	GEVENT_14,
+	GEVENT_15,
+	GEVENT_16,
+	GEVENT_17,
+	GEVENT_18,
+	GEVENT_19,
+	GEVENT_20,
+	GEVENT_21,
+	GEVENT_22,
+	GEVENT_23
+} GEVENT_COUNT;
+
+typedef struct _GEVENT_SETTINGS
+{
+	u8 EventEnable;      // 0: Disable, 1: Enable
+	u8 SciTrig;          // 0: Falling Edge, 1: Rising Edge
+	u8 SciLevl;          // 0: Edge trigger, 1: Level Trigger
+	u8 SmiSciEn;         // 0: Not send SMI, 1: Send SMI
+	u8 SciS0En;          // 0: Disable, 1: Enable
+	u8 SciMap;           // 0000b->1111b
+	u8 SmiTrig;          // 0: Active Low, 1: Active High
+	u8 SmiControl;       // 0: Disable, 1: SMI 2: NMI 3: IRQ13
+} GEVENT_SETTINGS;
+
+GEVENT_SETTINGS gevent_table[] =
+{
+	{GEVENT_00_EVENTENABLE, GEVENT_00_SCITRIG, GEVENT_00_SCILEVEL, GEVENT_00_SMISCIEN, GEVENT_00_SCIS0EN, GEVENT_00_SCIMAP, GEVENT_00_SMITRIG, GEVENT_00_SMICONTROL},
+	{GEVENT_01_EVENTENABLE, GEVENT_01_SCITRIG, GEVENT_01_SCILEVEL, GEVENT_01_SMISCIEN, GEVENT_01_SCIS0EN, GEVENT_01_SCIMAP, GEVENT_01_SMITRIG, GEVENT_01_SMICONTROL},
+	{GEVENT_02_EVENTENABLE, GEVENT_02_SCITRIG, GEVENT_02_SCILEVEL, GEVENT_02_SMISCIEN, GEVENT_02_SCIS0EN, GEVENT_02_SCIMAP, GEVENT_02_SMITRIG, GEVENT_02_SMICONTROL},
+	{GEVENT_03_EVENTENABLE, GEVENT_03_SCITRIG, GEVENT_03_SCILEVEL, GEVENT_03_SMISCIEN, GEVENT_03_SCIS0EN, GEVENT_03_SCIMAP, GEVENT_03_SMITRIG, GEVENT_03_SMICONTROL},
+	{GEVENT_04_EVENTENABLE, GEVENT_04_SCITRIG, GEVENT_04_SCILEVEL, GEVENT_04_SMISCIEN, GEVENT_04_SCIS0EN, GEVENT_04_SCIMAP, GEVENT_04_SMITRIG, GEVENT_04_SMICONTROL},
+	{GEVENT_05_EVENTENABLE, GEVENT_05_SCITRIG, GEVENT_05_SCILEVEL, GEVENT_05_SMISCIEN, GEVENT_05_SCIS0EN, GEVENT_05_SCIMAP, GEVENT_05_SMITRIG, GEVENT_05_SMICONTROL},
+	{GEVENT_06_EVENTENABLE, GEVENT_06_SCITRIG, GEVENT_06_SCILEVEL, GEVENT_06_SMISCIEN, GEVENT_06_SCIS0EN, GEVENT_06_SCIMAP, GEVENT_06_SMITRIG, GEVENT_06_SMICONTROL},
+	{GEVENT_07_EVENTENABLE, GEVENT_07_SCITRIG, GEVENT_07_SCILEVEL, GEVENT_07_SMISCIEN, GEVENT_07_SCIS0EN, GEVENT_07_SCIMAP, GEVENT_07_SMITRIG, GEVENT_07_SMICONTROL},
+	{GEVENT_08_EVENTENABLE, GEVENT_08_SCITRIG, GEVENT_08_SCILEVEL, GEVENT_08_SMISCIEN, GEVENT_08_SCIS0EN, GEVENT_08_SCIMAP, GEVENT_08_SMITRIG, GEVENT_08_SMICONTROL},
+	{GEVENT_09_EVENTENABLE, GEVENT_09_SCITRIG, GEVENT_09_SCILEVEL, GEVENT_09_SMISCIEN, GEVENT_09_SCIS0EN, GEVENT_09_SCIMAP, GEVENT_09_SMITRIG, GEVENT_09_SMICONTROL},
+	{GEVENT_10_EVENTENABLE, GEVENT_10_SCITRIG, GEVENT_10_SCILEVEL, GEVENT_10_SMISCIEN, GEVENT_10_SCIS0EN, GEVENT_10_SCIMAP, GEVENT_10_SMITRIG, GEVENT_10_SMICONTROL},
+	{GEVENT_11_EVENTENABLE, GEVENT_11_SCITRIG, GEVENT_11_SCILEVEL, GEVENT_11_SMISCIEN, GEVENT_11_SCIS0EN, GEVENT_11_SCIMAP, GEVENT_11_SMITRIG, GEVENT_11_SMICONTROL},
+	{GEVENT_12_EVENTENABLE, GEVENT_12_SCITRIG, GEVENT_12_SCILEVEL, GEVENT_12_SMISCIEN, GEVENT_12_SCIS0EN, GEVENT_12_SCIMAP, GEVENT_12_SMITRIG, GEVENT_12_SMICONTROL},
+	{GEVENT_13_EVENTENABLE, GEVENT_13_SCITRIG, GEVENT_13_SCILEVEL, GEVENT_13_SMISCIEN, GEVENT_13_SCIS0EN, GEVENT_13_SCIMAP, GEVENT_13_SMITRIG, GEVENT_13_SMICONTROL},
+	{GEVENT_14_EVENTENABLE, GEVENT_14_SCITRIG, GEVENT_14_SCILEVEL, GEVENT_14_SMISCIEN, GEVENT_14_SCIS0EN, GEVENT_14_SCIMAP, GEVENT_14_SMITRIG, GEVENT_14_SMICONTROL},
+	{GEVENT_15_EVENTENABLE, GEVENT_15_SCITRIG, GEVENT_15_SCILEVEL, GEVENT_15_SMISCIEN, GEVENT_15_SCIS0EN, GEVENT_15_SCIMAP, GEVENT_15_SMITRIG, GEVENT_15_SMICONTROL},
+	{GEVENT_16_EVENTENABLE, GEVENT_16_SCITRIG, GEVENT_16_SCILEVEL, GEVENT_16_SMISCIEN, GEVENT_16_SCIS0EN, GEVENT_16_SCIMAP, GEVENT_16_SMITRIG, GEVENT_16_SMICONTROL},
+	{GEVENT_17_EVENTENABLE, GEVENT_17_SCITRIG, GEVENT_17_SCILEVEL, GEVENT_17_SMISCIEN, GEVENT_17_SCIS0EN, GEVENT_17_SCIMAP, GEVENT_17_SMITRIG, GEVENT_17_SMICONTROL},
+	{GEVENT_18_EVENTENABLE, GEVENT_18_SCITRIG, GEVENT_18_SCILEVEL, GEVENT_18_SMISCIEN, GEVENT_18_SCIS0EN, GEVENT_18_SCIMAP, GEVENT_18_SMITRIG, GEVENT_18_SMICONTROL},
+	{GEVENT_19_EVENTENABLE, GEVENT_19_SCITRIG, GEVENT_19_SCILEVEL, GEVENT_19_SMISCIEN, GEVENT_19_SCIS0EN, GEVENT_19_SCIMAP, GEVENT_19_SMITRIG, GEVENT_19_SMICONTROL},
+	{GEVENT_20_EVENTENABLE, GEVENT_20_SCITRIG, GEVENT_20_SCILEVEL, GEVENT_20_SMISCIEN, GEVENT_20_SCIS0EN, GEVENT_20_SCIMAP, GEVENT_20_SMITRIG, GEVENT_20_SMICONTROL},
+	{GEVENT_21_EVENTENABLE, GEVENT_21_SCITRIG, GEVENT_21_SCILEVEL, GEVENT_21_SMISCIEN, GEVENT_21_SCIS0EN, GEVENT_21_SCIMAP, GEVENT_21_SMITRIG, GEVENT_21_SMICONTROL},
+	{GEVENT_22_EVENTENABLE, GEVENT_22_SCITRIG, GEVENT_22_SCILEVEL, GEVENT_22_SMISCIEN, GEVENT_22_SCIS0EN, GEVENT_22_SCIMAP, GEVENT_22_SMITRIG, GEVENT_22_SMICONTROL},
+	{GEVENT_23_EVENTENABLE, GEVENT_23_SCITRIG, GEVENT_23_SCILEVEL, GEVENT_23_SMISCIEN, GEVENT_23_SCIS0EN, GEVENT_23_SCIMAP, GEVENT_23_SMITRIG, GEVENT_23_SMICONTROL},
+};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------
+ *                          L O C A L    F U N C T I O N S
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif
diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c
new file mode 100644
index 0000000..afd8c67
--- /dev/null
+++ b/src/mainboard/amd/dinar/irq_tables.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+
+
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+		u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+		u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+		u8 slot, u8 rfu)
+{
+	pirq_info->bus = bus;
+	pirq_info->devfn = devfn;
+	pirq_info->irq[0].link = link0;
+	pirq_info->irq[0].bitmap = bitmap0;
+	pirq_info->irq[1].link = link1;
+	pirq_info->irq[1].bitmap = bitmap1;
+	pirq_info->irq[2].link = link2;
+	pirq_info->irq[2].bitmap = bitmap2;
+	pirq_info->irq[3].link = link3;
+	pirq_info->irq[3].bitmap = bitmap3;
+	pirq_info->slot = slot;
+	pirq_info->rfu = rfu;
+}
+extern u8 bus_isa;
+extern u8 bus_sb700[2];
+extern unsigned long sbdn_sb700;
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+	struct irq_routing_table *pirq;
+	struct irq_info *pirq_info;
+	u32 slot_num;
+	u8 *v;
+
+	u8 sum = 0;
+	int i;
+
+
+	get_bus_conf();		/* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+
+
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
+
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+	pirq = (void *)(addr);
+	v = (u8 *) (addr);
+
+	pirq->signature = PIRQ_SIGNATURE;
+	pirq->version = PIRQ_VERSION;
+
+	pirq->rtr_bus = bus_sb700[0];
+	pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4;
+
+	pirq->exclusive_irqs = 0;
+
+	pirq->rtr_vendor = 0x1002;
+	pirq->rtr_device = 0x4384;
+
+	pirq->miniport_data = 0;
+
+	memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+	pirq_info = (void *)(&pirq->checksum + 1);
+	slot_num = 0;
+
+
+	/* pci bridge */
+	write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4,
+			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+			0);
+	pirq_info++;
+
+
+
+	slot_num++;
+
+
+
+	pirq->size = 32 + 16 * slot_num;
+
+	for (i = 0; i < pirq->size; i++)
+		sum += v[i];
+
+	sum = pirq->checksum - sum;
+
+	if (sum != pirq->checksum) {
+		pirq->checksum = sum;
+	}
+
+	printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+	return (unsigned long)pirq_info;
+
+}
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
new file mode 100644
index 0000000..9d10390
--- /dev/null
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -0,0 +1,138 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <boot/tables.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <device/pci_def.h>
+#include <NbPlatform.h>
+#include "chip.h"
+
+#define ONE_MB  0x100000
+//#define SMBUS_IO_BASE 0x6000
+
+void set_pcie_reset(void *nbconfig);
+void set_pcie_dereset(void *nbconfig);
+
+/**
+ * TODO
+ * SB CIMx callback
+ */
+void set_pcie_reset(void *nbconfig)
+{
+}
+
+/**
+ * Mainboard specific RD890 CIMx callback
+ * Release Resets to PCIe Links
+ * SR5690 PCIE_RESET_GPIO1,2,3,4 to reset pcie
+ */
+void set_pcie_dereset(void *nbconfig)
+{
+	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+	u32 i;
+	u32 val;
+	u32 nb_addr;
+
+	val = 0x00000007UL;
+	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
+	for (i = 0; i < MAX_NB_COUNT; i ++) {
+		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
+		LibNbPciIndexRMW(nb_addr,
+				NB_HTIU_REGA8,
+				AccessS3SaveWidth32,
+				~val,
+				val,
+				&(pConfig->Northbridges[i]));
+	}
+}
+
+uint64_t uma_memory_base, uma_memory_size;
+
+/*************************************************
+ * enable the dedicated function in dinar board.
+ *************************************************/
+static void dinar_enable(device_t dev)
+{
+	printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
+#if (CONFIG_GFXUMA == 1)
+	msr_t msr, msr2;
+	uint32_t sys_mem;
+
+	/* TOP_MEM: the top of DRAM below 4G */
+	msr = rdmsr(TOP_MEM);
+	printk
+		(BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+		 __func__, msr.lo, msr.hi);
+
+	/* TOP_MEM2: the top of DRAM above 4G */
+	msr2 = rdmsr(TOP_MEM2);
+	printk (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+			__func__, msr2.lo, msr2.hi);
+
+	/* refer to UMA Size Consideration in Family15h BKDG. */
+	/* Please reference MemNGetUmaSizeOR () */
+	/*
+	 *     Total system memory   UMASize
+	 *     >= 2G                 512M
+	 *     >=1G                  256M
+	 *     <1G                    64M
+	 */
+	sys_mem = msr.lo + 16 * ONE_MB;   // Ignore 16MB allocated for C6 when finding UMA size
+	if ((msr2.hi & 0x0000000F) || (sys_mem >= 2048 * ONE_MB)) {
+		uma_memory_size = 512 * ONE_MB;
+	} else if (sys_mem >= 1024 * ONE_MB) {
+		uma_memory_size = 256 * ONE_MB;
+	} else {
+		uma_memory_size = 64 * ONE_MB;
+	}
+	uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+
+	printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+			__func__, uma_memory_size, uma_memory_base);
+
+	/* TODO: TOP_MEM2 */
+#else
+	uma_memory_size = 256 * ONE_MB; /* 256M recommended UMA */
+	uma_memory_base = 768 * ONE_MB; /* 1GB  system memory supported */
+#endif
+
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	/* UMA is removed from system memory in the northbridge code, but
+	 * in some circumstances we want the memory mentioned as reserved.
+	 */
+#if (CONFIG_GFXUMA == 1)
+	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+			uma_memory_base, uma_memory_size);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+			uma_memory_size);
+#endif
+	return 0;
+}
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("AMD DINAR Mainboard")
+		.enable_dev = dinar_enable,
+};
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
new file mode 100644
index 0000000..d988eb1
--- /dev/null
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/lapic.h>
+
+extern u8 bus_rd890[14];
+extern u8 bus_sb700[2];
+extern u32 bus_type[256];
+extern u32 sbdn_rd890;
+extern u32 sbdn_sb700;
+
+
+static void *smp_write_config_table(void *v)
+{
+	struct mp_config_table *mc;
+	int bus_isa;
+	u32 apicid_sb700;
+	u32 apicid_rd890;
+	device_t dev;
+	u32 dword;
+
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	mptable_init(mc, LAPIC_ADDR);
+
+	smp_write_processors(mc);
+	get_bus_conf();
+	mptable_write_buses(mc, NULL, &bus_isa);
+
+	/*
+	 * AGESA v5 Apply apic enumeration rules
+	 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
+	 * put the local-APICs at m..z
+	 * For systems with < 16 APICs, put the Local-APICs at 0..n and
+	 * put the IO-APICs at (n + 1)..z
+	 */
+#if CONFIG_MAX_CPUS >= 16
+	apicid_sb700 = 0x0;
+#else
+	apicid_sb700 = CONFIG_MAX_CPUS + 1
+#endif
+		apicid_rd890 = apicid_sb700 + 1;
+
+	//bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0.
+	dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0));
+	if (dev) {
+		/* Set sb700 IOAPIC ID */
+		dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
+		smp_write_ioapic(mc, apicid_sb700, 0x20, dword);
+
+#ifdef UNUSED_CODE
+		u8 byte;
+		/* Initialize interrupt mapping */
+		/* aza */
+		byte = pci_read_config8(dev, 0x63);
+		byte &= 0xf8;
+		byte |= 0; /* 0: INTA, ...., 7: INTH */
+		pci_write_config8(dev, 0x63, byte);
+		/* SATA */
+		dword = pci_read_config32(dev, 0xAC);
+		dword &= ~(7 << 26);
+		dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
+		/* dword |= 1<<22; PIC and APIC co exists */
+		pci_write_config32(dev, 0xAC, dword);
+#endif
+
+		/*
+		 * 00:12.0: PROG SATA : INT F
+		 * 00:13.0: INTA USB_0
+		 * 00:13.1: INTB USB_1
+		 * 00:13.2: INTC USB_2
+		 * 00:13.3: INTD USB_3
+		 * 00:13.4: INTC USB_4
+		 * 00:13.5: INTD USB2
+		 * 00:14.1: INTA IDE
+		 * 00:14.2: Prog HDA : INT E
+		 * 00:14.5: INTB ACI
+		 * 00:14.6: INTB MCI
+		 */
+
+		/* Set RS5650 IOAPIC ID */
+		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+		if (dev) {
+			pci_write_config32(dev, 0xF8, 0x1);
+			dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_rd890, 0x20, dword);
+		}
+
+	}
+
+	/* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+	smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+
+	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb700, 0);
+
+	/* PCI interrupts are level triggered, and are
+	 * associated with a specific bus/device/function tuple.
+	 */
+#define PCI_INT(bus, dev, int_sign, pin) \
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb700, (pin))
+
+	/* SMBUS */
+	//PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0
+
+	/* HD Audio */
+	PCI_INT(0x0, 0x14, 0x2, 0x10);
+
+	/* USB */
+	/* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */
+	/* EHCI hard-wired to 02h, corresponding to using INTB# */
+	/* USB1 */
+	PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */
+	PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */
+	PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */
+
+	/* USB2 */
+	PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */
+	PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */
+	PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */
+
+	/* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */
+	PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */
+
+	/* SATA */
+	PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG
+
+	/* on board NIC & Slot PCIE.  */
+	/* configuration B doesnt need dev 5,6,7 */
+	/*
+	 * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11);
+	 * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12);
+	 * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13);
+	 */
+
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */
+
+	/* PCI slots */
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15);
+
+
+	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
+	IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+	IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+	/* There is no extension information... */
+
+	/* Compute the checksums */
+	return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+	void *v;
+	v = smp_write_floating_table(addr, 0);
+	return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h
new file mode 100644
index 0000000..8265f87
--- /dev/null
+++ b/src/mainboard/amd/dinar/platform_cfg.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_CFG_H_
+#define _PLATFORM_CFG_H_
+
+
+/* northbridge customize options */
+/**
+ * Max number of northbridges in the system
+ */
+#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
+
+/**
+ *  Enable check for PCIe endpoint to be ready for PCI enumeration.
+ *
+ */
+//#define  EPREADY_WORKAROUND_DISABLED
+
+/**
+ *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
+ *
+ */
+#define  IOMMU_SUPPORT_DISABLE //TODO: enable it
+
+/**
+ *  Disable server PCIe hotplug support.
+ */
+
+//#define HOTPLUG_SUPPORT_DISABLED
+
+/**
+ *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
+ */
+
+//#define DEVICE_REMAP_DISABLE
+
+#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c
new file mode 100644
index 0000000..9518691
--- /dev/null
+++ b/src/mainboard/amd/dinar/rd890_cfg.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "NbPlatform.h"
+#include "rd890_cfg.h"
+#include "northbridge/amd/cimx/rd890/chip.h"
+#include "nbInitializer.h"
+#include <string.h>
+#include <arch/ioapic.h>
+
+#ifndef __PRE_RAM__
+#include <device/device.h>
+extern void set_pcie_reset(void *config);
+extern void set_pcie_dereset(void *config);
+
+/**
+ * Platform dependent configuration at ramstage
+ */
+static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
+{
+	u16 i;
+	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
+	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
+	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
+	DEFAULT_PLATFORM_CONFIG(platform_config);
+
+	/* update the platform depentent configuration by devicetree */
+	rd890_info  = nb_dev->chip_info;
+	platform_config.PortEnableMap = rd890_info->port_enable;
+	if (rd890_info->gpp1_configuration == 0) {
+		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp1_configuration == 1) {
+		platform_config.Gpp1Config = GFX_CONFIG_AABB;
+	}
+	if (rd890_info->gpp2_configuration == 0) {
+		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp2_configuration == 1) {
+		platform_config.Gpp2Config = GFX_CONFIG_AABB;
+	}
+	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
+
+	if (platform_config.Gpp1Config != 0) {
+		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
+	}
+	if (platform_config.Gpp2Config != 0) {
+		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
+	}
+	if (platform_config.Gpp3aConfig != 0) {
+		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
+	}
+
+	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
+	for (i = 0; i <= MAX_CORE_ID; i++) {
+		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
+		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
+	}
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
+	}
+
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
+			pPcieConfig->PortConfiguration[i].PortPresent = ON;
+			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
+				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
+			}
+			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
+				u16 j;
+				pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
+				/* Set Hotplug descriptor info */
+				for (j = 0; j < 8; j++) {
+					u32 PortDescriptor;
+					PortDescriptor = platform_config.PortHotplugDescriptors[j];
+					if ((PortDescriptor & 0xF) == j) {
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+}
+#endif // __PRE_RAM__
+
+/**
+ * @brief Entry point of Northbridge CIMx callout/CallBack
+ *
+ * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+ *
+ * @param[in] u32 func               Northbridge CIMx CallBackId
+ * @param[in] u32 data               Northbridge Input Data.
+ * @param[in] AMD_NB_CONFIG *config  Northbridge configuration structure pointer.
+ *
+ */
+static u32 rd890_callout_entry(u32 func, u32 data, void *config)
+{
+	u32 ret = 0;
+#ifndef __PRE_RAM__
+	device_t nb_dev = (device_t)data;
+#endif
+	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
+
+	switch (func) {
+		case PHCB_AmdPortTrainingCompleted:
+			break;
+
+		case PHCB_AmdPortResetDeassert:
+#ifndef __PRE_RAM__
+			set_pcie_dereset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetAssert:
+#ifndef __PRE_RAM__
+			set_pcie_reset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetSupported:
+			break;
+		case PHCB_AmdGeneratePciReset:
+			break;
+		case PHCB_AmdGetExclusionTable:
+			break;
+		case PHCB_AmdAllocateBuffer:
+			break;
+		case PHCB_AmdUpdateApicInterruptMapping:
+			break;
+		case PHCB_AmdFreeBuffer:
+			break;
+		case PHCB_AmdLocateBuffer:
+			break;
+		case PHCB_AmdReportEvent:
+			break;
+		case PHCB_AmdPcieAsmpInfo:
+			break;
+
+		case CB_AmdSetNbPorConfig:
+			break;
+		case CB_AmdSetHtConfig:
+			/*TODO: different HT path and deempasis for each NB */
+			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
+
+			break;
+		case CB_AmdSetPcieEarlyConfig:
+#ifndef __PRE_RAM__
+			nb_platform_config(nb_dev, nbConfigPtr);
+#endif
+			break;
+
+		case CB_AmdSetEarlyPostConfig:
+			break;
+
+		case CB_AmdSetMidPostConfig:
+			nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
+#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
+			/* SBIOS must alloc 16K memory for IOMMU MMIO */
+			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
+			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
+					AccessWidth32,
+					&MmcfgBarAddress,
+					nbConfigPtr);
+			MmcfgBarAddress &= ~0xf;
+			if (MmcfgBarAddress != 0) {
+				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
+			}
+			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
+#endif
+			break;
+
+		case CB_AmdSetLatePostConfig:
+			break;
+
+		case CB_AmdSetRecoveryConfig:
+			break;
+	}
+
+	return ret;
+}
+
+
+/**
+ * @brief North Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
+{
+	u16 i = 0;
+	PCI_ADDR PciAddress;
+	u32 val, sbNode, sbLink;
+
+	if (!pConfig) {
+		return;
+	}
+
+	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
+	for (i = 0; i < MAX_NB_COUNT; i++) {
+		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
+		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
+		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
+		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
+	}
+
+	/* Initialize all NB structures */
+	AmdInitializer(pConfig);
+
+	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
+	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
+	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
+	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+
+	/*
+	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
+	 * Always 0:0:0 on single NB platform.
+	 */
+	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+
+	/* Set HT path to NB by SbNode and SbLink */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbNode = (val >> 8) & 0x07;
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbLink = (val >> 8) & 0x07; //assum ganged
+	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
+	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
+	//TODO: other NBs
+
+#ifndef __PRE_RAM__
+	/* If temporrary MMIO enable set up CPU MMIO */
+	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
+		UINT32  MmioBase;
+		UINT32  LinkId;
+		UINT32  SubLinkId;
+		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
+		if (MmioBase != 0) {
+			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
+			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
+			/* Set Limit */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
+					AccessWidth32,
+					0x0,
+					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
+					&(pConfig->Northbridges[i]));
+			/* Set Base */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
+					AccessWidth32,
+					0x0,
+					(MmioBase << 12) | 0x3,
+					&(pConfig->Northbridges[i]));
+		}
+	}
+#endif
+}
+
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
new file mode 100644
index 0000000..a4f4e1a
--- /dev/null
+++ b/src/mainboard/amd/dinar/rd890_cfg.h
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef  _RD890_CFG_H_
+#define _RD890_CFG_H_
+
+#include "NbPlatform.h"
+
+#define RD890_IOAPIC_ADDR 0xC8000000
+/* platform dependent configuration default value */
+
+/**
+ * Path from CPU to NB
+ * [0..7]   - Node  (0..8)
+ * [8..11]  - Link  (0..3)
+ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
+ */
+#ifndef DEFAULT_HT_PATH
+#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x3}
+#endif
+#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x1}
+#endif
+#endif
+
+/**
+ * Bitmap of enabled ports on NB #0/1/2/3
+ * Bit[0] - Reserved
+ * Bit[1] - Reserved
+ * Bit[2] - Enable PCIe port 2
+ * Bit[3] - Enable PCIe port 3
+ * Bit[4] - Enable PCIe port 4
+ * Bit[5] - Enable PCIe port 5
+ * Bit[6] - Enable PCIe port 2
+ * Bit[7] - Enable PCIe port 7
+ * Bit[8] - Reserved
+ * Bit[9] - Enable PCIe port 9
+ * Bit[10]- Enable PCIe port 10
+ * Bit[11]- Enable PCIe port 11
+ * Bit[12]- Enable PCIe port 12
+ * Bit[13]- Enable PCIe port 13
+ * Example:
+ *  port_enable = 0x14
+ *  Port 2 and 4 enabled for training/initialization
+ */
+#ifndef DEFAULT_PORT_ENABLE_MAP
+#define DEFAULT_PORT_ENABLE_MAP		0x0014
+#endif
+
+/**
+ * Bitmap of ports that have slot or onboard device connected.
+ * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
+ * #define DEFAULT_PORT_FORCE_GEN1        0x604
+ */
+#ifndef DEFAULT_PORT_FORCE_GEN1
+#define DEFAULT_PORT_FORCE_GEN1		0x0
+#endif
+
+/**
+ * Bitmap of ports that have server hotplug support
+ */
+#ifndef DEFAULT_HOTPLUG_SUPPORT
+#define DEFAULT_HOTPLUG_SUPPORT		0x0
+#endif
+
+#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
+#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
+#endif
+
+#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
+#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
+#endif
+
+/**
+ * Default GPP1 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP1_CONFIG
+#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP2 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP2_CONFIG
+#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP3a core configuraton on NB #0/1/2/3.
+ * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
+ * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
+ * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
+ * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
+ * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
+ * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
+ */
+#ifndef DEFAULT_GPP3A_CONFIG
+#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
+#endif
+
+
+/**
+ * Default HT Transmitter de-emphasis setting
+ */
+#ifndef DEFAULT_HT_DEEMPASIES
+#define DEFAULT_HT_DEEMPASIES		0x3
+#endif
+
+/**
+ * Default APIC nterrupt base for IOAPIC
+ */
+#ifndef DEFAULT_APIC_INTERRUPT_BASE
+#define DEFAULT_APIC_INTERRUPT_BASE	24
+#endif
+
+
+#define DEFAULT_PLATFORM_CONFIG(name) \
+	NB_PLATFORM_CONFIG name = { \
+		DEFAULT_PORT_ENABLE_MAP, \
+		DEFAULT_PORT_FORCE_GEN1, \
+		DEFAULT_HOTPLUG_SUPPORT, \
+		DEFAULT_HOTPLUG_DESCRIPTOR, \
+		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
+		DEFAULT_GPP1_CONFIG, \
+		DEFAULT_GPP2_CONFIG, \
+		DEFAULT_GPP3A_CONFIG, \
+		DEFAULT_HT_DEEMPASIES, \
+		/*DEFAULT_HT_PATH,*/ \
+		DEFAULT_APIC_INTERRUPT_BASE, \
+	}
+
+/**
+ * Platform configuration
+ */
+typedef struct {
+	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
+	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
+	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
+	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
+	UINT32  TemporaryMmio;            ///< Temporary MMIO
+	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
+	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
+	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
+	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
+	//	HT_PATH NbHtPath;                 ///< HT path to NB
+	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
+} NB_PLATFORM_CONFIG;
+
+/**
+ * Bridge CIMx configuration
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
+
+#endif //_RD890_CFG_H_
diff --git a/src/mainboard/amd/dinar/reset.c b/src/mainboard/amd/dinar/reset.c
new file mode 100644
index 0000000..4cc1efd
--- /dev/null
+++ b/src/mainboard/amd/dinar/reset.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h>		/*inb, outb*/
+#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
new file mode 100644
index 0000000..39d8b45
--- /dev/null
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#include "cpu/x86/bist.h"
+#include "superio/smsc/sch4037/sch4037_early_init.c"
+#include "superio/smsc/sio1036/sio1036_early_init.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "pc80/i8254.c"
+#include "pc80/i8259.c"
+#include "nb_cimx.h"
+#include "sb_cimx.h"
+#include "Platform.h"
+#include <arch/cpu.h>
+
+#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
+u32 agesawrapper_amdinitmmio (void);
+u32 agesawrapper_amdinitreset (void);
+u32 agesawrapper_amdinitearly (void);
+u32 agesawrapper_amdinitenv (void);
+u32 agesawrapper_amdinitlate (void);
+u32 agesawrapper_amdinitpost (void);
+u32 agesawrapper_amdinitmid (void);
+
+
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+	u32 val;
+
+	if (!cpu_init_detectedx && boot_cpu()) {
+
+		post_code(0x30);
+
+		sch4037_early_init (CONFIG_SIO_PORT);
+
+		/* Detect SMSC SIO1036 LPC Debug Card status */
+		if (detect_sio1036_chip(0x4E)) {
+			/* Found SMSC SIO1036 LPC Debug Card */
+			sio1036_early_init(0x4E);
+		}
+
+		post_code(0x31);
+		uart_init();
+		console_init();
+
+		/*
+		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+		 * Disable all Pcie Bridges to work around It.
+		 */
+		sr56x0_rd890_disable_pcie_bridge();
+
+	}
+
+	post_code(0x32);
+	val = agesawrapper_amdinitmmio();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
+
+	/* Halt if there was a built in self test failure */
+	post_code(0x33);
+	report_bist_failure(bist);
+
+	// Load MPB
+	val = cpuid_eax(1);
+	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
+	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
+
+	if(boot_cpu()) {
+		post_code(0x34);
+		sb_Poweron_Init();
+	}
+
+	post_code(0x35);
+	val = agesawrapper_amdinitreset();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
+
+	post_code(0x36);
+	val = agesawrapper_amdinitearly ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
+
+	post_code(0x37);
+	nb_Poweron_Init();
+	post_code(0x38);
+	nb_Ht_Init();
+
+
+	post_code(0x39);
+	val = agesawrapper_amdinitpost ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
+
+	post_code(0x40);
+	val = agesawrapper_amdinitenv ();
+	if(val) {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
+	}
+	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
+
+
+	/* Initialize i8259 pic */
+	post_code(0x41);
+	setup_i8259 ();
+
+	/* Initialize i8254 timers */
+	post_code(0x42);
+	setup_i8254 ();
+
+	post_code(0x43);
+	print_debug("Disabling cache as ram ");
+	disable_cache_as_ram();
+	print_debug("done\n");
+
+	post_code(0x44);
+	copy_and_run(0);
+
+	post_code(0x45);  // Should never see this post code.
+}
+
diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c
new file mode 100644
index 0000000..36a453b
--- /dev/null
+++ b/src/mainboard/amd/dinar/sb700_cfg.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <string.h>
+#include <console/console.h>    /* printk */
+#include "Platform.h"
+#include "sb700_cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb700_cimx_config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
+	memset(sb_config, 0, sizeof(AMDSBCFG));
+
+	/* SB_POWERON_INIT */
+	sb_config->StdHeader.Func = SB_POWERON_INIT;
+
+	/* header */
+	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
+
+	/* static Build Parameters */
+	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+	sb_config->BuildParameters.EcKbd = 0;
+	sb_config->BuildParameters.EcChannel0 = 0;
+	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
+	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
+	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
+	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
+
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
+	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
+	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
+	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
+
+	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
+	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
+	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
+	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
+	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
+	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
+	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
+	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
+	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
+	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
+	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
+	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
+	sb_config->BuildParameters.IdeSsid = IDE_SSID;
+	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
+	sb_config->BuildParameters.LpcSsid = LPC_SSID;
+
+	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
+
+	/* General */
+	sb_config->Spi33Mhz = 1;
+	sb_config->SpreadSpectrum = 0;
+	sb_config->PciClk5 = 0;
+	sb_config->PciClks = 0x1F;
+	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
+	sb_config->TimerClockSource = 2;  // Auto
+	sb_config->S3Resume = 0;
+	sb_config->RebootRequired = 0;
+
+	/* HPET */
+	sb_config->HpetTimer = HPET_TIMER;
+
+	/* USB */
+	sb_config->UsbIntClock = 0;     // Use external clock
+	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
+	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
+	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
+	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
+	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
+	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
+	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
+	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
+
+	sb_config->AcpiS1Supported = 1;
+
+	/* SATA */
+	sb_config->SataController = 1;
+	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
+	sb_config->SataSmbus = 0;
+	sb_config->SataAggrLinkPmCap = 1;
+	sb_config->SataPortMultCap = 1;
+	sb_config->SataClkAutoOff = 1;
+	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
+	//TODO: set to secondary not take effect.
+	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
+	sb_config->SataEspPort = 0;
+	sb_config->SataClkAutoOffAhciMode = 1;
+	sb_config->SataHpcpButNonESP = 0;
+	sb_config->SataHideUnusedPort = 0;
+
+	/* Azalia HDA */
+	sb_config->AzaliaController = AZALIA_CONTROLLER;
+	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
+	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
+	sb_config->pAzaliaOemCodecTablePtr = NULL;
+
+#ifndef __PRE_RAM__
+	/* ramstage cimx config here */
+	if (!sb_config->StdHeader.pCallBack) {
+		sb_config->StdHeader.pCallBack = sb700_callout_entry;
+	}
+
+	//sb_config->
+#endif //!__PRE_RAM__
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
+}
+
diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h
new file mode 100644
index 0000000..b405f0e
--- /dev/null
+++ b/src/mainboard/amd/dinar/sb700_cfg.h
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _SB700_CFG_H_
+#define _SB700_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M                    0
+#define BIOS_SIZE_2M                    1
+#define BIOS_SIZE_4M                    3
+#define BIOS_SIZE_8M                    7
+
+/* In SB700, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+#define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+#define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+#define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM                 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER                      1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CINFIG              0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL                  0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#ifndef SATA_CONTROLLER
+#define SATA_CONTROLLER               1
+#endif
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_MODE
+#define SATA_MODE                     NATIVE_IDE_MODE
+#endif
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE                 0
+#define IDE_NATIVE_MODE                 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_IDE_MODE
+#define SATA_IDE_MODE                 IDE_LEGACY_MODE
+#endif
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK          0x00
+#define INTERNAL_CLOCK          0x01
+
+#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED     1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO                     0
+#define AZALIA_DISABLE                  1
+#define AZALIA_ENABLE                   2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#ifndef AZALIA_CONTROLLER
+#define AZALIA_CONTROLLER             AZALIA_AUTO
+#endif
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#ifndef AZALIA_PIN_CONFIG
+#define AZALIA_PIN_CONFIG             1
+#endif
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+#ifndef AZALIA_SDIN_PIN
+//#define AZALIA_SDIN_PIN             0xAA
+#define AZALIA_SDIN_PIN               0x2A
+#endif
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#ifndef GPP_CONTROLLER
+#define GPP_CONTROLLER                1
+#endif
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#ifndef GPP_CFGMODE
+#define GPP_CFGMODE                   GPP_CFGMODE_X1111
+#endif
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb700_cimx_config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func    Southbridge CIMx Function ID.
+ * @param[in] data    Southbridge Input Data.
+ * @param[in] sb_cfg  Southbridge configuration structure pointer.
+ *
+ */
+u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif //_SB700_CFG_H_


From gerrit at coreboot.org  Fri Jan 20 06:44:51 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:51 +0100
Subject: [coreboot] New patch to review for coreboot: ca51d78 SIO: Winbond
	w83627dhg update
References: <I42eaaf7d70aa48d7edf2710349b51e401526c1a6+0@gerrit.coreboot.org>
Message-ID: <I42eaaf7d70aa48d7edf2710349b51e401526c1a6+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565

-gerrit

commit ca51d783291758a292df19ed65de16558b2ec99f
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:59:55 2012 +0800

    SIO: Winbond w83627dhg update
    
    1. Stop include c file.
    2. W83627dhg Pin 89, Pin 90 are multi function pins,
       add support to select them to I2C function.
    
    Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/superio/winbond/w83627dhg/Makefile.inc   |    2 ++
 src/superio/winbond/w83627dhg/early_serial.c |   25 ++++++++++++++++++++++++-
 src/superio/winbond/w83627dhg/w83627dhg.h    |    4 ++++
 3 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc
index 0b0bb8b..09df47e 100644
--- a/src/superio/winbond/w83627dhg/Makefile.inc
+++ b/src/superio/winbond/w83627dhg/Makefile.inc
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,5 +19,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c
 
diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c
index f530dc6..61747f2 100644
--- a/src/superio/winbond/w83627dhg/early_serial.c
+++ b/src/superio/winbond/w83627dhg/early_serial.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,7 +19,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <device/pnp_def.h>
 #include <stdint.h>
 #include "w83627dhg.h"
 
@@ -35,7 +38,7 @@ static void pnp_exit_ext_func_mode(device_t dev)
 	outb(0xaa, port);
 }
 
-static void w83627dhg_enable_serial(device_t dev, u16 iobase)
+void w83627dhg_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
@@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase)
 	pnp_set_enable(dev, 1);
 	pnp_exit_ext_func_mode(dev);
 }
+
+/**
+ * Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
+ *  {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or
+ *  {RSTOUT3#, RSTOUT2#} or {SDA, SCL}
+ */
+void w83627dhg_enable_i2c(device_t dev)
+{
+	u8 val;
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+
+	val = pnp_read_config(dev, 0x2A);
+	val |= 1 << 1;
+	pnp_write_config(dev, 0x2A, val);
+
+	pnp_exit_ext_func_mode(dev);
+}
+
diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h
index 74761e9..0f1ea85 100644
--- a/src/superio/winbond/w83627dhg/w83627dhg.h
+++ b/src/superio/winbond/w83627dhg/w83627dhg.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -51,4 +52,7 @@
 
 /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
 
+void w83627dhg_enable_serial(device_t dev, u16 iobase);
+void w83627dhg_enable_i2c(device_t dev);
+
 #endif


From gerrit at coreboot.org  Fri Jan 20 06:44:52 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:52 +0100
Subject: [coreboot] New patch to review for coreboot: 76ebf2e SIO: condition
	compile Nuvoton WPCM450 early_init.c
References: <Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878+0@gerrit.coreboot.org>
Message-ID: <Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/566

-gerrit

commit 76ebf2e5f0d04c808ebf893965ddd332cbcce684
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 14:00:03 2012 +0800

    SIO: condition compile Nuvoton WPCM450 early_init.c
    
    Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450
    
    Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/superio/nuvoton/wpcm450/Makefile.inc |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc
index c70b2fb..b4e4ea7 100644
--- a/src/superio/nuvoton/wpcm450/Makefile.inc
+++ b/src/superio/nuvoton/wpcm450/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2011 Advanced Micro Devices, Inc.
+## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,6 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-romstage-y += early_init.c
+romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c
 ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c
 


From gerrit at coreboot.org  Fri Jan 20 06:44:53 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:53 +0100
Subject: [coreboot] New patch to review for coreboot: 05c67a4 Mainboard:
	Supermicro/h8qgi mainboard update
References: <Iaad8c9b08310813441188deee6797b3f6dd37d6d+0@gerrit.coreboot.org>
Message-ID: <Iaad8c9b08310813441188deee6797b3f6dd37d6d+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567

-gerrit

commit 05c67a451fd1c2048aa7a1685abfcc0f4a35aabe
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 14:21:43 2012 +0800

    Mainboard: Supermicro/h8qgi mainboard update
    
    1. Supermicro H8QGI mainboard update to support both family10 Revison D
       processor and family15 model 00-0fh processor in one binary image.
    2. RD890/SR56X0 IO hub CIMX wrapper support.
    3. SP5100/SB700 southbridge CIMX wrapper support.
    
    Both 8 cores and 16 Cores InterLagos Opteron Processor are
    tested on this platform.
    Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.
    
    Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/BiosCallOuts.c   |    2 +-
 src/mainboard/supermicro/h8qgi/BiosCallOuts.h   |    2 +-
 src/mainboard/supermicro/h8qgi/Kconfig          |   20 +-
 src/mainboard/supermicro/h8qgi/Makefile.inc     |   18 ++-
 src/mainboard/supermicro/h8qgi/OptionsIds.h     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/cpstate.asl |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/ide.asl     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/routing.asl |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/sata.asl    |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/usb.asl     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi_tables.c    |   95 +++++---
 src/mainboard/supermicro/h8qgi/agesawrapper.c   |  147 ++++++++-----
 src/mainboard/supermicro/h8qgi/agesawrapper.h   |    2 +-
 src/mainboard/supermicro/h8qgi/buildOpts.c      |  124 +++++++++--
 src/mainboard/supermicro/h8qgi/chip.h           |    2 +-
 src/mainboard/supermicro/h8qgi/cmos.layout      |    2 +-
 src/mainboard/supermicro/h8qgi/devicetree.cb    |   86 ++------
 src/mainboard/supermicro/h8qgi/dimmSpd.c        |   50 ++--
 src/mainboard/supermicro/h8qgi/dsdt.asl         |  217 +++++++-----------
 src/mainboard/supermicro/h8qgi/fadt.c           |   61 ++----
 src/mainboard/supermicro/h8qgi/get_bus_conf.c   |   30 +--
 src/mainboard/supermicro/h8qgi/irq_tables.c     |    8 +-
 src/mainboard/supermicro/h8qgi/mainboard.c      |   40 +++--
 src/mainboard/supermicro/h8qgi/mptable.c        |   59 +++---
 src/mainboard/supermicro/h8qgi/platform_cfg.h   |   54 +++++
 src/mainboard/supermicro/h8qgi/platform_oem.c   |    4 +-
 src/mainboard/supermicro/h8qgi/platform_oem.h   |   29 ---
 src/mainboard/supermicro/h8qgi/rd890_cfg.c      |  274 +++++++++++++++++++++++
 src/mainboard/supermicro/h8qgi/rd890_cfg.h      |  174 ++++++++++++++
 src/mainboard/supermicro/h8qgi/reset.c          |   66 ++++++
 src/mainboard/supermicro/h8qgi/romstage.c       |   79 +++++--
 src/mainboard/supermicro/h8qgi/sb700_cfg.c      |  142 ++++++++++++
 src/mainboard/supermicro/h8qgi/sb700_cfg.h      |  237 ++++++++++++++++++++
 33 files changed, 1504 insertions(+), 532 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
index b7f0124..e83d1f0 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
index 24a05fb..aa2d451 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
old mode 100755
new mode 100644
index 5df0bb4..e900ea8
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_AGESA_FAMILY10
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10
-	select SOUTHBRIDGE_AMD_SR5650
-	select SOUTHBRIDGE_AMD_SP5100
+	select CPU_AMD_AGESA_FAMILY15
+	select CPU_AMD_SOCKET_G34
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15
+	select NORTHBRIDGE_AMD_CIMX_RD890
+	select SOUTHBRIDGE_AMD_CIMX_SB700
 	select SUPERIO_WINBOND_W83627DHG
 	select SUPERIO_NUVOTON_WPCM450
+	select UDELAY_TSC
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
@@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
 	select SERIAL_CPU_INIT
-	select AMDMCT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
+	select TINY_BOOTBLOCK
 	#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
 
-config AMD_AGESA
-	bool
-	default y
-
 config MAINBOARD_DIR
 	string
 	default supermicro/h8qgi
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
old mode 100755
new mode 100644
index b09c5ca..82264a4
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,15 +17,31 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 romstage-y += buildOpts.c
 romstage-y += agesawrapper.c
 romstage-y += dimmSpd.c
 romstage-y += BiosCallOuts.c
 romstage-y += platform_oem.c
 
+ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += platform_oem.c
 
+AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
+CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
+AGESA_ROOT ?= $(AGESA_PREFIX)/f15
+NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
+SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
+
+subdirs-y += ../../../../$(AGESA_ROOT)
+#subdirs-y += ../../../../$(NB_CIMX_ROOT)
+#subdirs-y += ../../../../$(SB_CIMX_ROOT)
+
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
index eb756df..c4441e9 100644
--- a/src/mainboard/supermicro/h8qgi/OptionsIds.h
+++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
old mode 100755
new mode 100644
index 5eca9cc..2cb7aeb
--- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
old mode 100755
new mode 100644
index c79c18c..45303c0
--- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
old mode 100755
new mode 100644
index 8bc06f6..817f0f7
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
old mode 100755
new mode 100644
index bd4acf0..9ce8650
--- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
old mode 100755
new mode 100644
index 81ea9a2..099e7ac
--- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
index b8ce0b0..7314283 100644
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <arch/io.h>
 #include <device/pci.h>
@@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
 
 
 unsigned long acpi_fill_mcfg(unsigned long current)
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 #else
 	apicid_sp5100 = CONFIG_MAX_CPUS + 1
 #endif
-	apicid_sr5650 = apicid_sp5100 + 1;
+		apicid_sr5650 = apicid_sp5100 + 1;
 
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
@@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current)
 			0
 			);
 
-        /* IOAPIC on rs5690 */
-        gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
-        dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-        if (dev) {
-                pci_write_config32(dev, 0xF8, 0x1);
-                dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+	/* IOAPIC on rs5690 */
+	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (dev) {
+		pci_write_config32(dev, 0xF8, 0x1);
+		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
 				apicid_sr5650,
 				dword,
 				gsi_base
 				);
-        }
+	}
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
 			0, //BUS
@@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current)
 	return current;
 }
 
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
+
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
-	//acpi_header_t *ssdt;
+	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start)
 	}
 
 	/* SSDT */
-	/* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
-#ifdef UNUSED_CODE
-	current   = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-	if (ssdt != NULL) {
-		memcpy(current, ssdt, ssdt->length);
+	current	 = (current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
 		ssdt = (acpi_header_t *) current;
-		current += ssdt->length;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	} else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
 	}
-	else {
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
 		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		/* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	} else {
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
-
-	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 #endif
 
-	/* DSDT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 5bb4a9d..dbdd9d7 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,7 +34,6 @@
 #include "Dispatcher.h"
 #include "cpuCacheInit.h"
 #include "amdlib.h"
-#include "platform_oem.h"
 #include "Filecode.h"
 #include "heapManager.h"
 #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
@@ -54,7 +53,7 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-//VOID *AcpiAlib    = NULL;
+VOID *AcpiAlib    = NULL;
 
 
 /*----------------------------------------------------------------------------------------
@@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL;
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
+extern VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
 
 static UINT32 agesawrapper_amdinitcpuio(VOID)
 {
@@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 	UINT32			node;
 	UINT32			sblink;
 	UINT32			i;
+	UINT32			TOM;
 
 	/* get the number of coherent nodes in the system */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
@@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		PciData = 0x00000A03;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-		/* Set F0000000-FFFFFFFF to Node0 sbLink. */
+		/* Set TOM1-FFFFFFFF to Node0 sbLink. */
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
 		PciData = 0x00FFFF00;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciData = 0x00F00000 | 0x03;
+		TOM = (UINT32)MsrRead(TOP_MEM);
+		PciData = (TOM >> 8) | 0x03;
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
@@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 
-		/* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
+		/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink  and enabled VGA IO*/
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
-		PciData = 0x0000E000;
+		PciData = 0x00FFF000;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
-		PciData = 0x00009033;
+		PciData = 0x00000033;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	}
 
@@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
@@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = NULL;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 	AmdResetParams.HtConfig.Depth = 0;
 
 	//MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
@@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 
 	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
-	status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	status = AmdInitEarly(AmdEarlyParamsPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 
-	GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 
@@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	UINT16 i;
 	UINT32 *HeadPtr;
 	AMD_INTERFACE_PARAMS  AmdParamStruct;
+	AMD_POST_PARAMS *PostParams;
 	BIOS_HEAP_MANAGER    *BiosManagerPtr;
 	UINT32 TscRateInMhz;
 	CPU_SPECIFIC_SERVICES *FamilySpecificServices;
@@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	AmdCreateStruct(&AmdParamStruct);
-	status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-	if (status != AGESA_SUCCESS)
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
+	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+	status = AmdInitPost(PostParams);
+	if (status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+	}
 	AmdReleaseStruct(&AmdParamStruct);
 
 	/* Initialize heap space */
@@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	BiosManagerPtr->StartOfAllocatedNodes = 0;
 	BiosManagerPtr->StartOfFreedNodes = 0;
 
-	GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 
@@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_ENV_PARAMS *EnvParams;
 
 	LibAmdMemFill(&AmdParamStruct,
 			0,
@@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
-	status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
+	EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+	status = AmdInitEnv(EnvParams);
 	if (status != AGESA_SUCCESS)
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus);
 
 	AmdReleaseStruct(&AmdParamStruct);
 	return (UINT32)status;
@@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick)
 			return AcpiWheaMce;
 		case PICK_WHEA_CMC:
 			return AcpiWheaCmc;
-/*
 		case PICK_ALIB:
 			return AcpiAlib;
-*/
 		default:
 			return NULL;
 	}
@@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 	status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
@@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID)
 
 UINT32 agesawrapper_amdinitlate(VOID)
 {
-	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AGESA_STATUS		Status;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	AMD_LATE_PARAMS		*AmdLateParamsPtr;
 
-	LibAmdMemFill(&AmdLateParams,
-			0,
-			sizeof(AMD_LATE_PARAMS),
-			&(AmdLateParams.StdHeader));
+	LibAmdMemFill(&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
-	AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	Status = AmdInitLate(&AmdLateParams);
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate(AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
-		agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
 		ASSERT(Status == AGESA_SUCCESS);
 	}
-
-	DmiTable       = AmdLateParams.DmiTable;
-	AcpiPstate     = AmdLateParams.AcpiPState;
-	AcpiSrat       = AmdLateParams.AcpiSrat;
-	AcpiSlit       = AmdLateParams.AcpiSlit;
-
-	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-	//AcpiAlib       = AmdLateParams.AcpiAlib;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
@@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
 		ASSERT(Status <= AGESA_UNSUPPORTED);
 	}
 
-	DmiTable       = AmdLateParams.DmiTable;
-	AcpiPstate     = AmdLateParams.AcpiPState;
-	AcpiSrat       = AmdLateParams.AcpiSrat;
-	AcpiSlit       = AmdLateParams.AcpiSlit;
-
-	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-	//  AcpiAlib       = AmdLateParams.AcpiAlib;
-
 	return (UINT32)Status;
 }
 
@@ -784,9 +811,9 @@ static void agesa_error(EVENT_PARAMS *event)
 			printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
 			break;
 
-		case MEM_ERROR_ECC_DIS:
-			printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
-			break;
+//		case MEM_ERROR_ECC_DIS:
+//			printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
+//			break;
 
 		case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
 			printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
@@ -1141,6 +1168,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
  */
 UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 {
+	printk(BIOS_DEBUG, "enter in %s\n", __func__);
 	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
 
@@ -1164,6 +1192,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 		Status = AmdReadEventLog(&AmdEventParams);
 	}
 
+	printk(BIOS_DEBUG, "exit %s \n", __func__);
 	return (UINT32)Status;
 }
 
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
index 43c7d10..c1eb012 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.h
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 02cf79b..480c7b6 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,7 +70,10 @@
 ////#define BLDOPT_REMOVE_SLIT                     TRUE
 //#define BLDOPT_REMOVE_WHEA                     TRUE
 //#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
+
+/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
+#define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
+
 //#define BLDOPT_REMOVE_HT_ASSIST                TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
@@ -107,7 +110,7 @@
 #define BLDCFG_ONLINE_SPARE                       FALSE
 #define BLDCFG_BANK_SWIZZLE                       TRUE
 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY //DDR800_FREQUENCY
 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 #define BLDCFG_USE_BURST_MODE                     FALSE
@@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
 	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 
+	{1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+	{2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+	{3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
 	/* Coherent link deemphasis. */
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
@@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
 	{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
-
 };
 
 CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 {
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
+	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
+	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
 	{CPU_LIST_TERMINAL}
 };
 
@@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    FALSE//TRUE
+#define AGESA_ENTRY_INIT_RESET                    TRUE//FALSE
 #define AGESA_ENTRY_INIT_RECOVERY                 FALSE
 #define AGESA_ENTRY_INIT_EARLY                    TRUE
 #define AGESA_ENTRY_INIT_POST                     TRUE
@@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 
-#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
+/*
+#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1)
+  #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
+#endif
+#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1)
+  #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
+#endif
+*/
+
+//#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
 #include "MaranelloInstall.h"
 
 /*----------------------------------------------------------------------------------------
@@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
  *----------------------------------------------------------------------------------------
  */
 
+//reference BKDG Table87: works
+#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
+#define SEED_A 0x54
+#define SEED_B 0x4D
+#define SEED_C 0x45
+#define SEED_D 0x40
+
+#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
+//4B 41 51
+
 /*
  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@@ -486,6 +528,53 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 	//      Byte6Seed, Byte7Seed, ByteEccSeed)
 	//      Specifies the write leveling seed for a channel of a socket.
 	//
+#if 0//CONFIG_CPU_AMD_AGESA_FAMILY10
+	/* Specifies the write leveling seed for a channel of a socket.
+	 * WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed,
+	 *                     Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+	 *                     Byte6Seed, Byte7Seed, ByteEccSeed)
+	 */
+	WRITE_LEVELING_SEED(
+			ANY_SOCKET, ANY_CHANNEL, F10_WL_SEED, F10_WL_SEED,
+			F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, F10_WL_SEED,
+			F10_WL_SEED, F10_WL_SEED, F10_WL_SEED),
+#endif
+
+#if 0 //CONFIG_CPU_AMD_AGESA_FAMILY15
+	/* Specifies the write leveling seed for a channel of a socket.
+	 * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
+	 *                     Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
+	 *                     Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
+	 *                     ByteEccSeed)
+	 */
+	WRITE_LEVELING_SEED(
+			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
+			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+			F15_WL_SEED),
+
+	/* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
+	 *              Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
+	 *              Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
+	 */
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+		SEED_A),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
+		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
+		SEED_B),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
+		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
+		SEED_C),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
+		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
+		SEED_D),
+#endif
+
 	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
 	PSO_END
 };
@@ -493,7 +582,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 /*
  * These tables are optional and may be used to adjust memory timing settings
  */
-
 //HY Customer table
 UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
 {
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
index a252705..1181130 100644
--- a/src/mainboard/supermicro/h8qgi/chip.h
+++ b/src/mainboard/supermicro/h8qgi/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
old mode 100755
new mode 100644
index 3b98cbb..0fd4708
--- a/src/mainboard/supermicro/h8qgi/cmos.layout
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
@@ -2,7 +2,7 @@
 #
 #  This file is part of the coreboot project.
 #
-#  Copyright (C) 2011 Advanced Micro Devices, Inc.
+#  Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
old mode 100755
new mode 100644
index 9afaac7..9d77a73
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,20 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa/family10/root_complex
+chip northbridge/amd/agesa/family15/root_complex
 	device lapic_cluster 0 on
-		chip cpu/amd/agesa/family10
-			device lapic 0x10 on end
+		chip cpu/amd/agesa/family15
+			device lapic 0x20 on end #f15
+			#device lapic 0x10 on end #f10
 		end
 	end
 	device pci_domain 0 on
 		subsystemid 0x15d9 0xab11 inherit #SuperMicro
-		chip northbridge/amd/agesa/family10 # CPU side of HT root complex
-			device pci 18.0 on end # link 0
-			device pci 18.0 on end # link 1
-			device pci 18.0 on end # link 2
-			device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
-				chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
+		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
+			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
+				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex 0x9600
 					device pci 0.1 off end # CLKCONFIG
 					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
@@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
 					register "gpp1_configuration" = "0"   # Configuration 16:0 default
 					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
-					#register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
 					register "port_enable" = "0x2104"
-				end #southbridge/amd/sr5650
-				chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+				end #northbridge/amd/cimx/rd890
+				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB1
 					device pci 12.1 on end # USB1
@@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 13.1 on end # USB2
 					device pci 13.2 on end # USB2
 					device pci 14.0 on end # SM
-					device pci 14.1 on end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8qgi doesnt have codec.
+					device pci 14.1 off end # IDE  0x439c
+					device pci 14.2 off end # HDA  0x4383, h8qgi not have codec.
 					device pci 14.3 on # LPC  0x439d
 						chip superio/winbond/w83627dhg
 							device pnp 2e.0 off #  Floppy
@@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 3
 					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/sp5100
+				end # southbridge/amd/cimx/sb700
 			end # device pci 18.0
 
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 			device pci 18.4 on end
-
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-
-
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
-			end
-			device pci 1a.1 on end
-			device pci 1a.2 on end
-			device pci 1a.3 on end
-			device pci 1a.4 on end
-
-			device pci 1b.0 on end
-			device pci 1b.1 on end
-			device pci 1b.2 on end
-			device pci 1b.3 on end
-			device pci 1b.4 on end
-
-
-			device pci 1c.0 on end
-			device pci 1c.1 on end
-			device pci 1c.2 on end
-			device pci 1c.3 on end
-			device pci 1c.4 on end
-
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 on end
-			device pci 1d.4 on end
-
-
-			device pci 1e.0 on end
-			device pci 1e.1 on end
-			device pci 1e.2 on end
-			device pci 1e.3 on end
-			device pci 1e.4 on end
-
-			device pci 1f.0 on end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.4 on end
-
-		end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+			device pci 18.5 on end #f15
+		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #pci_domain
-end #northbridge/amd/agesa/family10/root_complex
+end #northbridge/amd/agesa/family15/root_complex
 
diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
index 4ff21ee..a838cb4 100644
--- a/src/mainboard/supermicro/h8qgi/dimmSpd.c
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -38,14 +38,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
  */
 static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 {
-        u8 value;
-        device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
-
-        value = pci_read_config8(sm_dev, reg);
-        value &= ~(enable);
-        value |= out;
-        value &= ~(enable << 4);
-        pci_write_config8(sm_dev, reg, value);
+	u8 value;
+	device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+
+	value = pci_read_config8(sm_dev, reg);
+	value &= ~(enable);
+	value |= out;
+	value &= ~(enable << 4);
+	pci_write_config8(sm_dev, reg, value);
 }
 
 /*-----------------------------------------------------------------------------
@@ -55,31 +55,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
 	/* socket 0 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 1 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 2 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 3 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 };
 
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
old mode 100755
new mode 100644
index ebdb1eb..3f10012
--- a/src/mainboard/supermicro/h8qgi/dsdt.asl
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,7 +27,7 @@ DefinitionBlock (
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+	/* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */
 
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
@@ -988,73 +988,58 @@ DefinitionBlock (
 
 	Scope(\_GPE) {	/* Start Scope GPE */
 		/*  General event 0  */
-		/* Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L00) {
+		      //DBGO("\\_GPE\\_L00\n")
+		}
 
 		/*  General event 1  */
-		/* Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L01) {
+		      //DBGO("\\_GPE\\_L01\n")
+		}
 
 		/*  General event 2  */
-		/* Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L02) {
+		      //DBGO("\\_GPE\\_L02\n")
+		}
 
 		/*  General event 3  */
 		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
+			//DBGO("\\_GPE\\_L00\n")
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
 		/*  General event 4  */
-		/* Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L04) {
+		      //DBGO("\\_GPE\\_L04\n")
+		}
 
 		/*  General event 5  */
-		/* Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L05) {
+		      //DBGO("\\_GPE\\_L05\n")
+		}
 
-		/*  General event 7 - Used for GPM7, moved to USB.asl */
-		/* Method(_L07) {
-		*	DBGO("\\_GPE\\_L07\n")
-		* }
-		*/
+		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
+		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
 
 		/*  Legacy PM event  */
 		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
+			//DBGO("\\_GPE\\_L08\n")
 		}
 
 		/*  Temp warning (TWarn) event  */
 		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
+			//DBGO("\\_GPE\\_L09\n")
 			Notify (\_TZ.TZ00, 0x80)
 		}
 
 		/*  Reserved  */
-		/* Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
-		* }
-		*/
+		Method(_L0A) {
+		      //DBGO("\\_GPE\\_L0A\n")
+		}
 
 		/*  USB controller PME#  */
 		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
+			//DBGO("\\_GPE\\_L0B\n")
 			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
@@ -1065,126 +1050,81 @@ DefinitionBlock (
 		}
 
 		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
-		* }
-		*/
+		Method(_L0C) {
+		      //DBGO("\\_GPE\\_L0C\n")
+		}
 
 		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
-		* }
-		*/
+		Method(_L0D) {
+		      //DBGO("\\_GPE\\_L0D\n")
+		}
 
-		/*  GPM9 SCI event - Moved to USB.asl */
-		/* Method(_L0E) {
-		*	DBGO("\\_GPE\\_L0E\n")
-		* }
-		*/
+		/* _L0E GPM9 SCI event - Moved to USB.asl */
 
 		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
-		* }
-		*/
+		Method(_L0F) {
+			//DBGO("\\_GPE\\_L0F\n")
+		}
 
 		/*  ExtEvent0 SCI event  */
 		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
+			//DBGO("\\_GPE\\_L10\n")
 		}
 
 
 		/*  ExtEvent1 SCI event  */
 		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
+			//DBGO("\\_GPE\\_L11\n")
 		}
 
 		/*  PCIe PME# event  */
-		/* Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
-		* }
-		*/
-
-		/*  GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
-		* }
-		*/
-
-		/*  GPM1 SCI event - Moved to USB.asl */
-		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
-		* }
-		*/
-
-		/*  GPM2 SCI event - Moved to USB.asl */
-		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
-		* }
-		*/
-
-		/*  GPM3 SCI event - Moved to USB.asl */
-		/* Method(_L16) {
-		*	DBGO("\\_GPE\\_L16\n")
-		* }
-		*/
+		Method(_L12) {
+		      //DBGO("\\_GPE\\_L12\n")
+		}
 
-		/*  GPM8 SCI event - Moved to USB.asl */
-		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
-		* }
-		*/
+		/* _L13 GPM0 SCI event - Moved to USB.asl */
+		/* _L14 GPM1 SCI event - Moved to USB.asl */
+		/* _L15 GPM2 SCI event - Moved to USB.asl */
+		/* _L16 GPM3 SCI event - Moved to USB.asl */
+		/* _L17 GPM8 SCI event - Moved to USB.asl */
 
 		/*  GPIO0 or GEvent8 event  */
 		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
+			//DBGO("\\_GPE\\_L18\n")
 			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
-		/*  GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
-		* }
-		*/
-
-		/*  GPM5 SCI event - Moved to USB.asl */
-		/* Method(_L1A) {
-		*	DBGO("\\_GPE\\_L1A\n")
-		* }
-		*/
+		/* _L19 GPM4 SCI event - Moved to USB.asl */
+		/* _L1A GPM5 SCI event - Moved to USB.asl */
 
 		/*  Azalia SCI event  */
 		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
+			//DBGO("\\_GPE\\_L1B\n")
 			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
 		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
-		* }
-		*/
+		Method(_L1C) {
+		      //DBGO("\\_GPE\\_L1C\n")
+		}
 
 		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
-		* }
-		*/
+		Method(_L1D) {
+		      //DBGO("\\_GPE\\_L1D\n")
+		}
 
 		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
-		* }
-		*/
+		Method(_L1E) {
+			//DBGO("\\_GPE\\_L1E\n")
+		}
 
-		/*  SATA SCI event - Moved to sata.asl */
-		/* Method(_L1F) {
-		*	 DBGO("\\_GPE\\_L1F\n")
-		* }
-		*/
+		/* _L1F SATA SCI event - Moved to sata.asl */
 
 	} 	/* End Scope GPE */
 
@@ -1569,7 +1509,7 @@ DefinitionBlock (
 					0x0CF8,             // Range Maximum
 					0x01,               // Alignment
 					0x08,               // Length
-				   	)
+					)
 
 				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 					0x0000,             // Granularity
@@ -1602,10 +1542,10 @@ DefinitionBlock (
 					,, , TypeStatic)
 				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 					0x0000,             // Granularity
-					0x9000,             // Range Minimum
-					0xefff,             // Range Maximum
+					0x0D00,             // Range Minimum
+					0xFFFF,             // Range Maximum
 					0x0000,             // Translation Offset
-					0x6000,             // Length
+					0xF300,             // Length
 					,, , TypeStatic)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
 
@@ -1613,21 +1553,26 @@ DefinitionBlock (
 						0xE0000000,         // Address Base
 						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
 						MMIO)
-				DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-						0x00000000,         // Granularity
-						0xF0000000,         // Range Minimum
-						0xFFFFFFFF,         // Range Maximum
-						0x00000000,         // Translation Offset
-						0x10000000,         // Length
-						,, , AddressRangeMemory, TypeStatic)
 			})
 
 			Method (_CRS, 0, NotSerialized)
 			{
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-				Store (PCBA, BAS1)
-				Store (PCLN, LEN1)
+
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+				Store(TOM1, BAS1)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, LEN1)
+				//DBGO(TOM1)
 
 				Return (CRS)
 			}
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
index c2f714d..0c63162 100644
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,21 +28,17 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-#include "southbridge/amd/sb700/sb700.h"
+#include "Platform.h" /*sb700 platform header*/
 
-u16 pm_base = SB700_ACPI_IO_BASE;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb700. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
+#ifndef ACPI_BLK_BASE
+  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
+#endif
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
 
-	pm_base &= 0xFFFF;
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
@@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 
-	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
-	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
-	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
-	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
-	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
-	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
-	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
-	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
-
-	/* CpuControl is in \_PR.CPU0, 6 bytes */
-	pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
-	pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
-
-	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
-	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
-
-	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
-	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
-						      * the contents of the PM registers at
-						      * index 60-6B to decode ACPI I/O address.
-						      * AcpiSmiEn & SmiCmdEn*/
 	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
 	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
 	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
 	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
 
 	fadt->pm1_evt_len = 4;
@@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_evt_blk.bit_width = 32;
 	fadt->x_pm1a_evt_blk.bit_offset = 0;
 	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 	fadt->x_pm1a_evt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_evt_blk.space_id = 1;
@@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
 	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm2_cnt_blk.bit_width = 0;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
 	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
 
@@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
 	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
 
@@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_gpe0_blk.bit_width = 32;
 	fadt->x_gpe0_blk.bit_offset = 0;
 	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 	fadt->x_gpe0_blk.addrh = 0x0;
 
 
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
index 14e6bca..8c31cbf 100644
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,8 +23,10 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/amd/amdfam10_sysconf.h>
 #include "agesawrapper.h"
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
 
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -34,22 +36,6 @@ u8 bus_isa;
 u8 bus_sp5100[2];
 u8 bus_sr5650[14];
 
-/*
- * Here you only need to set value in pci1234 for HT-IO that could be installed or not
- * You may need to preset pci1234 for HTIO board,
- * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- */
-u32 pci1234x[] = {
-	0x0000ff0,
-};
-
-/*
- * HT Chain device num, actually it is unit id base of every ht device in chain,
- * assume every chain only have 4 ht device at most
- */
-u32 hcdnx[] = {
-	0x20202020,
-};
 
 u32 bus_type[256];
 
@@ -106,8 +92,7 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;  /* pci */
 
-	bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
-	//  bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sr5650[0] = 0;
 	bus_sp5100[0] = bus_sr5650[0];
 
 	/* sp5100 */
@@ -151,4 +136,9 @@ void get_bus_conf(void)
 
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
+
+#if CONFIG_AMD_SB_CIMX
+	sb_After_Pci_Init();
+	sb_Late_Post();
+#endif
 }
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
index 640a0a6..11e5256 100644
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,9 +27,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+		u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+		u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+		u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index f00b5a0..675c87f 100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,36 +25,48 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include "southbridge/amd/sr5650/cmn.h"
+#include <NbPlatform.h>
 #include "chip.h"
 
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
+void set_pcie_dereset(void *nbconfig);
+void set_pcie_reset(void *nbconfig);
 
 /**
  *
  */
-void set_pcie_reset(void)
+void set_pcie_reset(void *nbconfig)
 {
 }
 
 /**
+ * Mainboard specific RD890 CIMx callback
  * Release Resets to PCIe Links
- * PCIE_RESET_GPIO1,2,4,5
+ * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
  */
-void set_pcie_dereset(void)
+void set_pcie_dereset(void *nbconfig)
 {
-	device_t pcie_core_dev;
+	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+	u32 i;
+	u32 val;
+	u32 nb_addr;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
-	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
+	val = 0x00000007UL;
+	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
+	for (i = 0; i < MAX_NB_COUNT; i ++) {
+		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
+		LibNbPciIndexRMW(nb_addr,
+				NB_HTIU_REGA8,
+				AccessS3SaveWidth32,
+				~val,
+				val,
+				 &(pConfig->Northbridges[i]));
+	}
 }
 
 
 /*************************************************
-* enable the dedicated function in h8qgi board.
-*************************************************/
+ * enable the dedicated function in h8qgi board.
+ *************************************************/
 static void h8qgi_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem)
 
 struct chip_operations mainboard_ops = {
 	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
-	.enable_dev = h8qgi_enable,
+		.enable_dev = h8qgi_enable,
 };
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 5c01994..92771bd 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,17 +33,16 @@ extern u8 bus_sp5100[2];
 extern u32 bus_type[256];
 extern u32 sbdn_sr5650;
 extern u32 sbdn_sp5100;
+extern u8 bus_isa;
 
 
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	int bus_isa;
 	u32 apicid_sp5100;
 	u32 apicid_sr5650;
 	device_t dev;
 	u32 dword;
-	u8 byte;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	mptable_init(mc, LAPIC_ADDR);
@@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v)
 #if CONFIG_MAX_CPUS >= 16
 	apicid_sp5100 = 0x0;
 #else
-	apicid_sp5100 = CONFIG_MAX_CPUS + 1;
+	apicid_sp5100 = CONFIG_MAX_CPUS + 1
 #endif
 	apicid_sr5650 = apicid_sp5100 + 1;
 
-	//bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
 	dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
 	if (dev) {
 		/* Set SP5100 IOAPIC ID */
 		dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
 		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
 
+#ifdef UNUSED_CODE
+		u8 byte;
 		/* Initialize interrupt mapping */
 		/* aza */
 		byte = pci_read_config8(dev, 0x63);
@@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v)
 		dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
 		/* dword |= 1<<22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
+#endif
 
 		/*
 		 * 00:12.0: PROG SATA : INT F
@@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v)
 
 		/* Set RS5650 IOAPIC ID */
 		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-                if (dev) {
-                        pci_write_config32(dev, 0xF8, 0x1);
-                        dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-                        smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
-                }
+		if (dev) {
+			pci_write_config32(dev, 0xF8, 0x1);
+			dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
+		}
 
 	}
 
@@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v)
 	 * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
 	 */
 
-        //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
-        //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
 
 	/* PCI slots */
-        /* PCI_SLOT 0. */
-        PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
-        PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
-        PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
-        PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
-        /* PCI_SLOT 1. */
-        PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
-        PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
-        PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
-        PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
-        /* PCI_SLOT 2. */
-        PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
-        PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
-        PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
-        PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
 
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h
new file mode 100644
index 0000000..bbc4ad7
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_CFG_H_
+#define _PLATFORM_CFG_H_
+
+
+/* northbridge customize options */
+/**
+ * Max number of northbridges in the system
+ */
+#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
+
+/**
+ *  Enable check for PCIe endpoint to be ready for PCI enumeration.
+ *
+ */
+//#define  EPREADY_WORKAROUND_DISABLED
+
+/**
+ *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
+ *
+ */
+#define  IOMMU_SUPPORT_DISABLE //TODO: enable it
+
+/**
+ *  Disable server PCIe hotplug support.
+ */
+
+//#define HOTPLUG_SUPPORT_DISABLED
+
+/**
+ *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
+ */
+
+//#define DEVICE_REMAP_DISABLE
+
+#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
index f36b0d8..883cad1 100644
--- a/src/mainboard/supermicro/h8qgi/platform_oem.c
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
 #include "amdlib.h"
 #include "Ids.h"
 #include "heapManager.h"
-#include "platform_oem.h"
 #include "Filecode.h"
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -43,6 +42,7 @@
  *
  **/
 /*---------------------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
 	//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
deleted file mode 100644
index ab0d6df..0000000
--- a/src/mainboard/supermicro/h8qgi/platform_oem.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#ifndef _PLATFORM_OEM_H_
-#define _PLATFORM_OEM_H_
-
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
-VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
-
-#endif //_PLATFORM_OEM_H_
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
new file mode 100644
index 0000000..7a947b3
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "NbPlatform.h"
+#include "rd890_cfg.h"
+#include "northbridge/amd/cimx/rd890/chip.h"
+#include "nbInitializer.h"
+#include <string.h>
+#include <arch/ioapic.h>
+
+#ifndef __PRE_RAM__
+#include <device/device.h>
+extern void set_pcie_reset(void *config);
+extern void set_pcie_dereset(void *config);
+
+/**
+ * Platform dependent configuration at ramstage
+ */
+static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
+{
+	u16 i;
+	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
+	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
+	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
+	DEFAULT_PLATFORM_CONFIG(platform_config);
+
+	/* update the platform depentent configuration by devicetree */
+	rd890_info  = nb_dev->chip_info;
+	platform_config.PortEnableMap = rd890_info->port_enable;
+	if (rd890_info->gpp1_configuration == 0) {
+		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp1_configuration == 1) {
+		platform_config.Gpp1Config = GFX_CONFIG_AABB;
+	}
+	if (rd890_info->gpp2_configuration == 0) {
+		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp2_configuration == 1) {
+		platform_config.Gpp2Config = GFX_CONFIG_AABB;
+	}
+	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
+
+	if (platform_config.Gpp1Config != 0) {
+		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
+	}
+	if (platform_config.Gpp2Config != 0) {
+		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
+	}
+	if (platform_config.Gpp3aConfig != 0) {
+		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
+	}
+
+	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
+	for (i = 0; i <= MAX_CORE_ID; i++) {
+		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
+		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
+	}
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
+	}
+
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
+			pPcieConfig->PortConfiguration[i].PortPresent = ON;
+			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
+				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
+			}
+			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
+				u16 j;
+				pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
+				/* Set Hotplug descriptor info */
+				for (j = 0; j < 8; j++) {
+					u32 PortDescriptor;
+					PortDescriptor = platform_config.PortHotplugDescriptors[j];
+					if ((PortDescriptor & 0xF) == j) {
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+}
+#endif // __PRE_RAM__
+
+/**
+ * @brief Entry point of Northbridge CIMx callout/CallBack
+ *
+ * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+ *
+ * @param[in] u32 func               Northbridge CIMx CallBackId
+ * @param[in] u32 data               Northbridge Input Data.
+ * @param[in] AMD_NB_CONFIG *config  Northbridge configuration structure pointer.
+ *
+ */
+static u32 rd890_callout_entry(u32 func, u32 data, void *config)
+{
+	u32 ret = 0;
+#ifndef __PRE_RAM__
+	device_t nb_dev = (device_t)data;
+#endif
+	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
+
+	switch (func) {
+		case PHCB_AmdPortTrainingCompleted:
+			break;
+
+		case PHCB_AmdPortResetDeassert:
+#ifndef __PRE_RAM__
+			set_pcie_dereset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetAssert:
+#ifndef __PRE_RAM__
+			set_pcie_reset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetSupported:
+			break;
+		case PHCB_AmdGeneratePciReset:
+			break;
+		case PHCB_AmdGetExclusionTable:
+			break;
+		case PHCB_AmdAllocateBuffer:
+			break;
+		case PHCB_AmdUpdateApicInterruptMapping:
+			break;
+		case PHCB_AmdFreeBuffer:
+			break;
+		case PHCB_AmdLocateBuffer:
+			break;
+		case PHCB_AmdReportEvent:
+			break;
+		case PHCB_AmdPcieAsmpInfo:
+			break;
+
+		case CB_AmdSetNbPorConfig:
+			break;
+		case CB_AmdSetHtConfig:
+			/*TODO: different HT path and deempasis for each NB */
+			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
+
+			break;
+		case CB_AmdSetPcieEarlyConfig:
+#ifndef __PRE_RAM__
+			nb_platform_config(nb_dev, nbConfigPtr);
+#endif
+			break;
+
+		case CB_AmdSetEarlyPostConfig:
+			break;
+
+		case CB_AmdSetMidPostConfig:
+			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
+#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
+			/* SBIOS must alloc 16K memory for IOMMU MMIO */
+			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
+			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
+					AccessWidth32,
+					&MmcfgBarAddress,
+					nbConfigPtr);
+			MmcfgBarAddress &= ~0xf;
+			if (MmcfgBarAddress != 0) {
+				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
+			}
+			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
+#endif
+			break;
+
+		case CB_AmdSetLatePostConfig:
+			break;
+
+		case CB_AmdSetRecoveryConfig:
+			break;
+	}
+
+	return ret;
+}
+
+
+/**
+ * @brief North Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
+{
+	u16 i = 0;
+	PCI_ADDR PciAddress;
+	u32 val, sbNode, sbLink;
+
+	if (!pConfig) {
+		return;
+	}
+
+	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
+	for (i = 0; i < MAX_NB_COUNT; i++) {
+		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
+		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
+		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
+		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
+	}
+
+	/* Initialize all NB structures */
+	AmdInitializer(pConfig);
+
+	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
+	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
+	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
+	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+
+	/*
+	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
+	 * Always 0:0:0 on single NB platform.
+	 */
+	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+
+	/* Set HT path to NB by SbNode and SbLink */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbNode = (val >> 8) & 0x07;
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbLink = (val >> 8) & 0x07; //assum ganged
+	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
+	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
+	//TODO: other NBs
+
+#ifndef __PRE_RAM__
+	/* If temporrary MMIO enable set up CPU MMIO */
+	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
+		UINT32  MmioBase;
+		UINT32  LinkId;
+		UINT32  SubLinkId;
+		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
+		if (MmioBase != 0) {
+			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
+			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
+			/* Set Limit */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
+					AccessWidth32,
+					0x0,
+					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
+					&(pConfig->Northbridges[i]));
+			/* Set Base */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
+					AccessWidth32,
+					0x0,
+					(MmioBase << 12) | 0x3,
+					&(pConfig->Northbridges[i]));
+		}
+	}
+#endif
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
new file mode 100644
index 0000000..8f45019
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef  _RD890_CFG_H_
+#define _RD890_CFG_H_
+
+#include "NbPlatform.h"
+
+/* platform dependent configuration default value */
+
+/**
+ * Path from CPU to NB
+ * [0..7]   - Node  (0..8)
+ * [8..11]  - Link  (0..3)
+ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
+ */
+#ifndef DEFAULT_HT_PATH
+#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x3}
+#endif
+#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x1}
+#endif
+#endif
+
+/**
+ * Bitmap of enabled ports on NB #0/1/2/3
+ * Bit[0] - Reserved
+ * Bit[1] - Reserved
+ * Bit[2] - Enable PCIe port 2
+ * Bit[3] - Enable PCIe port 3
+ * Bit[4] - Enable PCIe port 4
+ * Bit[5] - Enable PCIe port 5
+ * Bit[6] - Enable PCIe port 2
+ * Bit[7] - Enable PCIe port 7
+ * Bit[8] - Reserved
+ * Bit[9] - Enable PCIe port 9
+ * Bit[10]- Enable PCIe port 10
+ * Bit[11]- Enable PCIe port 11
+ * Bit[12]- Enable PCIe port 12
+ * Bit[13]- Enable PCIe port 13
+ * Example:
+ *  port_enable = 0x14
+ *  Port 2 and 4 enabled for training/initialization
+ */
+#ifndef DEFAULT_PORT_ENABLE_MAP
+#define DEFAULT_PORT_ENABLE_MAP		0x0014
+#endif
+
+/**
+ * Bitmap of ports that have slot or onboard device connected.
+ * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
+ * #define DEFAULT_PORT_FORCE_GEN1        0x604
+ */
+#ifndef DEFAULT_PORT_FORCE_GEN1
+#define DEFAULT_PORT_FORCE_GEN1		0x0
+#endif
+
+/**
+ * Bitmap of ports that have server hotplug support
+ */
+#ifndef DEFAULT_HOTPLUG_SUPPORT
+#define DEFAULT_HOTPLUG_SUPPORT		0x0
+#endif
+
+#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
+#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
+#endif
+
+#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
+#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
+#endif
+
+/**
+ * Default GPP1 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP1_CONFIG
+#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP2 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP2_CONFIG
+#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP3a core configuraton on NB #0/1/2/3.
+ * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
+ * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
+ * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
+ * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
+ * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
+ * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
+ */
+#ifndef DEFAULT_GPP3A_CONFIG
+#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
+#endif
+
+
+/**
+ * Default HT Transmitter de-emphasis setting
+ */
+#ifndef DEFAULT_HT_DEEMPASIES
+#define DEFAULT_HT_DEEMPASIES		0x3
+#endif
+
+/**
+ * Default APIC nterrupt base for IOAPIC
+ */
+#ifndef DEFAULT_APIC_INTERRUPT_BASE
+#define DEFAULT_APIC_INTERRUPT_BASE	24
+#endif
+
+
+#define DEFAULT_PLATFORM_CONFIG(name) \
+	NB_PLATFORM_CONFIG name = { \
+		DEFAULT_PORT_ENABLE_MAP, \
+		DEFAULT_PORT_FORCE_GEN1, \
+		DEFAULT_HOTPLUG_SUPPORT, \
+		DEFAULT_HOTPLUG_DESCRIPTOR, \
+		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
+		DEFAULT_GPP1_CONFIG, \
+		DEFAULT_GPP2_CONFIG, \
+		DEFAULT_GPP3A_CONFIG, \
+		DEFAULT_HT_DEEMPASIES, \
+		/*DEFAULT_HT_PATH,*/ \
+		DEFAULT_APIC_INTERRUPT_BASE, \
+	}
+
+/**
+ * Platform configuration
+ */
+typedef struct {
+	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
+	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
+	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
+	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
+	UINT32  TemporaryMmio;            ///< Temporary MMIO
+	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
+	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
+	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
+	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
+	//	HT_PATH NbHtPath;                 ///< HT path to NB
+	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
+} NB_PLATFORM_CONFIG;
+
+/**
+ * Bridge CIMx configuration
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
+
+#endif //_RD890_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c
new file mode 100644
index 0000000..68a39f2
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/reset.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h>		/*inb, outb*/
+#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 08b0eb2..119593e 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,34 +29,54 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "agesawrapper.h"
 #include "northbridge/amd/agesa/family10/reset_test.h"
-#include "southbridge/amd/sr5650/sr5650.h"
-#include "southbridge/amd/sb700/sb700.h"
+#include <nb_cimx.h>
+#include <sb_cimx.h>
 #include "superio/nuvoton/wpcm450/wpcm450.h"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 
 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
 
+//TODO: should not put here
+static void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, base);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= 1 << 2;
+	pci_write_config8(dev, 0x48, reg8);
+}
+
+static void sb7xx_51xx_disable_wideio(u8 wio_index)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, 0);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(dev, 0x48, reg8);
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	post_code(0x30);
 	agesawrapper_amdinitmmio();
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-		/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
-		 * disable all pcie bridges on SR56x0 to work around it
-		 */
-		sr5650_disable_pcie_bridge();
-		post_code(0x31);
-		sb7xx_51xx_lpc_port80();
-		post_code(0x32);
-	}
+	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
 	report_bist_failure(bist);
 
-	enable_sr5650_dev8();
-	sb7xx_51xx_lpc_init();
 	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
 	wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
 	sb7xx_51xx_disable_wideio(0);
@@ -78,7 +98,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
 	}
 
-	post_code(0x38);
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x38);
+		/*
+		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+		 * Disable all Pcie Bridges to work around It.
+		 */
+		sr56x0_rd890_disable_pcie_bridge();
+		post_code(0x39);
+		nb_Poweron_Init();
+		post_code(0x3A);
+		sb_Poweron_Init();
+	}
+	post_code(0x3B);
 	val = agesawrapper_amdinitearly();
 	if(val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
@@ -86,12 +118,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
 	}
 
-	sr5650_early_setup();
-	post_code(0x39);
-
-	sb7xx_51xx_early_setup();
-	sr5650_htinit();
-	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	post_code(0x3C);
+	nb_Ht_Init();
+	post_code(0x3D);
+	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	if (!warm_reset_detect(0)) {
 		print_info("...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
@@ -103,8 +133,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	val = agesawrapper_amdinitpost();
 	if (val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 	}
-	printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 
 	post_code(0x41);
 	val = agesawrapper_amdinitenv();
@@ -114,8 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
 
 	post_code(0x42);
-	sr5650_before_pci_init();
-	sb7xx_51xx_before_pci_init();
 
 	post_code(0x50);
 	print_debug("Disabling cache as ram ");
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
new file mode 100644
index 0000000..4cbb8ca
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <string.h>
+#include <console/console.h>    /* printk */
+#include "Platform.h"
+#include "sb700_cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb700_cimx_config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
+	memset(sb_config, 0, sizeof(AMDSBCFG));
+
+	/* SB_POWERON_INIT */
+	sb_config->StdHeader.Func = SB_POWERON_INIT;
+
+	/* header */
+	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
+
+	/* static Build Parameters */
+	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+	sb_config->BuildParameters.EcKbd = 0;
+	sb_config->BuildParameters.EcChannel0 = 0;
+	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
+	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
+	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
+	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
+
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
+	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
+	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
+	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
+
+	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
+	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
+	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
+	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
+	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
+	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
+	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
+	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
+	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
+	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
+	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
+	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
+	sb_config->BuildParameters.IdeSsid = IDE_SSID;
+	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
+	sb_config->BuildParameters.LpcSsid = LPC_SSID;
+
+	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
+
+	/* General */
+	sb_config->Spi33Mhz = 1;
+	sb_config->SpreadSpectrum = 0;
+	sb_config->PciClk5 = 0;
+	sb_config->PciClks = 0x1F;
+	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
+	sb_config->TimerClockSource = 2;  // Auto
+	sb_config->S3Resume = 0;
+	sb_config->RebootRequired = 0;
+
+	/* HPET */
+	sb_config->HpetTimer = HPET_TIMER;
+
+	/* USB */
+	sb_config->UsbIntClock = 0;     // Use external clock
+	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
+	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
+	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
+	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
+	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
+	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
+	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
+	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
+
+	sb_config->AcpiS1Supported = 1;
+
+	/* SATA */
+	sb_config->SataController = 1;
+	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
+	sb_config->SataSmbus = 0;
+	sb_config->SataAggrLinkPmCap = 1;
+	sb_config->SataPortMultCap = 1;
+	sb_config->SataClkAutoOff = 1;
+	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
+	//TODO: set to secondary not take effect.
+	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
+	sb_config->SataEspPort = 0;
+	sb_config->SataClkAutoOffAhciMode = 1;
+	sb_config->SataHpcpButNonESP = 0;
+	sb_config->SataHideUnusedPort = 0;
+
+	/* Azalia HDA */
+	sb_config->AzaliaController = AZALIA_CONTROLLER;
+	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
+	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
+	sb_config->pAzaliaOemCodecTablePtr = NULL;
+
+#ifndef __PRE_RAM__
+	/* ramstage cimx config here */
+	if (!sb_config->StdHeader.pCallBack) {
+		sb_config->StdHeader.pCallBack = sb700_callout_entry;
+	}
+
+	//sb_config->
+#endif //!__PRE_RAM__
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
new file mode 100644
index 0000000..aac61ec
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _SB700_CFG_H_
+#define _SB700_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M                    0
+#define BIOS_SIZE_2M                    1
+#define BIOS_SIZE_4M                    3
+#define BIOS_SIZE_8M                    7
+
+/* In SB700, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+#define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+#define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+#define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM                 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER                      1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CINFIG              0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL                  0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#ifndef SATA_CONTROLLER
+#define SATA_CONTROLLER               1
+#endif
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_MODE
+#define SATA_MODE                     NATIVE_IDE_MODE
+#endif
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE                 0
+#define IDE_NATIVE_MODE                 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_IDE_MODE
+#define SATA_IDE_MODE                 IDE_LEGACY_MODE
+#endif
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK          0x00
+#define INTERNAL_CLOCK          0x01
+
+#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED     1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO                     0
+#define AZALIA_DISABLE                  1
+#define AZALIA_ENABLE                   2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#ifndef AZALIA_CONTROLLER
+#define AZALIA_CONTROLLER             AZALIA_AUTO
+#endif
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#ifndef AZALIA_PIN_CONFIG
+#define AZALIA_PIN_CONFIG             1
+#endif
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+#ifndef AZALIA_SDIN_PIN
+//#define AZALIA_SDIN_PIN             0xAA
+#define AZALIA_SDIN_PIN               0x2A
+#endif
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#ifndef GPP_CONTROLLER
+#define GPP_CONTROLLER                1
+#endif
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#ifndef GPP_CFGMODE
+#define GPP_CFGMODE                   GPP_CFGMODE_X1111
+#endif
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb700_cimx_config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func    Southbridge CIMx Function ID.
+ * @param[in] data    Southbridge Input Data.
+ * @param[in] sb_cfg  Southbridge configuration structure pointer.
+ *
+ */
+u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif //_SB700_CFG_H_


From gerrit at coreboot.org  Fri Jan 20 06:44:54 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:54 +0100
Subject: [coreboot] New patch to review for coreboot: 82c2b07 H8QGI:
	supermicro/h8qgi xip size increase from 512K to 1M Bytes.
References: <I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe+0@gerrit.coreboot.org>
Message-ID: <I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568

-gerrit

commit 82c2b079985b8e647b3ab0913fde62d4de75e361
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 14:21:45 2012 +0800

    H8QGI: supermicro/h8qgi xip size increase from 512K to 1M Bytes.
    
    Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/Kconfig |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index e900ea8..201df45 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -123,5 +123,19 @@ config VGA_BIOS_ID
 	depends on VGA_BIOS
 	default "102b,0532"
 
+config XIP_ROM_BASE
+	hex
+	default 0xfff00000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+	help
+	  Overwride the default write through caching size as 1M Bytes.
+	  On some AMD paltform, one socket support 2 kinds of processor family,
+	  Compiling 2 cpu families agesa code will increase the romstage size.
+	  In order to execute romstage in place on the flash rom,
+	  more space is required to be set as write through caching.
+
 endif # BOARD_SUPERMICRO_H8QGI
 


From gerrit at coreboot.org  Fri Jan 20 06:44:55 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:55 +0100
Subject: [coreboot] New patch to review for coreboot: 46e3263 HWM: Winbond
	W83795 HWM support
References: <I8756f5ed02dc2fa0884cde36e51451fd8aacee27+0@gerrit.coreboot.org>
Message-ID: <I8756f5ed02dc2fa0884cde36e51451fd8aacee27+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569

-gerrit

commit 46e3263aaa1e8d150e877a2d710521e4959c5c30
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 14:21:47 2012 +0800

    HWM: Winbond W83795 HWM support
    
    Supermicro H8QGI-F 1 Unit Chassis contain 8 system Fans,
    they are controled by a saparate W83795 Hardware Monitor chip.
    This patch add the w83795 HWM support.
    
    Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/Makefile.inc |    1 +
 src/mainboard/supermicro/h8qgi/romstage.c   |    9 ++
 src/mainboard/supermicro/h8qgi/w83795.c     |  186 +++++++++++++++++++++++++++
 src/mainboard/supermicro/h8qgi/w83795.h     |   73 +++++++++++
 4 files changed, 269 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
index 82264a4..ef81caf 100644
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -17,6 +17,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+romstage-y += w83795.c
 romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 119593e..15828fe 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -33,6 +33,7 @@
 #include <sb_cimx.h>
 #include "superio/nuvoton/wpcm450/wpcm450.h"
 #include "superio/winbond/w83627dhg/w83627dhg.h"
+#include "w83795.h"
 
 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
 
@@ -119,6 +120,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x3C);
+	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
+	 * In order to access W83795G/ADG HWM using I2C protocol,
+	 * we select function to SDA, SCL function (or GP33, GP32 function).
+	 */
+	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
+	w83795_init(THERMAL_CRUISE_MODE);
+	w83627dhg_enable_serial(PNP_DEV(0x2E, W83627DHG_SP1), CONFIG_TTYS0_BASE);
+
 	nb_Ht_Init();
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
diff --git a/src/mainboard/supermicro/h8qgi/w83795.c b/src/mainboard/supermicro/h8qgi/w83795.c
new file mode 100644
index 0000000..7832dfa
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/w83795.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
+#include "w83795.h"
+
+static u32 w83795_set_bank(u8 bank)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank);
+}
+
+static u8 w83795_read(u16 reg)
+{
+	u32 ret;
+
+	ret = w83795_set_bank(reg >> 8);
+	if (ret < 0) {
+		printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff);
+	return ret;
+}
+
+static u8 w83795_write(u16 reg, u8 value)
+{
+	u32 err;
+
+	err = w83795_set_bank(reg >> 8);
+	if (err < 0) {
+		printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value);
+	return err;
+}
+
+#if 0
+static void w83795_set_speed(void)
+{
+
+}
+
+static void w83795_set_ttti(void)//KR it works
+{
+	u32 i;
+	for (i = 0; i < 6; i++) {
+		//w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40
+		//w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80
+	}
+}
+#endif
+
+static void w83795_set_tfmr(w83795_fan_mode_t mode)
+{
+	u8 val;
+	u8 i;
+
+	if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) {
+		val = 0xFF;
+	} else {
+		val = 0x00;
+	}
+
+	for (i = 0; i < 6; i++)
+		w83795_write(W83795_REG_TFMR(i), val);
+}
+
+static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
+{
+	if (mode == SPEED_CRUISE_MODE) {
+		w83795_write(W83795_REG_FCMS1, 0xFF);
+		printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n");
+	}  else {
+		w83795_write(W83795_REG_FCMS1, 0x00);
+		if (mode == THERMAL_CRUISE_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x00);
+			printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n");
+		} else if (mode == SMART_FAN_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x3F);
+			printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n");
+		} else {
+			printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void w83795_set_tss(void)
+{
+	u8 val;
+
+	val = 0x00;
+	w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */
+	w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */
+	w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */
+}
+
+static void w83795_set_fan(w83795_fan_mode_t mode)
+{
+	u8 i;
+
+	/* select temperature sensor (TSS)*/
+	w83795_set_tss();
+
+	/* select Temperature to Fan mapping Relationships (TFMR)*/
+	w83795_set_tfmr(mode);
+
+	/* set fan output controlled mode (FCMS)*/
+	w83795_set_fan_mode(mode);
+
+	/* Set Critical Temperature to Full Speed all fan (CTFS) */
+	for (i = 0; i < 6; i++) {
+		w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */
+	}
+
+	if (mode == THERMAL_CRUISE_MODE) {
+		/* Set Target Temperature of Temperature Inputs (TTTI) */
+		for (i = 0; i < 6; i++) {
+			w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */
+		}
+	} else if (mode == SMART_FAN_MODE) {
+		/* Set the Relative Register-at SMART FAN IV Control Mode Table */
+		//SFIV TODO
+	}
+
+	/* Set Hystersis of Temperature (HT) */
+}
+
+void w83795_init(w83795_fan_mode_t mode)
+{
+	u8 i;
+	u8 val;
+
+	if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
+		printk(BIOS_INFO, "W83795G/ADG Nuvoton H/W Monitor not found\n");
+		return;
+	}
+	val = w83795_read(W83795_REG_CONFIG);
+	if ((val & W83795_REG_CONFIG_CONFIG48) == 0)
+		printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n");
+	else if ((val & W83795_REG_CONFIG_CONFIG48) == 1)
+		printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n");
+
+	/* Reset */
+	val |= W83795_REG_CONFIG_INIT;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	/* enable monitoring operations */
+	val = w83795_read(W83795_REG_CONFIG);
+	val |= W83795_REG_CONFIG_START;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	w83795_set_fan(mode);
+
+	printk(BIOS_INFO, "Fan   CTFS(celsius)  TTTI(celsius)\n");
+	for (i = 0; i < 6; i++) {
+		val = w83795_read(W83795_REG_CTFS(i));
+		printk(BIOS_INFO, " %x     %d", i, val);
+		val = w83795_read(W83795_REG_TTTI(i));
+		printk(BIOS_INFO, "             %d\n", val);
+	}
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/w83795.h b/src/mainboard/supermicro/h8qgi/w83795.h
new file mode 100644
index 0000000..76623a0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/w83795.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _W83795_H_
+#define _W83795_H_
+
+#define W83795_DEV			0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */
+
+#define W83795_REG_I2C_ADDR		0xFC
+#define W83795_REG_BANKSEL		0x00
+#define W83795_REG_CONFIG		0x01
+#define W83795_REG_CONFIG_START		0x01
+#define W83795_REG_CONFIG_CONFIG48	0x04
+#define W83795_REG_CONFIG_INIT		0x80
+
+#define W83795_REG_TEMP_CTRL1		0x04 /* Temperature Monitoring Control Register */
+#define W83795_REG_TEMP_CTRL2		0x05 /* Temperature Monitoring Control Register */
+#define W83795_REG_FANIN_CTRL1		0x06
+#define W83795_REG_FANIN_CTRL2		0x07
+#define W83795_REG_TEMP_CTRL1_EN_DTS	0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */
+
+#define W83795_REG_TSS(n)		(0x209 + (n)) /* Temperature Source Selection Register */
+#define W83795_REG_TTTI(n)		(0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */
+#define W83795_REG_CTFS(n)		(0x268 + (n)) /* Critical Temperature to Full Speed all fan */
+#define W83795_REG_HT(n)		(0x270 + (n)) /* Hystersis of Temperature */
+#define W83795_REG_DTSC			0x301 /* Digital Temperature Sensor Configuration */
+
+#define W83795_REG_DTSE			0x302 /* Digital Temperature Sensor Enable */
+#define W83795_REG_DTS(n)		(0x26 + (n))
+#define W83795_REG_VRLSB		0x3C
+
+#define W83795_TEMP_REG_TR1		0x21
+#define W83795_TEMP_REG_TR2		0x22
+#define W83795_TEMP_REG_TR3		0x23
+#define W83795_TEMP_REG_TR4		0x24
+#define W83795_TEMP_REG_TR5		0x1F
+#define W83795_TEMP_REG_TR6		0x20
+
+#define W83795_REG_FCMS1		0x201
+#define W83795_REG_FCMS2		0x208
+#define W83795_REG_TFMR(n)		(0x202 + (n)) /*temperature to fam mappig*/
+#define W83795_REG_DFSP			0x20C
+
+#define W83795_REG_FTSH(n)		(0x240 + (n) * 2)
+#define W83795_REG_FTSL(n)		(0x241 + (n) * 2)
+#define W83795_REG_TFTS			0x250
+
+typedef enum w83795_fan_mode {
+	SPEED_CRUISE_MODE,	///< Fan Speed Cruise mode keeps the fan speed in a specified range
+	THERMAL_CRUISE_MODE,	///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI
+	SMART_FAN_MODE,		///< Smart Fan mode offers 6 slopes to control the fan speed
+	MANUAL_MODE,		///< control manually
+} w83795_fan_mode_t;
+
+void w83795_init(w83795_fan_mode_t mode);
+
+#endif


From gerrit at coreboot.org  Fri Jan 20 10:58:17 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 10:58:17 +0100
Subject: [coreboot] Patch set updated for coreboot: 7a89d8d Mainboard:
	Supermicro/h8qgi mainboard update
References: <Iaad8c9b08310813441188deee6797b3f6dd37d6d+0@gerrit.coreboot.org>
Message-ID: <Iaad8c9b08310813441188deee6797b3f6dd37d6d+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567

-gerrit

commit 7a89d8df8143f2f62376fbbc187ed31a9d70a4bf
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 18:50:11 2012 +0800

    Mainboard: Supermicro/h8qgi mainboard update
    
    1. Supermicro H8QGI mainboard update to support both family10 Revison D
       processor and family15 model 00-0fh processor in one binary image.
    2. RD890/SR56X0 IO hub CIMX wrapper support.
    3. SP5100/SB700 southbridge CIMX wrapper support.
    
    Both 8 cores and 16 Cores InterLagos Opteron Processor are
    tested on this platform.
    Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.
    
    Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/BiosCallOuts.c   |    2 +-
 src/mainboard/supermicro/h8qgi/BiosCallOuts.h   |    2 +-
 src/mainboard/supermicro/h8qgi/Kconfig          |   20 +-
 src/mainboard/supermicro/h8qgi/Makefile.inc     |   18 ++-
 src/mainboard/supermicro/h8qgi/OptionsIds.h     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/cpstate.asl |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/ide.asl     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/routing.asl |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/sata.asl    |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/usb.asl     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi_tables.c    |   95 +++++---
 src/mainboard/supermicro/h8qgi/agesawrapper.c   |  147 ++++++++-----
 src/mainboard/supermicro/h8qgi/agesawrapper.h   |    2 +-
 src/mainboard/supermicro/h8qgi/buildOpts.c      |  124 +++++++++--
 src/mainboard/supermicro/h8qgi/chip.h           |    2 +-
 src/mainboard/supermicro/h8qgi/cmos.layout      |    2 +-
 src/mainboard/supermicro/h8qgi/devicetree.cb    |   86 ++------
 src/mainboard/supermicro/h8qgi/dimmSpd.c        |   50 ++--
 src/mainboard/supermicro/h8qgi/dsdt.asl         |  217 +++++++-----------
 src/mainboard/supermicro/h8qgi/fadt.c           |   61 ++----
 src/mainboard/supermicro/h8qgi/get_bus_conf.c   |   30 +--
 src/mainboard/supermicro/h8qgi/irq_tables.c     |    8 +-
 src/mainboard/supermicro/h8qgi/mainboard.c      |   40 +++--
 src/mainboard/supermicro/h8qgi/mptable.c        |   59 +++---
 src/mainboard/supermicro/h8qgi/platform_cfg.h   |   54 +++++
 src/mainboard/supermicro/h8qgi/platform_oem.c   |    4 +-
 src/mainboard/supermicro/h8qgi/platform_oem.h   |   29 ---
 src/mainboard/supermicro/h8qgi/rd890_cfg.c      |  274 +++++++++++++++++++++++
 src/mainboard/supermicro/h8qgi/rd890_cfg.h      |  174 ++++++++++++++
 src/mainboard/supermicro/h8qgi/reset.c          |   66 ++++++
 src/mainboard/supermicro/h8qgi/romstage.c       |   79 +++++--
 src/mainboard/supermicro/h8qgi/sb700_cfg.c      |  142 ++++++++++++
 src/mainboard/supermicro/h8qgi/sb700_cfg.h      |  237 ++++++++++++++++++++
 33 files changed, 1504 insertions(+), 532 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
index b7f0124..e83d1f0 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
index 24a05fb..aa2d451 100644
--- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
+++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
old mode 100755
new mode 100644
index 5df0bb4..e900ea8
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -22,13 +22,15 @@ if BOARD_SUPERMICRO_H8QGI
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_AGESA_FAMILY10
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10_ROOT_COMPLEX
-	select NORTHBRIDGE_AMD_AGESA_FAMILY10
-	select SOUTHBRIDGE_AMD_SR5650
-	select SOUTHBRIDGE_AMD_SP5100
+	select CPU_AMD_AGESA_FAMILY15
+	select CPU_AMD_SOCKET_G34
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX
+	select NORTHBRIDGE_AMD_AGESA_FAMILY15
+	select NORTHBRIDGE_AMD_CIMX_RD890
+	select SOUTHBRIDGE_AMD_CIMX_SB700
 	select SUPERIO_WINBOND_W83627DHG
 	select SUPERIO_NUVOTON_WPCM450
+	select UDELAY_TSC
 	select BOARD_HAS_FADT
 	select HAVE_BUS_CONFIG
 	select HAVE_OPTION_TABLE
@@ -36,15 +38,11 @@ config BOARD_SPECIFIC_OPTIONS
 	select HAVE_MP_TABLE
 	select HAVE_HARD_RESET
 	select SERIAL_CPU_INIT
-	select AMDMCT
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_2048
+	select TINY_BOOTBLOCK
 	#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict
 
-config AMD_AGESA
-	bool
-	default y
-
 config MAINBOARD_DIR
 	string
 	default supermicro/h8qgi
diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
old mode 100755
new mode 100644
index b09c5ca..82264a4
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,15 +17,31 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
+romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 romstage-y += buildOpts.c
 romstage-y += agesawrapper.c
 romstage-y += dimmSpd.c
 romstage-y += BiosCallOuts.c
 romstage-y += platform_oem.c
 
+ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
+ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
 ramstage-y += buildOpts.c
 ramstage-y += agesawrapper.c
 ramstage-y += dimmSpd.c
 ramstage-y += BiosCallOuts.c
 ramstage-y += platform_oem.c
 
+AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa
+CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx
+AGESA_ROOT ?= $(AGESA_PREFIX)/f15
+NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890
+SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700
+
+subdirs-y += ../../../../$(AGESA_ROOT)
+#subdirs-y += ../../../../$(NB_CIMX_ROOT)
+#subdirs-y += ../../../../$(SB_CIMX_ROOT)
+
diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h
index eb756df..c4441e9 100644
--- a/src/mainboard/supermicro/h8qgi/OptionsIds.h
+++ b/src/mainboard/supermicro/h8qgi/OptionsIds.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
old mode 100755
new mode 100644
index 5eca9cc..2cb7aeb
--- a/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/cpstate.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/ide.asl b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
old mode 100755
new mode 100644
index c79c18c..45303c0
--- a/src/mainboard/supermicro/h8qgi/acpi/ide.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/ide.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/routing.asl b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
old mode 100755
new mode 100644
index 8bc06f6..817f0f7
--- a/src/mainboard/supermicro/h8qgi/acpi/routing.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/routing.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/sata.asl b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
old mode 100755
new mode 100644
index bd4acf0..9ce8650
--- a/src/mainboard/supermicro/h8qgi/acpi/sata.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/sata.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi/usb.asl b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
old mode 100755
new mode 100644
index 81ea9a2..099e7ac
--- a/src/mainboard/supermicro/h8qgi/acpi/usb.asl
+++ b/src/mainboard/supermicro/h8qgi/acpi/usb.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/acpi_tables.c b/src/mainboard/supermicro/h8qgi/acpi_tables.c
index b8ce0b0..7314283 100644
--- a/src/mainboard/supermicro/h8qgi/acpi_tables.c
+++ b/src/mainboard/supermicro/h8qgi/acpi_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <arch/ioapic.h>
 #include <arch/io.h>
 #include <device/pci.h>
@@ -48,7 +49,6 @@ static void dump_mem(u32 start, u32 end)
 #endif
 
 extern const unsigned char AmlCode[];
-extern const unsigned char AmlCode_ssdt[];
 
 
 unsigned long acpi_fill_mcfg(unsigned long current)
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 #else
 	apicid_sp5100 = CONFIG_MAX_CPUS + 1
 #endif
-	apicid_sr5650 = apicid_sp5100 + 1;
+		apicid_sr5650 = apicid_sp5100 + 1;
 
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
@@ -89,18 +89,18 @@ unsigned long acpi_fill_madt(unsigned long current)
 			0
 			);
 
-        /* IOAPIC on rs5690 */
-        gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
-        dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-        if (dev) {
-                pci_write_config32(dev, 0xF8, 0x1);
-                dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+	/* IOAPIC on rs5690 */
+	gsi_base += IO_APIC_INTERRUPTS;  /* SP5100 has 24 IOAPIC entries. */
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (dev) {
+		pci_write_config32(dev, 0xF8, 0x1);
+		dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
 		current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
 				apicid_sr5650,
 				dword,
 				gsi_base
 				);
-        }
+	}
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current,
 			0, //BUS
@@ -134,6 +134,29 @@ unsigned long acpi_fill_srat(unsigned long current)
 	return current;
 }
 
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	int lens;
+	msr_t msr;
+	char pscope[] = "\\_SB.PCI0";
+
+	lens = acpigen_write_scope(pscope);
+	msr = rdmsr(TOP_MEM);
+	lens += acpigen_write_name_dword("TOM1", msr.lo);
+	msr = rdmsr(TOP_MEM2);
+	/*
+	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
+	 * here.
+	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
+	 * slide 22ff.
+	 * Shift value right by 20 bit to make it fit into 32bit,
+	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
+	 */
+	lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
+	acpigen_patch_len(lens - 1);
+	return (unsigned long) (acpigen_get_current());
+}
+
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@@ -146,7 +169,9 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_fadt_t *fadt;
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
-	//acpi_header_t *ssdt;
+	acpi_header_t *ssdt;
+	acpi_header_t *ssdt2;
+	acpi_header_t *alib;
 
 	get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */
 
@@ -234,38 +259,38 @@ unsigned long write_acpi_tables(unsigned long start)
 	}
 
 	/* SSDT */
-	/* NOTE: we not update_ssdt, so ssdt only contain initialize value from ssdt.asl */
-#ifdef UNUSED_CODE
-	current   = ( current + 0x0f) & -0x10;
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-	if (ssdt != NULL) {
-		memcpy(current, ssdt, ssdt->length);
+	current	 = (current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA ALIB SSDT at %lx\n", current);
+	alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB);
+	if (alib != NULL) {
+		memcpy((void *)current, alib, alib->length);
 		ssdt = (acpi_header_t *) current;
-		current += ssdt->length;
+		current += alib->length;
+		acpi_add_table(rsdp,alib);
+	} else {
+		printk(BIOS_DEBUG, "	AGESA ALIB SSDT table NULL. Skipping.\n");
 	}
-	else {
+
+#if 0 // The DSDT needs additional work for the AGESA SSDT Pstate table
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * AGESA SSDT Pstate at %lx\n", current);
+	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
+	if (ssdt != NULL) {
+		memcpy((void *)current, ssdt, ssdt->length);
 		ssdt = (acpi_header_t *) current;
-		memcpy(ssdt, &AmlCode_ssdt, sizeof(acpi_header_t));
 		current += ssdt->length;
-		memcpy(ssdt, &AmlCode_ssdt, ssdt->length);
-		/* recalculate checksum */
-		ssdt->checksum = 0;
-		ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+	} else {
+		printk(BIOS_DEBUG, "  AGESA SSDT table NULL. Skipping.\n");
 	}
 	acpi_add_table(rsdp,ssdt);
-
-	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
 #endif
 
-	/* DSDT */
-	current   = ( current + 0x07) & -0x08;
-	printk(BIOS_DEBUG, "ACPI:    * DSDT at %lx\n", current);
-	dsdt = (acpi_header_t *)current; // it will used by fadt
-	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
-	current += dsdt->length;
-	memcpy(dsdt, &AmlCode, dsdt->length);
-	printk(BIOS_DEBUG, "ACPI:    * DSDT @ %p Length %x\n",dsdt,dsdt->length);
+	current	 = ( current + 0x0f) & -0x10;
+	printk(BIOS_DEBUG, "ACPI:  * coreboot TOM SSDT2 at %lx\n", current);
+	ssdt2 = (acpi_header_t *) current;
+	acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR);
+	current += ssdt2->length;
+	acpi_add_table(rsdp,ssdt2);
 
 #if DUMP_ACPI_TABLES == 1
 	printk(BIOS_DEBUG, "rsdp\n");
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 5bb4a9d..dbdd9d7 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,7 +34,6 @@
 #include "Dispatcher.h"
 #include "cpuCacheInit.h"
 #include "amdlib.h"
-#include "platform_oem.h"
 #include "Filecode.h"
 #include "heapManager.h"
 #include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */
@@ -54,7 +53,7 @@ VOID *AcpiSlit    = NULL;
 
 VOID *AcpiWheaMce = NULL;
 VOID *AcpiWheaCmc = NULL;
-//VOID *AcpiAlib    = NULL;
+VOID *AcpiAlib    = NULL;
 
 
 /*----------------------------------------------------------------------------------------
@@ -76,6 +75,7 @@ VOID *AcpiWheaCmc = NULL;
  *                          L O C A L    F U N C T I O N S
  *---------------------------------------------------------------------------------------
  */
+extern VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
 
 static UINT32 agesawrapper_amdinitcpuio(VOID)
 {
@@ -87,6 +87,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 	UINT32			node;
 	UINT32			sblink;
 	UINT32			i;
+	UINT32			TOM;
 
 	/* get the number of coherent nodes in the system */
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
@@ -130,12 +131,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		PciData = 0x00000A03;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
-		/* Set F0000000-FFFFFFFF to Node0 sbLink. */
+		/* Set TOM1-FFFFFFFF to Node0 sbLink. */
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C);
 		PciData = 0x00FFFF00;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-		PciData = 0x00F00000 | 0x03;
+		TOM = (UINT32)MsrRead(TOP_MEM);
+		PciData = (TOM >> 8) | 0x03;
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88);
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
@@ -155,13 +157,13 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 
-		/* Start to set IO 0x9000-0xEFFF to Node0 sbLink with ISA&VGA set. */
+		/* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink  and enabled VGA IO*/
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4);
-		PciData = 0x0000E000;
+		PciData = 0x00FFF000;
 		PciData |= sblink << 4;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 		PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0);
-		PciData = 0x00009033;
+		PciData = 0x00000033;
 		LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	}
 
@@ -190,9 +192,9 @@ UINT32 agesawrapper_amdinitmmio(VOID)
 	LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5;
+	MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5;
 	LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
-	MsrReg = (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800;
+	MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800;
 	LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
 
 	Status = AGESA_SUCCESS;
@@ -223,7 +225,10 @@ UINT32 agesawrapper_amdinitreset(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = NULL;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 	AmdResetParams.HtConfig.Depth = 0;
 
 	//MARG34PI disabled AGESA_ENTRY_INIT_RESET by default
@@ -257,16 +262,19 @@ UINT32 agesawrapper_amdinitearly(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 
 	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr;
 	OemCustomizeInitEarly(AmdEarlyParamsPtr);
 
-	status = AmdInitEarly((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr);
+	status = AmdInitEarly(AmdEarlyParamsPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
 
-	GetCpuServicesOfCurrentCore(&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 
@@ -280,6 +288,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	UINT16 i;
 	UINT32 *HeadPtr;
 	AMD_INTERFACE_PARAMS  AmdParamStruct;
+	AMD_POST_PARAMS *PostParams;
 	BIOS_HEAP_MANAGER    *BiosManagerPtr;
 	UINT32 TscRateInMhz;
 	CPU_SPECIFIC_SERVICES *FamilySpecificServices;
@@ -296,10 +305,15 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	AmdCreateStruct(&AmdParamStruct);
-	status = AmdInitPost((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);
-	if (status != AGESA_SUCCESS)
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
+	PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+	status = AmdInitPost(PostParams);
+	if (status != AGESA_SUCCESS) {
+		agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus);
+	}
 	AmdReleaseStruct(&AmdParamStruct);
 
 	/* Initialize heap space */
@@ -313,7 +327,7 @@ UINT32 agesawrapper_amdinitpost(VOID)
 	BiosManagerPtr->StartOfAllocatedNodes = 0;
 	BiosManagerPtr->StartOfFreedNodes = 0;
 
-	GetCpuServicesOfCurrentCore (&FamilySpecificServices, &AmdParamStruct.StdHeader);
+	GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader);
 	FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader);
 	printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz);
 
@@ -324,6 +338,7 @@ UINT32 agesawrapper_amdinitenv(VOID)
 {
 	AGESA_STATUS status;
 	AMD_INTERFACE_PARAMS AmdParamStruct;
+	AMD_ENV_PARAMS *EnvParams;
 
 	LibAmdMemFill(&AmdParamStruct,
 			0,
@@ -336,10 +351,15 @@ UINT32 agesawrapper_amdinitenv(VOID)
 	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
-	status = AmdInitEnv((AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr);
+
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
+	EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr;
+	status = AmdInitEnv(EnvParams);
 	if (status != AGESA_SUCCESS)
-		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus);
 
 	AmdReleaseStruct(&AmdParamStruct);
 	return (UINT32)status;
@@ -363,10 +383,8 @@ VOID * agesawrapper_getlateinitptr(int pick)
 			return AcpiWheaMce;
 		case PICK_WHEA_CMC:
 			return AcpiWheaCmc;
-/*
 		case PICK_ALIB:
 			return AcpiAlib;
-*/
 		default:
 			return NULL;
 	}
@@ -394,7 +412,10 @@ UINT32 agesawrapper_amdinitmid(VOID)
 	AmdParamStruct.StdHeader.Func = 0;
 	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	AmdCreateStruct(&AmdParamStruct);
+	status = AmdCreateStruct(&AmdParamStruct);
+	if (status != AGESA_SUCCESS) {
+		return (UINT32)status;
+	}
 	status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr);
 	if (status != AGESA_SUCCESS)
 		agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);
@@ -405,34 +426,49 @@ UINT32 agesawrapper_amdinitmid(VOID)
 
 UINT32 agesawrapper_amdinitlate(VOID)
 {
-	AGESA_STATUS Status;
-	AMD_LATE_PARAMS AmdLateParams;
+	AGESA_STATUS		Status;
+	AMD_INTERFACE_PARAMS	AmdParamStruct;
+	AMD_LATE_PARAMS		*AmdLateParamsPtr;
 
-	LibAmdMemFill(&AmdLateParams,
-			0,
-			sizeof(AMD_LATE_PARAMS),
-			&(AmdLateParams.StdHeader));
+	LibAmdMemFill(&AmdParamStruct,
+		       0,
+		       sizeof (AMD_INTERFACE_PARAMS),
+		       &(AmdParamStruct.StdHeader));
 
-	AmdLateParams.StdHeader.AltImageBasePtr = 0;
-	AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
-	AmdLateParams.StdHeader.Func = 0;
-	AmdLateParams.StdHeader.ImageBasePtr = 0;
-	AmdLateParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
+	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
+	AmdParamStruct.AllocationMethod = PostMemDram;
+	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
+	AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout;
+	AmdParamStruct.StdHeader.Func = 0;
+	AmdParamStruct.StdHeader.ImageBasePtr = 0;
 
-	Status = AmdInitLate(&AmdLateParams);
+	AmdCreateStruct (&AmdParamStruct);
+	AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
+
+	printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr);
+
+	Status = AmdInitLate(AmdLateParamsPtr);
 	if (Status != AGESA_SUCCESS) {
-		agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus);
+		agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus);
 		ASSERT(Status == AGESA_SUCCESS);
 	}
-
-	DmiTable       = AmdLateParams.DmiTable;
-	AcpiPstate     = AmdLateParams.AcpiPState;
-	AcpiSrat       = AmdLateParams.AcpiSrat;
-	AcpiSlit       = AmdLateParams.AcpiSlit;
-
-	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-	//AcpiAlib       = AmdLateParams.AcpiAlib;
+	DmiTable    = AmdLateParamsPtr->DmiTable;
+	AcpiPstate  = AmdLateParamsPtr->AcpiPState;
+	AcpiSrat    = AmdLateParamsPtr->AcpiSrat;
+	AcpiSlit    = AmdLateParamsPtr->AcpiSlit;
+	AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce;
+	AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc;
+	AcpiAlib    = AmdLateParamsPtr->AcpiAlib;
+
+	printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n"
+		"   DmiTable:%p\n   AcpiPstate: %p\n   AcpiSrat:%p\n   AcpiSlit:%p\n"
+		"   Mce:%p\n   Cmc:%p\n   Alib:%p\n",
+		 __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit,
+		 AcpiWheaMce, AcpiWheaCmc, AcpiAlib);
+
+	/* Don't release the structure until coreboot has copied the ACPI tables.
+	 * AmdReleaseStruct (&AmdLateParams);
+	 */
 
 	return (UINT32)Status;
 }
@@ -464,15 +500,6 @@ UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr)
 		ASSERT(Status <= AGESA_UNSUPPORTED);
 	}
 
-	DmiTable       = AmdLateParams.DmiTable;
-	AcpiPstate     = AmdLateParams.AcpiPState;
-	AcpiSrat       = AmdLateParams.AcpiSrat;
-	AcpiSlit       = AmdLateParams.AcpiSlit;
-
-	AcpiWheaMce    = AmdLateParams.AcpiWheaMce;
-	AcpiWheaCmc    = AmdLateParams.AcpiWheaCmc;
-	//  AcpiAlib       = AmdLateParams.AcpiAlib;
-
 	return (UINT32)Status;
 }
 
@@ -784,9 +811,9 @@ static void agesa_error(EVENT_PARAMS *event)
 			printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n");
 			break;
 
-		case MEM_ERROR_ECC_DIS:
-			printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
-			break;
+//		case MEM_ERROR_ECC_DIS:
+//			printk(BIOS_DEBUG, "ECC has been disabled as a result of an internal issue\n");
+//			break;
 
 		case MEM_ERROR_DIMM_SPARING_NOT_ENABLED:
 			printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n");
@@ -1141,6 +1168,7 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event)
  */
 UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 {
+	printk(BIOS_DEBUG, "enter in %s\n", __func__);
 	AGESA_STATUS Status;
 	EVENT_PARAMS AmdEventParams;
 
@@ -1164,6 +1192,7 @@ UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 		Status = AmdReadEventLog(&AmdEventParams);
 	}
 
+	printk(BIOS_DEBUG, "exit %s \n", __func__);
 	return (UINT32)Status;
 }
 
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.h b/src/mainboard/supermicro/h8qgi/agesawrapper.h
index 43c7d10..c1eb012 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.h
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 02cf79b..480c7b6 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,7 +70,10 @@
 ////#define BLDOPT_REMOVE_SLIT                     TRUE
 //#define BLDOPT_REMOVE_WHEA                     TRUE
 //#define BLDOPT_REMOVE_DMI                      TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES            FALSE
+
+/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
+#define BLDOPT_REMOVE_EARLY_SAMPLES		FALSE
+
 //#define BLDOPT_REMOVE_HT_ASSIST                TRUE
 //#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
@@ -107,7 +110,7 @@
 #define BLDCFG_ONLINE_SPARE                       FALSE
 #define BLDCFG_BANK_SWIZZLE                       TRUE
 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
-#define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
+#define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY //DDR800_FREQUENCY
 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 #define BLDCFG_USE_BURST_MODE                     FALSE
@@ -297,6 +300,27 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8qgi_deemphasis_list[] =
 	{0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 	{0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 
+	{1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+	{2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
+	{3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
+	{3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
+	{3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
+	{3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
+	{3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
+	{3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
+
 	/* Coherent link deemphasis. */
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 	{HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
@@ -373,22 +397,21 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8qgi_socket_map[] =
 	{HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
 	{HT_SOCKET3, HT_LINK3B, HT_SOCKET2},
-
 };
 
 CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 {
-	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull},
-	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull},
-	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000ull},
-	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818ull},
-	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818ull},
+	{AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
+	{AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
+	{AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
+	{AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
+	{AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
 	{CPU_LIST_TERMINAL}
 };
 
@@ -403,7 +426,7 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 /*  Process the options...
  * This file include MUST occur AFTER the user option selection settings
  */
-#define AGESA_ENTRY_INIT_RESET                    FALSE//TRUE
+#define AGESA_ENTRY_INIT_RESET                    TRUE//FALSE
 #define AGESA_ENTRY_INIT_RECOVERY                 FALSE
 #define AGESA_ENTRY_INIT_EARLY                    TRUE
 #define AGESA_ENTRY_INIT_POST                     TRUE
@@ -415,7 +438,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
 #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
 #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
 
-#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
+/*
+#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1)
+  #define BLDOPT_REMOVE_FAMILY_10_SUPPORT         TRUE
+#endif
+#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1)
+  #define BLDOPT_REMOVE_FAMILY_15_SUPPORT         TRUE
+#endif
+*/
+
+//#include "GnbInterface.h"     /*prototype for GnbInterfaceStub*/
 #include "MaranelloInstall.h"
 
 /*----------------------------------------------------------------------------------------
@@ -423,6 +455,16 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
  *----------------------------------------------------------------------------------------
  */
 
+//reference BKDG Table87: works
+#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
+#define SEED_A 0x54
+#define SEED_B 0x4D
+#define SEED_C 0x45
+#define SEED_D 0x40
+
+#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
+//4B 41 51
+
 /*
  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
@@ -486,6 +528,53 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 	//      Byte6Seed, Byte7Seed, ByteEccSeed)
 	//      Specifies the write leveling seed for a channel of a socket.
 	//
+#if 0//CONFIG_CPU_AMD_AGESA_FAMILY10
+	/* Specifies the write leveling seed for a channel of a socket.
+	 * WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed,
+	 *                     Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
+	 *                     Byte6Seed, Byte7Seed, ByteEccSeed)
+	 */
+	WRITE_LEVELING_SEED(
+			ANY_SOCKET, ANY_CHANNEL, F10_WL_SEED, F10_WL_SEED,
+			F10_WL_SEED, F10_WL_SEED, F10_WL_SEED, F10_WL_SEED,
+			F10_WL_SEED, F10_WL_SEED, F10_WL_SEED),
+#endif
+
+#if 0 //CONFIG_CPU_AMD_AGESA_FAMILY15
+	/* Specifies the write leveling seed for a channel of a socket.
+	 * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
+	 *                     Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
+	 *                     Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
+	 *                     ByteEccSeed)
+	 */
+	WRITE_LEVELING_SEED(
+			ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
+			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+			F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
+			F15_WL_SEED),
+
+	/* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
+	 *              Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
+	 *              Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
+	 */
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
+		SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
+		SEED_A),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
+		SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
+		SEED_B),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
+		SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
+		SEED_C),
+	HW_RXEN_SEED(
+		ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
+		SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
+		SEED_D),
+#endif
+
 	NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3
 	PSO_END
 };
@@ -493,7 +582,6 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 /*
  * These tables are optional and may be used to adjust memory timing settings
  */
-
 //HY Customer table
 UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] =
 {
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
index a252705..1181130 100644
--- a/src/mainboard/supermicro/h8qgi/chip.h
+++ b/src/mainboard/supermicro/h8qgi/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/cmos.layout b/src/mainboard/supermicro/h8qgi/cmos.layout
old mode 100755
new mode 100644
index 3b98cbb..0fd4708
--- a/src/mainboard/supermicro/h8qgi/cmos.layout
+++ b/src/mainboard/supermicro/h8qgi/cmos.layout
@@ -2,7 +2,7 @@
 #
 #  This file is part of the coreboot project.
 #
-#  Copyright (C) 2011 Advanced Micro Devices, Inc.
+#  Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 #  This program is free software; you can redistribute it and/or modify
 #  it under the terms of the GNU General Public License as published by
diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb
old mode 100755
new mode 100644
index 9afaac7..9d77a73
--- a/src/mainboard/supermicro/h8qgi/devicetree.cb
+++ b/src/mainboard/supermicro/h8qgi/devicetree.cb
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -16,20 +16,18 @@
 # along with this program; if not, write to the Free Software
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
-chip northbridge/amd/agesa/family10/root_complex
+chip northbridge/amd/agesa/family15/root_complex
 	device lapic_cluster 0 on
-		chip cpu/amd/agesa/family10
-			device lapic 0x10 on end
+		chip cpu/amd/agesa/family15
+			device lapic 0x20 on end #f15
+			#device lapic 0x10 on end #f10
 		end
 	end
 	device pci_domain 0 on
 		subsystemid 0x15d9 0xab11 inherit #SuperMicro
-		chip northbridge/amd/agesa/family10 # CPU side of HT root complex
-			device pci 18.0 on end # link 0
-			device pci 18.0 on end # link 1
-			device pci 18.0 on end # link 2
-			device pci 18.0 on # link3 SB on socket0 link 2, on internal Node0 Link 3
-				chip southbridge/amd/sr5650 # Southbridge PCI side of HT Root complex
+		chip northbridge/amd/agesa/family15 # CPU side of HT root complex
+			device pci 18.0 on     # Put IO-HUB at link_num 0, Instead of HT Link topology
+				chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex
 					device pci 0.0 on  end # HT Root Complex 0x9600
 					device pci 0.1 off end # CLKCONFIG
 					device pci 2.0 on  end # GPP1 Port0  x16 SLOT4, 0x5A16
@@ -46,11 +44,10 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci d.0 on  end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
 					register "gpp1_configuration" = "0"   # Configuration 16:0 default
 					register "gpp2_configuration" = "1"   # Configuration 8:8
-					register "gpp3a_configuration" = "2"   # Configuration 4:1:1:0:0:0
-					#register "gpp3a_configuration" = "11"   # Configuration 1:1:1:1:1:1
+					register "gpp3a_configuration" = "2"   # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
 					register "port_enable" = "0x2104"
-				end #southbridge/amd/sr5650
-				chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pci bus
+				end #northbridge/amd/cimx/rd890
+				chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus
 					device pci 11.0 on end # SATA
 					device pci 12.0 on end # USB1
 					device pci 12.1 on end # USB1
@@ -59,8 +56,8 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 13.1 on end # USB2
 					device pci 13.2 on end # USB2
 					device pci 14.0 on end # SM
-					device pci 14.1 on end # IDE  0x439c
-					device pci 14.2 off end # HDA  0x4383, h8qgi doesnt have codec.
+					device pci 14.1 off end # IDE  0x439c
+					device pci 14.2 off end # HDA  0x4383, h8qgi not have codec.
 					device pci 14.3 on # LPC  0x439d
 						chip superio/winbond/w83627dhg
 							device pnp 2e.0 off #  Floppy
@@ -113,64 +110,15 @@ chip northbridge/amd/agesa/family10/root_complex
 					device pci 14.4 on end # PCI 0x4384
 					device pci 14.5 on end # USB 3
 					register "boot_switch_sata_ide" = "0"   # 0: boot from SATA. 1: IDE
-				end # southbridge/amd/sp5100
+				end # southbridge/amd/cimx/sb700
 			end # device pci 18.0
 
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 			device pci 18.4 on end
-
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-			device pci 19.4 on end
-
-
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on end
-			device pci 1a.0 on # another 56x0 on socket 1 Link 2, internal Node0 link 3
-			end
-			device pci 1a.1 on end
-			device pci 1a.2 on end
-			device pci 1a.3 on end
-			device pci 1a.4 on end
-
-			device pci 1b.0 on end
-			device pci 1b.1 on end
-			device pci 1b.2 on end
-			device pci 1b.3 on end
-			device pci 1b.4 on end
-
-
-			device pci 1c.0 on end
-			device pci 1c.1 on end
-			device pci 1c.2 on end
-			device pci 1c.3 on end
-			device pci 1c.4 on end
-
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 on end
-			device pci 1d.4 on end
-
-
-			device pci 1e.0 on end
-			device pci 1e.1 on end
-			device pci 1e.2 on end
-			device pci 1e.3 on end
-			device pci 1e.4 on end
-
-			device pci 1f.0 on end
-			device pci 1f.1 on end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.4 on end
-
-		end #chip northbridge/amd/agesa/family10 # CPU side of HT root complex
+			device pci 18.5 on end #f15
+		end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
 	end #pci_domain
-end #northbridge/amd/agesa/family10/root_complex
+end #northbridge/amd/agesa/family15/root_complex
 
diff --git a/src/mainboard/supermicro/h8qgi/dimmSpd.c b/src/mainboard/supermicro/h8qgi/dimmSpd.c
index 4ff21ee..a838cb4 100644
--- a/src/mainboard/supermicro/h8qgi/dimmSpd.c
+++ b/src/mainboard/supermicro/h8qgi/dimmSpd.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -38,14 +38,14 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
  */
 static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 {
-        u8 value;
-        device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
-
-        value = pci_read_config8(sm_dev, reg);
-        value &= ~(enable);
-        value |= out;
-        value &= ~(enable << 4);
-        pci_write_config8(sm_dev, reg, value);
+	u8 value;
+	device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+
+	value = pci_read_config8(sm_dev, reg);
+	value &= ~(enable);
+	value |= out;
+	value &= ~(enable << 4);
+	pci_write_config8(sm_dev, reg, value);
 }
 
 /*-----------------------------------------------------------------------------
@@ -55,31 +55,31 @@ static void sp5100_set_gpio(u8 reg, u8 out, u8 enable)
 static const UINT8 spdAddressLookup [8] [4] [2] = { // socket, channel, dimm
 	/* socket 0 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 1 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 2 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 	/* socket 3 */
 	{
-		{0xAE, 0xAC},
-		{0xAA, 0xA8},
-		{0xA6, 0xA4},
-		{0xA2, 0xA0},
+		{0xAC, 0xAE},
+		{0xA8, 0xAA},
+		{0xA4, 0xA6},
+		{0xA0, 0xA2},
 	},
 };
 
diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl
old mode 100755
new mode 100644
index ebdb1eb..3f10012
--- a/src/mainboard/supermicro/h8qgi/dsdt.asl
+++ b/src/mainboard/supermicro/h8qgi/dsdt.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,7 +27,7 @@ DefinitionBlock (
 	0x00010001	/* OEM Revision */
 	)
 {	/* Start of ASL file */
-	/* #include "../../../arch/x86/acpi/debug.asl" */		/* Include global debug methods if needed */
+	/* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */
 
 	/* Data to be patched by the BIOS during POST */
 	/* FIXME the patching is not done yet! */
@@ -988,73 +988,58 @@ DefinitionBlock (
 
 	Scope(\_GPE) {	/* Start Scope GPE */
 		/*  General event 0  */
-		/* Method(_L00) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L00) {
+		      //DBGO("\\_GPE\\_L00\n")
+		}
 
 		/*  General event 1  */
-		/* Method(_L01) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L01) {
+		      //DBGO("\\_GPE\\_L01\n")
+		}
 
 		/*  General event 2  */
-		/* Method(_L02) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L02) {
+		      //DBGO("\\_GPE\\_L02\n")
+		}
 
 		/*  General event 3  */
 		Method(_L03) {
-			/* DBGO("\\_GPE\\_L00\n") */
+			//DBGO("\\_GPE\\_L00\n")
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
 		/*  General event 4  */
-		/* Method(_L04) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L04) {
+		      //DBGO("\\_GPE\\_L04\n")
+		}
 
 		/*  General event 5  */
-		/* Method(_L05) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
-
-		/*  General event 6 - Used for GPM6, moved to USB.asl */
-		/* Method(_L06) {
-		*	DBGO("\\_GPE\\_L00\n")
-		* }
-		*/
+		Method(_L05) {
+		      //DBGO("\\_GPE\\_L05\n")
+		}
 
-		/*  General event 7 - Used for GPM7, moved to USB.asl */
-		/* Method(_L07) {
-		*	DBGO("\\_GPE\\_L07\n")
-		* }
-		*/
+		/* _L06 General event 6 - Used for GPM6, moved to USB.asl */
+		/* _L07 General event 7 - Used for GPM7, moved to USB.asl */
 
 		/*  Legacy PM event  */
 		Method(_L08) {
-			/* DBGO("\\_GPE\\_L08\n") */
+			//DBGO("\\_GPE\\_L08\n")
 		}
 
 		/*  Temp warning (TWarn) event  */
 		Method(_L09) {
-			/* DBGO("\\_GPE\\_L09\n") */
+			//DBGO("\\_GPE\\_L09\n")
 			Notify (\_TZ.TZ00, 0x80)
 		}
 
 		/*  Reserved  */
-		/* Method(_L0A) {
-		*	DBGO("\\_GPE\\_L0A\n")
-		* }
-		*/
+		Method(_L0A) {
+		      //DBGO("\\_GPE\\_L0A\n")
+		}
 
 		/*  USB controller PME#  */
 		Method(_L0B) {
-			/* DBGO("\\_GPE\\_L0B\n") */
+			//DBGO("\\_GPE\\_L0B\n")
 			Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
@@ -1065,126 +1050,81 @@ DefinitionBlock (
 		}
 
 		/*  AC97 controller PME#  */
-		/* Method(_L0C) {
-		*	DBGO("\\_GPE\\_L0C\n")
-		* }
-		*/
+		Method(_L0C) {
+		      //DBGO("\\_GPE\\_L0C\n")
+		}
 
 		/*  OtherTherm PME#  */
-		/* Method(_L0D) {
-		*	DBGO("\\_GPE\\_L0D\n")
-		* }
-		*/
+		Method(_L0D) {
+		      //DBGO("\\_GPE\\_L0D\n")
+		}
 
-		/*  GPM9 SCI event - Moved to USB.asl */
-		/* Method(_L0E) {
-		*	DBGO("\\_GPE\\_L0E\n")
-		* }
-		*/
+		/* _L0E GPM9 SCI event - Moved to USB.asl */
 
 		/*  PCIe HotPlug event  */
-		/* Method(_L0F) {
-		* 	DBGO("\\_GPE\\_L0F\n")
-		* }
-		*/
+		Method(_L0F) {
+			//DBGO("\\_GPE\\_L0F\n")
+		}
 
 		/*  ExtEvent0 SCI event  */
 		Method(_L10) {
-			/* DBGO("\\_GPE\\_L10\n") */
+			//DBGO("\\_GPE\\_L10\n")
 		}
 
 
 		/*  ExtEvent1 SCI event  */
 		Method(_L11) {
-			/* DBGO("\\_GPE\\_L11\n") */
+			//DBGO("\\_GPE\\_L11\n")
 		}
 
 		/*  PCIe PME# event  */
-		/* Method(_L12) {
-		*	DBGO("\\_GPE\\_L12\n")
-		* }
-		*/
-
-		/*  GPM0 SCI event - Moved to USB.asl */
-		/* Method(_L13) {
-		* 	DBGO("\\_GPE\\_L13\n")
-		* }
-		*/
-
-		/*  GPM1 SCI event - Moved to USB.asl */
-		/* Method(_L14) {
-		* 	DBGO("\\_GPE\\_L14\n")
-		* }
-		*/
-
-		/*  GPM2 SCI event - Moved to USB.asl */
-		/* Method(_L15) {
-		* 	DBGO("\\_GPE\\_L15\n")
-		* }
-		*/
-
-		/*  GPM3 SCI event - Moved to USB.asl */
-		/* Method(_L16) {
-		*	DBGO("\\_GPE\\_L16\n")
-		* }
-		*/
+		Method(_L12) {
+		      //DBGO("\\_GPE\\_L12\n")
+		}
 
-		/*  GPM8 SCI event - Moved to USB.asl */
-		/* Method(_L17) {
-		* 	DBGO("\\_GPE\\_L17\n")
-		* }
-		*/
+		/* _L13 GPM0 SCI event - Moved to USB.asl */
+		/* _L14 GPM1 SCI event - Moved to USB.asl */
+		/* _L15 GPM2 SCI event - Moved to USB.asl */
+		/* _L16 GPM3 SCI event - Moved to USB.asl */
+		/* _L17 GPM8 SCI event - Moved to USB.asl */
 
 		/*  GPIO0 or GEvent8 event  */
 		Method(_L18) {
-			/* DBGO("\\_GPE\\_L18\n") */
+			//DBGO("\\_GPE\\_L18\n")
 			Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */
+			Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
-		/*  GPM4 SCI event - Moved to USB.asl */
-		/* Method(_L19) {
-		* 	DBGO("\\_GPE\\_L19\n")
-		* }
-		*/
-
-		/*  GPM5 SCI event - Moved to USB.asl */
-		/* Method(_L1A) {
-		*	DBGO("\\_GPE\\_L1A\n")
-		* }
-		*/
+		/* _L19 GPM4 SCI event - Moved to USB.asl */
+		/* _L1A GPM5 SCI event - Moved to USB.asl */
 
 		/*  Azalia SCI event  */
 		Method(_L1B) {
-			/* DBGO("\\_GPE\\_L1B\n") */
+			//DBGO("\\_GPE\\_L1B\n")
 			Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 			Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 		}
 
 		/*  GPM6 SCI event - Reassigned to _L06 */
-		/* Method(_L1C) {
-		*	DBGO("\\_GPE\\_L1C\n")
-		* }
-		*/
+		Method(_L1C) {
+		      //DBGO("\\_GPE\\_L1C\n")
+		}
 
 		/*  GPM7 SCI event - Reassigned to _L07 */
-		/* Method(_L1D) {
-		*	DBGO("\\_GPE\\_L1D\n")
-		* }
-		*/
+		Method(_L1D) {
+		      //DBGO("\\_GPE\\_L1D\n")
+		}
 
 		/*  GPIO2 or GPIO66 SCI event  */
-		/* Method(_L1E) {
-		* 	DBGO("\\_GPE\\_L1E\n")
-		* }
-		*/
+		Method(_L1E) {
+			//DBGO("\\_GPE\\_L1E\n")
+		}
 
-		/*  SATA SCI event - Moved to sata.asl */
-		/* Method(_L1F) {
-		*	 DBGO("\\_GPE\\_L1F\n")
-		* }
-		*/
+		/* _L1F SATA SCI event - Moved to sata.asl */
 
 	} 	/* End Scope GPE */
 
@@ -1569,7 +1509,7 @@ DefinitionBlock (
 					0x0CF8,             // Range Maximum
 					0x01,               // Alignment
 					0x08,               // Length
-				   	)
+					)
 
 				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 					0x0000,             // Granularity
@@ -1602,10 +1542,10 @@ DefinitionBlock (
 					,, , TypeStatic)
 				WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 					0x0000,             // Granularity
-					0x9000,             // Range Minimum
-					0xefff,             // Range Maximum
+					0x0D00,             // Range Minimum
+					0xFFFF,             // Range Maximum
 					0x0000,             // Translation Offset
-					0x6000,             // Length
+					0xF300,             // Length
 					,, , TypeStatic)
 				Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) 	// VGA memory space
 
@@ -1613,21 +1553,26 @@ DefinitionBlock (
 						0xE0000000,         // Address Base
 						0x10000000,         // Address Length, (1MB each Bus, 256 Buses by default)
 						MMIO)
-				DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
-						0x00000000,         // Granularity
-						0xF0000000,         // Range Minimum
-						0xFFFFFFFF,         // Range Maximum
-						0x00000000,         // Translation Offset
-						0x10000000,         // Length
-						,, , AddressRangeMemory, TypeStatic)
 			})
 
 			Method (_CRS, 0, NotSerialized)
 			{
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1)
 				CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1)
-				Store (PCBA, BAS1)
-				Store (PCLN, LEN1)
+
+                                /*
+                                 * Declare memory between TOM1 and 4GB as available
+                                 * for PCI MMIO.
+                                 * Use ShiftLeft to avoid 64bit constant (for XP).
+                                 * This will work even if the OS does 32bit arithmetic, as
+                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
+                                 * result as 64bit (0x100000000 - TOM1).
+                                 */
+				Store(TOM1, BAS1)
+                                ShiftLeft(0x10000000, 4, Local0)
+                                Subtract(Local0, TOM1, Local0)
+                                Store(Local0, LEN1)
+				//DBGO(TOM1)
 
 				Return (CRS)
 			}
diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c
index c2f714d..0c63162 100644
--- a/src/mainboard/supermicro/h8qgi/fadt.c
+++ b/src/mainboard/supermicro/h8qgi/fadt.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,21 +28,17 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/device.h>
-#include "southbridge/amd/sb700/sb700.h"
+#include "Platform.h" /*sb700 platform header*/
 
-u16 pm_base = SB700_ACPI_IO_BASE;
-/* pm_base should be set in sb acpi */
-/* pm_base should be got from bar2 of sb700. Here I compact ACPI
- * registers into 32 bytes limit.
- * */
+#ifndef ACPI_BLK_BASE
+  #define ACPI_BLK_BASE	PM1_EVT_BLK_ADDRESS
+#endif
 
 void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
 
-	pm_base &= 0xFFFF;
-	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
-
+	printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE);
 	/* Prepare the header */
 	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
@@ -65,38 +61,15 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->s4bios_req = 0x0;
 	fadt->pstate_cnt = 0xe2;
 
-	pm_iowrite(0x60, ACPI_PM_EVT_BLK & 0xFF);
-	pm_iowrite(0x61, ACPI_PM_EVT_BLK >> 8);
-	pm_iowrite(0x62, ACPI_PM1_CNT_BLK & 0xFF);
-	pm_iowrite(0x63, ACPI_PM1_CNT_BLK >> 8);
-	pm_iowrite(0x64, ACPI_PM_TMR_BLK & 0xFF);
-	pm_iowrite(0x65, ACPI_PM_TMR_BLK >> 8);
-	pm_iowrite(0x68, ACPI_GPE0_BLK & 0xFF);
-	pm_iowrite(0x69, ACPI_GPE0_BLK >> 8);
-
-	/* CpuControl is in \_PR.CPU0, 6 bytes */
-	pm_iowrite(0x66, ACPI_CPU_CONTROL & 0xFF);
-	pm_iowrite(0x67, ACPI_CPU_CONTROL >> 8);
-
-	pm_iowrite(0x6A, 0);	/* AcpiSmiCmdLo */
-	pm_iowrite(0x6B, 0);	/* AcpiSmiCmdHi */
-
-	pm_iowrite(0x6C, ACPI_PMA_CNT_BLK & 0xFF);
-	pm_iowrite(0x6D, ACPI_PMA_CNT_BLK >> 8);
-
-	pm_iowrite(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); /* AcpiDecodeEnable, When set, SB uses
-						      * the contents of the PM registers at
-						      * index 60-6B to decode ACPI I/O address.
-						      * AcpiSmiEn & SmiCmdEn*/
 	/* RTC_En_En, TMR_En_En, GBL_EN_EN */
-	outl(0x1, ACPI_PM1_CNT_BLK);		  /* set SCI_EN */
-	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;
+	outl(0x1, PM1_CNT_BLK_ADDRESS);           /* set SCI_EN */
+	fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS;
 	fadt->pm1b_evt_blk = 0x0000;
-	fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK;
+	fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS;
 	fadt->pm1b_cnt_blk = 0x0000;
-	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK;
-	fadt->pm_tmr_blk = ACPI_PM_TMR_BLK;
-	fadt->gpe0_blk = ACPI_GPE0_BLK;
+	fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS;
+	fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS;
+	fadt->gpe0_blk = GPE0_BLK_ADDRESS;
 	fadt->gpe1_blk = 0x0000;	/* we dont have gpe1 block, do we? */
 
 	fadt->pm1_evt_len = 4;
@@ -139,7 +112,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_evt_blk.bit_width = 32;
 	fadt->x_pm1a_evt_blk.bit_offset = 0;
 	fadt->x_pm1a_evt_blk.resv = 0;
-	fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK;
+	fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS;
 	fadt->x_pm1a_evt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_evt_blk.space_id = 1;
@@ -154,7 +127,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm1a_cnt_blk.bit_width = 16;
 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
 	fadt->x_pm1a_cnt_blk.resv = 0;
-	fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK;
+	fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS;
 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
 
 	fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -169,7 +142,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm2_cnt_blk.bit_width = 0;
 	fadt->x_pm2_cnt_blk.bit_offset = 0;
 	fadt->x_pm2_cnt_blk.resv = 0;
-	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK;
+	fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS;
 	fadt->x_pm2_cnt_blk.addrh = 0x0;
 
 
@@ -177,7 +150,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_pm_tmr_blk.bit_width = 32;
 	fadt->x_pm_tmr_blk.bit_offset = 0;
 	fadt->x_pm_tmr_blk.resv = 0;
-	fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK;
+	fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS;
 	fadt->x_pm_tmr_blk.addrh = 0x0;
 
 
@@ -185,7 +158,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_gpe0_blk.bit_width = 32;
 	fadt->x_gpe0_blk.bit_offset = 0;
 	fadt->x_gpe0_blk.resv = 0;
-	fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK;
+	fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS;
 	fadt->x_gpe0_blk.addrh = 0x0;
 
 
diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
index 14e6bca..8c31cbf 100644
--- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -23,8 +23,10 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/amd/amdfam10_sysconf.h>
 #include "agesawrapper.h"
+#if CONFIG_AMD_SB_CIMX
+#include <sb_cimx.h>
+#endif
 
 
 /* Global variables for MB layouts and these will be shared by irqtable mptable
@@ -34,22 +36,6 @@ u8 bus_isa;
 u8 bus_sp5100[2];
 u8 bus_sr5650[14];
 
-/*
- * Here you only need to set value in pci1234 for HT-IO that could be installed or not
- * You may need to preset pci1234 for HTIO board,
- * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- */
-u32 pci1234x[] = {
-	0x0000ff0,
-};
-
-/*
- * HT Chain device num, actually it is unit id base of every ht device in chain,
- * assume every chain only have 4 ht device at most
- */
-u32 hcdnx[] = {
-	0x20202020,
-};
 
 u32 bus_type[256];
 
@@ -106,8 +92,7 @@ void get_bus_conf(void)
 
 	bus_type[0] = 1;  /* pci */
 
-	bus_sr5650[0] = (pci1234x[0] >> 16) & 0xff;
-	//  bus_sp5100[0] = (sysconf.pci1234[0] >> 16) & 0xff;
+	bus_sr5650[0] = 0;
 	bus_sp5100[0] = bus_sr5650[0];
 
 	/* sp5100 */
@@ -151,4 +136,9 @@ void get_bus_conf(void)
 
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
+
+#if CONFIG_AMD_SB_CIMX
+	sb_After_Pci_Init();
+	sb_Late_Post();
+#endif
 }
diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c
index 640a0a6..11e5256 100644
--- a/src/mainboard/supermicro/h8qgi/irq_tables.c
+++ b/src/mainboard/supermicro/h8qgi/irq_tables.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -27,9 +27,9 @@
 
 
 static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
+		u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+		u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+		u8 slot, u8 rfu)
 {
 	pirq_info->bus = bus;
 	pirq_info->devfn = devfn;
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index f00b5a0..675c87f 100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,36 +25,48 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include "southbridge/amd/sr5650/cmn.h"
+#include <NbPlatform.h>
 #include "chip.h"
 
-void set_pcie_dereset(void);
-void set_pcie_reset(void);
+void set_pcie_dereset(void *nbconfig);
+void set_pcie_reset(void *nbconfig);
 
 /**
  *
  */
-void set_pcie_reset(void)
+void set_pcie_reset(void *nbconfig)
 {
 }
 
 /**
+ * Mainboard specific RD890 CIMx callback
  * Release Resets to PCIe Links
- * PCIE_RESET_GPIO1,2,4,5
+ * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie
  */
-void set_pcie_dereset(void)
+void set_pcie_dereset(void *nbconfig)
 {
-	device_t pcie_core_dev;
+	//u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+	u32 i;
+	u32 val;
+	u32 nb_addr;
 
-	pcie_core_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-	set_htiu_enable_bits(pcie_core_dev, 0xA8, 0x07000707, 0x07000707);
-	set_htiu_enable_bits(pcie_core_dev, 0xA9, 0x00000007, 0x00000007);
+	val = 0x00000007UL;
+	AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig;
+	for (i = 0; i < MAX_NB_COUNT; i ++) {
+		nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX;
+		LibNbPciIndexRMW(nb_addr,
+				NB_HTIU_REGA8,
+				AccessS3SaveWidth32,
+				~val,
+				val,
+				 &(pConfig->Northbridges[i]));
+	}
 }
 
 
 /*************************************************
-* enable the dedicated function in h8qgi board.
-*************************************************/
+ * enable the dedicated function in h8qgi board.
+ *************************************************/
 static void h8qgi_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
@@ -69,5 +81,5 @@ int add_mainboard_resources(struct lb_memory *mem)
 
 struct chip_operations mainboard_ops = {
 	CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard")
-	.enable_dev = h8qgi_enable,
+		.enable_dev = h8qgi_enable,
 };
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 5c01994..92771bd 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,17 +33,16 @@ extern u8 bus_sp5100[2];
 extern u32 bus_type[256];
 extern u32 sbdn_sr5650;
 extern u32 sbdn_sp5100;
+extern u8 bus_isa;
 
 
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	int bus_isa;
 	u32 apicid_sp5100;
 	u32 apicid_sr5650;
 	device_t dev;
 	u32 dword;
-	u8 byte;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 	mptable_init(mc, LAPIC_ADDR);
@@ -62,17 +61,18 @@ static void *smp_write_config_table(void *v)
 #if CONFIG_MAX_CPUS >= 16
 	apicid_sp5100 = 0x0;
 #else
-	apicid_sp5100 = CONFIG_MAX_CPUS + 1;
+	apicid_sp5100 = CONFIG_MAX_CPUS + 1
 #endif
 	apicid_sr5650 = apicid_sp5100 + 1;
 
-	//bus_sp5100[0], TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
 	dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
 	if (dev) {
 		/* Set SP5100 IOAPIC ID */
 		dword = pci_read_config32(dev, 0x74) & 0xfffffff0;
 		smp_write_ioapic(mc, apicid_sp5100, 0x20, dword);
 
+#ifdef UNUSED_CODE
+		u8 byte;
 		/* Initialize interrupt mapping */
 		/* aza */
 		byte = pci_read_config8(dev, 0x63);
@@ -85,6 +85,7 @@ static void *smp_write_config_table(void *v)
 		dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */
 		/* dword |= 1<<22; PIC and APIC co exists */
 		pci_write_config32(dev, 0xAC, dword);
+#endif
 
 		/*
 		 * 00:12.0: PROG SATA : INT F
@@ -102,11 +103,11 @@ static void *smp_write_config_table(void *v)
 
 		/* Set RS5650 IOAPIC ID */
 		dev = dev_find_slot(0, PCI_DEVFN(0, 0));
-                if (dev) {
-                        pci_write_config32(dev, 0xF8, 0x1);
-                        dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
-                        smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
-                }
+		if (dev) {
+			pci_write_config32(dev, 0xF8, 0x1);
+			dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+			smp_write_ioapic(mc, apicid_sr5650, 0x20, dword);
+		}
 
 	}
 
@@ -155,27 +156,27 @@ static void *smp_write_config_table(void *v)
 	 * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13);
 	 */
 
-        //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
-        //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */
+	//smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */
 
 	/* PCI slots */
-        /* PCI_SLOT 0. */
-        PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
-        PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
-        PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
-        PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
-
-        /* PCI_SLOT 1. */
-        PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
-        PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
-        PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
-        PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
-
-        /* PCI_SLOT 2. */
-        PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
-        PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
-        PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
-        PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
+	/* PCI_SLOT 0. */
+	PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);
+	PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15);
+	PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16);
+	PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17);
+
+	/* PCI_SLOT 1. */
+	PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15);
+	PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16);
+	PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17);
+	PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14);
+
+	/* PCI_SLOT 2. */
+	PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16);
+	PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17);
+	PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14);
+	PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15);
 
 
 	/*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
diff --git a/src/mainboard/supermicro/h8qgi/platform_cfg.h b/src/mainboard/supermicro/h8qgi/platform_cfg.h
new file mode 100644
index 0000000..bbc4ad7
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/platform_cfg.h
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _PLATFORM_CFG_H_
+#define _PLATFORM_CFG_H_
+
+
+/* northbridge customize options */
+/**
+ * Max number of northbridges in the system
+ */
+#define MAX_NB_COUNT		1 //TODO: only 1 NB tested
+
+/**
+ *  Enable check for PCIe endpoint to be ready for PCI enumeration.
+ *
+ */
+//#define  EPREADY_WORKAROUND_DISABLED
+
+/**
+ *  Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table.
+ *
+ */
+#define  IOMMU_SUPPORT_DISABLE //TODO: enable it
+
+/**
+ *  Disable server PCIe hotplug support.
+ */
+
+//#define HOTPLUG_SUPPORT_DISABLED
+
+/**
+ *  Disable support for device number remapping for PCIe portsserver PCIe hotplug support.
+ */
+
+//#define DEVICE_REMAP_DISABLE
+
+#endif //_PLATFORM_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.c b/src/mainboard/supermicro/h8qgi/platform_oem.c
index f36b0d8..883cad1 100644
--- a/src/mainboard/supermicro/h8qgi/platform_oem.c
+++ b/src/mainboard/supermicro/h8qgi/platform_oem.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,7 +21,6 @@
 #include "amdlib.h"
 #include "Ids.h"
 #include "heapManager.h"
-#include "platform_oem.h"
 #include "Filecode.h"
 
 #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@@ -43,6 +42,7 @@
  *
  **/
 /*---------------------------------------------------------------------------------------*/
+VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
 	//InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO;
diff --git a/src/mainboard/supermicro/h8qgi/platform_oem.h b/src/mainboard/supermicro/h8qgi/platform_oem.h
deleted file mode 100644
index ab0d6df..0000000
--- a/src/mainboard/supermicro/h8qgi/platform_oem.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#ifndef _PLATFORM_OEM_H_
-#define _PLATFORM_OEM_H_
-
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
-VOID OemCustomizeInitEarly(IN  OUT AMD_EARLY_PARAMS *InitEarly);
-
-#endif //_PLATFORM_OEM_H_
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
new file mode 100644
index 0000000..7a947b3
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "NbPlatform.h"
+#include "rd890_cfg.h"
+#include "northbridge/amd/cimx/rd890/chip.h"
+#include "nbInitializer.h"
+#include <string.h>
+#include <arch/ioapic.h>
+
+#ifndef __PRE_RAM__
+#include <device/device.h>
+extern void set_pcie_reset(void *config);
+extern void set_pcie_dereset(void *config);
+
+/**
+ * Platform dependent configuration at ramstage
+ */
+static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
+{
+	u16 i;
+	PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
+	//AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
+	struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
+	DEFAULT_PLATFORM_CONFIG(platform_config);
+
+	/* update the platform depentent configuration by devicetree */
+	rd890_info  = nb_dev->chip_info;
+	platform_config.PortEnableMap = rd890_info->port_enable;
+	if (rd890_info->gpp1_configuration == 0) {
+		platform_config.Gpp1Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp1_configuration == 1) {
+		platform_config.Gpp1Config = GFX_CONFIG_AABB;
+	}
+	if (rd890_info->gpp2_configuration == 0) {
+		platform_config.Gpp2Config = GFX_CONFIG_AAAA;
+	} else if (rd890_info->gpp2_configuration == 1) {
+		platform_config.Gpp2Config = GFX_CONFIG_AABB;
+	}
+	platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
+
+	if (platform_config.Gpp1Config != 0) {
+		pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
+	}
+	if (platform_config.Gpp2Config != 0) {
+		pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
+	}
+	if (platform_config.Gpp3aConfig != 0) {
+		pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
+	}
+
+	pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
+	for (i = 0; i <= MAX_CORE_ID; i++) {
+		NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
+		NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
+	}
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
+	}
+
+	for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+		if ((platform_config.PortEnableMap & (1 << i)) != 0) {
+			pPcieConfig->PortConfiguration[i].PortPresent = ON;
+			if ((platform_config.PortGen1Map & (1 << i)) != 0) {
+				pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
+			}
+			if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
+				u16 j;
+				pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
+				/* Set Hotplug descriptor info */
+				for (j = 0; j < 8; j++) {
+					u32 PortDescriptor;
+					PortDescriptor = platform_config.PortHotplugDescriptors[j];
+					if ((PortDescriptor & 0xF) == j) {
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap  = (PortDescriptor >> 4)  & 3;
+						pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6)  & 1;
+						break;
+					}
+				}
+			}
+		}
+	}
+}
+#endif // __PRE_RAM__
+
+/**
+ * @brief Entry point of Northbridge CIMx callout/CallBack
+ *
+ * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+ *
+ * @param[in] u32 func               Northbridge CIMx CallBackId
+ * @param[in] u32 data               Northbridge Input Data.
+ * @param[in] AMD_NB_CONFIG *config  Northbridge configuration structure pointer.
+ *
+ */
+static u32 rd890_callout_entry(u32 func, u32 data, void *config)
+{
+	u32 ret = 0;
+#ifndef __PRE_RAM__
+	device_t nb_dev = (device_t)data;
+#endif
+	AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
+
+	switch (func) {
+		case PHCB_AmdPortTrainingCompleted:
+			break;
+
+		case PHCB_AmdPortResetDeassert:
+#ifndef __PRE_RAM__
+			set_pcie_dereset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetAssert:
+#ifndef __PRE_RAM__
+			set_pcie_reset(config);
+#endif
+			break;
+
+		case PHCB_AmdPortResetSupported:
+			break;
+		case PHCB_AmdGeneratePciReset:
+			break;
+		case PHCB_AmdGetExclusionTable:
+			break;
+		case PHCB_AmdAllocateBuffer:
+			break;
+		case PHCB_AmdUpdateApicInterruptMapping:
+			break;
+		case PHCB_AmdFreeBuffer:
+			break;
+		case PHCB_AmdLocateBuffer:
+			break;
+		case PHCB_AmdReportEvent:
+			break;
+		case PHCB_AmdPcieAsmpInfo:
+			break;
+
+		case CB_AmdSetNbPorConfig:
+			break;
+		case CB_AmdSetHtConfig:
+			/*TODO: different HT path and deempasis for each NB */
+			nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
+
+			break;
+		case CB_AmdSetPcieEarlyConfig:
+#ifndef __PRE_RAM__
+			nb_platform_config(nb_dev, nbConfigPtr);
+#endif
+			break;
+
+		case CB_AmdSetEarlyPostConfig:
+			break;
+
+		case CB_AmdSetMidPostConfig:
+			nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR;
+#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
+			/* SBIOS must alloc 16K memory for IOMMU MMIO */
+			UINT32  MmcfgBarAddress; //using default IOmmuBaseAddress
+			LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
+					AccessWidth32,
+					&MmcfgBarAddress,
+					nbConfigPtr);
+			MmcfgBarAddress &= ~0xf;
+			if (MmcfgBarAddress != 0) {
+				nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
+			}
+			nbConfigPtr->IommuBaseAddress = 0; //disable iommu
+#endif
+			break;
+
+		case CB_AmdSetLatePostConfig:
+			break;
+
+		case CB_AmdSetRecoveryConfig:
+			break;
+	}
+
+	return ret;
+}
+
+
+/**
+ * @brief North Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
+{
+	u16 i = 0;
+	PCI_ADDR PciAddress;
+	u32 val, sbNode, sbLink;
+
+	if (!pConfig) {
+		return;
+	}
+
+	memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
+	for (i = 0; i < MAX_NB_COUNT; i++) {
+		pConfig->Northbridges[i].pNbConfig	= &nbConfig[i];
+		pConfig->Northbridges[i].pHtConfig	= &htConfig[i];
+		pConfig->Northbridges[i].pPcieConfig	= &pcieConfig[i];
+		pConfig->Northbridges[i].ConfigPtr	= &pConfig;
+	}
+
+	/* Initialize all NB structures */
+	AmdInitializer(pConfig);
+
+	pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
+	//pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
+	pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
+	pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+
+	/*
+	 * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
+	 * Always 0:0:0 on single NB platform.
+	 */
+	pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+
+	/* Set HT path to NB by SbNode and SbLink */
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbNode = (val >> 8) & 0x07;
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+	LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+	sbLink = (val >> 8) & 0x07; //assum ganged
+	pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
+	pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
+	//TODO: other NBs
+
+#ifndef __PRE_RAM__
+	/* If temporrary MMIO enable set up CPU MMIO */
+	for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
+		UINT32  MmioBase;
+		UINT32  LinkId;
+		UINT32  SubLinkId;
+		MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
+		if (MmioBase != 0) {
+			LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
+			SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
+			/* Set Limit */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
+					AccessWidth32,
+					0x0,
+					((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
+					&(pConfig->Northbridges[i]));
+			/* Set Base */
+			LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
+					AccessWidth32,
+					0x0,
+					(MmioBase << 12) | 0x3,
+					&(pConfig->Northbridges[i]));
+		}
+	}
+#endif
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
new file mode 100644
index 0000000..8f45019
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@@ -0,0 +1,174 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef  _RD890_CFG_H_
+#define _RD890_CFG_H_
+
+#include "NbPlatform.h"
+
+/* platform dependent configuration default value */
+
+/**
+ * Path from CPU to NB
+ * [0..7]   - Node  (0..8)
+ * [8..11]  - Link  (0..3)
+ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
+ */
+#ifndef DEFAULT_HT_PATH
+#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x3}
+#endif
+#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#define DEFAULT_HT_PATH		{0x0, 0x1}
+#endif
+#endif
+
+/**
+ * Bitmap of enabled ports on NB #0/1/2/3
+ * Bit[0] - Reserved
+ * Bit[1] - Reserved
+ * Bit[2] - Enable PCIe port 2
+ * Bit[3] - Enable PCIe port 3
+ * Bit[4] - Enable PCIe port 4
+ * Bit[5] - Enable PCIe port 5
+ * Bit[6] - Enable PCIe port 2
+ * Bit[7] - Enable PCIe port 7
+ * Bit[8] - Reserved
+ * Bit[9] - Enable PCIe port 9
+ * Bit[10]- Enable PCIe port 10
+ * Bit[11]- Enable PCIe port 11
+ * Bit[12]- Enable PCIe port 12
+ * Bit[13]- Enable PCIe port 13
+ * Example:
+ *  port_enable = 0x14
+ *  Port 2 and 4 enabled for training/initialization
+ */
+#ifndef DEFAULT_PORT_ENABLE_MAP
+#define DEFAULT_PORT_ENABLE_MAP		0x0014
+#endif
+
+/**
+ * Bitmap of ports that have slot or onboard device connected.
+ * Example force PCIe Gen1 supporton port 2 and 4  (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
+ * #define DEFAULT_PORT_FORCE_GEN1        0x604
+ */
+#ifndef DEFAULT_PORT_FORCE_GEN1
+#define DEFAULT_PORT_FORCE_GEN1		0x0
+#endif
+
+/**
+ * Bitmap of ports that have server hotplug support
+ */
+#ifndef DEFAULT_HOTPLUG_SUPPORT
+#define DEFAULT_HOTPLUG_SUPPORT		0x0
+#endif
+
+#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
+#define DEFAULT_HOTPLUG_DESCRIPTOR		{0, 0, 0, 0, 0, 0, 0, 0}
+#endif
+
+#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
+#define DEFAULT_TEMPMMIO_BASE_ADDRESS		0xD0000000
+#endif
+
+/**
+ * Default GPP1 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP1_CONFIG
+#define DEFAULT_GPP1_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP2 core configuraton on NB #0/1/2/3.
+ *  2  x8 slot, GFX_CONFIG_AABB
+ *  1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP2_CONFIG
+#define DEFAULT_GPP2_CONFIG		GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP3a core configuraton on NB #0/1/2/3.
+ * 4:2:0:0:0:0   - GPP_CONFIG_GPP420000, 0x1
+ * 4:1:1:0:0:0   - GPP_CONFIG_GPP411000, 0x2
+ * 2:2:2:0:0:0   - GPP_CONFIG_GPP222000, 0x3
+ * 2:2:1:1:0:0   - GPP_CONFIG_GPP221100, 0x4
+ * 2:1:1:1:1:0   - GPP_CONFIG_GPP211110, 0x5
+ * 1:1:1:1:1:1   - GPP_CONFIG_GPP111111, 0x6
+ */
+#ifndef DEFAULT_GPP3A_CONFIG
+#define DEFAULT_GPP3A_CONFIG		GPP_CONFIG_GPP111111
+#endif
+
+
+/**
+ * Default HT Transmitter de-emphasis setting
+ */
+#ifndef DEFAULT_HT_DEEMPASIES
+#define DEFAULT_HT_DEEMPASIES		0x3
+#endif
+
+/**
+ * Default APIC nterrupt base for IOAPIC
+ */
+#ifndef DEFAULT_APIC_INTERRUPT_BASE
+#define DEFAULT_APIC_INTERRUPT_BASE	24
+#endif
+
+
+#define DEFAULT_PLATFORM_CONFIG(name) \
+	NB_PLATFORM_CONFIG name = { \
+		DEFAULT_PORT_ENABLE_MAP, \
+		DEFAULT_PORT_FORCE_GEN1, \
+		DEFAULT_HOTPLUG_SUPPORT, \
+		DEFAULT_HOTPLUG_DESCRIPTOR, \
+		DEFAULT_TEMPMMIO_BASE_ADDRESS, \
+		DEFAULT_GPP1_CONFIG, \
+		DEFAULT_GPP2_CONFIG, \
+		DEFAULT_GPP3A_CONFIG, \
+		DEFAULT_HT_DEEMPASIES, \
+		/*DEFAULT_HT_PATH,*/ \
+		DEFAULT_APIC_INTERRUPT_BASE, \
+	}
+
+/**
+ * Platform configuration
+ */
+typedef struct {
+	UINT16  PortEnableMap;            ///< Bitmap of enabled ports
+	UINT16  PortGen1Map;              ///< Bitmap of ports to disable Gen2
+	UINT16  PortHotplugMap;           ///< Bitmap of ports support hotplug
+	UINT8   PortHotplugDescriptors[8];///< Ports Hotplug descriptors
+	UINT32  TemporaryMmio;            ///< Temporary MMIO
+	UINT32  Gpp1Config;               ///< Default PCIe GFX core configuration
+	UINT32  Gpp2Config;               ///< Default PCIe GPP2 core configuration
+	UINT32  Gpp3aConfig;              ///< Default PCIe GPP3a core configuration
+	UINT8   NbTransmitterDeemphasis;  ///< HT transmitter de-emphasis level
+	//	HT_PATH NbHtPath;                 ///< HT path to NB
+	UINT8   GlobalApicInterruptBase;  ///< Global APIC interrupt base that is used in MADT table for IO APIC.
+} NB_PLATFORM_CONFIG;
+
+/**
+ * Bridge CIMx configuration
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
+
+#endif //_RD890_CFG_H_
diff --git a/src/mainboard/supermicro/h8qgi/reset.c b/src/mainboard/supermicro/h8qgi/reset.c
new file mode 100644
index 0000000..68a39f2
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/reset.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <reset.h>
+#include <arch/io.h>		/*inb, outb*/
+#include <arch/romcc_io.h>	/*pci_read_config32, device_t, PCI_DEV*/
+
+#define HT_INIT_CONTROL		0x6C
+#define HTIC_BIOSR_Detect	(1<<5)
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 32
+#define NODE_PCI(x, fn)	((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
+#else
+#define NODE_PCI(x, fn)	PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)
+#endif
+
+static inline void set_bios_reset(void)
+{
+	u32 nodes;
+	u32 htic;
+	device_t dev;
+	int i;
+
+	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
+	for(i = 0; i < nodes; i++) {
+		dev = NODE_PCI(i, 0);
+		htic = pci_read_config32(dev, HT_INIT_CONTROL);
+		htic &= ~HTIC_BIOSR_Detect;
+		pci_write_config32(dev, HT_INIT_CONTROL, htic);
+	}
+}
+
+void hard_reset(void)
+{
+	set_bios_reset();
+	/* Try rebooting through port 0xcf9 */
+	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
+	outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}
+
+//SbReset();
+void soft_reset(void)
+{
+	set_bios_reset();
+	/* link reset */
+	outb(0x06, 0x0cf9);
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 08b0eb2..119593e 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -29,34 +29,54 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "agesawrapper.h"
 #include "northbridge/amd/agesa/family10/reset_test.h"
-#include "southbridge/amd/sr5650/sr5650.h"
-#include "southbridge/amd/sb700/sb700.h"
+#include <nb_cimx.h>
+#include <sb_cimx.h>
 #include "superio/nuvoton/wpcm450/wpcm450.h"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 
 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
 
+//TODO: should not put here
+static void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, base);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 |= 1 << 2;
+	pci_write_config8(dev, 0x48, reg8);
+}
+
+static void sb7xx_51xx_disable_wideio(u8 wio_index)
+{
+	/* TODO: Now assume wio_index=0 */
+	device_t dev;
+	u8 reg8;
+
+	//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0);	/* LPC Controller */
+	dev = PCI_DEV(0, 0x14, 3);	/* LPC Controller */
+	pci_write_config32(dev, 0x64, 0);
+	reg8 = pci_read_config8(dev, 0x48);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(dev, 0x48, reg8);
+}
+
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	post_code(0x30);
 	agesawrapper_amdinitmmio();
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
-		/* SR56x0 pcie bridges block pci_locate_device() before pcie training.
-		 * disable all pcie bridges on SR56x0 to work around it
-		 */
-		sr5650_disable_pcie_bridge();
-		post_code(0x31);
-		sb7xx_51xx_lpc_port80();
-		post_code(0x32);
-	}
+	post_code(0x31);
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x33);
 	report_bist_failure(bist);
 
-	enable_sr5650_dev8();
-	sb7xx_51xx_lpc_init();
 	sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
 	wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
 	sb7xx_51xx_disable_wideio(0);
@@ -78,7 +98,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n");
 	}
 
-	post_code(0x38);
+	if (!cpu_init_detectedx && boot_cpu()) {
+		post_code(0x38);
+		/*
+		 * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR,
+		 * Disable all Pcie Bridges to work around It.
+		 */
+		sr56x0_rd890_disable_pcie_bridge();
+		post_code(0x39);
+		nb_Poweron_Init();
+		post_code(0x3A);
+		sb_Poweron_Init();
+	}
+	post_code(0x3B);
 	val = agesawrapper_amdinitearly();
 	if(val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
@@ -86,12 +118,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n");
 	}
 
-	sr5650_early_setup();
-	post_code(0x39);
-
-	sb7xx_51xx_early_setup();
-	sr5650_htinit();
-	/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+	post_code(0x3C);
+	nb_Ht_Init();
+	post_code(0x3D);
+	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
 	if (!warm_reset_detect(0)) {
 		print_info("...WARM RESET...\n\n\n");
 		distinguish_cpu_resets(0);
@@ -103,8 +133,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	val = agesawrapper_amdinitpost();
 	if (val) {
 		printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
+	} else {
+		printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 	}
-	printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n");
 
 	post_code(0x41);
 	val = agesawrapper_amdinitenv();
@@ -114,8 +145,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n");
 
 	post_code(0x42);
-	sr5650_before_pci_init();
-	sb7xx_51xx_before_pci_init();
 
 	post_code(0x50);
 	print_debug("Disabling cache as ram ");
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
new file mode 100644
index 0000000..4cbb8ca
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <string.h>
+#include <console/console.h>    /* printk */
+#include "Platform.h"
+#include "sb700_cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb700_cimx_config(AMDSBCFG *sb_config)
+{
+	if (!sb_config) {
+		printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n");
+	memset(sb_config, 0, sizeof(AMDSBCFG));
+
+	/* SB_POWERON_INIT */
+	sb_config->StdHeader.Func = SB_POWERON_INIT;
+
+	/* header */
+	sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS;
+
+	/* static Build Parameters */
+	sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+	sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+	sb_config->BuildParameters.EcKbd = 0;
+	sb_config->BuildParameters.EcChannel0 = 0;
+	sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
+	sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
+	sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+	sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
+	sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
+
+	sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
+	sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
+	sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
+	sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT;
+	sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS;
+
+	sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
+	sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
+	sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
+	sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
+	sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID;
+	sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID;
+	sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID;
+	sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID;
+	sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
+	sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID;
+	sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID;
+	sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
+	sb_config->BuildParameters.IdeSsid = IDE_SSID;
+	sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
+	sb_config->BuildParameters.LpcSsid = LPC_SSID;
+
+	sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
+
+	/* General */
+	sb_config->Spi33Mhz = 1;
+	sb_config->SpreadSpectrum = 0;
+	sb_config->PciClk5 = 0;
+	sb_config->PciClks = 0x1F;
+	sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood
+	sb_config->TimerClockSource = 2;  // Auto
+	sb_config->S3Resume = 0;
+	sb_config->RebootRequired = 0;
+
+	/* HPET */
+	sb_config->HpetTimer = HPET_TIMER;
+
+	/* USB */
+	sb_config->UsbIntClock = 0;     // Use external clock
+	sb_config->Usb1Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 18 Func0
+	sb_config->Usb1Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 18 Func1
+	sb_config->Usb1Ehci  = 1; //0:disable  1:enable Bus 0 Dev 18 Func2
+	sb_config->Usb2Ohci0 = 1; //0:disable  1:enable Bus 0 Dev 19 Func0
+	sb_config->Usb2Ohci1 = 1; //0:disable  1:enable Bus 0 Dev 19 Func1
+	sb_config->Usb2Ehci  = 1; //0:disable  1:enable Bus 0 Dev 19 Func2
+	sb_config->Usb3Ohci  = 1; //0:disable  1:enable Bus 0 Dev 20 Func5
+	sb_config->UsbOhciLegacyEmulation = 1; //0:Enable  1:Disable
+
+	sb_config->AcpiS1Supported = 1;
+
+	/* SATA */
+	sb_config->SataController = 1;
+	sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci
+	sb_config->SataSmbus = 0;
+	sb_config->SataAggrLinkPmCap = 1;
+	sb_config->SataPortMultCap = 1;
+	sb_config->SataClkAutoOff = 1;
+	sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
+	//TODO: set to secondary not take effect.
+	sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled
+	sb_config->SataEspPort = 0;
+	sb_config->SataClkAutoOffAhciMode = 1;
+	sb_config->SataHpcpButNonESP = 0;
+	sb_config->SataHideUnusedPort = 0;
+
+	/* Azalia HDA */
+	sb_config->AzaliaController = AZALIA_CONTROLLER;
+	sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
+	sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN;
+	sb_config->pAzaliaOemCodecTablePtr = NULL;
+
+#ifndef __PRE_RAM__
+	/* ramstage cimx config here */
+	if (!sb_config->StdHeader.pCallBack) {
+		sb_config->StdHeader.pCallBack = sb700_callout_entry;
+	}
+
+	//sb_config->
+#endif //!__PRE_RAM__
+	printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n");
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
new file mode 100644
index 0000000..aac61ec
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
@@ -0,0 +1,237 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#ifndef _SB700_CFG_H_
+#define _SB700_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M                    0
+#define BIOS_SIZE_2M                    1
+#define BIOS_SIZE_4M                    3
+#define BIOS_SIZE_8M                    7
+
+/* In SB700, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+#define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+#define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+#define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ *  0 - Disable Spread Spectrum function
+ *  1 - Enable  Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM                 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ *  0 - Disable hpet
+ *  1 - Enable  hpet
+ */
+#define HPET_TIMER                      1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ *   0 - Disable
+ *   1 - Enable
+ *  Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ *  Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ *  Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ *  Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ *  Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ *  Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ *  Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CINFIG              0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ *   0 - disable
+ *   1 - enable
+ *  PCI SLOT 0 define at BIT0
+ *  PCI SLOT 1 define at BIT1
+ *  PCI SLOT 2 define at BIT2
+ *  PCI SLOT 3 define at BIT3
+ *  PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL                  0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#ifndef SATA_CONTROLLER
+#define SATA_CONTROLLER               1
+#endif
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_MODE
+#define SATA_MODE                     NATIVE_IDE_MODE
+#endif
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE                 0
+#define IDE_NATIVE_MODE                 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ *   NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_IDE_MODE
+#define SATA_IDE_MODE                 IDE_LEGACY_MODE
+#endif
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ *  PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ *  CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK          0x00
+#define INTERNAL_CLOCK          0x01
+
+#define SATA_CLOCK_SOURCE       EXTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED     1
+
+
+/**
+ * @def   AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def   AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def   AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO                     0
+#define AZALIA_DISABLE                  1
+#define AZALIA_ENABLE                   2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#ifndef AZALIA_CONTROLLER
+#define AZALIA_CONTROLLER             AZALIA_AUTO
+#endif
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ *  0 - disable
+ *  1 - enable
+ */
+#ifndef AZALIA_PIN_CONFIG
+#define AZALIA_PIN_CONFIG             1
+#endif
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ *  SDIN0 is define at BIT0 & BIT1
+ *   00 - GPIO PIN
+ *   01 - Reserved
+ *   10 - As a Azalia SDIN pin
+ *  SDIN1 is define at BIT2 & BIT3
+ *  SDIN2 is define at BIT4 & BIT5
+ *  SDIN3 is define at BIT6 & BIT7
+ */
+#ifndef AZALIA_SDIN_PIN
+//#define AZALIA_SDIN_PIN             0xAA
+#define AZALIA_SDIN_PIN               0x2A
+#endif
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#ifndef GPP_CONTROLLER
+#define GPP_CONTROLLER                1
+#endif
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ *  GPP_CFGMODE_X4000
+ *  GPP_CFGMODE_X2200
+ *  GPP_CFGMODE_X2110
+ *  GPP_CFGMODE_X1111
+ */
+#ifndef GPP_CFGMODE
+#define GPP_CFGMODE                   GPP_CFGMODE_X1111
+#endif
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb700_cimx_config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func    Southbridge CIMx Function ID.
+ * @param[in] data    Southbridge Input Data.
+ * @param[in] sb_cfg  Southbridge configuration structure pointer.
+ *
+ */
+u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif //_SB700_CFG_H_


From gerrit at coreboot.org  Fri Jan 20 10:58:17 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 10:58:17 +0100
Subject: [coreboot] Patch set updated for coreboot: 029f7f4 SIO: condition
	compile Nuvoton WPCM450 early_init.c
References: <Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878+0@gerrit.coreboot.org>
Message-ID: <Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/566

-gerrit

commit 029f7f455fb12b9ba04478317e1c40f0fc824a1d
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 18:49:07 2012 +0800

    SIO: condition compile Nuvoton WPCM450 early_init.c
    
    Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450
    
    Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/superio/nuvoton/wpcm450/Makefile.inc |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc
index c70b2fb..b4e4ea7 100644
--- a/src/superio/nuvoton/wpcm450/Makefile.inc
+++ b/src/superio/nuvoton/wpcm450/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2011 Advanced Micro Devices, Inc.
+## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,6 +18,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-romstage-y += early_init.c
+romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c
 ramstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += superio.c
 


From gerrit at coreboot.org  Fri Jan 20 10:58:18 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 10:58:18 +0100
Subject: [coreboot] Patch set updated for coreboot: ab58c62 SIO: Winbond
	w83627dhg update
References: <I42eaaf7d70aa48d7edf2710349b51e401526c1a6+0@gerrit.coreboot.org>
Message-ID: <I42eaaf7d70aa48d7edf2710349b51e401526c1a6+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565

-gerrit

commit ab58c622e32f97f7b6e14158dd21437c187c35d1
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 18:48:17 2012 +0800

    SIO: Winbond w83627dhg update
    
    1. Stop include c file.
    2. W83627dhg Pin 89, Pin 90 are multi function pins,
       add support to select them to I2C function.
    
    Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/asrock/939a785gmh/romstage.c   |    2 +-
 src/mainboard/kontron/kt690/romstage.c       |    2 +-
 src/superio/winbond/w83627dhg/Makefile.inc   |    2 +
 src/superio/winbond/w83627dhg/early_serial.c |   29 +++++++++++++++++++++++--
 src/superio/winbond/w83627dhg/superio.c      |    4 +-
 src/superio/winbond/w83627dhg/w83627dhg.h    |    6 +++++
 6 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 3183c1c..4a1b1c3 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -39,7 +39,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627dhg/early_serial.c"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index f2525e3..621c27f 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -40,7 +40,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627dhg/early_serial.c"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc
index 0b0bb8b..09df47e 100644
--- a/src/superio/winbond/w83627dhg/Makefile.inc
+++ b/src/superio/winbond/w83627dhg/Makefile.inc
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,5 +19,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c
 
diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c
index f530dc6..e0be8de 100644
--- a/src/superio/winbond/w83627dhg/early_serial.c
+++ b/src/superio/winbond/w83627dhg/early_serial.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,24 +19,26 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <device/pnp_def.h>
 #include <stdint.h>
 #include "w83627dhg.h"
 
-static void pnp_enter_ext_func_mode(device_t dev)
+void pnp_enter_ext_func_mode(device_t dev)
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
 	outb(0x87, port);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
+void pnp_exit_ext_func_mode(device_t dev)
 {
 	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-static void w83627dhg_enable_serial(device_t dev, u16 iobase)
+void w83627dhg_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
@@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase)
 	pnp_set_enable(dev, 1);
 	pnp_exit_ext_func_mode(dev);
 }
+
+/**
+ * Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
+ *  {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or
+ *  {RSTOUT3#, RSTOUT2#} or {SDA, SCL}
+ */
+void w83627dhg_enable_i2c(device_t dev)
+{
+	u8 val;
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+
+	val = pnp_read_config(dev, 0x2A);
+	val |= 1 << 1;
+	pnp_write_config(dev, 0x2A, val);
+
+	pnp_exit_ext_func_mode(dev);
+}
+
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 1771c26..a936ce1 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -26,13 +26,13 @@
 #include "chip.h"
 #include "w83627dhg.h"
 
-static void pnp_enter_ext_func_mode(device_t dev)
+void pnp_enter_ext_func_mode(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
 	outb(0x87, dev->path.pnp.port);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
+void pnp_exit_ext_func_mode(device_t dev)
 {
 	outb(0xaa, dev->path.pnp.port);
 }
diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h
index 74761e9..158e60b 100644
--- a/src/superio/winbond/w83627dhg/w83627dhg.h
+++ b/src/superio/winbond/w83627dhg/w83627dhg.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -51,4 +52,9 @@
 
 /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
 
+void pnp_enter_ext_func_mode(device_t dev);
+void pnp_exit_ext_func_mode(device_t dev);
+void w83627dhg_enable_serial(device_t dev, u16 iobase);
+void w83627dhg_enable_i2c(device_t dev);
+
 #endif


From gerrit at coreboot.org  Fri Jan 20 10:58:18 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 10:58:18 +0100
Subject: [coreboot] Patch set updated for coreboot: c54bf5d HWM: Winbond
	W83795 HWM support
References: <I8756f5ed02dc2fa0884cde36e51451fd8aacee27+0@gerrit.coreboot.org>
Message-ID: <I8756f5ed02dc2fa0884cde36e51451fd8aacee27+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/569

-gerrit

commit c54bf5d4ccb746743ed456909270a23526eb42dc
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 18:50:17 2012 +0800

    HWM: Winbond W83795 HWM support
    
    Supermicro H8QGI-F 1 Unit Chassis contain 8 system Fans,
    they are controled by a saparate W83795 Hardware Monitor chip.
    This patch add the w83795 HWM support.
    
    Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/Makefile.inc |    1 +
 src/mainboard/supermicro/h8qgi/romstage.c   |    9 ++
 src/mainboard/supermicro/h8qgi/w83795.c     |  186 +++++++++++++++++++++++++++
 src/mainboard/supermicro/h8qgi/w83795.h     |   73 +++++++++++
 4 files changed, 269 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/Makefile.inc b/src/mainboard/supermicro/h8qgi/Makefile.inc
index 82264a4..ef81caf 100644
--- a/src/mainboard/supermicro/h8qgi/Makefile.inc
+++ b/src/mainboard/supermicro/h8qgi/Makefile.inc
@@ -17,6 +17,7 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+romstage-y += w83795.c
 romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c
 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index 119593e..15828fe 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -33,6 +33,7 @@
 #include <sb_cimx.h>
 #include "superio/nuvoton/wpcm450/wpcm450.h"
 #include "superio/winbond/w83627dhg/w83627dhg.h"
+#include "w83795.h"
 
 extern void disable_cache_as_ram(void); /* cache_as_ram.inc */
 
@@ -119,6 +120,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	}
 
 	post_code(0x3C);
+	/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
+	 * In order to access W83795G/ADG HWM using I2C protocol,
+	 * we select function to SDA, SCL function (or GP33, GP32 function).
+	 */
+	w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
+	w83795_init(THERMAL_CRUISE_MODE);
+	w83627dhg_enable_serial(PNP_DEV(0x2E, W83627DHG_SP1), CONFIG_TTYS0_BASE);
+
 	nb_Ht_Init();
 	post_code(0x3D);
 	/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
diff --git a/src/mainboard/supermicro/h8qgi/w83795.c b/src/mainboard/supermicro/h8qgi/w83795.c
new file mode 100644
index 0000000..7832dfa
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/w83795.c
@@ -0,0 +1,186 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
+#include "w83795.h"
+
+static u32 w83795_set_bank(u8 bank)
+{
+	return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank);
+}
+
+static u8 w83795_read(u16 reg)
+{
+	u32 ret;
+
+	ret = w83795_set_bank(reg >> 8);
+	if (ret < 0) {
+		printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff);
+	return ret;
+}
+
+static u8 w83795_write(u16 reg, u8 value)
+{
+	u32 err;
+
+	err = w83795_set_bank(reg >> 8);
+	if (err < 0) {
+		printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8);
+		return -1;
+	}
+
+	err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value);
+	return err;
+}
+
+#if 0
+static void w83795_set_speed(void)
+{
+
+}
+
+static void w83795_set_ttti(void)//KR it works
+{
+	u32 i;
+	for (i = 0; i < 6; i++) {
+		//w83795_write(W83795_REG_TTTI(i), 0xa);//10 degree, default 40
+		//w83795_write(W83795_REG_CTFS(i), 0x20);//32 degree, default 80
+	}
+}
+#endif
+
+static void w83795_set_tfmr(w83795_fan_mode_t mode)
+{
+	u8 val;
+	u8 i;
+
+	if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) {
+		val = 0xFF;
+	} else {
+		val = 0x00;
+	}
+
+	for (i = 0; i < 6; i++)
+		w83795_write(W83795_REG_TFMR(i), val);
+}
+
+static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
+{
+	if (mode == SPEED_CRUISE_MODE) {
+		w83795_write(W83795_REG_FCMS1, 0xFF);
+		printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n");
+	}  else {
+		w83795_write(W83795_REG_FCMS1, 0x00);
+		if (mode == THERMAL_CRUISE_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x00);
+			printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n");
+		} else if (mode == SMART_FAN_MODE) {
+			w83795_write(W83795_REG_FCMS2, 0x3F);
+			printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n");
+		} else {
+			printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void w83795_set_tss(void)
+{
+	u8 val;
+
+	val = 0x00;
+	w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */
+	w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */
+	w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */
+}
+
+static void w83795_set_fan(w83795_fan_mode_t mode)
+{
+	u8 i;
+
+	/* select temperature sensor (TSS)*/
+	w83795_set_tss();
+
+	/* select Temperature to Fan mapping Relationships (TFMR)*/
+	w83795_set_tfmr(mode);
+
+	/* set fan output controlled mode (FCMS)*/
+	w83795_set_fan_mode(mode);
+
+	/* Set Critical Temperature to Full Speed all fan (CTFS) */
+	for (i = 0; i < 6; i++) {
+		w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */
+	}
+
+	if (mode == THERMAL_CRUISE_MODE) {
+		/* Set Target Temperature of Temperature Inputs (TTTI) */
+		for (i = 0; i < 6; i++) {
+			w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */
+		}
+	} else if (mode == SMART_FAN_MODE) {
+		/* Set the Relative Register-at SMART FAN IV Control Mode Table */
+		//SFIV TODO
+	}
+
+	/* Set Hystersis of Temperature (HT) */
+}
+
+void w83795_init(w83795_fan_mode_t mode)
+{
+	u8 i;
+	u8 val;
+
+	if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
+		printk(BIOS_INFO, "W83795G/ADG Nuvoton H/W Monitor not found\n");
+		return;
+	}
+	val = w83795_read(W83795_REG_CONFIG);
+	if ((val & W83795_REG_CONFIG_CONFIG48) == 0)
+		printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n");
+	else if ((val & W83795_REG_CONFIG_CONFIG48) == 1)
+		printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n");
+
+	/* Reset */
+	val |= W83795_REG_CONFIG_INIT;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	/* enable monitoring operations */
+	val = w83795_read(W83795_REG_CONFIG);
+	val |= W83795_REG_CONFIG_START;
+	w83795_write(W83795_REG_CONFIG, val);
+
+	w83795_set_fan(mode);
+
+	printk(BIOS_INFO, "Fan   CTFS(celsius)  TTTI(celsius)\n");
+	for (i = 0; i < 6; i++) {
+		val = w83795_read(W83795_REG_CTFS(i));
+		printk(BIOS_INFO, " %x     %d", i, val);
+		val = w83795_read(W83795_REG_TTTI(i));
+		printk(BIOS_INFO, "             %d\n", val);
+	}
+}
+
diff --git a/src/mainboard/supermicro/h8qgi/w83795.h b/src/mainboard/supermicro/h8qgi/w83795.h
new file mode 100644
index 0000000..76623a0
--- /dev/null
+++ b/src/mainboard/supermicro/h8qgi/w83795.h
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef _W83795_H_
+#define _W83795_H_
+
+#define W83795_DEV			0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */
+
+#define W83795_REG_I2C_ADDR		0xFC
+#define W83795_REG_BANKSEL		0x00
+#define W83795_REG_CONFIG		0x01
+#define W83795_REG_CONFIG_START		0x01
+#define W83795_REG_CONFIG_CONFIG48	0x04
+#define W83795_REG_CONFIG_INIT		0x80
+
+#define W83795_REG_TEMP_CTRL1		0x04 /* Temperature Monitoring Control Register */
+#define W83795_REG_TEMP_CTRL2		0x05 /* Temperature Monitoring Control Register */
+#define W83795_REG_FANIN_CTRL1		0x06
+#define W83795_REG_FANIN_CTRL2		0x07
+#define W83795_REG_TEMP_CTRL1_EN_DTS	0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */
+
+#define W83795_REG_TSS(n)		(0x209 + (n)) /* Temperature Source Selection Register */
+#define W83795_REG_TTTI(n)		(0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */
+#define W83795_REG_CTFS(n)		(0x268 + (n)) /* Critical Temperature to Full Speed all fan */
+#define W83795_REG_HT(n)		(0x270 + (n)) /* Hystersis of Temperature */
+#define W83795_REG_DTSC			0x301 /* Digital Temperature Sensor Configuration */
+
+#define W83795_REG_DTSE			0x302 /* Digital Temperature Sensor Enable */
+#define W83795_REG_DTS(n)		(0x26 + (n))
+#define W83795_REG_VRLSB		0x3C
+
+#define W83795_TEMP_REG_TR1		0x21
+#define W83795_TEMP_REG_TR2		0x22
+#define W83795_TEMP_REG_TR3		0x23
+#define W83795_TEMP_REG_TR4		0x24
+#define W83795_TEMP_REG_TR5		0x1F
+#define W83795_TEMP_REG_TR6		0x20
+
+#define W83795_REG_FCMS1		0x201
+#define W83795_REG_FCMS2		0x208
+#define W83795_REG_TFMR(n)		(0x202 + (n)) /*temperature to fam mappig*/
+#define W83795_REG_DFSP			0x20C
+
+#define W83795_REG_FTSH(n)		(0x240 + (n) * 2)
+#define W83795_REG_FTSL(n)		(0x241 + (n) * 2)
+#define W83795_REG_TFTS			0x250
+
+typedef enum w83795_fan_mode {
+	SPEED_CRUISE_MODE,	///< Fan Speed Cruise mode keeps the fan speed in a specified range
+	THERMAL_CRUISE_MODE,	///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI
+	SMART_FAN_MODE,		///< Smart Fan mode offers 6 slopes to control the fan speed
+	MANUAL_MODE,		///< control manually
+} w83795_fan_mode_t;
+
+void w83795_init(w83795_fan_mode_t mode);
+
+#endif


From gerrit at coreboot.org  Fri Jan 20 10:58:19 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 10:58:19 +0100
Subject: [coreboot] Patch set updated for coreboot: 40d0b33 H8QGI:
	supermicro/h8qgi xip size increase from 512K to 1M Bytes.
References: <I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe+0@gerrit.coreboot.org>
Message-ID: <I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe+2@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568

-gerrit

commit 40d0b33ba8a18805605c7818d45b48ed92d3c439
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 18:50:15 2012 +0800

    H8QGI: supermicro/h8qgi xip size increase from 512K to 1M Bytes.
    
    Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/supermicro/h8qgi/Kconfig |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig
index e900ea8..201df45 100644
--- a/src/mainboard/supermicro/h8qgi/Kconfig
+++ b/src/mainboard/supermicro/h8qgi/Kconfig
@@ -123,5 +123,19 @@ config VGA_BIOS_ID
 	depends on VGA_BIOS
 	default "102b,0532"
 
+config XIP_ROM_BASE
+	hex
+	default 0xfff00000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x100000
+	help
+	  Overwride the default write through caching size as 1M Bytes.
+	  On some AMD paltform, one socket support 2 kinds of processor family,
+	  Compiling 2 cpu families agesa code will increase the romstage size.
+	  In order to execute romstage in place on the flash rom,
+	  more space is required to be set as write through caching.
+
 endif # BOARD_SUPERMICRO_H8QGI
 


From gerrit at coreboot.org  Fri Jan 20 14:39:02 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 20 Jan 2012 14:39:02 +0100
Subject: [coreboot] Patch merged into coreboot/master: 5af98c9 Leave SSE and
	MMX instructions enabled in coreboot
References: <I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e+0@gerrit.coreboot.org>
Message-ID: <E1RoEgI-0004VV-7G@ra.coresystems.de>

the following patch was just integrated into master:
commit 5af98c9e3b9c2dc27085247946a48346c33ea4cd
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Wed Jan 18 23:28:52 2012 +0100

    Leave SSE and MMX instructions enabled in coreboot
    
    In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
    instructions in the CPU after romstage.
    
    Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jan 20 14:39:00 2012, giving +2
See http://review.coreboot.org/553 for details.

-gerrit


From wmkamp at datakamp.de  Fri Jan 20 17:45:42 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Fri, 20 Jan 2012 17:45:42 +0100
Subject: [coreboot] Change in coreboot[master]: Inagua: Synchronize
 AMD/inagua mainboard.
In-Reply-To: <gerrit.1326872167479.Ia038e5a2b9550fe81bb075f31e30b98354758e9e@review.coreboot.org>
References: <gerrit.1326872167479.Ia038e5a2b9550fe81bb075f31e30b98354758e9e@review.coreboot.org>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDD02@DATAKAMPONE.datakamp2008.local>

Hello Marc,

I reviewed the code and it looks good.
But real testing shows an issue with soft restart (UBUNTU).
The southbridge seems to hang. Coreboot stops because it could not read the SPI ROM of DIMM Module.
Please see logs.
The cold start log also reports errors but will successful boot Ubuntu.

Regards

Wolfgang



-----Urspr?ngliche Nachricht-----
Von: gerrit code review [mailto:gerrit at coreboot.org] 
Gesendet: Freitag, 20. Januar 2012 00:52
An: Wolfgang Kamp - datakamp
Cc: Kerry Sheh
Betreff: Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.

From Marc Jones <marcj303 at gmail.com>:

Hello Wolfgang Kamp,

I'd like you to do a code review.  Please visit

    http://review.coreboot.org/542

to review the following change.

Change subject: Inagua: Synchronize AMD/inagua mainboard.
.....................................................................

Inagua: Synchronize AMD/inagua mainboard.

AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.

Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui at gmail.com>
Signed-off-by: Kerry Sheh <kerry.she at amd.com>
---
M src/mainboard/amd/inagua/BiosCallOuts.c
M src/mainboard/amd/inagua/BiosCallOuts.h
M src/mainboard/amd/inagua/Kconfig
M src/mainboard/amd/inagua/Makefile.inc
M src/mainboard/amd/inagua/OptionsIds.h
M src/mainboard/amd/inagua/PlatformGnbPcie.c
D src/mainboard/amd/inagua/acpi/ssdt2.asl
D src/mainboard/amd/inagua/acpi/ssdt3.asl
D src/mainboard/amd/inagua/acpi/ssdt4.asl
D src/mainboard/amd/inagua/acpi/ssdt5.asl
M src/mainboard/amd/inagua/acpi_tables.c
M src/mainboard/amd/inagua/agesawrapper.c
M src/mainboard/amd/inagua/agesawrapper.h
M src/mainboard/amd/inagua/buildOpts.c
M src/mainboard/amd/inagua/devicetree.cb
M src/mainboard/amd/inagua/dimmSpd.c
M src/mainboard/amd/inagua/dsdt.asl
M src/mainboard/amd/inagua/fadt.c
M src/mainboard/amd/inagua/get_bus_conf.c
M src/mainboard/amd/inagua/irq_tables.c
M src/mainboard/amd/inagua/mainboard.c
M src/mainboard/amd/inagua/mptable.c
M src/mainboard/amd/inagua/platform_cfg.h
M src/mainboard/amd/inagua/romstage.c
24 files changed, 249 insertions(+), 717 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/542/2
--
To view, visit http://review.coreboot.org/542
To unsubscribe, visit http://review.coreboot.org/settings

Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Kerry Sheh <shekairui at gmail.com>
Gerrit-Reviewer: Kerry Sheh <shekairui at gmail.com>
Gerrit-Reviewer: Wolfgang Kamp <wmkamp at datakamp.de>
Gerrit-Reviewer: build bot (Jenkins)



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From marcj303 at gmail.com  Fri Jan 20 18:46:20 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Fri, 20 Jan 2012 10:46:20 -0700
Subject: [coreboot] Change in coreboot[master]: Inagua: Synchronize
 AMD/inagua mainboard.
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DC73DDD02@DATAKAMPONE.datakamp2008.local>
References: <gerrit.1326872167479.Ia038e5a2b9550fe81bb075f31e30b98354758e9e@review.coreboot.org>
	<4738C8CE0A30FF47AACA9C624746E3E20DC73DDD02@DATAKAMPONE.datakamp2008.local>
Message-ID: <CALrs_3hmDvY1D8dxJcn-NRm07yDeBC8shZTOZ9t1Z1SyX-fCeQ@mail.gmail.com>

On Fri, Jan 20, 2012 at 9:45 AM, Wolfgang Kamp - datakamp
<wmkamp at datakamp.de> wrote:
> Hello Marc,
>
> I reviewed the code and it looks good.
> But real testing shows an issue with soft restart (UBUNTU).
> The southbridge seems to hang. Coreboot stops because it could not read the SPI ROM of DIMM Module.
> Please see logs.
> The cold start log also reports errors but will successful boot Ubuntu.
>
> Regards
>
> Wolfgang
>

Woflgang,

The ASSERTs in the passing case are non-critical failures for early
heap use. These are AGESA bugs and have been reported to AMD, but they
are not critical.

As you said, The bad failure is this one:

EventLog:	EventClass = 7, EventInfo = 4011c00.
	Param1 = 0, Param2 = 0.
	Param3 = 0, Param4 = 0.

Which is the SPD problem...
#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs
have been found

Can you check what happens in AmdMemoryReadSPD(), in dimmSpd.c? Does
it check the correct dimm address? Is the i2c io address set
correctly?

Thanks,
Marc





>
>
> -----Urspr?ngliche Nachricht-----
> Von: gerrit code review [mailto:gerrit at coreboot.org]
> Gesendet: Freitag, 20. Januar 2012 00:52
> An: Wolfgang Kamp - datakamp
> Cc: Kerry Sheh
> Betreff: Change in coreboot[master]: Inagua: Synchronize AMD/inagua mainboard.
>
> From Marc Jones <marcj303 at gmail.com>:
>
> Hello Wolfgang Kamp,
>
> I'd like you to do a code review. ?Please visit
>
> ? ?http://review.coreboot.org/542
>
> to review the following change.
>
> Change subject: Inagua: Synchronize AMD/inagua mainboard.
> .....................................................................
>
> Inagua: Synchronize AMD/inagua mainboard.
>
> AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
> Persimmom update a lot in the last few month, sync these modification to inagua.
>
> Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
> Signed-off-by: Kerry Sheh <shekairui at gmail.com>
> Signed-off-by: Kerry Sheh <kerry.she at amd.com>
> ---
> M src/mainboard/amd/inagua/BiosCallOuts.c
> M src/mainboard/amd/inagua/BiosCallOuts.h
> M src/mainboard/amd/inagua/Kconfig
> M src/mainboard/amd/inagua/Makefile.inc
> M src/mainboard/amd/inagua/OptionsIds.h
> M src/mainboard/amd/inagua/PlatformGnbPcie.c
> D src/mainboard/amd/inagua/acpi/ssdt2.asl
> D src/mainboard/amd/inagua/acpi/ssdt3.asl
> D src/mainboard/amd/inagua/acpi/ssdt4.asl
> D src/mainboard/amd/inagua/acpi/ssdt5.asl
> M src/mainboard/amd/inagua/acpi_tables.c
> M src/mainboard/amd/inagua/agesawrapper.c
> M src/mainboard/amd/inagua/agesawrapper.h
> M src/mainboard/amd/inagua/buildOpts.c
> M src/mainboard/amd/inagua/devicetree.cb
> M src/mainboard/amd/inagua/dimmSpd.c
> M src/mainboard/amd/inagua/dsdt.asl
> M src/mainboard/amd/inagua/fadt.c
> M src/mainboard/amd/inagua/get_bus_conf.c
> M src/mainboard/amd/inagua/irq_tables.c
> M src/mainboard/amd/inagua/mainboard.c
> M src/mainboard/amd/inagua/mptable.c
> M src/mainboard/amd/inagua/platform_cfg.h
> M src/mainboard/amd/inagua/romstage.c
> 24 files changed, 249 insertions(+), 717 deletions(-)
>
>
> ?git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/542/2
> --
> To view, visit http://review.coreboot.org/542
> To unsubscribe, visit http://review.coreboot.org/settings
>
> Gerrit-MessageType: newchange
> Gerrit-Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
> Gerrit-PatchSet: 2
> Gerrit-Project: coreboot
> Gerrit-Branch: master
> Gerrit-Owner: Kerry Sheh <shekairui at gmail.com>
> Gerrit-Reviewer: Kerry Sheh <shekairui at gmail.com>
> Gerrit-Reviewer: Wolfgang Kamp <wmkamp at datakamp.de>
> Gerrit-Reviewer: build bot (Jenkins)
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



-- 
http://se-eng.com


From gerrit at coreboot.org  Sat Jan 21 11:05:20 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 21 Jan 2012 11:05:20 +0100
Subject: [coreboot] New patch to review for coreboot: 956045c adm1026:
	removed prototype
References: <I13a648acf7bae30635e0469e301ce5635d9d7a8c+0@gerrit.coreboot.org>
Message-ID: <I13a648acf7bae30635e0469e301ce5635d9d7a8c+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/570

-gerrit

commit 956045c67dc71e493f76ada4586bd1145fdad572
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 21 15:32:59 2012 +0530

    adm1026: removed prototype
    
    Removed the prototype and restructured the code
    
    Change-Id: I13a648acf7bae30635e0469e301ce5635d9d7a8c
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/drivers/i2c/adm1026/adm1026.c |   24 +++++++++++-------------
 1 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/src/drivers/i2c/adm1026/adm1026.c b/src/drivers/i2c/adm1026/adm1026.c
index 1aaae52..5b06629 100644
--- a/src/drivers/i2c/adm1026/adm1026.c
+++ b/src/drivers/i2c/adm1026/adm1026.c
@@ -20,19 +20,6 @@
 #define ADM1026_REG_CONFIG2 0x01
 #define ADM1026_REG_CONFIG3 0x07
 
-static void adm1026_enable_monitoring(device_t dev);
-
-static void adm1026_init(device_t dev)
-{
-	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
-		if (ops_smbus_bus(get_pbus_smbus(dev))) {
-			if (dev->bus->dev->path.type == DEVICE_PATH_I2C)
-				smbus_set_link(dev);	// it is under mux
-			adm1026_enable_monitoring(dev);
-		}
-	}
-}
-
 static void adm1026_enable_monitoring(device_t dev)
 {
 	int result;
@@ -47,6 +34,17 @@ static void adm1026_enable_monitoring(device_t dev)
 	}
 }
 
+static void adm1026_init(device_t dev)
+{
+	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
+		if (ops_smbus_bus(get_pbus_smbus(dev))) {
+			if (dev->bus->dev->path.type == DEVICE_PATH_I2C)
+				smbus_set_link(dev);	// it is under mux
+			adm1026_enable_monitoring(dev);
+		}
+	}
+}
+
 static void adm1026_noop(device_t dummy)
 {
 }


From gerrit at coreboot.org  Sat Jan 21 15:51:33 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sat, 21 Jan 2012 15:51:33 +0100
Subject: [coreboot] New patch to review for coreboot: 3041699 trivial:
	spelling fixes in comments
References: <Iad3d18eee3f498171cb766589aaebefdcf0e9767+0@gerrit.coreboot.org>
Message-ID: <Iad3d18eee3f498171cb766589aaebefdcf0e9767+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/571

-gerrit

commit 304169969441824b721b1029f864008a761d80a3
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 21 20:19:14 2012 +0530

    trivial: spelling fixes in comments
    
    Few spelling fixes in entry16.inc
    
    Change-Id: Iad3d18eee3f498171cb766589aaebefdcf0e9767
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/16bit/entry16.inc |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index fb21155..0fa8c11 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -70,7 +70,7 @@ _start:
 	 *
 	 * This means that anything except cs:ip relative offsets are
 	 * a real pain in 16 bit mode.  And explains why it is almost
-	 * imposible to get gas to do lgdt correctly.
+	 * impossible to get gas to do lgdt correctly.
 	 *
 	 * One way to work around this is to have the linker do the
 	 * math instead of the assembler.  This solves the very
@@ -94,7 +94,7 @@ _start:
 	 * The restrictions in reset16.inc mean that _start initially
 	 * must be loaded at or above 0xffff0000 or below 0x100000.
 	 *
-	 * The linker scripts computs gdtptr16_offset by simply returning
+	 * The linker scripts computes gdtptr16_offset by simply returning
 	 * the low 16 bits.  This means that the intial segment used
 	 * when start is called must be 64K aligned.  This should not
 	 * restrict the address as the ip address can be anything.


From gerrit at coreboot.org  Sat Jan 21 18:48:04 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 21 Jan 2012 18:48:04 +0100
Subject: [coreboot] Patch merged into coreboot/master: 956045c adm1026:
	removed prototype
References: <I13a648acf7bae30635e0469e301ce5635d9d7a8c+0@gerrit.coreboot.org>
Message-ID: <E1Rof2q-0004E2-Dz@ra.coresystems.de>

the following patch was just integrated into master:
commit 956045c67dc71e493f76ada4586bd1145fdad572
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 21 15:32:59 2012 +0530

    adm1026: removed prototype
    
    Removed the prototype and restructured the code
    
    Change-Id: I13a648acf7bae30635e0469e301ce5635d9d7a8c
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>

Build-Tested: build bot (Jenkins) at Sat Jan 21 11:28:42 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sat Jan 21 18:48:02 2012, giving +2
See http://review.coreboot.org/570 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan 21 18:49:01 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 21 Jan 2012 18:49:01 +0100
Subject: [coreboot] Patch merged into coreboot/master: 3041699 trivial:
	spelling fixes in comments
References: <Iad3d18eee3f498171cb766589aaebefdcf0e9767+0@gerrit.coreboot.org>
Message-ID: <E1Rof3l-0004Si-Tf@ra.coresystems.de>

the following patch was just integrated into master:
commit 304169969441824b721b1029f864008a761d80a3
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Sat Jan 21 20:19:14 2012 +0530

    trivial: spelling fixes in comments
    
    Few spelling fixes in entry16.inc
    
    Change-Id: Iad3d18eee3f498171cb766589aaebefdcf0e9767
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>

Build-Tested: build bot (Jenkins) at Sat Jan 21 16:04:09 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Sat Jan 21 18:48:47 2012, giving +2
See http://review.coreboot.org/571 for details.

-gerrit


From gerrit at coreboot.org  Sat Jan 21 19:35:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Sat, 21 Jan 2012 19:35:53 +0100
Subject: [coreboot] Patch set updated for coreboot: 7a36e53 Move SeaBIOS
	output out of coreboot source tree
References: <I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec+0@gerrit.coreboot.org>
Message-ID: <I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/552

-gerrit

commit 7a36e53735757b71befbeba7452666d1754e2463
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Sat Jan 21 10:34:22 2012 -0800

    Move SeaBIOS output out of coreboot source tree
    
    Make sure SeaBIOS build files live under $(OUT) instead of
    in the source tree.
    
    Change-Id: I7d357773e32bc25ba7e7eae3fb6ddc31feb413ec
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 payloads/external/SeaBIOS/Makefile.inc |   34 ++++++++++++++++----------------
 src/Kconfig                            |    2 +-
 src/arch/x86/Makefile.inc              |    4 ++-
 3 files changed, 21 insertions(+), 19 deletions(-)

diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc
index 99d402c..7d0d6fc 100644
--- a/payloads/external/SeaBIOS/Makefile.inc
+++ b/payloads/external/SeaBIOS/Makefile.inc
@@ -7,39 +7,39 @@ unexport KCONFIG_AUTOCONFIG
 
 all: build
 
-seabios:
+$(OUT)/seabios:
 	echo "    Cloning SeaBIOS from Git"
-	git clone git://git.seabios.org/seabios.git
+	git clone git://git.seabios.org/seabios.git $(OUT)/seabios
 
-fetch: seabios
-	cd seabios; git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
+fetch: $(OUT)/seabios
+	cd $(OUT)/seabios; git show $(TAG-y) >/dev/null 2>&1 ;	if [ $$? -ne 0 ]; \
 	then echo "    Fetching new commits from the SeaBIOS git repo"; git fetch; fi
 
 checkout: fetch
 	echo "    Checking out SeaBIOS revision $(TAG-y)"
-	cd seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
+	cd $(OUT)/seabios; git checkout master; git branch -D coreboot 2>/dev/null; git checkout -b coreboot $(TAG-y)
 
 config: checkout
 	echo "    CONFIG     SeaBIOS $(TAG-y)"
-	$(MAKE) -C seabios defconfig
-	echo "CONFIG_COREBOOT=y" >> seabios/.config
-	echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config
-	echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> seabios/.config
-	echo "CONFIG_COREBOOT_FLASH=y" >> seabios/.config
-	echo "CONFIG_LZMA=y" >> seabios/.config
-	echo "CONFIG_FLASH_FLOPPY=y" >> seabios/.config
-	echo "CONFIG_VGAHOOKS=y" >> seabios/.config
+	$(MAKE) -C $(OUT)/seabios defconfig OUT=$(OUT)/seabios/out/
+	echo "CONFIG_COREBOOT=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_DEBUG_SERIAL=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_DEBUG_SERIAL_PORT=0x3f8" >> $(OUT)/seabios/.config
+	echo "CONFIG_COREBOOT_FLASH=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_LZMA=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config
+	echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config
 	# This shows how to force a previously set .config option *off*
-	#echo "# CONFIG_SMBIOS is not set" >> seabios/.config
+	#echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config
 
 build: config
 	echo "    MAKE       SeaBIOS $(TAG-y)"
-	$(MAKE) -C seabios
+	$(MAKE) -C $(OUT)/seabios OUT=$(OUT)/seabios/out/
 
 clean:
-	test -d seabios && $(MAKE) -C seabios clean || exit 0
+	test -d $(OUT)/seabios && $(MAKE) -C $(OUT)/seabios clean OUT=$(OUT)/seabios/out/ || exit 0
 
 distclean:
-	rm -rf seabios
+	rm -rf $(OUT)/seabios
 
 .PHONY: checkout config build clean distclean clone fetch
diff --git a/src/Kconfig b/src/Kconfig
index 64c359e..c165d93 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -444,7 +444,7 @@ config PAYLOAD_FILE
 
 config PAYLOAD_FILE
 	depends on PAYLOAD_SEABIOS
-	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+	default "$(obj)/seabios/out/bios.bin.elf"
 
 config PAYLOAD_FILE
 	depends on PAYLOAD_FILO
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cbe38dd..c9cbb01 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -380,7 +380,9 @@ seabios:
 			CC="$(CC)" LD="$(LD)" OBJDUMP="$(OBJDUMP)" \
 			OBJCOPY="$(OBJCOPY)" STRIP="$(STRIP)" \
 			CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \
-			CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE)
+			CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \
+			OUT=$(abspath $(obj))
+
 filo:
 	$(MAKE) -C payloads/external/FILO -f Makefile.inc \
 			HOSTCC="$(HOSTCC)" \


From gerrit at coreboot.org  Sun Jan 22 21:17:28 2012
From: gerrit at coreboot.org (Vikram Narayanan (vikram186@gmail.com))
Date: Sun, 22 Jan 2012 21:17:28 +0100
Subject: [coreboot] New patch to review for coreboot: 392ad13 post code:
	Replaced hard-coded post code with macro
References: <I27cb27827272584a8a17a41c111e2dc155196a97+0@gerrit.coreboot.org>
Message-ID: <I27cb27827272584a8a17a41c111e2dc155196a97+1@gerrit.coreboot.org>

Vikram Narayanan (vikram186 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/572

-gerrit

commit 392ad135233600c2cecfd91cebeb9d1fa831efab
Author: Vikram Narayanan <vikram186 at gmail.com>
Date:   Mon Jan 23 01:44:44 2012 +0530

    post code: Replaced hard-coded post code with macro
    
    Added a macro in the post code list, which replaces hard coded
    value in cpu/x86/cache/cache.c
    
    Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97
    Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
---
 src/cpu/x86/cache/cache.c        |    3 +--
 src/include/console/post_codes.h |    7 +++++++
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
index a7cba4a..1df9e08 100644
--- a/src/cpu/x86/cache/cache.c
+++ b/src/cpu/x86/cache/cache.c
@@ -3,8 +3,7 @@
 
 void x86_enable_cache(void)
 {
-	post_code(0x60);
+	post_code(POST_ENABLING_CACHE);
 	printk(BIOS_INFO, "Enabling cache\n");
 	enable_cache();
 }
-
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index a72da69..1d12e5a 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -106,6 +106,13 @@
 #define POST_CONSOLE_BOOT_MSG			0x40
 
 /**
+ * \brief Before enabling the cache
+ *
+ * Going to enable the cache
+ */
+#define POST_ENABLING_CACHE			0x60
+
+/**
  * \brief Devices have been enumerated
  *
  * Bus scan, and device enumeration has completed.


From gerrit at coreboot.org  Fri Jan 20 06:44:33 2012
From: gerrit at coreboot.org (Kerry Sheh (shekairui@gmail.com))
Date: Fri, 20 Jan 2012 06:44:33 +0100
Subject: [coreboot] New patch to review for coreboot: 30a4932 AGESA F15: AMD
	family15 AGESA code
References: <If79392c104ace25f7e01db794fa205f47746bcad+0@gerrit.coreboot.org>
Message-ID: <If79392c104ace25f7e01db794fa205f47746bcad+1@gerrit.coreboot.org>

Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/554

-gerrit

commit 30a493289ad120f0556c7b8d167e9a09470d1929
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:57:48 2012 +0800

    AGESA F15: AMD family15 AGESA code
    
    AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
    AMD C32, G34, and AM3r2 Sockets are supported.
    
    Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/agesa/Makefile.inc              |    1 +
 src/vendorcode/amd/agesa/f15/AGESA.h               | 3566 ++++++++++++++++++
 src/vendorcode/amd/agesa/f15/AMD.h                 |  480 +++
 src/vendorcode/amd/agesa/f15/Dispatcher.h          |   52 +
 src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h |  167 +
 .../amd/agesa/f15/Include/CommonReturns.h          |  125 +
 src/vendorcode/amd/agesa/f15/Include/Filecode.h    | 1174 ++++++
 .../amd/agesa/f15/Include/GeneralServices.h        |  202 ++
 .../amd/agesa/f15/Include/GnbInterface.h           |  100 +
 .../amd/agesa/f15/Include/GnbInterfaceStub.h       |  301 ++
 src/vendorcode/amd/agesa/f15/Include/GnbPage.h     | 1972 ++++++++++
 src/vendorcode/amd/agesa/f15/Include/Ids.h         | 1178 ++++++
 src/vendorcode/amd/agesa/f15/Include/IdsHt.h       |  124 +
 .../amd/agesa/f15/Include/MaranelloInstall.h       |  116 +
 .../amd/agesa/f15/Include/OptionApmInstall.h       |   87 +
 .../amd/agesa/f15/Include/OptionC6Install.h        |  164 +
 .../amd/agesa/f15/Include/OptionCpbInstall.h       |  170 +
 .../f15/Include/OptionCpuCacheFlushOnHaltInstall.h |  126 +
 .../f15/Include/OptionCpuCoreLevelingInstall.h     |  120 +
 .../agesa/f15/Include/OptionCpuFamiliesInstall.h   |  407 +++
 .../agesa/f15/Include/OptionCpuFeaturesInstall.h   |   80 +
 src/vendorcode/amd/agesa/f15/Include/OptionDmi.h   |   90 +
 .../amd/agesa/f15/Include/OptionDmiInstall.h       |  215 ++
 .../amd/agesa/f15/Include/OptionFamily10hInstall.h | 2058 +++++++++++
 .../agesa/f15/Include/OptionFamily15hEarlySample.h |  231 ++
 .../amd/agesa/f15/Include/OptionFamily15hInstall.h | 1570 ++++++++
 .../amd/agesa/f15/Include/OptionFchInstall.h       |  988 +++++
 .../amd/agesa/f15/Include/OptionGfxRecovery.h      |   82 +
 .../agesa/f15/Include/OptionGfxRecoveryInstall.h   |   54 +
 src/vendorcode/amd/agesa/f15/Include/OptionGnb.h   |  109 +
 .../amd/agesa/f15/Include/OptionGnbInstall.h       |  591 +++
 .../amd/agesa/f15/Include/OptionHtInstall.h        |  319 ++
 .../amd/agesa/f15/Include/OptionHwC1eInstall.h     |   81 +
 .../amd/agesa/f15/Include/OptionIdsInstall.h       |  588 +++
 .../amd/agesa/f15/Include/OptionIoCstateInstall.h  |  133 +
 .../agesa/f15/Include/OptionL3FeaturesInstall.h    |  119 +
 .../agesa/f15/Include/OptionLowPwrPstateInstall.h  |   89 +
 .../amd/agesa/f15/Include/OptionMemory.h           |  358 ++
 .../amd/agesa/f15/Include/OptionMemoryInstall.h    | 3778 ++++++++++++++++++++
 .../amd/agesa/f15/Include/OptionMemoryRecovery.h   |   63 +
 .../f15/Include/OptionMemoryRecoveryInstall.h      |  263 ++
 .../agesa/f15/Include/OptionMsgBasedC1eInstall.h   |  116 +
 .../amd/agesa/f15/Include/OptionMultiSocket.h      |  214 ++
 .../agesa/f15/Include/OptionMultiSocketInstall.h   |  105 +
 .../f15/Include/OptionPreserveMailboxInstall.h     |  123 +
 .../amd/agesa/f15/Include/OptionPstate.h           |  116 +
 .../agesa/f15/Include/OptionPstateHpcModeInstall.h |   88 +
 .../amd/agesa/f15/Include/OptionPstateInstall.h    |  264 ++
 .../amd/agesa/f15/Include/OptionS3ScriptInstall.h  |   92 +
 src/vendorcode/amd/agesa/f15/Include/OptionSlit.h  |   97 +
 .../amd/agesa/f15/Include/OptionSlitInstall.h      |   80 +
 src/vendorcode/amd/agesa/f15/Include/OptionSrat.h  |   83 +
 .../amd/agesa/f15/Include/OptionSratInstall.h      |   74 +
 .../amd/agesa/f15/Include/OptionSwC1eInstall.h     |   81 +
 src/vendorcode/amd/agesa/f15/Include/OptionWhea.h  |   84 +
 .../amd/agesa/f15/Include/OptionWheaInstall.h      |   75 +
 src/vendorcode/amd/agesa/f15/Include/Options.h     |   98 +
 src/vendorcode/amd/agesa/f15/Include/OptionsHt.h   |  110 +
 src/vendorcode/amd/agesa/f15/Include/OptionsPage.h |  378 ++
 .../amd/agesa/f15/Include/PlatformInstall.h        | 2837 +++++++++++++++
 .../f15/Include/PlatformMemoryConfiguration.h      |  499 +++
 .../amd/agesa/f15/Include/SanMarinoInstall.h       |  116 +
 .../amd/agesa/f15/Include/ScorpiusInstall.h        |  115 +
 src/vendorcode/amd/agesa/f15/Include/Topology.h    |  163 +
 src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h  |  628 ++++
 .../f15/Legacy/PlatformMemoryConfiguration.inc     |  670 ++++
 .../amd/agesa/f15/Legacy/Proc/Dispatcher.c         |  159 +
 .../amd/agesa/f15/Legacy/Proc/agesaCallouts.c      |  441 +++
 .../amd/agesa/f15/Legacy/Proc/arch2008.asm         | 2676 ++++++++++++++
 .../amd/agesa/f15/Legacy/Proc/hobTransfer.c        |  393 ++
 src/vendorcode/amd/agesa/f15/Legacy/agesa.inc      | 2989 ++++++++++++++++
 src/vendorcode/amd/agesa/f15/Legacy/amd.inc        |  462 +++
 src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc   |  577 +++
 src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm |  671 ++++
 src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm |  110 +
 src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm |   84 +
 src/vendorcode/amd/agesa/f15/Lib/amdlib.c          | 1355 +++++++
 src/vendorcode/amd/agesa/f15/Lib/amdlib.h          |  403 +++
 src/vendorcode/amd/agesa/f15/Lib/helper.c          |   68 +
 src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm  |  591 +++
 src/vendorcode/amd/agesa/f15/MainPage.h            |  120 +
 src/vendorcode/amd/agesa/f15/Makefile.inc          |  532 +++
 src/vendorcode/amd/agesa/f15/Porting.h             |  289 ++
 .../f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c   |  126 +
 .../agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c   |  300 ++
 .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c   | 1537 ++++++++
 .../f15/Proc/CPU/Family/0x10/F10PackageType.h      |   84 +
 .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c  |  176 +
 .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h  |   78 +
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c    |  243 ++
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h    |   78 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c   |  296 ++
 .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h   |   77 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c   |  185 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h   |   77 +
 .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c  | 2251 ++++++++++++
 .../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c    |  151 +
 .../Family/0x10/RevC/BL/F10BlEquivalenceTable.c    |  106 +
 .../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c     |  122 +
 .../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c |  106 +
 .../0x10/RevC/BL/F10BlMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c  |  106 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c  |  196 +
 .../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c    |  144 +
 .../Family/0x10/RevC/DA/F10DaEquivalenceTable.c    |  107 +
 .../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c     |  283 ++
 .../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c |  107 +
 .../0x10/RevC/DA/F10DaMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c  |  106 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c  |  192 +
 .../Family/0x10/RevC/F10MicrocodePatch01000085.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c6.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c7.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c8.c   | 1037 ++++++
 .../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c |  439 +++
 .../f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c   |  205 ++
 .../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c   |  133 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c   |  265 ++
 .../f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c   |  181 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c   |  495 +++
 .../Family/0x10/RevC/RB/F10RbEquivalenceTable.c    |  110 +
 .../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c     |  120 +
 .../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c |  114 +
 .../0x10/RevC/RB/F10RbMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c  |  120 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c  |  234 ++
 .../Family/0x10/RevD/F10MicrocodePatch010000c5.c   | 1039 ++++++
 .../Family/0x10/RevD/F10MicrocodePatch010000d9.c   | 1066 ++++++
 .../f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm    |  113 +
 .../f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm    |  127 +
 .../Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c  |  516 +++
 .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c |  282 ++
 .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c   |  455 +++
 .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c    |  114 +
 .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c     | 1294 +++++++
 .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c  |  144 +
 .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c |  116 +
 .../0x10/RevD/HY/F10HyMicrocodePatchTables.c       |  114 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c  |  137 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c  |  384 ++
 .../Family/0x10/RevE/F10MicrocodePatch010000bf.c   | 1039 ++++++
 .../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c |  373 ++
 .../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c   |  134 +
 .../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c   |  225 ++
 .../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c   |  396 ++
 .../Family/0x10/RevE/PH/F10PhEquivalenceTable.c    |  105 +
 .../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c     |  117 +
 .../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c |   96 +
 .../0x10/RevE/PH/F10PhMicrocodePatchTables.c       |  105 +
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c   |  329 ++
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h   |  120 +
 .../agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c |  160 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c    |  335 ++
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c   |  136 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c    |  135 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c |  179 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c    |  127 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c   |  128 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c   |  142 +
 .../f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c |  131 +
 .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c  |  167 +
 .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c |  169 +
 .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c |  519 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c     |  454 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h     |   79 +
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c   |  393 ++
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h   |  195 +
 .../f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c   |  751 ++++
 .../f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c     |  289 ++
 .../f15/Proc/CPU/Family/0x10/cpuF10PciTables.c     |  772 ++++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c    |  411 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h    |   83 +
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h     |  547 +++
 .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c  |  182 +
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c    |  485 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h    |   77 +
 .../agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c  |  894 +++++
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c   |  124 +
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h   |   79 +
 .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.c     | 1176 ++++++
 .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.h     |  206 ++
 .../CPU/Family/0x10/cpuF10WheaInitDataTables.c     |  128 +
 .../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c  |  184 +
 .../f15/Proc/CPU/Family/0x15/F15PackageType.h      |   79 +
 .../f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c    |  208 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c     |  186 +
 .../agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c   |  183 +
 .../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c    |  834 +++++
 .../CPU/Family/0x15/OR/F15OrEquivalenceTable.c     |  135 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c |  833 +++++
 .../Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c  |  187 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c    |  377 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c  |  549 +++
 .../Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c |  120 +
 .../Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c    |  234 ++
 .../Family/0x15/OR/F15OrMicrocodePatch06000425.c   | 2674 ++++++++++++++
 .../0x15/OR/F15OrMicrocodePatch0600050D_Enc.c      | 2675 ++++++++++++++
 .../0x15/OR/F15OrMicrocodePatch06000624_Enc.c      | 2701 ++++++++++++++
 .../CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c |  112 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c |  305 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c   |  234 ++
 .../CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c   |  749 ++++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c   |  962 +++++
 .../Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c  |  317 ++
 .../Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h  |   77 +
 .../Family/0x15/OR/F15OrPowerMgmtSystemTables.c    |  177 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c  |  236 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h  |   77 +
 .../Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c  |  376 ++
 .../CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c  |  321 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c   |  939 +++++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h   |  169 +
 .../CPU/Family/0x15/OR/F15OrWorkaroundsTable.c     |  134 +
 .../CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c  |  184 +
 .../CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c    |  250 ++
 .../CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h    |   79 +
 .../f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c      |  419 +++
 .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c   |  422 +++
 .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h   |  211 ++
 .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c |  349 ++
 .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h |   79 +
 .../Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h    |  534 +++
 .../f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c   |  920 +++++
 .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c   |  128 +
 .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h   |   79 +
 .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.c   |  181 +
 .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.h   |   92 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c |  126 +
 .../agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c |  223 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c |  198 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c |  124 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h |   77 +
 .../f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c     |  136 +
 .../f15/Proc/CPU/Family/0x15/cpuF15PciTables.c     |  206 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c    |  441 +++
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h    |   82 +
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h     |  293 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15Utilities.c     | 1178 ++++++
 .../f15/Proc/CPU/Family/0x15/cpuF15Utilities.h     |  160 +
 .../CPU/Family/0x15/cpuF15WheaInitDataTables.c     |  128 +
 .../agesa/f15/Proc/CPU/Family/cpuFamRegisters.h    |  259 ++
 .../agesa/f15/Proc/CPU/Feature/PreserveMailbox.c   |  219 ++
 .../agesa/f15/Proc/CPU/Feature/PreserveMailbox.h   |   98 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuApm.c        |  205 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuApm.h        |  130 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c    |  261 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h    |  157 +
 .../f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c     |  200 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c  |  752 ++++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h  |  139 +
 .../agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c   |  363 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c        |  176 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h        |  134 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c        |  862 +++++
 .../f15/Proc/CPU/Feature/cpuFeatureLeveling.c      |  266 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.c   |  199 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h   |  269 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c      |  181 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h      |  126 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c   |  208 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h   |  284 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c |  350 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h |  361 ++
 .../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c   |  224 ++
 .../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h   |  130 +
 .../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c    |  212 ++
 .../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h    |  128 +
 .../agesa/f15/Proc/CPU/Feature/cpuPstateGather.c   |  411 +++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c  |  221 ++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h  |  101 +
 .../agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c | 1099 ++++++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateTables.c   |  891 +++++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateTables.h   |  331 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c       |  397 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c       |  617 ++++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c      |  178 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h      |  120 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c       |  284 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c         | 1233 +++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/S3.h         |  395 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c      | 1734 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h      | 1296 +++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm   |  362 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c     |  306 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm |  174 +
 .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c      | 1443 ++++++++
 .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.h      |  304 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c    |  172 +
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c |  313 ++
 .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.c          |  411 +++
 .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.h          |  305 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h |   74 +
 .../amd/agesa/f15/Proc/CPU/cpuEventLog.c           |  397 ++
 .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c  |  484 +++
 .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h  | 1008 ++++++
 .../amd/agesa/f15/Proc/CPU/cpuGeneralServices.c    | 1237 +++++++
 .../amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c     |  125 +
 .../amd/agesa/f15/Proc/CPU/cpuLateInit.c           |  394 ++
 .../amd/agesa/f15/Proc/CPU/cpuLateInit.h           |  888 +++++
 .../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c     |  420 +++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPage.h    |   62 +
 .../amd/agesa/f15/Proc/CPU/cpuPostInit.c           |  493 +++
 .../amd/agesa/f15/Proc/CPU/cpuPostInit.h           |  239 ++
 .../amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c          |  252 ++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c   |  570 +++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.h   |  127 +
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c  |  325 ++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.h  |  128 +
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h  |   93 +
 .../amd/agesa/f15/Proc/CPU/cpuRegisters.h          |  407 +++
 .../amd/agesa/f15/Proc/CPU/cpuServices.h           |  334 ++
 .../amd/agesa/f15/Proc/CPU/cpuWarmReset.c          |  235 ++
 .../amd/agesa/f15/Proc/CPU/heapManager.c           |  885 +++++
 .../amd/agesa/f15/Proc/CPU/heapManager.h           |  243 ++
 src/vendorcode/amd/agesa/f15/Proc/Common/AmdFch.h  |   66 +
 .../amd/agesa/f15/Proc/Common/AmdInitEarly.c       |  316 ++
 .../amd/agesa/f15/Proc/Common/AmdInitEnv.c         |  182 +
 .../amd/agesa/f15/Proc/Common/AmdInitLate.c        |  296 ++
 .../amd/agesa/f15/Proc/Common/AmdInitMid.c         |  170 +
 .../amd/agesa/f15/Proc/Common/AmdInitPost.c        |  341 ++
 .../amd/agesa/f15/Proc/Common/AmdInitRecovery.c    |  169 +
 .../amd/agesa/f15/Proc/Common/AmdInitReset.c       |  253 ++
 .../amd/agesa/f15/Proc/Common/AmdInitResume.c      |  239 ++
 .../amd/agesa/f15/Proc/Common/AmdLateRunApTask.c   |  160 +
 .../amd/agesa/f15/Proc/Common/AmdS3LateRestore.c   |  218 ++
 .../amd/agesa/f15/Proc/Common/AmdS3Save.c          |  388 ++
 .../amd/agesa/f15/Proc/Common/CommonInits.c        |  139 +
 .../amd/agesa/f15/Proc/Common/CommonInits.h        |   66 +
 .../amd/agesa/f15/Proc/Common/CommonPage.h         |  117 +
 .../amd/agesa/f15/Proc/Common/CommonReturns.c      |  213 ++
 .../amd/agesa/f15/Proc/Common/CreateStruct.c       |  314 ++
 .../amd/agesa/f15/Proc/Common/CreateStruct.h       |  196 +
 .../amd/agesa/f15/Proc/Common/S3RestoreState.c     |  442 +++
 .../amd/agesa/f15/Proc/Common/S3SaveState.c        |  652 ++++
 .../amd/agesa/f15/Proc/Common/S3SaveState.h        |  361 ++
 .../agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c    |  163 +
 .../agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.h    |   67 +
 .../amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c        |  485 +++
 .../agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c |  121 +
 .../agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.h |   58 +
 .../f15/Proc/HT/Fam10/htNbOptimizationFam10.c      |  222 ++
 .../f15/Proc/HT/Fam10/htNbOptimizationFam10.h      |   74 +
 .../amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c  |  402 +++
 .../amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.h  |   91 +
 .../agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c   |  445 +++
 .../agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.h   |  129 +
 .../agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c    |  162 +
 .../agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.h    |   67 +
 .../amd/agesa/f15/Proc/HT/Fam15/htNbFam15.c        |  248 ++
 .../agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c |  120 +
 .../agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.h |   58 +
 .../f15/Proc/HT/Fam15/htNbOptimizationFam15.c      |  148 +
 .../f15/Proc/HT/Fam15/htNbOptimizationFam15.h      |   63 +
 .../amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c  |  373 ++
 .../amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.h  |   93 +
 .../agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c   |  453 +++
 .../agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.h   |  137 +
 .../f15/Proc/HT/Features/htFeatDynamicDiscovery.c  |  783 ++++
 .../f15/Proc/HT/Features/htFeatDynamicDiscovery.h  |   80 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatGanging.c |  218 ++
 .../amd/agesa/f15/Proc/HT/Features/htFeatGanging.h |   81 +
 .../agesa/f15/Proc/HT/Features/htFeatNoncoherent.c |  375 ++
 .../agesa/f15/Proc/HT/Features/htFeatNoncoherent.h |   81 +
 .../f15/Proc/HT/Features/htFeatOptimization.c      |  890 +++++
 .../f15/Proc/HT/Features/htFeatOptimization.h      |  140 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatRouting.c |  493 +++
 .../amd/agesa/f15/Proc/HT/Features/htFeatRouting.h |   90 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatSets.c    |  135 +
 .../agesa/f15/Proc/HT/Features/htFeatSublinks.c    |  232 ++
 .../agesa/f15/Proc/HT/Features/htFeatSublinks.h    |   80 +
 .../Proc/HT/Features/htFeatTrafficDistribution.c   |  420 +++
 .../Proc/HT/Features/htFeatTrafficDistribution.h   |   79 +
 .../amd/agesa/f15/Proc/HT/Features/htIds.c         |  150 +
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c  |  492 +++
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h  |  178 +
 .../agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c   |  142 +
 .../agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.h   |   62 +
 .../agesa/f15/Proc/HT/NbCommon/htNbOptimization.c  |  258 ++
 .../agesa/f15/Proc/HT/NbCommon/htNbOptimization.h  |   91 +
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c |  335 ++
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.h |  108 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c      |  112 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.h      |  562 +++
 src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h     |  144 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph.c        |  199 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph1.c       |   70 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph2.c       |   71 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph3Line.c   |   76 +
 .../agesa/f15/Proc/HT/htGraph/htGraph3Triangle.c   |   77 +
 .../agesa/f15/Proc/HT/htGraph/htGraph4Degenerate.c |   80 +
 .../f15/Proc/HT/htGraph/htGraph4FullyConnected.c   |   83 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Kite.c   |   81 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Line.c   |   80 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Square.c |   80 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Star.c   |   80 +
 .../f15/Proc/HT/htGraph/htGraph5FullyConnected.c   |   80 +
 .../f15/Proc/HT/htGraph/htGraph5TwistedLadder.c    |   89 +
 .../f15/Proc/HT/htGraph/htGraph6DoubloonLower.c    |   75 +
 .../f15/Proc/HT/htGraph/htGraph6DoubloonUpper.c    |   75 +
 .../f15/Proc/HT/htGraph/htGraph6FullyConnected.c   |   86 +
 .../f15/Proc/HT/htGraph/htGraph6TwinTriangles.c    |   92 +
 .../f15/Proc/HT/htGraph/htGraph6TwistedLadder.c    |   92 +
 .../f15/Proc/HT/htGraph/htGraph7FullyConnected.c   |   78 +
 .../f15/Proc/HT/htGraph/htGraph7TwistedLadder.c    |   95 +
 .../agesa/f15/Proc/HT/htGraph/htGraph8DoubloonM.c  |   76 +
 .../f15/Proc/HT/htGraph/htGraph8FullyConnected.c   |   79 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c |   96 +
 .../Proc/HT/htGraph/htGraph8TwinFullyFourWays.c    |   96 +
 .../f15/Proc/HT/htGraph/htGraph8TwistedLadder.c    |   95 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c |  263 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.h |  490 +++
 .../amd/agesa/f15/Proc/HT/htInterfaceCoherent.c    |  264 ++
 .../amd/agesa/f15/Proc/HT/htInterfaceCoherent.h    |  115 +
 .../amd/agesa/f15/Proc/HT/htInterfaceGeneral.c     |  539 +++
 .../amd/agesa/f15/Proc/HT/htInterfaceGeneral.h     |  162 +
 .../amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c |  394 ++
 .../amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.h |  138 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c      |  579 +++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c        |  248 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNb.h        | 1134 ++++++
 .../amd/agesa/f15/Proc/HT/htNbCommonHardware.h     |  123 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c    |  670 ++++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h    |  298 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htPage.h      |   65 +
 .../amd/agesa/f15/Proc/HT/htTopologies.h           |   72 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h     |  125 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/IdsPage.h    |   58 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/OptionsIds.h |   80 +
 .../amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c     |  593 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c     |  356 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c        |  206 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c        |  260 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c        |  273 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c        |  428 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c        |  577 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c        |  356 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c        |  105 +
 .../amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c        |  106 +
 .../amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c        |  260 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c        |  258 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c    |  146 +
 .../amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c    |  212 ++
 .../amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c    |  356 ++
 .../amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c        |  623 ++++
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c        |  290 ++
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h        |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c        |  178 +
 .../f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c     |  207 ++
 .../agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c  |  549 +++
 .../agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.h  |  108 +
 .../agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c    |  164 +
 .../agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c  |  173 +
 .../amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.h  |   79 +
 .../amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c  |  152 +
 .../amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c    |  244 ++
 .../amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h    |   79 +
 .../f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c      |  175 +
 .../f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h      |   78 +
 .../amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c    |  170 +
 .../amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h    |   80 +
 .../f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c  |  289 ++
 .../f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c  |   86 +
 .../amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c          |  719 ++++
 .../amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c      |  398 ++
 .../amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c    |  380 ++
 .../amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c      |  382 ++
 .../amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c      |  376 ++
 .../amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c      |  380 ++
 .../amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c      |  423 +++
 .../amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c      |  382 ++
 .../amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c      |  382 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c  |  147 +
 .../amd/agesa/f15/Proc/Mem/Main/merrhdl.c          |  188 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c |  138 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c    |  253 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c |  696 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c |  136 +
 .../amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c    |  245 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c         |  292 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.h         |   86 +
 .../amd/agesa/f15/Proc/Mem/Main/mmMemClr.c         |  119 +
 .../amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c     |  607 ++++
 .../amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c |  147 +
 .../amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c    |  166 +
 .../agesa/f15/Proc/Mem/Main/mmParallelTraining.c   |  289 ++
 .../agesa/f15/Proc/Mem/Main/mmStandardTraining.c   |  241 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c       |  246 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmflow.c           |  395 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm  |  497 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.c    |  256 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c   |  721 ++++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c  |  228 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c        |  746 ++++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.h        |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c          |  493 +++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h          |  212 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c       |  454 +++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c      |  135 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c  |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c       |  214 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c        |  246 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c       |  222 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnprotoc32.c     |   66 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c       |  636 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c    |  225 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c          |  747 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.h          |   84 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c |  498 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h |  209 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c         |  468 +++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c        |  139 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c         |  208 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c          |  200 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c       |   86 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c         |  584 +++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c    |  225 ++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c          |  715 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c         |  514 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c |  491 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.h |  198 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c         |  194 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c          |  199 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c       |  169 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c         |  554 +++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c    |  228 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c          |  746 ++++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c         |  456 +++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c        |  134 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c |  496 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h |  212 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c         |  213 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c          |  247 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c         |  238 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c       |   66 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c         |  639 ++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h          |   85 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c         |  975 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c        |  134 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c    |  218 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c         |  340 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c |  640 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h |  361 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c          |  280 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c    |  219 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c         |  849 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c       |   99 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c         |  922 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c          | 1257 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c |  503 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h |  129 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c          |  775 ++++
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c    |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c         |  177 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c |  503 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h |  124 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c          |  775 ++++
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c    |  141 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c      |  530 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c    | 1356 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c   | 3453 ++++++++++++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c  | 1737 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c  |  333 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c   | 1286 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c   | 2041 +++++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c   |  551 +++
 .../amd/agesa/f15/Proc/Mem/NB/mntrain2.c           |  132 +
 .../amd/agesa/f15/Proc/Mem/NB/mntrain3.c           |  244 ++
 .../amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c       |  325 ++
 .../amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c       |  204 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c          |  160 +
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c          |  208 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c          |  165 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c          |  204 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c          |  191 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c          |  165 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c          |  160 +
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c          |  324 ++
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c          |  220 ++
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c          |  198 +
 .../amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c     |  223 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpUorA3.c     |  278 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c     |  320 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c     |  653 ++++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c     |  343 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c     |  336 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c     |  743 ++++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c     |  351 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c           |  228 ++
 .../amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c          |  209 ++
 .../amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c          |  209 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c      | 1225 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c |  206 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c |  117 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c |  117 +
 .../amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c          |  303 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c   |  196 +
 .../amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c           |  213 ++
 .../amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c        |  184 +
 .../amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c           |  236 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c   |  270 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c   |  220 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c   |  227 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c |  211 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c         |  233 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h         |  125 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c       |  163 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h       |   89 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c      | 1118 ++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h      |  183 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c         |  236 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h         |  135 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c   | 1448 ++++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.h   |  133 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c       |  168 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h       |   91 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c      |  319 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h      |   88 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c      |  503 +++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h      |   97 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c      | 1191 ++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h      |  177 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c     |  164 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c      |  719 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c    |  263 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c |  125 +
 .../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c    |  916 +++++
 .../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h    |  118 +
 .../amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c         | 1424 ++++++++
 .../amd/agesa/f15/Proc/Mem/Tech/mttecc.c           |  226 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mtthrc.c           |  311 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c  |  624 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c |  259 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c        |  428 +++
 .../amd/agesa/f15/Proc/Mem/Tech/mttsrc.c           |  346 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/ma.h         |  317 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/memPage.h    |   58 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h    |  104 +
 .../amd/agesa/f15/Proc/Mem/mfParallelTraining.h    |  114 +
 .../amd/agesa/f15/Proc/Mem/mfStandardTraining.h    |   82 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h   |   84 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mfs3.h       |  356 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h      |   81 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h         | 1307 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h         | 1743 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mp.h         |  607 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mport.h      |   71 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mt.h         |  510 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h         |  245 ++
 .../amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c  |  103 +
 .../amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h  |   76 +
 .../agesa/f15/Proc/Recovery/HT/htInitRecovery.c    |  168 +
 .../amd/agesa/f15/Proc/Recovery/HT/htInitReset.c   |  332 ++
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c    |  725 ++++
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h    |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c |  161 +
 .../f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c     |   61 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c  |  665 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c   |  164 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c  |  669 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c   |  166 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrndcthy.c   |   75 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c  |  725 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c   |  161 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c |   61 +
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c   |  341 ++
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c   |  145 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c  |  798 +++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h  |  129 +
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c |   61 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c  |  666 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h  |   96 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c  |  665 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h  |   96 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c       |  189 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c    | 1577 ++++++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c    |  296 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c |  158 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c       |  258 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c  |  182 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c  |  110 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c  |  110 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c    |  177 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c |  182 +
 .../agesa/f15/Proc/Recovery/Mem/Ps/mrprc10opspd.c  |   92 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c |  198 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c    |  217 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c    |  187 +
 .../agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c   |  188 +
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c      |  243 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c      |  361 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c      |  325 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h      |  131 +
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c      |  369 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c |  329 ++
 .../f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c  |  315 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c |  114 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c |  437 +++
 .../amd/agesa/f15/Proc/Recovery/Mem/mrdef.c        |  128 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrinit.c       |  125 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrm.c          |  288 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/mrport.h       |   86 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrt3.h         |  120 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mru.asm        |  187 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mru.h          |  140 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mruc.c         |  270 ++
 .../amd/agesa/f15/Proc/Recovery/recoveryPage.h     |   58 +
 src/vendorcode/amd/agesa/f15/cpcar.inc             | 1470 ++++++++
 src/vendorcode/amd/agesa/f15/cpcarmac.inc          |  457 +++
 src/vendorcode/amd/agesa/f15/errno.h               |   38 +
 src/vendorcode/amd/agesa/f15/gcccar.inc            | 1612 +++++++++
 733 files changed, 257251 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
index 5516888..b0e5ddf 100644
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -1,3 +1,4 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h
new file mode 100644
index 0000000..b18659e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/AGESA.h
@@ -0,0 +1,3566 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 60222 $   @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include  "Porting.h"
+#include  "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE              0x00028000
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA                0x00028100
+#define AGESA_DO_RESET                 0x00028101
+#define AGESA_ALLOCATE_BUFFER          0x00028102
+#define AGESA_DEALLOCATE_BUFFER        0x00028103
+#define AGESA_LOCATE_BUFFER            0x00028104
+#define AGESA_RUNFUNC_ONAP             0x00028105
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD                 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
+#define AGESA_READ_SPD_RECOVERY        0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
+#define AGESA_EXTERNAL____TRAIN_VREF_CHANGE     0x00028146
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA       0x00028200
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT          0x00028401
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+//                         HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS              4
+#define HT_WIDTH_2_BITS              2
+#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
+#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE          0x00000000
+#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
+
+#define HT_LIST_TERMINAL             0xFF             ///< End of list.
+#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS             0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS         0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS               0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS           0x10004000
+#define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+//                         HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+  MATCHED,                               ///< The link matches the requested customization.
+                                         ///< When used with IGNORE_LINK,
+                                         ///< this will generally require other software to initialize the link.
+                                         ///< When used with SKIP_REGANG,
+                                         ///< the two unganged links will be available for distribution.
+
+  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
+                                         ///< Power Off is only supported for coherent links.
+                                         ///< Link power off may occur at a warm reset rather than immediately.
+                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+  UNMATCHED,                             ///< The link should be processed according to normal defaults.
+                                         ///< Effectively, the link does not match the requested customization.
+                                         ///< This can be used to exclude links from a following match any.
+
+  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+  IN       UINT8 FromId;                 ///< The device responding to FromId,
+  IN       UINT8 ToId;                   ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed.  BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list.  Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking.  Device orientation can be detected automatically, or
+/// explicitly.  See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
+  IN       UINT8 Link;                         ///< The Link on the host for this chain
+  // Override fields
+  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed.  For Checks, 1 means to check the item
+/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
+  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
+  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
+  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
+  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
+  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
+  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings.  The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+  // Override fields
+  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
+  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
+  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
+  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
+  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
+  // Override fields
+     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
+     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
+     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
+     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+///  Limits for CPU to CPU Links.
+///
+///  For each coherent connection this interface is checked once.
+///  Provide the frequency and width if needed for this Link (usually based on board
+///  restriction).  This is used with CPU device capabilities and northbridge limits
+///  to compute the default settings.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Limit fields
+  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
+  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
+  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+///  Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
+  IN       UINT8 HostLink;                 ///< The Link about to be initialized
+  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
+  // Limit fields
+  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
+  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+///  Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control.  For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
+  IN       UINT8 Link;                   ///< The Link on the host for this chain
+  // Override fields
+  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
+  IN       UINT8 SubBus;                 ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+///  Ignore a Link.
+///
+///  This interface is checked every time a coherent Link is found and then every
+///  time a non-coherent Link from a CPU is found.
+///  Any coherent or non-coherent Link from a CPU can be ignored and not used
+///  for discovery or initialization.  Useful for connection based systems.
+///  (Note: not checked for IO device to IO Device Links.)
+///  (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
+  IN       UINT8 Link;                   ///< The Link about to be initialized
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+///  Skip reganging of subLinks.
+///
+///  This interface is checked whenever two subLinks are both connected to the same CPUs.
+///  Normally, unganged sublinks between the same two CPUs are reganged.
+///  Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+///  The System Socket layout, which sockets are physically connected.
+///
+///  The hardware method for Socket naming is preferred.  Use this software method only
+///  if required.
+
+typedef struct {
+  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
+  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
+  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+  // Basic level customization
+  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
+                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
+                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
+                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM}
+
+  // Advanced Level Customization
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
+                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
+                                                          ///< Use either auto bus numbering or override bus
+                                                          ///< numbers, not both.
+                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
+                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
+                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+  // Expert Level Customization
+  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
+                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+                                                     ///< The hardware socket naming method is preferred,
+                                                     ///<  If it can't be used, this provides a software method.
+                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ *              HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS         0x10005000
+#define HT_EVENT_BB_BUID_EXCEED    0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED  0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH     0x10065000
+
+/*----------------------------------------------------------------------------
+ *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
+                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
+                                   ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+
+//-----------------------------------------------------------------------------
+//                     FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+  SdDisable = 0,                      ///< Disabled
+  SdAmda,                             ///< AMDA,  set 24,18,16,  default
+  SdDma,                              ///< DMA clear 24, 16, set 18
+  SdPio                               ///< PIO clear 24,18,16
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+  Sd50MhzTraceCableLengthWithinSixInches = 4,           ///< 50Mhz, default
+  Sd40MhzTraceCableLengthSix2ElevenInches = 6,          ///< 40Mhz
+  Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7,   ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for AzaliaController
+typedef enum {
+  AzAuto = 0,                         ///< Auto - Detect Azalia controller automatically
+  AzDisable,                          ///< Diable - Disable Azalia controller
+  AzEnable                            ///< Enable - Enable Azalia controller
+} HDA_CONFIG;
+
+/// Configuration values for IrConfig
+typedef enum {
+  IrDisable  = 0,                     ///< Disable
+  IrRxTx0    = 1,                     ///< Rx and Tx0
+  IrRxTx1    = 2,                     ///< Rx and Tx1
+  IrRxTx0Tx1 = 3                      ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+  SataNativeIde = 0,                  ///< Native IDE mode
+  SataRaid,                           ///< RAID mode
+  SataAhci,                           ///< AHCI mode
+  SataLegacyIde,                      ///< Legacy IDE mode
+  SataIde2Ahci,                       ///< IDE->AHCI mode
+  SataAhci7804,                       ///< AHCI mode as 7804 ID (AMD driver)
+  SataIde2Ahci7804                    ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+  PortA4       = 0,                   ///< 4:0:0:0
+  PortA2B2     = 2,                   ///< 2:2:0:0
+  PortA2B1C1   = 3,                   ///< 2:1:1:0
+  PortA1B1C1D1 = 4                    ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+  AlwaysOff   = 0,                    ///< Always power off after power resumes
+  AlwaysOn    = 1,                    ///< Always power on after power resumes
+  UsePrevious = 3,                    ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+  Gen1   = 1,                         ///< SATA port GEN1 speed
+  Gen2   = 2,                         ///< SATA port GEN2 speed
+  Gen3   = 3,                         ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+  Function0   = 0,                    ///< GPIO Function 1
+  Function1   = 1,                    ///< GPIO Function 1
+  Function2   = 2,                    ///< GPIO Function 2
+  Function3   = 3,                    ///< GPIO Function 3
+} GPIO_FUN;
+
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+  OwnedByEc   = 1 << 0,               ///< This bit can only be written by EC
+  OwnedByHost = 1 << 1,               ///< This bit can only be written by host (BIOS)
+  Sticky      = 1 << 2,               ///< If set, [6:3] are sticky
+  PullUpB     = 1 << 3,               ///< 0: Pullup enable; 1: Pullup disabled
+  PullDown    = 1 << 4,               ///< 0: Pulldown disabled; 1: Pulldown enable
+  GpioOutEnB  = 1 << 5,               ///< 0: Output enable; 1: Output disable
+  GpioOut     = 1 << 6,               ///< Output state when GpioOutEnB is 0
+  GpioIn      = 1 << 7,               ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+  IN         UINT8        GpioPin;               ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+  IN         GPIO_FUN     PinFunction;           ///< Multi-function selection
+  IN         CFG_BYTE     CfgByte;               ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+  IN         UINT8        InputPin;              ///< Input Pin, valid range 0-63
+  IN         UINT8        GpeMap;                ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+  IN         BOOLEAN      CommonPhy;             ///< Common PHY or not
+                                      ///<   @li <b>FALSE</b> - Only applied to specified port
+                                      ///<   @li <b>TRUE</b>  - Apply to all SATA ports
+  IN         SATA_SPEED   Gen;                   ///< SATA speed
+  IN         UINT8        Port;                  ///< Port number, valid range: 0-7
+  IN         UINT32       PhyData;               ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       BOOLEAN      Xhci0Enable;         ///< XHCI0 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI0 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI0 controller enabled
+
+  IN       BOOLEAN      Xhci1Enable;         ///< XHCI1 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI1 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+  IN       SD_MODE      SdConfig;            ///< Secure Digital (SD) controller mode
+  IN       HDA_CONFIG   AzaliaController;    ///< Azalia HD Audio Controller
+
+  IN       IR_CONFIG    IrConfig;            ///< Infrared (IR) Configuration
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       SATA_CLASS   SataClass;           ///< SATA controller mode
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      SataIdeMode;         ///< Native mode of SATA IDE controller
+                                             ///<   @li <b>FALSE</b> - Legacy IDE mode
+                                             ///<   @li <b>TRUE</b> - Native IDE mode
+
+  IN       BOOLEAN      Ohci1Enable;         ///< OHCI controller #1 Function
+                                             ///<   @li <b>FALSE</b> - OHCI1 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI1 is enabled
+
+  IN       BOOLEAN      Ohci2Enable;         ///< OHCI controller #2 Function
+                                             ///<   @li <b>FALSE</b> - OHCI2 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI2 is enabled
+
+  IN       BOOLEAN      Ohci3Enable;         ///< OHCI controller #3 Function
+                                             ///<   @li <b>FALSE</b> - OHCI3 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI3 is enabled
+
+  IN       BOOLEAN      Ohci4Enable;         ///< OHCI controller #4 Function
+                                             ///<   @li <b>FALSE</b> - OHCI4 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI4 is enabled
+
+  IN       BOOLEAN      XhciSwitch;          ///< XHCI controller Function
+                                             ///<   @li <b>FALSE</b> - XHCI is disabled
+                                             ///<   @li <b>TRUE</b> - XHCI is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       POWER_FAIL   FchPowerFail;        ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ *   CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+  C1eModeDisabled                   = 0,   ///< Disabled
+  C1eModeAuto                       = 1,   ///< Auto mode enables the best C1e method for the
+                                           ///< currently installed processor
+  C1eModeHardware                   = 2,   ///< Hardware method
+  C1eModeMsgBased                   = 3,   ///< Message-based method
+  C1eModeSoftwareDeprecated         = 4,   ///< Deprecated software SMI method.
+                                           ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
+                                           ///< example host BIOS SMM Handler implementation
+  C1eModeHardwareSoftwareDeprecated = 5,   ///< Hardware or deprecated software SMI method
+  MaxC1eMode                        = 6    ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+  CStateModeDisabled = 0,           ///< Disabled
+  CStateModeC6       = 1,           ///< C6 State
+  MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+  CpbModeAuto     = 0,           ///< Auto
+  CpbModeDisabled = 1,           ///< Disabled
+  MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+typedef enum {
+  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO      = 0,           ///< Auto
+  LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE   = 1,           ///< Disabled
+  MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE  = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_LOW_POWER_PSTATE_MODES;
+
+/*----------------------------------------------------------------------------
+ *   GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+
+#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
+#define DESCRIPTOR_IGNORE                   0x40000000ull
+
+/// PCIe port misc extended controls
+typedef struct  {
+  IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+  IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+                                                             *  @li @b 0 - port can advertize muximum supported capability
+                                                             *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+                                                             */
+  IN      UINT8                     SbLink             :1;  /**< PCIe link type
+                                                             *  @li @b 0 - General purpose port
+                                                             *  @li @b 1 - Port connected to SB
+                                                             */
+} PCIe_PORT_MISC_CONTROL;
+
+
+/// PCIe port configuration data
+typedef struct  {
+  IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
+  IN       UINT8                   ChannelType;              /**< Channel type.
+                                                               *  @li @b 0 - "lowLoss",
+                                                               *  @li @b 1 - "highLoss",
+                                                               *  @li @b 2 - "mob0db",
+                                                               *  @li @b 3 - "mob3db",
+                                                               *  @li @b 4 - "extnd6db"
+                                                               *  @li @b 5 - "extnd8db"
+                                                               */
+  IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
+                                                               *   @li @b 0 - Native port device number
+                                                               *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14ONLaneConfigurations "Family 0x14(ON)")
+                                                               */
+  IN       UINT8                   FunctionNumber;           ///< Reserved for future use
+  IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
+                                                               *  @li @b 0 - Maximum supported by silicon
+                                                               *  @li @b 1 - Gen1
+                                                               *  @li @b 2 - Gen2
+                                                               *  @li @b 3 - Gen3
+                                                               */
+  IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - L0s only
+                                                               *  @li @b 2 - L1 only
+                                                               *  @li @b 3 - L0s and L1
+                                                               */
+  IN       UINT8                   LinkHotplug;              /**< Hotplug control.
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - Basic
+                                                               *  @li @b 2 - Server
+                                                               *  @li @b 3 - Enhanced
+                                                               */
+  IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                               *   identification which control reset for given port.
+                                                               *   Each port with unique GPIO should have unique ResetId assigned.
+                                                               *   All ports use same GPIO to control reset should have same ResetId assigned.
+                                                               *   see AgesaPcieSlotResetContol.
+                                                               */
+  IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct {                                          ///< Structure that discribe lane mapping
+  IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
+                                                           *  @li @b 0 - Map to lane 0
+                                                           *  @li @b 1 - Map to lane 1
+                                                           *  @li @b 2 - Map to lane 2
+                                                           *  @li @b 2 - Map to lane 3
+                                                           */
+  IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING;                                        ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+  IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
+  IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct  {
+  IN       UINT8                ConnectorType;            /**< Display Connector Type
+                                                            *  @li @b 0 - DP
+                                                            *  @li @b 1 - eDP
+                                                            *  @li @b 2 - Single Link DVI-D
+                                                            *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
+                                                            *  @li @b 4 - HDMI
+                                                            *  @li @b 5 - Travis DP-to-VGA
+                                                            *  @li @b 6 - Travis DP-to-LVDS
+                                                            *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+                                                            *  @li @b 8 - Single Link DVI-I
+                                                            *  @li @b 9 - Native CRT (Family 0x14)
+                                                            *  @li @b 10 - Native LVDS (Family 0x14)
+                                                            *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
+                                                            *              The auto detection method only support panel with EDID.
+                                                            */
+  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
+                                                            *  @li @b 0 - AUX1
+                                                            *  @li @b 1 - AUX2
+                                                            *  @li @b 2 - AUX3
+                                                            *  @li @b 3 - AUX4
+                                                            *  @li @b 4 - AUX5
+                                                            *  @li @b 5 - AUX6
+                                                            */
+  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
+                                                            *  @li @b 0 - HDP1
+                                                            *  @li @b 1 - HDP2
+                                                            *  @li @b 2 - HDP3
+                                                            *  @li @b 3 - HDP4
+                                                            *  @li @b 4 - HDP5
+                                                            *  @li @b 5 - HDP6
+                                                            */
+  IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
+                                                            *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+                                                            *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+                                                            *  if Mapping[x] set to 0 than default mapping assumed
+                                                            */
+  IN       UINT8                LanePnInversionMask;      /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+                                                            *  @li 0 - Do not invert (default)
+                                                            *  @li 1 - Invert P and N on this lane
+                                                            */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+  IN       UINT8                EngineType;               /**< Engine type
+                                                           *  @li @b 0 -  Ignore engine configuration
+                                                           *  @li @b 1 -  PCIe port
+                                                           *  @li @b 2 -  DDI
+                                                           */
+  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in topology
+                                                           */
+  IN       UINT32               SocketId;                 ///< Socket Id
+  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       VOID                 *Reserved;                ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+  AssertSlotReset,                                        ///< Assert slot reset
+  DeassertSlotReset                                       ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+/// Engine descriptor type
+typedef enum {
+  PcieUnusedEngine = 0,                                   ///< Unused descriptor
+  PciePortEngine = 1,                                     ///< PCIe port
+  PcieDdiEngine = 2,                                      ///< DDI
+  MaxPcieEngine                                           ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum  {
+  PcieGenMaxSupported,                                    ///< Maximum supported
+  PcieGen1 = 1,                                           ///< Gen1
+  PcieGen2,                                               ///< Gen2
+  MaxPcieGen                                              ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum  {
+  PsppDisabled,                                           ///< PSPP disabled
+  PsppPerformance = 1,                                    ///< Performance
+  PsppBalanceHigh,                                        ///< Balance-High
+  PsppBalanceLow,                                         ///< Balance-Low
+  PsppPowerSaving,                                        ///< Power Saving
+  MaxPspp                                                 ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+  ConnectorTypeDP,                                        ///< DP
+  ConnectorTypeEDP,                                       ///< eDP
+  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
+  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
+  ConnectorTypeHDMI,                                      ///< HDMI
+  ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
+  ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
+  ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
+  ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
+  ConnectorTypeCrt,                                       ///< CRT (VGA)
+  ConnectorTypeLvds,                                      ///< LVDS
+  ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
+  MaxConnectorType                                        ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+  ChannelTypeLowLoss,                                     ///< Low Loss
+  ChannelTypeHighLoss,                                    ///< High Loss
+  ChannelTypeMob0db,                                      ///< Mobile 0dB
+  ChannelTypeMob3db,                                      ///< Mobile 3dB
+  ChannelTypeExt6db,                                      ///< Extended 6dB
+  ChannelTypeExt8db,                                      ///< Extended 8dB
+  MaxChannelType                                          ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+  AspmDisabled,                                           ///< Disabled
+  AspmL0s,                                                ///< PCIe L0s link state
+  AspmL1,                                                 ///< PCIe L1 link state
+  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
+  MaxAspm                                                 ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+  HotplugDisabled,                                        ///< Hotplug disable
+  HotplugBasic,                                           ///< Basic Hotplug
+  HotplugServer,                                          ///< Server Hotplug
+  HotplugEnhanced,                                        ///< Enhanced
+  HotplugInboard,                                         ///< Inboard
+  MaxHotplug                                              ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+  PortDisabled,                                           ///< Disable
+  PortEnabled                                             ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+  Aux1,                                                   ///< Aux1
+  Aux2,                                                   ///< Aux2
+  Aux3,                                                   ///< Aux3
+  Aux4,                                                   ///< Aux4
+  Aux5,                                                   ///< Aux5
+  Aux6,                                                   ///< Aux6
+  MaxAux                                                  ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+  Hdp1,                                                   ///< Hdp1
+  Hdp2,                                                   ///< Hdp2
+  Hdp3,                                                   ///< Hdp3
+  Hdp4,                                                   ///< Hdp4
+  Hdp5,                                                   ///< Hdp5
+  Hdp6,                                                   ///< Hdp6
+  MaxHdp                                                  ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+// Macro for statically initialization of various structures
+#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
+#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0}
+#define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion}
+
+///IOMMU requestor ID
+typedef struct {
+  IN       UINT16     Bus       :8;                                ///< Bus
+  IN       UINT16     Device    :5;                                ///< Device
+  IN       UINT16     Function  :3;                                ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Flags[31] - Terminate descriptor array.
+                                                           * @li @b Flags[30] - Ignore descriptor.
+                                                           */
+  IN       IOMMU_REQUESTOR_ID   RequestorIdStart;         ///< Requestor ID start
+  IN       IOMMU_REQUESTOR_ID   RequestorIdEnd;           ///< Requestor ID end (use same as start for single ID)
+  IN       UINT64               RangeBaseAddress;         ///< Phisical base address of exclusion range
+  IN       UINT64               RangeLength;              ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ *   GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+  IN  UINT8     FpdiMode:1;          ///< This item configures LVDS 888bit panel mode
+                                     ///< @li FALSE = LVDS 888 panel in LDI mode
+                                     ///< @li TRUE =  LVDS 888 panel in FPDI mode
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+  IN  UINT8     DlChSwap:1;          ///< This item configures LVDS panel lower and upper link mapping
+                                     ///< @li FALSE = Lower link and upper link not swap
+                                     ///< @li TRUE = Lower link and upper link are swapped
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+  IN  UINT8     VsyncActiveLow:1;    ///< This item configures polarity of frame pulse encoded in lvds data stream
+                                     ///< @li FALSE = Active high Frame Pulse/Vsync
+                                     ///< @li TRUE = Active low Frame Pulse/Vsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+  IN  UINT8     HsyncActiveLow:1;    ///< This item configures polarity of line pulse encoded in lvds data
+                                     ///< @li FALSE = Active high Line Pulse
+                                     ///< @li TRUE = Active low Line Pulse / Hsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+  IN  UINT8     BLONActiveLow:1;     ///< This item configures polarity of signal sent to digital BLON output pin
+                                     ///< @li FALSE = Not inverted(active high)
+                                     ///< @li TRUE = Inverted (active low)
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+  IN  UINT8     Reserved:3;          ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+  IN LVDS_MISC_CONTROL_FIELD Field;  ///< LVDS_MISC_CONTROL_FIELD
+  IN UINT8   Value;                  ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Configuration settings for GNB.
+typedef struct {
+  IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
+                                          ///< @li 0 = Stereo 3D is disabled (default).
+                                          ///< @li 1 = Use processor pin HPD1.
+                                          ///< @li 2 = Use processor pin HPD2
+                                          ///< @li 3 = Use processor pin HPD3
+                                          ///< @li 4 = Use processor pin HPD4
+                                          ///< @li 5 = Use processor pin HPD5
+                                          ///< @li 6 = Use processor pin HPD6
+                                          ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+  IN  BOOLEAN    IommuSupport;            ///< IOMMU support.
+                                          ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+                                          ///< @li TRUE  = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+                                          ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+  IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN  UINT8      LvdsPowerOnSeqDigonToDe;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqDeToVaryBl;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+  IN  UINT8      LvdsPowerOnSeqDeToDigon;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToDe;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+  IN  UINT8      LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+  IN  UINT16     LvdsMaxPixelClockFreq;      ///< This item configures the maximum pixel clock frequency supported.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+  IN  UINT32     LcdBitDepthControlValue;    ///< This item configures the LCD bit depth control settings.
+                                             ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+  IN  UINT8      Lvds24bbpPanelMode;         ///< This item configures the LVDS 24 BBP mode.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+  IN  LVDS_MISC_CONTROL      LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+  IN  UINT16     PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
+                                             ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN  BOOLEAN    GnbRemoteDisplaySupport;    ///< This item enables Wireless Display Support
+                                             ///< @li TRUE  = Enable Wireless Display Support
+                                             ///< @li FALSE = Disable Wireless Display Support
+                                             ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+} GNB_ENV_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+                                                        * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
+                                                        * Example of topology definition for single socket system:
+                                                        * @code
+                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    }
+                                                        *  };
+                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+                                                        *    },
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+                                                        *    }
+                                                        *  };
+                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
+                                                        *   0,  //Socket ID
+                                                        *   &PortList[0],
+                                                        *   &DdiList[0],
+                                                        * }
+                                                        * @endcode
+                                                        */
+  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
+                                                         *  @li @b 0 - Disabled
+                                                         *  @li @b 1 - Performance
+                                                         *  @li @b 2 - Balance-High
+                                                         *  @li @b 3 - Balance-Low
+                                                         *  @li @b 4 - Power Saving
+                                                         */
+
+} GNB_CONFIGURATION;
+//
+//  MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+//   These Max values are used to define array sizes and associated loop
+//   counts in the code.  They reflect the maximum values that AGESA
+//   currently supports and does not necessarily reflect the hardware
+//   capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
+                                    ///< Eg: UINT16  *RcvEnDlys;
+                                    ///<     UINT8   *WrDqsDlys;
+                                    ///<     UINT8   *RdDqsDlys;
+                                    ///<     UINT8   *WrDatDlys;
+                                    ///<     UINT8   *RdDqsMinDlys;
+                                    ///<     UINT8   *RdDqsMaxDlys;
+                                    ///<     UINT8   *WrDatMinDlys;
+                                    ///<     UINT8   *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
+
+typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
+
+//        AGESA DEFINITIONS
+//
+//        Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
+/// CPU Package Type
+#define PT_L1       0                 ///< L1 Package type
+#define PT_M2       1                 ///< AM Package type
+#define PT_S1       2                 ///< S1 Package type
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
+  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
+  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
+  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+  DDR2_TECHNOLOGY,      ///< DDR2 technology
+  DDR3_TECHNOLOGY       ///< DDR3 technology
+} TECHNOLOGY_TYPE;
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+typedef enum {
+  DDR400_FREQUENCY = 200,     ///< DDR 400
+  DDR533_FREQUENCY = 266,     ///< DDR 533
+  DDR667_FREQUENCY = 333,     ///< DDR 667
+  DDR800_FREQUENCY = 400,     ///< DDR 800
+  DDR1066_FREQUENCY = 533,    ///< DDR 1066
+  DDR1333_FREQUENCY = 667,    ///< DDR 1333
+  DDR1600_FREQUENCY = 800,    ///< DDR 1600
+  DDR1866_FREQUENCY = 933,    ///< DDR 1866
+  DDR2100_FREQUENCY = 1050,   ///< DDR 2100
+  DDR2133_FREQUENCY = 1066,   ///< DDR 2133
+  DDR2400_FREQUENCY = 1200,   ///< DDR 2400
+  UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
+} MEMORY_BUS_SPEED;
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+typedef enum {
+  QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
+  QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
+} QUANDRANK_TYPE;
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+typedef enum {
+  TIMING_MODE_AUTO,           ///< Use best rate possible
+  TIMING_MODE_LIMITED,        ///< Set user top limit
+  TIMING_MODE_SPECIFIC        ///< Set user specified speed
+} USER_MEMORY_TIMING_MODE;
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+typedef enum {
+  POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
+  POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
+  POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
+} POWER_DOWN_MODE;
+
+/// Low voltage support
+typedef enum {
+  VOLT_INITIAL,              ///< Initial value for VDDIO
+  VOLT1_5,                   ///< 1.5 Volt
+  VOLT1_35,                  ///< 1.35 Volt
+  VOLT1_25,                  ///< 1.25 Volt
+  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+  UMA_NONE = 0,              ///< UMA None
+  UMA_SPECIFIED = 1,         ///< UMA Specified
+  UMA_AUTO = 2               ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+  FORCE_TRAIN_1D = 0,              ///< 1D Training only
+  FORCE_TRAIN___ = 1,              ///<
+  FORCE_TRAIN_AUTO = 2             ///<  Auto
+} FORCE_TRAIN_MODE;
+
+///  The possible DRAM prefetch mode settings.
+typedef enum  {
+  DRAM_PREFETCHER_AUTO,                         ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_DRAM_PREFETCH_FOR_IO,                 ///< Disable DRAM prefetching for I/O requests only.
+  DISABLE_DRAM_PREFETCH_FOR_CPU,                ///< Disable DRAM prefetching for requests from processor cores only.
+  DISABLE_DRAM_PREFETCHER,                      ///< Disable DRAM prefetching.
+  MAX_DRAM_FREFETCH_MODE                        ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
+  UMA_4MB_ALIGNED = 0x00FFFFC0,          ///< UMA 4MB aligned
+  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
+  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
+  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+///   Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
+  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
+  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
+  GsbSoftHole,               ///< A Node Base gap was created
+  GsbHWHole,                 ///< A HW dram remap was created
+  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
+  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                     ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+  EsbNoDimms,                  ///< No DIMMs
+  EsbSpdChkSum,                ///< SPD Checksum fail
+  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
+  EsbDimmMismatchT,            ///< dimm CL/T mismatch
+  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
+  EsbNoCycTime,                ///< SPD missing byte 23 or 25
+  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
+  EsbDramECCDis,               ///< Dram ECC requested but not enabled
+  EsbSpareDis,                 ///< Online spare requested but not enabled
+  EsbMinimumMode,              ///< Running in Minimum Mode
+  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
+  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
+  EsbSmallDqs,                 ///< DQS-DQ passing window too small
+  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
+
+  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
+  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
+                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
+                               ///< memory size of each DCT is not a power of two.
+
+  EsbEOL                       ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+///  Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+  SbRegistered,                ///< All DIMMs are Registered
+  SbEccDimms,                  ///< All banks ECC capable
+  SbParDimms,                  ///< All banks Addr/CMD Parity capable
+  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
+  Sb128bitmode,                ///< DCT in 128-bit mode operation
+  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
+  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
+  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
+  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
+  SbLrdimms,                   ///< All DIMMs are LRDIMMs
+
+  SbEOL                        ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG     0xC0010010
+//#define TOP_MEM     0xC001001A
+//#define TOP_MEM2    0xC001001D
+#ifndef TOP_MEM
+  #define TOP_MEM			0xC001001A
+#endif
+#ifndef TOP_MEM2
+  #define TOP_MEM2			0xC001001D
+#endif
+#define HWCR        0xC0010015
+#define NB_CFG      0xC001001F
+
+#define FS_BASE     0xC0000100
+#define IORR0_BASE  0xC0010016
+#define IORR0_MASK  0xC0010017
+#define BU_CFG      0xC0011023
+#define BU_CFG2     0xC001102A
+#define COFVID_STAT 0xC0010071
+#define TSC         0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
+  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
+  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
+                                 ///<  DIMM#  Select Signal
+                                 ///<  0      MA0_CS_L[0, 1]
+                                 ///<  1      MB0_CS_L[0, 1]
+                                 ///<  2      MA1_CS_L[0, 1]
+                                 ///<  3      MB1_CS_L[0, 1]
+                                 ///<  4      MA2_CS_L[0, 1]
+                                 ///<  5      MB2_CS_L[0, 1]
+                                 ///<  6      MA3_CS_L[0, 1]
+                                 ///<  7      MB3_CS_L[0, 1]
+
+  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+                                 ///<
+  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+  OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+  OUT UINT8   Loads;             ///< Number of devices loading bus
+  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
+  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
+  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
+                                 ///< FALSE = 1T
+                                 ///< TRUE = 2T
+  ///< The following pointers will be pointed to dynamically allocated buffers.
+  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ///< Example: If DIMM and Byte based training, then
+  ///< XX is a value in Hex
+  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
+  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
+  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
+  OUT UINT8   *WrDatDlys;       ///< Write Data delays
+  OUT UINT8   *RdDqs__Dlys;     ///< Read DQS data
+  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
+  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
+  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
+  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
+  OUT UINT16  *RcvEnDlysMemPs1;       ///< DQS Receiver Enable Delays for Mem Pstate 1
+  OUT UINT8   *WrDqsDlysMemPs1;       ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+  OUT UINT8   *RdDqsDlysMemPs1;       ///< Read Dqs delays for Memory Pstate 1
+  OUT UINT8   *WrDatDlysMemPs1;       ///< Write Data delays for Memory Pstate 1
+  OUT UINT8   *RdDqs__DlysMemPs1;     ///< Read DQS data for Memory Pstate 1
+  OUT UINT8   *RdDqsMinDlysMemPs1;    ///< Minimum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *RdDqsMaxDlysMemPs1;    ///< Maximum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *WrDatMinDlysMemPs1;    ///< Minimum Window for Write data for Memory Pstate 1
+  OUT UINT8   *WrDatMaxDlysMemPs1;    ///< Maximum Window for Write data for Memory Pstate 1
+  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
+  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
+  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
+  OUT UINT8   *FailingBitMaskMemPs1;    ///< Table of masks to Track Failing bits for Memory Pstate 1
+  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
+  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
+  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
+  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
+  OUT UINT8   Pattern;            ///< Current pattern
+  OUT UINT8   DqsDelay;           ///< Current DQS delay value
+  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT16  DctMaxRdLat[4];     ///< Max Read Latency (ns) for the DCT
+                                  ///< DctMaxRdLat [i] is for NBPstate i
+  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
+  OUT UINT8   MaxCh;              ///< Max number of CH in system
+  OUT UINT8   Dct;                ///< Dct pointer
+  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
+  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
+
+  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
+  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
+  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
+  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
+  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
+  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
+  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
+  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
+  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
+  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
+  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
+  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
+
+  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
+  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+  OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+  OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+  OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+  OUT UINT8   DimmNibbleAccess;   ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ///<  base on this array to disable unused MemClk to save power.
+                                  ///<
+                                  ///<  The array must have 8 entries. Each entry, which associates with
+                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ///<    Example:
+                                  ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ///<    is like below:
+                                  ///<         Bit AM3/S1g3 pin name
+                                  ///<         0   M[B,A]_CLK_H/L[0]
+                                  ///<         1   M[B,A]_CLK_H/L[1]
+                                  ///<         2   M[B,A]_CLK_H/L[2]
+                                  ///<         3   M[B,A]_CLK_H/L[3]
+                                  ///<         4   M[B,A]_CLK_H/L[4]
+                                  ///<         5   M[B,A]_CLK_H/L[5]
+                                  ///<         6   M[B,A]_CLK_H/L[6]
+                                  ///<         7   M[B,A]_CLK_H/L[7]
+                                  ///<    And platform has the following routing:
+                                  ///<         CS0   M[B,A]_CLK_H/L[4]
+                                  ///<         CS1   M[B,A]_CLK_H/L[2]
+                                  ///<         CS2   M[B,A]_CLK_H/L[3]
+                                  ///<         CS3   M[B,A]_CLK_H/L[5]
+                                  ///<    Then MemClkDisMap should be pointed to the following array:
+                                  ///<               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ///<  Each entry of the array is the bitmask of 8 chip selects.
+
+  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of CKE pins to the DIMMs' ranks.
+                                  ///<  The array must have 2 entries. Each entry, which associates with
+                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
+
+  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of ODT pins to the DIMMs' ranks.
+                                  ///<  The array must have 4 entries. Each entry, which associates with
+                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
+
+  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of chip select pins to the DIMMs' ranks.
+                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
+
+  OUT UINT8   MaxVref;            ///<  Maximum Vref Value for channel
+
+  OUT UINT8   Reserved[100];      ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+  OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
+  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
+  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
+  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
+  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
+  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
+                                  ///<  400 (MHz)
+                                  ///<  533 (MHz)
+                                  ///<  667 (MHz)
+                                  ///<  800 (MHz)
+                                  ///<  and so on...
+  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
+  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
+  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
+  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
+  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
+  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
+  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
+  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
+  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
+  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
+  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
+                                  ///<  0 = 75ns (for 256Mb devs)
+                                  ///<  1 = 105ns (for 512Mb devs)
+                                  ///<  2 = 127.5ns (for 1Gb devs)
+                                  ///<  3 = 195ns (for 2Gb devs)
+                                  ///<  4 = 327.5ns (for 4Gb devs)
+  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
+                                  ///<
+  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
+                                  ///< FALSE = 1T
+                                  ///< TRUE = 2T
+  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
+  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
+  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
+  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
+  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
+  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
+  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
+  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
+  OUT UINT16  MaxRdLat;           ///< Max Read Latency
+  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
+  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+  OUT UINT8   Dct;                ///< Current Dct
+  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
+  OUT CH_TIMING_STRUCT *TimingsMemPs1;   ///< Pointed to channel timing structure for memory Pstate 1
+  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
+  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
+  OUT BOOLEAN BkIntDis;           ///< Bank interleave requested but not enabled on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+  /// Advanced:
+
+  OUT UINT8   NodeId;              ///< Node ID of current controller
+  OUT UINT8   SocketId;            ///< Socket ID of this Die
+  OUT UINT8   DieId;               ///< ID of this die relative to the socket
+  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
+  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
+                                   ///<  0x0 = AGESA_SUCCESS
+                                   ///<  0x1 = AGESA_UNSUPPORTED
+                                   ///<  0x2 = AGESA_BOUNDS_CHK
+                                   ///<  0x3 = AGESA_ALERT
+                                   ///<  0x4 = AGESA_WARNING
+                                   ///<  0x5 = AGESA_ERROR
+                                   ///<  0x6 = AGESA_CRITICAL
+                                   ///<  0x7 = AGESA_FATAL
+                                   ///<
+  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
+                                   ///<
+  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
+                                   ///<
+  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+                                   ///<
+  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
+                                   ///<
+  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+                                   ///<
+  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
+                                   ///<
+  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
+                                   ///<   DIMM#  Select Signal
+                                   ///<   0      MA0_CS_L[0, 1]
+                                   ///<   1      MB0_CS_L[0, 1]
+                                   ///<   2      MA1_CS_L[0, 1]
+                                   ///<   3      MB1_CS_L[0, 1]
+                                   ///<   4      MA2_CS_L[0, 1]
+                                   ///<   5      MB2_CS_L[0, 1]
+                                   ///<   6      MA3_CS_L[0, 1]
+                                   ///<   7      MB3_CS_L[0, 1]
+                                   ///<
+  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+  OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+                                   ///<
+  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
+  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
+                                   ///<  0 in any bit field indicates Channel 0
+                                   ///<  1 in any bit field indicates Channel 1
+  OUT UINT8   Dct;                 ///<  Need to be removed
+                                   ///<  DCT pointer
+  OUT BOOLEAN GangedMode;          ///< Ganged mode
+                                   ///<  0 = disabled
+                                   ///<  1 = enabled
+  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+                                   ///<
+  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT8   MLoad;               ///< Need to be removed
+                                   ///< Number of devices loading MAA bus
+                                   ///<
+  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
+                                   ///<
+  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
+                                   ///<
+  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
+                                   ///<
+  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
+  OUT UINT8   Reserved[16];        ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
+     OUT   UINT16 Version;             ///< S3 Params version number
+  IN OUT   UINT32 Flags;               ///< Indicates operation
+  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
+  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
+  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
+  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+  // Basic (Return parameters)
+  // (This section contains the outbound parameters from the memory init code)
+
+  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
+                                  ///<
+  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+                                  ///<
+  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
+                                  ///<
+  OUT UINT32 Sub1THoleBase;       ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+                                  ///<
+  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
+                                  ///<
+  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
+                                  ///<
+  OUT UINT8 ExternalVrefValue;    ///< Target reference voltage for external Vref for training
+                                  ///<
+  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
+
+  //  Advanced (Optional parameters)
+  //  Optional (all defaults values will be initialized by the
+  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
+  //  to the IBV/OEM to change the defaults after initialization
+  //  but prior to the main entry to the memory code):
+
+  // Memory Map/Mgt.
+
+  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
+                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
+                                   ///<
+  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+  IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+  // Dram Timing
+
+  IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
+                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+  IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
+                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+  // Dram Configuration
+
+  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
+                                   ///<  - FALSE =disable (default)
+                                   ///<  - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+  // ECC
+
+  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+  // Dram Power
+
+  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
+                                   ///<   - FALSE =disable (default)
+                                   ///<   - TRUE =enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+  // Online Spare
+
+  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+                                   ///<  - FALSE = disable Spare (default)
+                                   ///<  - TRUE = enable Spare
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+  IN PSO_TABLE *PlatformMemoryConfiguration;
+                                   ///< A table that contains platform specific settings.
+                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ///< contains default conservative settings. Platform BIOS can either tweak
+                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ///<
+  IN BOOLEAN EnableParity;         ///< Parity control.
+                                   ///<  - TRUE = enable
+                                   ///<  - FALSE = disable (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+                                   ///<
+
+  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+
+  // Uma Configuration
+
+  IN UMA_MODE UmaMode;             ///<  Uma Mode
+                                   ///<  0 = None
+                                   ///<  1 = Specified
+                                   ///<  2 = Auto
+  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
+                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ///<
+  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
+                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ///<
+
+  /// Memory Restore Feature
+
+  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
+                                   ///<   FALSE = perform memory init as normal (AMD default)
+                                   ///<   TRUE = restore memory context and skip training. This requires
+                                   ///<          MemContext is valid before AmdInitPost
+                                   ///<
+  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
+                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ///<           expected to call S3Save later in POST if it wants to
+                                   ///<           use memory context restore feature.
+                                   ///<
+  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+                                   ///< save and restore for memory context restore feature to work.
+                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
+                                   ///< may save only S3 block and uses it for both S3 resume and
+                                   ///< memory context restore.
+                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ///<    before AmdInitPost.
+                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ///<    right after AmdInitPost.
+                                   ///<
+  IN BOOLEAN ExternalVrefCtl;      ///< Control the use of external Vref
+                                   ///<   TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+                                   ///<          to change the vref
+                                   ///<   FALSE = AGESA will will use the internal vref control.
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+                                   ///<
+  IN FORCE_TRAIN_MODE ForceTrainMode;   ///<  Training Mode
+                                   ///<  0 = Force 1D Training for all configurations
+                                   ///<  1 = Force training for all configurations
+                                   ///<  2 = Auto - AGESA will control
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+  // PUBLIC required Internal functions
+
+  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
+  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
+
+  // PUBLIC optional functions
+
+  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
+  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
+  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
+  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
+  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
+  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
+  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
+  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
+  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
+  IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);               ///< NB code for LRDIMMs
+  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
+
+  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+
+  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
+
+  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
+
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
+                                   ///< SocketList is a shortcut for IBVs to retrieve training
+                                   ///< and timing data for each channel indexed by socket/channel,
+                                   ///< eliminating their need to parse die/dct/channel etc.
+                                   ///< It contains pointers to the populated data structures for
+                                   ///< each channel and skips the channel structures that are
+                                   ///< unpopulated. In the case of channels sharing the same DCT,
+                                   ///< the pTimings pointers will point to the same DCT Timing data.
+
+  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
+  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
+
+  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
+
+  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
+
+  IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
+
+  OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
+  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
+  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
+  OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
+  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
+  OUT UINT8 Reserved[3];       ///< Reserved for future usage
+} UMA_INFO;
+
+/// Bitfield for ID
+typedef struct {
+  OUT UINT16 SocketId:8;       ///< Socket ID
+  OUT UINT16 ModuleId:8;       ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+  OUT ID_FIELD IdField;         ///< Bitfield for ID
+  OUT UINT16 IdInformation;     ///< ID information for call out
+} ID_INFO;
+
+//  AGESA MEMORY ERRORS
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+                                                       ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO____RDDQS_WINDOW 0x040D0300           ///< No RdDqs Window
+#define MEM_ERROR_NO____RDDQS_HEIGHT 0x040E0300  ///< No RdDqs Height
+#define MEM_ERROR____DQS_ERROR  0x040F0300 ///< RdDqs Error
+#define MEM_ERROR_INVALID____RDDQS_VALUE  0x04022400 ///< RdDqs invalid value found
+#define MEM_ERROR____DQS_VREF_MARGIN_ERROR  0x04023400 ///< RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND  0x04013500 ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND  0x04023500 ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND  0x04033500 ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND  0x04043500 ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND  0x04053500 ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND  0x04063500 ///< No RTT value is found
+#define MEM_ERROR_P___NOT_FOUND  0x04073500 ///< No training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND  0x04083500 ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND  0x04093500 ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND  0x040A3500 ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND  0x040B3500 ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND  0x040C3500 ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND  0x040D3500 ///< No training seed is found
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS                 0x04041700  ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
+                                                        ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO   0x04012400 ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO   0x04012500 ///< Cannot find a commonly supported VDDIO
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED      0x04022500     ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR___     0x040B1F00    ///< Heap allocation error for training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR___     0x040C1F00    ///< Heap de-allocation error for training data
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                    CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
+
+//================================================================
+// CPU General events
+//    Heap allocation                     (AppFunction =      01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
+#define CPU_ERROR_HEAP_IS_FULL                          0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
+//    BrandId                             (AppFunction =      02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
+//    Micro code patch                    (AppFunction =      03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
+//    Power management                    (AppFunction =      04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
+//    Other CPU events                    (AppFunction =      05h)
+#define CPU_EVENT_BIST_ERROR                            0x08000500
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY              0x08010500
+#define CPU_EVENT_STACK_REENTRY                         0x08020500
+#define CPU_EVENT_CORE_NOT_IDENTIFIED                   0x08030500
+
+//=================================================================
+// CPU Feature events
+//    Execution cache                     (AppFunction =      21h)
+//        AGESA_CACHE_SIZE_REDUCED                            2101
+//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
+//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
+//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
+//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
+//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
+//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
+//    Core Leveling                       (AppFunction =      22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
+//    HT Assist                           (AppFunction =      23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
+  IN  UINT64 MsrData;     ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000    0x00000250
+#define AMD_AP_MTRR_FIX16k_80000    0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000    0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000     0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000     0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
+#define CPU_LIST_TERMINAL           0xFFFFFFFF
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
+  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
+  IN OUT UINTN Reserved;              ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
+  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
+  OUT       VOID                *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
+  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
+  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
+  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
+  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
+  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
+  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
+  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// Buffer Handles
+typedef enum {
+  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
+  AMD_ACPI_ALIB_BUFFER_HANDLE,                  ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+  AMD_ACPI_IVRS_BUFFER_HANDLE                   ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
+} AMD_BUFFER_HANDLE;
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+  IN        UINTN               ResetType,
+  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
+  );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
+  );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
+  );
+
+AGESA_STATUS
+AgesaReadSpd (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN               ApicIdOfCore,
+  IN        AP_EXE_PARAMS       *LaunchApParams
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+  IN      VOID                  *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal__TrainVrefChange (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+/************************************************************************
+ *
+ *  AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration:  The parameters in boot branch function
+ **********************************************************************/
+
+///  The possible platform control flow settings.
+typedef enum  {
+  Nfcm,                                          ///< Normal Flow Control Mode.
+  UmaDr,                                         ///< UMA using Display Refresh flow control.
+  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
+  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
+  Iommu,                                         ///< An IOMMU is in use in the system.
+  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+///  Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+  DeemphasisLevelNone,                           ///< No Deemphasis.
+  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
+  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
+  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
+  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
+  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
+  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
+  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
+  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
+  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
+  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
+  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
+  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+///  Provide Deemphasis Levels for HT Links.
+///
+///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
+///  is in the inclusive range HighFreq:LoFreq.
+///  AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
+  IN       UINT8 Link;                                          ///< The Link on this Processor.
+  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
+  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
+  // Value fields
+  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
+  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+
+///  The possible hardware prefetch mode settings.
+typedef enum  {
+  HARDWARE_PREFETCHER_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_L1_PREFETCHER,                        ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
+  DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+  DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
+  DISABLE_HARDWARE_PREFETCH,                    ///< Disable hardware prefetching.
+  MAX_HARDWARE_PREFETCH_MODE                    ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+///  The possible software prefetch mode settings.
+typedef enum  {
+  SOFTWARE_PREFETCHES_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_SOFTWARE_PREFETCHES,                  ///< Disable software prefetches (convert software prefetch instructions to NOP).
+  MAX_SOFTWARE_PREFETCH_MODE                    ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+  IN HARDWARE_PREFETCH_MODE  HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+  IN SOFTWARE_PREFETCH_MODE  SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+  IN DRAM_PREFETCH_MODE      DramPrefetchMode;     ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+///  The possible platform power policy settings.
+typedef enum  {
+  Performance,                                   ///< Optimize for performance.
+  BatteryLife,                                   ///< Optimize for battery life.
+  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+///  Platform performance settings for optimized settings.
+///  Several configuration settings for the processor depend upon other parts and
+///  general designer choices for the system. The determination of these data points
+///  is not standard for all platforms, so the host environment needs to provide these
+///  to specify how the system is to be configured.
+typedef struct {
+  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+  IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
+  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
+                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+  IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile;   ///< The advanced platform performance settings.
+  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+} PERFORMANCE_PROFILE;
+
+///  Platform settings that describe the voltage regulator modules of the system.
+///  Many power management settings are dependent upon the characteristics of the
+///  on-board voltage regulator module (VRM).  The host environment needs to provide
+///  these to specify how the system is to be configured.
+typedef struct {
+  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+  IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
+  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+  IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
+} PLATFORM_VRM_CONFIGURATION;
+
+///  The VRM types to characterize.
+typedef enum  {
+  CoreVrm,                                       ///< VDD plane.
+  NbVrm,                                         ///< VDDNB plane.
+  MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// FCH Platform Configuration Policy
+typedef struct {
+  IN UINT16     CfgSmbus0BaseAddress;             ///< SMBUS0 Controller Base Address
+  IN UINT16     CfgSmbus1BaseAddress;             ///< SMBUS1 Controller Base Address
+  IN UINT16     CfgSioPmeBaseAddress;             ///< I/O base address for LPC I/O target range
+  IN UINT16     CfgAcpiPm1EvtBlkAddr;             ///< I/O base address of ACPI power management Event Block
+  IN UINT16     CfgAcpiPm1CntBlkAddr;             ///< I/O base address of ACPI power management Control Block
+  IN UINT16     CfgAcpiPmTmrBlkAddr;              ///< I/O base address of ACPI power management Timer Block
+  IN UINT16     CfgCpuControlBlkAddr;             ///< I/O base address of ACPI power management CPU Control Block
+  IN UINT16     CfgAcpiGpe0BlkAddr;               ///< I/O base address of ACPI power management General Purpose Event Block
+  IN UINT16     CfgSmiCmdPortAddr;                ///< I/O base address of ACPI SMI Command Block
+  IN UINT16     CfgAcpiPmaCntBlkAddr;             ///< I/O base address of ACPI power management additional control block
+  IN UINT32     CfgGecShadowRomBase;              ///< 32-bit base address to the GEC shadow ROM
+  IN UINT32     CfgWatchDogTimerBase;             ///< Watchdog Timer base address
+  IN UINT32     CfgSpiRomBaseAddress;             ///< Base address for the SPI ROM controller
+  IN UINT32     CfgHpetBaseAddress;               ///< HPET MMIO base address
+  IN UINT32     CfgAzaliaSsid;                    ///< Subsystem ID of HD Audio controller
+  IN UINT32     CfgSmbusSsid;                     ///< Subsystem ID of SMBUS controller
+  IN UINT32     CfgIdeSsid;                       ///< Subsystem ID of IDE controller
+  IN UINT32     CfgSataAhciSsid;                  ///< Subsystem ID of SATA controller in AHCI mode
+  IN UINT32     CfgSataIdeSsid;                   ///< Subsystem ID of SATA controller in IDE mode
+  IN UINT32     CfgSataRaid5Ssid;                 ///< Subsystem ID of SATA controller in RAID5 mode
+  IN UINT32     CfgSataRaidSsid;                  ///< Subsystem ID of SATA controller in RAID mode
+  IN UINT32     CfgEhciSsid;                      ///< Subsystem ID of EHCI
+  IN UINT32     CfgOhciSsid;                      ///< Subsystem ID of OHCI
+  IN UINT32     CfgLpcSsid;                       ///< Subsystem ID of LPC ISA Bridge
+  IN UINT32     CfgSdSsid;                        ///< Subsystem ID of SecureDigital controller
+  IN UINT32     CfgXhciSsid;                      ///< Subsystem ID of XHCI
+  IN BOOLEAN    CfgFchPort80BehindPcib;           ///< Is port80 cycle going to the PCI bridge
+  IN BOOLEAN    CfgFchEnableAcpiSleepTrap;        ///< ACPI sleep SMI enable/disable
+  IN GPP_LINKMODE CfgFchGppLinkConfig;            ///< GPP link configuration
+  IN BOOLEAN    CfgFchGppPort0Present;            ///< Is FCH GPP port 0 present
+  IN BOOLEAN    CfgFchGppPort1Present;            ///< Is FCH GPP port 1 present
+  IN BOOLEAN    CfgFchGppPort2Present;            ///< Is FCH GPP port 2 present
+  IN BOOLEAN    CfgFchGppPort3Present;            ///< Is FCH GPP port 3 present
+  IN BOOLEAN    CfgFchGppPort0HotPlug;            ///< Is FCH GPP port 0 hotplug capable
+  IN BOOLEAN    CfgFchGppPort1HotPlug;            ///< Is FCH GPP port 1 hotplug capable
+  IN BOOLEAN    CfgFchGppPort2HotPlug;            ///< Is FCH GPP port 2 hotplug capable
+  IN BOOLEAN    CfgFchGppPort3HotPlug;            ///< Is FCH GPP port 3 hotplug capable
+
+  IN UINT8   CfgFchEsataPortBitMap;               ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+  IN UINT8   CfgFchIrPinControl;                  ///< Register bitfield describing Infrared Pin Control:
+                                                  ///<   [0] - IR Enable 0
+                                                  ///<   [1] - IR Enable 1
+                                                  ///<   [2] - IR Tx0
+                                                  ///<   [3] - IR Tx1
+                                                  ///<   [4] - IR Open Drain
+                                                  ///<   [5] - IR Enable LED
+  IN SD_CLOCK_CONTROL CfgFchSdClockControl;       ///< FCH SD Clock Control
+  IN SCI_MAP_CONTROL  *CfgFchSciMapControl;       ///< FCH SCI Mapping Control
+  IN SATA_PHY_CONTROL *CfgFchSataPhyControl;      ///< FCH SATA PHY Control
+  IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
+
+  //Build Option Area
+  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+  IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+  IN BOOLEAN OptionPStatesInHpcMode;              ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE"
+  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
+  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
+  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
+  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData3;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
+  IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+  IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
+  IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
+  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
+  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
+  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
+  IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
+
+  IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+  IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
+  IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
+  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
+  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+  IN BOOLEAN CfgLimitMemoryToBelow1Tb;            ///< Limit memory address space to below 1TB
+  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
+  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
+  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
+  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
+  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
+  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
+  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
+  IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
+  IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
+  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
+  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
+  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
+  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
+  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
+  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
+  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
+  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
+  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
+  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
+  IN UINT8   CfgAbmSupport;                       ///< Abm Support
+  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
+  IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
+  IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
+  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+  IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+  IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
+
+  IN BOOLEAN    CfgIommuSupport;                  ///< IOMMU support
+  IN UINT8      CfgLvdsPowerOnSeqDigonToDe;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToVaryBl;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToDigon;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToDe;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqOnToOffDelay;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToBlon;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqBlonToVaryBl;    ///< Panel initialization timing
+  IN UINT16     CfgLvdsMaxPixelClockFreq;         ///< The maximum pixel clock frequency supported
+  IN UINT32     CfgLcdBitDepthControlValue;       ///< The LCD bit depth control settings
+  IN UINT8      CfgLvds24bbpPanelMode;            ///< The LVDS 24 BBP mode
+  IN LVDS_MISC_CONTROL CfgLvdsMiscControl;        ///< THe LVDS Misc control
+  IN UINT16     CfgPcieRefClkSpreadSpectrum;      ///< PCIe Reference Clock Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN BOOLEAN    CfgExternalVrefCtlFeature;        ///< External Vref control
+  IN FORCE_TRAIN_MODE   CfgForceTrainMode;        ///< Force Train Mode
+  IN BOOLEAN    CfgGnbRemoteDisplaySupport;       ///< Wireless Display Support
+  IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+  IN BOOLEAN Reserved;                            ///< reserved...
+} BUILD_OPT_CFG;
+
+///  A structure containing platform specific operational characteristics. This
+///  structure is initially populated by the initializer with a copy of the same
+///  structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
+  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
+                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+  IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
+  IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
+  IN UINT32              C1ePlatformData3;            ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3}
+  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+  IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+                                                      ///< If CStateMode is CStateModeC6, this item is reserved
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+  IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+                                                      ///< can be used to allow the CPU to enter Cstates.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+  IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
+  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
+  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
+  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
+  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
+  IN PLATFORM_LOW_POWER_PSTATE_MODES  LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+  IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
+                                                      ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+  IN BOOLEAN             PStatesInHpcMode;            ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE}
+  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+  IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+  IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                      ///< essentially it enables function 1 of graphics device.
+                                                      ///< @li 0 = HD Audio disable
+                                                      ///< @li 1 = HD Audio enable
+                                                      ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+  IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                      ///< characteristic specific to display panel which used by platform design.
+                                                      ///< @li 0 = ABM support disabled
+                                                      ///< @li 1 = ABM support enabled
+                                                      ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+  IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
+                                                      ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+  IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
+                                                      ///< If equal to 0 backlight not controlled by iGPU
+                                                      ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+
+/*  Interface Parameter Structures  */
+/// DMI Type4 - Processor ID
+typedef struct {
+  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
+  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+  OUT UINT8                     T4ProcType;             ///< CPU Type
+  OUT UINT8                     T4ProcFamily;           ///< Family 1
+  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
+  OUT UINT8                     T4Voltage;              ///< Voltage
+  OUT UINT16                    T4ExternalClock;        ///< External clock
+  OUT UINT16                    T4MaxSpeed;             ///< Max speed
+  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
+  OUT UINT8                     T4Status;               ///< Status
+  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
+  OUT UINT8                     T4CoreCount;            ///< Core count
+  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
+  OUT UINT8                     T4ThreadCount;          ///< Thread count
+  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
+  OUT UINT16                    T4ProcFamily2;          ///< Family 2
+  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
+  OUT UINT16                    T7MaxCacheSize;         ///< Max size
+  OUT UINT16                    T7InstallSize;          ///< Install size
+  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
+  OUT UINT16                    T7CurrentSramType;      ///< Current type
+  OUT UINT8                     T7CacheSpeed;           ///< Speed
+  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
+  OUT UINT8                     T7SystemCacheType;      ///< Cache type
+  OUT UINT8                     T7Associativity;        ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
+                                                        ///< for the array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+  OUT UINT64                    ExtMaxCapacity;         ///< The maximum memory capacity, in bytes,
+                                                        ///< for this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType                                           ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Reserved2:3;            ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[19];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 and 20 - for memory use
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
+  OUT UINT8                     PartNumber[18];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
+  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
+  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
+  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
+  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call:  AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS    3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
+  IN OUT   UINT32               ExeCacheSize;           ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call:  AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
+     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  );
+
+/// Selection type for core leveling
+typedef enum {
+  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
+  CORE_LEVEL_TWO,               ///< Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
+  CORE_LEVEL_NONE,              ///< Do no leveling
+  CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
+  CORE_LEVEL_ONE,               ///< Level to 1 core
+  CORE_LEVEL_THREE,             ///< Level to 3 cores
+  CORE_LEVEL_FOUR,              ///< Level to 4 cores
+  CORE_LEVEL_FIVE,              ///< Level to 5 cores
+  CORE_LEVEL_SIX,               ///< Level to 6 cores
+  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
+  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
+  CORE_LEVEL_NINE,              ///< Level to 9 cores
+  CORE_LEVEL_TEN,               ///< Level to 10 cores
+  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
+  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
+  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
+  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
+  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
+  CoreLevelModeMax              ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ *  AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call:  AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
+  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
+  IN       FCH_RESET_INTERFACE       FchInterface;     ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS     *ResetParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
+  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
+  IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
+  IN       FCH_INTERFACE          FchInterface;         ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS       *EnvParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS       *MidParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
+  IN       IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;   ///< Pointer to array of exclusion ranges
+     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
+     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
+     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
+     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
+     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
+     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
+     OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
+     OUT   VOID                   *AcpiIvrs;              ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS      *LateParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
+  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
+  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
+  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS    *ResumeParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call:  AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Core's Socket.
+  IN       UINT8             Core;             ///< The Core id.
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
+     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call:  AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Processor's socket
+  IN       UINT8             Module;           ///< The Module in that Processor
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
+     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT8             Socket;            ///< The current Core's Socket
+     OUT   UINT8             Module;            ///< The current Core's Processor Module
+     OUT   UINT8             Core;              ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call:  AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
+     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
+     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
+  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
+  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
+  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  );
+
+
+#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
+  AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
+  AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
+  AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+  AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
+  AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
+
+  AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
+
+  AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
+
+  AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
+  AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
+  AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
+  AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
+  AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
+
+  AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
+  AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f15/AMD.h b/src/vendorcode/amd/agesa/f15/AMD.h
new file mode 100644
index 0000000..d1092c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/AMD.h
@@ -0,0 +1,480 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION  "Arch2008"
+#define AGESA_ID        "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY          0xFFFFFFFF
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
+                                 ///<  Not logged.
+  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
+                                 ///< Example, memory address not installed, heap buffer handle not found.
+                                 ///< Not Logged.
+  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
+                                 ///<  See log.  Example, HT CRC.
+  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
+  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
+  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
+                                 ///< may not be able to reliably produce log events.
+  AgesaStatusMax                 ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in]        Function      The specific callout function being invoked.
+ * @param[in]        FcnData       Function specific data item.
+ * @param[in,out]    ConfigPtr     Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+  IN       UINT32  Function,
+  IN       UINTN   FcnData,
+  IN OUT   VOID    *ConfigPtr
+  );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+  // AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
+  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
+  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
+  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
+  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
+  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
+  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
+  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
+  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
+  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
+  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
+  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
+  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
+  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
+  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
+  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
+  AMD_GET_EXECACHE_SIZE,                                    ///< AmdGetAvailableExeCacheSize general service handle
+  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
+  AMD_IDENTIFY_DIMMS                                        ///< AmdIdentifyDimm general service handle
+} AGESA_STRUCT_NAME;
+
+  /*  ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       UINT32          Func;             ///< The service desired
+  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
+  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
+  IN       UINT64          HeapBasePtr;      ///< Location of the heap
+  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
+  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
+  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
+  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
+                                                   ///< The struct to init for ByHost allocation,
+                                                   ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+/// AGESA Binary module header structure
+typedef struct {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE  {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+  IN  CHAR8   Signature[8];                       ///< code header Signature
+  IN  CHAR8   ComponentName[8];                   ///< 8 character name of the code module
+  IN  CHAR8   Version[12];                        ///< 12 character version string
+  IN  CHAR8   TerminatorNull;                     ///< null terminated string
+  IN  CHAR8   VerReserved[7];                     ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct {
+  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
+  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
+  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
+  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX                                ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/f15/Dispatcher.h b/src/vendorcode/amd/agesa/f15/Dispatcher.h
new file mode 100644
index 0000000..b99ae77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Dispatcher.h
@@ -0,0 +1,52 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h
new file mode 100644
index 0000000..6860897
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h
@@ -0,0 +1,167 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 52180 $   @e \$Date: 2011-05-03 05:17:25 -0600 (Tue, 03 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ *                           HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  );
+
+/*----------------------------------------------------------------------------
+ *                        HT Recovery   FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+///----------------------------------------------------------------------------
+///                          MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
+  );
+
+VOID
+memDefRet ( VOID );
+
+BOOLEAN
+memDefTrue ( VOID );
+
+BOOLEAN
+memDefFalse ( VOID );
+
+VOID
+MemRecDefRet ( VOID );
+
+BOOLEAN
+MemRecDefTrue ( VOID );
+
+#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h
new file mode 100644
index 0000000..b59de4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default".  Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 54372 $   @e \$Date: 2011-06-07 22:22:22 -0600 (Tue, 07 Jun 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+
+/**
+* Return True
+*
+* @retval True    Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue ( VOID );
+
+/**
+* Return False.
+*
+* @retval FALSE    Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse ( VOID );
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 ( VOID );
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 ( VOID );
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 ( VOID );
+
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL ( VOID );
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess ( VOID );
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid ( VOID );
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert ( VOID );
+
+#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/Filecode.h b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
new file mode 100644
index 0000000..0d9f67a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
@@ -0,0 +1,1174 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 56033 $   @e \$Date: 2011-07-06 01:12:20 -0600 (Wed, 06 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE                          (0xA001)
+#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE                   (0xA002)
+#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE                   (0xA003)
+#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE                              (0xA004)
+#define PROC_GNB_GFX_GFXGMCINIT_FILECODE                                 (0xA006)
+#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE                           (0xA010)
+#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE                           (0xA011)
+#define PROC_GNB_GFX_GFXINITATPOST_FILECODE                              (0xA012)
+#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE                 (0xA013)
+#define PROC_GNB_GFX_GFXLIB_FILECODE                                     (0xA014)
+#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE                             (0xA015)
+#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE                              (0xA016)
+#define PROC_GNB_GNBINITATEARLY_FILECODE                                 (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE                                   (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE                                  (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE                                   (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE                                  (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE                                 (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE                    (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE              (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE                (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE               (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE              (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE                 (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE              (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE            (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE      (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE      (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE          (0xA034)
+#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE                 (0xA035)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE           (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE            (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE          (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE          (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE              (0xA03A)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE     (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE   (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE       (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE       (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE        (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE      (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE         (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE   (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE             (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE  (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE        (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE     (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE         (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE      (0xA04B)
+#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE                  (0xA04C)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE                   (0xA04D)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE                        (0xA04E)
+#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE                (0xA04F)
+#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE                    (0xA050)
+#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE                     (0xA051)
+#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE                          (0xA052)
+#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE                         (0xA053)
+#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE                           (0xA054)
+#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE                    (0xA055)
+#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE                      (0xA056)
+#define PROC_GNB_NB_NBCONFIGDATA_FILECODE                                (0xA060)
+#define PROC_GNB_NB_NBINIT_FILECODE                                      (0xA061)
+#define PROC_GNB_NB_NBINITATEARLY_FILECODE                               (0xA062)
+#define PROC_GNB_NB_NBINITATENV_FILECODE                                 (0xA063)
+#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE                            (0xA070)
+#define PROC_GNB_NB_NBINITATPOST_FILECODE                                (0xA071)
+#define PROC_GNB_NB_NBINITATRESET_FILECODE                               (0xA072)
+#define PROC_GNB_NB_NBPOWERMGMT_FILECODE                                 (0xA073)
+#define PROC_GNB_NB_NBSMULIB_FILECODE                                    (0xA074)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE                   (0xA075)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE          (0xA076)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE        (0xA077)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE            (0xA078)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE            (0xA079)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE        (0xA07A)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE                     (0xA07D)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE            (0xA07E)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE          (0xA07F)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE              (0xA080)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE              (0xA081)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE          (0xA082)
+#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE                     (0xA083)
+#define PROC_GNB_PCIE_PCIEINIT_FILECODE                                  (0xA084)
+#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE                       (0xA085)
+#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE                             (0xA086)
+#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE                        (0xA087)
+#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE                            (0xA088)
+#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE                              (0xA089)
+#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE                              (0xA08B)
+#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE                          (0xA08C)
+#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE              (0xA08D)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE              (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE             (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE                      (0xA090)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE        (0xA091)
+#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE                 (0xA092)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE              (0xA093)
+#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE                 (0xA094)
+#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE     (0xA095)
+#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE                     (0xA096)
+#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE                 (0xA097)
+#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE                (0xA098)
+#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE               (0xA09A)
+#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE                 (0xA09B)
+#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE               (0xA09C)
+#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE                 (0xA09D)
+#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE                (0xA09E)
+#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE             (0xA09F)
+#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE                 (0xA0A0)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE              (0xA0A1)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE                (0xA0A2)
+#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE                    (0xA0A3)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE                (0xA0A4)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE               (0xA0A5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
+#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE              (0xA0A7)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE                  (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE          (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE   (0xA0AA)
+#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE               (0xA0AB)
+#define PROC_GNB_GFX_FAMILY_KR_KRGFXSERVICES_FILECODE                    (0xA0AC)
+#define PROC_GNB_NB_FAMILY_KR_KRNBSMU_FILECODE                           (0xA0AD)
+#define PROC_GNB_NB_FAMILY_KR_KRNBPOWERGATE_FILECODE                     (0xA0AE)
+#define PROC_GNB_NB_FAMILY_KR_KRNBSERVICES_FILECODE                      (0xA0AF)
+#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKNCLKRATIO_FILECODE                 (0xA0B0)
+#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKDPM_FILECODE                       (0xA0B1)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEALIB_FILECODE                      (0xA0B2)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXCONFIG_FILECODE             (0xA0B3)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXSERVICES_FILECODE           (0xA0B4)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPHYSERVICES_FILECODE               (0xA0B5)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEWRAPPERSERVICES_FILECODE           (0xA0B6)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPIFSERVICES_FILECODE               (0xA0B7)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE              (0xA0B8)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTN_FILECODE                   (0xA0B9)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE                     (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE                      (0xA0BB)
+#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE            (0xA0BC)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBSTALL_FILECODE               (0xA0BD)
+#define PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE            (0xA0BE)
+#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE            (0xA0BF)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE             (0xA0C0)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE     (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE     (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE    (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE       (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE          (0xA0CB)
+
+#define PROC_GNB_MODULES_GNBINITKM_GNBEARLYINITKM_FILECODE               (0xA0CC)
+#define PROC_GNB_MODULES_GNBINITKM_GNBENVINITKM_FILECODE                 (0xA0CD)
+#define PROC_GNB_MODULES_GNBINITKM_GNBIOMMUIVRSKM_FILECODE               (0xA0CE)
+#define PROC_GNB_MODULES_GNBINITKM_GNBMIDINITKM_FILECODE                 (0xA0CF)
+#define PROC_GNB_MODULES_GNBINITKM_GNBPOSTINITKM_FILECODE                (0xA0D0)
+#define PROC_GNB_MODULES_GNBINITKM_GNBREGISTERACCKM_FILECODE             (0xA0D1)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMC2012_FILECODE       (0xA0D2)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMFM2_FILECODE         (0xA0D3)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMG2012_FILECODE       (0xA0D4)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECONFIGKM_FILECODE                 (0xA0D5)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEEARLYINITKM_FILECODE              (0xA0D6)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEENVINITKM_FILECODE                (0xA0D7)
+#define PROC_GNB_MODULES_GNBINITKM_PCIELIBKM_FILECODE                    (0xA0D8)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEMIDINITKM_FILECODE                (0xA0D9)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEPOSTINITKM_FILECODE               (0xA0DA)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE       (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE       (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE    (0xA0DD)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                           (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                        (0xAE02)
+
+// FCH
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE                             (0xB001)
+#define PROC_FCH_AZALIA_AZALIAENV_FILECODE                               (0xB002)
+#define PROC_FCH_AZALIA_AZALIAMID_FILECODE                               (0xB003)
+#define PROC_FCH_AZALIA_AZALIALATE_FILECODE                              (0xB004)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE                                 (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE                                  (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE                               (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE                            (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE                                  (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE                                  (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE                                (0xB016)
+#define PROC_FCH_GEC_GECRESET_FILECODE                                   (0xB020)
+#define PROC_FCH_GEC_GECENV_FILECODE                                     (0xB021)
+#define PROC_FCH_GEC_GECMID_FILECODE                                     (0xB022)
+#define PROC_FCH_GEC_GECLATE_FILECODE                                    (0xB023)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE           (0xB024)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE        (0xB025)
+#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECSERVICE_FILECODE                 (0xB026)
+#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECENVSERVICE_FILECODE              (0xB027)
+#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE                             (0xB030)
+#define PROC_FCH_HWACPI_HWACPIENV_FILECODE                               (0xB031)
+#define PROC_FCH_HWACPI_HWACPIMID_FILECODE                               (0xB032)
+#define PROC_FCH_HWACPI_HWACPILATE_FILECODE                              (0xB033)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE  (0xB034)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE  (0xB035)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE         (0xB037)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIENVSERVICE_FILECODE        (0xB038)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIMIDSERVICE_FILECODE        (0xB039)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPILATESERVICE_FILECODE       (0xB03A)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBASSSERVICE_FILECODE               (0xB03B)
+#define PROC_FCH_HWM_HWMRESET_FILECODE                                   (0xB040)
+#define PROC_FCH_HWM_HWMENV_FILECODE                                     (0xB041)
+#define PROC_FCH_HWM_HWMMID_FILECODE                                     (0xB042)
+#define PROC_FCH_HWM_HWMLATE_FILECODE                                    (0xB043)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE        (0xB044)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE        (0xB045)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE       (0xB046)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMENVSERVICE_FILECODE              (0xB047)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMMIDSERVICE_FILECODE              (0xB048)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMLATESERVICE_FILECODE             (0xB049)
+#define PROC_FCH_IDE_IDEENV_FILECODE                                     (0xB050)
+#define PROC_FCH_IDE_IDEMID_FILECODE                                     (0xB051)
+#define PROC_FCH_IDE_IDELATE_FILECODE                                    (0xB052)
+#define PROC_FCH_IMC_IMCENV_FILECODE                                     (0xB060)
+#define PROC_FCH_IMC_IMCMID_FILECODE                                     (0xB061)
+#define PROC_FCH_IMC_IMCLATE_FILECODE                                    (0xB062)
+#define PROC_FCH_IMC_IMCLIB_FILECODE                                     (0xB063)
+#define PROC_FCH_IMC_IMCRESET_FILECODE                                   (0xB064)
+#define PROC_FCH_IMC_FCHECENV_FILECODE                                   (0xB065)
+#define PROC_FCH_IMC_FCHECMID_FILECODE                                   (0xB066)
+#define PROC_FCH_IMC_FCHECLATE_FILECODE                                  (0xB067)
+#define PROC_FCH_IMC_FCHECRESET_FILECODE                                 (0xB068)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE           (0xB069)
+#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE                 (0xB06A)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE                         (0xB070)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE                           (0xB071)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE                         (0xB072)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE                           (0xB073)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE                          (0xB074)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE                           (0xB075)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE                            (0xB076)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE                      (0xB077)
+#define PROC_FCH_IR_IRENV_FILECODE                                       (0xB080)
+#define PROC_FCH_IR_IRMID_FILECODE                                       (0xB081)
+#define PROC_FCH_IR_IRLATE_FILECODE                                      (0xB082)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE                                 (0xB090)
+#define PROC_FCH_PCIB_PCIBENV_FILECODE                                   (0xB091)
+#define PROC_FCH_PCIB_PCIBMID_FILECODE                                   (0xB092)
+#define PROC_FCH_PCIB_PCIBLATE_FILECODE                                  (0xB093)
+#define PROC_FCH_PCIE_ABRESET_FILECODE                                   (0xB0A0)
+#define PROC_FCH_PCIE_ABENV_FILECODE                                     (0xB0A1)
+#define PROC_FCH_PCIE_ABMID_FILECODE                                     (0xB0A2)
+#define PROC_FCH_PCIE_ABLATE_FILECODE                                    (0xB0A3)
+#define PROC_FCH_PCIE_GPPHP_FILECODE                                     (0xB0A4)
+#define PROC_FCH_PCIE_GPPLIB_FILECODE                                    (0xB0A5)
+#define PROC_FCH_PCIE_GPPRESET_FILECODE                                  (0xB0A6)
+#define PROC_FCH_PCIE_GPPENV_FILECODE                                    (0xB0A7)
+#define PROC_FCH_PCIE_GPPMID_FILECODE                                    (0xB0A8)
+#define PROC_FCH_PCIE_GPPLATE_FILECODE                                   (0xB0A9)
+#define PROC_FCH_PCIE_PCIERESET_FILECODE                                 (0xB0AA)
+#define PROC_FCH_PCIE_PCIEENV_FILECODE                                   (0xB0AB)
+#define PROC_FCH_PCIE_PCIEMID_FILECODE                                   (0xB0AC)
+#define PROC_FCH_PCIE_PCIELATE_FILECODE                                  (0xB0AD)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE      (0xB0AE)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE        (0xB0AF)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE           (0xB0B0)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE     (0xB0B1)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE          (0xB0B2)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE      (0xB0B3)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE         (0xB0B4)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE            (0xB0B5)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE              (0xB0B6)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE                 (0xB0B7)
+#define PROC_FCH_SATA_AHCIENV_FILECODE                                   (0xB0C0)
+#define PROC_FCH_SATA_AHCIMID_FILECODE                                   (0xB0C1)
+#define PROC_FCH_SATA_AHCILATE_FILECODE                                  (0xB0C2)
+#define PROC_FCH_SATA_AHCILIB_FILECODE                                   (0xB0C3)
+#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE                               (0xB0C4)
+#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE                               (0xB0C5)
+#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE                              (0xB0C6)
+#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE                               (0xB0C7)
+#define PROC_FCH_SATA_RAIDENV_FILECODE                                   (0xB0C8)
+#define PROC_FCH_SATA_RAIDMID_FILECODE                                   (0xB0C9)
+#define PROC_FCH_SATA_RAIDLATE_FILECODE                                  (0xB0CA)
+#define PROC_FCH_SATA_RAIDLIB_FILECODE                                   (0xB0CB)
+#define PROC_FCH_SATA_SATAENV_FILECODE                                   (0xB0CC)
+#define PROC_FCH_SATA_SATAENVLIB_FILECODE                                (0xB0CD)
+#define PROC_FCH_SATA_SATAIDEENV_FILECODE                                (0xB0CE)
+#define PROC_FCH_SATA_SATAIDEMID_FILECODE                                (0xB0CF)
+#define PROC_FCH_SATA_SATAIDELATE_FILECODE                               (0xB0D0)
+#define PROC_FCH_SATA_SATAIDELIB_FILECODE                                (0xB0D1)
+#define PROC_FCH_SATA_SATAMID_FILECODE                                   (0xB0D2)
+#define PROC_FCH_SATA_SATALATE_FILECODE                                  (0xB0D3)
+#define PROC_FCH_SATA_SATALIB_FILECODE                                   (0xB0D4)
+#define PROC_FCH_SATA_SATARESET_FILECODE                                 (0xB0D5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE    (0xB0D6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE      (0xB0D7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE         (0xB0D8)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE          (0xB0D9)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE            (0xB0DA)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE               (0xB0DB)
+#define PROC_FCH_SD_SDENV_FILECODE                                       (0xB0E0)
+#define PROC_FCH_SD_SDMID_FILECODE                                       (0xB0E1)
+#define PROC_FCH_SD_SDLATE_FILECODE                                      (0xB0E2)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE             (0xB0E3)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE        (0xB0E4)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE          (0xB0E5)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDSERVICE_FILECODE                   (0xB0E6)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDRESETSERVICE_FILECODE              (0xB0E7)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDENVSERVICE_FILECODE                (0xB0E8)
+#define PROC_FCH_SPI_LPCRESET_FILECODE                                   (0xB0F0)
+#define PROC_FCH_SPI_LPCENV_FILECODE                                     (0xB0F1)
+#define PROC_FCH_SPI_LPCMID_FILECODE                                     (0xB0F2)
+#define PROC_FCH_SPI_LPCLATE_FILECODE                                    (0xB0F3)
+#define PROC_FCH_SPI_SPIRESET_FILECODE                                   (0xB0F4)
+#define PROC_FCH_SPI_SPIENV_FILECODE                                     (0xB0F5)
+#define PROC_FCH_SPI_SPIMID_FILECODE                                     (0xB0F6)
+#define PROC_FCH_SPI_SPILATE_FILECODE                                    (0xB0F7)
+#define PROC_FCH_USB_EHCIRESET_FILECODE                                  (0xB100)
+#define PROC_FCH_USB_EHCIENV_FILECODE                                    (0xB101)
+#define PROC_FCH_USB_EHCIMID_FILECODE                                    (0xB102)
+#define PROC_FCH_USB_EHCILATE_FILECODE                                   (0xB103)
+#define PROC_FCH_USB_OHCIRESET_FILECODE                                  (0xB104)
+#define PROC_FCH_USB_OHCIENV_FILECODE                                    (0xB105)
+#define PROC_FCH_USB_OHCIMID_FILECODE                                    (0xB106)
+#define PROC_FCH_USB_OHCILATE_FILECODE                                   (0xB107)
+#define PROC_FCH_USB_USBRESET_FILECODE                                   (0xB108)
+#define PROC_FCH_USB_USBENV_FILECODE                                     (0xB109)
+#define PROC_FCH_USB_USBMID_FILECODE                                     (0xB10A)
+#define PROC_FCH_USB_USBLATE_FILECODE                                    (0xB10B)
+#define PROC_FCH_USB_XHCIRESET_FILECODE                                  (0xB10C)
+#define PROC_FCH_USB_XHCIENV_FILECODE                                    (0xB10D)
+#define PROC_FCH_USB_XHCIMID_FILECODE                                    (0xB10E)
+#define PROC_FCH_USB_XHCILATE_FILECODE                                   (0xB10F)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE       (0xB110)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE       (0xB111)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE      (0xB112)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE       (0xB113)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE       (0xB114)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE      (0xB115)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE     (0xB116)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE       (0xB117)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE       (0xB118)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE      (0xB119)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIENVSERVICE_FILECODE          (0xB11A)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIMIDSERVICE_FILECODE          (0xB11B)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCILATESERVICE_FILECODE         (0xB11C)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIENVSERVICE_FILECODE          (0xB11D)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIMIDSERVICE_FILECODE          (0xB11E)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCILATESERVICE_FILECODE         (0xB11F)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIRESETSERVICE_FILECODE        (0xB120)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIENVSERVICE_FILECODE          (0xB121)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIMIDSERVICE_FILECODE          (0xB122)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCILATESERVICE_FILECODE         (0xB123)
+#define PROC_FCH_USB_XHCIRECOVERY_FILECODE                            (0xB124)
+#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE                            (0xB125)
+
+#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE                              (0xB200)
+#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE                              (0xB220)
+#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE                     (0xB221)
+#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE                       (0xB222)
+#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE                (0xB230)
+#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE                          (0xB240)
+#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE              (0xB250)
+#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE                 (0xB251)
+#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE                        (0xB252)
+#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE                              (0xB260)
+#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE                               (0xB261)
+#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE                               (0xB262)
+#define UEFI_PEI_FCHPEI_LIBAMDPEI_FILECODE                              (0xB263)
+#define UEFI_PEI_SMBUS_SMBUS_FILECODE                                   (0xB270)
+#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE                              (0xB280)
+#define UEFI_SMM_FCHSMM_GPESMI_FILECODE                                (0xB282)
+#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE                             (0xB283)
+#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE                               (0xB284)
+#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE                      (0xB285)
+#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE                        (0xB286)
+#define UEFI_SMM_FCHSMM_SWSMI_FILECODE                                 (0xB287)
+#define UEFI_SMM_FCHSMM_SXSMI_FILECODE                                 (0xB288)
+#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE                               (0xB2A0)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE                     (0xB290)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE        (0xB292)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE  (0xB293)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE      (0xB294)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE  (0xB296)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE          (0xB297)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE          (0xB298)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE        (0xB299)
+
+#define LIB_AMDLIB_FILECODE                                              (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE            (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE                (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE      (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE                (0xC142)
+#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE                               (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
+#define PROC_CPU_CPUBRANDID_FILECODE                                     (0xC402)
+#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE                              (0xC409)
+#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
+#define PROC_CPU_S3_FILECODE                                             (0xC460)
+
+// Family 10h
+#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE              (0xC801)
+#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE                      (0xC802)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE                (0xC803)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE             (0xC804)
+#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE                          (0xC805)
+#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE                    (0xC806)
+#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE              (0xC807)
+#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE                  (0xC808)
+#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE                    (0xC809)
+#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE                    (0xC80A)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE                   (0xC80B)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE        (0xC80C)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE                   (0xC80D)
+#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE              (0xC80E)
+#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE                    (0xC80F)
+#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE           (0xC810)
+#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE                       (0xC811)
+#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE                          (0xC812)
+#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE             (0xC813)
+#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE                  (0xC820)
+#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE             (0xC821)
+#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE              (0xC822)
+#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE                  (0xC823)
+#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE                 (0xC824)
+#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE                  (0xC825)
+#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE          (0xC826)
+#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE                        (0xC827)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE              (0xC830)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE                  (0xC831)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE                  (0xC832)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE              (0xC833)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE              (0xC834)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE            (0xC835)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE           (0xC836)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE       (0xC837)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE  (0xC838)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE             (0xC839)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE      (0xC83A)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE             (0xC83B)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE      (0xC83C)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE           (0xC83D)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE       (0xC83E)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE  (0xC83F)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE             (0xC840)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE      (0xC841)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE             (0xC842)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE      (0xC843)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE           (0xC844)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE       (0xC845)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE  (0xC846)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE             (0xC847)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE      (0xC848)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE             (0xC849)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE              (0xC850)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE            (0xC851)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE             (0xC852)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE           (0xC853)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE        (0xC854)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE       (0xC855)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE  (0xC856)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE             (0xC857)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE      (0xC858)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE             (0xC859)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE              (0xC860)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE              (0xC861)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE              (0xC862)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE            (0xC863)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE      (0xC864)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE           (0xC865)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE       (0xC866)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE  (0xC867)
+
+// Family 12h
+#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE              (0xC901)
+#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE                      (0xC902)
+#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE                (0xC903)
+#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE                          (0xC904)
+#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE                    (0xC905)
+#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE            (0xC906)
+#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE                    (0xC907)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE                   (0xC908)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE        (0xC909)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE                   (0xC90A)
+#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE              (0xC90B)
+#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE                    (0xC90C)
+#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE           (0xC90D)
+#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE                       (0xC90E)
+#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE                         (0xC90F)
+#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE                             (0xC910)
+#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE                        (0xC911)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE            (0xC921)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE       (0xC922)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE           (0xC923)
+#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE             (0xC924)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE               (0xC925)
+
+// Family 14h
+#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE              (0xCA01)
+#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE                      (0xCA02)
+#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE                (0xCA03)
+#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE                          (0xCA04)
+#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE                    (0xCA05)
+#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE                    (0xCA06)
+#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE                    (0xCA07)
+#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE           (0xCA08)
+#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0xCA09)
+#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE                        (0xCA0A)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA0B)
+
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE                 (0xCA21)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE                    (0xCA22)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA23)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA24)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA25)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE             (0xCA26)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE               (0xCA27)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE                  (0xCA28)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE                  (0xCA29)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE      (0xCA2A)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE               (0xCA2B)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE                        (0xCA2C)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE            (0xCA2D)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE                 (0xCA2E)
+
+#define PROC_CPU_FAMILY_0X14_KR_F14KREQUIVALENCETABLE_FILECODE           (0xCA41)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRINITEARLYTABLE_FILECODE             (0xCA42)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRLOGICALIDTABLES_FILECODE            (0xCA43)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRMICROCODEPATCHTABLES_FILECODE       (0xCA44)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRCPB_FILECODE                        (0xCA45)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRC6STATE_FILECODE                    (0xCA46)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRUTILITIES_FILECODE                  (0xCA47)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERPLANE_FILECODE                 (0xCA48)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERMGMTSYSTEMTABLES_FILECODE      (0xCA49)
+#define PROC_CPU_FAMILY_0X14_KR_F14KREARLYNBPSTATEINIT_FILECODE          (0xCA4A)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRMSRTABLES_FILECODE                  (0xCA4B)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPCITABLES_FILECODE                  (0xCA4C)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRSOFTWARETHERMAL_FILECODE            (0xCA4D)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERCHECK_FILECODE                 (0xCA4E)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE              (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE                      (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE                (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE                          (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE                    (0xCB05)
+#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE                    (0xCB06)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE                   (0xCB07)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE                    (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE           (0xCB09)
+#define PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE                   (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE                          (0xCB0B)
+
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE          (0xCB20)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE                     (0xCB21)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE            (0xCB22)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE                  (0xCB23)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE                 (0xCB24)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE                (0xCB25)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE            (0xCB26)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE       (0xCB27)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE                  (0xCB28)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE             (0xCB29)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE           (0xCB2A)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE                  (0xCB2B)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB2C)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE                 (0xCB2D)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE                  (0xCB2E)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE           (0xCB2F)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE             (0xCB30)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE               (0xCB31)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE        (0xCB32)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE         (0xCB33)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE                    (0xCB34)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE               (0xCB35)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE                        (0xCB36)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE                   (0xCB37)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE        (0xCB38)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE         (0xCB39)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE         (0xCB3A)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE             (0xCB3B)
+
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE          (0xCB50)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE                     (0xCB51)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE            (0xCB52)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE                  (0xCB53)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE            (0xCB54)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE       (0xCB55)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE                  (0xCB56)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE             (0xCB57)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE           (0xCB58)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE                  (0xCB59)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB5A)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE                 (0xCB5B)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE                  (0xCB5C)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE                    (0xCB5D)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE                        (0xCB5E)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE                   (0xCB5F)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE        (0xCB60)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNSOFTWARETHERMAL_FILECODE         (0xCB61)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE             (0xCB62)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE               (0xCB63)
+
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCOREAFTERRESET_FILECODE          (0xCB80)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMDMI_FILECODE                     (0xCB81)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMNBAFTERRESET_FILECODE            (0xCB82)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMPSTATE_FILECODE                  (0xCB83)
+#define PROC_CPU_FAMILY_0X15_KM_F15KML3FEATURES_FILECODE                 (0xCB84)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMSGBASEDC1E_FILECODE                (0xCB85)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMLOGICALIDTABLES_FILECODE            (0xCB86)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMICROCODEPATCHTABLES_FILECODE       (0xCB87)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMSRTABLES_FILECODE                  (0xCB88)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMSHAREDMSRTABLE_FILECODE             (0xCB89)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMEQUIVALENCETABLE_FILECODE           (0xCB8A)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPCITABLES_FILECODE                  (0xCB8B)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB8C)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERPLANE_FILECODE                 (0xCB8D)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMUTILITIES_FILECODE                  (0xCB8E)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMWORKAROUNDSTABLE_FILECODE           (0xCB8F)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPMNBCOFVIDINIT_FILECODE             (0xCB90)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMLOWPWRPSTATE_FILECODE               (0xCB91)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMSINGLELINKPCITABLES_FILECODE        (0xCB92)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMULTILINKPCITABLES_FILECODE         (0xCB93)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMC6STATE_FILECODE                    (0xCB94)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMCPB_FILECODE                        (0xCB95)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMIOCSTATE_FILECODE                   (0xCB96)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCACHEFLUSHONHALT_FILECODE        (0xCB97)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMFEATURELEVELING_FILECODE         (0xCB98)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMSOFTWARETHERMAL_FILECODE         (0xCB99)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMINITEARLYTABLE_FILECODE             (0xCB9A)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
+#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE                          (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
+#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE                               (0xDC80)
+#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE                               (0xDC81)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE                                 (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE                        (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE                            (0xDC85)
+#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE                       (0xDC86)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE                                 (0xDC87)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE                           (0xDE01)
+
+#define PROC_HT_FEATURES_HTFEATSETS_FILECODE                             (0xE001)
+#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE                 (0xE002)
+#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE                          (0xE003)
+#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE                      (0xE004)
+#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE                     (0xE005)
+#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE                          (0xE006)
+#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE                         (0xE007)
+#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE              (0xE008)
+#define PROC_HT_FEATURES_HTIDS_FILECODE                                  (0xE009)
+#define PROC_HT_HTFEAT_FILECODE                                          (0xE021)
+#define PROC_HT_HTINTERFACE_FILECODE                                     (0xE022)
+#define PROC_HT_HTINTERFACECOHERENT_FILECODE                             (0xE023)
+#define PROC_HT_HTINTERFACEGENERAL_FILECODE                              (0xE024)
+#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE                          (0xE025)
+#define PROC_HT_HTMAIN_FILECODE                                          (0xE026)
+#define PROC_HT_HTNOTIFY_FILECODE                                        (0xE027)
+#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE                                 (0xE028)
+#define PROC_HT_HTNB_FILECODE                                            (0xE081)
+#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE                           (0xE082)
+#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE                        (0xE083)
+#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE                       (0xE084)
+#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE                          (0xE085)
+#define PROC_HT_FAM10_HTNBFAM10_FILECODE                                 (0xE0C1)
+#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE                         (0xE0C2)
+#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE                      (0xE0C3)
+#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE                     (0xE0C4)
+#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE                           (0xE0C5)
+#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE                        (0xE0C6)
+#define PROC_HT_FAM12_HTNBFAM12_FILECODE                                 (0xE101)
+#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE                        (0xE102)
+#define PROC_HT_FAM14_HTNBFAM14_FILECODE                                 (0xE141)
+#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE                        (0xE142)
+#define PROC_HT_FAM15_HTNBFAM15_FILECODE                                 (0xE181)
+#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE                         (0xE182)
+#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE                      (0xE183)
+#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE                     (0xE184)
+#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE                           (0xE185)
+#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE                        (0xE186)
+#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE                       (0xE187)
+#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE              (0xE188)
+#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE                       (0xE189)
+#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE              (0xE18A)
+#define PROC_HT_FAM15MOD2X_HTNBFAM15MOD2X_FILECODE                             (0xE191)
+#define PROC_HT_FAM15MOD2X_HTNBCOHERENTFAM15MOD2X_FILECODE                     (0xE192)
+#define PROC_HT_FAM15MOD2X_HTNBNONCOHERENTFAM15MOD2X_FILECODE                  (0xE193)
+#define PROC_HT_FAM15MOD2X_HTNBOPTIMIZATIONFAM15MOD2X_FILECODE                 (0xE194)
+#define PROC_HT_FAM15MOD2X_HTNBSYSTEMFAM15MOD2X_FILECODE                       (0xE195)
+#define PROC_HT_FAM15MOD2X_HTNBUTILITIESFAM15MOD2X_FILECODE                    (0xE196)
+
+#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE                         (0xE302)
+#define PROC_RECOVERY_HT_HTINITRESET_FILECODE                            (0xE301)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE                                 (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
+#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE                   (0xE805)
+#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE                 (0xE806)
+#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE                 (0xE807)
+#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE                 (0xE808)
+#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE                 (0xE809)
+#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE                   (0xE80A)
+#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE                   (0xE80B)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE                   (0xE80C)
+#define PROC_IDS_FAMILY_0X14_KR_IDSF14KRALLSERVICE_FILECODE              (0xE80D)
+#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE              (0xE80E)
+#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE              (0xE80F)
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE                              (0xE810)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE                              (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE                            (0xE81F)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
+#define PROC_MEM_ARDK_DR_MARDR2_FILECODE                             (0xF002)
+#define PROC_MEM_ARDK_DR_MARDR3_FILECODE                             (0xF003)
+#define PROC_MEM_ARDK_HY_MARHY3_FILECODE                             (0xF004)
+#define PROC_MEM_ARDK_LN_MASLN3_FILECODE                             (0xF005)
+#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE                             (0xF006)
+#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE                             (0xF007)
+#define PROC_MEM_ARDK_LN_MAULN3_FILECODE                             (0xF008)
+#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE                             (0xF009)
+#define PROC_MEM_ARDK_DA_MASDA2_FILECODE                             (0xF00A)
+#define PROC_MEM_ARDK_DA_MASDA3_FILECODE                             (0xF00B)
+#define PROC_MEM_ARDK_NI_MASNI3_FILECODE                             (0xF00C)
+#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE                          (0xF00D)
+#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE                          (0xF00E)
+#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE                             (0xF00F)
+#define PROC_MEM_ARDK_ON_MASON3_FILECODE                             (0xF010)
+#define PROC_MEM_ARDK_ON_MAUON3_FILECODE                             (0xF011)
+#define PROC_MEM_ARDK_PH_MASPH3_FILECODE                             (0xF012)
+#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE                             (0xF013)
+#define PROC_MEM_ARDK_OR_MAROR3_FILECODE                             (0xF014)
+#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE                             (0xF017)
+#define PROC_MEM_ARDK_RB_MASRB3_FILECODE                             (0xF018)
+#define PROC_MEM_ARDK_RB_MAURB3_FILECODE                             (0xF019)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE                     (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE                         (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE                         (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
+#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE                           (0xF107)
+#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE                           (0xF108)
+#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE                           (0xF109)
+#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE                           (0xF10A)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
+#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE                           (0xF111)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
+#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE                         (0xF114)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
+#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE                           (0xF119)
+#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE                           (0xF11A)
+#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE                           (0xF11B)
+#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE                           (0xF11C)
+#define PROC_MEM_MAIN_KR_MMFLOWKR_FILECODE                           (0xF11D)
+
+#define PROC_MEM_NB_DR_MNDR_FILECODE                                 (0XF213)
+#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE                             (0XF214)
+#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE                         (0XF216)
+#define PROC_MEM_NB_DR_MNMCTDR_FILECODE                              (0XF217)
+#define PROC_MEM_NB_DR_MNDCTDR_FILECODE                              (0XF218)
+#define PROC_MEM_NB_DR_MNOTDR_FILECODE                               (0XF219)
+#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE                         (0XF21A)
+#define PROC_MEM_NB_DR_MNPROTODR_FILECODE                            (0XF21C)
+#define PROC_MEM_NB_DR_MNS3DR_FILECODE                               (0XF21D)
+#define PROC_MEM_NB_DR_MNREGDR_FILECODE                              (0XF21E)
+#define PROC_MEM_NB_RB_MNRB_FILECODE                                 (0XF220)
+#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE                             (0XF221)
+#define PROC_MEM_NB_RB_MNS3RB_FILECODE                               (0XF222)
+#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE                         (0XF223)
+#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE                             (0XF233)
+#define PROC_MEM_NB_HY_MNHY_FILECODE                                 (0XF235)
+#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE                         (0XF236)
+#define PROC_MEM_NB_HY_MNMCTHY_FILECODE                              (0XF237)
+#define PROC_MEM_NB_HY_MNDCTHY_FILECODE                              (0XF238)
+#define PROC_MEM_NB_HY_MNOTHY_FILECODE                               (0XF239)
+#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE                         (0XF23A)
+#define PROC_MEM_NB_HY_MNPHYHY_FILECODE                              (0XF23B)
+#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE                            (0XF23C)
+#define PROC_MEM_NB_HY_MNS3HY_FILECODE                               (0XF23D)
+#define PROC_MEM_NB_HY_MNREGHY_FILECODE                              (0XF23E)
+#define PROC_MEM_NB_ON_MNON_FILECODE                                 (0xF240)
+#define PROC_MEM_NB_ON_MNREGON_FILECODE                              (0xF241)
+#define PROC_MEM_NB_ON_MNDCTON_FILECODE                              (0xF242)
+#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE                         (0xF244)
+#define PROC_MEM_NB_ON_MNMCTON_FILECODE                              (0xF245)
+#define PROC_MEM_NB_ON_MNOTON_FILECODE                               (0xF246)
+#define PROC_MEM_NB_ON_MNPHYON_FILECODE                              (0xF247)
+#define PROC_MEM_NB_ON_MNS3ON_FILECODE                               (0xF248)
+#define PROC_MEM_NB_ON_MNFLOWON_FILECODE                             (0xF249)
+#define PROC_MEM_NB_ON_MNPROTOON_FILECODE                            (0xF24A)
+#define PROC_MEM_NB_LN_MNDCTLN_FILECODE                              (0XF252)
+#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE                             (0XF253)
+#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE                         (0XF254)
+#define PROC_MEM_NB_LN_MNMCTLN_FILECODE                              (0XF255)
+#define PROC_MEM_NB_LN_MNOTLN_FILECODE                               (0XF256)
+#define PROC_MEM_NB_LN_MNPHYLN_FILECODE                              (0XF257)
+#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE                            (0XF258)
+#define PROC_MEM_NB_LN_MNLN_FILECODE                                 (0XF259)
+#define PROC_MEM_NB_LN_MNS3LN_FILECODE                               (0XF25A)
+#define PROC_MEM_NB_LN_MNREGLN_FILECODE                              (0XF25B)
+#define PROC_MEM_NB_DA_MNDA_FILECODE                                 (0XF260)
+#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE                             (0XF261)
+#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE                         (0XF263)
+#define PROC_MEM_NB_DA_MNMCTDA_FILECODE                              (0XF264)
+#define PROC_MEM_NB_DA_MNDCTDA_FILECODE                              (0XF265)
+#define PROC_MEM_NB_DA_MNOTDA_FILECODE                               (0XF266)
+#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE                         (0XF267)
+#define PROC_MEM_NB_DA_MNPROTODA_FILECODE                            (0XF269)
+#define PROC_MEM_NB_DA_MNS3DA_FILECODE                               (0XF26A)
+#define PROC_MEM_NB_DA_MNREGDA_FILECODE                              (0XF26B)
+#define PROC_MEM_NB_C32_MNC32_FILECODE                               (0XF26C)
+#define PROC_MEM_NB_C32_MNDCTC32_FILECODE                            (0XF26D)
+#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE                           (0XF26E)
+#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE                       (0XF26F)
+#define PROC_MEM_NB_C32_MNMCTC32_FILECODE                            (0XF270)
+#define PROC_MEM_NB_C32_MNOTC32_FILECODE                             (0XF271)
+#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE                       (0XF272)
+#define PROC_MEM_NB_C32_MNPHYC32_FILECODE                            (0XF273)
+#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE                          (0XF274)
+#define PROC_MEM_NB_C32_MNS3C32_FILECODE                             (0XF275)
+#define PROC_MEM_NB_C32_MNREGC32_FILECODE                            (0XF277)
+#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
+#define PROC_MEM_NB_MNTRAIN2_FILECODE                                (0XF283)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
+#define PROC_MEM_NB_NI_MNNI_FILECODE                                 (0XF286)
+#define PROC_MEM_NB_NI_MNS3NI_FILECODE                               (0XF287)
+#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE                             (0XF288)
+#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE                             (0XF289)
+#define PROC_MEM_NB_PH_MNPH_FILECODE                                 (0XF28A)
+#define PROC_MEM_NB_PH_MNS3PH_FILECODE                               (0XF28B)
+#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE                         (0XF28C)
+#define PROC_MEM_NB_PH_MNMCTPH_FILECODE                              (0XF28D)
+#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE                             (0XF290)
+#define PROC_MEM_NB_OR_MNOR_FILECODE                                 (0XF291)
+#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE                         (0XF292)
+#define PROC_MEM_NB_OR_MNMCTOR_FILECODE                              (0XF293)
+#define PROC_MEM_NB_OR_MNDCTOR_FILECODE                              (0XF294)
+#define PROC_MEM_NB_OR_MNOTOR_FILECODE                               (0XF295)
+#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE                         (0XF296)
+#define PROC_MEM_NB_OR_MNPHYOR_FILECODE                              (0XF297)
+#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE                            (0XF298)
+#define PROC_MEM_NB_OR_MNS3OR_FILECODE                               (0XF299)
+#define PROC_MEM_NB_OR_MNREGOR_FILECODE                              (0XF29A)
+#define PROC_MEM_NB_TN_MNREGTN_FILECODE                              (0XF29B)
+#define PROC_MEM_NB_TN_MNTN_FILECODE                                 (0XF29C)
+#define PROC_MEM_NB_TN_MNMCTTN_FILECODE                              (0XF29D)
+#define PROC_MEM_NB_TN_MNOTTN_FILECODE                               (0XF29E)
+#define PROC_MEM_NB_TN_MNDCTTN_FILECODE                              (0XF29F)
+#define PROC_MEM_NB_TN_MNPHYTN_FILECODE                              (0XF2A0)
+#define PROC_MEM_NB_TN_MNS3TN_FILECODE                               (0XF2A1)
+#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE                         (0XF2A2)
+#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE                             (0XF2A3)
+#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE                            (0XF2A4)
+#define PROC_MEM_NB_KR_MNREGKR_FILECODE                              (0xF2A5)
+#define PROC_MEM_NB_KR_MNDCTKR_FILECODE                              (0xF2A6)
+#define PROC_MEM_NB_KR_MNIDENDIMMKR_FILECODE                         (0xF2A7)
+#define PROC_MEM_NB_KR_MNMCTKR_FILECODE                              (0xF2A8)
+#define PROC_MEM_NB_KR_MNOTKR_FILECODE                               (0xF2A9)
+#define PROC_MEM_NB_KR_MNPHYKR_FILECODE                              (0xF2AA)
+#define PROC_MEM_NB_KR_MNS3KR_FILECODE                               (0xF2AB)
+#define PROC_MEM_NB_KR_MNFLOWKR_FILECODE                             (0xF2AC)
+#define PROC_MEM_NB_KR_MNPROTOKR_FILECODE                            (0xF2AD)
+#define PROC_MEM_NB_KR_MNKR_FILECODE                                 (0xF2AE)
+#define PROC_MEM_NB_KM_MNREGKM_FILECODE                              (0XF2AF)
+#define PROC_MEM_NB_KM_MNKM_FILECODE                                 (0XF2B0)
+#define PROC_MEM_NB_KM_MNMCTKM_FILECODE                              (0XF2B1)
+#define PROC_MEM_NB_KM_MNOTKM_FILECODE                               (0XF2B2)
+#define PROC_MEM_NB_KM_MNDCTKM_FILECODE                              (0XF2B3)
+#define PROC_MEM_NB_KM_MNPHYKM_FILECODE                              (0XF2B4)
+#define PROC_MEM_NB_KM_MNS3KM_FILECODE                               (0XF2B5)
+#define PROC_MEM_NB_KM_MNIDENDIMMKM_FILECODE                         (0XF2B6)
+#define PROC_MEM_NB_KM_MNFLOWKM_FILECODE                             (0XF2B7)
+#define PROC_MEM_NB_KM_MNPROTOKM_FILECODE                            (0XF2B8)
+
+
+#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
+#define PROC_MEM_PS_DR_MPRDR3_FILECODE                               (0XF402)
+#define PROC_MEM_PS_HY_MPRHY3_FILECODE                               (0XF403)
+#define PROC_MEM_PS_LN_MPRLN3_FILECODE                               (0XF404)
+#define PROC_MEM_PS_DR_MPSDR3_FILECODE                               (0XF405)
+#define PROC_MEM_PS_HY_MPSHY3_FILECODE                               (0XF406)
+#define PROC_MEM_PS_LN_MPSLN3_FILECODE                               (0XF407)
+#define PROC_MEM_PS_DR_MPUDR3_FILECODE                               (0XF408)
+#define PROC_MEM_PS_HY_MPUHY3_FILECODE                               (0XF409)
+#define PROC_MEM_PS_LN_MPULN3_FILECODE                               (0XF40A)
+#define PROC_MEM_PS_DA_MPUDA3_FILECODE                               (0XF40B)
+#define PROC_MEM_PS_DA_MPSDA2_FILECODE                               (0XF40C)
+#define PROC_MEM_PS_DA_MPSDA3_FILECODE                               (0XF40D)
+#define PROC_MEM_PS_DR_MPRDR2_FILECODE                               (0XF40E)
+#define PROC_MEM_PS_DR_MPUDR2_FILECODE                               (0XF40F)
+#define PROC_MEM_PS_C32_MPRC32_3_FILECODE                            (0XF410)
+#define PROC_MEM_PS_C32_MPUC32_3_FILECODE                            (0XF411)
+#define PROC_MEM_PS_NI_MPSNI3_FILECODE                               (0XF412)
+#define PROC_MEM_PS_NI_MPUNI3_FILECODE                               (0XF413)
+#define PROC_MEM_PS_ON_MPSON3_FILECODE                               (0XF414)
+#define PROC_MEM_PS_ON_MPUON3_FILECODE                               (0XF415)
+#define PROC_MEM_PS_PH_MPSPH3_FILECODE                               (0XF416)
+#define PROC_MEM_PS_PH_MPUPH3_FILECODE                               (0XF417)
+#define PROC_MEM_PS_RB_MPSRB3_FILECODE                               (0XF418)
+#define PROC_MEM_PS_RB_MPURB3_FILECODE                               (0XF419)
+#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE                          (0XF41A)
+#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE                          (0XF41B)
+#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE                          (0XF41C)
+#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE                          (0XF41D)
+#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE                          (0XF41E)
+#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE                          (0XF41F)
+#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE                          (0XF420)
+#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE                          (0XF421)
+#define PROC_MEM_PS_MPRTT_FILECODE                                   (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE                               (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE                                (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE                                   (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE                                   (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE                                (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE                             (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE                                 (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE                                 (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE                                 (0XF42B)
+#define PROC_MEM_PS_OR_MPOR3_FILECODE                                (0XF42C)
+#define PROC_MEM_PS_TN_MPSTN3_FILECODE                               (0XF42D)
+#define PROC_MEM_PS_TN_MPTN3_FILECODE                                (0XF42E)
+#define PROC_MEM_PS_TN_MPUTN3_FILECODE                               (0XF42F)
+#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE                         (0XF430)
+#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE                         (0XF431)
+#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE                         (0XF432)
+#define PROC_MEM_PS_KR_MPKR3_FILECODE                                (0XF433)
+#define PROC_MEM_PS_KR_MPUKR3_FILECODE                               (0XF434)
+#define PROC_MEM_PS_KR_MPSKR3_FILECODE                               (0XF435)
+#define PROC_MEM_PS_MPS___FILECODE                                   (0XF436)
+#define PROC_MEM_PS_KM_FM2_MPUKMFM2_FILECODE                         (0XF437)
+#define PROC_MEM_PS_KM_FM2_MPSKMFM2_FILECODE                         (0XF438)
+#define PROC_MEM_PS_KM_C2012_MPRKMC3_FILECODE                        (0XF439)
+#define PROC_MEM_PS_KM_C2012_MPUKMC3_FILECODE                        (0XF43A)
+#define PROC_MEM_PS_KM_C2012_MPLKMC3_FILECODE                        (0XF43B)
+#define PROC_MEM_PS_KM_G2012_MPRKMG3_FILECODE                        (0XF43C)
+#define PROC_MEM_PS_KM_G2012_MPUKMG3_FILECODE                        (0XF43D)
+#define PROC_MEM_PS_KM_G2012_MPLKMG3_FILECODE                        (0XF43E)
+#define PROC_MEM_PS_KM_MPKM3_FILECODE                                (0XF43F)
+#define PROC_MEM_PS_MPSEEDS_FILECODE                                 (0XF440)
+
+#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
+#define PROC_MEM_TECH_DDR2_MT2_FILECODE                              (0XF541)
+#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE                            (0XF543)
+#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE                           (0XF544)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE                        (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE                       (0XF58A)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE                             (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE                            (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE                               (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE                              (0XF804)
+#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE                       (0XF812)
+#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE                    (0XF813)
+#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE                    (0XF821)
+#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE                       (0XF822)
+#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE                    (0XF823)
+#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE                  (0XF825)
+#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE                    (0XF831)
+#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE                    (0XF832)
+#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE                       (0XF833)
+#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE                       (0XF842)
+#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE                    (0XF843)
+#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE                       (0XF845)
+#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE                     (0XF851)
+#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE                  (0XF852)
+#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE                (0XF853)
+#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE                    (0xF861)
+#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE                    (0xF862)
+#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE                       (0xF863)
+#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE                       (0xF871)
+#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE                       (0xF881)
+#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE                    (0xF891)
+#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE                    (0xF892)
+#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE                       (0xF893)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE                      (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE                      (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE                    (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE                 (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE                 (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE                 (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE                 (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE                            (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE                         (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE                         (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE                      (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE                      (0XF8CC)
+#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE                    (0XF8CD)
+#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE                       (0XF8CE)
+#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE                    (0XF8CF)
+#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE                  (0XF8D0)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE                            (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE                         (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE                      (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE                         (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE                         (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE                      (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE                   (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE                       (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE                       (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE                       (0XF8E9)
+#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE                    (0XF8F3)
+#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE                       (0XF8F4)
+#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE                    (0XF8F5)
+#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE                  (0XF8F6)
+#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE                     (0XF8F7)
+#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE                      (0XF8F8)
+#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE                     (0XF8F9)
+#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE                    (0XF8FA)
+#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE                       (0XF8FB)
+#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE                    (0XF8FC)
+#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE                  (0XF8FD)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE             (0XF8FE)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
new file mode 100644
index 0000000..3b2bc80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
@@ -0,0 +1,202 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components.  Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
+  UINT32   EventInfo;        ///< Uniquely identifies the event.
+  UINT32   DataParam1;       ///< Event specific additional data
+  UINT32   DataParam2;       ///< Event specific additional data
+  UINT32   DataParam3;       ///< Event specific additional data
+  UINT32   DataParam4;       ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h
new file mode 100644
index 0000000..ca53656
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT  AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
new file mode 100644
index 0000000..e4f89d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
@@ -0,0 +1,301 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset Stub
+ *
+ *
+ *
+ * @param[in] StdHeader           Standard configuration header
+ * @retval    AGESA_SUCCESS       Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+* @retval     AGESA_SUCCESS       Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in,out] PostParamsPtr    Pointer to Post configuration params.
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr     Pointer to late configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AmdGnbRecovery
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_SUCCESS   Always succeeds
+ */
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr   Pointer to post configuration parameters
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Before CPU Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
new file mode 100644
index 0000000..2ccdfc5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
@@ -0,0 +1,1972 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for GNB Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/**
+ * @page gnbmain GNB Component Documentation
+ *
+ * Additional documentation for the GNB component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage F12PcieLaneDescription    "Family 0x12 PCIe/DDI Lane description table"
+ *   - @subpage F14ONPcieLaneDescription  "Family 0x14(ON) PCIe/DDI Lane description table"
+ *   - @subpage F12LaneConfigurations     "Family 0x12 PCIe port/DDI link configurations"
+ *   - @subpage F14ONLaneConfigurations   "Family 0x14(ON) PCIe port/DDI link configurations"
+ *   - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description"
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+
+/**
+ *  @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
+ *     <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 8 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 9 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][4]</TD></TR>
+ *     <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][5]</TD></TR>
+ *     <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][6]</TD></TR>
+ *     <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][7]</TD></TR>
+ *     <TR><TD class="indexvalue" > 16</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][8]</TD></TR>
+ *     <TR><TD class="indexvalue" > 17</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][9]</TD></TR>
+ *     <TR><TD class="indexvalue" > 18</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][10]</TD></TR>
+ *     <TR><TD class="indexvalue" > 19</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][11]</TD></TR>
+ *     <TR><TD class="indexvalue" > 20</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][12]</TD></TR>
+ *     <TR><TD class="indexvalue" > 21</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][13]</TD></TR>
+ *     <TR><TD class="indexvalue" > 22</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][14]</TD></TR>
+ *     <TR><TD class="indexvalue" > 23</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][15]</TD></TR>
+ *     <TR><TD class="indexvalue" > 24</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 25</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 26</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 27</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 28</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 29</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 30</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 31</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
+ *  </TABLE>
+ *
+ */
+
+
+/**
+ *  @page F14ONPcieLaneDescription Family 0x14(ON) PCIe/DDI Lanes
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
+ *     <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 8</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 9</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
+ *  </TABLE>
+ *
+ */
+
+
+/**
+ *  @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description
+ *  Examples of various Dual Link DVI descriptors.
+ *  @code
+ *  // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * @endcode
+ */
+
+/**
+ * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations
+ * <div class=WordSection1>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 8 through 23. </span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.25pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Configuration</p>
+ *   </td>
+ *   <td width=132 valign=top style='width:99.0pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=29 valign=top style='width:125.25pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Config A*</p>
+ *   </td>
+ *   <td width=132 rowspan=15 valign=top style='width:99.0pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>2</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>&nbsp;</p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(9)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>9(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>10(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(10)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(13)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>13(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>14(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(14)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(17)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>17(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>18(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(18)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(21)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>21(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>22(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(22)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=132 rowspan=14 valign=top style='width:99.0pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>3</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>&nbsp;</p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(9)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>9(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>10(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(10)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(13)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>13(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>14(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(14)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(17)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>17(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>18(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(18)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(21)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>21(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>22(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(22)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=641 colspan=4 valign=top style='width:480.75pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>* Lanes selection for port 2/3 should not overlap in port configuration</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 4 through 7.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(6)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6 or 7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link
+ * configurations for lanes 24 through 31.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:28.35pt'>
+ *   <td width=167 valign=top style='width:125.0pt;border-top:none;border-left:
+ *   solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>24(31)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>31(24)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>24</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>27</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>28</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>31</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link
+ * configurations for lanes 8 through 23.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:17.85pt'>
+ *   <td width=167 rowspan=2 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:16.5pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:16.5pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:93.0pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:18.3pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *  </div>
+ */
+
+/**
+ * @page F14ONLaneConfigurations Family 0x14(ON) PCIe port/DDI link configurations
+ * <div class=WordSection1>
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 4 through 7.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(6)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6 or 7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>CRT/DDI link
+ * configurations for lanes 8 through 19.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-I*</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-I*</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>CRT*</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:35.85pt'>
+ *   <td width=638 colspan=4 valign=top style='width:6.65in;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:35.85pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>* - Only one connector of this time can exist in configuration</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * <p class=MsoNormal>&nbsp;</p>
+ *
+ * </div>
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h
new file mode 100644
index 0000000..b8d5091
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Ids.h
@@ -0,0 +1,1178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 55079 $   @e \$Date: 2011-06-16 03:48:27 -0600 (Thu, 16 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+  /* Macros to aid debugging */
+  /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE  1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
+#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+  #define IDS_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ *  IDS Option Hook Points
+ *
+ *  These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum {                        //vv- for debug reference only
+  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+                                          ///<   IDS Object is initialized.
+                                          ///<   Override CPU Core Leveling Mode.
+                                          ///<   Set P-State in Post
+  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+                                          ///< It will be used to control the following tables.
+                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+                                          ///<   ACPI SRAT Table
+                                          ///<   ACPI SLIT Table
+                                          ///<   ACPI WHEA Table
+                                          ///<   DMI Table
+  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+                                          ///<   Control Interleaving and DRAM memory hole
+                                          ///<   Override the setting of ECC Control
+                                          ///<   Override the setting of Online Spare Rank
+  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
+  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
+  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
+  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
+  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
+  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
+  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
+  IDS_BEFORE_WARM_RESET ,             ///< 12 Override PCI or MSR Registers Before Warm Reset
+  IDS_BEFORE_PCI_INIT,                ///< 13 Override PCI or MSR Registers Before PCI Init
+  IDS_BEFORE_AP_EARLY_HALT,           ///< 14 Option Hook Point before AP early halt
+  IDS_BEFORE_S3_RESUME,               ///< 15 Option Hook Point before s3 resume
+  IDS_AFTER_S3_RESUME,                ///< 16 Option Hook Point after s3 resume
+  IDS_BEFORE_PM_INIT,                 ///< 17 Option Hook Point Before Pm Init
+
+  IDS_MT_BASE = 0x20,                 ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
+
+  // All the above timing point is used by BVM, their value should never be changed
+  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
+  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
+                                          ///< Dram Controller, Drive Strength and DQS Timing
+  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
+  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
+  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
+  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
+  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
+  IDS_ECC,                            ///< 48 override ECC parameter
+  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
+  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
+  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
+  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
+  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
+  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
+  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
+  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
+  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
+  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
+  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
+  IDS_PHY_DLL_STANDBY_CTRL,           ///< 54 Enable/Disable Phy DLL standby feature
+  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
+  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
+  IDS_MEM_IGNORE_ERROR,               ///< 57 Ignore error and do not do fatal exit in memory
+  IDS_GNB_SMU_SERVICE_CONFIG,         ///< 58 Config GNB SMU service
+  IDS_GNB_ORBDYNAMIC_WAKE,            ///< 59 config GNB dynamic wake
+  IDS_GNB_PLATFORMCFG_OVERRIDE,       ///< 5a override ids gnb platform config
+  IDS_GNB_LCLK_DPM_EN,                ///< 5b override GNB LCLK DPM configuration
+  IDS_GNB_LCLK_DEEP_SLEEP,            ///< 5c override GNB LCLK DPM deep sleep
+  IDS_GNB_CLOCK_GATING,               ///< 5d Override GNB Clock gating config
+  IDS_NB_PSTATE_DIDVID,               ///< 5e Override NB P-state settings
+  IDS_CPB_CTRL,                       ///< 5f Config the Core peformance boost feature
+  IDS_HTC_CTRL,                       ///< 60 Hook for Hardware Thermal Control
+  IDS_CC6_WORKAROUND,                 ///< 61 Hook for skip CC6 work around
+  IDS_MEM_MR0,                        ///< 62 Hook for override Memory Mr0 register
+  IDS_REG_TABLE,                      ///< 63 Hook for add IDS register table to the loop
+  IDS_NBBUFFERALLOCATIONATEARLY,      ///< 64 Hook for override North bridge bufer allocation
+  IDS_BEFORE_S3_SPECIAL,              ///< 65 Hook to bypass S3 special functions
+  IDS_SET_PCI_REGISTER_ENTRY,         ///< 66 Hook to SetRegisterForPciEntry
+  IDS_ERRATUM463_WORKAROUND,          ///< 67 Hook to Erratum 463 workaround
+  IDS_BEFORE_MEMCLR,                  ///< 68 Hook before set Memclr bit
+  IDS_OVERRIDE_IO_CSTATE,             ///< 69 Hook for override io C-state setting
+  IDS_NBPSDIS_OVERRIDE,               ///< 6a Hook for override NB pstate disable setting
+  IDS_NBPS_REG_OVERRIDE,              ///< 6b Hook for override Memory NBps reg
+  IDS_LOW_POWER_PSTATE,               ///< 6c Hook for disalbe Low power_Pstates feature
+  IDS_CST_CREATE,                     ///< 6d Hook for create _CST
+  IDS_CST_SIZE,                       ///< 6e Hook for get _CST size
+  IDS_ENFORCE_VDDIO,                  ///< 6f Hook to override VDDIO
+  IDS_STRETCH_FREQUENCY_LIMIT,        ///< 70 Hook for enforcing memory stretch frequency limit
+  IDS_INIT_MEM_REG_TABLE,             ///< 71 Hook for init memory register table
+  IDS_SKIP_FUSED_MAX_RATE,            ///< 72 Hook to skip fused max rate cap
+  IDS_FCH_INIT_AT_RESET,              ///< 73 Hook for FCH reset parameter
+  IDS_FCH_INIT_AT_ENV,                ///< 74 Hook for FCH ENV parameter
+  IDS_ENFORCE_PLAT_TABLES,            ///< 75 Hook to enforce platform specific tables
+  IDS_NBPS_MIN_FREQ,                  ///< 76 Hook for override MIN nb ps freq
+  IDS_GNB_FORCE_CABLESAFE,            ///< 77 Hook for override Force Cable Safe
+  IDS_SKIP_PM_TRANSITION_STEP,        ///< 78 Hook for provide IDS ability to skip this PM step
+  IDS_GNB_PROPERTY,                   ///< 79 Hook for GNB Property
+  IDS_GNB_PCIE_POWER_GATING,          ///< 7A Hook for GNB PCIe Power Gating
+  IDS_MEM_DYN_DRAM_TERM,              ///< 7B Hook for Override Dynamic Dram Term
+  IDS_MEM_DRAM_TERM,                  ///< 7C Hook for Override Dram Term
+  IDS_TRACE_MODE,                     ///< 7D Trace Mode
+  IDS_GNB_ALTVDDNB,                   ///< 7E Hook for Override AltVddNB
+  IDS_UCODE,                          ///< 7F Enable or Disable microcode patching
+  IDS_FAM_REG_GMMX,                   ///< 80 GMMX register access
+  IDS_MEMORY_POWER_POLICY,            ///< 81 Memory power policy
+  IDS_GET_STRETCH_FREQUENCY_LIMIT,    ///< 82 Hook for enforcing memory stretch frequency limit
+  IDS_CPU_FEAT,                       ///< 83 Hook for runtime force cpu feature disable
+  IDS_OPTION_END,                     ///< 84 End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+  #define IDSOPT_IDS_ENABLED        FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+  #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+  #define IDSOPT_TRACING_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+  #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+  #define IDSOPT_HEAP_CHECKING           FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+  #define IDSOPT_ASSERT_ENABLED         FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+  #define IDSOPT_DEBUG_CODE_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+  #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+  #define IDSOPT_C_OPTIMIZATION_DISABLED   FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef  IDSOPT_CONTROL_ENABLED
+  #undef  IDSOPT_TRACING_ENABLED
+  #undef  IDSOPT_PERF_ANALYSIS
+  #undef  IDSOPT_HEAP_CHECKING
+  #undef  IDSOPT_ASSERT_ENABLED
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #undef  IDSOPT_DEBUG_CODE_ENABLED
+  #undef  IDSOPT_TRACE_USER_OPTIONS
+
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+  #define IDSOPT_TRACING_ENABLED    FALSE
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+  #define IDSOPT_HEAP_CHECKING      FALSE
+  #define IDSOPT_ASSERT_ENABLED     FALSE
+  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+  #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+  #define IDSOPT_TRACE_USER_OPTIONS FALSE
+#endif
+
+/**
+ *  Make a Progress Report to the User.
+ *
+ *  This Macro is always enabled. The default action is to write the TestPoint value
+ *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ *  in OptionsIds.h in their build tip.
+ *
+ *  @param[in]      TestPoint       The value for display indicating progress
+ *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader)
+
+#ifndef IDS_DEBUG_PORT
+  #define IDS_DEBUG_PORT  0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ *  (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ *  Causes the program to halt and display the file number of the source of the
+ *  halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+  #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+  #define STOP_HERE  STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ *  Test an assertion that the given statement is True.
+ *
+ *  The statement is evaluated to a boolean value. If the statement is True,
+ *  then no action is taken (no error). If the statement is False, a error stop
+ *  is generated to halt the program. Used for testing for fatal errors that
+ *  must be resolved before production. This is used to do parameter checks,
+ *  bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+  #if IDSOPT_ASSERT_ENABLED == TRUE
+    #ifdef STOP_CODE
+      #undef STOP_CODE
+    #endif
+    #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+    #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+  #else
+    #define ASSERT(conditional)
+  #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#else
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+
+#ifndef DEBUG_CODE
+  #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+    #define  DEBUG_CODE(Code)
+  #else
+    #define  DEBUG_CODE(Code)
+  #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_ERROR_TRAP  IdsErrorStop (STOP_CODE)
+#else
+  #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+  #define IDS_INITIAL_F10_PM_STEP
+  #define IDS_INITIAL_F12_PM_STEP
+  #define IDS_INITIAL_F14_PM_STEP
+  #define IDS_INITIAL_F15_OR_PM_STEP
+  #define IDS_INITIAL_F15_TN_PM_STEP
+  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+  #define IDS_EXTENDED_HEAP_SIZE 0
+  #define IDS_EXT_INCLUDE_F10(file)
+  #define IDS_EXT_INCLUDE_F12(file)
+  #define IDS_EXT_INCLUDE_F14(file)
+  #define IDS_EXT_INCLUDE_F15(file)
+  #define IDS_EXT_INCLUDE(file)
+  #define IDS_PAD_4K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+  #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+    #undef IDS_AP_GET_NV_FROM_CMOS
+    #define IDS_AP_GET_NV_FROM_CMOS(x)
+    #ifdef IDS_OPT_CMOS_INDEX_PORT
+      #undef IDS_CMOS_INDEX_PORT
+      #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_DATA_PORT
+      #undef IDS_CMOS_DATA_PORT
+      #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_START
+      #undef IDS_CMOS_REGION_START
+      #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_END
+      #undef IDS_CMOS_REGION_END
+      #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+    #endif
+  #endif
+#else
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
+#endif
+
+/**
+ *  Macro to add a *skip* hook for IDS options
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, IDS dispatcher function will be called to perform
+ *  the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in]       IdsOption       IDS Option ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#else
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a heap manager routine
+ *
+ *  when memory is allocated the heap manager actually allocates two extra dwords of data,
+ *  one dword buffer before the actual memory, and one dword afterwards.
+ *  a complete heap walk and check to be performed at any time.
+ *  it would ASSERT if the heap is corrupt
+ *
+ * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548    // "Head"
+#define SENTINEL_AFTER_VALUE  0x6C696154    // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_HEAP_CHECKING == TRUE
+    #define SIZE_OF_SENTINEL  4
+    #define NUM_OF_SENTINEL   2             // Before ("Head") and After ("Tail")
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+    #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+    #define Heap_Check(stdheader)
+  #else
+    #define SIZE_OF_SENTINEL  0
+    #define NUM_OF_SENTINEL   0
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #endif
+#else
+  #define SIZE_OF_SENTINEL    0
+  #define NUM_OF_SENTINEL     0
+  #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+  #define SET_SENTINEL_AFTER(NodePtr)
+  #define Heap_Check(stdheader)
+#endif
+
+/**
+ *  Macro to add IDT for debugging exception.
+ *
+ *  A debug feature. Adding a 'jmp $' into every exception handler.
+ *  So debugger could use HDT to skip 'jmp $' and execute the iret,
+ *  then they could find which instruction cause the exception.
+ *
+ * @param[in]       FunctionId      IDS Function ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+  #else
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+  #endif
+#else
+  #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+
+
+/**
+ *  Macro to add HDT OUT
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, the debug information can be displayed in HDT or other
+ *  devices.
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_TRACING_ENABLED == TRUE
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+
+      #ifdef __GNUC__
+        #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
+		/* print all*/
+		//#define IDS_HDT_CONSOLE(f, s, args...) do {do_printk(BIOS_DEBUG, s, ##args);} while (0)
+		#define IDS_HDT_CONSOLE(f, s, args...) do {\
+			if (f == MAIN_FLOW) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == MEM_FLOW) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == CPU_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == HT_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == GNB_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == FCH_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			}\
+		} while(0)
+        #else
+        #define IDS_HDT_CONSOLE(s, args...) do {} while(0)
+        #endif
+        #else
+     #define IDS_HDT_CONSOLE(s, args...)
+    #endif
+
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR        NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    //#define CONSOLE(s, ...)
+  #else
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+    #define IDS_HDT_CONSOLE(f, s, ...)
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR                 NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    //#define CONSOLE(s, ...)        CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+  #endif
+#else
+  #define IDS_HDT_CONSOLE_INIT(x)
+  #define IDS_HDT_CONSOLE_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+  #define IDS_HDT_CONSOLE(f, s, ...)
+  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+  #define IDS_HDT_CONSOLE_ASSERT(x)
+  #define IDS_FUNCLIST_ADDR                   NULL
+  #define IDS_FUNCLIST_EXTERN()
+  #define IDS_TIMEOUT_CTL(t)
+  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+//  #define CONSOLE(s, ...)        CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG  IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#else
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL  0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY    TRUE
+#define IDS_ALL_CORES   FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT      0x01                             ///< The function data of IDS callout function of initialization.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+  UINT32  FuncAddr;       ///< Function address in ROM
+  CHAR8   FuncName[40];   ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ *  AGESA Test Points
+ *
+ *  These are the values displayed to the user to indicate progress through boot.
+ *  These can be used in a debug environment to stop the debugger at a specific
+ *  test point:
+ *  For SimNow!, this command
+ *      bi 81 w vb 49
+ *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
+
+  // Memory test points
+  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
+  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
+  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
+  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
+  TpProcMemSPDChecking,               ///< 05 ..
+  TpProcMemModeChecking,              ///< 06 ..
+  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
+  TpProcMemSpdTiming,                 ///< 08 ..
+  TpProcMemDramMapping,               ///< 09 ..
+  TpProcMemPlatformSpecificConfig,    ///< 0A ..
+  TPProcMemPhyCompensation,           ///< 0B ..
+  TpProcMemStartDcts,                 ///< 0C ..
+  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
+  TpProcMemPhyFenceTraining,          ///< 0E ..
+  TpProcMemSynchronizeDcts,           ///< 0F ..
+  TpProcMemSystemMemoryMapping,       ///< 10 ..
+  TpProcMemMtrrConfiguration,         ///< 11 ..
+  TpProcMemDramTraining,              ///< 12 ..
+  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
+  TpProcMemWriteLevelizationTraining, ///< 14 ..
+  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
+  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
+  TpProcMemWlTrainTargetDimm,         ///< 17 .. Target DIMM configured
+  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
+  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
+  TpProcMemReceiverEnableTraining,    ///< 1A ..
+  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
+  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
+  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
+  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
+  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
+  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
+  TpProcMemReceiveDqsTraining,        ///< 21 ..
+  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
+  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
+  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
+  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
+  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
+  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
+  TpProcMemRcvDqsResults,             ///< 28 .. Update results
+  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
+  TpProcMemTransmitDqsTraining,       ///< 2A ..
+  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
+  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
+  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
+  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
+  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
+  TpProcMemTxDqResults,               ///< 30 .. Update results
+  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
+  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
+  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
+  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
+  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
+  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
+  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
+  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
+  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
+  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
+  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
+  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
+  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
+  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
+  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
+  TpProcMemBeforeAgesaHookBeforeDramInit,    ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeDramInit,     ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeExitSelfRef,  ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
+  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
+  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
+  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
+  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
+  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
+  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
+  TpProcMemMemClr,                    ///< 4D .. Before MemClr
+  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
+  TpProcMemDmi,                       ///< 4F .. Before DMI
+  TpProcMemEnd,                       ///< 50 .. End of memory code
+
+  // CPU test points
+  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
+  TpProcCpuEntryPstate,               ///< 52 .. Entry point GenerateSsdt
+  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
+  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
+  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
+  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
+  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
+  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
+  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
+  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
+  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
+  TpProcCpuBeforePMFeatureInit,       ///< 5C .. BeforePM feature dispatch point
+  TpProcCpuPowerMgmtInit,             ///< 5D .. Power Management table processing
+  TpProcCpuEarlyFeatureInit,          ///< 5E .. Early feature dispatch point
+  TpProcCpuCoreLeveling,              ///< 5F .. Core Leveling
+  TpProcCpuApMtrrSync,                ///< 60 .. AP MTRR sync up
+  TpProcCpuPostFeatureInit,           ///< 61 .. POST feature dispatch point
+  TpProcCpuFeatureLeveling,           ///< 62 .. CPU Feature Leveling
+  TpProcCpuBeforeRelinquishAPsFeatureInit,   ///< 63 .. Before Relinquishing control of APs feature dispatch point
+  TpProcCpuBeforeAllocateWheaBuffer,  ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateWheaBuffer,   ///< 65 .. After the WHEA init code calls out to allocate a buffer
+  TpProcCpuBeforeAllocateSratBuffer,  ///< 66 .. Before the SRAT init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSratBuffer,   ///< 67 .. After the SRAT init code calls out to allocate a buffer
+  TpProcCpuBeforeLocateSsdtBuffer,    ///< 68 .. Before the P-state init code calls out to locate a buffer
+  TpProcCpuAfterLocateSsdtBuffer,     ///< 69 .. After the P-state init code calls out to locate a buffer
+  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 6A .. Before the P-state init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSsdtBuffer,   ///< 6B .. After the P-state init code calls out to allocate a buffer
+
+  // HT test points
+  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
+  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
+  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
+  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
+  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
+  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
+  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
+  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
+  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
+  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
+  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
+  TpProcHtDone,                       ///< 7C .. HT Init complete
+  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
+  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
+
+  // Extended memory test point
+  TpProcMemSendMRS2 = 0x80,           ///< 80 .. Sending MRS2
+  TpProcMemSendMRS3,                  ///< 81 .. Sedding MRS3
+  TpProcMemSendMRS1,                  ///< 82 .. Sending MRS1
+  TpProcMemSendMRS0,                  ///< 83 .. Sending MRS0
+  TpProcMemContinPatternGenRead,      ///< 84 .. Continuous Pattern Read
+  TpProcMemContinPatternGenWrite,     ///< 85 .. Continuous Pattern Write
+  TpProcMem__RdDqsTraining,           ///< 86 .. Mem: RdDqs Training begin
+  TpProcMemBefore__TrainExtVrefChange,///< 87 .. Mem: Before optional callout to platfrom BIOS to change External Vref during training
+  TpProcMemAfter__TrainExtVrefChange, ///< 88 .. Mem: After optional callout to platfrom BIOS to change External Vref during training
+
+  StartNbTestPoints = 0x90,           ///< 90 Entry used for range testing for @b NorthBridge related TPs
+  TpNbxxx,                            ///< 91 .
+  EndNbTestPoints,                    ///< 92 End of TP range for NB
+
+  StartFchTestPoints = 0xB0,          ///< B0 Entry used for range testing for @b FCH related TPs
+  TpFchInitResetDispatching,          ///< B1 .. FCH InitReset dispatch point
+  TpFchGppBeforePortTraining,         ///< B2 .. Before FCH GPP port training
+  TpFchGppGen1PortPolling,            ///< B3 .. FCH GPP port polling with GEN1 speed
+  TpFchGppGen2PortPolling,            ///< B4 .. FCH GPP port polling with GEN2 speed
+  TpFchGppAfterPortTraining,          ///< B5 .. After FCH GPP port training
+  TpFchInitEnvDispatching,            ///< B6 .. FCH InitEnv dispatch point
+  TpFchInitMidDispatching,            ///< B7 .. FCH InitMid dispatch point
+  TpFchInitLateDispatching,           ///< B8 .. FCH InitLate dispatch point
+  TpFchGppHotPlugging,                ///< B9 .. FCH GPP hot plug event
+  TpFchGppHotUnplugging,              ///< BA .. AFCH GPP hot unplug event
+  TpFchInitS3EarlyDispatching,        ///< BB .. FCH InitS3Early dispatch point
+  TpFchInitS3LateDispatching,         ///< BC .. FCH InitS3Late dispatch point
+  EndFchTestPoints,                   ///< BF End of TP range for FCH
+
+  // Interface test points
+  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
+  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
+  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
+  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
+  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
+  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
+  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
+  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
+  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
+  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
+  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
+  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
+  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
+  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
+  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
+  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
+  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
+  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
+  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
+  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
+  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
+  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
+  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
+  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
+  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
+  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
+  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
+  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
+  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
+  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
+  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
+  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
+  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
+  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
+  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
+  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
+  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
+  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
+  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
+  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
+  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
+  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
+  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
+  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
+  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
+  TpPerfUnit,                         ///< F8 .. The Unit of performance measure.
+  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
+  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
+  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
+  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
+  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
+  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
+  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
+  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
+  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
+  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
+  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
+  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
+  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
+  IDS_FEAT_GNB_PLATFORMCFG,         ///< Feat for override GNB platform config
+  IDS_FEAT_CPB_CTRL,                ///< Feat for Config the Core peformance boost feature
+  IDS_FEAT_HTC_CTRL,                ///< Feat for Hardware Thermal Control
+  IDS_FEAT_MEMORY_MAPPING,          ///< Feat for Memory Mapping
+  IDS_FEAT_POWER_POLICY,            ///< Feat for Power Policy
+  IDS_FEAT_NV_TO_CMOS,              ///< Feat for Save BSP Nv to CMOS
+  IDS_FEAT_COMMON,                  ///< Common Feat
+  IDS_FEAT_END = 0xFF               ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+  IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000,   ///< Function ID for saving IDTR for BSC
+  IDS_IDT_RESTORE_IDTR_FOR_BSC,            ///< Function ID for restoring IDTR for BSC
+  IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP,  ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef  struct _IDS_FAMILY_FEAT_STRUCT {
+  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
+  BOOLEAN IsBsp;          ///< swith for Bsp check
+  AGESA_IDS_OPTION IdsOption;   ///< IDS option
+  UINT64 CpuFamily;       ///<
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef  struct _IDS_OPTION_STRUCT {
+  AGESA_IDS_OPTION idsoption;       ///< IDS option
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+  UINT8 version;      ///<Version of IDS option table
+  UINT16 size;        ///<Size of IDS option table
+  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE   1
+#define IDS_NV_TO_CMOS_LEN_WORD   2
+#define IDS_NV_TO_CMOS_LEN_END   0xFF
+#define IDS_NV_TO_CMOS_ID_END   0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+  UINT8 Length;       ///< Length of NV
+  UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsOptionCallout (
+  IN       UINTN                CallOutId,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintS3Exit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintS3ApExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrint (
+  IN       UINT64 Flag,
+  IN       CHAR8 *Format,
+  IN       ...
+  );
+
+VOID
+AmdIdsDebugPrintHt (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintCpu (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintMem (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintGnb (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintFlush (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  );
+
+VOID
+IdsAgesaTestPoint (
+  IN      AGESA_TP TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval         TRUE     No error
+**/
+BOOLEAN
+IdsAssert (
+  IN      UINT32 FileCode
+  );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+  IN      UINT32 FileCode
+  );
+
+VOID
+IdsDelay (
+  IN	VOID
+);
+
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsExceptionTrap (
+  IN       IDS_IDT_FUNC_ID IdsIdtFuncId,
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef IEM_SKIP_CODE
+  #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+  #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+  #define IEM_INSERT_CODE(L,Fn,Parm)
+#endif
+
+//Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a)   ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG                                  DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG                                  DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW                                    DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS                                  DEBUG_PRINT_SHIFT (3)
+#define MEMORY_TRACE_RSV1                           DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2                           DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3                           DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4                           DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5                           DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6                           DEBUG_PRINT_SHIFT (9)
+
+
+
+//CPU Masks
+#define CPU_TRACE                                   DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1                              DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2                              DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3                              DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4                              DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5                              DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6                              DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7                              DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8                              DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9                              DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE                                   DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC                                   DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE                          DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE                          DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2                              DEBUG_PRINT_SHIFT (24)
+#define NB_MISC                                     DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3                              DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC                                    DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE                             DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1                              DEBUG_PRINT_SHIFT (29)
+
+//HT Masks
+#define HT_TRACE                                    DEBUG_PRINT_SHIFT (30)
+#define HT_TRACE_RSV1                               DEBUG_PRINT_SHIFT (31)
+#define HT_TRACE_RSV2                               DEBUG_PRINT_SHIFT (32)
+#define HT_TRACE_RSV3                               DEBUG_PRINT_SHIFT (33)
+#define HT_TRACE_RSV4                               DEBUG_PRINT_SHIFT (34)
+#define HT_TRACE_RSV5                               DEBUG_PRINT_SHIFT (35)
+#define HT_TRACE_RSV6                               DEBUG_PRINT_SHIFT (36)
+#define HT_TRACE_RSV7                               DEBUG_PRINT_SHIFT (37)
+#define HT_TRACE_RSV8                               DEBUG_PRINT_SHIFT (38)
+#define HT_TRACE_RSV9                               DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE                                    DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1                               DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2                               DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3                               DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4                               DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5                               DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6                               DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7                               DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8                               DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9                               DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW                                    DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG                                    DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE                          DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE                                    DEBUG_PRINT_SHIFT (53)
+#define IDS_REG                                      DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2                               DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3                               DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE                                     DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD                                   DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR                                   DEBUG_PRINT_SHIFT (59)
+
+//Reserved
+#define TRACE_RSV3                                   DEBUG_PRINT_SHIFT (60)
+#define TRACE_RSV4                                   DEBUG_PRINT_SHIFT (61)
+#define TRACE_RSV5                                   DEBUG_PRINT_SHIFT (62)
+#define TRACE_RSV6                                   DEBUG_PRINT_SHIFT (63)
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/IdsHt.h b/src/vendorcode/amd/agesa/f15/Include/IdsHt.h
new file mode 100644
index 0000000..bdda364
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/IdsHt.h
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M            0
+#define HT_FREQUENCY_400M            2
+#define HT_FREQUENCY_600M            4
+#define HT_FREQUENCY_800M            5
+#define HT_FREQUENCY_1000M           6
+#define HT_FREQUENCY_1200M           7
+#define HT_FREQUENCY_1400M           8
+#define HT_FREQUENCY_1600M           9
+#define HT_FREQUENCY_1800M           10
+#define HT_FREQUENCY_2000M           11
+#define HT_FREQUENCY_2200M           12
+#define HT_FREQUENCY_2400M           13
+#define HT_FREQUENCY_2600M           14
+#define HT_FREQUENCY_2800M           17
+#define HT_FREQUENCY_3000M           18
+#define HT_FREQUENCY_3200M           19
+#define HT_FREQUENCY_3600M           20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings.  No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ *   - HT_LIST_MATCH_ANY == Match Any Socket
+ *   - 0 .. 7 == The matching socket
+ * - Link
+ *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+  // Match Fields
+  UINT8       Socket;      ///< The Socket which this port is on.
+  UINT8       Link;        ///< The port for this package link on that socket.
+  // Override fields
+  UINT8       Frequency;   ///< Absolutely override the port's frequency.
+  UINT8       WidthIn;     ///< Absolutely override the port's width.
+  UINT8       WidthOut;    ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
new file mode 100644
index 0000000..a1dd4fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 59375 $   @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                    // This is the delivery package title, "MarG34PI"
+                    // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+                    // This is the release version number of the AGESA component
+                    // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+
+
+// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
+#define INSTALL_G34_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_10_SUPPORT            TRUE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_10_SUPPORT
+    #define INSTALL_FAMILY_10_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+    #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
new file mode 100644
index 0000000..4b3b9a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Application Power Management (APM).
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 54493 $   @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_APM_INSTALL_H_
+#define _OPTION_APM_INSTALL_H_
+
+#include "cpuApm.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_APM_FEAT
+#define F15_APM_SUPPORT
+
+#if OPTION_CPU_APM == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
+          #undef OPTION_CPU_APM_FEAT
+          #define OPTION_CPU_APM_FEAT &CpuFeatureApm,
+          extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport;
+          #undef F15_APM_SUPPORT
+          #define F15_APM_SUPPORT {AMD_FAMILY_15_OR | AMD_FAMILY_15_KM, &F15ApmSupport},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
+{
+  F15_APM_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
+{
+  (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &ApmFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_APM_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
new file mode 100644
index 0000000..2e944bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_C6_STATE_INSTALL_H_
+#define _OPTION_C6_STATE_INSTALL_H_
+
+#include "cpuC6State.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_C6_STATE_FEAT
+#define F12_C6_STATE_SUPPORT
+#define F14_ON_C6_STATE_SUPPORT
+#define F15_OR_C6_STATE_SUPPORT
+
+#if OPTION_C6_STATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
+          #undef F12_C6_STATE_SUPPORT
+          #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
+
+          #if OPTION_EARLY_SAMPLES == TRUE
+            extern F_F12_ES_C6_INIT F12C6A0Workaround;
+
+            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+            {
+              F12C6A0Workaround
+            };
+          #else
+            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+            {
+              (PF_F12_ES_C6_INIT) CommonVoid
+            };
+          #endif
+
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if (OPTION_FAMILY14H_ON == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
+          #undef F14_ON_C6_STATE_SUPPORT
+          #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
+
+          #if (OPTION_EARLY_SAMPLES == TRUE)
+            extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
+            extern F_F14_ON_ES_C6_INIT F14C6A0Workaround;
+
+            CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
+            {
+              F14IsC6DisabledEarlySample,
+              F14C6A0Workaround
+            };
+          #else
+            CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
+            {
+              (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
+              (PF_F14_ON_ES_C6_INIT) CommonVoid
+            };
+          #endif
+        #endif
+
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
+          #undef F15_OR_C6_STATE_SUPPORT
+          #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
+
+          #if (OPTION_EARLY_SAMPLES == TRUE)
+            extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample;
+
+            CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
+            {
+              F15OrIsC6DisabledEarlySample
+            };
+          #else
+            CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
+            {
+              (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
+            };
+          #endif
+        #endif
+
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
+{
+  F12_C6_STATE_SUPPORT
+  F14_ON_C6_STATE_SUPPORT
+  F15_OR_C6_STATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
+{
+  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &C6FamilyServiceArray[0]
+};
+
+#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
new file mode 100644
index 0000000..d47619b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
@@ -0,0 +1,170 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Core Performance Boost
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 46389 $   @e \$Date: 2011-01-31 20:22:49 -0700 (Mon, 31 Jan 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPB_INSTALL_H_
+#define _OPTION_CPB_INSTALL_H_
+
+#include "cpuCpb.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPB_FEAT
+#define F10_CPB_SUPPORT
+#define F12_CPB_SUPPORT
+#define F14_ON_CPB_SUPPORT
+#define F15_OR_CPB_SUPPORT
+
+#if OPTION_CPB == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    // Family 10h
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_PH == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
+          #undef F10_CPB_SUPPORT
+          #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 12h
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
+          #undef F12_CPB_SUPPORT
+          #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
+          #if OPTION_EARLY_SAMPLES == TRUE
+            #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+              extern F_F12_ES_CPB_INIT F12LnA1CpbHook;
+
+              CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+              {
+                F12LnA1CpbHook
+              };
+            #else
+              CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+              {
+                (PF_F12_ES_CPB_INIT) CommonVoid
+              };
+            #endif
+          #else
+            CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+            {
+              (PF_F12_ES_CPB_INIT) CommonVoid
+            };
+          #endif
+        #endif
+      #endif
+    #endif
+
+    // Family 14h
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if OPTION_FAMILY14H_ON == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
+          #undef F14_ON_CPB_SUPPORT
+          #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
+          #undef F15_OR_CPB_SUPPORT
+          #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
+
+          #if OPTION_EARLY_SAMPLES == TRUE
+            extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample;
+
+            CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
+            {
+              F15OrIsCpbDisabledEarlySample
+            };
+          #else
+            CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
+            {
+              (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
+            };
+          #endif
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
+{
+  F10_CPB_SUPPORT
+  F12_CPB_SUPPORT
+  F14_ON_CPB_SUPPORT
+  F15_OR_CPB_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
+{
+  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpbFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100644
index 0000000..35362ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F10_BL_CPU_CFOH_SUPPORT
+#define F10_DA_CPU_CFOH_SUPPORT
+#define F10_CPU_CFOH_SUPPORT
+#define F15_OR_CPU_CFOH_SUPPORT
+#define F15_TN_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY10H_BL == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
+          #undef F10_BL_CPU_CFOH_SUPPORT
+          #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY10H_DA == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
+          #undef F10_DA_CPU_CFOH_SUPPORT
+          #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
+        #endif
+
+        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
+          #undef F10_CPU_CFOH_SUPPORT
+          #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
+          #undef F15_OR_CPU_CFOH_SUPPORT
+          #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
+          #undef F15_TN_CPU_CFOH_SUPPORT
+          #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+  F10_BL_CPU_CFOH_SUPPORT
+  F10_DA_CPU_CFOH_SUPPORT
+  F10_CPU_CFOH_SUPPORT
+  F15_OR_CPU_CFOH_SUPPORT
+  F15_TN_CPU_CFOH_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
new file mode 100644
index 0000000..d0743ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Core Leveling
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
+#define _OPTION_CPU_CORELEVELING_INSTALL_H_
+
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CORE_LEVELING_FEAT
+#define F10_REVE_CPU_CORELEVELING_SUPPORT
+#define F10_REVD_CPU_CORELEVELING_SUPPORT
+#define F10_REVC_CPU_CORELEVELING_SUPPORT
+#define F15_OR_CPU_CORELEVELING_SUPPORT
+#define F15_TN_CPU_CORELEVELING_SUPPORT
+
+#if OPTION_CPU_CORELEVLING == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+
+    // Family 10h
+    #if OPTION_FAMILY10H == TRUE
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+      #if OPTION_FAMILY10H_HY == TRUE
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
+        #undef F10_REVD_CPU_CORELEVELING_SUPPORT
+        #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
+      #endif
+
+      #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
+        #undef F10_REVC_CPU_CORELEVELING_SUPPORT
+        #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
+      #endif
+
+      #if (OPTION_FAMILY10H_PH == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
+        #undef F10_REVE_CPU_CORELEVELING_SUPPORT
+        #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
+      #endif
+    #endif
+    // Family 15h
+    #if OPTION_FAMILY15H == TRUE
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+      #if (OPTION_FAMILY15H_OR == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
+        #undef F15_OR_CPU_CORELEVELING_SUPPORT
+        #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
+      #endif
+      #if (OPTION_FAMILY15H_TN == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
+        #undef F15_TN_CPU_CORELEVELING_SUPPORT
+        #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
+{
+  F15_TN_CPU_CORELEVELING_SUPPORT
+  F15_OR_CPU_CORELEVELING_SUPPORT
+  F10_REVE_CPU_CORELEVELING_SUPPORT
+  F10_REVD_CPU_CORELEVELING_SUPPORT
+  F10_REVC_CPU_CORELEVELING_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
+{
+  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CoreLevelingFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
new file mode 100644
index 0000000..5cc4819
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
@@ -0,0 +1,407 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of all appropriate CPU family specific support.
+ *
+ * This file generates the defaults tables for all family specific
+ * combinations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 50628 $   @e \$Date: 2011-04-12 15:18:38 -0600 (Tue, 12 Apr 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*  Default all CPU Specific Service members to off.  They
+    will be enabled as needed by cross referencing families
+    with entry points in the family / model install files.  */
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define GET_NB_IDD_MAX              FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define BASE_FAMILY_WORKAROUNDS     FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_CFOH_REG                FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+
+/*
+ * Pull in family specific services based on entry point
+ */
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef DISABLE_PSTATE
+  #define DISABLE_PSTATE              TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef GET_NB_IDD_MAX
+  #define GET_NB_IDD_MAX              TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef BASE_FAMILY_WORKAROUNDS
+  #define BASE_FAMILY_WORKAROUNDS     TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef GET_CFOH_REG
+  #define GET_CFOH_REG                TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RESUME == TRUE
+  #undef GET_CFOH_REG
+  #define GET_CFOH_REG                TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+/*
+ * Initialize PCI MMIO mask to 0
+ */
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+
+/*
+ * Initialize all families to disabled
+ */
+#define OPT_F10_TABLE
+#define OPT_F12_TABLE
+#define OPT_F14_TABLE
+#define OPT_F15_TABLE
+
+#define OPT_F10_ID_TABLE
+#define OPT_F12_ID_TABLE
+#define OPT_F14_ID_TABLE
+#define OPT_F15_ID_TABLE
+
+
+/*
+ * Install family specific support
+ */
+#if (OPTION_FAMILY10H == TRUE)
+  #include  "OptionFamily10hInstall.h"
+#endif
+
+#if (OPTION_FAMILY12H == TRUE)
+  #include  "OptionFamily12hInstall.h"
+#endif
+
+#if (OPTION_FAMILY14H == TRUE)
+  #include  "OptionFamily14hInstall.h"
+#endif
+
+#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
+  #include  "OptionFamily15hInstall.h"
+#endif
+
+
+/*
+ * Process PCI MMIO mask
+ */
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+/*
+ * Process sockets / modules
+ */
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+/*
+ * Instantiate global data needed for processor identification
+ */
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
+{
+  OPT_F10_TABLE
+  OPT_F12_TABLE
+  OPT_F14_TABLE
+  OPT_F15_TABLE
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
+{
+  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpuSupportedFamiliesArray[0]
+};
+
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+  OPT_F12_ID_TABLE
+  OPT_F14_ID_TABLE
+  OPT_F15_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
new file mode 100644
index 0000000..44df5ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
@@ -0,0 +1,80 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of multiple CPU features.
+ *
+ * Aggregates enabled CPU features into a list for the dispatcher to process.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 54493 $   @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
+#define _OPTION_CPU_FEATURES_INSTALL_H_
+
+#include "OptionHwC1eInstall.h"
+#include "OptionMsgBasedC1eInstall.h"
+#include "OptionSwC1eInstall.h"
+#include "OptionL3FeaturesInstall.h"
+#include "OptionCpuCoreLevelingInstall.h"
+#include "OptionIoCstateInstall.h"
+#include "OptionC6Install.h"
+#include "OptionCpbInstall.h"
+#include "OptionCpuCacheFlushOnHaltInstall.h"
+#include "OptionPstateHpcModeInstall.h"
+#include "OptionLowPwrPstateInstall.h"
+#include "OptionApmInstall.h"
+#include "OptionPreserveMailboxInstall.h"
+
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+{
+  OPTION_HW_C1E_FEAT
+  OPTION_MSG_BASED_C1E_FEAT
+  OPTION_SW_C1E_FEAT
+  OPTION_L3_FEAT
+  OPTION_CPU_CORE_LEVELING_FEAT
+  OPTION_IO_CSTATE_FEAT
+  OPTION_C6_STATE_FEAT
+  OPTION_CPB_FEAT
+  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+  OPTION_CPU_PSTATE_HPC_MODE_FEAT             // this function should be run before low power pstate for prochot
+  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
+  OPTION_CPU_APM_FEAT
+  OPTION_PRESERVE_MAILBOX_FEAT
+  NULL
+};
+
+
+#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h
new file mode 100644
index 0000000..83fb7e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI option API.
+ *
+ * Contains structures and values used to control the DMI option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_DMI_H_
+#define _OPTION_DMI_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_DMI_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiPtr
+  );
+
+typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define DMI_STRUCT_VERSION  0x01
+
+/// DMI option configuration. Determine the item of structure when compiling.
+typedef struct  {
+  UINT16              OptDmiVersion;      ///< Dmi version.
+  OPTION_DMI_FEATURE  *DmiFeature;        ///< Feature main routine, otherwise dummy.
+  OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
+  UINT16              NumEntries;         ///< Number of entry.
+  VOID                *((*FamilyList)[]); ///< Family service.
+} OPTION_DMI_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
new file mode 100644
index 0000000..a6d48b3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
@@ -0,0 +1,215 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: DMI
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DMI_INSTALL_H_
+#define _OPTION_DMI_INSTALL_H_
+
+#include "cpuLateInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_DMI
+    #error  BLDOPT: Option not defined: "OPTION_DMI"
+  #endif
+  #if OPTION_DMI == TRUE
+    OPTION_DMI_FEATURE          GetDmiInfoMain;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
+    #define USER_DMI_OPTION     &GetDmiInfoMain
+    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
+
+    // This additional check keeps AP launch routines from being unnecessarily included
+    // in single socket systems.
+    #if OPTION_MULTISOCKET == TRUE
+      #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+      #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
+    #else
+      #define CPU_DMI_AP_GET_TYPE4_TYPE7
+    #endif
+
+    // Family 10
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
+        #define FAM10_DMI_SUPPORT FAM10_ENABLED,
+        #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
+      #else
+        #define FAM10_DMI_SUPPORT
+        #define FAM10_DMI_TABLE
+      #endif
+    #else
+      #define FAM10_DMI_SUPPORT
+      #define FAM10_DMI_TABLE
+    #endif
+
+    // Family 12
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
+        #define FAM12_DMI_SUPPORT FAM12_ENABLED,
+        #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
+      #else
+        #define FAM12_DMI_SUPPORT
+        #define FAM12_DMI_TABLE
+      #endif
+    #else
+      #define FAM12_DMI_SUPPORT
+      #define FAM12_DMI_TABLE
+    #endif
+
+    // Family 14
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
+        #define FAM14_DMI_SUPPORT FAM14_ENABLED,
+        #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
+      #else
+        #define FAM14_DMI_SUPPORT
+        #define FAM14_DMI_TABLE
+      #endif
+    #else
+      #define FAM14_DMI_SUPPORT
+      #define FAM14_DMI_TABLE
+    #endif
+
+    // Family 15
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
+          #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
+          #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
+        #else
+          #define FAM15_OR_DMI_SUPPORT
+          #define FAM15_OR_DMI_TABLE
+        #endif
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
+          #define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED,
+          #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
+        #else
+          #define FAM15_TN_DMI_SUPPORT
+          #define FAM15_TN_DMI_TABLE
+        #endif
+      #else
+        #define FAM15_OR_DMI_SUPPORT
+        #define FAM15_OR_DMI_TABLE
+        #define FAM15_TN_DMI_SUPPORT
+        #define FAM15_TN_DMI_TABLE
+      #endif
+    #else
+      #define FAM15_OR_DMI_SUPPORT
+      #define FAM15_OR_DMI_TABLE
+      #define FAM15_TN_DMI_SUPPORT
+      #define FAM15_TN_DMI_TABLE
+    #endif
+
+  #else
+    OPTION_DMI_FEATURE          GetDmiInfoStub;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+    #define USER_DMI_OPTION     GetDmiInfoStub
+    #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+    #define FAM10_DMI_SUPPORT
+    #define FAM10_DMI_TABLE
+    #define FAM12_DMI_SUPPORT
+    #define FAM12_DMI_TABLE
+    #define FAM14_DMI_SUPPORT
+    #define FAM14_DMI_TABLE
+    #define FAM15_OR_DMI_SUPPORT
+    #define FAM15_OR_DMI_TABLE
+    #define FAM15_TN_DMI_SUPPORT
+    #define FAM15_TN_DMI_TABLE
+    #define CPU_DMI_AP_GET_TYPE4_TYPE7
+  #endif
+#else
+  OPTION_DMI_FEATURE          GetDmiInfoStub;
+  OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+  #define USER_DMI_OPTION     GetDmiInfoStub
+  #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+  #define FAM10_DMI_SUPPORT
+  #define FAM10_DMI_TABLE
+  #define FAM12_DMI_SUPPORT
+  #define FAM12_DMI_TABLE
+  #define FAM14_DMI_SUPPORT
+  #define FAM14_DMI_TABLE
+  #define FAM15_OR_DMI_SUPPORT
+  #define FAM15_OR_DMI_TABLE
+  #define FAM15_TN_DMI_SUPPORT
+  #define FAM15_TN_DMI_TABLE
+  #define CPU_DMI_AP_GET_TYPE4_TYPE7
+#endif
+
+/// DMI supported families enum
+typedef enum {
+  FAM10_DMI_SUPPORT                   ///< Conditionally define F10 support
+  FAM12_DMI_SUPPORT                   ///< Conditionally define F12 support
+  FAM14_DMI_SUPPORT                   ///< Conditionally define F14 support
+  FAM15_OR_DMI_SUPPORT                ///< Conditionally define F15 OR support
+  FAM15_TN_DMI_SUPPORT                ///< Conditionally define F15 TN support
+  NUM_DMI_FAMILIES                    ///< Number of installed families
+} AGESA_DMI_SUPPORTED_FAM;
+
+/*  Declare the Family List. An array of pointers to tables that each describe a family  */
+CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
+  FAM10_DMI_TABLE
+  FAM12_DMI_TABLE
+  FAM14_DMI_TABLE
+  FAM15_OR_DMI_TABLE
+  FAM15_TN_DMI_TABLE
+  NULL
+};
+
+/*  Declare the instance of the DMI option configuration structure  */
+CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
+  DMI_STRUCT_VERSION,
+  USER_DMI_OPTION,
+  USER_DMI_RELEASE_BUFFER,
+  NUM_DMI_FAMILIES,
+  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
+};
+
+#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h
new file mode 100644
index 0000000..7eeea69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h
@@ -0,0 +1,2058 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 10h support
+ *
+ * This file generates the defaults tables for family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 60726 $   @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_10H_INSTALL_H_
+#define _OPTION_FAMILY_10H_INSTALL_H_
+
+/*
+ * Common Family 10h routines
+ */
+extern F_CPU_DISABLE_PSTATE F10DisablePstate;
+extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
+extern F_CPU_GET_TSC_RATE F10GetTscRate;
+extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
+extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
+extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
+extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
+extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
+extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
+extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
+extern F_CPU_SAVE_FEATURES F10SaveFeatures;
+extern F_CPU_WRITE_FEATURES F10WriteFeatures;
+extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
+extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
+extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
+extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
+extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
+extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
+extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
+extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
+extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
+
+
+/*
+ * Install family 10h model 5 support
+ */
+#ifdef OPTION_FAMILY10H_BL
+  #if OPTION_FAMILY10H_BL == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10BlPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10BlMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10BlHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10BlMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10BlMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10BlRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define BL_SOCKETS 1
+    #define BL_MODULES 1
+    #define BL_RECOVERY_SOCKETS 1
+    #define BL_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
+    #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES BL_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < BL_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES BL_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_BL_UCODE_C6
+      #define F10_BL_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+          #undef F10_BL_UCODE_C6
+          #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+        #endif
+        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_BL_UCODE_C8
+          #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+      {
+        F10_BL_UCODE_C6
+        F10_BL_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
+  #else
+    #define OPT_F10_BL_CPU
+    #define OPT_F10_BL_ID
+  #endif
+#else
+  #define OPT_F10_BL_CPU
+  #define OPT_F10_BL_ID
+#endif
+
+/*
+ * Install family 10h model 6 support
+ */
+#ifdef OPTION_FAMILY10H_DA
+  #if OPTION_FAMILY10H_DA == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10DaPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10DaMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10DaHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10DaMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10DaMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10DaRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define DA_SOCKETS 1
+    #define DA_MODULES 1
+    #define DA_RECOVERY_SOCKETS 1
+    #define DA_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
+    #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES DA_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < DA_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES DA_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_DA_UCODE_C7
+      #define F10_DA_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
+          #undef F10_DA_UCODE_C7
+          #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
+        #endif
+        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_DA_UCODE_C8
+          #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+      {
+        F10_DA_UCODE_C7
+        F10_DA_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
+  #else
+    #define OPT_F10_DA_CPU
+    #define OPT_F10_DA_ID
+  #endif
+#else
+  #define OPT_F10_DA_CPU
+  #define OPT_F10_DA_ID
+#endif
+
+/*
+ * Install family 10h models 8 & 9 support
+ */
+#ifdef OPTION_FAMILY10H_HY
+  #if OPTION_FAMILY10H_HY == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevDGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevDGetNumberOfPhysicalCores;
+    extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10MultiLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10HyPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10HyMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HyHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevDGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevDGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevDGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevDGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevDGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10HyMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10HyMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10HyRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+      #else
+        NULL,
+      #endif
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_C32_SOCKET_SUPPORT == TRUE
+          GetF10HyEarlyInitOnCoreTable
+        #else
+          GetF10EarlyInitOnCoreTable
+        #endif
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define HY_SOCKETS 8
+    #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
+      #define HY_MODULES 2
+    #else
+      #define HY_MODULES 1
+    #endif
+    #define HY_RECOVERY_SOCKETS 1
+    #define HY_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
+    #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES HY_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < HY_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES HY_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_HY_UCODE_D9
+      #define F10_HY_UCODE_C5
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_C32_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
+          #undef F10_HY_UCODE_C5
+          #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
+        #endif
+        #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9;
+          #undef F10_HY_UCODE_D9
+          #define F10_HY_UCODE_D9 &CpuF10MicrocodePatch010000d9,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
+      {
+        F10_HY_UCODE_D9
+        F10_HY_UCODE_C5
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
+  #else
+    #define OPT_F10_HY_CPU
+    #define OPT_F10_HY_ID
+  #endif
+#else
+  #define OPT_F10_HY_CPU
+  #define OPT_F10_HY_ID
+#endif
+
+/*
+ * Install family 10h model 10 support
+ */
+#ifdef OPTION_FAMILY10H_PH
+  #if OPTION_FAMILY10H_PH == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevEGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevEGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevEPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevEMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevEHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10PhHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevEGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevEGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevEGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevEGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevEGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10PhMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10PhMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10PhRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define PH_SOCKETS 1
+    #define PH_MODULES 1
+    #define PH_RECOVERY_SOCKETS 1
+    #define PH_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
+    #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES PH_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < PH_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES PH_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_PH_UCODE_BF
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
+          #undef F10_PH_UCODE_BF
+          #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
+      {
+        F10_PH_UCODE_BF
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
+  #else
+    #define OPT_F10_PH_CPU
+    #define OPT_F10_PH_ID
+  #endif
+#else
+  #define OPT_F10_PH_CPU
+  #define OPT_F10_PH_ID
+#endif
+
+
+/*
+ * Install family 10h model 4 support
+ */
+#ifdef OPTION_FAMILY10H_RB
+  #if OPTION_FAMILY10H_RB == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10MultiLinkPciRegisterTable,
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RbPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RbMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RbHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10RbMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10RbMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10RbRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define RB_SOCKETS 8
+    #define RB_MODULES 1
+    #define RB_RECOVERY_SOCKETS 1
+    #define RB_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
+    #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES RB_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < RB_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES RB_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_RB_UCODE_85
+      #define F10_RB_UCODE_C6
+      #define F10_RB_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_RB_UCODE_85
+          #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
+          #undef F10_RB_UCODE_C6
+          #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+          #undef F10_RB_UCODE_C8
+          #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
+      {
+        F10_RB_UCODE_85
+        F10_RB_UCODE_C6
+        F10_RB_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
+  #else
+    #define OPT_F10_RB_CPU
+    #define OPT_F10_RB_ID
+  #endif
+#else
+  #define OPT_F10_RB_CPU
+  #define OPT_F10_RB_ID
+#endif
+
+
+/*
+ * Install unknown family 10h support
+ */
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
+  {
+    #if BASE_FAMILY_PCI == TRUE
+      &F10PciRegisterTable,
+    #endif
+    #if BASE_FAMILY_MSR == TRUE
+      &F10MsrRegisterTable,
+    #endif
+    #if BASE_FAMILY_HT_PCI == TRUE
+      &F10HtPhyRegisterTable,
+    #endif
+    #if OPTION_MULTISOCKET == TRUE
+      #if MODEL_SPECIFIC_PCI == TRUE
+        &F10MultiLinkPciRegisterTable,
+      #endif
+    #endif
+    #if OPTION_MULTISOCKET == FALSE
+      #if MODEL_SPECIFIC_PCI == TRUE
+        &F10SingleLinkPciRegisterTable,
+      #endif
+    #endif
+    #if BASE_FAMILY_WORKAROUNDS == TRUE
+      &F10WorkaroundsTable,
+    #endif
+    // the end.
+    NULL
+  };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
+  {
+    {MsrRegister, SetRegisterForMsrEntry},
+    {PciRegister, SetRegisterForPciEntry},
+    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+    {HtPhyRegister, SetRegisterForHtPhyEntry},
+    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+    {HtHostPciRegister, SetRegisterForHtHostEntry},
+    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+    // End
+    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+  };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
+{
+  0,
+  #if DISABLE_PSTATE == TRUE
+    F10DisablePstate,
+  #else
+    (PF_CPU_DISABLE_PSTATE) CommonAssert,
+  #endif
+  #if TRANSITION_PSTATE == TRUE
+    F10TransitionPstate,
+  #else
+    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+  #endif
+  #if PROC_IDD_MAX == TRUE
+    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_IDD_MAX) CommonAssert,
+  #endif
+  #if GET_TSC_RATE == TRUE
+    F10GetTscRate,
+  #else
+    (PF_CPU_GET_TSC_RATE) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    F10GetCurrentNbFrequency,
+  #else
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #endif
+  #if IS_NBCOF_INIT_NEEDED == TRUE
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+  #else
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+  #endif
+  #if GET_NB_IDD_MAX == TRUE
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #endif
+  #if AP_INITIAL_LAUNCH == TRUE
+    F10LaunchApCore,
+  #else
+    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+  #endif
+  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8,
+  #else
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+  #endif
+  #if GET_AP_MAILBOX_FROM_HW == TRUE
+    F10GetApMailboxFromHardware,
+  #else
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #endif
+  #if SET_AP_CORE_NUMBER == TRUE
+    F10SetApCoreNumber,
+  #else
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if GET_AP_CORE_NUMBER == TRUE
+    F10GetApCoreNumber,
+  #else
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if TRANSFER_AP_CORE_NUMBER == TRUE
+    F10TransferApCoreNumber,
+  #else
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if ID_POSITION_INITIAL_APICID == TRUE
+    F10CpuAmdCoreIdPositionInInitialApicId,
+  #else
+    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+  #endif
+  #if SAVE_FEATURES == TRUE
+    F10SaveFeatures,
+  #else
+    (PF_CPU_SAVE_FEATURES) CommonAssert,
+  #endif
+  #if WRITE_FEATURES == TRUE
+    F10WriteFeatures,
+  #else
+    (PF_CPU_WRITE_FEATURES) CommonAssert,
+  #endif
+  #if SET_WARM_RESET_FLAG == TRUE
+    F10SetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if GET_WARM_RESET_FLAG == TRUE
+    F10GetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if BRAND_STRING1 == TRUE
+    GetF10BrandIdString1,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if BRAND_STRING2 == TRUE
+    GetF10BrandIdString2,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_CACHE_INFO == TRUE
+    GetF10CacheInfo,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_SYSTEM_PM_TABLE == TRUE
+    GetF10SysPmTable,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_WHEA_INIT == TRUE
+    GetF10WheaInitData,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+    F10GetPlatformTypeSpecificInfo,
+  #else
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+  #endif
+  #if IS_NB_PSTATE_ENABLED == TRUE
+    (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+  #else
+    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F10NextLinkHasHtPhyFeats,
+  #else
+    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F10SetHtPhyRegister,
+  #else
+    (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  #endif
+  #if BASE_FAMILY_PCI == TRUE
+    F10GetNextHtLinkFeatures,
+  #else
+    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (REGISTER_TABLE **) F10UnknownRegisterTables,
+  #else
+    NULL,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
+  #else
+    NULL,
+  #endif
+  NULL,
+  NULL,
+  InitCacheDisabled,
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    GetF10EarlyInitOnCoreTable
+  #else
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #endif
+};
+
+// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+  #undef  FAMILY_MMIO_BASE_MASK
+  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+#undef OPT_F10_ID_TABLE
+#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
+#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
+
+#undef OPT_F10_TABLE
+#define OPT_F10_TABLE   OPT_F10_BL_CPU  OPT_F10_DA_CPU  OPT_F10_HY_CPU  OPT_F10_PH_CPU  OPT_F10_RB_CPU  OPT_F10_UNKNOWN_CPU
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
+  #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
+  #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
+#else
+  #define F10_G34_BRANDSTRING1
+  #define F10_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
+  #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
+  #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
+#else
+  #define F10_C32_BRANDSTRING1
+  #define F10_C32_BRANDSTRING2
+#endif
+#if OPTION_S1G3_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
+  #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
+  #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
+#else
+  #define F10_S1G3_BRANDSTRING1
+  #define F10_S1G3_BRANDSTRING2
+#endif
+#if OPTION_S1G4_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
+  #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
+  #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
+#else
+  #define F10_S1G4_BRANDSTRING1
+  #define F10_S1G4_BRANDSTRING2
+#endif
+#if OPTION_ASB2_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
+  #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
+  #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
+#else
+  #define F10_ASB2_BRANDSTRING1
+  #define F10_ASB2_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
+  #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
+  #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
+#else
+  #define F10_AM3_BRANDSTRING1
+  #define F10_AM3_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+  {
+    F10_G34_BRANDSTRING1
+    F10_C32_BRANDSTRING1
+    F10_S1G3_BRANDSTRING1
+    F10_S1G4_BRANDSTRING1
+    F10_ASB2_BRANDSTRING1
+    F10_AM3_BRANDSTRING1
+  };
+
+  CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+  {
+    F10_G34_BRANDSTRING2
+    F10_C32_BRANDSTRING2
+    F10_S1G3_BRANDSTRING2
+    F10_S1G4_BRANDSTRING2
+    F10_ASB2_BRANDSTRING2
+    F10_AM3_BRANDSTRING2
+  };
+
+  CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
+{
+  OPT_F10_BL_ID
+  OPT_F10_DA_ID
+  OPT_F10_HY_ID
+  OPT_F10_PH_ID
+  OPT_F10_RB_ID
+};
+
+#endif  // _OPTION_FAMILY_10H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h
new file mode 100644
index 0000000..9d77332
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h
@@ -0,0 +1,231 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family 15h 'early sample' support
+ *
+ * This file defines the required structures for family 15h pre-production processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 53356 $   @e \$Date: 2011-05-18 14:14:18 -0600 (Wed, 18 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
+#define _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*
+ * Install family 15h model 0x00 - 0x0F Early Sample support
+ */
+
+/**
+ *  Early sample hook point during HTC initialization
+ *
+ *  @param[in,out] HtcRegister             Value of F3x64 to be written.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_HTC_INIT_HOOK (
+  IN OUT   UINT32  *HtcRegister,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_HTC_INIT_HOOK *PF_F15_OR_ES_HTC_INIT_HOOK;
+
+/// Hook points in the core functionality necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_HTC_INIT_HOOK     F15OrHtcInitHook;    ///< Allows for override of a certain processor register value during HTC init
+} F15_OR_ES_CORE_SUPPORT;
+
+/**
+ *  Returns whether or not the processor should enable the CPB feature.
+ *
+ *  @param[in,out] IsEnabled               Whether or not to enable CPB
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_IS_CPB_SUPPORTED (
+  IN OUT   BOOLEAN *IsEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_IS_CPB_SUPPORTED *PF_F15_OR_ES_IS_CPB_SUPPORTED;
+
+
+
+/// Hook points in the CPB feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_IS_CPB_SUPPORTED    F15OrIsCpbSupportedHook;   ///< CPB enablement override
+} F15_OR_ES_CPB_SUPPORT;
+
+/**
+ *  Returns whether or not the processor should enable the C6 feature.
+ *
+ *  @param[in,out] IsEnabled               Whether or not to enable C6
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_IS_C6_SUPPORTED (
+  IN OUT   BOOLEAN *IsEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_IS_C6_SUPPORTED *PF_F15_OR_ES_IS_C6_SUPPORTED;
+
+
+
+/// Hook points in the C6 feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_IS_C6_SUPPORTED    F15OrIsC6SupportedHook;   ///< C6 enablement override
+} F15_OR_ES_C6_SUPPORT;
+
+
+/**
+ *  Workaround to avoid patch loading from causing NB cycles
+ *
+ *  @param[in,out] StdHeader     - Config handle for library and services.
+ *  @param[in,out] SavedMsrValue - Saved a MSR value
+ *
+ */
+typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_START (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT64            *SavedMsrValue
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AVOID_NB_CYCLES_START *PF_F15_OR_ES_AVOID_NB_CYCLES_START;
+
+/**
+ *  Workaround to avoid patch loading from causing NB cycles
+ *
+ *  @param[in,out] StdHeader - Config handle for library and services.
+ *  @param[in] SavedMsrValue - Saved a MSR value
+ *
+ *
+ */
+typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_END (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT64            *SavedMsrValue
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AVOID_NB_CYCLES_END *PF_F15_OR_ES_AVOID_NB_CYCLES_END;
+
+/**
+ *  Workaround for Ax processors after patch is loaded.
+ *
+ *  @param[in] StdHeader     - Config handle for library and services.
+ *  @param[in] IsPatchLoaded - Is patch loaded
+ *
+ *
+ */
+typedef VOID F_F15_OR_ES_AFTER_PATCH_LOADED (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       BOOLEAN IsPatchLoaded
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AFTER_PATCH_LOADED *PF_F15_OR_ES_AFTER_PATCH_LOADED;
+
+/**
+ *  Update the CPU microcode.
+ *
+ *  @param[in] StdHeader   - Config handle for library and services.
+ *
+ *  @retval    TRUE   - Patch Loaded Successfully.
+ *  @retval    FALSE  - Patch Did Not Get Loaded.
+ *
+ */
+typedef BOOLEAN F_F15_OR_ES_LOAD_MCU_PATCH (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_LOAD_MCU_PATCH *PF_F15_OR_ES_LOAD_MCU_PATCH;
+
+
+/// Hook points in the Microcode Update feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_AVOID_NB_CYCLES_START  F15OrESAvoidNbCyclesStart; ///< Workaround to avoid patch loading from causing NB cycles
+  PF_F15_OR_ES_AVOID_NB_CYCLES_END    F15OrESAvoidNbCyclesEnd;   ///< Workaround to avoid patch loading from causing NB cycles
+  PF_F15_OR_ES_LOAD_MCU_PATCH         F15OrUpdateMcuPatchHook;   ///< Processor MCU Update override
+  PF_F15_OR_ES_AFTER_PATCH_LOADED     F15OrESAfterPatchLoaded;   ///< Workaround for Ax processors after patch is loaded
+} F15_OR_ES_MCU_PATCH;
+
+
+
+typedef BOOLEAN F_F15_TN_ES_LOAD_MCU_PATCH (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_TN_ES_LOAD_MCU_PATCH *PF_F15_TN_ES_LOAD_MCU_PATCH;
+
+/// Hook points in the Microcode Update feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_TN_ES_LOAD_MCU_PATCH    F15TnUpdateMcuPatchHook;   ///< Processor MCU Update override
+} F15_TN_ES_MCU_PATCH;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
new file mode 100644
index 0000000..73eeb6f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
@@ -0,0 +1,1570 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 15h support
+ *
+ * This file generates the defaults tables for family 15h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 60770 $   @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_15H_INSTALL_H_
+#define _OPTION_FAMILY_15H_INSTALL_H_
+
+#include "OptionFamily15hEarlySample.h"
+
+/*
+ * Pull in family specific services based on entry point
+ */
+
+/*
+ * Common Family 15h routines
+ */
+extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
+
+/*
+ * Install family 15h model 0 support
+ */
+#ifdef OPTION_FAMILY15H_OR
+  #if OPTION_FAMILY15H_OR == TRUE
+    extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
+    extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
+    extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
+    extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable;
+    #endif
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
+      {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
+      {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15OrMultiLinkPciRegisterTable,
+          &F15OrSingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15OrPciRegisterTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySamplePciRegisterTable,
+          #endif
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15OrMsrRegisterTable,
+          #if (OPTION_AM3_SOCKET_SUPPORT == TRUE) && (CFG_FORCE_MICROSERVER == FALSE)
+            &F15OrAM3MsrWorkaroundTable,
+          #endif
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleMsrRegisterTable,
+          #endif
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15OrSharedMsrRegisterTable,
+          &F15OrSharedMsrCuRegisterTable,
+          &F15OrSharedMsrWorkaroundTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleSharedMsrRegisterTable,
+            &F15OrEarlySampleSharedMsrWorkaroundTable,
+          #endif
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F15OrHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F15OrWorkaroundsTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleWorkaroundsTable,
+          #endif
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15OrGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15OrGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15OrGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F15OrSetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15OrGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F15OrTransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        // F15OrSaveFeatures,
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        // F15OrWriteFeatures,
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15OrMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15OrMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15OrSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15OrRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15OrEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define OR_SOCKETS 8
+    #define OR_MODULES 2
+    #define OR_RECOVERY_SOCKETS 1
+    #define OR_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
+    #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES OR_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < OR_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES OR_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F15_OR_UCODE_17_UNENC
+      #define F15_OR_UCODE_11F_UNENC
+      #define F15_OR_UCODE_425
+      #define F15_OR_UCODE_50D
+      #define F15_OR_UCODE_624
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+          extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 [];
+          #undef F15_OR_UCODE_425
+          #define F15_OR_UCODE_425 CpuF15OrMicrocodePatch06000425,
+
+          extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc [];
+          #undef F15_OR_UCODE_50D
+          #define F15_OR_UCODE_50D CpuF15OrMicrocodePatch0600050D_Enc,
+        #endif
+        extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc [];
+        #undef F15_OR_UCODE_624
+        #define F15_OR_UCODE_624 CpuF15OrMicrocodePatch06000624_Enc,
+      #endif
+
+      CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] =
+      {
+        F15_OR_UCODE_624
+        F15_OR_UCODE_50D
+        F15_OR_UCODE_425
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart;
+      extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd;
+      extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch;
+      extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded;
+
+      CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
+      {
+        F15OrEarlySamplesAvoidNbCyclesStart,
+        F15OrEarlySamplesAvoidNbCyclesEnd,
+        F15OrEarlySamplesLoadMicrocodePatch,
+        F15OrEarlySamplesAfterPatchLoaded
+      };
+    #else
+      CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
+      {
+        (PF_F15_OR_ES_AVOID_NB_CYCLES_START)  CommonVoid,
+        (PF_F15_OR_ES_AVOID_NB_CYCLES_END)    CommonVoid,
+        (PF_F15_OR_ES_LOAD_MCU_PATCH)         LoadMicrocodePatch,
+        (PF_F15_OR_ES_AFTER_PATCH_LOADED)     CommonVoid
+      };
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
+
+      CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
+      {
+        #if AGESA_ENTRY_INIT_EARLY == TRUE
+          F15OrHtcInitEarlySampleHook,
+        #else
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
+        #endif
+      };
+    #else
+      CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
+      {
+        #if AGESA_ENTRY_INIT_EARLY == TRUE
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
+        #else
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
+        #endif
+      };
+    #endif
+
+    #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
+
+  #else  //  OPTION_FAMILY15H_OR == TRUE
+    #define OPT_F15_OR_CPU
+    #define OPT_F15_OR_ID
+  #endif  //  OPTION_FAMILY15H_OR == TRUE
+#else  //  defined (OPTION_FAMILY15H_OR)
+  #define OPT_F15_OR_CPU
+  #define OPT_F15_OR_ID
+#endif  //  defined (OPTION_FAMILY15H_OR)
+
+
+/*
+ * Install family 15h model 10h - 1Fh support
+ */
+#ifdef OPTION_FAMILY15H_TN
+  #if OPTION_FAMILY15H_TN == TRUE
+    extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware;
+    extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15TnPciRegisterTable,
+          &F15TnPciWorkaroundTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15TnMsrRegisterTable,
+          &F15TnSharedMsrRegisterTable,
+          &F15TnSharedMsrCuRegisterTable,
+          &F15TnSharedMsrWorkaroundTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15TnGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15TnGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15TnGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15TnGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15TnMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15TnMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15TnSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15TnRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        NULL,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15TnEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define TN_SOCKETS 1
+    #define TN_MODULES 1
+    #define TN_RECOVERY_SOCKETS 1
+    #define TN_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev;
+    #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES TN_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < TN_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES TN_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F15_TN_UCODE_04
+      #define F15_TN_UCODE_04_UNENC
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+          extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004_Unenc [];
+          #undef F15_TN_UCODE_04_UNENC
+          #define F15_TN_UCODE_04_UNENC CpuF15TnMicrocodePatch06001004_Unenc,
+
+          extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004 [];
+          #undef F15_TN_UCODE_04
+          #define F15_TN_UCODE_04 CpuF15TnMicrocodePatch06001004,
+        #endif
+      #endif
+
+      CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] =
+      {
+        F15_TN_UCODE_04
+        F15_TN_UCODE_04_UNENC
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_TN_ES_LOAD_MCU_PATCH F15TnEarlySamplesLoadMicrocodePatch;
+
+      CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
+      {
+        F15TnEarlySamplesLoadMicrocodePatch
+      };
+    #else
+      CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
+      {
+        (PF_F15_TN_ES_LOAD_MCU_PATCH) LoadMicrocodePatch
+      };
+    #endif
+
+    #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices},
+
+  #else  //  OPTION_FAMILY15H_TN == TRUE
+    #define OPT_F15_TN_CPU
+    #define OPT_F15_TN_ID
+  #endif  //  OPTION_FAMILY15H_TN == TRUE
+#else  //  defined (OPTION_FAMILY15H_TN)
+  #define OPT_F15_TN_CPU
+  #define OPT_F15_TN_ID
+#endif  //  defined (OPTION_FAMILY15H_TN)
+
+/*
+ * Install family 15h model 20h - 2Fh support
+ */
+#ifdef OPTION_FAMILY15H_KM
+  #if OPTION_FAMILY15H_KM == TRUE
+    extern F_CPU_GET_IDD_MAX F15KmGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15KmGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15KmGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15KmGetMinMaxNbFrequency;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15KmGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15KmGetApMailboxFromHardware;
+    extern F_CPU_SET_AP_CORE_NUMBER F15KmSetApCoreNumber;
+    extern F_CPU_GET_AP_CORE_NUMBER F15KmGetApCoreNumber;
+    extern F_CPU_TRANSFER_AP_CORE_NUMBER F15KmTransferApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15KmCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15KmEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15Mod2xPackageLinkMap[];
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15KmCorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
+      {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
+      {0x1F, 0x1F, EvenCoresMapping},                               ///< 5 Compute Units all with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
+      {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
+      {0x1F, 0, AllCoresMapping},                                   ///< 5 Compute Units all with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15KmRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15KmPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15KmMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15KmSharedMsrRegisterTable,
+          &F15KmSharedMsrCuRegisterTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15KmTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15KmServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15KmGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15KmGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15KmGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F15KmSetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15KmGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F15KmTransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15KmMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15KmMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15KmSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15KmRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15KmTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam15Mod2xPackageLinkMap,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15KmCorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15KmEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define KM_SOCKETS 8
+    #define KM_MODULES 2
+    #define KM_RECOVERY_SOCKETS 1
+    #define KM_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15KmLogicalIdAndRev;
+    #define OPT_F15_KM_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15KmLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < KM_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES KM_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < KM_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES KM_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15KmMicroCodePatchArray[] =
+      {
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15KmNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15KmMicroCodePatchArray) / sizeof (CpuF15KmMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F15_KM_CPU {AMD_FAMILY_15_KM, &cpuF15KmServices},
+
+  #else  //  OPTION_FAMILY15H_KM == TRUE
+    #define OPT_F15_KM_CPU
+    #define OPT_F15_KM_ID
+  #endif  //  OPTION_FAMILY15H_KM == TRUE
+#else  //  defined (OPTION_FAMILY15H_KM)
+  #define OPT_F15_KM_CPU
+  #define OPT_F15_KM_ID
+#endif  //  defined (OPTION_FAMILY15H_KM)
+
+/*
+ * Install unknown family 15h support
+ */
+
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
+  {
+    #if BASE_FAMILY_PCI == TRUE
+      &F15PciRegisterTable,
+    #endif
+    #if BASE_FAMILY_MSR == TRUE
+      &F15MsrRegisterTable,
+    #endif
+    // the end.
+    NULL
+  };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
+  {
+    {MsrRegister, SetRegisterForMsrEntry},
+    {PciRegister, SetRegisterForPciEntry},
+    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+    {HtPhyRegister, SetRegisterForHtPhyEntry},
+    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+    {HtHostPciRegister, SetRegisterForHtHostEntry},
+    {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+    {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+    {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+    // End
+    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+  };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
+{
+  0,
+  #if DISABLE_PSTATE == TRUE
+    F15DisablePstate,
+  #else
+    (PF_CPU_DISABLE_PSTATE) CommonAssert,
+  #endif
+  #if TRANSITION_PSTATE == TRUE
+    F15TransitionPstate,
+  #else
+    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+  #endif
+  #if PROC_IDD_MAX == TRUE
+    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_IDD_MAX) CommonAssert,
+  #endif
+  #if GET_TSC_RATE == TRUE
+    F15GetTscRate,
+  #else
+    (PF_CPU_GET_TSC_RATE) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #else
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #endif
+  #if IS_NBCOF_INIT_NEEDED == TRUE
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+  #else
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+  #endif
+  #if GET_NB_IDD_MAX == TRUE
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #endif
+  #if AP_INITIAL_LAUNCH == TRUE
+    F15LaunchApCore,
+  #else
+    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+  #endif
+  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
+  #else
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+  #endif
+  #if GET_AP_MAILBOX_FROM_HW == TRUE
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #else
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #endif
+  #if SET_AP_CORE_NUMBER == TRUE
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if GET_AP_CORE_NUMBER == TRUE
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if TRANSFER_AP_CORE_NUMBER == TRUE
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if ID_POSITION_INITIAL_APICID == TRUE
+    F15CpuAmdCoreIdPositionInInitialApicId,
+  #else
+    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+  #endif
+  #if SAVE_FEATURES == TRUE
+    // F15SaveFeatures,
+    (PF_CPU_SAVE_FEATURES) CommonVoid,
+  #else
+    (PF_CPU_SAVE_FEATURES) CommonAssert,
+  #endif
+  #if WRITE_FEATURES == TRUE
+    // F15WriteFeatures,
+    (PF_CPU_WRITE_FEATURES) CommonVoid,
+  #else
+    (PF_CPU_WRITE_FEATURES) CommonAssert,
+  #endif
+  #if SET_WARM_RESET_FLAG == TRUE
+    F15SetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if GET_WARM_RESET_FLAG == TRUE
+    F15GetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if BRAND_STRING1 == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if BRAND_STRING2 == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_CACHE_INFO == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_SYSTEM_PM_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_WHEA_INIT == TRUE
+    GetF15WheaInitData,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+  #else
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+  #endif
+  #if IS_NB_PSTATE_ENABLED == TRUE
+    F15IsNbPstateEnabled,
+  #else
+    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F15NextLinkHasHtPhyFeats,
+  #else
+    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F15SetHtPhyRegister,
+  #else
+    (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  #endif
+  #if BASE_FAMILY_PCI == TRUE
+    F15GetNextHtLinkFeatures,
+  #else
+    (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (REGISTER_TABLE **) F15UnknownRegisterTables,
+  #else
+    NULL,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
+  #else
+    NULL,
+  #endif
+  NULL,
+  NULL,
+  InitCacheEnabled,
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #else
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #endif
+};
+
+// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+  #undef  FAMILY_MMIO_BASE_MASK
+  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+
+#undef OPT_F15_ID_TABLE
+#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
+#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
+
+#undef OPT_F15_TABLE
+#define OPT_F15_TABLE   OPT_F15_OR_CPU OPT_F15_TN_CPU OPT_F15_KM_CPU OPT_F15_UNKNOWN_CPU
+
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+  #define F15_G34_BRANDSTRING1 NULL,
+  #define F15_G34_BRANDSTRING2 NULL,
+#else
+  #define F15_G34_BRANDSTRING1
+  #define F15_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+  #define F15_C32_BRANDSTRING1 NULL,
+  #define F15_C32_BRANDSTRING2 NULL,
+#else
+  #define F15_C32_BRANDSTRING1
+  #define F15_C32_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+  #define F15_AM3_BRANDSTRING1 NULL,
+  #define F15_AM3_BRANDSTRING2 NULL,
+#else
+  #define F15_AM3_BRANDSTRING1
+  #define F15_AM3_BRANDSTRING2
+#endif
+#if OPTION_FS1_SOCKET_SUPPORT == TRUE
+  #define F15_FS1_BRANDSTRING1 NULL,
+  #define F15_FS1_BRANDSTRING2 NULL,
+#else
+  #define F15_FS1_BRANDSTRING1
+  #define F15_FS1_BRANDSTRING2
+#endif
+#if OPTION_FM2_SOCKET_SUPPORT == TRUE
+  #define F15_FM2_BRANDSTRING1 NULL,
+  #define F15_FM2_BRANDSTRING2 NULL,
+#else
+  #define F15_FM2_BRANDSTRING1
+  #define F15_FM2_BRANDSTRING2
+#endif
+#if OPTION_FP2_SOCKET_SUPPORT == TRUE
+  #define F15_FP2_BRANDSTRING1 NULL,
+  #define F15_FP2_BRANDSTRING2 NULL,
+#else
+  #define F15_FP2_BRANDSTRING1
+  #define F15_FP2_BRANDSTRING2
+#endif
+#if OPTION_G2012_SOCKET_SUPPORT == TRUE
+  #define F15_G2012_BRANDSTRING1 NULL,
+  #define F15_G2012_BRANDSTRING2 NULL,
+#else
+  #define F15_G2012_BRANDSTRING1
+  #define F15_G2012_BRANDSTRING2
+#endif
+#if OPTION_C2012_SOCKET_SUPPORT == TRUE
+  #define F15_C2012_BRANDSTRING1 NULL,
+  #define F15_C2012_BRANDSTRING2 NULL,
+#else
+  #define F15_C2012_BRANDSTRING1
+  #define F15_C2012_BRANDSTRING2
+#endif
+
+
+#if BRAND_STRING1 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
+  {
+    F15_G34_BRANDSTRING1
+    F15_C32_BRANDSTRING1
+    F15_AM3_BRANDSTRING1
+    F15_FS1_BRANDSTRING1
+    F15_FM2_BRANDSTRING1
+    F15_FP2_BRANDSTRING1
+    F15_G2012_BRANDSTRING1
+    F15_C2012_BRANDSTRING1
+  };
+
+  CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
+  {
+    F15_G34_BRANDSTRING2
+    F15_C32_BRANDSTRING2
+    F15_AM3_BRANDSTRING2
+    F15_FS1_BRANDSTRING2
+    F15_FM2_BRANDSTRING2
+    F15_FP2_BRANDSTRING2
+    F15_G2012_BRANDSTRING2
+    F15_C2012_BRANDSTRING2
+  };
+
+  CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
+{
+  OPT_F15_OR_ID
+  OPT_F15_TN_ID
+  OPT_F15_KM_ID
+};
+
+#endif  // _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h
new file mode 100644
index 0000000..715e162
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h
@@ -0,0 +1,988 @@
+/*********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _OPTION_FCH_INSTALL_H_
+#define _OPTION_FCH_INSTALL_H_
+
+#include "AmdFch.h"
+
+#define  FCH_SUPPORT   FALSE
+
+
+/* ACPI block register offset definitions */
+#define PM1_STATUS_OFFSET              0x00
+#define PM1_ENABLE_OFFSET              0x02
+#define PM_CONTROL_OFFSET              0x04
+#define PM_TIMER_OFFSET                0x08
+#define CPU_CONTROL_OFFSET             0x10
+#define EVENT_STATUS_OFFSET            0x20
+#define EVENT_ENABLE_OFFSET            0x24
+
+
+#if  FCH_SUPPORT == TRUE
+  /*
+   * FCH subfunctions
+   */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitResetAb;
+      extern FCH_TASK_ENTRY    FchInitResetSpi;
+      extern FCH_TASK_ENTRY    FchInitResetGec;
+      extern FCH_TASK_ENTRY    FchInitResetSata;
+      extern FCH_TASK_ENTRY    FchInitResetLpc;
+      extern FCH_TASK_ENTRY    FchInitResetPcib;
+      extern FCH_TASK_ENTRY    FchInitResetPcie;
+      extern FCH_TASK_ENTRY    FchInitResetGpp;
+      extern FCH_TASK_ENTRY    FchInitResetUsb;
+      extern FCH_TASK_ENTRY    FchInitResetEhci;
+      extern FCH_TASK_ENTRY    FchInitResetOhci;
+      extern FCH_TASK_ENTRY    FchInitResetXhci;
+      extern FCH_TASK_ENTRY    FchInitResetImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern FCH_TASK_ENTRY    FchInitEnvUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsb;
+      extern FCH_TASK_ENTRY    FchInitEnvAb;
+      extern FCH_TASK_ENTRY    FchInitEnvGpp;
+      extern FCH_TASK_ENTRY    FchInitEnvPcie;
+      extern FCH_TASK_ENTRY    FchInitEnvPcib;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitEnvAbSpecial;
+      extern FCH_TASK_ENTRY    FchInitEnvSpi;
+      extern FCH_TASK_ENTRY    FchInitEnvGec;
+      extern FCH_TASK_ENTRY    FchInitEnvSata;
+      extern FCH_TASK_ENTRY    FchInitEnvIde;
+      extern FCH_TASK_ENTRY    FchInitEnvSd;
+      extern FCH_TASK_ENTRY    FchInitEnvIr;
+      extern FCH_TASK_ENTRY    FchInitEnvAzalia;
+      extern FCH_TASK_ENTRY    FchInitEnvHwm;
+      extern FCH_TASK_ENTRY    FchInitEnvImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern FCH_TASK_ENTRY    FchInitMidHwm;
+      extern FCH_TASK_ENTRY    FchInitMidAzalia;
+      extern FCH_TASK_ENTRY    FchInitMidGec;
+      extern FCH_TASK_ENTRY    FchInitMidSata;
+      extern FCH_TASK_ENTRY    FchInitMidIde;
+      extern FCH_TASK_ENTRY    FchInitMidAb;
+      extern FCH_TASK_ENTRY    FchInitMidUsb;
+      extern FCH_TASK_ENTRY    FchInitMidUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitMidImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern FCH_TASK_ENTRY    FchInitLateHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitLateSpi;
+      extern FCH_TASK_ENTRY    FchInitLateGec;
+      extern FCH_TASK_ENTRY    FchInitLateSata;
+      extern FCH_TASK_ENTRY    FchInitLateIde;
+      extern FCH_TASK_ENTRY    FchInitLatePcib;
+      extern FCH_TASK_ENTRY    FchInitLateAb;
+      extern FCH_TASK_ENTRY    FchInitLatePcie;
+      extern FCH_TASK_ENTRY    FchInitLateGpp;
+      extern FCH_TASK_ENTRY    FchInitLateUsb;
+      extern FCH_TASK_ENTRY    FchInitLateUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitLateImc;
+      extern FCH_TASK_ENTRY    FchInitLateAzalia;
+      extern FCH_TASK_ENTRY    FchInitLateHwm;
+    #endif
+  #endif
+
+  extern FCH_TASK_ENTRY    FchTaskDummy;
+  extern FCH_TASK_ENTRY    FchGppHotplugSmiCallback;
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  /* FCH Interface entries */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern  FCH_INIT      FchInitReset;
+      extern  FCH_INIT      FchResetConstructor;
+
+      #define FP_FCH_INIT_RESET              &FchInitReset
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &FchResetConstructor
+    #else
+      #define FP_FCH_INIT_RESET              &CommonFchInitStub
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern  FCH_INIT      FchInitEnv;
+      extern  FCH_INIT      FchEnvConstructor;
+
+      #define FP_FCH_INIT_ENV                &FchInitEnv
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &FchEnvConstructor
+    #else
+      #define FP_FCH_INIT_ENV                &CommonFchInitStub
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern  FCH_INIT      FchInitMid;
+      extern  FCH_INIT      FchMidConstructor;
+
+      #define FP_FCH_INIT_MID                &FchInitMid
+      #define FP_FCH_INIT_MID_CONSTRUCT      &FchMidConstructor
+    #else
+      #define FP_FCH_INIT_MID                &CommonFchInitStub
+      #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern  FCH_INIT      FchInitLate;
+      extern  FCH_INIT      FchLateConstructor;
+
+      #define FP_FCH_INIT_LATE               &FchInitLate
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &FchLateConstructor
+    #else
+      #define FP_FCH_INIT_LATE               &CommonFchInitStub
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+    #endif
+  #endif
+
+  /* FCH subcomponent build options */
+  #undef  FCH_NO_HWACPI_SUPPORT
+  #undef  FCH_NO_AB_SUPPORT
+  #undef  FCH_NO_SPI_SUPPORT
+  #undef  FCH_NO_GEC_SUPPORT
+  #undef  FCH_NO_SATA_SUPPORT
+  #undef  FCH_NO_IDE_SUPPORT
+  #undef  FCH_NO_LPC_SUPPORT
+  #undef  FCH_NO_PCIB_SUPPORT
+  #undef  FCH_NO_PCIE_SUPPORT
+  #undef  FCH_NO_GPP_SUPPORT
+  #undef  FCH_NO_USB_SUPPORT
+  #undef  FCH_NO_EHCI_SUPPORT
+  #undef  FCH_NO_OHCI_SUPPORT
+  #undef  FCH_NO_XHCI_SUPPORT
+  #undef  FCH_NO_IMC_SUPPORT
+  #undef  FCH_NO_SD_SUPPORT
+  #undef  FCH_NO_IR_SUPPORT
+  #undef  FCH_NO_AZALIA_SUPPORT
+  #undef  FCH_NO_HWM_SUPPORT
+
+  //
+  // Installable blocks depending on build switches
+  //
+  #ifndef FCH_NO_HWACPI_SUPPORT
+    #define BLOCK_HWACPI_SIZE           sizeof (FCH_ACPI)
+    #define InstallFchInitResetHwAcpiP  &FchInitResetHwAcpiP
+    #define InstallFchInitResetHwAcpi   &FchInitResetHwAcpi
+    #define InstallFchInitEnvHwAcpiP    &FchInitEnvHwAcpiP
+    #define InstallFchInitEnvHwAcpi     &FchInitEnvHwAcpi
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchInitLateHwAcpi
+  #else
+    #define BLOCK_HWACPI_SIZE           0
+    #define InstallFchInitResetHwAcpiP  &FchTaskDummy
+    #define InstallFchInitResetHwAcpi   &FchTaskDummy
+    #define InstallFchInitEnvHwAcpi     &FchTaskDummy
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_AB_SUPPORT
+    #define BLOCK_AB_SIZE               sizeof (FCH_AB)
+    #define InstallFchInitResetAb       &FchInitResetAb
+    #define InstallFchInitEnvAb         &FchInitEnvAb
+    #define InstallFchInitEnvAbS        &FchInitEnvAbSpecial
+    #define InstallFchInitMidAb         &FchInitMidAb
+    #define InstallFchInitLateAb        &FchInitLateAb
+  #else
+    #define BLOCK_AB_SIZE               0
+    #define InstallFchInitResetAb       &FchTaskDummy
+    #define InstallFchInitEnvAb         &FchTaskDummy
+    #define InstallFchInitEnvAbS        &FchTaskDummy
+    #define InstallFchInitMidAb         &FchTaskDummy
+    #define InstallFchInitLateAb        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SPI_SUPPORT
+    #define BLOCK_SPI_SIZE              sizeof (FCH_SPI)
+    #define InstallFchInitResetSpi      &FchInitResetSpi
+    #define InstallFchInitEnvSpi        &FchInitEnvSpi
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchInitLateSpi
+  #else
+    #define BLOCK_SPI_SIZE              0
+    #define InstallFchInitResetSpi      &FchTaskDummy
+    #define InstallFchInitEnvSpi        &FchTaskDummy
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GEC_SUPPORT
+    #define BLOCK_GEC_SIZE              sizeof (FCH_GEC)
+    #define InstallFchInitResetGec      &FchInitResetGec
+    #define InstallFchInitEnvGec        &FchInitEnvGec
+    #define InstallFchInitMidGec        &FchInitMidGec
+    #define InstallFchInitLateGec       &FchInitLateGec
+  #else
+    #define BLOCK_GEC_SIZE              0
+    #define InstallFchInitResetGec      &FchTaskDummy
+    #define InstallFchInitEnvGec        &FchTaskDummy
+    #define InstallFchInitMidGec        &FchTaskDummy
+    #define InstallFchInitLateGec       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SATA_SUPPORT
+    #define BLOCK_SATA_SIZE             sizeof (FCH_SATA)
+    #define InstallFchInitResetSata     &FchInitResetSata
+    #define InstallFchInitEnvSata       &FchInitEnvSata
+    #define InstallFchInitMidSata       &FchInitMidSata
+    #define InstallFchInitLateSata      &FchInitLateSata
+  #else
+    #define BLOCK_SATA_SIZE             0
+    #define InstallFchInitResetSata     &FchTaskDummy
+    #define InstallFchInitEnvSata       &FchTaskDummy
+    #define InstallFchInitMidSata       &FchTaskDummy
+    #define InstallFchInitLateSata      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IDE_SUPPORT
+    #define BLOCK_IDE_SIZE              sizeof (FCH_IDE)
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchInitEnvIde
+    #define InstallFchInitMidIde        &FchInitMidIde
+    #define InstallFchInitLateIde       &FchInitLateIde
+  #else
+    #define BLOCK_IDE_SIZE              0
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchTaskDummy
+    #define InstallFchInitMidIde        &FchTaskDummy
+    #define InstallFchInitLateIde       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_LPC_SUPPORT
+    #define BLOCK_LPC_SIZE              sizeof (FCH_LPC)
+    #define InstallFchInitResetLpc      &FchInitResetLpc
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #else
+    #define BLOCK_LPC_SIZE              0
+    #define InstallFchInitResetLpc      &FchTaskDummy
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIB_SUPPORT
+    #define BLOCK_PCIB_SIZE             sizeof (FCH_PCIB)
+    #define InstallFchInitResetPcib     &FchInitResetPcib
+    #define InstallFchInitEnvPcib       &FchInitEnvPcib
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchInitLatePcib
+  #else
+    #define BLOCK_PCIB_SIZE             0
+    #define InstallFchInitResetPcib     &FchTaskDummy
+    #define InstallFchInitEnvPcib       &FchTaskDummy
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIE_SUPPORT
+    #define InstallFchInitResetPcie     &FchInitResetPcie
+    #define InstallFchInitEnvPcie       &FchInitEnvPcie
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchInitLatePcie
+  #else
+    #define InstallFchInitResetPcie     &FchTaskDummy
+    #define InstallFchInitEnvPcie       &FchTaskDummy
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GPP_SUPPORT
+    #define BLOCK_GPP_SIZE              sizeof (FCH_GPP)
+    #define InstallFchInitResetGpp      &FchInitResetGpp
+    #define InstallFchInitEnvGpp        &FchInitEnvGpp
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchInitLateGpp
+    #define InstallHpSmiCallback        &FchGppHotplugSmiCallback
+  #else
+    #define BLOCK_GPP_SIZE              0
+    #define InstallFchInitResetGpp      &FchTaskDummy
+    #define InstallFchInitEnvGpp        &FchTaskDummy
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchTaskDummy
+    #define InstallHpSmiCallback        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_USB_SUPPORT
+    #define BLOCK_USB_SIZE              sizeof (FCH_USB)
+    #define InstallFchInitResetUsb      &FchInitResetUsb
+    #define InstallFchInitEnvUsb        &FchInitEnvUsb
+    #define InstallFchInitMidUsb        &FchInitMidUsb
+    #define InstallFchInitLateUsb       &FchInitLateUsb
+  #else
+    #define BLOCK_USB_SIZE              0
+    #define InstallFchInitResetUsb      &FchTaskDummy
+    #define InstallFchInitEnvUsb        &FchTaskDummy
+    #define InstallFchInitMidUsb        &FchTaskDummy
+    #define InstallFchInitLateUsb       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_EHCI_SUPPORT
+    #define InstallFchInitResetUsbEhci  &FchInitResetEhci
+    #define InstallFchInitEnvUsbEhci    &FchInitEnvUsbEhci
+    #define InstallFchInitMidUsbEhci    &FchInitMidUsbEhci
+    #define InstallFchInitLateUsbEhci   &FchInitLateUsbEhci
+  #else
+    #define InstallFchInitResetUsbEhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbEhci    &FchTaskDummy
+    #define InstallFchInitMidUsbEhci    &FchTaskDummy
+    #define InstallFchInitLateUsbEhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_OHCI_SUPPORT
+    #define InstallFchInitResetUsbOhci  &FchInitResetOhci
+    #define InstallFchInitEnvUsbOhci    &FchInitEnvUsbOhci
+    #define InstallFchInitMidUsbOhci    &FchInitMidUsbOhci
+    #define InstallFchInitLateUsbOhci   &FchInitLateUsbOhci
+  #else
+    #define InstallFchInitResetUsbOhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbOhci    &FchTaskDummy
+    #define InstallFchInitMidUsbOhci    &FchTaskDummy
+    #define InstallFchInitLateUsbOhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_XHCI_SUPPORT
+    #define InstallFchInitResetUsbXhci  &FchInitResetXhci
+    #define InstallFchInitEnvUsbXhci    &FchInitEnvUsbXhci
+    #define InstallFchInitMidUsbXhci    &FchInitMidUsbXhci
+    #define InstallFchInitLateUsbXhci   &FchInitLateUsbXhci
+  #else
+    #define InstallFchInitResetUsbXhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbXhci    &FchTaskDummy
+    #define InstallFchInitMidUsbXhci    &FchTaskDummy
+    #define InstallFchInitLateUsbXhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IMC_SUPPORT
+    #define BLOCK_IMC_SIZE              sizeof (FCH_IMC)
+    #define InstallFchInitResetImc      &FchInitResetImc
+    #define InstallFchInitEnvImc        &FchInitEnvImc
+    #define InstallFchInitMidImc        &FchInitMidImc
+    #define InstallFchInitLateImc       &FchInitLateImc
+  #else
+    #define BLOCK_IMC_SIZE              0
+    #define InstallFchInitResetImc      &FchTaskDummy
+    #define InstallFchInitEnvImc        &FchTaskDummy
+    #define InstallFchInitMidImc        &FchTaskDummy
+    #define InstallFchInitLateImc       &FchTaskDummy
+  #endif
+
+
+  #ifndef FCH_NO_SD_SUPPORT
+    #define BLOCK_SD_SIZE               sizeof (FCH_SD)
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchInitEnvSd
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #else
+    #define BLOCK_SD_SIZE               0
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchTaskDummy
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IR_SUPPORT
+    #define BLOCK_IR_SIZE               sizeof (FCH_IR)
+    #define InstallFchInitResetIr       &FchTaskDummy
+    #define InstallFchInitEnvIr         &FchInitEnvIr
+    #define InstallFchInitMidIr         &FchTaskDummy
+    #define InstallFchInitLateIr        &FchTaskDummy
+  #else
+    #define BLOCK_IR_SIZE               0
+    #define InstallFchInitResetIr       &FchTaskDummy
+    #define InstallFchInitEnvIr         &FchTaskDummy
+    #define InstallFchInitMidIr         &FchTaskDummy
+    #define InstallFchInitLateIr        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_AZALIA_SUPPORT
+    #define BLOCK_AZALIA_SIZE           sizeof (FCH_AZALIA)
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchInitEnvAzalia
+    #define InstallFchInitMidAzalia     &FchInitMidAzalia
+    #define InstallFchInitLateAzalia    &FchInitLateAzalia
+  #else
+    #define BLOCK_AZALIA_SIZE           0
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchTaskDummy
+    #define InstallFchInitMidAzalia     &FchTaskDummy
+    #define InstallFchInitLateAzalia    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_HWM_SUPPORT
+    #define BLOCK_HWM_SIZE              sizeof (FCH_HWM)
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchInitEnvHwm
+    #define InstallFchInitMidHwm        &FchInitMidHwm
+    #define InstallFchInitLateHwm       &FchInitLateHwm
+  #else
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchTaskDummy
+    #define InstallFchInitMidHwm        &FchTaskDummy
+    #define InstallFchInitLateHwm       &FchTaskDummy
+  #endif
+
+
+  #define BLOCK_SMBUS_SIZE      sizeof (FCH_SMBUS)
+  #define BLOCK_HPET_SIZE       sizeof (FCH_HPET)
+  #define BLOCK_GCPU_SIZE       sizeof (FCH_GCPU)
+  #define BLOCK_SDB_SIZE        sizeof (FCH_SERIALDB)
+  #define BLOCK_MISC_SIZE       sizeof (FCH_MISC)
+
+
+  // Optionally declare OEM hooks after each phase
+  #ifndef FCH_INIT_RESET_HOOK
+    #define InstallFchInitResetHook     FchTaskDummy
+  #else
+    #define InstallFchInitResetHook     OemFchInitResetHook
+  #endif
+
+
+  //
+  // Define FCH build time options and configurations
+  //
+  #ifdef BLDCFG_SMBUS0_BASE_ADDRESS
+    #define CFG_SMBUS0_BASE_ADDRESS           BLDCFG_SMBUS0_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS0_BASE_ADDRESS           DFLT_SMBUS0_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMBUS1_BASE_ADDRESS
+    #define CFG_SMBUS1_BASE_ADDRESS           BLDCFG_SMBUS1_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS1_BASE_ADDRESS           DFLT_SMBUS1_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SIO_PME_BASE_ADDRESS
+    #define CFG_SIO_PME_BASE_ADDRESS          BLDCFG_SIO_PME_BASE_ADDRESS
+  #else
+    #define CFG_SIO_PME_BASE_ADDRESS          DFLT_SIO_PME_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       DFLT_ACPI_GPE0_BLOCK_ADDRESS
+  #endif
+
+
+  #ifdef BLDCFG_WATCHDOG_TIMER_BASE
+    #define CFG_WATCHDOG_TIMER_BASE           BLDCFG_WATCHDOG_TIMER_BASE
+  #else
+    #define CFG_WATCHDOG_TIMER_BASE           DFLT_WATCHDOG_TIMER_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       BLDCFG_ACPI_PMA_BLK_ADDRESS
+  #else
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       DFLT_ACPI_PMA_CNT_BLK_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
+    #define CFG_SMI_CMD_PORT_ADDRESS          BLDCFG_SMI_CMD_PORT_ADDRESS
+  #else
+    #define CFG_SMI_CMD_PORT_ADDRESS          DFLT_SMI_CMD_PORT
+  #endif
+
+  #ifdef BLDCFG_ROM_BASE_ADDRESS
+    #define CFG_SPI_ROM_BASE_ADDRESS          BLDCFG_ROM_BASE_ADDRESS
+  #else
+    #define CFG_SPI_ROM_BASE_ADDRESS          DFLT_SPI_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_GEC_SHADOW_ROM_BASE
+    #define CFG_GEC_SHADOW_ROM_BASE           BLDCFG_GEC_SHADOW_ROM_BASE
+  #else
+    #define CFG_GEC_SHADOW_ROM_BASE           DFLT_GEC_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_HPET_BASE_ADDRESS
+    #define CFG_HPET_BASE_ADDRESS           BLDCFG_HPET_BASE_ADDRESS
+  #else
+    #define CFG_HPET_BASE_ADDRESS           DFLT_HPET_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_AZALIA_SSID
+    #define CFG_AZALIA_SSID                 BLDCFG_AZALIA_SSID
+  #else
+    #define CFG_AZALIA_SSID                 DFLT_AZALIA_SSID
+  #endif
+
+  #ifdef BLDCFG_SMBUS_SSID
+    #define CFG_SMBUS_SSID                  BLDCFG_SMBUS_SSID
+  #else
+    #define CFG_SMBUS_SSID                  DFLT_SMBUS_SSID
+  #endif
+
+  #ifdef BLDCFG_IDE_SSID
+    #define CFG_IDE_SSID                    BLDCFG_IDE_SSID
+  #else
+    #define CFG_IDE_SSID                    DFLT_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_AHCI_SSID
+    #define CFG_SATA_AHCI_SSID              BLDCFG_SATA_AHCI_SSID
+  #else
+    #define CFG_SATA_AHCI_SSID              DFLT_SATA_AHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_IDE_SSID
+    #define CFG_SATA_IDE_SSID               BLDCFG_SATA_IDE_SSID
+  #else
+    #define CFG_SATA_IDE_SSID               DFLT_SATA_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID5_SSID
+    #define CFG_SATA_RAID5_SSID             BLDCFG_SATA_RAID5_SSID
+  #else
+    #define CFG_SATA_RAID5_SSID             DFLT_SATA_RAID5_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID_SSID
+    #define CFG_SATA_RAID_SSID              BLDCFG_SATA_RAID_SSID
+  #else
+    #define CFG_SATA_RAID_SSID              DFLT_SATA_RAID_SSID
+  #endif
+
+  #ifdef BLDCFG_EHCI_SSID
+    #define CFG_EHCI_SSID                   BLDCFG_EHCI_SSID
+  #else
+    #define CFG_EHCI_SSID                   DFLT_EHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_OHCI_SSID
+    #define CFG_OHCI_SSID                   BLDCFG_OHCI_SSID
+  #else
+    #define CFG_OHCI_SSID                   DFLT_OHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_LPC_SSID
+    #define CFG_LPC_SSID                    BLDCFG_LPC_SSID
+  #else
+    #define CFG_LPC_SSID                    DFLT_LPC_SSID
+  #endif
+
+  #ifdef BLDCFG_SD_SSID
+    #define CFG_SD_SSID                     BLDCFG_SD_SSID
+  #else
+    #define CFG_SD_SSID                     DFLT_SD_SSID
+  #endif
+
+  #ifdef BLDCFG_XHCI_SSID
+    #define CFG_XHCI_SSID                   BLDCFG_XHCI_SSID
+  #else
+    #define CFG_XHCI_SSID                   DFLT_XHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
+    #define CFG_FCH_PORT80_BEHIND_PCIB      BLDCFG_FCH_PORT80_BEHIND_PCIB
+  #else
+    #define CFG_FCH_PORT80_BEHIND_PCIB      DFLT_FCH_PORT80_BEHIND_PCIB
+  #endif
+
+  #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #else
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_LINK_CONFIG
+    #define CFG_FCH_GPP_LINK_CONFIG         BLDCFG_FCH_GPP_LINK_CONFIG
+  #else
+    #define CFG_FCH_GPP_LINK_CONFIG         DFLT_FCH_GPP_LINK_CONFIG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
+    #define CFG_FCH_GPP_PORT0_PRESENT       BLDCFG_FCH_GPP_PORT0_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT0_PRESENT       DFLT_FCH_GPP_PORT0_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
+    #define CFG_FCH_GPP_PORT1_PRESENT       BLDCFG_FCH_GPP_PORT1_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT1_PRESENT       DFLT_FCH_GPP_PORT1_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
+    #define CFG_FCH_GPP_PORT2_PRESENT       BLDCFG_FCH_GPP_PORT2_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT2_PRESENT       DFLT_FCH_GPP_PORT2_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
+    #define CFG_FCH_GPP_PORT3_PRESENT       BLDCFG_FCH_GPP_PORT3_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT3_PRESENT       DFLT_FCH_GPP_PORT3_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       BLDCFG_FCH_GPP_PORT0_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       DFLT_FCH_GPP_PORT0_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       BLDCFG_FCH_GPP_PORT1_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       DFLT_FCH_GPP_PORT1_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       BLDCFG_FCH_GPP_PORT2_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       DFLT_FCH_GPP_PORT2_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       BLDCFG_FCH_GPP_PORT3_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       DFLT_FCH_GPP_PORT3_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
+    #define CFG_FCH_ESATA_PORT_BITMAP       BLDCFG_FCH_ESATA_PORT_BITMAP
+  #else
+    #define CFG_FCH_ESATA_PORT_BITMAP       0
+  #endif
+
+  #ifdef BLDCFG_FCH_IR_PIN_CONTROL
+    #define CFG_FCH_IR_PIN_CONTROL          BLDCFG_FCH_IR_PIN_CONTROL
+  #else
+    #define CFG_FCH_IR_PIN_CONTROL          (BIT5 | BIT1 | BIT0)
+  #endif
+
+  #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
+    #define CFG_FCH_SD_CLOCK_CONTROL        BLDCFG_FCH_SD_CLOCK_CONTROL
+  #else
+    #define CFG_FCH_SD_CLOCK_CONTROL        Sd50MhzTraceCableLengthWithinSixInches
+  #endif
+
+  #ifdef BLDCFG_FCH_SCI_MAP_LIST
+    #define CFG_FCH_SCI_MAP_LIST            BLDCFG_FCH_SCI_MAP_LIST
+  #else
+    #define CFG_FCH_SCI_MAP_LIST            NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_SATA_PHY_LIST
+    #define CFG_FCH_SATA_PHY_LIST           BLDCFG_FCH_SATA_PHY_LIST
+  #else
+    #define CFG_FCH_SATA_PHY_LIST           NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
+    #define CFG_FCH_GPIO_CONTROL_LIST       BLDCFG_FCH_GPIO_CONTROL_LIST
+  #else
+    #define CFG_FCH_GPIO_CONTROL_LIST       NULL
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      //
+      // Define task list for InitReset phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
+        InstallFchInitResetHwAcpiP,
+        InstallFchInitResetAb,
+        InstallFchInitResetSpi,
+        InstallFchInitResetGec,
+        InstallFchInitResetHwAcpi,
+        InstallFchInitResetSata,
+        InstallFchInitResetLpc,
+        InstallFchInitResetPcib,
+        InstallFchInitResetPcie,
+        InstallFchInitResetGpp,
+        InstallFchInitResetUsb,
+        InstallFchInitResetUsbEhci,
+        InstallFchInitResetUsbOhci,
+        InstallFchInitResetUsbXhci,
+        InstallFchInitResetImc,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for InitEnv phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
+        InstallFchInitEnvHwAcpiP,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvImc,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvUsbEhci,
+        InstallFchInitEnvUsbOhci,
+        InstallFchInitEnvUsbXhci,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvAbS,
+        InstallFchInitEnvHwm,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      //
+      // Define task list for InitMid phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
+        InstallFchInitMidImc,
+        InstallFchInitMidUsb,
+        InstallFchInitMidUsbEhci,
+        InstallFchInitMidUsbOhci,
+        InstallFchInitMidUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitMidHwm,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for InitLate phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateGec,
+        InstallFchInitLateAzalia,
+        InstallFchInitLateImc,
+        InstallFchInitLateHwm,
+        InstallFchInitLateGpp,
+        InstallFchInitLateHwAcpi,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for S3 resume before PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvAbS,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for S3 resume after PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateHwAcpi,
+        InstallFchInitEnvHwm,
+        InstallFchInitLateHwm,
+        NULL
+      };
+    #endif
+  #endif
+  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
+
+
+#else   // FCH_SUPPORT == FALSE
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  #define FP_FCH_INIT_RESET              &CommonFchInitStub
+  #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+  #define FP_FCH_INIT_ENV                &CommonFchInitStub
+  #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_MID                &CommonFchInitStub
+  #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_LATE               &CommonFchInitStub
+  #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+
+  #define CFG_SMBUS0_BASE_ADDRESS            0
+  #define CFG_SMBUS1_BASE_ADDRESS            0
+  #define CFG_SIO_PME_BASE_ADDRESS           0
+  #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS      0
+  #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_GPE0_BLOCK_ADDRESS        0
+  #define CFG_SPI_ROM_BASE_ADDRESS           0
+  #define CFG_WATCHDOG_TIMER_BASE            0
+  #define CFG_HPET_BASE_ADDRESS              0
+  #define CFG_SMI_CMD_PORT_ADDRESS           0
+  #define CFG_ACPI_PMA_CNTBLK_ADDRESS        0
+  #define CFG_GEC_SHADOW_ROM_BASE            0
+  #define CFG_AZALIA_SSID                    0
+  #define CFG_SMBUS_SSID                     0
+  #define CFG_IDE_SSID                       0
+  #define CFG_SATA_AHCI_SSID                 0
+  #define CFG_SATA_IDE_SSID                  0
+  #define CFG_SATA_RAID5_SSID                0
+  #define CFG_SATA_RAID_SSID                 0
+  #define CFG_EHCI_SSID                      0
+  #define CFG_OHCI_SSID                      0
+  #define CFG_LPC_SSID                       0
+  #define CFG_SD_SSID                        0
+  #define CFG_XHCI_SSID                      0
+  #define CFG_FCH_PORT80_BEHIND_PCIB         0
+  #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP     0
+  #define CFG_FCH_GPP_LINK_CONFIG            0
+  #define CFG_FCH_GPP_PORT0_PRESENT          0
+  #define CFG_FCH_GPP_PORT1_PRESENT          0
+  #define CFG_FCH_GPP_PORT2_PRESENT          0
+  #define CFG_FCH_GPP_PORT3_PRESENT          0
+  #define CFG_FCH_GPP_PORT0_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT1_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT2_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT3_HOTPLUG          0
+
+  #define CFG_FCH_ESATA_PORT_BITMAP          0
+  #define CFG_FCH_IR_PIN_CONTROL             0
+  #define CFG_FCH_SD_CLOCK_CONTROL           0
+  #define CFG_FCH_SCI_MAP_LIST               0
+  #define CFG_FCH_SATA_PHY_LIST              0
+  #define CFG_FCH_GPIO_CONTROL_LIST          0
+
+#endif
+
+
+CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
+  FP_FCH_INIT_RESET,
+  FP_FCH_INIT_RESET_CONSTRUCT,
+  FP_FCH_INIT_ENV,
+  FP_FCH_INIT_ENV_CONSTRUCT,
+  FP_FCH_INIT_MID,
+  FP_FCH_INIT_MID_CONSTRUCT,
+  FP_FCH_INIT_LATE,
+  FP_FCH_INIT_LATE_CONSTRUCT,
+};
+
+#endif  // _OPTION_FCH_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h
new file mode 100644
index 0000000..a7b1173
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD GFX Recovery option API.
+ *
+ * Contains structures and values used to control the GfxRecovery option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GFX_RECOVERY_H_
+#define _OPTION_GFX_RECOVERY_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#define GFX_RECOVERY_STRUCT_VERSION  0x01
+
+/// The Option Configuration of GFX Recovery
+typedef struct  {
+  UINT16              OptGfxRecoveryVersion;       ///< The version number of GFX Recovery
+  OPTION_GFX_RECOVERY_FEATURE  *GfxRecoveryFeature;        ///< The Option Feature of GFX Recovery
+} OPTION_GFX_RECOVERY_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h
new file mode 100644
index 0000000..1f29c8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h
@@ -0,0 +1,54 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GfxRecovery
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
+#define _OPTION_GFX_RECOVERY_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h
new file mode 100644
index 0000000..4b58645
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ALIB option API.
+ *
+ * Contains structures and values used to control the ALIB option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 53099 $   @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GNB_H_
+#define _OPTION_GNB_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef AGESA_STATUS OPTION_GNB_FEATURE (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+/// The Option Configuration
+typedef struct {
+  UINT64                Type;                   ///< Type
+  OPTION_GNB_FEATURE    *GnbFeature;            ///< The GNB Feature
+} OPTION_GNB_CONFIGURATION;
+
+/// The Build time options configuration
+typedef struct {
+  BOOLEAN               IgfxModeAsPcieEp;                   ///< Itegrated Gfx mode Pcie EP or Legacy
+  BOOLEAN               LclkDeepSleepEn;                    ///< Default for LCLK deep sleep
+  BOOLEAN               LclkDpmEn;                          ///< Default for LCLK DPM
+  BOOLEAN               GmcPowerGateStutterOnly;            ///< Force GMC power gate to stutter only
+  BOOLEAN               SmuSclkClockGatingEnable;           ///< Control SMU SCLK gating
+  BOOLEAN               PcieAspmBlackListEnable;            ///< Control Pcie Aspm Black List
+  BOOLEAN               IvrsRelativeAddrNamesSupport;       ///< Support for relative address names
+  BOOLEAN               GnbLoadRealFuseTable;               ///< Support for fuse table loading
+  UINT32                CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32                CfgGnbLinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32                CfgGnbLinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32                CfgGnbLinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us
+  UINT8                 CfgGnbTrainingAlgorithm;            ///< distribution of training across interface calls
+  BOOLEAN               CfgForceCableSafeOff;               ///< Force cable safe off
+  BOOLEAN               CfgOrbClockGatingEnable;            ///< Control ORB clock gating
+  UINT8                 CfgPciePowerGatingFlags;            ///< Pcie Power gating flags
+  BOOLEAN               CfgIocLclkClockGatingEnable;        ///< Control IOC LCLK clock gating
+  BOOLEAN               CfgIocSclkClockGatingEnable;        ///< Control IOC SCLK clock gating
+  BOOLEAN               CfgIommuL1ClockGatingEnable;        ///< Control IOMMU L1 clock gating
+  BOOLEAN               CfgIommuL2ClockGatingEnable;        ///< Control IOMMU L2 clock gating
+  BOOLEAN               CfgAltVddNb;                        ///< AltVDDNB support
+  BOOLEAN               CfgBapmSupport;                     ///< BAPM support
+  BOOLEAN               CfgUnusedSimdPowerGatingEnable;     ///< Control unused SIMD power gate
+  BOOLEAN               CfgUnusedRbPowerGatingEnable;       ///< Control unused SIMD power gate
+} GNB_BUILD_OPTIONS;
+
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
new file mode 100644
index 0000000..7733859
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
@@ -0,0 +1,591 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GNB
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 53099 $   @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GNB_INSTALL_H_
+#define _OPTION_GNB_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+//---------------------------------------------------------------------------------------------------
+// Family installation
+//---------------------------------------------------------------------------------------------------
+
+
+#define GNB_TYPE_LN   FALSE
+#define GNB_TYPE_ON   FALSE
+
+#if (OPTION_FAMILY14H_ON == TRUE)
+  #undef  GNB_TYPE_ON
+  #define GNB_TYPE_ON  TRUE
+#endif
+
+#if (OPTION_FAMILY12H_LN == TRUE)
+  #undef  GNB_TYPE_LN
+  #define GNB_TYPE_LN  TRUE
+#endif
+
+
+#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+//---------------------------------------------------------------------------------------------------
+// Service installation
+//---------------------------------------------------------------------------------------------------
+
+  #include "Gnb.h"
+  #include "GnbPcie.h"
+
+  #define SERVICES_POINTER  NULL
+  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
+
+//---------------------------------------------------------------------------------------------------
+// BUILD options
+//---------------------------------------------------------------------------------------------------
+
+  #ifndef CFG_IGFX_AS_PCIE_EP
+    #define CFG_IGFX_AS_PCIE_EP                           TRUE
+  #endif
+
+  #ifndef CFG_LCLK_DEEP_SLEEP_EN
+    #define  CFG_LCLK_DEEP_SLEEP_EN                       TRUE
+  #endif
+
+  #ifndef CFG_LCLK_DPM_EN
+    #define CFG_LCLK_DPM_EN                               TRUE
+  #endif
+
+  #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
+    #define CFG_GMC_POWER_GATE_STUTTER_ONLY               FALSE
+  #endif
+
+  #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_ON == TRUE)
+      #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+    #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE               TRUE
+  #endif
+
+  #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
+    #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT      FALSE
+  #endif
+
+  #ifndef CFG_GNB_LOAD_REAL_FUSE
+    #define  CFG_GNB_LOAD_REAL_FUSE                       TRUE
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
+    #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_L0_POOLING
+    #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
+    #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
+    #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
+  #endif
+
+  #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
+  #else
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
+  #endif
+
+  #ifndef CFG_GNB_FORCE_CABLESAFE_OFF
+    #define CFG_GNB_FORCE_CABLESAFE_OFF                   FALSE
+  #endif
+
+  #ifndef CFG_ORB_CLOCK_GATING_ENABLE
+      #define CFG_ORB_CLOCK_GATING_ENABLE                 TRUE
+    #endif
+
+  #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
+    #define CFG_GNB_PCIE_POWERGATING_FLAGS                0x0
+  #endif
+
+  #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
+      #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
+      #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
+      #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
+      #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_GNB_ALTVDDNB_SUPPORT
+    #define CFG_GNB_ALTVDDNB_SUPPORT                      TRUE
+  #endif
+
+  #ifndef CFG_GNB_BAPM_SUPPORT
+    #define CFG_GNB_BAPM_SUPPORT                          TRUE
+  #endif
+
+  #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
+    #define CFG_UNUSED_SIMD_POWERGATING_ENABLE            TRUE
+  #endif
+
+  #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
+    #define CFG_UNUSED_RB_POWERGATING_ENABLE              FALSE
+  #endif
+
+  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
+    CFG_IGFX_AS_PCIE_EP,
+    CFG_LCLK_DEEP_SLEEP_EN,
+    CFG_LCLK_DPM_EN,
+    CFG_GMC_POWER_GATE_STUTTER_ONLY,
+    CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
+    CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
+    CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
+    CFG_GNB_LOAD_REAL_FUSE,
+    CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
+    CFG_GNB_PCIE_LINK_L0_POOLING,
+    CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
+    CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
+    CFG_GNB_PCIE_TRAINING_ALGORITHM,
+    CFG_GNB_FORCE_CABLESAFE_OFF,
+    CFG_ORB_CLOCK_GATING_ENABLE,
+    CFG_GNB_PCIE_POWERGATING_FLAGS,
+    CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
+    CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
+    CFG_GNB_ALTVDDNB_SUPPORT,
+    CFG_GNB_BAPM_SUPPORT,
+    CFG_UNUSED_SIMD_POWERGATING_ENABLE,
+    CFG_UNUSED_RB_POWERGATING_ENABLE
+  };
+
+  //---------------------------------------------------------------------------------------------------
+  // Module entries
+  //---------------------------------------------------------------------------------------------------
+
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLY_INIT
+      #define OPTION_NB_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtEarly;
+      #define OPTION_NBINITATEARLY_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
+    #else
+      #define OPTION_NBINITATEARLY_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+  // SMU init
+    #ifndef OPTION_SMU
+      #define OPTION_SMU  TRUE
+    #endif
+    #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  F12NbSmuInitFeature;
+      #define OPTION_F12NBSMUINITFEATURE_ENTRY            {AMD_FAMILY_LN, F12NbSmuInitFeature},
+    #else
+      #define OPTION_F12NBSMUINITFEATURE_ENTRY
+    #endif
+    #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbSmuInitFeature;
+      #define OPTION_F14NBSMUINITFEATURE_ENTRY            {AMD_FAMILY_ON, F14NbSmuInitFeature},
+    #else
+      #define OPTION_F14NBSMUINITFEATURE_ENTRY
+    #endif
+      #define OPTION_KRNBSMUINITFEATURE_ENTRY
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_MAP
+      #define OPTION_PCIE_CONFIG_MAP TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                 PcieConfigurationMap;
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationMap},
+    #else
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_EARLY_INIT
+      #define OPTION_PCIE_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtEarly;
+      #define OPTION_PCIEINITATEARLY_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
+    #else
+      #define  OPTION_PCIEINITATEARLY_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
+      OPTION_NBINITATEARLY_ENTRY
+      OPTION_F12NBSMUINITFEATURE_ENTRY
+      OPTION_F14NBSMUINITFEATURE_ENTRY
+      OPTION_PCIECONFIGURATIONMAP_ENTRY
+      OPTION_PCIEINITATEARLY_ENTRY
+      {0, NULL}
+    };
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_INIT
+      #define OPTION_PCIE_CONFIG_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieConfigurationInit;
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
+    #else
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLIER_INIT
+      #define OPTION_NB_EARLIER_INIT TRUE
+    #endif
+
+    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
+      OPTION_PCIECONFIGURATIONINIT_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_POST_INIT
+      #define OPTION_GFX_CONFIG_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxConfigPostInterface;
+      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY         {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
+    #else
+      #define  OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_POST_INIT
+      #define OPTION_GFX_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtPost;
+      #define OPTION_GFXINITATPOST_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
+    #else
+      #define  OPTION_GFXINITATPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_POST_INIT
+      #define OPTION_NB_POST_INIT TRUE
+    #endif
+    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtPost;
+      #define OPTION_NBINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
+    #else
+      #define OPTION_NBINITATPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_EALRY_INIT
+      #define OPTION_PCIE_POST_EALRY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtPostEarly;
+    #define OPTION_PCIEINITATPOSTEARLY_ENTRY              {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
+    #else
+      #define OPTION_PCIEINITATPOSTEARLY_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_INIT
+      #define OPTION_PCIE_POST_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtPost;
+      #define OPTION_PCIEINITATPOST_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
+    #else
+      #define OPTION_PCIEINITATPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+      OPTION_PCIEINITATPOSTEARLY_ENTRY
+      OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+      OPTION_GFXINITATPOST_ENTRY
+      OPTION_GFXPOSTINTERFACETN_ENTRY
+      {0, NULL}
+    };
+
+    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
+      OPTION_NBINITATPOST_ENTRY
+      OPTION_PCIEINITATPOST_ENTRY
+      OPTION_PCIEPOSTINTERFACETN_ENTRY
+      OPTION_PCIEPOSTINTERFACEKM_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_ENV == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_FUSE_TABLE_INIT
+      #define OPTION_FUSE_TABLE_INIT TRUE
+    #endif
+    #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbFuseTableFeature;
+      #define OPTION_NBFUSETABLEFEATURE_ENTRY             {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
+    #else
+      #define OPTION_NBFUSETABLEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_ENV_INIT
+      #define OPTION_NB_ENV_INIT TRUE
+    #endif
+    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtEnv;
+      #define OPTION_NBINITATENVT_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
+    #else
+      #define OPTION_NBINITATENVT_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_ENV_INIT
+      #define OPTION_GFX_CONFIG_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
+      #define OPTION_GFXCONFIGENVINTERFACE_ENTRY           {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
+    #else
+      #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_ENV_INIT
+      #define OPTION_GFX_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtEnvPost;
+      #define OPTION_GFXINITATENVPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
+    #else
+      #define OPTION_GFXINITATENVPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_POWER_GATE
+      #define OPTION_POWER_GATE TRUE
+    #endif
+    #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  F12NbPowerGateFeature;
+      #define OPTION_F12NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbPowerGateFeature},
+    #else
+      #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
+    #endif
+    #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbPowerGateFeature;
+      #define OPTION_F14NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbPowerGateFeature},
+    #else
+      #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_ENV_INIT
+      #define OPTION_PCIE_ENV_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtEnv;
+      #define OPTION_PCIEINITATENV_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
+    #else
+      #define OPTION_PCIEINITATENV_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+
+    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
+      OPTION_NBFUSETABLEFEATURE_ENTRY
+      OPTION_NBINITATENVT_ENTRY
+      OPTION_PCIEINITATENV_ENTRY
+      OPTION_GFXCONFIGENVINTERFACE_ENTRY
+      OPTION_GFXINITATENVPOST_ENTRY
+      OPTION_F12NBPOWERGATEFEATURE_ENTRY
+      OPTION_F14NBPOWERGATEFEATURE_ENTRY
+      OPTION_KRNBPOWERGATEFEATURE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_MID == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GNB_CABLESAFE
+      #define OPTION_GNB_CABLESAFE TRUE
+    #endif
+    #if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbCableSafeEntry;
+      #define OPTION_GNBCABLESAFEENTRY_ENTRY              {AMD_FAMILY_LN, GnbCableSafeEntry},
+    #else
+      #define OPTION_GNBCABLESAFEENTRY_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_LCLK_NCLK_RATIO
+      #define OPTION_NB_LCLK_NCLK_RATIO TRUE
+    #endif
+    #if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbLclkNclkRatioFeature;
+      #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY      {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
+    #else
+      #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_LCLK_DPM_INIT
+      #define OPTION_NB_LCLK_DPM_INIT TRUE
+    #endif
+    #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbLclkDpmFeature;
+      #define OPTION_NBLCLKDPMFEATURE_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
+    #else
+      #define OPTION_NBLCLKDPMFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POWER_GATE
+      #define OPTION_PCIE_POWER_GATE TRUE
+    #endif
+    #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  PciePowerGateFeature;
+      #define OPTION_PCIEPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_LN, PciePowerGateFeature},
+    #else
+      #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_MID_INIT
+      #define OPTION_GFX_MID_INIT TRUE
+    #endif
+    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtMidPost;
+      #define OPTION_GFXINITATMIDPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
+    #else
+      #define OPTION_GFXINITATMIDPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
+      #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
+    #endif
+    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                 GfxIntegratedInfoTableEntry;
+      #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY        {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
+    #else
+      #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIe_MID_INIT
+      #define OPTION_PCIe_MID_INIT TRUE
+    #endif
+    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtMid;
+      #define OPTION_PCIEINITATMID_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
+    #else
+      #define OPTION_PCIEINITATMID_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_MID_INIT
+      #define OPTION_NB_MID_INIT TRUE
+    #endif
+    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtLatePost;
+      #define OPTION_NBINITATLATEPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
+    #else
+      #define OPTION_NBINITATLATEPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
+      OPTION_GFXINITATMIDPOST_ENTRY
+      OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+      OPTION_GNBCABLESAFEENTRY_ENTRY
+      OPTION_PCIEINITATMID_ENTRY
+      OPTION_NBINITATLATEPOST_ENTRY
+      OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+      OPTION_NBLCLKDPMFEATURE_ENTRY
+      OPTION_PCIEPOWERGATEFEATURE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_ALIB
+      #define OPTION_ALIB FALSE
+    #endif
+    #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieAlibFeature;
+      #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
+    #else
+      #define OPTION_PCIEALIBFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_IOMMU_ACPI_IVRS
+      #define OPTION_IOMMU_ACPI_IVRS TRUE
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
+      OPTION_PCIEALIBFEATURE_ENTRY
+      OPTIONIOMMUACPIIVRSLATE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if  (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+    S3_DISPATCH_FUNCTION  NbSmuServiceRequestS3Script;
+    S3_DISPATCH_FUNCTION  PcieLateRestoreS3Script;
+    S3_DISPATCH_FUNCTION  NbSmuIndirectWriteS3Script;
+    #define GNB_S3_DISPATCH_FUNCTION_TABLE \
+    {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
+    {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
+    {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
+  #endif
+
+
+#endif
+#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
new file mode 100644
index 0000000..056777d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
@@ -0,0 +1,319 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Ht
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 51975 $   @e \$Date: 2011-04-29 01:33:06 -0600 (Fri, 29 Apr 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HT_INSTALL_H_
+#define _OPTION_HT_INSTALL_H_
+
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htTopologies.h"
+/*
+ * Advanced Option only, hardware socket naming is the preferred method.
+ */
+#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
+#else
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
+#endif
+
+/*
+ * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
+ */
+#ifndef OPTION_IS_RECOVERY_HT
+  #define OPTION_IS_RECOVERY_HT TRUE
+#endif
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition.
+ */
+
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+/*
+ * Based on user level options, set Ht internal options.
+ * For now, Family 10h support will assume single module.  For multi module,
+ * this will have to be changed to not set non-coherent only.
+ */
+#define OPTION_HT_NON_COHERENT_ONLY FALSE
+
+#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+/* Families with only PCIe do not need a non-coherent only option. */
+#else
+  // Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable.
+  #if OPTION_G34_SOCKET_SUPPORT == FALSE
+  // Hydra has coherent support, other Family 10h should follow MultiSocket support.
+    #if OPTION_MULTISOCKET == FALSE
+      #undef OPTION_HT_NON_COHERENT_ONLY
+      #define OPTION_HT_NON_COHERENT_ONLY TRUE
+    #endif
+  #endif
+#endif
+
+/*
+ * Macros will generate the correct item reference based on options
+ */
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  // Select the interface and features
+  #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
+    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
+  #else
+      // Family 10h and 15h Models 00h-0Fh
+      #if OPTION_HT_NON_COHERENT_ONLY == FALSE
+        #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesDefault
+        #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceDefault
+      #else
+        #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+        #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNonCoherentOnly
+        #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceNonCoherentOnly
+      #endif
+    #endif
+  // Select Northbridge components
+  #if OPTION_FAMILY10H == TRUE
+    #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly,
+    #else
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault,
+    #endif
+  #else
+    #define INTERNAL_HT_OPTION_FAM10_NB
+  #endif
+
+  #if OPTION_FAMILY12H == TRUE
+    #define INTERNAL_HT_OPTION_FAM12_NB     &HtFam12Nb,
+  #else
+    #define INTERNAL_HT_OPTION_FAM12_NB
+  #endif
+
+  #if OPTION_FAMILY14H == TRUE
+      #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
+  #else
+    #define INTERNAL_HT_OPTION_FAM14_NB
+  #endif
+
+  #if OPTION_FAMILY15H == TRUE
+    #if OPTION_FAMILY15H_OR == TRUE
+      #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+        #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbNonCoherentOnly,
+      #else
+        #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbDefault,
+      #endif
+    #else
+      #define INTERNAL_HT_OPTION_FAM15_NB
+    #endif
+      #define INTERNAL_HT_OPTION_FAM15TN_NB
+      #define INTERNAL_HT_OPTION_FAM15KM_NB
+  #else
+    #define INTERNAL_HT_OPTION_FAM15_NB
+    #define INTERNAL_HT_OPTION_FAM15TN_NB
+    #define INTERNAL_HT_OPTION_FAM15KM_NB
+  #endif
+
+  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
+  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
+    #undef INTERNAL_ONLY_NB_LIST_ITEM
+    #define INTERNAL_ONLY_NB_LIST_ITEM
+  #endif
+
+  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
+   * is ok to have a comma because the final item (NULL) is added below.
+   */
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
+                                             INTERNAL_ONLY_NB_LIST_ITEM \
+                                             INTERNAL_HT_OPTION_FAM10_NB \
+                                             INTERNAL_HT_OPTION_FAM15_NB \
+                                             INTERNAL_HT_OPTION_FAM12_NB \
+                                             INTERNAL_HT_OPTION_FAM14_NB
+#else
+  // Not Init Early
+  #define INTERNAL_HT_OPTION_FEATURES     NULL
+  #define INTERNAL_HT_OPTION_INTERFACE    NULL
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
+  #define HT_OPTIONS_PLATFORM             NULL
+  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+#endif
+
+#ifdef AGESA_ENTRY_INIT_EARLY
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+
+    extern HT_FEATURES HtFeaturesDefault;
+    extern HT_FEATURES HtFeaturesNonCoherentOnly;
+    extern HT_FEATURES HtFeaturesCoherentOnly;
+    extern HT_FEATURES HtFeaturesNone;
+    extern HT_INTERFACE HtInterfaceDefault;
+    extern HT_INTERFACE HtInterfaceNonCoherentOnly;
+    extern HT_INTERFACE HtInterfaceCoherentOnly;
+    extern HT_INTERFACE HtInterfaceMapsOnly;
+    extern HT_INTERFACE HtInterfaceNone;
+    extern NORTHBRIDGE HtFam10NbDefault;
+    extern NORTHBRIDGE HtFam10RevDNbDefault;
+    extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam10RevENbDefault;
+    extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam12Nb;
+    extern NORTHBRIDGE HtFam14Nb;
+    extern NORTHBRIDGE HtFam10NbNone;
+    extern NORTHBRIDGE HtFam15NbDefault;
+    extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
+
+    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
+      INTERNAL_HT_OPTION_SUPPORTED_NBS
+      NULL
+    };
+
+    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
+    {
+      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
+      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
+      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
+      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
+      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
+      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
+      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
+      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
+    };
+    #ifndef HT_OPTIONS_PLATFORM
+      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
+    #endif
+
+    /**
+     * A list of all the supported topologies.
+     *
+     */
+    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
+      {
+        amdHtTopologySingleNode,
+        amdHtTopologyDualNode,
+        amdHtTopologyThreeLine,
+        amdHtTopologyTriangle,
+        amdHtTopologyFourLine,
+        amdHtTopologyFourStar,
+        amdHtTopologyFourDegenerate,
+        amdHtTopologyFourSquare,
+        amdHtTopologyFourKite,
+        amdHtTopologyFourFully,
+        amdHtTopologyFiveFully,
+        amdHtTopologyFiveTwistedLadder,
+        amdHtTopologySixFully,
+        amdHtTopologySixDoubloonLower,
+        amdHtTopologySixDoubloonUpper,
+        amdHtTopologySixTwistedLadder,
+        amdHtTopologySevenFully,
+        amdHtTopologySevenTwistedLadder,
+        amdHtTopologyEightFully,
+        amdHtTopologyEightDoubloon,
+        amdHtTopologyEightTwistedLadder,
+        amdHtTopologyEightStraightLadder,
+        amdHtTopologySixTwinTriangles,
+        amdHtTopologyEightTwinFullyFourWays,
+        NULL
+      };
+      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
+    #endif
+
+    /**
+     * Declare the instance of the Ht option configuration structure
+     */
+    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
+      OPTION_IS_RECOVERY_HT,
+      CFG_SET_HTCRC_SYNC_FLOOD,
+      CFG_USE_UNIT_ID_CLUMPING,
+      HT_OPTIONS_PLATFORM,
+      INTERNAL_HT_OPTION_INTERFACE,
+      INTERNAL_HT_OPTION_FEATURES,
+      &HtInstalledFamilyNorthbridgeList,
+      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+    };
+
+  #endif
+#endif
+
+#ifndef OPTION_HT_INIIT_RESET_ENTRY
+
+  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+  #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
+
+  #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY NULL
+    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
+  #endif
+
+  #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
+  #endif
+
+#endif
+
+#ifdef AGESA_ENTRY_INIT_RESET
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+
+    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      0                                            // Unused by options
+    };
+
+    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
+      OPTION_HT_INIIT_RESET_ENTRY,
+      OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    };
+  #endif
+
+#endif
+
+#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h
new file mode 100644
index 0000000..4580809
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: HW C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HW_C1E_INSTALL_H_
+#define _OPTION_HW_C1E_INSTALL_H_
+
+#include "cpuHwC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_HW_C1E_FEAT
+#define F10_HW_C1E_SUPPORT
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
+        #undef OPTION_HW_C1E_FEAT
+        #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
+        extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
+        #undef F10_HW_C1E_SUPPORT
+        #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
+      #endif
+    #endif
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
+  {
+    F10_HW_C1E_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
+  {
+    (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &HwC1eFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
new file mode 100644
index 0000000..16cd68c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
@@ -0,0 +1,588 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option Install File
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 55277 $   @e \$Date: 2011-06-19 23:03:21 -0600 (Sun, 19 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_INSTALL_H_
+#define _OPTION_IDS_INSTALL_H_
+#include "Ids.h"
+#include "IdsHt.h"
+#include "IdsLib.h"
+#ifdef __IDS_EXTENDED__
+  #include OPTION_IDS_EXT_INSTALL_FILE
+#endif
+
+#define IDS_LATE_RUN_AP_TASK
+
+#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    // Check for all families which include HT Features.
+    #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)) && (AGESA_ENTRY_INIT_POST == TRUE)
+      #undef M_HTIDS_PORT_OVERRIDE_HOOK
+      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
+    #endif
+  #endif
+#endif // OPTION_IDS_LEVEL
+CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
+
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+    #undef IDS_LATE_RUN_AP_TASK
+    #define IDS_LATE_RUN_AP_TASK
+  #endif
+#endif // OPTION_IDS_LEVEL
+
+#if (IDSOPT_TRACING_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+    #include <mu.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+      { (UINT32) (UINT64) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+      { (UINT32) (UINT64) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
+    };
+  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+    #include <mru.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+      { (UINT32) (UINT64) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
+      { (UINT32) (UINT64) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
+    };
+  #else
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+    };
+  #endif
+#else
+  CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+    { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+    { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
+    { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+  };
+#endif
+
+
+#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
+#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
+       ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+        (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+        (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+    #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
+      #define OPTION_IDS_NV_TO_CMOS_COMMON
+
+      #ifdef OPTION_FAMILY10H
+        #if OPTION_FAMILY10H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F10
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY12H
+        #if OPTION_FAMILY12H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F12
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY14H
+        #if OPTION_FAMILY14H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F14
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY15H_OR
+        #if OPTION_FAMILY15H_OR == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F15_OR
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY15H_TN
+        #if OPTION_FAMILY15H_TN == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F15_TN\
+            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
+        #endif
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F10
+        #define OPTION_IDS_NV_TO_CMOS_F10
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F12
+        #define OPTION_IDS_NV_TO_CMOS_F12
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F14
+        #define OPTION_IDS_NV_TO_CMOS_F14
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F15_OR
+        #define OPTION_IDS_NV_TO_CMOS_F15_OR
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
+        #define OPTION_IDS_NV_TO_CMOS_F15_TN
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
+        #define OPTION_IDS_NV_TO_CMOS_EXTEND
+      #endif
+
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_COMMON
+        OPTION_IDS_NV_TO_CMOS_F10
+        OPTION_IDS_NV_TO_CMOS_F12
+        OPTION_IDS_NV_TO_CMOS_F14
+        OPTION_IDS_NV_TO_CMOS_F15_OR
+        OPTION_IDS_NV_TO_CMOS_F15_TN
+        OPTION_IDS_NV_TO_CMOS_EXTEND
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #else
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #endif
+  #else
+    IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+      OPTION_IDS_NV_TO_CMOS_END
+    };
+  #endif
+#else
+  IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+    OPTION_IDS_NV_TO_CMOS_END
+  };
+#endif
+
+///Ids Feat Options
+#if ((IDSOPT_IDS_ENABLED == TRUE) && \
+     ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+      (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+      (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    #ifndef OPTION_IDS_EXTEND_FEATS
+      #define OPTION_IDS_EXTEND_FEATS
+    #endif
+
+    #define OPTION_IDS_FEAT_ECCCTRL\
+                OPTION_IDS_FEAT_ECCCTRL_F10 \
+                OPTION_IDS_FEAT_ECCCTRL_F12 \
+                OPTION_IDS_FEAT_ECCCTRL_F15_OR
+
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+
+    #define OPTION_IDS_FEAT_CPB_CTRL\
+                OPTION_IDS_FEAT_CPB_CTRL_F12
+
+    #define OPTION_IDS_FEAT_HTC_CTRL\
+                OPTION_IDS_FEAT_HTC_CTRL_F15_OR \
+                OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING\
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+
+    #define OPTION_IDS_FEAT_HT_ASSIST\
+                OPTION_IDS_FEAT_HT_ASSIST_F10HY \
+                OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
+                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
+                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+
+/*----------------------------------------------------------------------------
+ *                        Family 10 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
+    #define OPTION_IDS_FEAT_ECCCTRL_F10
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+//Ecc symbol size
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
+        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
+        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
+
+//ECC scrub control
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F10
+        #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
+      #endif
+    #endif
+
+    //Misc Features
+    #define OPTION_IDS_FEAT_HT_ASSIST_F10HY
+    #ifdef OPTION_FAMILY10H_HY
+      #if OPTION_FAMILY10H_HY == TRUE
+        #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
+
+        #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
+                    &IdsFeatHtAssistBlockPlatformCfgF10Hy,
+      #endif
+    #endif
+/*----------------------------------------------------------------------------
+ *                        Family 12 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
+    #define OPTION_IDS_FEAT_ECCCTRL_F12
+    #define OPTION_IDS_FEAT_CPB_CTRL_F12
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
+
+        //ECC scrub control
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F12
+        #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
+
+        #undef OPTION_IDS_FEAT_CPB_CTRL_F12
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
+        #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
+                    &IdsFeatMemoryChIntlvPostBeforeBlockF12, \
+                    &IdsFeatMemoryMappingChIntlvBlockF12,
+
+      #endif
+    #endif
+
+/*----------------------------------------------------------------------------
+ *                        Family 14 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
+      #endif
+    #endif
+
+/*----------------------------------------------------------------------------
+ *                        Family 15 OR feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
+    #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+    #define OPTION_IDS_FEAT_ECCCTRL_F15_OR
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+    #ifdef OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
+        #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
+                    &IdsFeatHtcControlBlockF15Or,\
+                    &IdsFeatHtcControlLateBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
+        &IdsFeatMemoryMappingPostBeforeBlockF15Or,\
+        &IdsFeatMemoryMappingChIntlvBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
+        #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+        #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
+        &IdsFeatHtAssistBlockPlatformCfgF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
+        #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
+        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
+
+      #endif
+    #endif
+/*----------------------------------------------------------------------------
+ *                        Family 15 TN feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+    #ifdef OPTION_FAMILY15H_TN
+      #if OPTION_FAMILY15H_TN == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+        #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
+                    &IdsFeatHtcControlBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
+        &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
+        &IdsFeatMemoryMappingChIntlvBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
+      #endif
+    #endif
+
+    #define OPTION_IDS_FEAT_NV_TO_CMOS
+    #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+      #undef OPTION_IDS_FEAT_NV_TO_CMOS
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
+      #define OPTION_IDS_FEAT_NV_TO_CMOS\
+        &IdsFeatNvToCmosSaveBlock, \
+        &IdsFeatNvToCmosRestoreBlock,
+
+    #endif
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
+    {
+      IDS_FEAT_UCODE_UPDATE,
+      IDS_ALL_CORES,
+      IDS_UCODE,
+      IDS_FAMILY_ALL,
+      IdsSubUCode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
+    {
+      IDS_FEAT_POWER_POLICY,
+      IDS_ALL_CORES,
+      IDS_PLATFORMCFG_OVERRIDE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerPolicyOverride
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
+    {
+      IDS_FEAT_TARGET_PSTATE,
+      IDS_BSP_ONLY,
+      IDS_INIT_LATE_AFTER,
+      IDS_FAMILY_ALL,
+      IdsSubTargetPstate
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
+    {
+      IDS_FEAT_POSTPSTATE,
+      IDS_ALL_CORES,
+      IDS_CPU_Early_Override,
+      IDS_FAMILY_ALL,
+      IdsSubPostPState
+    };
+
+    //Dram controller Features
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
+    {
+      IDS_FEAT_DCT_ALLMEMCLK,
+      IDS_BSP_ONLY,
+      IDS_ALL_MEMORY_CLOCK,
+      IDS_FAMILY_ALL,
+      IdsSubAllMemClkEn
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
+    {
+      IDS_FEAT_DCT_GANGMODE,
+      IDS_BSP_ONLY,
+      IDS_GANGING_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubGangingMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
+    {
+      IDS_FEAT_DCT_BURSTLENGTH,
+      IDS_BSP_ONLY,
+      IDS_BURST_LENGTH32,
+      AMD_FAMILY_10,
+      IdsSubBurstLength32
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_INIT_POST_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownCtrl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
+    {
+      IDS_FEAT_DCT_DLLSHUTDOWN,
+      IDS_BSP_ONLY,
+      IDS_DLL_SHUT_DOWN,
+      IDS_FAMILY_ALL,
+      IdsSubDllShutDownSR
+    };
+
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_POWERDOWN_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
+    {
+      IDS_FEAT_HDTOUT,
+      IDS_BSP_ONLY,
+      IDS_INIT_EARLY_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubHdtOut
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
+    {
+      IDS_FEAT_HT_SETTING,
+      IDS_BSP_ONLY,
+      IDS_HT_CONTROL,
+      IDS_FAMILY_ALL,
+      IdsSubHtLinkControl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+    {
+      &IdsFeatUcodeBlock,
+      &IdsFeatPowerPolicyBlock,
+
+      &IdsFeatTargetPstateBlock,
+
+      &IdsFeatPostPstateBlock,
+
+      OPTION_IDS_FEAT_NV_TO_CMOS
+
+      OPTION_IDS_FEAT_ECCSYMBOLSIZE
+
+      OPTION_IDS_FEAT_ECCCTRL
+
+      &IdsFeatDctAllMemClkBlock,
+
+      &IdsFeatDctGangModeBlock,
+
+      &IdsFeatDctBurstLengthBlock,
+
+      &IdsFeatDctPowerDownCtrlBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      OPTION_IDS_FEAT_HT_ASSIST
+
+      &IdsFeatHdtOutBlock,
+
+      &IdsFeatHtSettingBlock,
+
+      OPTION_IDS_FEAT_GNB_PLATFORMCFG
+
+      OPTION_IDS_FEAT_CPB_CTRL
+
+      OPTION_IDS_FEAT_HTC_CTRL
+
+      OPTION_IDS_FEAT_MEMORY_MAPPING
+
+      OPTION_IDS_EXTEND_FEATS
+
+      NULL
+    };
+  #else
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+    {
+      NULL
+    };
+  #endif//IDSOPT_CONTROL_ENABLED
+
+  #define OPTION_IDS_FAM_REGACC\
+            OPTION_IDS_FAM_REGACC_F15TN
+
+  #define OPTION_IDS_FAM_REGACC_F15TN
+  #ifdef OPTION_FAMILY15H_TN
+    #if OPTION_FAMILY15H_TN == TRUE
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
+      #undef OPTION_IDS_FAM_REGACC_F15TN
+      #define OPTION_IDS_FAM_REGACC_F15TN \
+                &IdsFeatRegGmmxF15Tn,
+    #endif
+  #endif
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    OPTION_IDS_FAM_REGACC
+    NULL
+  };
+
+#else
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+  {
+    NULL
+  };
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    NULL
+  };
+#endif// IDSOPT_IDS_ENABLED
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
new file mode 100644
index 0000000..f83ad70
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
@@ -0,0 +1,133 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: IO C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_IO_CSTATE_INSTALL_H_
+#define _OPTION_IO_CSTATE_INSTALL_H_
+
+#include "cpuIoCstate.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define OPTION_IO_CSTATE_FEAT
+#define F10_IO_CSTATE_SUPPORT
+#define F12_IO_CSTATE_SUPPORT
+#define F14_IO_CSTATE_SUPPORT
+#define F15_OR_IO_CSTATE_SUPPORT
+
+#if OPTION_IO_CSTATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_PH == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
+          #undef F10_IO_CSTATE_SUPPORT
+          #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
+          #undef F12_IO_CSTATE_SUPPORT
+          #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if (OPTION_FAMILY14H_ON == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
+          #undef F14_IO_CSTATE_SUPPORT
+          #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
+          #undef F15_OR_IO_CSTATE_SUPPORT
+          #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
+{
+  F10_IO_CSTATE_SUPPORT
+  F12_IO_CSTATE_SUPPORT
+  F14_IO_CSTATE_SUPPORT
+  F15_OR_IO_CSTATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
+{
+  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &IoCstateFamilyServiceArray[0]
+};
+
+#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
new file mode 100644
index 0000000..5804f1d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: L3 Dependent Features
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_L3_FEATURES_INSTALL_H_
+#define _OPTION_L3_FEATURES_INSTALL_H_
+
+#include "cpuL3Features.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_L3_FEAT
+#define F10_L3_FEAT_SUPPORT
+#define F15_OR_L3_FEAT_SUPPORT
+#define F15_KM_L3_FEAT_SUPPORT
+#define L3_FEAT_AP_DISABLE_CACHE
+#define L3_FEAT_AP_ENABLE_CACHE
+
+#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
+
+    #ifdef  OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          #undef OPTION_L3_FEAT
+          #define OPTION_L3_FEAT &CpuL3Features,
+          extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
+          #undef F10_L3_FEAT_SUPPORT
+          #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
+        #endif
+      #endif
+    #endif
+
+    #ifdef  OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        #undef OPTION_L3_FEAT
+        #define OPTION_L3_FEAT &CpuL3Features,
+        extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
+        #undef F15_OR_L3_FEAT_SUPPORT
+        #define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features},
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H_KM
+      #if OPTION_FAMILY15H_KM == TRUE
+        #undef OPTION_L3_FEAT
+        #define OPTION_L3_FEAT &CpuL3Features,
+        extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15KmL3Features;
+        #undef F15_KM_L3_FEAT_SUPPORT
+        #define F15_KM_L3_FEAT_SUPPORT {AMD_FAMILY_15_KM, &F15KmL3Features},
+      #endif
+    #endif
+
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #undef L3_FEAT_AP_DISABLE_CACHE
+    #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
+    #undef L3_FEAT_AP_ENABLE_CACHE
+    #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
+{
+  F10_L3_FEAT_SUPPORT
+  F15_OR_L3_FEAT_SUPPORT
+  F15_KM_L3_FEAT_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
+{
+  (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &L3FeatureFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_L3_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h
new file mode 100644
index 0000000..9950d94
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 53056 $   @e \$Date: 2011-05-13 23:48:24 -0600 (Fri, 13 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+
+#include "cpuLowPwrPstate.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
+#define F15_OR_LOW_PWR_PSTATE_SUPPORT
+
+#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
+            extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
+            #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
+            #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
+            extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
+            #undef F15_OR_LOW_PWR_PSTATE_SUPPORT
+            #define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
+{
+  F15_OR_LOW_PWR_PSTATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
+{
+  (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &LowPwrPstateFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h
new file mode 100644
index 0000000..2635dbc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h
@@ -0,0 +1,358 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 55039 $   @e \$Date: 2011-06-15 23:31:36 -0600 (Wed, 15 Jun 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_H_
+#define _OPTION_MEMORY_H_
+
+/* Memory Includes */
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mp.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_FF_TYPES      6   ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+* STANDARD MEMORY FEATURE FUNCTION POINTER
+*/
+
+typedef BOOLEAN OPTION_MEM_FEATURE_NB (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+typedef BOOLEAN MEM_TECH_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+typedef UINT8 MEM_TABLE_FEAT (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+
+#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION  0x01
+
+/**
+ *  MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Northbridge devices supported by
+ *  AGESA.
+ */
+typedef struct _MEM_FEAT_BLOCK_NB {
+  UINT16              OptMemFeatVersion; ///< Version of memory feature block.
+  OPTION_MEM_FEATURE_NB  *OnlineSpare; ///< Online spare support.
+  OPTION_MEM_FEATURE_NB  *InterleaveBanks; ///< Bank (Chip select) interleaving support.
+  OPTION_MEM_FEATURE_NB  *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
+  OPTION_MEM_FEATURE_NB  *CheckInterleaveNodes; ///< Check for Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveNodes; ///< Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveChannels; ///< Channel interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveRegion;  ///< Interleave Region support.
+  OPTION_MEM_FEATURE_NB  *CheckEcc; ///< Check for ECC support.
+  OPTION_MEM_FEATURE_NB  *InitEcc; ///< ECC support.
+  OPTION_MEM_FEATURE_NB  *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
+  OPTION_MEM_FEATURE_NB  *LvDdr3; ///< Low voltage DDR3 dimm support
+  OPTION_MEM_FEATURE_NB  *OnDimmThermal; ///< On-Dimm thermal management
+  MEM_TECH_FEAT  *DramInit; ///< Choose the type of Dram init (hardware based or software based).
+  OPTION_MEM_FEATURE_NB  *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_NB  *InitEarlySampleSupport; ///< Initialize early sample support.
+  OPTION_MEM_FEATURE_NB  *InitCPG; ///< Continuous pattern generation.
+  OPTION_MEM_FEATURE_NB  *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
+} MEM_FEAT_BLOCK_NB;
+
+typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+typedef BOOLEAN MEM_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
+  IN       UINT8 NodeID
+  );
+
+typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+typedef VOID MEM_INITIALIZER (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+ );
+
+typedef AGESA_STATUS MEM_PLATFORM_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN UINT8 SocketID,
+  IN CH_DEF_STRUCT *CurrentChannel
+  );
+
+typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_TECH_TRAINING_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+typedef AGESA_STATUS MEM_FLOW_CFG (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemData
+  );
+
+#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION  0x01
+
+/**
+ * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_BLOCK_MAIN {
+  UINT16              OptMemFeatVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
+  OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
+  OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
+  OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
+  OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
+  OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
+  OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
+  OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
+  OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
+  OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
+} MEM_FEAT_BLOCK_MAIN;
+
+#define MEM_NB_SUPPORT_STRUCT_VERSION  0x01
+#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION  0x01
+#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION  0x01
+#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
+/**
+ *  MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_FEAT_BLOCK {
+  UINT16  OptMemTechFeatVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
+  MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
+  MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
+  MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
+  MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
+  MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
+  MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
+  MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
+  MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
+  MEM_TECH_FEAT *RdDqs__Training; ///< Read DQS Training
+} MEM_TECH_FEAT_BLOCK;
+
+/**
+ *  MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various LRDIMM features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_LRDIMM {
+  UINT16  OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
+} MEM_TECH_LRDIMM;
+/**
+ * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
+ * options together in a list to provide a single access point for all code to use
+ * and to ensure that everything corresponding to the same NB type is grouped together.
+ *
+ * The Technology Block pointers are not included in this structure because DRAM technology
+ * needs to be decoupled from the northbridge type.
+ *
+ */
+typedef struct _MEM_NB_SUPPORT {
+  UINT16              MemNBSupportVersion; ///< Version of northbridge support.
+  MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
+  MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
+  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
+  MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
+  MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
+} MEM_NB_SUPPORT;
+
+/*
+ *  MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
+ *  memory non-training feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology devices supported by
+ *  AGESA.
+ */
+
+/**
+ * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_TRAIN_SEQ {
+  UINT16              OptMemTrainingSequenceListVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
+  OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
+  MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
+} MEM_FEAT_TRAIN_SEQ;
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
+ * entries which are used by PSC engine
+ */
+typedef struct _MEM_PSC_TABLE_BLOCK {
+  PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
+  PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
+  PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
+  PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
+  PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
+  PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
+  PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
+  PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
+  PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
+  PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
+  PSC_TBL_ENTRY **TblEntryOfS__; ///< Table entry of training configs
+  PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
+  PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
+} MEM_PSC_TABLE_BLOCK;
+
+typedef BOOLEAN MEM_PSC_FLOW (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
+ * specific configuration.
+ */
+typedef struct _MEM_PSC_FLOW_BLOCK {
+  MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
+  MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
+  MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
+  MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
+  MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
+  MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
+  MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
+  MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
+  MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
+  MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
+  MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
+  MEM_PSC_FLOW *S__; ///< Sub-engine which performs training configuration  checking
+  MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
+} MEM_PSC_FLOW_BLOCK;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+/* Feature Default Return */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN MemMDefRet (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+/* Table Feature Default Return */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+/* S3 Feature Default Return */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+   );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
new file mode 100644
index 0000000..24c1ae8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
@@ -0,0 +1,3778 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56315 $   @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_INSTALL_H_
+#define _OPTION_MEMORY_INSTALL_H_
+
+/* Memory Includes */
+#include "OptionMemory.h"
+
+/*-------------------------------------------------------------------------------
+ *  This option file is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+/*----------------------------------------------------------------------------------
+ * FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN MemMDefRet (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return TRUE;
+}
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return FALSE;
+}
+/*----------------------------------------------------------------------------------
+ * TABLE FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  )
+{
+  return 0;
+}
+/*----------------------------------------------------------------------------------
+ * FEATURE S3 BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return TRUE;
+}
+
+#if (OPTION_MEMCTLR_DR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
+  #else
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      #if (OPTION_MEMCTLR_Ni == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_DA == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_PH == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_RB == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
+      #endif
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
+    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
+    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
+  #else
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
+    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
+    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_OR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
+  #else
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_HY == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
+  #else
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_C32 == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
+  #else
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+/*----------------------------------------------------------------------------------
+ * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
+ *
+ *----------------------------------------------------------------------------------
+*/
+#define MEM_NB_SUPPORT_DR
+#define MEM_NB_SUPPORT_RB
+#define MEM_NB_SUPPORT_DA
+#define MEM_NB_SUPPORT_Ni
+#define MEM_NB_SUPPORT_PH
+#define MEM_NB_SUPPORT_HY
+#define MEM_NB_SUPPORT_OR
+#define MEM_NB_SUPPORT_C32
+#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
+
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  /*----------------------------------------------------------------------------------
+   * FLOW CONTROL FUNCTION
+   *
+   *  This section selects the function that controls the memory initialization sequence
+   *  based upon the number of processor families that the BIOS will support.
+   */
+  extern MEM_FLOW_CFG MemMFlowDef;
+  extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+
+
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDr;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDA;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    extern MEM_FLOW_CFG MemMFlowHy;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    extern MEM_FLOW_CFG MemMFlowOr;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    extern MEM_FLOW_CFG MemMFlowC32;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_Ni == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDA;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    extern MEM_FLOW_CFG MemMFlowRb;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    extern MEM_FLOW_CFG MemMFlowPh;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
+  #endif
+
+  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+    MEM_MAIN_FLOW_CONTROL_PTR_Dr
+    MEM_MAIN_FLOW_CONTROL_PTR_DA
+    MEM_MAIN_FLOW_CONTROL_PTR_RB
+    MEM_MAIN_FLOW_CONTROL_PTR_PH
+    MEM_MAIN_FLOW_CONTROL_PTR_Hy
+    MEM_MAIN_FLOW_CONTROL_PTR_OR
+    MEM_MAIN_FLOW_CONTROL_PTR_C32
+    MEM_MAIN_FLOW_CONTROL_PTR_Ni
+    NULL
+  };
+
+  #if (OPTION_ONLINE_SPARE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
+    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
+    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
+  #else
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
+    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
+  #endif
+
+  #if (OPTION_MEM_RESTORE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
+    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
+  #else
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
+  #endif
+
+  #if (OPTION_BANK_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
+    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
+  #else
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
+  #endif
+
+  #if (OPTION_NODE_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
+    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
+  #else
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
+  #endif
+
+  #if (OPTION_DCT_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
+  #else
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
+  #endif
+
+  #if (OPTION_ECC == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
+    #define MEM_MAIN_FEATURE_ECC  MemMEcc
+    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
+    extern OPTION_MEM_FEATURE_NB MemFInitECC;
+    #define MEM_FEATURE_CK_ECC   MemFCheckECC
+    #define MEM_FEATURE_ECC   MemFInitECC
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #else
+    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
+    #define MEM_FEATURE_CK_ECC   MemFDefRet
+    #define MEM_FEATURE_ECC   MemFDefRet
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #endif
+
+    #define MEM_FEATURE_EMP   MemFDefRet
+
+  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
+  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
+
+  #if (OPTION_DMI == TRUE)
+    #if (OPTION_DDR3 == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
+    #else
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
+    #endif
+  #else
+    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
+  #endif
+
+  #if (OPTION_DDR3 == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
+    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
+    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
+    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
+  #else
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
+    #define MEM_FEATURE_LVDDR3 MemFDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
+  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
+
+  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
+  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
+
+  #if (OPTION_PARALLEL_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
+  #else
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+  #endif
+
+  #if (OPTION_DIMM_EXCLUDE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
+    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
+  #else
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
+  #endif
+
+  /*----------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
+   *
+   *----------------------------------------------------------------------------------
+  */
+  #if OPTION_DDR2 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
+    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR2
+  #endif
+  #if OPTION_DDR3 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
+    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * FEATURE BLOCKS
+   *
+   *  This section instantiates a feature block structure for each memory controller installed
+   *  by the platform solution install file.
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
+  #endif
+  extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEERHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MemFDefRet,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_DR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
+    extern MEM_INITIALIZER MemNInitDefaultsDR;
+
+
+    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
+  #endif // OPTION_MEMCTRL_DR
+
+  /*---------------------------------------------------------------------------------------------------
+   * DASHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    #if (OPTION_MEMCTLR_Ni == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_Ni
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
+      extern MEM_INITIALIZER MemNInitDefaultsNi;
+
+      #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
+    #endif
+
+    #if (OPTION_MEMCTLR_PH == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_PH
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
+      extern MEM_INITIALIZER MemNInitDefaultsPh;
+
+      #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
+    #endif
+
+    #if (OPTION_MEMCTLR_RB == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_RB
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
+      extern MEM_INITIALIZER MemNInitDefaultsRb;
+
+      #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
+    #endif
+
+    #if (OPTION_MEMCTLR_DA == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_DA
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
+      extern MEM_INITIALIZER MemNInitDefaultsDA;
+
+      #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+    #endif
+  #endif // OPTION_MEMCTRL_DA
+
+  /*---------------------------------------------------------------------------------------------------
+   * HYDRA FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_HY
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
+    extern MEM_INITIALIZER MemNInitDefaultsHY;
+    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
+  #endif // OPTION_MEMCTRL_HY
+  /*---------------------------------------------------------------------------------------------------
+   * OROCHI FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_MAIN_FEATURE_LVDDR3
+      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
+      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT)
+      #undef MEM_FEATURE_REGION_INTERLEAVE
+      #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet
+    #endif
+
+    #if (OPTION_EARLY_SAMPLES == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
+    #else
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
+    #else
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MEM_FEATURE_REGION_INTERLEAVE,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_EARLY_SAMPLE_SUPPORT,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_OR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
+    extern MEM_INITIALIZER MemNInitDefaultsOR;
+    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
+  #endif // OPTION_MEMCTRL_OR
+
+  /*---------------------------------------------------------------------------------------------------
+   * C32 FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #if (OPTION_MEMCTLR_OR == TRUE)
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #else
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #endif
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_C32
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
+    extern MEM_INITIALIZER MemNInitDefaultsC32;
+    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
+  #endif // OPTION_MEMCTRL_C32
+
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
+    MEM_MAIN_FEATURE_TRAINING,
+    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
+    MEM_MAIN_FEATURE_ONLINE_SPARE,
+    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
+    MEM_MAIN_FEATURE_ECC,
+    MEM_MAIN_FEATURE_MEM_CLEAR,
+    MEM_MAIN_FEATURE_MEM_DMI,
+    MEM_MAIN_FEATURE_LVDDR3,
+    MEM_MAIN_FEATURE_UMAALLOC,
+    MEM_MAIN_FEATURE_MEM_SAVE,
+    MEM_MAIN_FEATURE_MEM_RESTORE
+  };
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * Technology Training SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
+  #if OPTION_MEMCTLR_DR
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
+    #endif
+    #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+    #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+    #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+    #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+    #endif
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
+    #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+    #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+    #endif
+    #endif
+    #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+      #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+      #endif
+    #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+    #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+    #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+    };
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+
+  #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #if (OPTION_MEMCTLR_DA)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_PH)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_RB)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+
+      #if (OPTION_MEMCTLR_Ni)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #if (OPTION_MEMCTLR_DA)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_PH)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_RB)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_Ni)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #if OPTION_MEMCTLR_HY
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #if OPTION_MEMCTLR_C32
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+
+  #if OPTION_MEMCTLR_OR
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NB_TRAIN_FLOW_DDR2,
+    NB_TRAIN_FLOW_DDR3,
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    MEM_TECH_CONSTRUCTOR_DDR2
+    MEM_TECH_CONSTRUCTOR_DDR3
+    NULL
+  };
+   /*---------------------------------------------------------------------------------------------------
+   * PLATFORM SPECIFIC BLOCK FORM FACTOR DEFINITION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if  OPTION_MEMCTLR_HY
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUHy3,
+      #else
+        #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+        #endif
+          #else
+      #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+        #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsRHy3,
+        #else
+        #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+        #endif
+    #else
+      #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsSHy3,
+      #else
+        #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+      #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+    #define PLAT_SP_HY_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_HY_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
+    PLAT_SP_HY_FF_UDIMM2
+    PLAT_SP_HY_FF_RDIMM2
+    PLAT_SP_HY_FF_SDIMM2
+    PLAT_SP_HY_FF_UDIMM3
+    PLAT_SP_HY_FF_RDIMM3
+    PLAT_SP_HY_FF_SDIMM3
+  };
+
+  #if OPTION_MEMCTLR_DR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        extern MEM_PLAT_SPEC_CFG MemPConstructPsUDr2;
+        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDr2,
+      #else
+        #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDr3,
+      #else
+        #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        extern MEM_PLAT_SPEC_CFG MemPConstructPsRDr2;
+        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsRDr2,
+  #else
+        #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+  #endif
+    #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsRDr3,
+      #else
+        #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+          #else
+      #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+          #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+        #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsSDr3,
+      #else
+        #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+        #else
+      #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+        #endif
+      #else
+    #define PLAT_SP_DR_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DR_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDR[MAX_FF_TYPES] = {
+    PLAT_SP_DR_FF_UDIMM2
+    PLAT_SP_DR_FF_RDIMM2
+    PLAT_SP_DR_FF_SDIMM2
+    PLAT_SP_DR_FF_UDIMM3
+    PLAT_SP_DR_FF_RDIMM3
+    PLAT_SP_DR_FF_SDIMM3
+  };
+
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDA3,
+      #else
+        #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+      #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #else
+      #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsSDA2,
+  #else
+        #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+  #endif
+    #if OPTION_DDR3
+        #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsSDA3,
+      #else
+        #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+      #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+        #endif
+          #else
+    #define PLAT_SP_DA_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_DA_FF_UDIMM3    MemPConstructPsUDef,
+        #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
+    PLAT_SP_DA_FF_UDIMM2
+    PLAT_SP_DA_FF_RDIMM2
+    PLAT_SP_DA_FF_SDIMM2
+    PLAT_SP_DA_FF_UDIMM3
+    PLAT_SP_DA_FF_RDIMM3
+    PLAT_SP_DA_FF_SDIMM3
+  };
+
+  #if (OPTION_MEMCTLR_Ni == TRUE)
+    #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsSNi3,
+    #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUNi3,
+      #else
+    #define PLAT_SP_NI_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_NI_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
+    PLAT_SP_NI_FF_UDIMM2
+    PLAT_SP_NI_FF_RDIMM2
+    PLAT_SP_NI_FF_SDIMM2
+    PLAT_SP_NI_FF_UDIMM3
+    PLAT_SP_NI_FF_RDIMM3
+    PLAT_SP_NI_FF_SDIMM3
+  };
+
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsSPh3,
+    #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUPh3,
+        #else
+    #define PLAT_SP_PH_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_PH_FF_UDIMM3    MemPConstructPsUDef,
+        #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
+    PLAT_SP_PH_FF_UDIMM2
+    PLAT_SP_PH_FF_RDIMM2
+    PLAT_SP_PH_FF_SDIMM2
+    PLAT_SP_PH_FF_UDIMM3
+    PLAT_SP_PH_FF_RDIMM3
+    PLAT_SP_PH_FF_SDIMM3
+  };
+
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsSRb3,
+    #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsURb3,
+  #else
+    #define PLAT_SP_RB_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_RB_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
+    PLAT_SP_RB_FF_UDIMM2
+    PLAT_SP_RB_FF_RDIMM2
+    PLAT_SP_RB_FF_SDIMM2
+    PLAT_SP_RB_FF_UDIMM3
+    PLAT_SP_RB_FF_RDIMM3
+    PLAT_SP_RB_FF_SDIMM3
+  };
+
+  #if  OPTION_MEMCTLR_C32
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUC32_3,
+      #else
+        #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+      #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+      #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+      #else
+        #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+      #endif
+      #if OPTION_DDR3
+        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsRC32_3,
+      #else
+        #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+      #else
+      #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+      #endif
+    #if OPTION_SODIMMS
+      #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
+      #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
+    #endif
+  #else
+    #define PLAT_SP_C32_FF_SDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_RDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_UDIMM2    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_SDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_RDIMM3    MemPConstructPsUDef,
+    #define PLAT_SP_C32_FF_UDIMM3    MemPConstructPsUDef,
+  #endif
+  MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
+    PLAT_SP_C32_FF_UDIMM2
+    PLAT_SP_C32_FF_RDIMM2
+    PLAT_SP_C32_FF_SDIMM2
+    PLAT_SP_C32_FF_UDIMM3
+    PLAT_SP_C32_FF_RDIMM3
+    PLAT_SP_C32_FF_SDIMM3
+      };
+
+  /*---------------------------------------------------------------------------------------------------
+   * PLATFORM-SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  #if OPTION_MEMCTLR_DR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_UDIMM_DDR2     //MemAGetPsCfgUDr2
+    #else
+        #define PSC_DR_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_DR_UDIMM_DDR3    MemAGetPsCfgUDr3,
+      #else
+        #define PSC_DR_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_RDIMM_DDR2    MemAGetPsCfgRDr2,
+  #else
+        #define PSC_DR_RDIMM_DDR2
+  #endif
+    #if OPTION_DDR3
+        #define PSC_DR_RDIMM_DDR3    MemAGetPsCfgRDr3,
+      #else
+        #define PSC_DR_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_DR_SODIMM_DDR2    //MemAGetPsCfgSDr2
+      #else
+        #define PSC_DR_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_DR_SODIMM_DDR3    //MemAGetPsCfgSDr3
+      #else
+        #define PSC_DR_SODIMM_DDR3
+        #endif
+        #endif
+  #endif
+
+  #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
+    #if OPTION_MEMCTLR_Ni
+      #define PSC_NI_UDIMM_DDR2
+      #define PSC_NI_UDIMM_DDR3     MemAGetPsCfgUNi3,
+      #define PSC_NI_RDIMM_DDR2
+      #define PSC_NI_RDIMM_DDR3
+      #define PSC_NI_SODIMM_DDR2
+      #define PSC_NI_SODIMM_DDR3    MemAGetPsCfgSNi3,
+    #endif
+    #if OPTION_MEMCTLR_PH
+      #define PSC_PH_UDIMM_DDR2
+      #define PSC_PH_UDIMM_DDR3     MemAGetPsCfgUPh3,
+      #define PSC_PH_RDIMM_DDR2
+      #define PSC_PH_RDIMM_DDR3
+      #define PSC_PH_SODIMM_DDR2
+      #define PSC_PH_SODIMM_DDR3    MemAGetPsCfgSPh3,
+    #endif
+    #if OPTION_MEMCTLR_RB
+      #define PSC_RB_UDIMM_DDR2
+      #define PSC_RB_UDIMM_DDR3     MemAGetPsCfgURb3,
+      #define PSC_RB_RDIMM_DDR2
+      #define PSC_RB_RDIMM_DDR3
+      #define PSC_RB_SODIMM_DDR2
+      #define PSC_RB_SODIMM_DDR3    MemAGetPsCfgSRb3,
+    #endif
+    #if OPTION_MEMCTLR_DA
+      #if OPTION_UDIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_UDIMM_DDR2     //MemAGetPsCfgUDr2
+        #else
+          #define PSC_DA_UDIMM_DDR2
+        #endif
+        #if OPTION_DDR3
+          #define PSC_DA_UDIMM_DDR3    MemAGetPsCfgUDA3,
+          #else
+          #define PSC_DA_UDIMM_DDR3
+          #endif
+        #endif
+      #if OPTION_RDIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_RDIMM_DDR2
+      #else
+          #define PSC_DA_RDIMM_DDR2
+        #endif
+        #if OPTION_DDR3
+          #define PSC_DA_RDIMM_DDR3
+        #else
+          #define PSC_DA_RDIMM_DDR3
+        #endif
+      #endif
+      #if OPTION_SODIMMS
+        #if OPTION_DDR2
+          #define PSC_DA_SODIMM_DDR2    MemAGetPsCfgSDA2,
+      #else
+          #define PSC_DA_SODIMM_DDR2
+      #endif
+        #if OPTION_DDR3
+          #define PSC_DA_SODIMM_DDR3    MemAGetPsCfgSDA3,
+      #else
+          #define PSC_DA_SODIMM_DDR3
+      #endif
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_HY
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_UDIMM_DDR2     //MemAGetPsCfgUDr2,
+      #else
+        #define PSC_HY_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_HY_UDIMM_DDR3    MemAGetPsCfgUHy3,
+      #else
+        #define PSC_HY_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_RDIMM_DDR2
+      #else
+        #define PSC_HY_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_HY_RDIMM_DDR3    MemAGetPsCfgRHy3,
+      #else
+        #define PSC_HY_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_HY_SODIMM_DDR2    //MemAGetPsCfgSHy2,
+    #else
+        #define PSC_HY_SODIMM_DDR2
+    #endif
+      #if OPTION_DDR3
+        #define PSC_HY_SODIMM_DDR3    //MemAGetPsCfgSHy3,
+  #else
+        #define PSC_HY_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_C32
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_UDIMM_DDR2     //MemAGetPsCfgUDr2,
+      #else
+        #define PSC_C32_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_UDIMM_DDR3    MemAGetPsCfgUC32_3,
+      #else
+        #define PSC_C32_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_RDIMM_DDR2
+      #else
+        #define PSC_C32_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_RDIMM_DDR3    MemAGetPsCfgRC32_3,
+      #else
+        #define PSC_C32_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_C32_SODIMM_DDR2    //MemAGetPsCfgSC32_2,
+      #else
+        #define PSC_C32_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_C32_SODIMM_DDR3    //MemAGetPsCfgSC32_3,
+      #else
+        #define PSC_C32_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  #if OPTION_MEMCTLR_OR
+    #if OPTION_UDIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_UDIMM_DDR2     //MemAGetPsCfgUOr2,
+      #else
+        #define PSC_OR_UDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_UDIMM_DDR3     //MemAGetPsCfgUOr3,
+      #else
+        #define PSC_OR_UDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_RDIMM_DDR2
+      #else
+        #define PSC_OR_RDIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_RDIMM_DDR3     //MemAGetPsCfgROr3,
+      #else
+        #define PSC_OR_RDIMM_DDR3
+      #endif
+    #endif
+    #if OPTION_SODIMMS
+      #if OPTION_DDR2
+        #define PSC_OR_SODIMM_DDR2    //MemAGetPsCfgSOr2,
+      #else
+        #define PSC_OR_SODIMM_DDR2
+      #endif
+      #if OPTION_DDR3
+        #define PSC_OR_SODIMM_DDR3    //MemAGetPsCfgSOr3,
+      #else
+        #define PSC_OR_SODIMM_DDR3
+      #endif
+    #endif
+  #endif
+
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+
+  #ifndef PSC_DR_UDIMM_DDR2
+    #define PSC_DR_UDIMM_DDR2
+      #endif
+  #ifndef PSC_DR_RDIMM_DDR2
+    #define PSC_DR_RDIMM_DDR2
+    #endif
+  #ifndef PSC_DR_SODIMM_DDR2
+    #define PSC_DR_SODIMM_DDR2
+      #endif
+  #ifndef PSC_DR_UDIMM_DDR3
+    #define PSC_DR_UDIMM_DDR3
+      #endif
+  #ifndef PSC_DR_RDIMM_DDR3
+    #define PSC_DR_RDIMM_DDR3
+    #endif
+  #ifndef PSC_DR_SODIMM_DDR3
+    #define PSC_DR_SODIMM_DDR3
+      #endif
+  #ifndef PSC_RB_UDIMM_DDR2
+    #define PSC_RB_UDIMM_DDR2
+      #endif
+  #ifndef PSC_RB_RDIMM_DDR2
+    #define PSC_RB_RDIMM_DDR2
+    #endif
+  #ifndef PSC_RB_SODIMM_DDR2
+    #define PSC_RB_SODIMM_DDR2
+  #endif
+  #ifndef PSC_RB_UDIMM_DDR3
+    #define PSC_RB_UDIMM_DDR3
+  #endif
+  #ifndef PSC_RB_RDIMM_DDR3
+    #define PSC_RB_RDIMM_DDR3
+  #endif
+  #ifndef PSC_RB_SODIMM_DDR3
+    #define PSC_RB_SODIMM_DDR3
+  #endif
+  #ifndef PSC_DA_UDIMM_DDR2
+    #define PSC_DA_UDIMM_DDR2
+      #endif
+  #ifndef PSC_DA_RDIMM_DDR2
+    #define PSC_DA_RDIMM_DDR2
+    #endif
+  #ifndef PSC_DA_SODIMM_DDR2
+    #define PSC_DA_SODIMM_DDR2
+      #endif
+  #ifndef PSC_DA_UDIMM_DDR3
+    #define PSC_DA_UDIMM_DDR3
+    #endif
+  #ifndef PSC_DA_RDIMM_DDR3
+    #define PSC_DA_RDIMM_DDR3
+  #endif
+  #ifndef PSC_DA_SODIMM_DDR3
+    #define PSC_DA_SODIMM_DDR3
+      #endif
+  #ifndef PSC_NI_UDIMM_DDR2
+    #define PSC_NI_UDIMM_DDR2
+      #endif
+  #ifndef PSC_NI_RDIMM_DDR2
+    #define PSC_NI_RDIMM_DDR2
+    #endif
+  #ifndef PSC_NI_SODIMM_DDR2
+    #define PSC_NI_SODIMM_DDR2
+      #endif
+  #ifndef PSC_NI_UDIMM_DDR3
+    #define PSC_NI_UDIMM_DDR3
+      #endif
+  #ifndef PSC_NI_RDIMM_DDR3
+    #define PSC_NI_RDIMM_DDR3
+    #endif
+  #ifndef PSC_NI_SODIMM_DDR3
+    #define PSC_NI_SODIMM_DDR3
+    #endif
+  #ifndef PSC_PH_UDIMM_DDR2
+    #define PSC_PH_UDIMM_DDR2
+  #endif
+  #ifndef PSC_PH_RDIMM_DDR2
+    #define PSC_PH_RDIMM_DDR2
+      #endif
+  #ifndef PSC_PH_SODIMM_DDR2
+    #define PSC_PH_SODIMM_DDR2
+    #endif
+  #ifndef PSC_PH_UDIMM_DDR3
+    #define PSC_PH_UDIMM_DDR3
+      #endif
+  #ifndef PSC_PH_RDIMM_DDR3
+      #define PSC_PH_RDIMM_DDR3
+    #endif
+  #ifndef PSC_PH_SODIMM_DDR3
+    #define PSC_PH_SODIMM_DDR3
+  #endif
+  #ifndef PSC_HY_UDIMM_DDR2
+        #define PSC_HY_UDIMM_DDR2
+      #endif
+  #ifndef PSC_HY_RDIMM_DDR2
+        #define PSC_HY_RDIMM_DDR2
+      #endif
+  #ifndef PSC_HY_SODIMM_DDR2
+        #define PSC_HY_SODIMM_DDR2
+      #endif
+  #ifndef PSC_HY_UDIMM_DDR3
+    #define PSC_HY_UDIMM_DDR3
+      #endif
+  #ifndef PSC_HY_RDIMM_DDR3
+    #define PSC_HY_RDIMM_DDR3
+    #endif
+  #ifndef PSC_HY_SODIMM_DDR3
+    #define PSC_HY_SODIMM_DDR3
+  #endif
+  #ifndef PSC_LN_UDIMM_DDR2
+    #define PSC_LN_UDIMM_DDR2
+      #endif
+  #ifndef PSC_LN_RDIMM_DDR2
+    #define PSC_LN_RDIMM_DDR2
+      #endif
+  #ifndef PSC_LN_SODIMM_DDR2
+    #define PSC_LN_SODIMM_DDR2
+    #endif
+  #ifndef PSC_LN_UDIMM_DDR3
+    #define PSC_LN_UDIMM_DDR3
+      #endif
+  #ifndef PSC_LN_RDIMM_DDR3
+    #define PSC_LN_RDIMM_DDR3
+      #endif
+  #ifndef PSC_LN_SODIMM_DDR3
+    #define PSC_LN_SODIMM_DDR3
+    #endif
+  #ifndef PSC_OR_UDIMM_DDR2
+    #define PSC_OR_UDIMM_DDR2
+      #endif
+  #ifndef PSC_OR_RDIMM_DDR2
+    #define PSC_OR_RDIMM_DDR2
+      #endif
+  #ifndef PSC_OR_SODIMM_DDR2
+    #define PSC_OR_SODIMM_DDR2
+    #endif
+  #ifndef PSC_OR_UDIMM_DDR3
+    #define PSC_OR_UDIMM_DDR3
+  #endif
+  #ifndef PSC_OR_RDIMM_DDR3
+    #define PSC_OR_RDIMM_DDR3
+      #endif
+  #ifndef PSC_OR_SODIMM_DDR3
+    #define PSC_OR_SODIMM_DDR3
+      #endif
+  #ifndef PSC_C32_UDIMM_DDR3
+    #define PSC_C32_UDIMM_DDR3
+    #endif
+  #ifndef PSC_C32_RDIMM_DDR3
+    #define PSC_C32_RDIMM_DDR3
+      #endif
+  #ifndef PSC_ON_UDIMM_DDR2
+    #define PSC_ON_UDIMM_DDR2
+      #endif
+  #ifndef PSC_ON_RDIMM_DDR2
+    #define PSC_ON_RDIMM_DDR2
+    #endif
+  #ifndef PSC_ON_SODIMM_DDR2
+    #define PSC_ON_SODIMM_DDR2
+      #endif
+  #ifndef PSC_ON_UDIMM_DDR3
+    #define PSC_ON_UDIMM_DDR3
+      #endif
+  #ifndef PSC_ON_RDIMM_DDR3
+    #define PSC_ON_RDIMM_DDR3
+    #endif
+  #ifndef PSC_ON_SODIMM_DDR3
+    #define PSC_ON_SODIMM_DDR3
+  #endif
+
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    PSC_DR_UDIMM_DDR2
+    PSC_DR_RDIMM_DDR2
+    PSC_DR_SODIMM_DDR2
+    PSC_DR_UDIMM_DDR3
+    PSC_DR_RDIMM_DDR3
+    PSC_DR_SODIMM_DDR3
+    PSC_RB_UDIMM_DDR3
+    PSC_RB_SODIMM_DDR3
+    PSC_DA_SODIMM_DDR2
+    PSC_DA_UDIMM_DDR3
+    PSC_DA_SODIMM_DDR3
+    PSC_NI_UDIMM_DDR3
+    PSC_NI_SODIMM_DDR3
+    PSC_PH_UDIMM_DDR3
+    PSC_PH_SODIMM_DDR3
+    PSC_HY_UDIMM_DDR3
+    PSC_HY_RDIMM_DDR3
+    PSC_HY_SODIMM_DDR3
+    PSC_LN_UDIMM_DDR3
+    PSC_LN_RDIMM_DDR3
+    PSC_LN_SODIMM_DDR3
+    PSC_OR_UDIMM_DDR3
+    PSC_OR_RDIMM_DDR3
+    PSC_OR_SODIMM_DDR3
+    PSC_C32_UDIMM_DDR3
+    PSC_C32_RDIMM_DDR3
+    PSC_ON_UDIMM_DDR3
+    PSC_ON_RDIMM_DDR3
+    PSC_ON_SODIMM_DDR3
+    NULL
+  };
+  CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
+//  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
+//    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
+//  #endif
+
+  /*---------------------------------------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_PSC_FLOW_BLOCK_END NULL
+  #define PSC_TBL_END NULL
+  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
+
+  #if OPTION_MEMCTLR_OR
+    #if OPTION_UDIMMS
+      #if OPTION_AM3_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3  &MaxFreqTblEntUAM3,
+        extern PSC_TBL_ENTRY DramTermTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3  &DramTermTblEntUAM3,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3  &OdtPat1DTblEntUAM3,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3  &OdtPat2DTblEntUAM3,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3  &OdtPat3DTblEntUAM3,
+        extern PSC_TBL_ENTRY SAOTblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_SAO_AM3  &SAOTblEntUAM3,
+        extern PSC_TBL_ENTRY ClkDisMapEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3 &ClkDisMapEntUAM3,
+        extern PSC_TBL_ENTRY S__TblEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_S___AM3  &S__TblEntUAM3,
+        extern PSC_TBL_ENTRY WLPass1SeedEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3  &WLPass1SeedEntUAM3,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3;
+        #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3  &HWRxEnPass1SeedEntUAM3,
+      #endif
+      #if OPTION_C32_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32  &MaxFreqTblEntUC32,
+        extern PSC_TBL_ENTRY DramTermTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32  &DramTermTblEntUC32,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntUC32,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32  &OdtPat2DTblEntUC32,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntUC32,
+        extern PSC_TBL_ENTRY SAOTblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_SAO_C32  &SAOTblEntUC32,
+        extern PSC_TBL_ENTRY ClkDisMapEntUC32;
+        #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32 &ClkDisMapEntUC32,
+        extern PSC_TBL_ENTRY ClkDisMap3DEntUC32;
+        #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32 &ClkDisMap3DEntUC32,
+        extern PSC_TBL_ENTRY S__TblEntUC32;
+        #define PSC_TBL_OR_UDIMM3_S___C32  &S__TblEntUC32,
+        extern PSC_TBL_ENTRY WLPass1SeedEntUC32;
+        #define PSC_TBL_OR_UDIMM3_WL_SEED_C32  &WLPass1SeedEntUC32,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUC32;
+        #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32  &HWRxEnPass1SeedEntUC32,
+      #endif
+      #if OPTION_G34_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34  &MaxFreqTblEntUG34,
+        extern PSC_TBL_ENTRY DramTermTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34  &DramTermTblEntUG34,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntUG34,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34  &OdtPat2DTblEntUG34,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntUG34,
+        extern PSC_TBL_ENTRY SAOTblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_SAO_G34  &SAOTblEntUG34,
+        extern PSC_TBL_ENTRY ClkDisMapEntUG34;
+        #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34 &ClkDisMapEntUG34,
+        extern PSC_TBL_ENTRY S__TblEntUG34;
+        #define PSC_TBL_OR_UDIMM3_S___G34  &S__TblEntUG34,
+        extern PSC_TBL_ENTRY WLPass1SeedEntUG34;
+        #define PSC_TBL_OR_UDIMM3_WL_SEED_G34  &WLPass1SeedEntUG34,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntUG34;
+        #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34  &HWRxEnPass1SeedEntUG34,
+    #endif
+    #endif
+    #if OPTION_RDIMMS
+      #if OPTION_C32_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32  &MaxFreqTblEntRC32,
+        extern PSC_TBL_ENTRY DramTermTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32  &DramTermTblEntRC32,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntRC32,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32  &OdtPat2DTblEntRC32,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntRC32,
+        extern PSC_TBL_ENTRY SAOTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_SAO_C32  &SAOTblEntRC32,
+        extern PSC_TBL_ENTRY RC2IBTTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_RC2IBT_C32  &RC2IBTTblEntRC32,
+        extern PSC_TBL_ENTRY RC10OpSpdTblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32  &RC10OpSpdTblEntRC32,
+        extern PSC_TBL_ENTRY ClkDisMapEntRC32;
+        #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32 &ClkDisMapEntRC32,
+        extern PSC_TBL_ENTRY S__TblEntRC32;
+        #define PSC_TBL_OR_RDIMM3_S___C32  &S__TblEntRC32,
+        extern PSC_TBL_ENTRY WLPass1SeedEntRC32;
+        #define PSC_TBL_OR_RDIMM3_WL_SEED_C32  &WLPass1SeedEntRC32,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRC32;
+        #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32  &HWRxEnPass1SeedEntRC32,
+    #endif
+      #if OPTION_G34_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34  &MaxFreqTblEntRG34,
+        extern PSC_TBL_ENTRY DramTermTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34  &DramTermTblEntRG34,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntRG34,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34  &OdtPat2DTblEntRG34,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntRG34,
+        extern PSC_TBL_ENTRY SAOTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_SAO_G34  &SAOTblEntRG34,
+        extern PSC_TBL_ENTRY RC2IBTTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_RC2IBT_G34  &RC2IBTTblEntRG34,
+        extern PSC_TBL_ENTRY RC10OpSpdTblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34  &RC10OpSpdTblEntRG34,
+        extern PSC_TBL_ENTRY ClkDisMapEntRG34;
+        #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34 &ClkDisMapEntRG34,
+        extern PSC_TBL_ENTRY S__TblEntRG34;
+        #define PSC_TBL_OR_RDIMM3_S___G34  &S__TblEntRG34,
+        extern PSC_TBL_ENTRY WLPass1SeedEntRG34;
+        #define PSC_TBL_OR_RDIMM3_WL_SEED_G34  &WLPass1SeedEntRG34,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntRG34;
+        #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34  &HWRxEnPass1SeedEntRG34,
+    #endif
+    #endif
+    //#if OPTION_SODIMMS
+    //#endif
+    #if OPTION_LRDIMMS
+      #if OPTION_C32_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32  &MaxFreqTblEntLRC32,
+        extern PSC_TBL_ENTRY DramTermTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32  &DramTermTblEntLRC32,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32  &OdtPat1DTblEntLRC32,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32  &OdtPat2DTblEntLRC32,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32  &OdtPat3DTblEntLRC32,
+        extern PSC_TBL_ENTRY SAOTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_SAO_C32  &SAOTblEntLRC32,
+        extern PSC_TBL_ENTRY IBTTblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_IBT_C32  &IBTTblEntLRC32,
+        extern PSC_TBL_ENTRY ClkDisMapEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32 &ClkDisMapEntLRC32,
+        extern PSC_TBL_ENTRY S__TblEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_S___C32  &S__TblEntLRC32,
+        extern PSC_TBL_ENTRY WLPass1SeedEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32  &WLPass1SeedEntLRC32,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRC32;
+        #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32 &HWRxEnPass1SeedEntLRC32,
+    #endif
+      #if OPTION_G34_SOCKET_SUPPORT
+        extern PSC_TBL_ENTRY MaxFreqTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34  &MaxFreqTblEntLRG34,
+        extern PSC_TBL_ENTRY DramTermTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34  &DramTermTblEntLRG34,
+        extern PSC_TBL_ENTRY OdtPat1DTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34  &OdtPat1DTblEntLRG34,
+        extern PSC_TBL_ENTRY OdtPat2DTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34  &OdtPat2DTblEntLRG34,
+        extern PSC_TBL_ENTRY OdtPat3DTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34  &OdtPat3DTblEntLRG34,
+        extern PSC_TBL_ENTRY SAOTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_SAO_G34  &SAOTblEntLRG34,
+        extern PSC_TBL_ENTRY IBTTblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_IBT_G34  &IBTTblEntLRG34,
+        extern PSC_TBL_ENTRY ClkDisMapEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34 &ClkDisMapEntLRG34,
+        extern PSC_TBL_ENTRY S__TblEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_S___G34  &S__TblEntLRG34,
+        extern PSC_TBL_ENTRY WLPass1SeedEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34  &WLPass1SeedEntLRG34,
+        extern PSC_TBL_ENTRY HWRxEnPass1SeedEntLRG34;
+        #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34 &HWRxEnPass1SeedEntLRG34,
+    #endif
+    #endif
+    extern PSC_TBL_ENTRY MR0WrTblEntry;
+    #define PSC_TBL_OR_MR0_WR  &MR0WrTblEntry,
+    extern PSC_TBL_ENTRY MR0CLTblEntry;
+    #define PSC_TBL_OR_MR0_CL  &MR0CLTblEntry,
+    extern PSC_TBL_ENTRY OrDdr3CKETriEnt;
+    #define PSC_TBL_OR_CKE_TRI &OrDdr3CKETriEnt,
+    extern PSC_TBL_ENTRY OrDdr3ODTTri3DEnt;
+    #define PSC_TBL_OR_ODT_TRI_3D &OrDdr3ODTTri3DEnt,
+    extern PSC_TBL_ENTRY OrDdr3ODTTriEnt;
+    #define PSC_TBL_OR_ODT_TRI &OrDdr3ODTTriEnt,
+    extern PSC_TBL_ENTRY OrUDdr3CSTriEnt;
+    #define PSC_TBL_OR_UDIMM3_CS_TRI &OrUDdr3CSTriEnt,
+    extern PSC_TBL_ENTRY OrDdr3CSTriEnt;
+    #define PSC_TBL_OR_CS_TRI &OrDdr3CSTriEnt,
+    extern PSC_TBL_ENTRY OrLRDdr3ODTTri3DEnt;
+    #define PSC_TBL_OR_LRDIMM3_ODT_TRI_3D &OrLRDdr3ODTTri3DEnt,
+    extern PSC_TBL_ENTRY OrLRDdr3ODTTriEnt;
+    #define PSC_TBL_OR_LRDIMM3_ODT_TRI &OrLRDdr3ODTTriEnt,
+
+    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
+      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
+      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
+      #define PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
+      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
+      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
+      #define PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____C32
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT____C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT____G34
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT____G34
+  #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
+      #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
+      #define PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
+      #endif
+    #ifndef PSC_TBL_OR_UDIMM3_SAO_AM3
+      #define PSC_TBL_OR_UDIMM3_SAO_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_SAO_C32
+      #define PSC_TBL_OR_UDIMM3_SAO_C32
+      #endif
+    #ifndef PSC_TBL_OR_UDIMM3_SAO_G34
+      #define PSC_TBL_OR_UDIMM3_SAO_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_S___AM3
+      #define PSC_TBL_OR_UDIMM3_S___AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_S___C32
+      #define PSC_TBL_OR_UDIMM3_S___C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_S___G34
+      #define PSC_TBL_OR_UDIMM3_S___G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_AM3
+      #define PSC_TBL_OR_UDIMM3_WL_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_C32
+      #define PSC_TBL_OR_UDIMM3_WL_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_WL_SEED_G34
+      #define PSC_TBL_OR_UDIMM3_WL_SEED_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
+      #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
+      #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
+      #define PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
+      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
+      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
+      #define PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
+      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
+      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
+      #define PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____C32
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT____C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT____G34
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT____G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
+      #define PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_SAO_AM3
+      #define PSC_TBL_OR_RDIMM3_SAO_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_SAO_C32
+      #define PSC_TBL_OR_RDIMM3_SAO_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_SAO_G34
+      #define PSC_TBL_OR_RDIMM3_SAO_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_S___AM3
+      #define PSC_TBL_OR_RDIMM3_S___AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_S___C32
+      #define PSC_TBL_OR_RDIMM3_S___C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_S___G34
+      #define PSC_TBL_OR_RDIMM3_S___G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_AM3
+      #define PSC_TBL_OR_RDIMM3_RC2IBT_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_C32
+      #define PSC_TBL_OR_RDIMM3_RC2IBT_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC2IBT_G34
+      #define PSC_TBL_OR_RDIMM3_RC2IBT_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
+      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
+      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
+      #define PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_AM3
+      #define PSC_TBL_OR_RDIMM3_WL_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_C32
+      #define PSC_TBL_OR_RDIMM3_WL_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_WL_SEED_G34
+      #define PSC_TBL_OR_RDIMM3_WL_SEED_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
+      #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
+      #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
+      #define PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
+      #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
+      #define PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
+      #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
+      #define PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
+      #define PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_SAO_C32
+      #define PSC_TBL_OR_LRDIMM3_SAO_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_SAO_G34
+      #define PSC_TBL_OR_LRDIMM3_SAO_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_S___C32
+      #define PSC_TBL_OR_LRDIMM3_S___C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_S___G34
+      #define PSC_TBL_OR_LRDIMM3_S___G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_IBT_C32
+      #define PSC_TBL_OR_LRDIMM3_IBT_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_IBT_G34
+      #define PSC_TBL_OR_LRDIMM3_IBT_G34
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
+      #define PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_C32
+      #define PSC_TBL_OR_UDIMM3_CLK_DIS_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
+      #define PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
+    #endif
+    #ifndef PSC_TBL_OR_UDIMM3_CLK_DIS_G34
+      #define PSC_TBL_OR_UDIMM3_CLK_DIS_G34
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_C32
+      #define PSC_TBL_OR_RDIMM3_CLK_DIS_C32
+    #endif
+    #ifndef PSC_TBL_OR_RDIMM3_CLK_DIS_G34
+      #define PSC_TBL_OR_RDIMM3_CLK_DIS_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
+      #define PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
+      #define PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
+      #define PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_C32
+      #define PSC_TBL_OR_LRDIMM3_WL_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_WL_SEED_G34
+      #define PSC_TBL_OR_LRDIMM3_WL_SEED_G34
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
+      #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
+      #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
+    #endif
+    #ifndef PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
+      #define PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
+    #endif
+
+
+    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_MAX_FREQ_AM3
+      PSC_TBL_OR_UDIMM3_MAX_FREQ_C32
+      PSC_TBL_OR_UDIMM3_MAX_FREQ_G34
+      PSC_TBL_OR_RDIMM3_MAX_FREQ_AM3
+      PSC_TBL_OR_RDIMM3_MAX_FREQ_C32
+      PSC_TBL_OR_RDIMM3_MAX_FREQ_G34
+      PSC_TBL_OR_LRDIMM3_MAX_FREQ_C32
+      PSC_TBL_OR_LRDIMM3_MAX_FREQ_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblDramTermArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_DRAM_TERM_AM3
+      PSC_TBL_OR_UDIMM3_DRAM_TERM_C32
+      PSC_TBL_OR_UDIMM3_DRAM_TERM_G34
+      PSC_TBL_OR_RDIMM3_DRAM_TERM_AM3
+      PSC_TBL_OR_RDIMM3_DRAM_TERM_C32
+      PSC_TBL_OR_RDIMM3_DRAM_TERM_G34
+      PSC_TBL_OR_LRDIMM3_DRAM_TERM_C32
+      PSC_TBL_OR_LRDIMM3_DRAM_TERM_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblODTPatArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
+      PSC_TBL_OR_UDIMM3_ODT_PAT____AM3
+      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
+      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
+      PSC_TBL_OR_RDIMM3_ODT_PAT____AM3
+      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
+      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
+      PSC_TBL_OR_UDIMM3_ODT_PAT____C32
+      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
+      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
+      PSC_TBL_OR_RDIMM3_ODT_PAT____C32
+      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
+      PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_C32
+      PSC_TBL_OR_LRDIMM3_ODT_PAT____C32
+      PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_C32
+      PSC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
+      PSC_TBL_OR_UDIMM3_ODT_PAT____G34
+      PSC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
+      PSC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
+      PSC_TBL_OR_RDIMM3_ODT_PAT____G34
+      PSC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
+      PSC_TBL_OR_LRDIMM3_ODT_PAT_1D_G34
+      PSC_TBL_OR_LRDIMM3_ODT_PAT____G34
+      PSC_TBL_OR_LRDIMM3_ODT_PAT_3D_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblSAOArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_SAO_AM3
+      PSC_TBL_OR_UDIMM3_SAO_C32
+      PSC_TBL_OR_UDIMM3_SAO_G34
+      PSC_TBL_OR_RDIMM3_SAO_AM3
+      PSC_TBL_OR_RDIMM3_SAO_C32
+      PSC_TBL_OR_RDIMM3_SAO_G34
+      PSC_TBL_OR_LRDIMM3_SAO_C32
+      PSC_TBL_OR_LRDIMM3_SAO_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblS__ArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_S___AM3
+      PSC_TBL_OR_UDIMM3_S___C32
+      PSC_TBL_OR_UDIMM3_S___G34
+      PSC_TBL_OR_RDIMM3_S___AM3
+      PSC_TBL_OR_RDIMM3_S___C32
+      PSC_TBL_OR_RDIMM3_S___G34
+      PSC_TBL_OR_LRDIMM3_S___C32
+      PSC_TBL_OR_LRDIMM3_S___G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0WRArrayOR[] = {
+      PSC_TBL_OR_MR0_WR
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblMR0CLArrayOR[] = {
+      PSC_TBL_OR_MR0_CL
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblRC2IBTArrayOR[] = {
+      PSC_TBL_OR_RDIMM3_RC2IBT_AM3
+      PSC_TBL_OR_RDIMM3_RC2IBT_C32
+      PSC_TBL_OR_RDIMM3_RC2IBT_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblRC10OPSPDArrayOR[] = {
+      PSC_TBL_OR_RDIMM3_RC10OPSPD_AM3
+      PSC_TBL_OR_RDIMM3_RC10OPSPD_C32
+      PSC_TBL_OR_RDIMM3_RC10OPSPD_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblLRIBTArrayOR[] = {
+      PSC_TBL_OR_LRDIMM3_IBT_C32
+      PSC_TBL_OR_LRDIMM3_IBT_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblGenArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_CLK_DIS_AM3
+      PSC_TBL_OR_UDIMM3_CLK_DIS_C32
+      PSC_TBL_OR_UDIMM3_CLK_DIS_3D_C32
+      PSC_TBL_OR_UDIMM3_CLK_DIS_G34
+      PSC_TBL_OR_RDIMM3_CLK_DIS_C32
+      PSC_TBL_OR_RDIMM3_CLK_DIS_G34
+      PSC_TBL_OR_LRDIMM3_CLK_DIS_C32
+      PSC_TBL_OR_LRDIMM3_CLK_DIS_G34
+      PSC_TBL_OR_CKE_TRI
+      PSC_TBL_OR_ODT_TRI_3D
+      PSC_TBL_OR_ODT_TRI
+      PSC_TBL_OR_LRDIMM3_ODT_TRI_3D
+      PSC_TBL_OR_LRDIMM3_ODT_TRI
+      PSC_TBL_OR_UDIMM3_CS_TRI
+      PSC_TBL_OR_CS_TRI
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblWLSeedArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_WL_SEED_AM3
+      PSC_TBL_OR_UDIMM3_WL_SEED_C32
+      PSC_TBL_OR_UDIMM3_WL_SEED_G34
+      PSC_TBL_OR_RDIMM3_WL_SEED_AM3
+      PSC_TBL_OR_RDIMM3_WL_SEED_C32
+      PSC_TBL_OR_RDIMM3_WL_SEED_G34
+      PSC_TBL_OR_LRDIMM3_WL_SEED_AM3
+      PSC_TBL_OR_LRDIMM3_WL_SEED_C32
+      PSC_TBL_OR_LRDIMM3_WL_SEED_G34
+      PSC_TBL_END
+    };
+
+    PSC_TBL_ENTRY* memPSCTblHWRxEnSeedArrayOR[] = {
+      PSC_TBL_OR_UDIMM3_HWRXEN_SEED_AM3
+      PSC_TBL_OR_UDIMM3_HWRXEN_SEED_C32
+      PSC_TBL_OR_UDIMM3_HWRXEN_SEED_G34
+      PSC_TBL_OR_RDIMM3_HWRXEN_SEED_AM3
+      PSC_TBL_OR_RDIMM3_HWRXEN_SEED_C32
+      PSC_TBL_OR_RDIMM3_HWRXEN_SEED_G34
+      PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_AM3
+      PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_C32
+      PSC_TBL_OR_LRDIMM3_HWRXEN_SEED_G34
+      PSC_TBL_END
+    };
+
+    MEM_PSC_TABLE_BLOCK memPSCTblBlockOr = {
+      (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblSAOArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0WRArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblMR0CLArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblRC2IBTArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblRC10OPSPDArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblLRIBTArrayOR,
+      NULL,
+      NULL,
+      (PSC_TBL_ENTRY **)&memPSCTblGenArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblS__ArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblWLSeedArrayOR,
+      (PSC_TBL_ENTRY **)&memPSCTblHWRxEnSeedArrayOR
+    };
+
+    extern MEM_PSC_FLOW MemPGetMaxFreqSupported;
+    #define PSC_FLOW_OR_MAX_FREQ   MemPGetMaxFreqSupported
+    extern MEM_PSC_FLOW MemPGetRttNomWr;
+    #define PSC_FLOW_OR_DRAM_TERM   MemPGetRttNomWr
+    extern MEM_PSC_FLOW MemPGetODTPattern;
+    #define PSC_FLOW_OR_ODT_PATTERN   MemPGetODTPattern
+    extern MEM_PSC_FLOW MemPGetSAO;
+    #define PSC_FLOW_OR_SAO   MemPGetSAO
+    extern MEM_PSC_FLOW MemPGetMR0WrCL;
+    #define PSC_FLOW_OR_MR0_WRCL   MemPGetMR0WrCL
+    extern MEM_PSC_FLOW MemPGetS__;
+    #define PSC_FLOW_OR_S__   MemPGetS__
+    extern MEM_PSC_FLOW MemPGetTrainingSeeds;
+    #define PSC_FLOW_OR_SEED MemPGetTrainingSeeds
+    #if OPTION_RDIMMS
+      extern MEM_PSC_FLOW MemPGetRC2IBT;
+      #define PSC_FLOW_OR_RC2_IBT    MemPGetRC2IBT
+      extern MEM_PSC_FLOW MemPGetRC10OpSpd;
+      #define PSC_FLOW_OR_RC10_OPSPD   MemPGetRC10OpSpd
+    #endif
+    #if OPTION_LRDIMMS
+      extern MEM_PSC_FLOW MemPGetLRIBT;
+      #define PSC_FLOW_OR_LR_IBT   MemPGetLRIBT
+      extern MEM_PSC_FLOW MemPGetLRNPR;
+      #define PSC_FLOW_OR_LR_NPR   MemPGetLRNPR
+      extern MEM_PSC_FLOW MemPGetLRNLR;
+      #define PSC_FLOW_OR_LR_NLR  MemPGetLRNLR
+    #endif
+    #ifndef PSC_FLOW_OR_MAX_FREQ
+      #define PSC_FLOW_OR_MAX_FREQ   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_DRAM_TERM
+      #define PSC_FLOW_OR_DRAM_TERM   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_ODT_PATTERN
+      #define PSC_FLOW_OR_ODT_PATTERN   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_SAO
+      #define PSC_FLOW_OR_SAO   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_MR0_WRCL
+      #define PSC_FLOW_OR_MR0_WRCL   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_RC2_IBT
+      #define PSC_FLOW_OR_RC2_IBT   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_RC10_OPSPD
+      #define PSC_FLOW_OR_RC10_OPSPD   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_LR_IBT
+      #define PSC_FLOW_OR_LR_IBT   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_LR_NPR
+      #define PSC_FLOW_OR_LR_NPR   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_LR_NLR
+      #define PSC_FLOW_OR_LR_NLR   MEM_PSC_FLOW_DEFTRUE
+  #endif
+    #ifndef PSC_FLOW_OR_S__
+      #define PSC_FLOW_OR_S__   MEM_PSC_FLOW_DEFTRUE
+    #endif
+    #ifndef PSC_FLOW_OR_SEED
+      #define PSC_FLOW_OR_SEED   MEM_PSC_FLOW_DEFTRUE
+    #endif
+
+    MEM_PSC_FLOW_BLOCK memPlatSpecFlowOR = {
+      &memPSCTblBlockOr,
+      PSC_FLOW_OR_MAX_FREQ,
+      PSC_FLOW_OR_DRAM_TERM,
+      PSC_FLOW_OR_ODT_PATTERN,
+      PSC_FLOW_OR_SAO,
+      PSC_FLOW_OR_MR0_WRCL,
+      PSC_FLOW_OR_RC2_IBT,
+      PSC_FLOW_OR_RC10_OPSPD,
+      PSC_FLOW_OR_LR_IBT,
+      PSC_FLOW_OR_LR_NPR,
+      PSC_FLOW_OR_LR_NLR,
+      PSC_FLOW_OR_S__,
+      PSC_FLOW_OR_SEED
+    };
+    #define MEM_PSC_FLOW_BLOCK_OR &memPlatSpecFlowOR,
+  #else
+    #define MEM_PSC_FLOW_BLOCK_OR
+  #endif
+
+  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+    MEM_PSC_FLOW_BLOCK_OR
+    MEM_PSC_FLOW_BLOCK_END
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+  *
+  *  LRDIMM CONTROL
+  *
+  *---------------------------------------------------------------------------------------------------
+  */
+  #if (OPTION_LRDIMMS == TRUE)
+    #if ((OPTION_MEMCTLR_OR == TRUE))
+      #define MEM_TECH_FEATURE_LRDIMM_INIT  &MemTLrdimmConstructor3
+    #else //#if ((OPTION_MEMCTLR_OR == FALSE))
+      #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
+    #endif
+  #else //#if (OPTION_LRDIMMS == FALSE)
+    #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
+  #endif
+  MEM_TECH_LRDIMM memLrdimmSupported = {
+    MEM_TECH_LRDIMM_STRUCT_VERSION,
+    MEM_TECH_FEATURE_LRDIMM_INIT
+  };
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY MAP
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    #undef MEM_NB_SUPPORT_DR
+    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
+  #endif
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    #undef MEM_NB_SUPPORT_RB
+    #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    #undef MEM_NB_SUPPORT_DA
+    #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+  #endif
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    #undef MEM_NB_SUPPORT_PH
+    #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    #undef MEM_NB_SUPPORT_HY
+    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    #undef MEM_NB_SUPPORT_C32
+    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
+  #endif
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    #undef MEM_NB_SUPPORT_OR
+    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, NULL, NULL, NULL, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
+  #endif
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT Technology Training
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if OPTION_DDR2
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+      NULL
+    };
+    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+      NULL
+    };
+  #endif
+  #if OPTION_DDR3
+    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+      NULL
+    };
+    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+      NULL
+    };
+  #endif
+    /*---------------------------------------------------------------------------------------------------
+     * DEFAULT Platform Specific list
+     *
+     *
+     *---------------------------------------------------------------------------------------------------
+     */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_Ni == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = {
+      NULL
+    };
+  #endif
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+    NULL
+  };
+
+  /*----------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+    NULL
+  };
+
+  MEM_TECH_LRDIMM memLrdimmSupported = {
+    MEM_TECH_LRDIMM_STRUCT_VERSION,
+    NULL
+  };
+#endif
+
+/*---------------------------------------------------------------------------------------------------
+ * NORTHBRIDGE SUPPORT LIST
+ *
+ *
+ *---------------------------------------------------------------------------------------------------
+ */
+MEM_NB_SUPPORT memNBInstalled[] = {
+  MEM_NB_SUPPORT_RB
+  MEM_NB_SUPPORT_DA
+  MEM_NB_SUPPORT_Ni
+  MEM_NB_SUPPORT_PH
+  MEM_NB_SUPPORT_HY
+  MEM_NB_SUPPORT_OR
+  MEM_NB_SUPPORT_C32
+  MEM_NB_SUPPORT_END
+};
+
+#endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecovery.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecovery.h
new file mode 100644
index 0000000..6153aea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecovery.h
@@ -0,0 +1,63 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_RECOVERY_H_
+#define _OPTION_MEMORY_RECOVERY_H_
+
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+
+typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_REC_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h
new file mode 100644
index 0000000..f5dea81
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryRecoveryInstall.h
@@ -0,0 +1,263 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 54577 $   @e \$Date: 2011-06-09 04:28:28 -0600 (Thu, 09 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
+#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
+
+#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
+    #define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
+  #else
+    #define MEM_REC_NB_SUPPORT_DR
+  #endif
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
+    #define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
+  #else
+    #define MEM_REC_NB_SUPPORT_RB
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
+    #define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
+  #else
+    #define MEM_REC_NB_SUPPORT_DA
+  #endif
+  #if (OPTION_MEMCTLR_NI == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
+    #define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
+  #else
+    #define MEM_REC_NB_SUPPORT_NI
+  #endif
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
+    #define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
+  #else
+    #define MEM_REC_NB_SUPPORT_PH
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
+    #define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
+  #else
+    #define MEM_REC_NB_SUPPORT_HY
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
+    #define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
+  #else
+    #define MEM_REC_NB_SUPPORT_C32
+  #endif
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockOr;
+    #define MEM_REC_NB_SUPPORT_OR MemRecConstructNBBlockOr,
+  #else
+    #define MEM_REC_NB_SUPPORT_OR
+  #endif
+
+  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
+    MEM_REC_NB_SUPPORT_DR
+    MEM_REC_NB_SUPPORT_RB
+    MEM_REC_NB_SUPPORT_DA
+    MEM_REC_NB_SUPPORT_PH
+    MEM_REC_NB_SUPPORT_HY
+    MEM_REC_NB_SUPPORT_C32
+    MEM_REC_NB_SUPPORT_OR
+    MEM_REC_NB_SUPPORT_NI
+    NULL
+  };
+
+  #define MEM_REC_TECH_CONSTRUCTOR_DDR2
+  #if (OPTION_DDR3 == TRUE)
+    extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
+  #else
+    #define MEM_REC_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+  MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
+    MEM_REC_TECH_CONSTRUCTOR_DDR3
+    MEM_REC_TECH_CONSTRUCTOR_DDR2
+    NULL
+  };
+
+  #if OPTION_MEMCTLR_DR
+    #define PSC_REC_DR_UDIMM_DDR2
+    #define PSC_REC_DR_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
+    #define PSC_REC_DR_RDIMM_DDR2
+    #define PSC_REC_DR_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
+    #define PSC_REC_DR_SODIMM_DDR2
+    #define PSC_REC_DR_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
+  #endif
+  #if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
+    #define PSC_REC_DA_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
+    #define PSC_REC_DA_SODIMM_DDR2
+    #define PSC_REC_DA_SODIMM_DDR3    MemRecNGetPsCfgSODIMM3Nb,
+  #endif
+  #if OPTION_MEMCTLR_HY
+    #define PSC_REC_HY_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
+    #define PSC_REC_HY_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
+  #endif
+  #if OPTION_MEMCTLR_C32
+    #define PSC_REC_C32_UDIMM_DDR3    MemRecNGetPsCfgUDIMM3Nb,
+    #define PSC_REC_C32_RDIMM_DDR3    MemRecNGetPsCfgRDIMM3Nb,
+  #endif
+  #if OPTION_MEMCTLR_OR
+    #define PSC_REC_OR_UDIMM_DDR3    //MemRecNGetPsCfgUDIMM3OR,
+    #define PSC_REC_OR_RDIMM_DDR3    //MemRecNGetPsCfgRDIMM3OR,
+  #endif
+
+  #ifndef PSC_REC_DR_UDIMM_DDR2
+    #define PSC_REC_DR_UDIMM_DDR2
+  #endif
+  #ifndef PSC_REC_DR_UDIMM_DDR3
+    #define PSC_REC_DR_UDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_DR_RDIMM_DDR2
+    #define PSC_REC_DR_RDIMM_DDR2
+  #endif
+  #ifndef PSC_REC_DR_RDIMM_DDR3
+    #define PSC_REC_DR_RDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_DR_SODIMM_DDR2
+    #define PSC_REC_DR_SODIMM_DDR2
+  #endif
+  #ifndef PSC_REC_DR_SODIMM_DDR3
+    #define PSC_REC_DR_SODIMM_DDR3
+  #endif
+  #ifndef PSC_REC_DA_UDIMM_DDR3
+    #define PSC_REC_DA_UDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_DA_SODIMM_DDR2
+    #define PSC_REC_DA_SODIMM_DDR2
+  #endif
+  #ifndef PSC_REC_DA_SODIMM_DDR3
+    #define PSC_REC_DA_SODIMM_DDR3
+  #endif
+  #ifndef PSC_REC_HY_UDIMM_DDR3
+    #define PSC_REC_HY_UDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_HY_RDIMM_DDR3
+    #define PSC_REC_HY_RDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_C32_UDIMM_DDR3
+    #define PSC_REC_C32_UDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_C32_RDIMM_DDR3
+    #define PSC_REC_C32_RDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_OR_UDIMM_DDR3
+    #define PSC_REC_OR_UDIMM_DDR3
+  #endif
+  #ifndef PSC_REC_OR_RDIMM_DDR3
+    #define PSC_REC_OR_RDIMM_DDR3
+  #endif
+
+  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
+    PSC_REC_DR_UDIMM_DDR2
+    PSC_REC_DR_RDIMM_DDR2
+    PSC_REC_DR_SODIMM_DDR2
+    PSC_REC_DR_UDIMM_DDR3
+    PSC_REC_DR_RDIMM_DDR3
+    PSC_REC_DR_SODIMM_DDR3
+    PSC_REC_DA_SODIMM_DDR2
+    PSC_REC_DA_UDIMM_DDR3
+    PSC_REC_DA_SODIMM_DDR3
+    PSC_REC_HY_UDIMM_DDR3
+    PSC_REC_HY_RDIMM_DDR3
+    PSC_REC_C32_UDIMM_DDR3
+    PSC_REC_C32_RDIMM_DDR3
+    PSC_REC_OR_UDIMM_DDR3
+    PSC_REC_OR_RDIMM_DDR3
+    NULL
+  };
+
+  /*---------------------------------------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_PSC_REC_FLOW_BLOCK_END NULL
+  #define PSC_REC_TBL_END NULL
+  #define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) MemRecDefTrue
+
+
+#else
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT TECHNOLOGY BLOCK
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {    // Types of technology installed
+    NULL
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * DEFAULT NORTHBRIDGE SUPPORT LIST
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
+    NULL
+  };
+  /*----------------------------------------------------------------------
+   * DEFAULT PSCFG DEFINITIONS
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
+    NULL
+  };
+  /*----------------------------------------------------------------------
+   * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
+   *
+   *----------------------------------------------------------------------
+   */
+  MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
+    NULL
+  };
+#endif
+#endif  // _OPTION_MEMORY_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h
new file mode 100644
index 0000000..a64321e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMsgBasedC1eInstall.h
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Message-Based C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
+#define _OPTION_MSG_BASED_C1E_INSTALL_H_
+
+#include "cpuMsgBasedC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_MSG_BASED_C1E_FEAT
+#define F10_MSG_BASED_C1E_SUPPORT
+#define F15_OR_MSG_BASED_C1E_SUPPORT
+#if OPTION_MSG_BASED_C1E == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
+
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
+            #undef OPTION_MSG_BASED_C1E_FEAT
+            #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
+          #endif
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
+          #undef OPTION_MSG_BASED_C1E_FEAT
+          #define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
+            extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
+            #undef F10_MSG_BASED_C1E_SUPPORT
+            #define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
+          #endif
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
+          extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e;
+          #undef F15_OR_MSG_BASED_C1E_SUPPORT
+          #define F15_OR_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15_OR, &F15OrMsgBasedC1e},
+        #endif
+      #endif
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
+    {
+      F10_MSG_BASED_C1E_SUPPORT
+      F15_OR_MSG_BASED_C1E_SUPPORT
+      {0, NULL}
+    };
+    CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
+    {
+      (sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+      &MsgBasedC1eFamilyServiceArray[0]
+    };
+  #endif
+#endif
+#endif  // _OPTION_MSG_BASED_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocket.h b/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocket.h
new file mode 100644
index 0000000..493e46e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocket.h
@@ -0,0 +1,214 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Multi-socket option API.
+ *
+ * Contains structures and values used to control the multi-socket option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 51891 $   @e \$Date: 2011-04-28 12:39:55 -0600 (Thu, 28 Apr 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MULTISOCKET_H_
+#define _OPTION_MULTISOCKET_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * This function loops through all possible socket locations, gathering the number
+ * of power management steps each populated socket requires, and returns the
+ * highest number.
+ *
+ * @param[out] NumSystemSteps    Maximum number of system steps required
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_PM_STEPS (
+     OUT   UINT8 *NumSystemSteps,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, starting core 0 of
+ * each populated socket to perform the passed in AP_TASK.  After starting all
+ * other core 0s, the BSC will perform the AP_TASK as well.  This must be run by
+ * the system BSC only.
+ *
+ * @param[in]  TaskPtr           Function descriptor
+ * @param[in]  StdHeader         Config handle for library and services
+ * @param[in]  ConfigParams      AMD entry point's CPU parameter structure
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
+  IN       VOID *TaskPtr,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       VOID *ConfigParams
+  );
+
+/**
+ * This function loops through all possible socket locations, comparing the
+ * maximum NB frequencies to determine the slowest.  This function also
+ * determines if all coherent NB frequencies are equivalent.
+ *
+ * @param[in]  NbPstate                    NB P-state number to check (0 = fastest)
+ * @param[in]  PlatformConfig              Platform profile/build option config structure.
+ * @param[out] SystemNbCofNumerator        NB frequency numerator for the system in MHz
+ * @param[out] SystemNbCofDenominator      NB frequency denominator for the system
+ * @param[out] SystemNbCofsMatch           Whether or not all NB frequencies are equivalent
+ * @param[out] NbPstateIsEnabledOnAllCPUs  Whether or not NbPstate is valid on all CPUs
+ * @param[in]  StdHeader                   Config handle for library and services
+ *
+ * @retval     TRUE                        At least one processor has NbPstate enabled.
+ * @retval     FALSE                       NbPstate is disabled on all CPUs
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
+  IN       UINT32 NbPstate,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32 *SystemNbCofNumerator,
+     OUT   UINT32 *SystemNbCofDenominator,
+     OUT   BOOLEAN *SystemNbCofsMatch,
+     OUT   BOOLEAN *NbPstateIsEnabledOnAllCPUs,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, checking whether
+ * any populated sockets require NB COF VID programming.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations, collecting any
+ * power management initialization errors that may have occurred.  These errors
+ * are transferred from the core 0s of the socket in which the errors occurred
+ * to the BSC's heap.  The BSC's heap is then searched for the most severe error
+ * that occurred, and returns it.  This function must be called by the BSC only.
+ *
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function loops through all possible socket locations and Nb Pstates,
+ * comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
+ * the system.
+ *
+ * @param[in]  PlatformConfig      Platform profile/build option config structure.
+ * @param[out] MinSysNbFreq        NB frequency numerator for the system in MHz
+ * @param[out] MinP0NbFreq         NB frequency numerator for P0 in MHz
+ * @param[in]  StdHeader           Config handle for library and services
+ */
+typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+     OUT   UINT32                 *MinSysNbFreq,
+     OUT   UINT32                 *MinP0NbFreq,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ * This function returns the current running core's PCI Config Space address.
+ *
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[in]    StdHeader    Header for library and services.
+ */
+typedef BOOLEAN OPTION_MULTISOCKET_GET_PCI_ADDRESS (
+     OUT   PCI_ADDR               *PciAddress,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/**
+ *  This function writes to all nodes on the executing core's socket.
+ *
+ *  @param[in]     PciAddress    The Function and Register to update
+ *  @param[in]     Mask          The bitwise AND mask to apply to the current register value
+ *  @param[in]     Data          The bitwise OR mask to apply to the current register value
+ *  @param[in]     StdHeader     Header for library and services.
+ *
+ */
+typedef VOID OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI (
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 Mask,
+  IN       UINT32                 Data,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+#define MULTISOCKET_STRUCT_VERSION  0x01
+
+/**
+ * Provide build configuration of cpu multi-socket or single socket support.
+ *
+ */
+typedef struct  {
+  UINT16              OptMultiSocketVersion;                       ///< Table version
+  OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps;           ///< Method: Get number of power mgt tasks
+  OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s;   ///< Method: Perform tasks on Core 0 of each processor
+  OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings;         ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate;    ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
+  OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors;  ///< Method: Gathers error information from all Core 0s.
+  OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof;                   ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS *GetCurrPciAddr;              ///< Method: Get PCI Config Space Address for the current running core.
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI *ModifyCurrSocketPci;  ///< Method: Writes to all nodes on the executing core's socket.
+} OPTION_MULTISOCKET_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_MULTISOCKET_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocketInstall.h
new file mode 100644
index 0000000..0f44278
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMultiSocketInstall.h
@@ -0,0 +1,105 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Multiple Socket Support
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 51891 $   @e \$Date: 2011-04-28 12:39:55 -0600 (Thu, 28 Apr 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MULTISOCKET_INSTALL_H_
+#define _OPTION_MULTISOCKET_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+#if OPTION_MULTISOCKET == TRUE
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrMulti
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sMulti
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
+  #define GET_SYS_NB_COF      GetSystemNbCofMulti
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
+  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
+  #define GET_MIN_NB_COF GetMinNbCofMulti
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrMulti;
+  #define GET_PCI_ADDRESS GetCurrPciAddrMulti
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti;
+  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciMulti
+#else
+  OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
+  #define GET_NUM_PM_STEPS    GetNumberOfSystemPmStepsPtrSingle
+  OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
+  #define CORE0_PM_TASK       RunCodeOnAllSystemCore0sSingle
+  OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
+  #define GET_SYS_NB_COF      GetSystemNbCofSingle
+  OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
+  #define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
+  OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
+  #define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
+  OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
+  #define GET_MIN_NB_COF GetMinNbCofSingle
+  OPTION_MULTISOCKET_GET_PCI_ADDRESS GetCurrPciAddrSingle;
+  #define GET_PCI_ADDRESS GetCurrPciAddrSingle
+  OPTION_MULTISOCKET_MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle;
+  #define MODIFY_CURR_SOCKET_PCI ModifyCurrSocketPciSingle
+#endif
+
+/*  Declare the instance of the multisocket option configuration structure  */
+OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
+  MULTISOCKET_STRUCT_VERSION,
+  GET_NUM_PM_STEPS,
+  CORE0_PM_TASK,
+  GET_SYS_NB_COF,
+  GET_SYS_NB_COF_UPDATE,
+  GET_EARLY_PM_ERRORS,
+  GET_MIN_NB_COF,
+  GET_PCI_ADDRESS,
+  MODIFY_CURR_SOCKET_PCI
+};
+
+#endif  // _OPTION_MULTISOCKET_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h
new file mode 100644
index 0000000..2b40f77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPreserveMailboxInstall.h
@@ -0,0 +1,123 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Preserve Mailbox
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
+
+#include "PreserveMailbox.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_PRESERVE_MAILBOX_FEAT
+#define F10_PRESERVE_MAILBOX_SUPPORT
+#define F15_PRESERVE_MAILBOX_SUPPORT
+
+#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
+  #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
+    #undef OPTION_PRESERVE_MAILBOX_FEAT
+    #define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
+  #endif
+  #if OPTION_FAMILY10H == TRUE
+    CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = {
+      {
+        {MAKE_SBDFO (0, 0, 0, 3, 0x168)},
+        0x00000FFF
+      },
+      {
+        {MAKE_SBDFO (0, 0, 0, 3, 0x170)},
+        0x00000FFF
+      },
+      {
+        {ILLEGAL_SBDFO},
+        0
+      }
+    };
+    CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
+      0,
+      TRUE,
+      (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters
+    };
+    #undef F10_PRESERVE_MAILBOX_SUPPORT
+    #define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
+  #endif
+  #if OPTION_FAMILY15H == TRUE
+    CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = {
+      {
+        {MAKE_SBDFO (0, 0, 0, 3, 0x168)},
+        0x00000FFF
+      },
+      {
+        {MAKE_SBDFO (0, 0, 0, 3, 0x170)},
+        0x00000FFF
+      },
+      {
+        {ILLEGAL_SBDFO},
+        0
+      }
+    };
+    CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
+      0,
+      TRUE,
+      (PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters
+    };
+    #undef F15_PRESERVE_MAILBOX_SUPPORT
+    #define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
+  {
+    F10_PRESERVE_MAILBOX_SUPPORT
+    F15_PRESERVE_MAILBOX_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
+  {
+    (sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &PreserveMailboxFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_PRESERVE_MAILBOX_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPstate.h b/src/vendorcode/amd/agesa/f15/Include/OptionPstate.h
new file mode 100644
index 0000000..018ddf9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPstate.h
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ACPI PState option API.
+ *
+ * Contains structures and values used to control the PStates option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_PSTATE_H_
+#define _OPTION_PSTATE_H_
+
+#include "cpuPstateTables.h"
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_SSDT_FEATURE (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **AcpiPstatePtr
+  );
+
+typedef UINT32 OPTION_ACPI_FEATURE (
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PSTATE_LEVELING        *PStateLevelingBuffer,
+  IN OUT   VOID                   **AcpiPStatePtr,
+  IN       UINT8                  LocalApicId,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_GATHER (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN OUT   S_CPU_AMD_PSTATE  *PStateStrucPtr
+  );
+
+typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
+  IN OUT   S_CPU_AMD_PSTATE   *PStateStrucPtr,
+  IN       AMD_CONFIG_PARAMS  *StdHeader
+  );
+
+#define PSTATE_STRUCT_VERSION  0x01
+
+/// Indirection vectors for POST/PEI PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_PSTATE_GATHER    *PstateGather;        ///< vector for data gathering routine
+  OPTION_PSTATE_LEVELING  *PstateLeveling;      ///< vector for leveling routine
+} OPTION_PSTATE_POST_CONFIGURATION;
+
+/// Indirection vectors for LATE/DXE PState code
+typedef struct  {
+  UINT16                  OptPstateVersion;     ///< revision of this structure
+  OPTION_SSDT_FEATURE     *SsdtFeature;         ///< vector for routine to generate SSDT
+  OPTION_ACPI_FEATURE     *PstateFeature;       ///< vector for routine to generate ACPI PState Objects
+  OPTION_ACPI_FEATURE     *CstateFeature;       ///< vector for routine to generate ACPI CState Objects
+  BOOLEAN                 CfgPstatePpc;         ///< boolean for creating _PPC method
+  BOOLEAN                 CfgPstatePct;         ///< boolean for creating _PCT method
+  BOOLEAN                 CfgPstatePsd;         ///< boolean for creating _PSD method
+  BOOLEAN                 CfgPstatePss;         ///< boolean for creating _PSS method
+  BOOLEAN                 CfgPstateXpss;        ///< boolean for creating _XPSS method
+} OPTION_PSTATE_LATE_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_PSTATE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h
new file mode 100644
index 0000000..061b6f5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPstateHpcModeInstall.h
@@ -0,0 +1,88 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Pstate HPC mode.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 52150 $   @e \$Date: 2011-05-03 01:01:08 -0600 (Tue, 03 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSTATE_HPC_MODE_INSTALL_H_
+#define _OPTION_PSTATE_HPC_MODE_INSTALL_H_
+
+#include "cpuPstateHpcMode.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_PSTATE_HPC_MODE_FEAT
+#define F15_PSTATE_HPC_MODE_SUPPORT
+
+#if OPTION_CPU_PSTATE_HPC_MODE == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        // Orochi and Komodo
+        #if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePstateHpcMode;
+          #undef OPTION_CPU_PSTATE_HPC_MODE_FEAT
+          #define OPTION_CPU_PSTATE_HPC_MODE_FEAT &CpuFeaturePstateHpcMode,
+          extern CONST PSTATE_HPC_MODE_FAMILY_SERVICES ROMDATA F15PstateHpcSupport;
+          #undef F15_PSTATE_HPC_MODE_SUPPORT
+          #define F15_PSTATE_HPC_MODE_SUPPORT {(AMD_FAMILY_15_OR | AMD_FAMILY_15_KM), &F15PstateHpcSupport},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateHpcModeFamilyServiceArray[] =
+{
+  F15_PSTATE_HPC_MODE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateHpcModeFamilyServiceTable =
+{
+  (sizeof (PstateHpcModeFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PstateHpcModeFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_PSTATE_HPC_MODE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h
new file mode 100644
index 0000000..8ca835c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionPstateInstall.h
@@ -0,0 +1,264 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: PState
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 52904 $   @e \$Date: 2011-05-12 16:42:35 -0600 (Thu, 12 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_PSTATE_INSTALL_H_
+#define _OPTION_PSTATE_INSTALL_H_
+
+#include "cpuPstateTables.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define F10_PSTATE_SERVICE_SUPPORT
+#define F12_PSTATE_SERVICE_SUPPORT
+#define F14_PSTATE_SERVICE_SUPPORT
+#define F15_OR_PSTATE_SERVICE_SUPPORT
+#define F15_TN_PSTATE_SERVICE_SUPPORT
+#define F15_KM_PSTATE_SERVICE_SUPPORT
+
+
+#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
+  //
+  //Define Pstate CPU Family service
+  //
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
+      #undef F10_PSTATE_SERVICE_SUPPORT
+      #define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY12H
+    #if OPTION_FAMILY12H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
+      #undef F12_PSTATE_SERVICE_SUPPORT
+      #define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY14H
+    #if OPTION_FAMILY14H == TRUE
+      extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
+      #undef F14_PSTATE_SERVICE_SUPPORT
+      #define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
+    #endif
+  #endif
+
+  #ifdef OPTION_FAMILY15H
+    #if OPTION_FAMILY15H == TRUE
+      #ifdef OPTION_FAMILY15H_OR
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices;
+          #undef F15_OR_PSTATE_SERVICE_SUPPORT
+          #define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices},
+        #endif
+      #endif
+      #ifdef OPTION_FAMILY15H_TN
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
+          #undef F15_TN_PSTATE_SERVICE_SUPPORT
+          #define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
+        #endif
+      #endif
+      #ifdef OPTION_FAMILY15H_KM
+        #if OPTION_FAMILY15H_KM == TRUE
+          extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15KmPstateServices;
+          #undef F15_KM_PSTATE_SERVICE_SUPPORT
+          #define F15_KM_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_KM, &F15KmPstateServices},
+        #endif
+      #endif
+    #endif
+  #endif
+  //
+  //Define ACPI Pstate objects.
+  //
+  #ifndef OPTION_ACPI_PSTATES
+    #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
+  #endif
+  #if (OPTION_ACPI_PSTATES == TRUE)
+    OPTION_SSDT_FEATURE               GenerateSsdt;
+    #define USER_SSDT_MAIN            GenerateSsdt
+    #ifndef OPTION_MULTISOCKET
+      #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+    #endif
+
+    OPTION_ACPI_FEATURE               CreatePStateAcpiTables;
+    OPTION_PSTATE_GATHER              PStateGatherMain;
+    #if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
+      OPTION_PSTATE_LEVELING          PStateLevelingMain;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingMain
+    #else
+      OPTION_PSTATE_LEVELING            PStateLevelingStub;
+      #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #endif
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      #define USER_PSTATE_OPTION_MAIN   CreatePStateAcpiTables
+    #else
+      OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+      #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #endif
+    #if AGESA_ENTRY_INIT_POST == TRUE
+      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
+    #else
+      OPTION_PSTATE_GATHER              PStateGatherStub;
+      #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #endif
+    #if CFG_ACPI_PSTATES_PPC == TRUE
+      #define USER_PSTATE_CFG_PPC   TRUE
+    #else
+      #define USER_PSTATE_CFG_PPC   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PCT == TRUE
+      #define USER_PSTATE_CFG_PCT   TRUE
+    #else
+      #define USER_PSTATE_CFG_PCT   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSD == TRUE
+      #define USER_PSTATE_CFG_PSD   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSD   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_PSS == TRUE
+      #define USER_PSTATE_CFG_PSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_PSS   FALSE
+    #endif
+    #if CFG_ACPI_PSTATES_XPSS == TRUE
+      #define USER_PSTATE_CFG_XPSS   TRUE
+    #else
+      #define USER_PSTATE_CFG_XPSS   FALSE
+    #endif
+
+    #if OPTION_IO_CSTATE == TRUE
+      OPTION_ACPI_FEATURE             CreateCStateAcpiTables;
+      #define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
+    #else
+      OPTION_ACPI_FEATURE             CreateAcpiTablesStub;
+      #define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
+    #endif
+  #else
+    OPTION_SSDT_FEATURE               GenerateSsdtStub;
+    OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+    OPTION_PSTATE_GATHER              PStateGatherStub;
+    OPTION_PSTATE_LEVELING            PStateLevelingStub;
+    #define USER_SSDT_MAIN            GenerateSsdtStub
+    #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
+    #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+    #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+    #define USER_PSTATE_CFG_PPC    FALSE
+    #define USER_PSTATE_CFG_PCT    FALSE
+    #define USER_PSTATE_CFG_PSD    FALSE
+    #define USER_PSTATE_CFG_PSS    FALSE
+    #define USER_PSTATE_CFG_XPSS   FALSE
+
+    // If ACPI Objects are disabled for PStates, we still need to check
+    // whether ACPI Objects are enabled for CStates
+    #if OPTION_IO_CSTATE == TRUE
+      OPTION_SSDT_FEATURE               GenerateSsdt;
+      OPTION_PSTATE_GATHER              PStateGatherMain;
+      OPTION_ACPI_FEATURE               CreateCStateAcpiTables;
+      #undef  USER_SSDT_MAIN
+      #define USER_SSDT_MAIN            GenerateSsdt
+      #undef  USER_PSTATE_OPTION_GATHER
+      #define USER_PSTATE_OPTION_GATHER PStateGatherMain
+      #undef  USER_CSTATE_OPTION_MAIN
+      #define USER_CSTATE_OPTION_MAIN   CreateCStateAcpiTables
+    #endif
+  #endif
+#else
+  OPTION_SSDT_FEATURE               GenerateSsdtStub;
+  OPTION_ACPI_FEATURE               CreateAcpiTablesStub;
+  OPTION_PSTATE_GATHER              PStateGatherStub;
+  OPTION_PSTATE_LEVELING            PStateLevelingStub;
+  #define USER_SSDT_MAIN            GenerateSsdtStub
+  #define USER_PSTATE_OPTION_MAIN   CreateAcpiTablesStub
+  #define USER_CSTATE_OPTION_MAIN   CreateAcpiTablesStub
+  #define USER_PSTATE_OPTION_GATHER PStateGatherStub
+  #define USER_PSTATE_OPTION_LEVEL  PStateLevelingStub
+  #define USER_PSTATE_CFG_PPC    FALSE
+  #define USER_PSTATE_CFG_PCT    FALSE
+  #define USER_PSTATE_CFG_PSD    FALSE
+  #define USER_PSTATE_CFG_PSS    FALSE
+  #define USER_PSTATE_CFG_XPSS   FALSE
+#endif
+
+/*  Declare the instance of the PSTATE option configuration structure  */
+OPTION_PSTATE_POST_CONFIGURATION      OptionPstatePostConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_PSTATE_OPTION_GATHER,
+  USER_PSTATE_OPTION_LEVEL
+};
+
+OPTION_PSTATE_LATE_CONFIGURATION      OptionPstateLateConfiguration = {
+  PSTATE_STRUCT_VERSION,
+  USER_SSDT_MAIN,
+  USER_PSTATE_OPTION_MAIN,
+  USER_CSTATE_OPTION_MAIN,
+  USER_PSTATE_CFG_PPC,
+  USER_PSTATE_CFG_PCT,
+  USER_PSTATE_CFG_PSD,
+  USER_PSTATE_CFG_PSS,
+  USER_PSTATE_CFG_XPSS
+};
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
+{
+  F10_PSTATE_SERVICE_SUPPORT
+  F12_PSTATE_SERVICE_SUPPORT
+  F14_PSTATE_SERVICE_SUPPORT
+  F15_OR_PSTATE_SERVICE_SUPPORT
+  F15_TN_PSTATE_SERVICE_SUPPORT
+  F15_KM_PSTATE_SERVICE_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
+{
+  (sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &PstateCpuFamilyServiceArray[0]
+};
+#endif  // _OPTION_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionS3ScriptInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionS3ScriptInstall.h
new file mode 100644
index 0000000..9036235
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionS3ScriptInstall.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: S3SCRIPT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_S3SCRIPT_INSTALL_H_
+#define _OPTION_S3SCRIPT_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#ifndef OPTION_S3SCRIPT
+  #define OPTION_S3SCRIPT  FALSE    //if not define assume PI not use script
+#endif
+
+#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_INIT      S3ScriptInitState
+  #endif
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+  #if OPTION_S3SCRIPT == TRUE
+    #define P_S3_SCRIPT_RESTORE   S3ScriptRestoreState
+  #endif
+#endif
+
+#ifndef P_S3_SCRIPT_INIT
+  #define P_S3_SCRIPT_INIT        S3ScriptInitStateStub
+#endif
+
+#ifndef P_S3_SCRIPT_RESTORE
+  #define P_S3_SCRIPT_RESTORE     S3ScriptInitStateStub
+  #undef  GNB_S3_DISPATCH_FUNCTION_TABLE
+#endif
+
+#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
+  #define GNB_S3_DISPATCH_FUNCTION_TABLE
+#endif
+
+/*  Declare the instance of the S3SCRIPT option configuration structure  */
+S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
+  P_S3_SCRIPT_INIT,
+  P_S3_SCRIPT_RESTORE
+};
+
+S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
+  GNB_S3_DISPATCH_FUNCTION_TABLE
+  {0, NULL}
+};
+#endif  // _OPTION_S3SCRIPT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionSlit.h b/src/vendorcode/amd/agesa/f15/Include/OptionSlit.h
new file mode 100644
index 0000000..6e77ac4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionSlit.h
@@ -0,0 +1,97 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SLIT option API.
+ *
+ * Contains structures and values used to control the SLIT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SLIT_H_
+#define _OPTION_SLIT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Create the ACPI System Locality Distance Information Table.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN OUT   VOID                   **SlitPtr
+  );
+
+/**
+ * Clean up DRAM used during SLIT creation.
+ *
+ */
+typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define SLIT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SLIT
+typedef struct  {
+  UINT16              OptSlitVersion;       ///< The version number of SLIT
+  OPTION_SLIT_FEATURE  *SlitFeature;        ///< The Option Feature of SLIT
+  OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
+} OPTION_SLIT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SLIT_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionSlitInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionSlitInstall.h
new file mode 100644
index 0000000..b98d181
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionSlitInstall.h
@@ -0,0 +1,80 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: SLIT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SLIT_INSTALL_H_
+#define _OPTION_SLIT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SLIT
+    #error  BLDOPT: Option not defined: "OPTION_SLIT"
+  #endif
+  #if OPTION_SLIT == TRUE
+    OPTION_SLIT_FEATURE               GetAcpiSlitMain;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBuffer;
+    #define USER_SLIT_OPTION     GetAcpiSlitMain
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
+  #else
+    OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+    OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+    #define USER_SLIT_OPTION     GetAcpiSlitStub
+    #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+  #endif
+#else
+  OPTION_SLIT_FEATURE               GetAcpiSlitStub;
+  OPTION_SLIT_RELEASE_BUFFER   ReleaseSlitBufferStub;
+  #define USER_SLIT_OPTION     GetAcpiSlitStub
+  #define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
+#endif
+/*  Declare the instance of the SLIT option configuration structure  */
+OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
+  SLIT_STRUCT_VERSION,
+  USER_SLIT_OPTION,
+  USER_SLIT_RELEASE_BUFFER
+};
+
+#endif  // _OPTION_SLIT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionSrat.h b/src/vendorcode/amd/agesa/f15/Include/OptionSrat.h
new file mode 100644
index 0000000..987d051
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionSrat.h
@@ -0,0 +1,83 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD SRAT option API.
+ *
+ * Contains structures and values used to control the SRAT option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_SRAT_H_
+#define _OPTION_SRAT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_SRAT_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader,
+  IN OUT   VOID                  **SratPtr
+  );
+
+#define SRAT_STRUCT_VERSION  0x01
+
+/// The Option Configuration of SRAT
+typedef struct  {
+  UINT16              OptSratVersion;       ///< The version number of SRAT
+  OPTION_SRAT_FEATURE  *SratFeature;        ///< The Option Feature of SRAT
+} OPTION_SRAT_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_SRAT_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionSratInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionSratInstall.h
new file mode 100644
index 0000000..aa3323f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionSratInstall.h
@@ -0,0 +1,74 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: SRAT
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SRAT_INSTALL_H_
+#define _OPTION_SRAT_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_SRAT
+    #error  BLDOPT: Option not defined: "OPTION_SRAT"
+  #endif
+  #if OPTION_SRAT == TRUE
+    OPTION_SRAT_FEATURE          GetAcpiSratMain;
+    #define USER_SRAT_OPTION     GetAcpiSratMain
+  #else
+    OPTION_SRAT_FEATURE          GetAcpiSratStub;
+    #define USER_SRAT_OPTION     GetAcpiSratStub
+  #endif
+#else
+  OPTION_SRAT_FEATURE            GetAcpiSratStub;
+  #define USER_SRAT_OPTION       GetAcpiSratStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
+  SRAT_STRUCT_VERSION,
+  USER_SRAT_OPTION
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionSwC1eInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionSwC1eInstall.h
new file mode 100644
index 0000000..74967e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionSwC1eInstall.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: SW C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_SW_C1E_INSTALL_H_
+#define _OPTION_SW_C1E_INSTALL_H_
+
+#include "cpuSwC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_SW_C1E_FEAT
+#define F10_SW_C1E_SUPPORT
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
+        #undef OPTION_SW_C1E_FEAT
+        #define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
+        extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
+        #undef F10_SW_C1E_SUPPORT
+        #define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
+      #endif
+    #endif
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
+  {
+    F10_SW_C1E_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
+  {
+    (sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &SwC1eFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_SW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionWhea.h b/src/vendorcode/amd/agesa/f15/Include/OptionWhea.h
new file mode 100644
index 0000000..0ae3447
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionWhea.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD WHEA option API.
+ *
+ * Contains structures and values used to control the WHEA option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_WHEA_H_
+#define _OPTION_WHEA_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_WHEA_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   VOID                 **WheaMcePtr,
+  IN OUT   VOID                 **WheaCmcPtr
+  );
+
+#define WHEA_STRUCT_VERSION  0x01
+
+/// The Option Configuration of WHEA
+typedef struct  {
+  UINT16              OptWheaVersion;       ///< The version number of WHEA
+  OPTION_WHEA_FEATURE  *WheaFeature;        ///< The Option Feature of WHEA
+} OPTION_WHEA_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_WHEA_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionWheaInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionWheaInstall.h
new file mode 100644
index 0000000..a7f388c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionWheaInstall.h
@@ -0,0 +1,75 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: WHEA
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_WHEA_INSTALL_H_
+#define _OPTION_WHEA_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_WHEA
+    #error  BLDOPT: Option not defined: "OPTION_WHEA"
+  #endif
+  #if OPTION_WHEA == TRUE
+    OPTION_WHEA_FEATURE          GetAcpiWheaMain;
+    #define USER_WHEA_OPTION     GetAcpiWheaMain
+  #else
+    OPTION_WHEA_FEATURE          GetAcpiWheaStub;
+    #define USER_WHEA_OPTION     GetAcpiWheaStub
+  #endif
+
+#else
+  OPTION_WHEA_FEATURE            GetAcpiWheaStub;
+  #define USER_WHEA_OPTION       GetAcpiWheaStub
+#endif
+
+/*  Declare the instance of the WHEA option configuration structure  */
+OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
+  WHEA_STRUCT_VERSION,
+  USER_WHEA_OPTION
+};
+
+#endif  // _OPTION_WHEA_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/Options.h b/src/vendorcode/amd/agesa/f15/Include/Options.h
new file mode 100644
index 0000000..abb4a76
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Options.h
@@ -0,0 +1,98 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 53142 $   @e \$Date: 2011-05-16 12:01:19 -0600 (Mon, 16 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+  UINT32              PlatformNumberOfSockets;                  ///< The limit to the number of processors based on
+                                                                ///< supported families and other build options.
+  UINT32              PlatformNumberOfModules;                  ///< The limit to the number of modules in a processor, based
+                                                                ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+  UINT32              FunctionId;                   ///< The function id specified.
+  IMAGE_ENTRY         EntryPoint;                   ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (BLDCFG_PLATFORM_POWER_POLICY_MODE)
+#else
+  #define CFG_PLATFORM_POWER_POLICY_MODE  (Performance)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_BASE
+  #define CFG_PCI_MMIO_BASE               (BLDCFG_PCI_MMIO_BASE)
+#else
+  #define CFG_PCI_MMIO_BASE               (0)
+#endif
+
+#ifdef BLDCFG_PCI_MMIO_SIZE
+  #define CFG_PCI_MMIO_SIZE               (BLDCFG_PCI_MMIO_SIZE)
+#else
+  #define CFG_PCI_MMIO_SIZE               (0)
+#endif
+
+#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
+  #define CFG_AP_MTRR_SETTINGS_LIST           (BLDCFG_AP_MTRR_SETTINGS_LIST)
+#else
+  #define CFG_AP_MTRR_SETTINGS_LIST           (NULL)
+#endif
+
+#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
+  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
+#else
+  #define CFG_IOMMU_EXCLUSION_RANGE_LIST      (NULL)
+#endif
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionsHt.h b/src/vendorcode/amd/agesa/f15/Include/OptionsHt.h
new file mode 100644
index 0000000..ddcc024
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionsHt.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD HyperTransport option API.
+ *
+ * Contains option pre-compile logic.  This file is used by the options
+ * installer and internally by the HT code initializers.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_HT_H_
+#define _OPTION_HT_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Provide HT build option results
+ */
+typedef struct {
+  CONST BOOLEAN IsUsingRecoveryHt;                   ///< Manual BUID Swap List processing should assume that HT Recovery was used.
+  CONST BOOLEAN IsSetHtCrcFlood;                     ///< Enable setting of HT CRC Flood.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
+  CONST BOOLEAN IsUsingUnitIdClumping;               ///< Enable automatically HT Spec compliant Unit Id Clumping.
+                                                     ///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
+  CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults;  ///< A set of build time options for HT constructor.
+  CONST VOID *HtOptionInternalInterface;             ///< Use this internal interface initializer.
+  CONST VOID *HtOptionInternalFeatures;              ///< Use this internal feature set initializer.
+  CONST VOID *HtOptionFamilyNorthbridgeList;         ///< Use this list of northbridge initializers.
+  CONST UINT8 *CONST *HtOptionBuiltinTopologies;     ///< Use this list of built-in topologies.
+} OPTION_HT_CONFIGURATION;
+
+typedef AGESA_STATUS
+F_OPTION_HT_INIT_RESET (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
+
+typedef AGESA_STATUS
+F_OPTION_HT_RESET_CONSTRUCTOR (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
+
+/**
+ * Provide HT reset initialization build option results
+ */
+typedef struct {
+  PF_OPTION_HT_INIT_RESET HtInitReset;               ///< Method: HT reset initialization.
+  PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
+} OPTION_HT_INIT_RESET;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_HT_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionsPage.h b/src/vendorcode/amd/agesa/f15/Include/OptionsPage.h
new file mode 100644
index 0000000..0cb1567
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionsPage.h
@@ -0,0 +1,378 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for Build Configuration and Options Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 52274 $   @e \$Date: 2011-05-04 01:00:15 -0600 (Wed, 04 May 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/**
+ * @page optionmain Build Configuration and Options Documentation
+ *
+ * Additional documentation for the Build Configuration and Options component consists of
+ *
+ * - Introduction and Overview to Build Options
+ *   - @subpage platforminstall "Platform Build Options"
+ *   - @subpage bldcfg "Build Configuration Item Cross Reference"
+ *   - @subpage examplecustomizations "Customization Examples"
+ * - Maintenance Guides:
+ *   -  For debug of the Options system, use compiler options
+ *      @n <tt>      /P /EP /C /FAs      </tt> @n
+ *      PreProcessor output is produced in an .i file in the directory where the project
+ *      file is located.
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+/**
+ * @page platforminstall Platform Build Options.
+ *
+ * Build options are boolean constants. The purpose of build options is to remove code
+ * from the build to reduce the overall code size present in the ROM image. Unless
+ * otherwise specified, the default action is to include all options. If a build option is
+ * not specifically listed as disabled, then it is included into the build.
+ *
+ * The documented build options are imported from a user controlled file for
+ * processing. The build options for all platform solutions are listed below:
+ *
+ * @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
+ * @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
+ *        If unbuffered DIMMs are NOT expected to be required in the system, the code that
+ *        handles unbuffered DIMMs can be removed from the build.
+ *
+ * @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
+ * @li @e  BLDOPT_REMOVE_RDIMMS_SUPPORT @n
+ *         If registered DIMMs are NOT expected to be required in the system, the code
+ *         that handles registered DIMMs can be removed from the build.
+ *
+  * @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
+ * @li @e  BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
+ *         If Load Reduced DIMMs are NOT expected to be required in the system, the code
+ *         that handles Load Reduced DIMMs can be removed from the build.
+ *
+ *     @note The above three options operate independently from each other; however, at
+ *     least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
+ *
+ * @anchor BLDOPT_REMOVE_ECC_SUPPORT
+ * @li @e  BLDOPT_REMOVE_ECC_SUPPORT @n
+ *         Use this option to remove the code for Error Checking & Correction.
+ *
+ * @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_BANK_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory between banks on a DIMM.
+ *
+ * @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_DCT_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory from two DRAM controllers.
+ *
+ * @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
+ * @li @e  BLDOPT_REMOVE_NODE_INTERLEAVE @n
+ *         Interleaving is a mechanism to do performance fine tuning. This option
+ *         interleaves memory from two HyperTransport nodes.
+ *
+ * @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
+ * @li @e  BLDOPT_REMOVE_PARALLEL_TRAINING @n
+ *         For multi-socket systems, training memory in parallel can reduce the time
+ *         needed to boot.
+ *
+ * @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+ * @li @e  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
+ *         Online Spare support is removed by this option.
+ *
+ * @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+ * @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
+ *        Many systems use only a single socket and may benefit in code space to remove
+ *        this code. However, certain processors have multiple HyperTransport nodes
+ *        within a single socket. For these processors, the multi-node support is
+ *        required and this option has no effect.
+ *
+ * @anchor BLDOPT_REMOVE_ACPI_PSTATES
+ * @li @e  BLDOPT_REMOVE_ACPI_PSTATES @n
+ *         This option removes the code that generates the ACPI tables used in power
+ *         management.
+ *
+ * @anchor BLDCFG_PSTATE_HPC_MODE
+ * @li @e  BLDCFG_PSTATE_HPC_MODE @n
+ *         This option enables PStates high performance computing mode (HPC mode)
+ *
+ * @anchor BLDOPT_REMOVE_SRAT
+ * @li @e  BLDOPT_REMOVE_SRAT @n
+ *         This option removes the code that generates the SRAT tables used in performance
+ *         tuning.
+ *
+ * @anchor BLDOPT_REMOVE_SLIT
+ * @li @e  BLDOPT_REMOVE_SLIT @n
+ *         This option removes the code that generates the SLIT tables used in performance
+ *         tuning.
+ *
+ * @anchor BLDOPT_REMOVE_WHEA
+ * @li @e  BLDOPT_REMOVE_WHEA @n
+ *         This option removes the code that generates the WHEA tables used in error
+ *         handling and reporting.
+ *
+ * @anchor BLDOPT_REMOVE_DMI
+ * @li @e  BLDOPT_REMOVE_DMI @n
+ *         This option removes the code that generates the DMI tables used in system
+ *         management.
+ *
+ * @anchor BLDOPT_REMOVE_DQS_TRAINING
+ * @li @e  BLDOPT_REMOVE_DQS_TRAINING @n
+ *         This option removes the code used in memory performance tuning.
+ *
+ * @anchor BLDOPT_REMOVE_EARLY_SAMPLES
+ * @li @e  BLDOPT_REMOVE_EARLY_SAMPLES @n
+ *         Special support for Early Samples is included. Default setting is FALSE.
+ *
+ * @anchor BLDOPT_REMOVE_HT_ASSIST
+ * @li @e  BLDOPT_REMOVE_HT_ASSIST @n
+ *         This option removes the code which implements the HT Assist feature.
+ *
+ * @anchor BLDOPT_REMOVE_ATM_MODE
+ * @li @e  BLDOPT_REMOVE_ATM_MODE @n
+ *         This option removes the code which implements the ATM feature.
+ *
+ * @anchor BLDOPT_REMOVE_MSG_BASED_C1E
+ * @li @e  BLDOPT_REMOVE_MSG_BASED_C1E @n
+ *         This option removes the code which implements the Message Based C1e feature.
+ *
+ * @anchor BLDOPT_REMOVE_C6_STATE
+ * @li @e  BLDOPT_REMOVE_C6_STATE @n
+ *         This option removes the code which implements the C6 C-state feature.
+ *
+ * @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+ * @li @e  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
+ *         This option removes the memory context restore feature.
+ *
+ * @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
+ *         If the package contains support for family 10h processors, remove that support.
+ *
+ * @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
+ *         If the package contains support for family 10h processors, remove that support.
+ *
+ * @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
+ *         If the package contains support for family 14h processors, remove that support.
+ *
+ * @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
+ *         If the package contains support for family 15h processors, remove that support.
+ *
+ * @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for AM3 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for ASB2 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for C32 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for FM1 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for FP1 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for FS1 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for FT1 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for G34 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for S1G3 sockets.
+ *
+ * @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
+ * @li @e  BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
+ *         This option removes the code which implements support for processors packaged for S1G4 sockets.
+ */
+
+/**
+ * @page examplecustomizations Customization Examples
+ *
+ * The Addendum \<plat\>Options.c file for each platform contains the minimum required
+ * customizations for that platform.  That is, it contains settings which would be needed
+ * to boot a SimNow! bsd for that platform.
+ * However, each individual product based on that platform will have customizations necessary for
+ * that hardware.  Since the actual customizations needed vary so much, they are not included in
+ * the \<plat\>Options.c.  This section provides examples of useful customizations that you can use or
+ * modify to suit your needs.
+ *
+ * @par
+ *
+ * Source for the examples shown can be found at Addendum\\Examples. @n
+ *
+ * - @ref DeemphasisExamples "Deemphasis List Examples"
+ * - @ref FrequencyLimitExamples "Frequency Limit Examples"
+ * - @ref PerfPerWattHt "A performance-per-watt optimization Example"
+ *
+ * @anchor DeemphasisExamples
+ * @par Deemphasis List Examples
+ *
+ * These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
+ * Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
+ * @dontinclude DeemphasisExamples.c
+ * <ul>
+ * <li>
+ *  The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
+ *  High Speed HT frequencies are supported.  There is only one non-coherent chain.  Note the technique of
+ *  putting specified link matches before all uses of match any.  It often works well to specify the non-coherent links
+ *  and use match any for the coherent links.
+ *  @skip DinarDeemphasisList
+ *  @until {
+ *  The non-coherent chain can run up to 2600 MHz.  The chain is located on Socket 0, package Link 2.
+ *  @until {
+ *  @line }
+ *  @line {
+ *  @line }
+ *  The coherent links can run up to 3200 MHz.
+ *  @until HT_FREQUENCY_MAX
+ *  @line }
+ *  end of list:
+ *  @until }
+ *  Make this list the build time customized deemphasis list.
+ *  @line define
+ *
+ * </li><li>
+ *
+ * The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
+ * This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
+ * There can be one to four IO Chains, depending on the IO board.
+ * @skipline DoubloonDeemphasisList
+ * @until DoubloonDeemphasisList
+ *
+ * </li><li>
+ *
+ * The following deemphasis list further illustrates complex coherent system deemphasis.  This is the same
+ * Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
+ * might be needed if each link has unique characterization).  For this example, we skip the non-coherent chains.
+ * (A real system would have to include them, see example above.)
+ *  @skip DinarPerLinkDeemphasisList
+ *  @until {
+ *  Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
+ *  Provide entries to customize all HT3 frequencies at which the links may run.  This example covers all HT3 speeds.
+ *  @until {
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  Link 3 on both sockets connects different internal die:  sublink 0 connects the internal node zeroes, and
+ *  sublink 1 connects the internal node ones.  So the link is unganged and both sublinks must be specifically
+ *  customized.
+ *  @until {
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  @until DcvLevelMinus6
+ *  end of list:
+ *  @until define
+ *
+ * </ul>
+ *
+ * @anchor FrequencyLimitExamples
+ * @par Frequency Limit Examples
+ *
+ * These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
+ * Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
+ * @dontinclude FrequencyLimitExamples.c
+ * <ul>
+ * <li>
+ *    The following list provides an example for limiting all coherent links to non-extended frequencies,
+ * that is, to 2600 MHz or less.
+ * @skipline NonExtendedCpuToCpuLimitList
+ * @until {
+ *   Provide the limit customization.  Match links from any socket, any package link, to any socket, any package link. Width is not limited.
+ * @until HT_FREQUENCY_LIMIT_2600M
+ * End of list:
+ * @until ;
+ * Customize the build to use this cpu to cpu frequency limit.
+ * @until NonExtendedCpuToCpuLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all coherent links to HT 1 frequencies,
+ * that is, to 1000 MHz or less.  This is sometimes useful for test and debug.
+ * @skipline Ht1CpuToCpuLimitList
+ * @until Ht1CpuToCpuLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
+ *    The chain is matched by host processor Socket and package Link.  The depth can be used to select a particular device
+ *    to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
+ * @skipline No2600MhzIoLimitList
+ * @until No2600MhzIoLimitList
+ * @n </li>
+ * <li>
+ *    The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
+ * that is, to 1200 MHz or less.  This can be useful for test and debug.
+ * @skipline MinHt3IoLimitList
+ * @until MinHt3IoLimitList
+ * @n </li>
+ *
+ * </ul>
+ *
+ * @anchor PerfPerWattHt
+ * @par Performance-per-Watt Optimization Example
+ *
+ * This example customizes AMD_HT_INTERFACE.SkipRegangList.
+ * Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
+ * @dontinclude PerfPerWatt.c
+ * To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
+ * @skipline PerfPerWatt
+ * @until PerfPerWatt
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
new file mode 100644
index 0000000..38ec4ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h
@@ -0,0 +1,2837 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a combination of package type, processor, and features.
+ *
+ * This file generates the defaults tables for the all platform solution
+ * combinations.  The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 60740 $   @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*****************************************************************************
+ *
+ * Start processing the user options:  First, set default settings
+ *
+ ****************************************************************************/
+
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.  Turn these on in your option c file, not
+ * here.
+ */
+// #define AGESA_ENTRY_INIT_RESET                    TRUE
+// #define AGESA_ENTRY_INIT_RECOVERY                 TRUE
+// #define AGESA_ENTRY_INIT_EARLY                    TRUE
+// #define AGESA_ENTRY_INIT_POST                     TRUE
+// #define AGESA_ENTRY_INIT_ENV                      TRUE
+// #define AGESA_ENTRY_INIT_MID                      TRUE
+// #define AGESA_ENTRY_INIT_LATE                     TRUE
+// #define AGESA_ENTRY_INIT_S3SAVE                   TRUE
+// #define AGESA_ENTRY_INIT_RESUME                   TRUE
+// #define AGESA_ENTRY_INIT_LATE_RESTORE             TRUE
+// #define AGESA_ENTRY_INIT_GENERAL_SERVICES         TRUE
+
+/*  Defaults for private/internal build control settings  */
+/* Available options for image builds.
+ *
+ * As part of the image build for each image, define the options below to select the
+ * AGESA entry points included in that image.
+ */
+
+VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+  //ModuleHeaderSignature
+  // Remove 'DOM$' as temp solution before update BinUtil.exe ,
+  Int32FromChar ('0', '0', '0', '0'),
+  //ModuleIdentifier[8]
+  AGESA_ID,
+  //ModuleVersion[12]
+  AGESA_VERSION_STRING,
+  //ModuleDispatcher
+  NULL,//(VOID *)(UINT64)((MODULE_ENTRY)AmdAgesaDispatcher),
+  //NextBlock
+  NULL
+};
+
+/*  Process user desired AGESA entry points  */
+#ifndef AGESA_ENTRY_INIT_RESET
+  #define AGESA_ENTRY_INIT_RESET                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RECOVERY
+  #define AGESA_ENTRY_INIT_RECOVERY                  FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_EARLY
+  #define AGESA_ENTRY_INIT_EARLY                     FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_POST
+  #define AGESA_ENTRY_INIT_POST                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_ENV
+  #define AGESA_ENTRY_INIT_ENV                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_MID
+  #define AGESA_ENTRY_INIT_MID                       FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE
+  #define AGESA_ENTRY_INIT_LATE                      FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_S3SAVE
+  #define AGESA_ENTRY_INIT_S3SAVE                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_RESUME
+  #define AGESA_ENTRY_INIT_RESUME                    FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_LATE_RESTORE
+  #define AGESA_ENTRY_INIT_LATE_RESTORE              FALSE
+#endif
+
+#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
+  #define AGESA_ENTRY_INIT_GENERAL_SERVICES          FALSE
+#endif
+
+/*  Default the late AP entry point to off.  It can be enabled
+    by any family that may need the late AP functionality, or
+    by any feature code that may need it.  The IBVs no longer
+    have control over this entry point.  */
+#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
+  #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+#endif
+#define AGESA_ENTRY_LATE_RUN_AP_TASK    FALSE
+
+
+
+/* Process solution defined socket / family installations
+ *
+ * As part of the release package for each image, define the options below to select the
+ * AGESA processor support included in that image.
+ */
+
+/*  Default sockets to off  */
+#define OPTION_G34_SOCKET_SUPPORT    FALSE
+#define OPTION_C32_SOCKET_SUPPORT    FALSE
+#define OPTION_G2012_SOCKET_SUPPORT  FALSE
+#define OPTION_C2012_SOCKET_SUPPORT  FALSE
+#define OPTION_S1G3_SOCKET_SUPPORT   FALSE
+#define OPTION_S1G4_SOCKET_SUPPORT   FALSE
+#define OPTION_ASB2_SOCKET_SUPPORT   FALSE
+#define OPTION_FS1_SOCKET_SUPPORT    FALSE
+#define OPTION_FM1_SOCKET_SUPPORT    FALSE
+#define OPTION_FM2_SOCKET_SUPPORT    FALSE
+#define OPTION_FP1_SOCKET_SUPPORT    FALSE
+#define OPTION_FP2_SOCKET_SUPPORT    FALSE
+#define OPTION_FT1_SOCKET_SUPPORT    FALSE
+#define OPTION_FT2_SOCKET_SUPPORT    FALSE
+#define OPTION_AM3_SOCKET_SUPPORT    FALSE
+
+/*  Default families to off  */
+#define OPTION_FAMILY10H             FALSE
+#define OPTION_FAMILY12H             FALSE
+#define OPTION_FAMILY14H             FALSE
+#define OPTION_FAMILY15H             FALSE
+#define OPTION_FAMILY15H_MODEL_0x    FALSE
+#define OPTION_FAMILY15H_MODEL_1x    FALSE
+#define OPTION_FAMILY15H_MODEL_2x    FALSE
+
+
+/*  Enable the appropriate socket support  */
+#ifdef INSTALL_G34_SOCKET_SUPPORT
+  #if  INSTALL_G34_SOCKET_SUPPORT == TRUE
+    #undef OPTION_G34_SOCKET_SUPPORT
+    #define OPTION_G34_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_C32_SOCKET_SUPPORT
+  #if  INSTALL_C32_SOCKET_SUPPORT == TRUE
+    #undef OPTION_C32_SOCKET_SUPPORT
+    #define OPTION_C32_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_G2012_SOCKET_SUPPORT
+  #if  INSTALL_G2012_SOCKET_SUPPORT == TRUE
+    #undef OPTION_G2012_SOCKET_SUPPORT
+    #define OPTION_G2012_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_C2012_SOCKET_SUPPORT
+  #if  INSTALL_C2012_SOCKET_SUPPORT == TRUE
+    #undef OPTION_C2012_SOCKET_SUPPORT
+    #define OPTION_C2012_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_S1G3_SOCKET_SUPPORT
+  #if  INSTALL_S1G3_SOCKET_SUPPORT == TRUE
+    #undef OPTION_S1G3_SOCKET_SUPPORT
+    #define OPTION_S1G3_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_S1G4_SOCKET_SUPPORT
+  #if  INSTALL_S1G4_SOCKET_SUPPORT == TRUE
+    #undef OPTION_S1G4_SOCKET_SUPPORT
+    #define OPTION_S1G4_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_ASB2_SOCKET_SUPPORT
+  #if  INSTALL_ASB2_SOCKET_SUPPORT == TRUE
+    #undef OPTION_ASB2_SOCKET_SUPPORT
+    #define OPTION_ASB2_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FS1_SOCKET_SUPPORT
+  #if  INSTALL_FS1_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FS1_SOCKET_SUPPORT
+    #define OPTION_FS1_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FM1_SOCKET_SUPPORT
+  #if  INSTALL_FM1_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FM1_SOCKET_SUPPORT
+    #define OPTION_FM1_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FM2_SOCKET_SUPPORT
+  #if  INSTALL_FM2_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FM2_SOCKET_SUPPORT
+    #define OPTION_FM2_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FP1_SOCKET_SUPPORT
+  #if  INSTALL_FP1_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FP1_SOCKET_SUPPORT
+    #define OPTION_FP1_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FP2_SOCKET_SUPPORT
+  #if  INSTALL_FP2_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FP2_SOCKET_SUPPORT
+    #define OPTION_FP2_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FT1_SOCKET_SUPPORT
+  #if  INSTALL_FT1_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FT1_SOCKET_SUPPORT
+    #define OPTION_FT1_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_FT2_SOCKET_SUPPORT
+  #if  INSTALL_FT2_SOCKET_SUPPORT == TRUE
+    #undef OPTION_FT2_SOCKET_SUPPORT
+    #define OPTION_FT2_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+#ifdef INSTALL_AM3_SOCKET_SUPPORT
+  #if  INSTALL_AM3_SOCKET_SUPPORT == TRUE
+    #undef OPTION_AM3_SOCKET_SUPPORT
+    #define OPTION_AM3_SOCKET_SUPPORT  TRUE
+  #endif
+#endif
+
+
+/*  Enable the appropriate family support  */
+// F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
+#ifdef INSTALL_FAMILY_10_SUPPORT
+  #if  INSTALL_FAMILY_10_SUPPORT == TRUE
+    #undef OPTION_FAMILY10H
+    #define OPTION_FAMILY10H     TRUE
+  #endif
+#endif
+
+// F12 is supported in FP1, FS1, & FM1
+#ifdef INSTALL_FAMILY_12_SUPPORT
+  #if  INSTALL_FAMILY_12_SUPPORT == TRUE
+    #undef OPTION_FAMILY12H
+    #define OPTION_FAMILY12H     TRUE
+  #endif
+#endif
+
+// F14 is supported in FT1 and FT2
+#ifdef INSTALL_FAMILY_14_SUPPORT
+  #if  INSTALL_FAMILY_14_SUPPORT == TRUE
+    #undef OPTION_FAMILY14H
+    #define OPTION_FAMILY14H     TRUE
+  #endif
+#endif
+
+// F15_0x is supported in G34, C32, & AM3
+#ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+  #if  INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE
+    #undef OPTION_FAMILY15H
+    #define OPTION_FAMILY15H     TRUE
+    #undef OPTION_FAMILY15H_MODEL_0x
+    #define OPTION_FAMILY15H_MODEL_0x     TRUE
+  #endif
+#endif
+
+// F15_1x is supported in FS1r2, FM2, & FP2
+#ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT
+  #if  INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE
+    #undef OPTION_FAMILY15H
+    #define OPTION_FAMILY15H     TRUE
+    #undef OPTION_FAMILY15H_MODEL_1x
+    #define OPTION_FAMILY15H_MODEL_1x     TRUE
+  #endif
+#endif
+
+// F15_2x is supported in G2012, C2012, & FM2
+#ifdef INSTALL_FAMILY_15_MODEL_2x_SUPPORT
+  #if  INSTALL_FAMILY_15_MODEL_2x_SUPPORT == TRUE
+    #undef OPTION_FAMILY15H
+    #define OPTION_FAMILY15H     TRUE
+    #undef OPTION_FAMILY15H_MODEL_2x
+    #define OPTION_FAMILY15H_MODEL_2x     TRUE
+  #endif
+#endif
+
+
+/*  Turn off families not required by socket designations */
+#if (OPTION_FAMILY10H == TRUE)
+  #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY10H
+    #define OPTION_FAMILY10H  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY12H == TRUE)
+  #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY12H
+    #define OPTION_FAMILY12H  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY14H == TRUE)
+  #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) && (OPTION_FT2_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY14H
+    #define OPTION_FAMILY14H  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY15H_MODEL_0x == TRUE)
+  #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY15H_MODEL_0x
+    #define OPTION_FAMILY15H_MODEL_0x  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY15H_MODEL_1x == TRUE)
+  #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY15H_MODEL_1x
+    #define OPTION_FAMILY15H_MODEL_1x  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY15H_MODEL_2x == TRUE)
+  #if (OPTION_G2012_SOCKET_SUPPORT == FALSE) && (OPTION_C2012_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE)
+    #undef OPTION_FAMILY15H_MODEL_2x
+    #define OPTION_FAMILY15H_MODEL_2x  FALSE
+  #endif
+#endif
+
+#if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
+  #undef OPTION_FAMILY15H
+  #define OPTION_FAMILY15H     FALSE
+#endif
+
+/*  Check for invalid combinations of socket/family */
+#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
+    #error No G34 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
+    #error No C32 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_G2012_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
+    #error No G2012 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_C2012_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
+    #error No C2012 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE)
+    #error No S1G3 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE)
+    #error No S1G4 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE)
+    #error No ASB2 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE)
+    #error No FS1 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY12H == FALSE)
+    #error No FM1 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
+    #error No FM2 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY12H == FALSE)
+    #error No FP1 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FP2_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY15H_MODEL_1x == FALSE)
+    #error No FP2 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY14H == FALSE)
+    #error No FT1 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_FT2_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY14H == FALSE)
+    #error No FT2 supported families included in the build
+  #endif
+#endif
+
+#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
+    #error No AM3 supported families included in the build
+  #endif
+#endif
+
+
+/* Process AGESA private data
+ *
+ * Turn on appropriate CPU models and memory controllers,
+ * as well as some other memory controls.
+ */
+
+/*  Default all models to off  */
+#define OPTION_FAMILY10H_BL          FALSE
+#define OPTION_FAMILY10H_DA          FALSE
+#define OPTION_FAMILY10H_HY          FALSE
+#define OPTION_FAMILY10H_PH          FALSE
+#define OPTION_FAMILY10H_RB          FALSE
+#define OPTION_FAMILY12H_LN          FALSE
+#define OPTION_FAMILY14H_ON          FALSE
+#define OPTION_FAMILY14H_KR          FALSE
+#define OPTION_FAMILY15H_OR          FALSE
+#define OPTION_FAMILY15H_TN          FALSE
+#define OPTION_FAMILY15H_KM          FALSE
+
+/*  Default all memory controllers to off  */
+#define OPTION_MEMCTLR_DR            FALSE
+#define OPTION_MEMCTLR_HY            FALSE
+#define OPTION_MEMCTLR_OR            FALSE
+#define OPTION_MEMCTLR_C32           FALSE
+#define OPTION_MEMCTLR_DA            FALSE
+#define OPTION_MEMCTLR_LN            FALSE
+#define OPTION_MEMCTLR_ON            FALSE
+#define OPTION_MEMCTLR_KR            FALSE
+#define OPTION_MEMCTLR_Ni            FALSE
+#define OPTION_MEMCTLR_PH            FALSE
+#define OPTION_MEMCTLR_RB            FALSE
+#define OPTION_MEMCTLR_TN            FALSE
+#define OPTION_MEMCTLR_KM            FALSE
+
+/*  Default all memory controls to off  */
+#define OPTION_HW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_SW_WRITE_LEV_TRAINING            FALSE
+#define OPTION_CONTINOUS_PATTERN_GENERATION     FALSE
+#define OPTION_HW_DQS_REC_EN_TRAINING           FALSE
+#define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING   FALSE
+#define OPTION_OPT_SW_DQS_REC_EN_TRAINING       FALSE
+#define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING    FALSE
+#define OPTION_OPT_SW_RD_WR_POS_TRAINING        FALSE
+#define OPTION_MAX_RD_LAT_TRAINING              FALSE
+#define OPTION_HW_DRAM_INIT                     FALSE
+#define OPTION_SW_DRAM_INIT                     FALSE
+#define OPTION_S3_MEM_SUPPORT                   FALSE
+#define OPTION_ADDR_TO_CS_TRANSLATOR            FALSE
+#define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
+#define OPTION_RDDQS____TRAINING                FALSE
+
+/*  Defaults for public user options  */
+#define OPTION_UDIMMS                           FALSE
+#define OPTION_RDIMMS                           FALSE
+#define OPTION_SODIMMS                          FALSE
+#define OPTION_LRDIMMS                          FALSE
+#define OPTION_DDR2                             FALSE
+#define OPTION_DDR3                             FALSE
+#define OPTION_ECC                              FALSE
+#define OPTION_BANK_INTERLEAVE                  FALSE
+#define OPTION_DCT_INTERLEAVE                   FALSE
+#define OPTION_NODE_INTERLEAVE                  FALSE
+#define OPTION_PARALLEL_TRAINING                FALSE
+#define OPTION_ONLINE_SPARE                     FALSE
+#define OPTION_MEM_RESTORE                      FALSE
+#define OPTION_DIMM_EXCLUDE                     FALSE
+
+/*  Default all CPU controls to off  */
+#define OPTION_MULTISOCKET                      FALSE
+#define OPTION_SRAT                             FALSE
+#define OPTION_SLIT                             FALSE
+#define OPTION_HT_ASSIST                        FALSE
+#define OPTION_ATM_MODE                         FALSE
+#define OPTION_CPU_CORELEVLING                  FALSE
+#define OPTION_MSG_BASED_C1E                    FALSE
+#define OPTION_CPU_CFOH                         FALSE
+#define OPTION_C6_STATE                         FALSE
+#define OPTION_IO_CSTATE                        FALSE
+#define OPTION_CPB                              FALSE
+#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT   FALSE
+#define OPTION_CPU_PSTATE_HPC_MODE              FALSE
+#define OPTION_CPU_APM                          FALSE
+#define OPTION_S3SCRIPT                         FALSE
+#define OPTION_GFX_RECOVERY                     FALSE
+
+/*  Default FCH controls to off  */
+#define FCH_SUPPORT                             FALSE
+
+/*  Enable all private controls based on socket/family enables  */
+#if (OPTION_G34_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_HY
+    #define OPTION_FAMILY10H_HY  TRUE
+    #undef OPTION_MEMCTLR_HY
+    #define OPTION_MEMCTLR_HY    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET  TRUE
+    #undef OPTION_SRAT
+    #define OPTION_SRAT  TRUE
+    #undef OPTION_SLIT
+    #define OPTION_SLIT  TRUE
+    #undef OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_RDIMMS
+    #define OPTION_RDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+  #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
+    #undef OPTION_FAMILY15H_OR
+    #define OPTION_FAMILY15H_OR  TRUE
+    #undef OPTION_MEMCTLR_OR
+    #define OPTION_MEMCTLR_OR    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_CONTINOUS_PATTERN_GENERATION
+    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
+    #undef OPTION_HW_DQS_REC_EN_TRAINING
+    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET  TRUE
+    #undef OPTION_C6_STATE
+    #define OPTION_C6_STATE  TRUE
+    #undef OPTION_IO_CSTATE
+    #define OPTION_IO_CSTATE TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB  TRUE
+    #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
+    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
+    #undef OPTION_CPU_APM
+    #define OPTION_CPU_APM TRUE
+    #undef OPTION_SRAT
+    #define OPTION_SRAT  TRUE
+    #undef OPTION_SLIT
+    #define OPTION_SLIT  TRUE
+    #undef OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST  TRUE
+    #undef OPTION_ATM_MODE
+    #define OPTION_ATM_MODE  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_RDIMMS
+    #define OPTION_RDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_LRDIMMS
+    #define OPTION_LRDIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#if (OPTION_C32_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_HY
+    #define OPTION_FAMILY10H_HY  TRUE
+    #undef OPTION_MEMCTLR_C32
+    #define OPTION_MEMCTLR_C32   TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR  FALSE
+    #undef OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET  TRUE
+    #undef OPTION_SRAT
+    #define OPTION_SRAT  TRUE
+    #undef OPTION_SLIT
+    #define OPTION_SLIT  TRUE
+    #undef OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_RDIMMS
+    #define OPTION_RDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+  #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
+    #undef OPTION_FAMILY15H_OR
+    #define OPTION_FAMILY15H_OR  TRUE
+    #undef OPTION_MEMCTLR_OR
+    #define OPTION_MEMCTLR_OR    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_CONTINOUS_PATTERN_GENERATION
+    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
+    #undef OPTION_HW_DQS_REC_EN_TRAINING
+    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
+    #undef OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET  TRUE
+    #undef OPTION_C6_STATE
+    #define OPTION_C6_STATE  TRUE
+    #undef OPTION_IO_CSTATE
+    #define OPTION_IO_CSTATE TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB  TRUE
+    #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
+    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
+    #undef OPTION_CPU_APM
+    #define OPTION_CPU_APM TRUE
+    #undef OPTION_SRAT
+    #define OPTION_SRAT  TRUE
+    #undef OPTION_SLIT
+    #define OPTION_SLIT  TRUE
+    #undef OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST  TRUE
+    #undef OPTION_ATM_MODE
+    #define OPTION_ATM_MODE  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_RDIMMS
+    #define OPTION_RDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_LRDIMMS
+    #define OPTION_LRDIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_BL
+    #define OPTION_FAMILY10H_BL  TRUE
+    #undef OPTION_FAMILY10H_DA
+    #define OPTION_FAMILY10H_DA  TRUE
+    #undef OPTION_MEMCTLR_DA
+    #define OPTION_MEMCTLR_DA    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_BL
+    #define OPTION_FAMILY10H_BL  TRUE
+    #undef OPTION_FAMILY10H_DA
+    #define OPTION_FAMILY10H_DA  TRUE
+    #undef OPTION_MEMCTLR_DA
+    #define OPTION_MEMCTLR_DA    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_BL
+    #define OPTION_FAMILY10H_BL  TRUE
+    #undef OPTION_FAMILY10H_DA
+    #define OPTION_FAMILY10H_DA  TRUE
+    #undef OPTION_MEMCTLR_Ni
+    #define OPTION_MEMCTLR_Ni    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
+  #if (OPTION_FAMILY10H == TRUE)
+    #undef OPTION_FAMILY10H_BL
+    #define OPTION_FAMILY10H_BL  TRUE
+    #undef OPTION_FAMILY10H_DA
+    #define OPTION_FAMILY10H_DA  TRUE
+    #undef OPTION_FAMILY10H_PH
+    #define OPTION_FAMILY10H_PH  TRUE
+    #undef OPTION_FAMILY10H_RB
+    #define OPTION_FAMILY10H_RB  TRUE
+    #undef OPTION_MEMCTLR_RB
+    #define OPTION_MEMCTLR_RB   TRUE
+    #undef OPTION_MEMCTLR_DA
+    #define OPTION_MEMCTLR_DA   TRUE
+    #undef OPTION_MEMCTLR_PH
+    #define OPTION_MEMCTLR_PH   TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
+    #define OPTION_OPT_SW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_IO_CSTATE
+    #define OPTION_IO_CSTATE TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+  #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
+    #undef OPTION_FAMILY15H_OR
+    #define OPTION_FAMILY15H_OR  TRUE
+    #undef OPTION_MEMCTLR_OR
+    #define OPTION_MEMCTLR_OR    TRUE
+    #undef OPTION_HW_WRITE_LEV_TRAINING
+    #define OPTION_HW_WRITE_LEV_TRAINING  TRUE
+    #undef OPTION_CONTINOUS_PATTERN_GENERATION
+    #define OPTION_CONTINOUS_PATTERN_GENERATION  TRUE
+    #undef OPTION_HW_DQS_REC_EN_TRAINING
+    #define OPTION_HW_DQS_REC_EN_TRAINING  TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      TRUE
+    #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
+    #define OPTION_OPT_SW_RD_WR_POS_TRAINING  TRUE
+    #undef OPTION_MAX_RD_LAT_TRAINING
+    #define OPTION_MAX_RD_LAT_TRAINING  TRUE
+    #undef OPTION_SW_DRAM_INIT
+    #define OPTION_SW_DRAM_INIT  TRUE
+    #undef OPTION_C6_STATE
+    #define OPTION_C6_STATE  TRUE
+    #undef OPTION_IO_CSTATE
+    #define OPTION_IO_CSTATE TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB  TRUE
+    #undef OPTION_CPU_APM
+    #define OPTION_CPU_APM TRUE
+    #undef OPTION_S3_MEM_SUPPORT
+    #define OPTION_S3_MEM_SUPPORT  TRUE
+    #undef OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR  TRUE
+    #undef OPTION_ATM_MODE
+    #define OPTION_ATM_MODE TRUE
+    #undef OPTION_CPU_CORELEVLING
+    #define OPTION_CPU_CORELEVLING  TRUE
+    #undef OPTION_CPU_CFOH
+    #define OPTION_CPU_CFOH  TRUE
+    #undef OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E  TRUE
+    #undef OPTION_UDIMMS
+    #define OPTION_UDIMMS  TRUE
+    #undef OPTION_RDIMMS
+    #define OPTION_RDIMMS  TRUE
+    #undef OPTION_LRDIMMS
+    #define OPTION_LRDIMMS  TRUE
+    #undef OPTION_SODIMMS
+    #define OPTION_SODIMMS  TRUE
+    #undef OPTION_DDR3
+    #define OPTION_DDR3  TRUE
+    #undef OPTION_ECC
+    #define OPTION_ECC  TRUE
+    #undef OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE  TRUE
+    #undef OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE  TRUE
+    #undef OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE  TRUE
+    #undef OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE  TRUE
+    #undef OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE TRUE
+    #undef OPTION_DIMM_EXCLUDE
+    #define OPTION_DIMM_EXCLUDE  TRUE
+  #endif
+#endif
+
+#define OPTION_ACPI_PSTATES             TRUE
+#define OPTION_WHEA                     TRUE
+#define OPTION_DMI                      TRUE
+#define OPTION_EARLY_SAMPLES            FALSE
+#define CFG_ACPI_PSTATES_PPC            TRUE
+#define CFG_ACPI_PSTATES_PCT            TRUE
+#define CFG_ACPI_PSTATES_PSD            TRUE
+#define CFG_ACPI_PSTATES_PSS            TRUE
+#define CFG_ACPI_PSTATES_XPSS           TRUE
+#define CFG_ACPI_PSTATE_PSD_INDPX       FALSE
+#define CFG_VRM_HIGH_SPEED_ENABLE       FALSE
+#define CFG_VRM_NB_HIGH_SPEED_ENABLE    FALSE
+#define OPTION_ALIB                     TRUE
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Second, process the user's selections
+ *--------------------------------------------------------------------------*/
+#ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
+  #if  BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
+    #undef  OPTION_MULTISOCKET
+    #define OPTION_MULTISOCKET          FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ECC_SUPPORT
+  #if  BLDOPT_REMOVE_ECC_SUPPORT == TRUE
+    #undef  OPTION_ECC
+    #define OPTION_ECC        FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
+    #undef  OPTION_UDIMMS
+    #define OPTION_UDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
+    #undef  OPTION_RDIMMS
+    #define OPTION_RDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
+    #undef  OPTION_SODIMMS
+    #define OPTION_SODIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
+  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
+    #undef  OPTION_LRDIMMS
+    #define OPTION_LRDIMMS               FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
+  #if  BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
+    #undef  OPTION_BANK_INTERLEAVE
+    #define OPTION_BANK_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
+  #if  BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
+    #undef  OPTION_DCT_INTERLEAVE
+    #define OPTION_DCT_INTERLEAVE       FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
+  #if  BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
+    #undef  OPTION_NODE_INTERLEAVE
+    #define OPTION_NODE_INTERLEAVE      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
+  #if  BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
+    #undef  OPTION_PARALLEL_TRAINING
+    #define OPTION_PARALLEL_TRAINING    FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
+  #if  BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
+    #undef  OPTION_ONLINE_SPARE
+    #define OPTION_ONLINE_SPARE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
+  #if  BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
+    #undef  OPTION_MEM_RESTORE
+    #define OPTION_MEM_RESTORE         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
+  #if  BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
+    #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
+    #define OPTION_HW_DQS_REC_EN_SEED_TRAINING      FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ACPI_PSTATES
+  #if  BLDOPT_REMOVE_ACPI_PSTATES == TRUE
+    #undef  OPTION_ACPI_PSTATES
+    #define OPTION_ACPI_PSTATES         FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SRAT
+  #if  BLDOPT_REMOVE_SRAT == TRUE
+    #undef  OPTION_SRAT
+    #define OPTION_SRAT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_SLIT
+  #if  BLDOPT_REMOVE_SLIT == TRUE
+    #undef  OPTION_SLIT
+    #define OPTION_SLIT                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_WHEA
+  #if  BLDOPT_REMOVE_WHEA == TRUE
+    #undef  OPTION_WHEA
+    #define OPTION_WHEA                 FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_DMI
+  #if  BLDOPT_REMOVE_DMI == TRUE
+    #undef  OPTION_DMI
+    #define OPTION_DMI                  FALSE
+  #endif
+#endif
+#ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
+  #if  BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
+    #undef  OPTION_ADDR_TO_CS_TRANSLATOR
+    #define OPTION_ADDR_TO_CS_TRANSLATOR        FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_HT_ASSIST
+  #if  BLDOPT_REMOVE_HT_ASSIST == TRUE
+    #undef  OPTION_HT_ASSIST
+    #define OPTION_HT_ASSIST      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ATM_MODE
+  #if  BLDOPT_REMOVE_ATM_MODE == TRUE
+    #undef  OPTION_ATM_MODE
+    #define OPTION_ATM_MODE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_MSG_BASED_C1E
+  #if  BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
+    #undef  OPTION_MSG_BASED_C1E
+    #define OPTION_MSG_BASED_C1E      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_C6_STATE
+  #if  BLDOPT_REMOVE_C6_STATE == TRUE
+    #undef  OPTION_C6_STATE
+    #define OPTION_C6_STATE      FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_GFX_RECOVERY
+  #if  BLDOPT_REMOVE_GFX_RECOVERY == TRUE
+    #undef  OPTION_GFX_RECOVERY
+    #define OPTION_GFX_RECOVERY         FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
+    #undef  CFG_ACPI_PSTATES_PPC
+    #define CFG_ACPI_PSTATES_PPC        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
+    #undef  CFG_ACPI_PSTATES_PCT
+    #define CFG_ACPI_PSTATES_PCT        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
+    #undef  CFG_ACPI_PSTATES_PSD
+    #define CFG_ACPI_PSTATES_PSD        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
+    #undef  CFG_ACPI_PSTATES_PSS
+    #define CFG_ACPI_PSTATES_PSS        FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
+  #if  BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
+    #undef  CFG_ACPI_PSTATES_XPSS
+    #define CFG_ACPI_PSTATES_XPSS       FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
+  #if  BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT  == TRUE
+    #undef  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
+    #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT    FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_PSTATE_HPC_MODE
+  #if  BLDCFG_PSTATE_HPC_MODE  == TRUE
+    #undef  OPTION_CPU_PSTATE_HPC_MODE
+    #define OPTION_CPU_PSTATE_HPC_MODE    TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
+  #if  BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
+    #undef  CFG_ACPI_PSTATE_PSD_INDPX
+    #define CFG_ACPI_PSTATE_PSD_INDPX       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
+  #if  BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
+    #undef  CFG_VRM_HIGH_SPEED_ENABLE
+    #define CFG_VRM_HIGH_SPEED_ENABLE       TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
+  #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
+    #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
+    #define CFG_VRM_NB_HIGH_SPEED_ENABLE    TRUE
+  #endif
+#endif
+
+#ifdef BLDCFG_STARTING_BUSNUM
+  #define CFG_STARTING_BUSNUM         (BLDCFG_STARTING_BUSNUM)
+#else
+  #define CFG_STARTING_BUSNUM         (0)
+#endif
+
+#ifdef BLDCFG_AMD_PLATFORM_TYPE
+  #define CFG_AMD_PLATFORM_TYPE              BLDCFG_AMD_PLATFORM_TYPE
+#else
+  #define CFG_AMD_PLATFORM_TYPE              0
+#endif
+
+CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
+
+#ifdef BLDCFG_MAXIMUM_BUSNUM
+  #define CFG_MAXIMUM_BUSNUM          (BLDCFG_MAXIMUM_BUSNUM)
+#else
+  #define CFG_MAXIMUM_BUSNUM          (0xF8)
+#endif
+
+#ifdef BLDCFG_ALLOCATED_BUSNUM
+  #define CFG_ALLOCATED_BUSNUM        (BLDCFG_ALLOCATED_BUSNUM)
+#else
+  #define CFG_ALLOCATED_BUSNUM        (0x20)
+#endif
+
+#ifdef BLDCFG_BUID_SWAP_LIST
+  #define CFG_BUID_SWAP_LIST         (BLDCFG_BUID_SWAP_LIST)
+#else
+  #define CFG_BUID_SWAP_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
+#else
+  #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTFABRIC_LIMITS_LIST
+  #define CFG_HTFABRIC_LIMITS_LIST         (BLDCFG_HTFABRIC_LIMITS_LIST)
+#else
+  #define CFG_HTFABRIC_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_HTCHAIN_LIMITS_LIST
+  #define CFG_HTCHAIN_LIMITS_LIST         (BLDCFG_HTCHAIN_LIMITS_LIST)
+#else
+  #define CFG_HTCHAIN_LIMITS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_BUS_NUMBERS_LIST
+  #define CFG_BUS_NUMBERS_LIST         (BLDCFG_BUS_NUMBERS_LIST)
+#else
+  #define CFG_BUS_NUMBERS_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_IGNORE_LINK_LIST
+  #define CFG_IGNORE_LINK_LIST         (BLDCFG_IGNORE_LINK_LIST)
+#else
+  #define CFG_IGNORE_LINK_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_LINK_SKIP_REGANG_LIST
+  #define CFG_LINK_SKIP_REGANG_LIST         (BLDCFG_LINK_SKIP_REGANG_LIST)
+#else
+  #define CFG_LINK_SKIP_REGANG_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (BLDCFG_SET_HTCRC_SYNC_FLOOD)
+#else
+  #define CFG_SET_HTCRC_SYNC_FLOOD         (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_UNIT_ID_CLUMPING
+  #define CFG_USE_UNIT_ID_CLUMPING         (BLDCFG_USE_UNIT_ID_CLUMPING)
+#else
+  #define CFG_USE_UNIT_ID_CLUMPING         (FALSE)
+#endif
+
+#ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
+#else
+  #define CFG_ADDITIONAL_TOPOLOGIES_LIST         (NULL)
+#endif
+
+#ifdef BLDCFG_USE_HT_ASSIST
+  #define CFG_USE_HT_ASSIST               (BLDCFG_USE_HT_ASSIST)
+#else
+  #define CFG_USE_HT_ASSIST               (TRUE)
+#endif
+
+#ifdef BLDCFG_USE_ATM_MODE
+  #define CFG_USE_ATM_MODE                (BLDCFG_USE_ATM_MODE)
+#else
+  #define CFG_USE_ATM_MODE                (TRUE)
+#endif
+
+#ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
+#else
+  #define CFG_PLATFORM_CONTROL_FLOW_MODE  (Nfcm)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
+  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
+#else
+  #define CFG_PERFORMANCE_HARDWARE_PREFETCHER  (HARDWARE_PREFETCHER_AUTO)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
+  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
+#else
+  #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES  (SOFTWARE_PREFETCHES_AUTO)
+#endif
+
+#ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
+  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
+#else
+  #define CFG_PERFORMANCE_DRAM_PREFETCHER  (DRAM_PREFETCHER_AUTO)
+#endif
+
+#ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
+#else
+  #define CFG_PLATFORM_DEEMPHASIS_LIST  (NULL)
+#endif
+
+#ifdef BLDCFG_VRM_ADDITIONAL_DELAY
+  #define CFG_VRM_ADDITIONAL_DELAY      (BLDCFG_VRM_ADDITIONAL_DELAY)
+#else
+  #define CFG_VRM_ADDITIONAL_DELAY      (0)
+#endif
+
+#ifdef BLDCFG_VRM_CURRENT_LIMIT
+  #define CFG_VRM_CURRENT_LIMIT            BLDCFG_VRM_CURRENT_LIMIT
+#else
+  #define CFG_VRM_CURRENT_LIMIT            0
+#endif
+
+#ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
+  #define CFG_VRM_LOW_POWER_THRESHOLD      BLDCFG_VRM_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_LOW_POWER_THRESHOLD      0
+#endif
+
+#ifdef BLDCFG_VRM_SLEW_RATE
+  #define CFG_VRM_SLEW_RATE                BLDCFG_VRM_SLEW_RATE
+#else
+  #define CFG_VRM_SLEW_RATE                DFLT_VRM_SLEW_RATE
+#endif
+
+#ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     BLDCFG_VRM_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_INRUSH_CURRENT_LIMIT     0
+#endif
+
+#ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
+  #define CFG_VRM_NB_ADDITIONAL_DELAY      (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
+#else
+  #define CFG_VRM_NB_ADDITIONAL_DELAY      (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
+  #define CFG_VRM_NB_CURRENT_LIMIT         BLDCFG_VRM_NB_CURRENT_LIMIT
+#else
+  #define CFG_VRM_NB_CURRENT_LIMIT         (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
+  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
+#else
+  #define CFG_VRM_NB_LOW_POWER_THRESHOLD   (0)
+#endif
+
+#ifdef BLDCFG_VRM_NB_SLEW_RATE
+  #define CFG_VRM_NB_SLEW_RATE             BLDCFG_VRM_NB_SLEW_RATE
+#else
+  #define CFG_VRM_NB_SLEW_RATE             DFLT_VRM_SLEW_RATE
+#endif
+
+#ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
+  #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
+#else
+  #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT  (0)
+#endif
+
+
+#ifdef BLDCFG_PLAT_NUM_IO_APICS
+  #define CFG_PLAT_NUM_IO_APICS            BLDCFG_PLAT_NUM_IO_APICS
+#else
+  #define CFG_PLAT_NUM_IO_APICS            0
+#endif
+
+#ifdef BLDCFG_MEM_INIT_PSTATE
+  #define CFG_MEM_INIT_PSTATE              BLDCFG_MEM_INIT_PSTATE
+#else
+  #define CFG_MEM_INIT_PSTATE              0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_MODE
+  #define CFG_C1E_MODE                        BLDCFG_PLATFORM_C1E_MODE
+#else
+  #define CFG_C1E_MODE                        C1eModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA
+  #define CFG_C1E_OPDATA                      BLDCFG_PLATFORM_C1E_OPDATA
+#else
+  #define CFG_C1E_OPDATA                      0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA1
+  #define CFG_C1E_OPDATA1                     BLDCFG_PLATFORM_C1E_OPDATA1
+#else
+  #define CFG_C1E_OPDATA1                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA2
+  #define CFG_C1E_OPDATA2                     BLDCFG_PLATFORM_C1E_OPDATA2
+#else
+  #define CFG_C1E_OPDATA2                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_C1E_OPDATA3
+  #define CFG_C1E_OPDATA3                     BLDCFG_PLATFORM_C1E_OPDATA3
+#else
+  #define CFG_C1E_OPDATA3                     0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_MODE
+  #define CFG_CSTATE_MODE                     BLDCFG_PLATFORM_CSTATE_MODE
+#else
+  #define CFG_CSTATE_MODE                     CStateModeDisabled
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
+  #define CFG_CSTATE_OPDATA                   BLDCFG_PLATFORM_CSTATE_OPDATA
+#else
+  #define CFG_CSTATE_OPDATA                   0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
+  #define CFG_CSTATE_IO_BASE_ADDRESS       BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
+#else
+  #define CFG_CSTATE_IO_BASE_ADDRESS       0
+#endif
+
+#ifdef BLDCFG_PLATFORM_CPB_MODE
+  #define CFG_CPB_MODE                        BLDCFG_PLATFORM_CPB_MODE
+#else
+  #define CFG_CPB_MODE                        CpbModeAuto
+#endif
+
+#ifdef BLDCFG_CORE_LEVELING_MODE
+  #define CFG_CORE_LEVELING_MODE           BLDCFG_CORE_LEVELING_MODE
+#else
+  #define CFG_CORE_LEVELING_MODE           0
+#endif
+
+#ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
+  #define CFG_AMD_PSTATE_CAP_VALUE           BLDCFG_AMD_PSTATE_CAP_VALUE
+#else
+  #define CFG_AMD_PSTATE_CAP_VALUE           0
+#endif
+
+#ifdef BLDCFG_HEAP_DRAM_ADDRESS
+  #define CFG_HEAP_DRAM_ADDRESS                 BLDCFG_HEAP_DRAM_ADDRESS
+#else
+  #define CFG_HEAP_DRAM_ADDRESS                 AMD_HEAP_RAM_ADDRESS
+#endif
+
+#ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
+#else
+  #define CFG_MEMORY_BUS_FREQUENCY_LIMIT        DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_MEMORY_MODE_UNGANGED
+  #define CFG_MEMORY_MODE_UNGANGED              BLDCFG_MEMORY_MODE_UNGANGED
+#else
+  #define CFG_MEMORY_MODE_UNGANGED              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          BLDCFG_MEMORY_QUAD_RANK_CAPABLE
+#else
+  #define CFG_MEMORY_QUAD_RANK_CAPABLE          TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_QUADRANK_TYPE
+  #define CFG_MEMORY_QUADRANK_TYPE              BLDCFG_MEMORY_QUADRANK_TYPE
+#else
+  #define CFG_MEMORY_QUADRANK_TYPE              DFLT_MEMORY_QUADRANK_TYPE
+#endif
+
+#ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
+  #define CFG_MEMORY_RDIMM_CAPABLE              BLDCFG_MEMORY_RDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_RDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
+  #define CFG_MEMORY_LRDIMM_CAPABLE              BLDCFG_MEMORY_LRDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_LRDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
+  #define CFG_MEMORY_UDIMM_CAPABLE              BLDCFG_MEMORY_UDIMM_CAPABLE
+#else
+  #define CFG_MEMORY_UDIMM_CAPABLE              TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
+  #define CFG_MEMORY_SODIMM_CAPABLE             BLDCFG_MEMORY_SODIMM_CAPABLE
+#else
+  #define CFG_MEMORY_SODIMM_CAPABLE             FALSE
+#endif
+
+#ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
+#else
+  #define CFG_LIMIT_MEMORY_TO_BELOW_1TB         TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING   TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
+#else
+  #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING   FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       BLDCFG_MEMORY_CHANNEL_INTERLEAVING
+#else
+  #define CFG_MEMORY_CHANNEL_INTERLEAVING       TRUE
+#endif
+
+#ifdef BLDCFG_MEMORY_POWER_DOWN
+  #define CFG_MEMORY_POWER_DOWN                 BLDCFG_MEMORY_POWER_DOWN
+#else
+  #define CFG_MEMORY_POWER_DOWN                 FALSE
+#endif
+
+#ifdef BLDCFG_POWER_DOWN_MODE
+  #define CFG_POWER_DOWN_MODE                   BLDCFG_POWER_DOWN_MODE
+#else
+  #define CFG_POWER_DOWN_MODE                   POWER_DOWN_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_ONLINE_SPARE
+  #define CFG_ONLINE_SPARE                      BLDCFG_ONLINE_SPARE
+#else
+  #define CFG_ONLINE_SPARE                      FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_PARITY_ENABLE
+  #define CFG_MEMORY_PARITY_ENABLE              BLDCFG_MEMORY_PARITY_ENABLE
+#else
+  #define CFG_MEMORY_PARITY_ENABLE              FALSE
+#endif
+
+#ifdef BLDCFG_BANK_SWIZZLE
+  #define CFG_BANK_SWIZZLE                      BLDCFG_BANK_SWIZZLE
+#else
+  #define CFG_BANK_SWIZZLE                      TRUE
+#endif
+
+#ifdef BLDCFG_TIMING_MODE_SELECT
+  #define CFG_TIMING_MODE_SELECT                BLDCFG_TIMING_MODE_SELECT
+#else
+  #define CFG_TIMING_MODE_SELECT                TIMING_MODE_AUTO
+#endif
+
+#ifdef BLDCFG_MEMORY_CLOCK_SELECT
+  #define CFG_MEMORY_CLOCK_SELECT               BLDCFG_MEMORY_CLOCK_SELECT
+#else
+  #define CFG_MEMORY_CLOCK_SELECT               DDR800_FREQUENCY
+#endif
+
+#ifdef BLDCFG_DQS_TRAINING_CONTROL
+  #define CFG_DQS_TRAINING_CONTROL              BLDCFG_DQS_TRAINING_CONTROL
+#else
+  #define CFG_DQS_TRAINING_CONTROL              TRUE
+#endif
+
+#ifdef BLDCFG_IGNORE_SPD_CHECKSUM
+  #define CFG_IGNORE_SPD_CHECKSUM               BLDCFG_IGNORE_SPD_CHECKSUM
+#else
+  #define CFG_IGNORE_SPD_CHECKSUM               FALSE
+#endif
+
+#ifdef BLDCFG_USE_BURST_MODE
+  #define CFG_USE_BURST_MODE                    BLDCFG_USE_BURST_MODE
+#else
+  #define CFG_USE_BURST_MODE                    FALSE
+#endif
+
+#ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
+  #define CFG_MEMORY_ALL_CLOCKS_ON              BLDCFG_MEMORY_ALL_CLOCKS_ON
+#else
+  #define CFG_MEMORY_ALL_CLOCKS_ON              FALSE
+#endif
+
+#ifdef BLDCFG_ENABLE_ECC_FEATURE
+  #define CFG_ENABLE_ECC_FEATURE                BLDCFG_ENABLE_ECC_FEATURE
+#else
+  #define CFG_ENABLE_ECC_FEATURE                TRUE
+#endif
+
+#ifdef BLDCFG_ECC_REDIRECTION
+  #define CFG_ECC_REDIRECTION                   BLDCFG_ECC_REDIRECTION
+#else
+  #define CFG_ECC_REDIRECTION                   FALSE
+#endif
+
+#ifdef BLDCFG_SCRUB_DRAM_RATE
+  #define CFG_SCRUB_DRAM_RATE         BLDCFG_SCRUB_DRAM_RATE
+#else
+  #define CFG_SCRUB_DRAM_RATE         DFLT_SCRUB_DRAM_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_L2_RATE
+  #define CFG_SCRUB_L2_RATE           BLDCFG_SCRUB_L2_RATE
+#else
+  #define CFG_SCRUB_L2_RATE           DFLT_SCRUB_L2_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_L3_RATE
+  #define CFG_SCRUB_L3_RATE           BLDCFG_SCRUB_L3_RATE
+#else
+  #define CFG_SCRUB_L3_RATE           DFLT_SCRUB_L3_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_IC_RATE
+  #define CFG_SCRUB_IC_RATE           BLDCFG_SCRUB_IC_RATE
+#else
+  #define CFG_SCRUB_IC_RATE           DFLT_SCRUB_IC_RATE
+#endif
+
+#ifdef BLDCFG_SCRUB_DC_RATE
+  #define CFG_SCRUB_DC_RATE           BLDCFG_SCRUB_DC_RATE
+#else
+  #define CFG_SCRUB_DC_RATE           DFLT_SCRUB_DC_RATE
+#endif
+
+#ifdef BLDCFG_ECC_SYNC_FLOOD
+  #define CFG_ECC_SYNC_FLOOD          BLDCFG_ECC_SYNC_FLOOD
+#else
+  #define CFG_ECC_SYNC_FLOOD          TRUE
+#endif
+
+#ifdef BLDCFG_ECC_SYMBOL_SIZE
+  #define CFG_ECC_SYMBOL_SIZE         BLDCFG_ECC_SYMBOL_SIZE
+#else
+  #define CFG_ECC_SYMBOL_SIZE         0
+#endif
+
+#ifdef BLDCFG_1GB_ALIGN
+  #define CFG_1GB_ALIGN               BLDCFG_1GB_ALIGN
+#else
+  #define CFG_1GB_ALIGN               FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_MODE
+  #define CFG_UMA_MODE                BLDCFG_UMA_ALLOCATION_MODE
+#else
+  #define CFG_UMA_MODE                UMA_AUTO
+#endif
+
+#ifdef BLDCFG_FORCE_TRAINING_MODE
+  #define CFG_FORCE_TRAIN_MODE                BLDCFG_FORCE_TRAINING_MODE
+#else
+  #define CFG_FORCE_TRAIN_MODE                FORCE_TRAIN_AUTO
+#endif
+
+#ifdef BLDCFG_UMA_ALLOCATION_SIZE
+  #define CFG_UMA_SIZE                BLDCFG_UMA_ALLOCATION_SIZE
+#else
+  #define CFG_UMA_SIZE                0
+#endif
+
+#ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
+  #define CFG_UMA_ABOVE4G           BLDCFG_UMA_ABOVE4G_SUPPORT
+#else
+  #define CFG_UMA_ABOVE4G           FALSE
+#endif
+
+#ifdef BLDCFG_UMA_ALIGNMENT
+  #define CFG_UMA_ALIGNMENT           BLDCFG_UMA_ALIGNMENT
+#else
+  #define CFG_UMA_ALIGNMENT           NO_UMA_ALIGNED
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
+  #define CFG_PROCESSOR_SCOPE_IN_SB   BLDCFG_PROCESSOR_SCOPE_IN_SB
+#else
+  #define CFG_PROCESSOR_SCOPE_IN_SB   FALSE
+#endif
+
+#ifdef BLDCFG_S3_LATE_RESTORE
+  #define CFG_S3_LATE_RESTORE         BLDCFG_S3_LATE_RESTORE
+#else
+  #define CFG_S3_LATE_RESTORE         TRUE
+#endif
+
+#ifdef BLDCFG_USE_32_BYTE_REFRESH
+  #define CFG_USE_32_BYTE_REFRESH  (BLDCFG_USE_32_BYTE_REFRESH)
+#else
+  #define CFG_USE_32_BYTE_REFRESH  (FALSE)
+#endif
+
+#ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+#else
+  #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY  (FALSE)
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
+  #define CFG_PROCESSOR_SCOPE_NAME0          BLDCFG_PROCESSOR_SCOPE_NAME0
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME0          SCOPE_NAME_VALUE
+#endif
+
+#ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
+  #define CFG_PROCESSOR_SCOPE_NAME1          BLDCFG_PROCESSOR_SCOPE_NAME1
+#else
+  #define CFG_PROCESSOR_SCOPE_NAME1          SCOPE_NAME_VALUE1
+#endif
+
+#ifdef BLDCFG_CFG_GNB_HD_AUDIO
+  #define CFG_GNB_HD_AUDIO                   BLDCFG_CFG_GNB_HD_AUDIO
+#else
+  #define CFG_GNB_HD_AUDIO                   TRUE
+#endif
+
+#ifdef BLDCFG_CFG_ABM_SUPPORT
+  #define CFG_ABM_SUPPORT                    BLDCFG_CFG_ABM_SUPPORT
+#else
+  #define CFG_ABM_SUPPORT                    FALSE
+#endif
+
+#ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+  #define CFG_DINAMIC_REFRESH_RATE           BLDCFG_CFG_DYNAMIC_REFRESH_RATE
+#else
+  #define CFG_DYNAMIC_REFRESH_RATE           0
+#endif
+
+#ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+  #define CFG_LCD_BACK_LIGHT_CONTROL         BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
+#else
+  #define CFG_LCD_BACK_LIGHT_CONTROL         0
+#endif
+
+#ifdef BLDCFG_STEREO_3D_PINOUT
+  #define CFG_GNB_STEREO_3D_PINOUT           BLDCFG_STEREO_3D_PINOUT
+#else
+  #define CFG_GNB_STEREO_3D_PINOUT           0
+#endif
+
+#ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
+  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     BLDCFG_REMOTE_DISPLAY_SUPPORT
+#else
+  #define CFG_GNB_REMOTE_DISPLAY_SUPPORT     FALSE
+#endif
+
+#ifdef BLDCFG_IGPU_SUBSYSTEM_ID
+  #define CFG_GNB_IGPU_SSID                  BLDCFG_IGPU_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_IGPU_SSID                  0
+#endif
+
+#ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
+  #define CFG_GNB_HDAUDIO_SSID               BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_HDAUDIO_SSID               0
+#endif
+
+#ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
+  #define CFG_GNB_PCIE_SSID                  BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
+#else
+  #define CFG_GNB_PCIE_SSID                  0x12341022
+#endif
+
+#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
+#else
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM               0
+#endif
+
+#ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
+#else
+  #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
+#endif
+
+#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+#else
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
+#endif
+
+#ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
+#else
+  #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
+#endif
+
+#ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
+  #define CFG_ENABLE_EXTERNAL_VREF                BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
+#else
+  #define CFG_ENABLE_EXTERNAL_VREF                FALSE
+#endif
+
+#ifdef BLDOPT_REMOVE_EARLY_SAMPLES
+  #if  BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        FALSE
+  #else
+    #undef  OPTION_EARLY_SAMPLES
+    #define OPTION_EARLY_SAMPLES        TRUE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_ALIB
+  #if  BLDOPT_REMOVE_ALIB == TRUE
+    #undef  OPTION_ALIB
+    #define OPTION_ALIB                 FALSE
+  #else
+    #undef  OPTION_ALIB
+    #define OPTION_ALIB                 TRUE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FCH_COMPONENT
+  #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
+    #undef FCH_SUPPORT
+    #define FCH_SUPPORT                            FALSE
+  #endif
+#endif
+
+#ifdef BLDCFG_IOMMU_SUPPORT
+  #define CFG_IOMMU_SUPPORT             BLDCFG_IOMMU_SUPPORT
+#else
+  #define CFG_IOMMU_SUPPORT             TRUE
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
+  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE             0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL           0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON             0
+#endif
+
+#ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
+  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
+#else
+  #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE          0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
+  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY         0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
+  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON         0
+#endif
+
+#ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
+  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
+#else
+  #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL         0
+#endif
+
+#ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
+  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
+#else
+  #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ             0
+#endif
+
+#ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
+  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
+#else
+  #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE           0
+#endif
+
+
+// BLDCFG_LVDS_24BBP_PANEL_MODE
+// This specifies the LVDS 24 BBP mode.
+// 0 - Use LDI mode (default).
+// 1 - Use FPDI mode.
+#ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
+  #define CFG_LVDS_24BBP_PANEL_MODE                 BLDCFG_LVDS_24BBP_PANEL_MODE
+#else
+  #define CFG_LVDS_24BBP_PANEL_MODE                 0
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 BLDCFG_LVDS_MISC_888_FPDI_MODE
+#else
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 BLDCFG_LVDS_MISC_DL_CH_SWAP
+#else
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_FORCE_MICROSERVER
+  #define CFG_FORCE_MICROSERVER                         BLDCFG_FORCE_MICROSERVER
+#else
+  #define CFG_FORCE_MICROSERVER                         FALSE
+#endif
+
+/*---------------------------------------------------------------------------
+ *       Processing the options:  Third, perform the option cross checks
+ *--------------------------------------------------------------------------*/
+// Assure that at least one type of memory support is included
+#if OPTION_UDIMMS == FALSE
+  #if OPTION_RDIMMS == FALSE
+    #if OPTION_SODIMMS == FALSE
+      #if OPTION_LRDIMMS == FALSE
+        #error  BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure at least one dimm type is capable
+#if CFG_MEMORY_RDIMM_CAPABLE == FALSE
+  #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
+    #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
+      #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
+        #error   BLDCFG: No dimm type is capable
+      #endif
+    #endif
+  #endif
+#endif
+// Check LRDIMM CODE and LRDIMM CFG item
+#if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
+  #if  BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
+    #error   Warning: LRDIMM capability is false, but LRIDMM support code included
+  #endif
+#endif
+//  Turn off multi-socket based features if only one node...
+#if OPTION_MULTISOCKET == FALSE
+  #undef  OPTION_PARALLEL_TRAINING
+  #define OPTION_PARALLEL_TRAINING    FALSE
+  #undef  OPTION_NODE_INTERLEAVE
+  #define OPTION_NODE_INTERLEAVE      FALSE
+#endif
+// Ensure that at least one write leveling option is selected
+#if OPTION_DDR3 == TRUE
+  #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
+    #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
+      #error  No Write leveling option selected for DDR3
+    #endif
+  #endif
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error   Software dram init must be enabled for DDR3 dimms
+  #endif
+#endif
+// Ensure at least one DQS receiver training option is selected
+#if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
+  #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+    #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
+      #error    No DQS receiver training option has been slected
+    #endif
+  #endif
+#endif
+// Ensure at least one Rd Wr position training option has been selected
+#if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
+  #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
+    #error    No Rd Wr position training option has been selected
+  #endif
+#endif
+// Ensure at least one dram init option has been selected
+#if OPTION_HW_DRAM_INIT == FALSE
+  #if OPTION_SW_DRAM_INIT == FALSE
+    #error    No Dram init option has been selected
+  #endif
+#endif
+// Ensure the frequency limit is valid
+#if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
+  #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
+    #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
+      #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
+        #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
+          #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
+            #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
+              #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
+                #error    BLDCFG: Unsupported memory bus frequency
+              #endif
+            #endif
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+// Ensure timing mode is valid
+#if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
+  #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
+    #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
+      #error    BLDCFG: Invalid timing mode is set
+    #endif
+  #endif
+#endif
+// Ensure the scrub rate is valid
+#if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
+  #error    BLDCFG: Unsupported dram scrub rate set
+#endif
+#if CFG_SCRUB_L2_RATE > 0x16
+  #error   BLDCFG: Unsupported L2 scrubber rate set
+#endif
+#if CFG_SCRUB_L3_RATE > 0x16
+  #error   BLDCFG: unsupported L3 scrubber rate set
+#endif
+#if CFG_SCRUB_IC_RATE > 0x16
+  #error    BLDCFG: Unsupported Instruction cache scrub rate set
+#endif
+#if CFG_SCRUB_DC_RATE > 0x16
+  #error   BLDCFG: Unsupported Dcache scrub rate set
+#endif
+// Ensure Quad rank dimm type is valid
+#if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
+  #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
+    #error     BLDCFG: Invalid quad rank dimm type set
+  #endif
+#endif
+// Ensure ECC symbol size is valid
+#if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
+  #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
+    #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
+      #error   BLDCFG: Invalid Ecc symbol size set
+    #endif
+  #endif
+#endif
+// Ensure power down mode is valid
+#if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
+  #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
+    #error     BLDCFG: Invalid power down mode set
+  #endif
+#endif
+
+/*****************************************************************************
+ *
+ * Process the option logic, setting local control variables
+ *
+ ****************************************************************************/
+#if OPTION_ACPI_PSTATES == TRUE
+  #define OPTFCN_ACPI_TABLES           CreateAcpiTablesMain
+  #define OPTFCN_GATHER_DATA           PStateGatherData
+  #if OPTION_MULTISOCKET == TRUE
+    #define OPTFCN_PSTATE_LEVELING     PStateLeveling
+  #else
+    #define OPTFCN_PSTATE_LEVELING     CommonReturnAgesaSuccess
+  #endif
+#else
+  #define OPTFCN_ACPI_TABLES           CommonReturnAgesaSuccess
+  #define OPTFCN_GATHER_DATA           CommonReturnAgesaSuccess
+  #define OPTFCN_PSTATE_LEVELING       CommonReturnAgesaSuccess
+#endif
+
+
+/*****************************************************************************
+ *
+ * Include the structure definitions for the defaults table structures
+ *
+ ****************************************************************************/
+#include  "Options.h"
+#include  "OptionCpuFamiliesInstall.h"
+#include  "OptionsHt.h"
+#include  "OptionHtInstall.h"
+#include  "OptionMemory.h"
+#include  "PlatformMemoryConfiguration.h"
+#include  "OptionMemoryInstall.h"
+#include  "OptionMemoryRecovery.h"
+#include  "OptionMemoryRecoveryInstall.h"
+#include  "OptionCpuFeaturesInstall.h"
+#include  "OptionDmi.h"
+#include  "OptionDmiInstall.h"
+#include  "OptionPstate.h"
+#include  "OptionPstateInstall.h"
+#include  "OptionWhea.h"
+#include  "OptionWheaInstall.h"
+#include  "OptionSrat.h"
+#include  "OptionSratInstall.h"
+#include  "OptionSlit.h"
+#include  "OptionSlitInstall.h"
+#include  "OptionMultiSocket.h"
+#include  "OptionMultiSocketInstall.h"
+#include  "OptionIdsInstall.h"
+#include  "OptionGfxRecovery.h"
+#include  "OptionGfxRecoveryInstall.h"
+#include  "OptionGnb.h"
+#include  "OptionGnbInstall.h"
+#include  "OptionS3ScriptInstall.h"
+#include  "OptionFchInstall.h"
+
+
+/*****************************************************************************
+ *
+ *  Generate the output structures (defaults tables)
+ *
+ ****************************************************************************/
+
+FCH_PLATFORM_POLICY  FchUserOptions = {
+  CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
+  CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
+  CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
+  CFG_ACPI_PM1_EVT_BLOCK_ADDRESS,       // CfgAcpiPm1EvtBlkAddr
+  CFG_ACPI_PM1_CNT_BLOCK_ADDRESS,       // CfgAcpiPm1CntBlkAddr
+  CFG_ACPI_PM_TMR_BLOCK_ADDRESS,        // CfgAcpiPmTmrBlkAddr
+  CFG_ACPI_CPU_CNT_BLOCK_ADDRESS,       // CfgCpuControlBlkAddr
+  CFG_ACPI_GPE0_BLOCK_ADDRESS,          // CfgAcpiGpe0BlkAddr
+  CFG_SMI_CMD_PORT_ADDRESS,             // CfgSmiCmdPortAddr
+  CFG_ACPI_PMA_CNTBLK_ADDRESS,          // CfgAcpiPmaCntBlkAddr
+  CFG_GEC_SHADOW_ROM_BASE,              // CfgGecShadowRomBase
+  CFG_WATCHDOG_TIMER_BASE,              // CfgWatchDogTimerBase
+  CFG_SPI_ROM_BASE_ADDRESS,             // CfgSpiRomBaseAddress
+  CFG_HPET_BASE_ADDRESS,                // CfgHpetBaseAddress
+  CFG_AZALIA_SSID,                      // CfgAzaliaSsid
+  CFG_SMBUS_SSID,                       // CfgSmbusSsid
+  CFG_IDE_SSID,                         // CfgIdeSsid
+  CFG_SATA_AHCI_SSID,                   // CfgSataAhciSsid
+  CFG_SATA_IDE_SSID,                    // CfgSataIdeSsid
+  CFG_SATA_RAID5_SSID,                  // CfgSataRaid5Ssid
+  CFG_SATA_RAID_SSID,                   // CfgSataRaidSsid
+  CFG_EHCI_SSID,                        // CfgEhcidSsid
+  CFG_OHCI_SSID,                        // CfgOhcidSsid
+  CFG_LPC_SSID,                         // CfgLpcSsid
+  CFG_SD_SSID,                          // CfgSdSsid
+  CFG_XHCI_SSID,                        // CfgXhciSsid
+  CFG_FCH_PORT80_BEHIND_PCIB,           // CfgFchPort80BehindPcib
+  CFG_FCH_ENABLE_ACPI_SLEEP_TRAP,       // CfgFchEnableAcpiSleepTrap
+  CFG_FCH_GPP_LINK_CONFIG,              // CfgFchGppLinkConfig
+  CFG_FCH_GPP_PORT0_PRESENT,            // CfgFchGppPort0Present
+  CFG_FCH_GPP_PORT1_PRESENT,            // CfgFchGppPort1Present
+  CFG_FCH_GPP_PORT2_PRESENT,            // CfgFchGppPort2Present
+  CFG_FCH_GPP_PORT3_PRESENT,            // CfgFchGppPort3Present
+  CFG_FCH_GPP_PORT0_HOTPLUG,            // CfgFchGppPort0HotPlug
+  CFG_FCH_GPP_PORT1_HOTPLUG,            // CfgFchGppPort1HotPlug
+  CFG_FCH_GPP_PORT2_HOTPLUG,            // CfgFchGppPort2HotPlug
+  CFG_FCH_GPP_PORT3_HOTPLUG,            // CfgFchGppPort3HotPlug
+
+  CFG_FCH_ESATA_PORT_BITMAP,            // CfgFchEsataPortBitMap
+  CFG_FCH_IR_PIN_CONTROL,               // CfgFchIrPinControl
+  CFG_FCH_SD_CLOCK_CONTROL,             // CfgFchSdClockControl
+  CFG_FCH_SCI_MAP_LIST,                 // *CfgFchSciMapControl
+  CFG_FCH_SATA_PHY_LIST,                // *CfgFchSataPhyControl
+  CFG_FCH_GPIO_CONTROL_LIST             // *CfgFchGpioControl
+};
+
+BUILD_OPT_CFG UserOptions = {
+  {                                             // AGESA version string
+    AGESA_CODE_SIGNATURE,                       //    code header Signature
+    AGESA_PACKAGE_STRING,                       //    8 character ID
+    AGESA_VERSION_STRING,                       //    12 character version string
+    0                                           //    null string terminator
+  },
+  //Build Option Area
+  OPTION_UDIMMS,                        //UDIMMS
+  OPTION_RDIMMS,                        //RDIMMS
+  OPTION_LRDIMMS,                       //LRDIMMS
+  OPTION_ECC,                           //ECC
+  OPTION_BANK_INTERLEAVE,               //BANK_INTERLEAVE
+  OPTION_DCT_INTERLEAVE,                //DCT_INTERLEAVE
+  OPTION_NODE_INTERLEAVE,               //NODE_INTERLEAVE
+  OPTION_PARALLEL_TRAINING,             //PARALLEL_TRAINING
+  OPTION_ONLINE_SPARE,                  //ONLINE_SPARE
+  OPTION_MEM_RESTORE,                   //MEM CONTEXT RESTORE
+  OPTION_MULTISOCKET,                   //MULTISOCKET
+  OPTION_ACPI_PSTATES,                  //ACPI_PSTATES
+  OPTION_CPU_PSTATE_HPC_MODE,           //High Preformace Computing (HPC) mode
+  OPTION_SRAT,                          //SRAT
+  OPTION_SLIT,                          //SLIT
+  OPTION_WHEA,                          //WHEA
+  OPTION_DMI,                           //DMI
+  OPTION_EARLY_SAMPLES,                 //EARLY_SAMPLES
+  OPTION_ADDR_TO_CS_TRANSLATOR,         //ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  CFG_PCI_MMIO_BASE,
+  CFG_PCI_MMIO_SIZE,
+  {
+    // CoreVrm
+    {
+      CFG_VRM_CURRENT_LIMIT,              // VrmCurrentLimit
+      CFG_VRM_LOW_POWER_THRESHOLD,        // VrmLowPowerThershold
+      CFG_VRM_SLEW_RATE,                  // VrmSlewRate
+      CFG_VRM_ADDITIONAL_DELAY,           // VrmAdditionalDelay
+      CFG_VRM_HIGH_SPEED_ENABLE,          // VrmHiSpeedEnable
+      CFG_VRM_INRUSH_CURRENT_LIMIT        // VrmInrushCurrentLimit
+    },
+    // NbVrm
+    {
+      CFG_VRM_NB_CURRENT_LIMIT,           // VrmNbCurrentLimit
+      CFG_VRM_NB_LOW_POWER_THRESHOLD,     // VrmNbLowPowerThershold
+      CFG_VRM_NB_SLEW_RATE,               // VrmNbSlewRate
+      CFG_VRM_NB_ADDITIONAL_DELAY,        // VrmNbAdditionalDelay
+      CFG_VRM_NB_HIGH_SPEED_ENABLE,       // VrmNbHiSpeedEnable
+      CFG_VRM_NB_INRUSH_CURRENT_LIMIT     // VrmNbInrushCurrentLimit
+    }
+  },
+  CFG_PLAT_NUM_IO_APICS,                //PlatformApicIoNumber
+  CFG_MEM_INIT_PSTATE,                  //MemoryInitPstate
+  CFG_C1E_MODE,                         //C1eMode
+  CFG_C1E_OPDATA,                       //C1ePlatformData
+  CFG_C1E_OPDATA1,                      //C1ePlatformData1
+  CFG_C1E_OPDATA2,                      //C1ePlatformData2
+  CFG_C1E_OPDATA3,                      //C1ePlatformData3
+  CFG_CSTATE_MODE,                      //CStateMode
+  CFG_CSTATE_OPDATA,                    //CStatePlatformData
+  CFG_CSTATE_IO_BASE_ADDRESS,           //CStateIoBaseAddress
+  CFG_CPB_MODE,                         //CpbMode
+  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO,    //Low power Pstate for PROCHOT, it's always set to 'AUTO'
+  CFG_CORE_LEVELING_MODE,               //CoreLevelingCofig
+  {
+    CFG_PLATFORM_CONTROL_FLOW_MODE,       // The platform's control flow mode.
+    CFG_USE_HT_ASSIST,                    // CfgUseHtAssist
+    CFG_USE_ATM_MODE,                     // CfgUseAtmMode
+    CFG_USE_32_BYTE_REFRESH,              // Display Refresh uses 32 byte packets.
+    CFG_USE_VARIABLE_MCT_ISOC_PRIORITY,   // The Memory controller will be set to Variable Isoc Priority.
+    // ADVANCED_PERFORMANCE_PROFILE
+    {
+      CFG_PERFORMANCE_HARDWARE_PREFETCHER,  // Hardware prefetcher mode
+      CFG_PERFORMANCE_SOFTWARE_PREFETCHES,  // Software prefetcher mode
+      CFG_PERFORMANCE_DRAM_PREFETCHER       // Dram prefetcher mode
+    },
+    CFG_PLATFORM_POWER_POLICY_MODE        // The platform's power policy mode.
+  },
+  (CPU_HT_DEEMPHASIS_LEVEL *)CFG_PLATFORM_DEEMPHASIS_LIST,         // Deemphasis settings
+  CFG_AMD_PLATFORM_TYPE,                //AmdPlatformType
+  CFG_AMD_PSTATE_CAP_VALUE,             // Amd pstate ceiling enabling deck
+
+  CFG_MEMORY_BUS_FREQUENCY_LIMIT,       // CfgMemoryBusFrequencyLimit
+  CFG_MEMORY_MODE_UNGANGED,             // CfgMemoryModeUnganged
+  CFG_MEMORY_QUAD_RANK_CAPABLE,         // CfgMemoryQuadRankCapable
+  CFG_MEMORY_QUADRANK_TYPE,             // CfgMemoryQuadrankType
+  CFG_MEMORY_RDIMM_CAPABLE,             // CfgMemoryRDimmCapable
+  CFG_MEMORY_LRDIMM_CAPABLE,            // CfgMemoryLRDimmCapable
+  CFG_MEMORY_UDIMM_CAPABLE,             // CfgMemoryUDimmCapable
+  CFG_MEMORY_SODIMM_CAPABLE,            // CfgMemorySodimmCapable
+  CFG_LIMIT_MEMORY_TO_BELOW_1TB,        // CfgLimitMemoryToBelow1Tb
+  CFG_MEMORY_ENABLE_BANK_INTERLEAVING,  // CfgMemoryEnableBankInterleaving
+  CFG_MEMORY_ENABLE_NODE_INTERLEAVING,  // CfgMemoryEnableNodeInterleaving
+  CFG_MEMORY_CHANNEL_INTERLEAVING,      // CfgMemoryChannelInterleaving
+  CFG_MEMORY_POWER_DOWN,                // CfgMemoryPowerDown
+  CFG_POWER_DOWN_MODE,                  // CfgPowerDownMode
+  CFG_ONLINE_SPARE,                     // CfgOnlineSpare
+  CFG_MEMORY_PARITY_ENABLE,             // CfgMemoryParityEnable
+  CFG_BANK_SWIZZLE,                     // CfgBankSwizzle
+  CFG_TIMING_MODE_SELECT,               // CfgTimingModeSelect
+  CFG_MEMORY_CLOCK_SELECT,              // CfgMemoryClockSelect
+  CFG_DQS_TRAINING_CONTROL,             // CfgDqsTrainingControl
+  CFG_IGNORE_SPD_CHECKSUM,              // CfgIgnoreSpdChecksum
+  CFG_USE_BURST_MODE,                   // CfgUseBurstMode
+  CFG_MEMORY_ALL_CLOCKS_ON,             // CfgMemoryAllClocksOn
+  CFG_ENABLE_ECC_FEATURE,               // CfgEnableEccFeature
+  CFG_ECC_REDIRECTION,                  // CfgEccRedirection
+  CFG_SCRUB_DRAM_RATE,                  // CfgScrubDramRate
+  CFG_SCRUB_L2_RATE,                    // CfgScrubL2Rate
+  CFG_SCRUB_L3_RATE,                    // CfgScrubL3Rate
+  CFG_SCRUB_IC_RATE,                    // CfgScrubIcRate
+  CFG_SCRUB_DC_RATE,                    // CfgScrubDcRate
+  CFG_ECC_SYNC_FLOOD,                   // CfgEccSyncFlood
+  CFG_ECC_SYMBOL_SIZE,                  // CfgEccSymbolSize
+  CFG_HEAP_DRAM_ADDRESS,                // CfgHeapDramAddress
+  CFG_1GB_ALIGN,                        // CfgNodeMem1GBAlign
+  CFG_S3_LATE_RESTORE,                  // CfgS3LateRestore
+  CFG_ACPI_PSTATE_PSD_INDPX,            // CfgAcpiPstateIndependent
+  (AP_MTRR_SETTINGS *) CFG_AP_MTRR_SETTINGS_LIST, // CfgApMtrrSettingsList
+  CFG_UMA_MODE,                         // CfgUmaMode
+  CFG_UMA_SIZE,                         // CfgUmaSize
+  CFG_UMA_ABOVE4G,                      // CfgUmaAbove4G
+  CFG_UMA_ALIGNMENT,                    // CfgUmaAlignment
+  CFG_PROCESSOR_SCOPE_IN_SB,            // CfgProcessorScopeInSb
+  CFG_PROCESSOR_SCOPE_NAME0,            // CfgProcessorScopeName0
+  CFG_PROCESSOR_SCOPE_NAME1,            // CfgProcessorScopeName1
+  CFG_GNB_HD_AUDIO,                     // CfgGnbHdAudio
+  CFG_ABM_SUPPORT,                      // CfgAbmSupport
+  CFG_DYNAMIC_REFRESH_RATE,             // CfgDynamicRefreshRate
+  CFG_LCD_BACK_LIGHT_CONTROL,           // CfgLcdBackLightControl
+  CFG_GNB_STEREO_3D_PINOUT,             // CfgGnb3dStereoPinIndex
+  CFG_TEMP_PCIE_MMIO_BASE_ADDRESS,      // CfgTempPcieMmioBaseAddress
+  CFG_GNB_IGPU_SSID,                    // CfgGnbIGPUSSID
+  CFG_GNB_HDAUDIO_SSID,                 // CfgGnbHDAudioSSID
+  CFG_GNB_PCIE_SSID,                    // CfgGnbPcieSSID
+  CFG_GFX_LVDS_SPREAD_SPECTRUM,         // CfgLvdsSpreadSpectrum
+  CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE,    // CfgLvdsSpreadSpectrumRate
+
+  &FchUserOptions,                      // FchBldCfg
+
+  CFG_IOMMU_SUPPORT,                    // CfgIommuSupport
+  CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE,    // CfgLvdsPowerOnSeqDigonToDe
+  CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL,  // CfgLvdsPowerOnSeqDeToVaryBl
+  CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON,    // CfgLvdsPowerOnSeqDeToDigon
+  CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE, // CfgLvdsPowerOnSeqVaryBlToDe
+  CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY,// CfgLvdsPowerOnSeqOnToOffDelay
+  CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON,// CfgLvdsPowerOnSeqVaryBlToBlon
+  CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL,// CfgLvdsPowerOnSeqBlonToVaryBl
+  CFG_LVDS_MAX_PIXEL_CLOCK_FREQ,        // CfgLvdsMaxPixelClockFreq
+  CFG_LCD_BIT_DEPTH_CONTROL_VALUE,      // CfgLcdBitDepthControlValue
+  CFG_LVDS_24BBP_PANEL_MODE,            // CfgLvds24bbpPanelMode
+  {{
+    CFG_LVDS_MISC_888_FPDI_MODE,          // CfgLvdsMiscControl
+    CFG_LVDS_MISC_DL_CH_SWAP,             // CfgLvdsMiscControl
+    CFG_LVDS_MISC_VSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
+    CFG_LVDS_MISC_HSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
+    CFG_LVDS_MISC_BLON_ACTIVE_LOW,        // CfgLvdsMiscControl
+  }},
+  CFG_PCIE_REFCLK_SPREAD_SPECTRUM,      // CfgPcieRefClkSpreadSpectrum
+  CFG_ENABLE_EXTERNAL_VREF,             // CfgExternalVrefCtlFeature
+  CFG_FORCE_TRAIN_MODE,                 // CfgForceTrainMode
+  CFG_GNB_REMOTE_DISPLAY_SUPPORT,       // CfgGnbRemoteDisplaySupport
+  (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
+  0,                                    //reserved...
+};
+
+CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
+{
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET,
+      sizeof (AMD_RESET_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResetConstructor,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_RESET_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY,
+      sizeof (AMD_RECOVERY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY,
+      sizeof (AMD_EARLY_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEarlyInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_EARLY_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV,
+      sizeof (AMD_ENV_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitEnvInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_ENV_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE,
+      sizeof (AMD_LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitLateInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor,
+      AMD_INIT_LATE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID,
+      sizeof (AMD_MID_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitMidInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_INIT_MID_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST,
+      sizeof (AMD_POST_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitPostInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor,
+      AMD_INIT_POST_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME,
+      sizeof (AMD_RESUME_PARAMS),
+      (PF_AGESA_FUNCTION) AmdInitResumeInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor,
+      AMD_INIT_RESUME_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE,
+      sizeof (AMD_S3LATE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_S3_LATE_RESTORE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE,
+      sizeof (AMD_S3SAVE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdS3SaveInitializer,
+      (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor,
+      AMD_S3_SAVE_HANDLE
+    },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK,
+      sizeof (AP_EXE_PARAMS),
+      (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer,
+      (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess,
+      AMD_LATE_RUN_AP_TASK_HANDLE
+    },
+  #endif
+  { 0, 0, NULL, NULL, 0 }
+};
+
+CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
+
+CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
+{
+  { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct },
+  { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct },
+
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+    { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RECOVERY == TRUE
+    { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery },
+  #endif
+
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly },
+  #endif
+
+  #if AGESA_ENTRY_INIT_POST == TRUE
+    { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost },
+  #endif
+
+  #if AGESA_ENTRY_INIT_ENV == TRUE
+    { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv },
+  #endif
+
+  #if AGESA_ENTRY_INIT_MID == TRUE
+    { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE == TRUE
+    { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate },
+  #endif
+
+  #if AGESA_ENTRY_INIT_S3SAVE == TRUE
+    { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save },
+  #endif
+
+  #if AGESA_ENTRY_INIT_RESUME == TRUE
+    { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume },
+  #endif
+
+  #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+    { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore },
+  #endif
+
+  #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+    { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId },
+    { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress },
+    { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore },
+    { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog },
+    { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm },
+    { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize },
+  #endif
+
+  #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
+    { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask },
+  #endif
+  { 0, NULL }
+};
+
+CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
+{
+  IDS_LATE_RUN_AP_TASK
+  // Get DMI info
+  CPU_DMI_AP_GET_TYPE4_TYPE7
+  // Probe filter enable
+  L3_FEAT_AP_DISABLE_CACHE
+  L3_FEAT_AP_ENABLE_CACHE
+  // Cpu Late Init
+  CPU_LATE_INIT_AP_TASK
+  { 0, NULL }
+};
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #if IDSOPT_IDS_ENABLED == TRUE
+    #if IDSOPT_TRACING_ENABLED == TRUE
+      #define MAKE_DBG_STR(x, y)  MAKE_AS_A_STRING(x : y)
+      CONST CHAR8 *BldOptDebugOutput[] = {
+        #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
+          //Build Option Area
+          MAKE_DBG_STR (\nOptUDIMM,             OPTION_UDIMMS)
+          MAKE_DBG_STR (\nOptRDIMM,             OPTION_RDIMMS)
+          MAKE_DBG_STR (\nOptLRDIMM,            OPTION_LRDIMMS)
+          MAKE_DBG_STR (\nOptECC,               OPTION_ECC)
+          MAKE_DBG_STR (\nOptCsIntlv,           OPTION_BANK_INTERLEAVE)
+          MAKE_DBG_STR (\nOptDctIntlv,          OPTION_DCT_INTERLEAVE)
+          MAKE_DBG_STR (\nOptNodeIntlv,         OPTION_NODE_INTERLEAVE)
+          //MAKE_DBG_STR (\nOptParallelTraining,  OPTION_PARALLEL_TRAINING)
+          MAKE_DBG_STR (\nOptOnlineSpare,       OPTION_ONLINE_SPARE)
+          MAKE_DBG_STR (\nOptAddr2CsTranslator, OPTION_ADDR_TO_CS_TRANSLATOR)
+          MAKE_DBG_STR (\nOptMemRestore,        OPTION_MEM_RESTORE)
+          MAKE_DBG_STR (\nOptMultiSocket,       OPTION_MULTISOCKET)
+          MAKE_DBG_STR (\nOptPstates,           OPTION_ACPI_PSTATES)
+          MAKE_DBG_STR (\nOptSRAT,              OPTION_SRAT)
+          MAKE_DBG_STR (\nOptSLIT,              OPTION_SLIT)
+          MAKE_DBG_STR (\nOptWHEA,              OPTION_WHEA)
+          MAKE_DBG_STR (\nOptDMI,               OPTION_DMI)
+          MAKE_DBG_STR (\nOptEarlySamples,      OPTION_EARLY_SAMPLES),
+
+          //Build Configuration Area
+          // CoreVrm
+          MAKE_DBG_STR (\nVrmCurrentLimit      , CFG_VRM_CURRENT_LIMIT)
+          MAKE_DBG_STR (\nVrmLowPowerThreshold , CFG_VRM_LOW_POWER_THRESHOLD)
+          MAKE_DBG_STR (\nVrmSlewRate          , CFG_VRM_SLEW_RATE)
+          MAKE_DBG_STR (\nVrmAdditionalDelay   , CFG_VRM_ADDITIONAL_DELAY)
+          MAKE_DBG_STR (\nVrmHiSpeedEnable     , CFG_VRM_HIGH_SPEED_ENABLE)
+          MAKE_DBG_STR (\nVrmInrushCurrentLimit, CFG_VRM_INRUSH_CURRENT_LIMIT)
+          // NbVrm
+          MAKE_DBG_STR (\nNbVrmCurrentLimit      , CFG_VRM_NB_CURRENT_LIMIT)
+          MAKE_DBG_STR (\nNbVrmLowPowerThreshold , CFG_VRM_NB_LOW_POWER_THRESHOLD)
+          MAKE_DBG_STR (\nNbVrmSlewRate          , CFG_VRM_NB_SLEW_RATE)
+          MAKE_DBG_STR (\nNbVrmAdditionalDelay   , CFG_VRM_NB_ADDITIONAL_DELAY)
+          MAKE_DBG_STR (\nNbVrmHiSpeedEnable     , CFG_VRM_NB_HIGH_SPEED_ENABLE)
+          MAKE_DBG_STR (\nNbVrmInrushCurrentLimit, CFG_VRM_NB_INRUSH_CURRENT_LIMIT),
+
+          MAKE_DBG_STR (\nNumIoApics            , CFG_PLAT_NUM_IO_APICS)
+          MAKE_DBG_STR (\nMemInitPstate         , CFG_MEM_INIT_PSTATE)
+          MAKE_DBG_STR (\nC1eMode               , CFG_C1E_MODE)
+          MAKE_DBG_STR (\nC1eOpData             , CFG_C1E_OPDATA)
+          MAKE_DBG_STR (\nC1eOpdata1            , CFG_C1E_OPDATA1)
+          MAKE_DBG_STR (\nC1eOpdata2            , CFG_C1E_OPDATA2)
+          MAKE_DBG_STR (\nC1eOpdata3            , CFG_C1E_OPDATA3)
+          MAKE_DBG_STR (\nCStateMode            , CFG_CSTATE_MODE)
+          MAKE_DBG_STR (\nCStateOpData          , CFG_CSTATE_OPDATA)
+          MAKE_DBG_STR (\nCStateIoBaseAddr      , CFG_CSTATE_IO_BASE_ADDRESS)
+          MAKE_DBG_STR (\nCpbMode               , CFG_CPB_MODE)
+          MAKE_DBG_STR (\nCoreLevelingMode      , CFG_CORE_LEVELING_MODE),
+
+          MAKE_DBG_STR (\nControlFlowMode       , CFG_PLATFORM_CONTROL_FLOW_MODE)
+          MAKE_DBG_STR (\nUseHtAssist           , CFG_USE_HT_ASSIST)
+          MAKE_DBG_STR (\nUseAtmMode            , CFG_USE_ATM_MODE)
+          MAKE_DBG_STR (\nUse32ByteRefresh      , CFG_USE_32_BYTE_REFRESH)
+          MAKE_DBG_STR (\nUseVarMctIsocPriority , CFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
+          MAKE_DBG_STR (\nPowerPolicy           , CFG_PLATFORM_POWER_POLICY_MOD)
+
+          MAKE_DBG_STR (\nDeemphasisList        , CFG_PLATFORM_DEEMPHASIS_LIST)
+
+          MAKE_DBG_STR (\nPciMmioAddr           , CFG_PCI_MMIO_BASE)
+          MAKE_DBG_STR (\nPciMmioSize           , CFG_PCI_MMIO_SIZE)
+          MAKE_DBG_STR (\nPlatformType          , CFG_AMD_PLATFORM_TYPE)
+          MAKE_DBG_STR (\nPstateCapValue        , CFG_AMD_PSTATE_CAP_VALUE),
+
+          MAKE_DBG_STR (\nMemBusFreqLimit       , CFG_MEMORY_BUS_FREQUENCY_LIMIT)
+          MAKE_DBG_STR (\nTimingModeSelect      , CFG_TIMING_MODE_SELECT)
+          MAKE_DBG_STR (\nMemoryClockSelect     , CFG_MEMORY_CLOCK_SELECT)
+
+          MAKE_DBG_STR (\nMemUnganged           , CFG_MEMORY_MODE_UNGANGED)
+          MAKE_DBG_STR (\nQRCap                 , CFG_MEMORY_QUAD_RANK_CAPABLE)
+          MAKE_DBG_STR (\nQRType                , CFG_MEMORY_QUADRANK_TYPE)
+          MAKE_DBG_STR (\nRDimmCap              , CFG_MEMORY_RDIMM_CAPABLE)
+          MAKE_DBG_STR (\nLRDimmCap             , CFG_MEMORY_LRDIMM_CAPABLE)
+          MAKE_DBG_STR (\nUDimmCap              , CFG_MEMORY_UDIMM_CAPABLE)
+          MAKE_DBG_STR (\nSODimmCap             , CFG_MEMORY_SODIMM_CAPABLE)
+          MAKE_DBG_STR (\nDqsTrainingControl    , CFG_DQS_TRAINING_CONTROL)
+          MAKE_DBG_STR (\nIgnoreSpdChecksum     , CFG_IGNORE_SPD_CHECKSUM)
+          MAKE_DBG_STR (\nUseBurstMode          , CFG_USE_BURST_MODE)
+          MAKE_DBG_STR (\nAllMemClkOn           , CFG_MEMORY_ALL_CLOCKS_ON),
+
+          MAKE_DBG_STR (\nPowerDownEn           , CFG_MEMORY_POWER_DOWN)
+          MAKE_DBG_STR (\nPowerDownMode         , CFG_POWER_DOWN_MODE)
+          MAKE_DBG_STR (\nOnlineSpare           , CFG_ONLINE_SPARE)
+          MAKE_DBG_STR (\nAddrParityEn          , CFG_MEMORY_PARITY_ENABLE)
+          MAKE_DBG_STR (\nBankSwizzle           , CFG_BANK_SWIZZLE)
+          MAKE_DBG_STR (\nLimitBelow1TB         , CFG_LIMIT_MEMORY_TO_BELOW_1TB)
+          MAKE_DBG_STR (\nCsIntlvEn             , CFG_MEMORY_ENABLE_BANK_INTERLEAVING)
+          MAKE_DBG_STR (\nNodeIntlvEn           , CFG_MEMORY_ENABLE_NODE_INTERLEAVING)
+          MAKE_DBG_STR (\nDctIntlvEn            , CFG_MEMORY_CHANNEL_INTERLEAVING),
+
+          MAKE_DBG_STR (\nUmaMode                , CFG_UMA_MODE)
+          MAKE_DBG_STR (\nUmaSize                , CFG_UMA_SIZE)
+          MAKE_DBG_STR (\nUmaAbove4G             , CFG_UMA_ABOVE4G)
+          MAKE_DBG_STR (\nUmaAlignment           , CFG_UMA_ALIGNMENT)
+
+          MAKE_DBG_STR (\nEccEn                 , CFG_ENABLE_ECC_FEATURE)
+          MAKE_DBG_STR (\nEccRedirect           , CFG_ECC_REDIRECTION)
+          MAKE_DBG_STR (\nScrubDramRate         , CFG_SCRUB_DRAM_RATE)
+          MAKE_DBG_STR (\nScrubL2Rate           , CFG_SCRUB_L2_RATE)
+          MAKE_DBG_STR (\nScrubL3Rate           , CFG_SCRUB_L3_RATE)
+          MAKE_DBG_STR (\nScrubIcRate           , CFG_SCRUB_IC_RATE)
+          MAKE_DBG_STR (\nScrubDcRate           , CFG_SCRUB_DC_RATE)
+          MAKE_DBG_STR (\nEccSyncFlood          , CFG_ECC_SYNC_FLOOD)
+          MAKE_DBG_STR (\nEccSymbolSize         , CFG_ECC_SYMBOL_SIZE)
+          MAKE_DBG_STR (\nHeapDramAddress       , CFG_HEAP_DRAM_ADDRESS)
+          MAKE_DBG_STR (\nNodeMem1GBAlign       , CFG_1GB_ALIGN),
+
+          MAKE_DBG_STR (\nS3LateRestore         , CFG_S3_LATE_RESTORE)
+          MAKE_DBG_STR (\nAcpiPstateIndependent , CFG_ACPI_PSTATE_PSD_INDPX)
+
+          MAKE_DBG_STR (\nApMtrrSettingsList     , CFG_AP_MTRR_SETTINGS_LIST)
+
+          MAKE_DBG_STR (\nProcessorScopeInSb     , CFG_PROCESSOR_SCOPE_IN_SB)
+          MAKE_DBG_STR (\nProcessorScopeName0    , CFG_PROCESSOR_SCOPE_NAME0)
+          MAKE_DBG_STR (\nProcessorScopeName1    , CFG_PROCESSOR_SCOPE_NAME1)
+          MAKE_DBG_STR (\nGnbHdAudio             , CFG_GNB_HD_AUDIO)
+          MAKE_DBG_STR (\nAbmSupport             , CFG_ABM_SUPPORT)
+          MAKE_DBG_STR (\nDynamicRefreshRate     , CFG_DYNAMIC_REFRESH_RATE)
+          MAKE_DBG_STR (\nLcdBackLightControl    , CFG_LCD_BACK_LIGHT_CONTROL)
+          MAKE_DBG_STR (\nGnb3dStereoPinIndex    , CFG_GNB_STEREO_3D_PINOUT)
+          MAKE_DBG_STR (\nTempPcieMmioBaseAddress, CFG_TEMP_PCIE_MMIO_BASE_ADDRESS),
+          MAKE_DBG_STR (\nCfgGnbIGPUSSID         , CFG_GNB_IGPU_SSID)
+          MAKE_DBG_STR (\nCfgGnbHDAudioSSID      , CFG_GNB_HDAUDIO_SSID)
+          MAKE_DBG_STR (\nCfgGnbPcieSSID         , CFG_GNB_PCIE_SSID)
+          MAKE_DBG_STR (\nCfgIommuSupport        , CFG_IOMMU_SUPPORT)
+          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum  , CFG_GFX_LVDS_SPREAD_SPECTRUM)
+          MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDigonToDe    , CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToVaryBl   , CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqDeToDigon    , CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToDe   , CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqOnToOffDelay , CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqVaryBlToBlon , CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON)
+          MAKE_DBG_STR (\nCfgLvdsPowerOnSeqBlonToVaryBl , CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL)
+          MAKE_DBG_STR (\nCfgLvdsMaxPixelClockFreq      , CFG_LVDS_MAX_PIXEL_CLOCK_FREQ)
+          MAKE_DBG_STR (\nCfgLcdBitDepthControlValue    , CFG_LCD_BIT_DEPTH_CONTROL_VALUE)
+          MAKE_DBG_STR (\nCfgLvds24bbpPanelMode         , CFG_LVDS_24BBP_PANEL_MODE),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode   , CFG_LVDS_MISC_888_FPDI_MODE),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap           , CFG_LVDS_MISC_DL_CH_SWAP),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow     , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow     , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow      , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum   , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
+          MAKE_DBG_STR (\nCfgExtVref                    , CFG_ENABLE_EXTERNAL_VREF),
+          MAKE_DBG_STR (\nCfgForceTrainMode             , CFG_FORCE_TRAIN_MODE),
+          MAKE_DBG_STR (\nCfgGnbRemoteDisplaySupport    , CFG_GNB_REMOTE_DISPLAY_CONFIG),
+          MAKE_DBG_STR (\nCfgIvrsExclusionRangeList     , CFG_IOMMU_EXCLUSION_RANGE_LIST),
+        #endif
+        NULL
+      };
+    #endif
+  #endif
+#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h
new file mode 100644
index 0000000..402b1cf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/PlatformMemoryConfiguration.h
@@ -0,0 +1,499 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Platform Specific Memory Configuration
+ *
+ * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 52513 $   @e \$Date: 2011-05-08 21:50:58 -0600 (Sun, 08 May 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
+#define _PLATFORM_MEMORY_CONFIGURATION_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+  #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ *                 PLATFORM SPECIFIC MEMORY DEFINITIONS
+ *----------------------------------------------------------------------------------------
+ */
+///
+///  Memory Speed and DIMM Population Masks
+///
+///<  DDR Speed Masks
+///<    Specifies the DDR Speed on a memory channel
+///
+#define ANY_SPEED 0xFFFFFFFF
+#define DDR400  ((UINT32) 1 << (DDR400_FREQUENCY  / 66))
+#define DDR533  ((UINT32) 1 << (DDR533_FREQUENCY  / 66))
+#define DDR667  ((UINT32) 1 << (DDR667_FREQUENCY  / 66))
+#define DDR800  ((UINT32) 1 << (DDR800_FREQUENCY  / 66))
+#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
+#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
+#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
+#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
+#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
+#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
+///
+///<  DIMM POPULATION MASKS
+///<    Specifies the DIMM Population on a channel (can be added together to specify configuration).
+///<    ex. SR_DIMM0 + SR_DIMM1                       : Single Rank Dimm in slot 0 AND Slot 1
+///<        SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1  : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
+///
+#define ANY_       0xFF       ///< Any dimm configuration the current channel
+#define SR_DIMM0   0x0001     ///< Single rank dimm in slot 0 on the current channel
+#define SR_DIMM1   0x0010     ///< Single rank dimm in slot 1 on the current channel
+#define SR_DIMM2   0x0100     ///< Single rank dimm in slot 2 on the current channel
+#define SR_DIMM3   0x1000     ///< Single rank dimm in slot 3 on the current channel
+#define DR_DIMM0   0x0002     ///< Dual rank dimm in slot 0 on the current channel
+#define DR_DIMM1   0x0020     ///< Dual rank dimm in slot 1 on the current channel
+#define DR_DIMM2   0x0200     ///< Dual rank dimm in slot 2 on the current channel
+#define DR_DIMM3   0x2000     ///< Dual rank dimm in slot 3 on the current channel
+#define QR_DIMM0   0x0004     ///< Quad rank dimm in slot 0 on the current channel
+#define QR_DIMM1   0x0040     ///< Quad rank dimm in slot 1 on the current channel
+#define QR_DIMM2   0x0400     ///< Quad rank dimm in slot 2 on the current channel
+#define QR_DIMM3   0x4000     ///< Quad rank dimm in slot 3 on the current channel
+#define LR_DIMM0   0x0001     ///< Lrdimm in slot 0 on the current channel
+#define LR_DIMM1   0x0010     ///< Lrdimm in slot 1 on the current channel
+#define LR_DIMM2   0x0100     ///< Lrdimm in slot 2 on the current channel
+#define LR_DIMM3   0x1000     ///< Lrdimm in slot 3 on the current channel
+#define ANY_DIMM0   0x000F    ///< Any Dimm combination in slot 0 on the current channel
+#define ANY_DIMM1   0x00F0    ///< Any Dimm combination in slot 1 on the current channel
+#define ANY_DIMM2   0x0F00    ///< Any Dimm combination in slot 2 on the current channel
+#define ANY_DIMM3   0xF000    ///< Any Dimm combination in slot 3 on the current channel
+///
+///<  CS POPULATION MASKS
+///<    Specifies the CS Population on a channel (can be added together to specify configuration).
+///<    ex. CS0 + CS1                       : CS0 and CS1 apply to the setting
+///
+#define CS_ANY_       0xFF       ///< Any CS configuration
+#define CS0_   0x01     ///< CS0 bit map mask
+#define CS1_   0x02     ///< CS1 bit map mask
+#define CS2_   0x04     ///< CS2 bit map mask
+#define CS3_   0x08     ///< CS3 bit map mask
+#define CS4_   0x10     ///< CS4 bit map mask
+#define CS5_   0x20     ///< CS5 bit map mask
+#define CS6_   0x40     ///< CS6 bit map mask
+#define CS7_   0x80     ///< CS7 bit map mask
+///
+///< Number of Dimms on the current channel
+///<   This is a mask used to indicate the number of dimms in a channel
+///<   They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
+///
+#define ANY_NUM     0xFF      ///< Any number of Dimms
+#define NO_DIMM     0x00      ///< No Dimms present
+#define ONE_DIMM    0x01      ///< One dimm Poulated on the current channel
+#define TWO_DIMM    0x02      ///< Two dimms Poulated on the current channel
+#define THREE_DIMM  0x04      ///< Three dimms Poulated on the current channel
+#define FOUR_DIMM   0x08      ///< Four dimms Poulated on the current channel
+
+///
+///<  DIMM VOLTAGE MASKS
+///
+#define VOLT_ANY_   0xFF      ///< Any voltage configuration
+#define VOLT1_5_    0x01      ///< Voltage 1.5V bit map mask
+#define VOLT1_35_   0x02      ///< Voltage 1.35V bit map mask
+#define VOLT1_25_   0x04      ///< Voltage 1.25V bit map mask
+
+//
+// < Not applicable
+//
+#define NA_ 0                 ///< Not applicable
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Override Definitions for Socket, Channel and Dimm
+ * This indicates where a platform override will be applied.
+ *
+ *----------------------------------------------------------------------------------------
+ */
+///
+///< SOCKET MASKS
+///<   Indicates associated processor sockets to apply override settings
+///
+#define ANY_SOCKET     0xFF    ///<  Apply to all sockets
+#define SOCKET0        0x01    ///<  Apply to socket 0
+#define SOCKET1        0x02    ///<  Apply to socket 1
+#define SOCKET2        0x04    ///<  Apply to socket 2
+#define SOCKET3        0x08    ///<  Apply to socket 3
+#define SOCKET4        0x10    ///<  Apply to socket 4
+#define SOCKET5        0x20    ///<  Apply to socket 5
+#define SOCKET6        0x40    ///<  Apply to socket 6
+#define SOCKET7        0x80    ///<  Apply to socket 7
+///
+///< CHANNEL MASKS
+///<   Indicates Memory channels where override should be applied
+///
+#define ANY_CHANNEL    0xFF    ///<  Apply to all Memory channels
+#define CHANNEL_A      0x01    ///<  Apply to Channel A
+#define CHANNEL_B      0x02    ///<  Apply to Channel B
+#define CHANNEL_C      0x04    ///<  Apply to Channel C
+#define CHANNEL_D      0x08    ///<  Apply to Channel D
+///
+/// DIMM MASKS
+///   Indicates Dimm Slots where override should be applied
+///
+#define ALL_DIMMS      0xFF    ///<  Apply to all dimm slots
+#define DIMM0          0x01    ///<  Apply to Dimm Slot 0
+#define DIMM1          0x02    ///<  Apply to Dimm Slot 1
+#define DIMM2          0x04    ///<  Apply to Dimm Slot 2
+#define DIMM3          0x08    ///<  Apply to Dimm Slot 3
+///
+/// REGISTER ACCESS MASKS
+///   Not supported as an at this time
+///
+#define ACCESS_NB0     0x0
+#define ACCESS_NB1     0x1
+#define ACCESS_NB2     0x2
+#define ACCESS_NB3     0x3
+#define ACCESS_NB4     0x4
+#define ACCESS_PHY     0x5
+#define ACCESS_DCT_XT  0x6
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Overriding Table Definitions
+ *
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PSO_END           0     ///< Table End
+#define PSO_CKE_TRI       1     ///< CKE Tristate Map
+#define PSO_ODT_TRI       2     ///< ODT Tristate Map
+#define PSO_CS_TRI        3     ///< CS Tristate Map
+#define PSO_MAX_DIMMS     4     ///< Max Dimms per channel
+#define PSO_CLK_SPEED     5     ///< Clock Speed
+#define PSO_DIMM_TYPE     6     ///< Dimm Type
+#define PSO_MEMCLK_DIS    7     ///< MEMCLK Disable Map
+#define PSO_MAX_CHNLS     8     ///< Max Channels per Socket
+#define PSO_BUS_SPEED     9     ///< Max Memory Bus Speed
+#define PSO_MAX_CHIPSELS 10     ///< Max Chipsel per Channel
+#define PSO_MEM_TECH     11     ///< Channel Memory Type
+#define PSO_WL_SEED      12     ///< DDR3 Write Levelization Seed delay
+#define PSO_RXEN_SEED    13     ///< Hardwared based RxEn seed
+#define PSO_NO_LRDIMM_CS67_ROUTING 14     ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
+#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15  ///< Soldered down SODIMM type
+#define PSO_LVDIMM_VOLT1_5_SUPPORT 16     ///< Force LvDimm voltage to 1.5V
+#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17    ///< Min RD/WR dataeye width
+#define PSO_CPU_FAMILY_TO_OVERRIDE 18     ///< CPU family signature to tell following PSO macros are CPU family dependent
+
+/*----------------------------------
+ * CONDITIONAL PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition Types
+#define CONDITIONAL_PSO_MIN   100     ///< Start of Conditional Entry Types
+#define PSO_CONDITION_AND     100     ///< And Block - Start of Conditional block
+#define PSO_CONDITION_LOC     101     ///< Location - Specify Socket, Channel, Dimms to be affected
+#define PSO_CONDITION_SPD     102     ///< SPD - Specify a specific SPD value on a Dimm on the channel
+#define PSO_CONDITION_REG     103     //   Reserved
+#define PSO_CONDITION_MAX     103     ///< End Of Condition Entry Types
+// Action Types
+#define PSO_ACTION_MIN        120     ///< Start of Action Entry Types
+#define PSO_ACTION_ODT        120     ///< ODT values to override
+#define PSO_ACTION_ADDRTMG    121     ///< Address/Timing values to override
+#define PSO_ACTION_ODCCONTROL 122     ///< ODC Control values to override
+#define PSO_ACTION_SLEWRATE   123     ///< Slew Rate value to override
+#define PSO_ACTION_REG        124     //   Reserved
+#define PSO_ACTION_SPEEDLIMIT 125     ///< Memory Bus speed Limit based on configuration
+#define PSO_ACTION_MAX        125     ///< End of Action Entry Types
+#define CONDITIONAL_PSO_MAX   139     ///< End of Conditional Entry Types
+
+/*----------------------------------
+ * TABLE DRIVEN PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition descriptor
+#define PSO_TBLDRV_CONFIG        200  ///< Configuration Descriptor
+
+// Overriding entry types
+#define PSO_TBLDRV_START         210  ///< Start of Table Driven Overriding Entry Types
+#define PSO_TBLDRV_SPEEDLIMIT    210  ///< Speed Limit
+#define PSO_TBLDRV_ODT_RTTNOM    211  ///< RttNom
+#define PSO_TBLDRV_ODT_RTTWR     212  ///< RttWr
+#define PSO_TBLDRV_ODTPATTERN    213  ///< Odt Patterns
+#define PSO_TBLDRV_ADDRTMG       214  ///< Address/Timing values
+#define PSO_TBLDRV_ODCCTRL       215  ///< ODC Control values
+#define PSO_TBLDRV_SLOWACCMODE   216  ///< Slow Access Mode
+#define PSO_TBLDRV_MR0_CL        217  ///< MR0[CL]
+#define PSO_TBLDRV_MR0_WR        218  ///< MR0[WR]
+#define PSO_TBLDRV_RC2_IBT       219  ///< RC2[IBT]
+#define PSO_TBLDRV_RC10_OPSPEED  220  ///< RC10[Opearting Speed]
+#define PSO_TBLDRV_LRDIMM_IBT    221  ///< LrDIMM IBT
+#define PSO_TBLDRV____TRAINING   222  ///< training
+#define PSO_TBLDRV_INVALID_TYPE  223  ///< Invalid Type
+#define PSO_TBLDRV_END           223  ///< End of Table Driven Overriding Entry Types
+
+/*----------------------------------------------------------------------------------------
+ *                 CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
+  PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
+  ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
+
+#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+  PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
+  , Bit7Map
+
+#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
+  PSO_CKE_TRI, 5, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map
+
+#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+  PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+  PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
+  PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
+
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
+  PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
+
+#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
+  PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
+
+#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
+  PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
+  BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
+
+#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
+  PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
+
+#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+  Byte6Seed, Byte7Seed, ByteEccSeed) \
+  PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+  Byte6Seed, Byte7Seed, ByteEccSeed
+
+#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+  Byte6Seed, Byte7Seed, ByteEccSeed) \
+  PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
+  Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
+  Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
+
+#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
+  PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
+  PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
+  PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
+
+#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
+  PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
+
+/*----------------------------------------------------------------------------------------
+ *                 CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CONDITION_AND \
+  PSO_CONDITION_AND, 0
+
+#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
+  PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
+
+#define COND_SPD(Byte, Mask, Value) \
+  PSO_CONDITION_SPD, 3, Byte, Mask, Value
+
+#define COND_REG(Access, Offset, Mask, Value) \
+ PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
+   ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
+   ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
+
+#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
+  PSO_ACTION_ODT, 9, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
+  Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
+
+#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
+  PSO_ACTION_ADDRTMG, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
+
+#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
+  PSO_ACTION_ODCCONTROL, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
+
+#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
+  PSO_ACTION_SLEWRATE, 10, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
+
+#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
+  PSO_ACTION_SPEEDLIMIT, 9, \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
+  (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
+  (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
+  (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
+
+/*----------------------------------------------------------------------------------------
+ *                 END OF CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ *                 TABLE DRIVEN OVERRIDE  MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/// Configuration sub-descriptors
+typedef enum {
+  CONFIG_GENERAL,        ///< CONFIG_GENERAL
+  CONFIG_SPEEDLIMIT,     ///< CONFIG_SPEEDLIMIT
+  CONFIG_RC2IBT,         ///< CONFIG_RC2IBT
+  CONFIG_DONT_CARE,      ///< CONFIG_DONT_CARE
+} Config_Type;
+
+// ====================
+// Configuration Macros
+// ====================
+#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
+  PSO_TBLDRV_CONFIG, 9, \
+  CONFIG_GENERAL, \
+  DimmPerCH, DimmVolt, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
+
+#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
+  PSO_TBLDRV_CONFIG, 7, \
+  CONFIG_SPEEDLIMIT, \
+  DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
+
+#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
+  PSO_TBLDRV_CONFIG, 10, \
+  CONFIG_RC2IBT, \
+  DimmPerCH, DimmVolt, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+  NumOfReg
+
+//==================
+// Overriding Macros
+//==================
+#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
+  PSO_TBLDRV_SPEEDLIMIT, 6, \
+  (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
+  (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
+  (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
+  PSO_TBLDRV_ODT_RTTNOM, 2, \
+  TgtCS, RttNom
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
+  PSO_TBLDRV_ODT_RTTWR, 2, \
+  TgtCS, RttWr
+
+#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
+  PSO_TBLDRV_ODTPATTERN, 16, \
+  ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
+  ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
+  ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
+  ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
+  PSO_TBLDRV_ADDRTMG, 4, \
+  ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
+  PSO_TBLDRV_ODCCTRL, 4, \
+  ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
+  PSO_TBLDRV_SLOWACCMODE, 1, \
+  SlowAccMode
+
+#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
+  PSO_TBLDRV_RC2_IBT, 2, \
+  TgtDimm, IBT
+
+#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
+  PSO_TBLDRV_CONFIG, 1, \
+  CONFIG_DONT_CARE, \
+  PSO_TBLDRV_MR0_CL, 3, \
+  RegValOfTcl, MR0CL13, MR0CL0
+
+#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
+  PSO_TBLDRV_CONFIG, 1, \
+  CONFIG_DONT_CARE, \
+  PSO_TBLDRV_MR0_WR, 2, \
+  RegValOfTwr, MR0WR
+
+#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
+  PSO_TBLDRV_CONFIG, 1, \
+  CONFIG_DONT_CARE, \
+  PSO_TBLDRV_RC10_OPSPEED, 5, \
+  ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+  MR10OPSPEED
+
+#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
+  PSO_TBLDRV_LRDIMM_IBT, 4, \
+  F0RC8, F1RC0, F1RC1, F1RC2
+
+#define TBLDRV_CONFIG_ENTRY____TRAINING(Training__Mode) \
+  PSO_TBLDRV____TRAINING, 1, \
+  Training__Mode
+
+//============================
+// Macros for removing entries
+//============================
+#define INVALID_CONFIG_FLAG   0x8000
+
+#define TBLDRV_INVALID_CONFIG \
+  PSO_TBLDRV_INVALID_TYPE, 0
+
+/*----------------------------------------------------------------------------------------
+ *                 END OF TABLE DRIVEN OVERRIDE  MACROS
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h b/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
new file mode 100644
index 0000000..6e0393c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/SanMarinoInstall.h
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a SanMarino platform solution
+ *
+ * This file generates the defaults tables for the "San Marino" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 59375 $   @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "OrochiPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+
+// The San Marino solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the C32 socket.
+#define INSTALL_C32_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_10_SUPPORT            TRUE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_10_SUPPORT
+    #define INSTALL_FAMILY_10_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+    #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h b/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h
new file mode 100644
index 0000000..bb152d7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/ScorpiusInstall.h
@@ -0,0 +1,115 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Scorpius platform solution
+ *
+ * This file generates the defaults tables for the "Scorpius" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 59375 $   @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                  // This is the delivery package title, "OrochiPI"
+                  // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+                  // This is the release version number of the AGESA component
+                  // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+
+// The Scorpius solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the AM3 socket.
+#define INSTALL_AM3_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_10_SUPPORT            TRUE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_10_SUPPORT
+    #define INSTALL_FAMILY_10_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+    #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f15/Include/Topology.h b/src/vendorcode/amd/agesa/f15/Include/Topology.h
new file mode 100644
index 0000000..915e13c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Topology.h
@@ -0,0 +1,163 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Topology interface definitions.
+ *
+ * Contains AMD AGESA internal interface for topology related data which
+ * is consumed by code other than HyperTransport init (and produced by
+ * HyperTransport init.)
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _TOPOLOGY_H_
+#define _TOPOLOGY_H_
+
+// Defines for limiting data structure maximum allocation and limit checking.
+#define MAX_NODES 8
+#define MAX_SOCKETS MAX_NODES
+#define MAX_DIES 2
+
+// Defines useful with package link
+#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
+#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
+#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
+
+/**
+ * Hop Count Table.
+ * This is a heap data structure.  The Hops array is filled as a size x size matrix.
+ * The unused space, if any, is all at the end.
+ */
+typedef struct {
+  UINT8 Size;                         ///< The row and column size of actual hop count data */
+  UINT8 Hops[MAX_NODES * MAX_NODES];  ///< Room for a dynamic two dimensional array of [size][size] */
+} HOP_COUNT_TABLE;
+
+/**
+ * Socket and Module to Node Map Item.
+ * Provide the Node Id and core id range for each module in each processor.
+ */
+typedef struct {
+  UINT8 Node;                 ///< The module's Node id.
+  UINT8 LowCore;              ///< The lowest processor core id for this module.
+  UINT8 HighCore;             ///< The highest processor core id for this module.
+  UINT8 EnabledComputeUnits;  ///< The value of Enabled for this processor module.
+  UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
+} SOCKET_DIE_TO_NODE_ITEM;
+
+/**
+ * Socket and Module to Node Map.
+ * This type is a pointer to the actual map, it can be used for a struct item or
+ * for typecasting a heap buffer pointer.
+ */
+typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
+
+/**
+ * Node id to Socket Die Map Item.
+ */
+typedef struct {
+  UINT8 Socket;             ///< socket of the processor containing the Node.
+  UINT8 Die;                ///< the module in the processor which is Node.
+} NODE_TO_SOCKET_DIE_ITEM;
+
+/**
+ * Node id to Socket Die Map.
+ */
+typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
+
+/**
+ * Provide AP core with socket and node context at start up.
+ * This information is posted to the AP cores using a register as a mailbox.
+ */
+typedef struct {
+  UINT32 Node:4;          ///< The node id of Core's node.
+  UINT32 Socket:4;        ///< The socket of this Core's node.
+  UINT32 Module:2;        ///< The internal module number for Core's node.
+  UINT32 ModuleType:2;    ///< Single Module = 0, Multi-module = 1.
+  UINT32 :20;             ///< Reserved
+} AP_MAIL_INFO_FIELDS;
+
+/**
+ * AP info fields can be written and read to a register.
+ */
+typedef union {
+  UINT32              Info;        ///< Just a number for register access, or opaque passing.
+  AP_MAIL_INFO_FIELDS Fields;      ///< access to the info fields.
+} AP_MAIL_INFO;
+
+/**
+ * Provide AP core with system degree and system core number at start up.
+ * This information is posted to the AP cores using a register as a mailbox.
+ */
+typedef struct {
+  UINT32 SystemDegree:3;  ///< The number of connected links
+  UINT32 :3;              ///< Reserved
+  UINT32 HeapIndex:6;     ///< The zero-based system core number
+  UINT32 :20;             ///< Reserved
+} AP_MAIL_EXT_INFO_FIELDS;
+
+/**
+ * AP info fields can be written and read to a register.
+ */
+typedef union {
+  UINT32              Info;        ///< Just a number for register access, or opaque passing.
+  AP_MAIL_EXT_INFO_FIELDS Fields;  ///< access to the info fields.
+} AP_MAIL_EXT_INFO;
+
+/**
+ * AP Info mailbox set.
+ */
+typedef struct {
+  AP_MAIL_INFO      ApMailInfo;    ///< The AP mail info
+  AP_MAIL_EXT_INFO  ApMailExtInfo; ///< The extended AP mail info
+} AP_MAILBOXES;
+
+/**
+ * Provide a northbridge to package mapping for link assignments.
+ *
+ */
+typedef struct {
+  UINT8  Link;             ///< The Node's link
+  UINT8  Module;           ///< The internal module position of Node
+  UINT8  PackageLink;      ///< The corresponding package link
+} PACKAGE_HTLINK_MAP_ITEM;
+
+/**
+ * A Processor's complete set of link assignments
+ */
+typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
+
+#endif  // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h
new file mode 100644
index 0000000..3191348
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h
@@ -0,0 +1,628 @@
+/*
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#if defined (__GNUC__)
+
+
+/* I/O intrin functions.  */
+static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
+{
+  unsigned char value;
+
+  __asm__ __volatile__ (
+    "in  %%dx, %%al"
+    : "=a" (value)
+    : "d" (Port)
+    );
+
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
+{
+  unsigned short value;
+
+  __asm__ __volatile__ (
+    "in  %%dx, %%ax"
+    : "=a" (value)
+    : "d" (Port)
+    );
+
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
+{
+  unsigned long value;
+
+  __asm__ __volatile__ (
+    "in  %%dx, %%eax"
+    : "=a" (value)
+    : "d" (Port)
+    );
+  return value;
+
+}
+
+static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
+{
+  __asm__ __volatile__ (
+    "out  %%al, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
+{
+  __asm__ __volatile__ (
+    "out  %%ax, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "out  %%eax, %%dx"
+    :
+    : "a" (Data), "d" (Port)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insb "
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insw "
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; insl "
+    : "=D" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; outsb "
+    : "=S" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+    "cld ; rep ; outsw "
+    : "=S" (Buffer), "=c" (Count)
+    : "d"(Port), "0"(Buffer), "1" (Count)
+  );
+}
+
+static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+  __asm__ __volatile__ (
+   "cld ; rep ; outsl "
+   : "=S" (Buffer), "=c" (Count)
+   : "d"(Port), "0"(Buffer), "1" (Count)
+   );
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr0, %[value]"
+    : [value] "=a" (value)
+    );
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr1, %[value]"
+    : [value] "=a" (value)
+    );
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr2, %[value]"
+    : [value] "=a" (value)
+    );
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr3, %[value]"
+    : [value] "=a" (value)
+    );
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%dr7, %[value]"
+    : [value] "=a" (value)
+    );
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
+{
+  switch (reg){
+    case 0:
+      return __readdr0 ();
+      break;
+
+    case 1:
+      return __readdr1 ();
+      break;
+
+    case 2:
+      return __readdr2 ();
+      break;
+
+    case 3:
+      return __readdr3 ();
+      break;
+
+    case 7:
+      return __readdr7 ();
+      break;
+
+    default:
+      return -1;
+  }
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr0"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr1"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr2"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr3"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%dr7"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
+{
+  switch (reg){
+    case 0:
+      __writedr0 (Data);
+      break;
+
+    case 1:
+      __writedr1 (Data);
+      break;
+
+    case 2:
+      __writedr2 (Data);
+      break;
+
+    case 3:
+      __writedr3 (Data);
+      break;
+
+    case 7:
+      __writedr7 (Data);
+      break;
+
+    default:
+      ;
+  }
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr0, %[value]"
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr2, %[value]"
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr3, %[value]"
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr4, %[value]"
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
+{
+  unsigned long value;
+  __asm__ __volatile__ (
+    "mov %%cr8, %[value]"
+    : [value] "=a" (value));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
+{
+  switch (reg){
+    case 0:
+      return __readcr0 ();
+      break;
+
+    case 2:
+      return __readcr2 ();
+      break;
+
+    case 3:
+      return __readcr3 ();
+      break;
+
+    case 4:
+      return __readcr4 ();
+      break;
+
+    case 8:
+      return __readcr8 ();
+      break;
+
+    default:
+      return -1;
+  }
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr0"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr2"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr3"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr4"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
+{
+  __asm__ __volatile__ (
+    "mov %%eax, %%cr8"
+    :
+    : "a" (Data)
+    );
+}
+
+static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
+{
+  switch (reg){
+    case 0:
+      __writecr0 (Data);
+      break;
+
+    case 2:
+      __writecr2 (Data);
+      break;
+
+    case 3:
+      __writecr3 (Data);
+      break;
+
+    case 4:
+      __writecr4 (Data);
+      break;
+
+    case 8:
+      __writecr8 (Data);
+      break;
+
+    default:
+      ;
+  }
+}
+
+static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
+{
+  UINT64 retval;
+  __asm__ __volatile__(
+       "rdmsr\n\t"
+       : "=A" (retval)
+       : "c" (msr)
+       );
+   return retval;
+}
+
+static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
+{
+  __asm__ __volatile__ (
+     "wrmsr\n\t"
+     :
+     : "c" (msr), "A" (Value)
+     );
+}
+
+static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
+{
+  UINT64 retval;
+  __asm__ __volatile__ (
+     "rdtsc"
+     : "=A" (retval));
+  return retval;
+}
+
+static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
+{
+   __asm__ __volatile__(
+     "cpuid"
+     :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
+     : "a" (InfoType)
+     );
+}
+
+
+static __inline__ __attribute__((always_inline)) void _disable(void)
+{
+  __asm__ __volatile__ ("cli");
+}
+
+
+static __inline__ __attribute__((always_inline)) void _enable(void)
+{
+  __asm__ __volatile__ ("sti");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __halt(void)
+{
+  __asm__ __volatile__ ("hlt");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __debugbreak(void)
+{
+  __asm__ __volatile__ ("int3");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __wbinvd(void)
+{
+  __asm__ __volatile__ ("wbinvd");
+}
+
+
+static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
+{
+  __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data)
+{
+  __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data)
+{
+  __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data)
+{
+  __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset)
+{
+  unsigned char value;
+  __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset)
+{
+  unsigned short value;
+  __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset)
+{
+  unsigned long long value;
+  __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+  return value;
+}
+
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
+{
+  __asm__(".byte 0x64"); // fs prefix
+  __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
+}
+
+static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
+{
+  __m128i data;
+  data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
+  _mm_stream_si128_fs2 (__A, data);
+}
+#endif
+
+static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
+{
+  __asm__(".byte 0x64"); // fs prefix
+  __builtin_ia32_clflush (__A);
+}
+static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
+{
+  __builtin_ia32_mfence ();
+}
+static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
+{
+  __builtin_ia32_sfence ();
+}
+
+static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
+{
+   __asm__ __volatile__ (
+    "cld ; rep ; stosb "
+    : "=D" (dest), "=c" (count)
+    : "a"(data), "0"(dest), "1" (count)
+  );
+}
+
+static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count)
+{
+   __asm__ __volatile__ (
+    "cld ; rep ; movsb "
+    : "=D" (dest), "=S"(data), "=c" (count)
+    : "S"(data), "0"(dest), "1" (count)
+  );
+}
+
+static __inline__ __attribute__((always_inline))
+void debug_point ( unsigned short Port,  unsigned long Data )
+{
+   __outdword (Port, Data);
+   __asm__ __volatile__ (".word 0xfeeb");
+
+}
+
+static __inline__ __attribute__((always_inline))
+void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
+{
+  UINTN  Index;
+  Index = 0;
+  __outdword (Port, Data);
+  while (Index < delayTime * 600000) {
+    __outdword (0xE0, 0);
+    Index ++;
+  }
+}
+#endif // defined (__GNUC__)
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc b/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc
new file mode 100644
index 0000000..cf111ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/PlatformMemoryConfiguration.inc
@@ -0,0 +1,670 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * AMD Platform Specific Memory Configuration
+; *
+; * Contains AMD AGESA Memory Configuration Override Interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 22910 $   @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
+;
+; ****************************************************************************
+; *
+; * Copyright (C) 2012 Advanced Micro Devices, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; *       its contributors may be used to endorse or promote products derived
+; *       from this software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *
+; **************************************************************************
+IFNDEF PSO_ENTRY
+  PSO_ENTRY           TEXTEQU    <UINT8>; < Platform Configuration Table Entry
+ENDIF
+; *****************************************************************************************
+; *
+; *                 PLATFORM SPECIFIC MEMORY DEFINITIONS
+; *
+; *****************************************************************************************
+; */
+;
+; < Memory Speed and DIMM Population Masks
+;
+; < DDR Speed Masks
+;
+ANY_SPEED     EQU     0FFFFFFFFh
+DDR400        EQU     ( 1 SHL (DDR400_FREQUENCY   / 66))
+DDR533        EQU     ( 1 SHL (DDR533_FREQUENCY   / 66))
+DDR667        EQU     ( 1 SHL (DDR667_FREQUENCY   / 66))
+DDR800        EQU     ( 1 SHL (DDR800_FREQUENCY   / 66))
+DDR1066       EQU     ( 1 SHL (DDR1066_FREQUENCY  / 66))
+DDR1333       EQU     ( 1 SHL (DDR1333_FREQUENCY  / 66))
+DDR1600       EQU     ( 1 SHL (DDR1600_FREQUENCY  / 66))
+DDR1866       EQU     ( 1 SHL (DDR1866_FREQUENCY  / 66))
+DDR2133       EQU     ( 1 SHL (DDR2133_FREQUENCY  / 66))
+DDR2400       EQU     ( 1 SHL (DDR2400_FREQUENCY  / 66))
+; <
+; <  DIMM POPULATION MASKS
+;
+ANY_        EQU      0FFh
+SR_DIMM0    EQU     0001h
+SR_DIMM1    EQU     0010h
+SR_DIMM2    EQU     0100h
+SR_DIMM3    EQU     1000h
+DR_DIMM0    EQU     0002h
+DR_DIMM1    EQU     0020h
+DR_DIMM2    EQU     0200h
+DR_DIMM3    EQU     2000h
+QR_DIMM0    EQU     0004h
+QR_DIMM1    EQU     0040h
+QR_DIMM2    EQU     0400h
+QR_DIMM3    EQU     4000h
+LR_DIMM0    EQU     0001h
+LR_DIMM1    EQU     0010h
+LR_DIMM2    EQU     0100h
+LR_DIMM3    EQU     1000h
+ANY_DIMM0   EQU     000Fh
+ANY_DIMM1   EQU     00F0h
+ANY_DIMM2   EQU     0F00h
+ANY_DIMM3   EQU    0F000h
+; <
+; <  CS POPULATION MASKS
+;
+CS_ANY_     EQU     0FFh
+CS0_        EQU      01h
+CS1_        EQU      02h
+CS2_        EQU      04h
+CS3_        EQU      08h
+CS4_        EQU      10h
+CS5_        EQU      20h
+CS6_        EQU      40h
+CS7_        EQU      80h
+;
+;  Number of Dimms
+;
+ANY_NUM      EQU    0FFh
+NO_DIMM      EQU     00h
+ONE_DIMM     EQU     01h
+TWO_DIMM     EQU     02h
+THREE_DIMM   EQU     04h
+FOUR_DIMM    EQU     08h
+;
+;  DIMM VOLTAGE MASK
+;
+VOLT_ANY_    EQU    0FFh
+VOLT1_5_     EQU     01h
+VOLT1_35_    EQU     02h
+VOLT1_25_    EQU     04h
+;
+;  NOT APPLICIABLE
+;
+NA_          EQU     00h
+; *****************************************************************************************
+; *
+; * Platform Specific Override Definitions for Socket, Channel and Dimm
+; * This indicates where a platform override will be applied.
+; *
+; *****************************************************************************************
+;
+;  SOCKET MASKS
+;
+ANY_SOCKET      EQU    0FFh
+SOCKET0         EQU     01h
+SOCKET1         EQU     02h
+SOCKET2         EQU     04h
+SOCKET3         EQU     08h
+SOCKET4         EQU     10h
+SOCKET5         EQU     20h
+SOCKET6         EQU     40h
+SOCKET7         EQU     80h
+;
+;  CHANNEL MASKS
+;
+ANY_CHANNEL     EQU    0FFh
+CHANNEL_A       EQU     01h
+CHANNEL_B       EQU     02h
+CHANNEL_C       EQU     04h
+CHANNEL_D       EQU     08h
+;
+;  DIMM MASKS
+;
+ALL_DIMMS       EQU    0FFh
+DIMM0           EQU     01h
+DIMM1           EQU     02h
+DIMM2           EQU     04h
+DIMM3           EQU     08h
+;
+;  REGISTER ACCESS MASKS
+;
+ACCESS_NB0      EQU      0h
+ACCESS_NB1      EQU     01h
+ACCESS_NB2      EQU     02h
+ACCESS_NB3      EQU     03h
+ACCESS_NB4      EQU     04h
+ACCESS_PHY      EQU     05h
+ACCESS_DCT_XT   EQU     06h
+; *****************************************************************************************
+; *
+; * Platform Specific Overriding Table Definitions
+; *
+; *****************************************************************************************
+PSO_END                EQU      0     ; < Table End
+PSO_CKE_TRI            EQU      1     ; < CKE Tristate Map
+PSO_ODT_TRI            EQU      2     ; < ODT Tristate Map
+PSO_CS_TRI             EQU      3     ; < CS Tristate Map
+PSO_MAX_DIMMS          EQU      4     ; < Max Dimms per channel
+PSO_CLK_SPEED          EQU      5     ; < Clock Speed
+PSO_DIMM_TYPE          EQU      6     ; < Dimm Type
+PSO_MEMCLK_DIS         EQU      7     ; < MEMCLK Disable Map
+PSO_MAX_CHNLS          EQU      8     ; < Max Channels per Socket
+PSO_BUS_SPEED          EQU      9     ; < Max Memory Bus Speed
+PSO_MAX_CHIPSELS       EQU     10     ; < Max Chipsel per Channel
+PSO_MEM_TECH           EQU     11     ; < Channel Memory Type
+PSO_WL_SEED            EQU     12     ; < DDR3 Write Levelization Seed delay
+PSO_RXEN_SEED          EQU     13     ; < Hardwared based RxEn seed
+PSO_NO_LRDIMM_CS67_ROUTING          EQU    14     ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
+PSO_SOLDERED_DOWN_SODIMM_TYPE       EQU    15     ; < Soldered down SODIMM type
+PSO_LVDIMM_VOLT1_5_SUPPORT          EQU    16     ; < Force LvDimm voltage to 1.5V
+PSO_MIN_RD_WR_DATAEYE_WIDTH         EQU    17     ; < Min RD/WR dataeye width
+PSO_CPU_FAMILY_TO_OVERRIDE          EQU    18     ; < CPU family signature to tell following PSO macros are CPU family dependent
+; **********************************
+; * CONDITIONAL PSO SPECIFIC ENTRIES
+; **********************************
+;  Condition Types
+CONDITIONAL_PSO_MIN   EQU     100     ; < Start of Conditional Entry Types
+PSO_CONDITION_AND     EQU     100     ; < And Block - Start of Conditional block
+PSO_CONDITION_LOC     EQU     101     ; < Location - Specify Socket, Channel, Dimms to be affected
+PSO_CONDITION_SPD     EQU     102     ; < SPD - Specify a specific SPD value on a Dimm on the channel
+PSO_CONDITION_REG     EQU     103     ;    Reserved
+PSO_CONDITION_MAX     EQU     103     ; < End Of Condition Entry Types
+;  Action Types
+PSO_ACTION_MIN        EQU     120     ; < Start of Action Entry Types
+PSO_ACTION_ODT        EQU     120     ; < ODT values to override
+PSO_ACTION_ADDRTMG    EQU     121     ; < Address/Timing values to override
+PSO_ACTION_ODCCONTROL EQU     122     ; < ODC Control values to override
+PSO_ACTION_SLEWRATE   EQU     123     ; < Slew Rate value to override
+PSO_ACTION_REG        EQU     124     ;    Reserved
+PSO_ACTION_SPEEDLIMIT EQU     125     ; < Memory Bus speed Limit based on configuration
+PSO_ACTION_MAX        EQU     125     ; < End of Action Entry Types
+CONDITIONAL_PSO_MAX   EQU     139     ; < End of Conditional Entry Types
+; **********************************
+; * TABLE DRIVEN PSO SPECIFIC ENTRIES
+; **********************************
+;  Condition descriptor
+PSO_TBLDRV_CONFIG       EQU     200     ; < Configuration Descriptor
+
+;  Overriding entry types
+PSO_TBLDRV_START        EQU     210     ; < Start of Table Driven Overriding Entry Types
+PSO_TBLDRV_SPEEDLIMIT   EQU     210     ; < Speed Limit
+PSO_TBLDRV_ODT_RTTNOM   EQU     211     ; < RttNom
+PSO_TBLDRV_ODT_RTTWR    EQU     212     ; < RttWr
+PSO_TBLDRV_ODTPATTERN   EQU     213     ; < Odt Patterns
+PSO_TBLDRV_ADDRTMG      EQU     214     ; < Address/Timing values
+PSO_TBLDRV_ODCCTRL      EQU     215     ; < ODC Control values
+PSO_TBLDRV_SLOWACCMODE  EQU     216     ; < Slow Access Mode
+PSO_TBLDRV_MR0_CL       EQU     217     ; < MR0[CL]
+PSO_TBLDRV_MR0_WR       EQU     218     ; < MR0[WR]
+PSO_TBLDRV_RC2_IBT      EQU     219     ; < RC2[IBT]
+PSO_TBLDRV_RC10_OPSPEED EQU     220     ; < RC10[Opearting Speed]
+PSO_TBLDRV_LRDIMM_IBT   EQU     221     ; < LrDIMM IBT
+PSO_TBLDRV____TRAINING   EQU     222    ; < training
+PSO_TBLDRV_INVALID_TYPE EQU     223     ; < Invalid Type
+PSO_TBLDRV_END          EQU     223     ; < End of Table Driven Overriding Entry Types
+
+
+; *****************************************************************************************
+; *
+; *                 CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
+CPU_FAMILY_TO_OVERRIDE     MACRO     CpuFamilyRevision:REQ
+ DB PSO_CPU_FAMILY_TO_OVERRIDE
+ DB 4
+ DD CpuFamilyRevision
+ENDM
+
+MEMCLK_DIS_MAP    MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
+ DB PSO_MEMCLK_DIS
+ DB 11
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ DB Bit4Map
+ DB Bit5Map
+ DB Bit6Map
+ DB Bit7Map
+ENDM
+
+CKE_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
+ DB PSO_CKE_TRI
+ DB 5
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB Bit0Map
+ DB Bit1Map
+ENDM
+
+ODT_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
+ DB PSO_ODT_TRI
+ DB 7
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ENDM
+
+CS_TRI_MAP     MACRO     SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
+ DB PSO_CS_TRI
+ DB 11
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB Bit0Map
+ DB Bit1Map
+ DB Bit2Map
+ DB Bit3Map
+ DB Bit4Map
+ DB Bit5Map
+ DB Bit6Map
+ DB Bit7Map
+ENDM
+
+NUMBER_OF_DIMMS_SUPPORTED     MACRO     SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
+ DB PSO_MAX_DIMMS
+ DB 4
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB NumberOfDimmSlotsPerChannel
+ENDM
+
+NUMBER_OF_CHIP_SELECTS_SUPPORTED     MACRO     SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
+ DB PSO_MAX_CHIPSELS
+ DB 4
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DB NumberOfChipSelectsPerChannel
+ENDM
+
+NUMBER_OF_CHANNELS_SUPPORTED     MACRO     SocketID:REQ, NumberOfChannelsPerSocket:REQ
+ DB PSO_MAX_CHNLS
+ DB 4
+ DB SocketID
+ DB ANY_CHANNEL
+ DB ALL_DIMMS
+ DB NumberOfChannelsPerSocket
+ENDM
+
+OVERRIDE_DDR_BUS_SPEED     MACRO     SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
+ PSO_BUS_SPEED
+ DB 11
+ DB SocketID
+ DB ChannelID
+ DB ALL_DIMMS
+ DD TimingMode
+ DD BusSpeed
+ENDM
+
+DRAM_TECHNOLOGY           MACRO SocketID:REQ, MemTechType:REQ
+ DB PSO_MEM_TECH
+ DB 7
+ DB SocketID
+ DB ANY_CHANNEL
+ DB ALL_DIMMS
+ DD MemTechType
+ENDM
+
+WRITE_LEVELING_SEED     MACRO SocketID:REQ, ChannelID:REQ, DimmID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
+Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
+ DB PSO_WL_SEED
+ DB 12
+ DB SocketID
+ DB ChannelID
+ DB DimmID
+ DB Byte0Seed
+ DB Byte1Seed
+ DB Byte2Seed
+ DB Byte3Seed
+ DB Byte4Seed
+ DB Byte5Seed
+ DB Byte6Seed
+ DB Byte7Seed
+ DB ByteEccSeed
+ENDM
+
+HW_RXEN_SEED     MACRO SocketID:REQ, ChannelID:REQ, DimmID: REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
+Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
+  DB PSO_RXEN_SEED
+  DB 21
+  DB SocketID
+  DB ChannelID
+  DB DimmID
+  DW Byte0Seed
+  DW Byte1Seed
+  DW Byte2Seed
+  DW Byte3Seed
+  DW Byte4Seed
+  DW Byte5Seed
+  DW Byte6Seed
+  DW Byte7Seed
+  DW ByteEccSeed
+ENDM
+
+NO_LRDIMM_CS67_ROUTING     MACRO SocketID:REQ, ChannelID:REQ
+  DB PSO_NO_LRDIMM_CS67_ROUTING
+  DB 4
+  DB SocketID
+  DB ChannelID
+  DB ALL_DIMMS
+  DB 1
+ENDM
+
+SOLDERED_DOWN_SODIMM_TYPE     MACRO SocketID:REQ, ChannelID:REQ
+  DB PSO_SOLDERED_DOWN_SODIMM_TYPE
+  DB 4
+  DB SocketID
+  DB ChannelID
+  DB ALL_DIMMS
+  DB 1
+ENDM
+
+LVDIMM_FORCE_VOLT1_5_FOR_D0    MACRO
+ DB PSO_LVDIMM_VOLT1_5_SUPPORT
+ DB 4
+ DB ANY_SOCKET
+ DB ANY_CHANNEL
+ DB ALL_DIMMS
+ DB 1
+ENDM
+
+MIN_RD_WR_DATAEYE_WIDTH        MACRO     SocketID:REQ, ChannelID:REQ, MinRdDataeyeWidth:REQ, MinWrDataeyeWidth:REQ
+  DB PSO_MIN_RD_WR_DATAEYE_WIDTH
+  DB 5
+  DB SocketID
+  DB ChannelID
+  DB ALL_DIMMS
+  DB MinRdDataeyeWidth
+  DB MinWrDataeyeWidth
+ENDM
+
+; *****************************************************************************************
+; *
+; *                 CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
+CONDITION_AND      MACRO
+ DB PSO_CONDITION_AND
+ DB 0
+ENDM
+
+COND_LOC     MACRO     SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
+ DB PSO_CONDITION_LOC
+ DB 3
+ DB SocketMsk
+ DB ChannelMsk
+ DB DimmMsk
+ENDM
+
+COND_SPD     MACRO     Byte:REQ, Mask:REQ, Value:REQ
+ DB PSO_CONDITION_SPD
+ DB 3
+ DB Byte
+ DB Mask
+ DB Value
+ENDM
+
+COND_REG     MACRO     Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
+ DB PSO_CONDITION_REG
+ DB 11
+ DB Access
+ DW Offset
+ DD Mask
+ DD Value
+ENDM
+
+ACTION_ODT     MACRO     Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
+ DB PSO_ACTION_ODT
+ DB 9
+ DD Frequency
+ DB Dimms
+ DB QrDimms
+ DB DramOdt
+ DB QrDramOdt
+ DB DramDynOdt
+ENDM
+
+ACTION_ADDRTMG     MACRO     Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
+ DB PSO_ACTION_ADDRTMG
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD AddrTmg
+ENDM
+
+ACTION_ODCCTRL     MACRO     Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
+ DB PSO_ACTION_ODCCONTROL
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD OdcCtrl
+ENDM
+
+ACTION_SLEWRATE     MACRO     Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
+ DB PSO_ACTION_SLEWRATE
+ DB 10
+ DD Frequency
+ DW DimmConfig
+ DD SlewRate
+ENDM
+
+ACTION_SPEEDLIMIT     MACRO     DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
+ DB PSO_ACTION_SPEEDLIMIT
+ DB 9
+ DW DimmConfig
+ DB Dimms
+ DW SpeedLimit15
+ DW SpeedLimit135
+ DW SpeedLimit125
+ENDM
+
+; *****************************************************************************************
+; *
+; *                 END OF CONDITIONAL OVERRIDE TABLE MACROS
+; *
+; *****************************************************************************************
+; *****************************************************************************************
+; *
+; *                 TABLE DRIVEN OVERRIDE  MACROS
+; *
+; *****************************************************************************************
+; Configuration sub-descriptors
+CONFIG_GENERAL        EQU   0
+CONFIG_SPEEDLIMIT     EQU   1
+CONFIG_RC2IBT         EQU   2
+CONFIG_DONT_CARE      EQU   3
+Config_Type  TEXTEQU  <DWORD>
+;
+; Configuration Macros
+;
+TBLDRV_CONFIG_TO_OVERRIDE     MACRO     DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 9
+ DB CONFIG_GENERAL
+ DB DimmPerCH
+ DB DimmVolt
+ DD Frequency
+ DW DimmConfig
+ENDM
+
+TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE     MACRO     DimmPerCH:REQ, Dimms:REQ, NumOfSR:REQ, NumOfDR:REQ, NumOfQR:REQ,  NumOfLRDimm:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 7
+ DB CONFIG_SPEEDLIMIT
+ DB DimmPerCH
+ DB Dimms
+ DB NumOfSR
+ DB NumOfDR
+ DB NumOfQR
+ DB NumOfLRDimm
+ENDM
+
+TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE     MACRO     DimmPerCH:REQ, Frequency:REQ, DimmVolt:REQ, DimmConfig:REQ, NumOfReg:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 10
+ DB CONFIG_RC2IBT
+ DB DimmPerCH
+ DB DimmVolt
+ DD Frequency
+ DW DimmConfig
+ DB NumOfReg
+ENDM
+;
+; Overriding Macros
+;
+TBLDRV_CONFIG_ENTRY_SPEEDLIMIT     MACRO     SpeedLimit1_5:REQ, SpeedLimit1_35:REQ, SpeedLimit1_25:REQ
+ DB PSO_TBLDRV_SPEEDLIMIT
+ DB 6
+ DW SpeedLimit1_5
+ DW SpeedLimit1_35
+ DW SpeedLimit1_25
+ENDM
+
+TBLDRV_CONFIG_ENTRY_ODT_RTTNOM     MACRO     TgtCS:REQ, RttNom:REQ
+ DB PSO_TBLDRV_ODT_RTTNOM
+ DB 2
+ DB TgtCS
+ DB RttNom
+ENDM
+
+TBLDRV_CONFIG_ENTRY_ODT_RTTWR     MACRO     TgtCS:REQ, RttWr:REQ
+ DB PSO_TBLDRV_ODT_RTTWR
+ DB 2
+ DB TgtCS
+ DB RttWr
+ENDM
+
+TBLDRV_CONFIG_ENTRY_ODTPATTERN     MACRO     RdODTCSHigh:REQ, RdODTCSLow:REQ, WrODTCSHigh:REQ, WrODTCSLow:REQ
+ DB PSO_TBLDRV_ODTPATTERN
+ DB 16
+ DD RdODTCSHigh
+ DD RdODTCSLow
+ DD WrODTCSHigh
+ DD WrODTCSLow
+ENDM
+
+TBLDRV_CONFIG_ENTRY_ADDRTMG     MACRO     AddrTmg:REQ
+ DB PSO_TBLDRV_ADDRTMG
+ DB 4
+ DD AddrTmg
+ENDM
+
+TBLDRV_CONFIG_ENTRY_ODCCTRL     MACRO     OdcCtrl:REQ
+ DB PSO_TBLDRV_ODCCTRL
+ DB 4
+ DD OdcCtrl
+ENDM
+
+TBLDRV_CONFIG_ENTRY_SLOWACCMODE     MACRO     SlowAccMode:REQ
+ DB PSO_TBLDRV_SLOWACCMODE
+ DB 1
+ DB SlowAccMode
+ENDM
+
+TBLDRV_CONFIG_ENTRY_RC2_IBT     MACRO     TgtDimm:REQ, IBT:REQ
+ DB PSO_TBLDRV_RC2_IBT
+ DB 2
+ DB TgtDimm
+ DB IBT
+ENDM
+
+TBLDRV_OVERRIDE_MR0_CL     MACRO     RegValOfTcl:REQ, MR0CL13:REQ, MR0CL0:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 1
+ DB CONFIG_DONT_CARE
+ DB PSO_TBLDRV_MR0_CL
+ DB 3
+ DB RegValOfTcl
+ DB MR0CL13
+ DB MR0CL0
+ENDM
+
+TBLDRV_OVERRIDE_MR0_WR     MACRO     RegValOfTwr:REQ, MR0WR:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 1
+ DB CONFIG_DONT_CARE
+ DB PSO_TBLDRV_MR0_WR
+ DB 2
+ DB RegValOfTcl
+ DB MR0WR
+ENDM
+
+TBLDRV_OVERRIDE_RC10_OPSPEED     MACRO     Frequency:REQ, MR10OPSPEED:REQ
+ DB PSO_TBLDRV_CONFIG
+ DB 1
+ DB CONFIG_DONT_CARE
+ DB PSO_TBLDRV_RC10_OPSPEED
+ DB 5
+ DD Frequency
+ DB MR10OPSPEED
+ENDM
+
+TBLDRV_CONFIG_ENTRY_LRDMM_IBT     MACRO     F0RC8:REQ, F1RC0:REQ, F1RC1:REQ, F1RC2:REQ
+ DB PSO_TBLDRV_LRDIMM_IBT
+ DB 4
+ DB F0RC8
+ DB F1RC0
+ DB F1RC1
+ DB F1RC2
+ENDM
+
+TBLDRV_CONFIG_ENTRY____TRAINING     MACRO     Training__Mode:REQ
+ DB PSO_TBLDRV____TRAINING
+ DB 1
+ DB Training__Mode
+ENDM
+
+;
+; Macros for removing entries
+;
+INVALID_CONFIG_FLAG   EQU   8000h
+
+TBLDRV_INVALID_CONFIG     MACRO
+ DB PSO_TBLDRV_INVALID_TYPE
+ DB 0
+ENDM
+; *****************************************************************************************
+; *
+; *                 END OF TABLE DRIVEN OVERRIDE  MACROS
+; *
+; *****************************************************************************************
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
new file mode 100644
index 0000000..7ad4bb9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/Dispatcher.c
@@ -0,0 +1,159 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD binary block interface
+ *
+ * Contains the block entry function dispatcher
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 56322 $   @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Dispatcher.h"
+#include "Options.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST DISPATCH_TABLE DispatchTable[];
+extern AMD_MODULE_HEADER mCpuModuleID;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The Dispatcher is the entry point into the AGESA software. It takes a function
+ * number as entry parameter in order to invoke the published function
+ *
+ * @param[in,out]  ConfigPtr
+ *
+ * @return   AGESA Status.
+ *
+ */
+AGESA_STATUS
+CALLCONV
+AmdAgesaDispatcher (
+  IN OUT   VOID *ConfigPtr
+  )
+{
+  AGESA_STATUS Status;
+  IMAGE_ENTRY ImageEntry;
+  MODULE_ENTRY  ModuleEntry;
+  DISPATCH_TABLE *Entry;
+  UINT32 ImageStart;
+  UINT32 ImageEnd;
+  AMD_IMAGE_HEADER* AltImagePtr;
+
+  Status = AGESA_UNSUPPORTED;
+  ImageEntry = NULL;
+  ModuleEntry = NULL;
+  ImageStart = 0xFFF00000;
+  ImageEnd = 0xFFFFFFFF;
+  AltImagePtr = NULL;
+
+  Entry = (DISPATCH_TABLE *) DispatchTable;
+  while (Entry->FunctionId != 0) {
+    if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
+      Status = Entry->EntryPoint (ConfigPtr);
+      break;
+    }
+    Entry++;
+  }
+
+  // 2. Try next dispatcher if possible, and we have not already got status back
+  if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
+    ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
+    if (ModuleEntry != NULL) {
+      Status = (*ModuleEntry) (ConfigPtr);
+    }
+  }
+
+  // 3. If not this image specific function, see if we can find alternative image instead
+  if (Status == AGESA_UNSUPPORTED) {
+    if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF  ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) {
+      ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
+      ImageEnd = ImageStart + 4;
+      // Locate/test image base that matches this component
+      AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, (CHAR8 *) AGESA_ID);
+      if (AltImagePtr != NULL) {
+        //Invoke alternative Image
+        ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
+        Status = (*ImageEntry) (ConfigPtr);
+      }
+    }
+  }
+
+  return (Status);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * The host environment interface of callout.
+ *
+ * @param[in]      Func
+ * @param[in]      Data
+ * @param[in,out]  ConfigPtr
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+CALLCONV
+AmdAgesaCallout (
+  IN       UINT32  Func,
+  IN       UINT32  Data,
+  IN OUT   VOID    *ConfigPtr
+  )
+{
+  UINT32 Result;
+  Result = AGESA_UNSUPPORTED;
+  if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
+    return Result;
+  }
+
+  Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
+  return (Result);
+}
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
new file mode 100644
index 0000000..1af03b9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/agesaCallouts.c
@@ -0,0 +1,441 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU AGESA Callout Functions
+ *
+ * Contains code to set / get useful platform information.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 50871 $   @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
+ *
+ */
+/*****************************************************************************
+ * AMD Generic Encapsulated Software Architecture
+ *
+ * Description: agesaCallouts.c - AGESA Call out functions
+ *
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                            M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Dispatcher.h"
+#include "cpuServices.h"
+#include "Ids.h"
+#include "Filecode.h"
+
+#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S - (AGESA ONLY)
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ *  Call the host environment interface to do the warm or cold reset.
+ *
+ *  @param[in]      ResetType       Warm or Cold Reset is requested
+ *  @param[in,out]  StdHeader       Config header
+ *
+ */
+VOID
+AgesaDoReset (
+  IN       UINTN             ResetType,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  AGESA_STATUS Status;
+  WARM_RESET_REQUEST Request;
+
+  // Clear warm request bit and set state bits to the current post stage
+  GetWarmResetFlag (StdHeader, &Request);
+  Request.RequestBit = FALSE;
+  Request.StateBits = Request.PostStage;
+  SetWarmResetFlag (StdHeader, &Request);
+
+  Status =  AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Call the host environment interface to allocate buffer in main system memory.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  AllocParams  Heap manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN       UINTN               FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS *AllocParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to deallocate buffer in main system memory.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  DeallocParams   Heap Manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ */
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS  *DeallocParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Call the host environment interface to Locate buffer Pointer in main system memory
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  LocateParams   Heap manager parameters
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_BUFFER_PARAMS  *LocateParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to launch APs
+ *
+ * @param[in]      ApicIdOfCore
+ * @param[in,out]  LaunchApParams
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN         ApicIdOfCore,
+  IN        AP_EXE_PARAMS *LaunchApParams
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to read an SPD's content.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  ReadSpd
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaReadSpd (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_READ_SPD_PARAMS *ReadSpd
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to read an SPD's content.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  ReadSpd
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN       UINTN                 FcnData,
+  IN OUT   AGESA_READ_SPD_PARAMS *ReadSpd
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to provide a user hook opportunity.
+ *
+ * @param[in]      FcnData
+ * @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
+
+  return Status;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to provide a user hook opportunity.
+ *
+ * @param[in]      SocketIdModuleId - (SocketID << 8) | ModuleId
+ * @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN       UINTN           SocketIdModuleId,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Call the host environment interface to provide a user hook opportunity.
+ *
+ *  @param[in]      SocketIdModuleId - (SocketID << 8) | ModuleId
+ *  @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN       UINTN           SocketIdModuleId,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Call the host environment interface to provide a user hook opportunity.
+ *
+ *  @param[in]      FcnData
+ *  @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
+
+  return Status;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Call the host environment interface to provide a user hook opportunity.
+ *
+ * @param[in]      Data
+ * @param[in,out]  IdsCalloutData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
+
+  return Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * PCIE slot reset control
+ *
+ *
+ *
+ * @param[in]  FcnData              Function data
+ * @param[in]  ResetInfo            Reset information
+ * @retval     Status               Agesa status
+ */
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+  )
+{
+  AGESA_STATUS Status;
+  Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
+  return  Status;
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * OEM callout function for FCH data override
+ *
+ *
+ * @param[in]  FchData              FCH data pointer
+ * @retval     Status               This feature is not supported
+ */
+
+AGESA_STATUS
+AgesaFchOemCallout (
+  IN      VOID              *FchData
+  )
+{
+  return AGESA_UNSUPPORTED;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Optional call to the host environment interface to change the external Vref for training.
+ *
+ * @param[in]      SocketIdModuleId - (SocketID << 8) | ModuleId
+ * @param[in,out]  MemData
+ *
+ * @return   The AGESA Status returned from the callout.
+ *
+ */
+AGESA_STATUS
+AgesaExternal__TrainVrefChange (
+  IN       UINTN           SocketIdModuleId,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  )
+{
+  AGESA_STATUS Status;
+
+  Status =  AmdAgesaCallout (AGESA_EXTERNAL____TRAIN_VREF_CHANGE, (UINT32)SocketIdModuleId, MemData);
+
+  return Status;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm b/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm
new file mode 100644
index 0000000..fcc18bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/arch2008.asm
@@ -0,0 +1,2676 @@
+;*****************************************************************************
+; AMD Generic Encapsulated Software Architecture
+;
+;  Workfile: arch2008.asm     $Revision: 50871 $    $Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
+;
+; Description: ARCH2008.ASM - AGESA Architecture 2008 Wrapper Template
+;
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+    .XLIST
+    INCLUDE agesa.inc
+    INCLUDE acwrapg.inc       ; Necessary support file as part of wrapper, including but not limited to segment start/end macros.
+    INCLUDE acwrap.inc        ; IBVs may specify host BIOS-specific include files required when building.
+    INCLUDE cpcarmac.inc
+    INCLUDE bridge32.inc
+    .LIST
+    .586p
+    .mmx
+
+
+;----------------------------------------------------------------------------
+; Local definitions
+;----------------------------------------------------------------------------
+
+sOemCallout STRUCT
+    FuncName   DD   ?         ; Call out function name
+    FuncPtr    DW   ?         ; Call out function pointer
+sOemCallout ENDS
+
+sOemEventHandler STRUCT
+    ClassCode  DD   ?         ; AGESA event log sub-class code
+    FuncPtr    DW   ?         ; Event handler function pointer
+sOemEventHandler ENDS
+
+;; A typical legacy BIOS implementation may require the E000 and F000 segments
+;; to be cached.
+EXE_CACHE_REGION_BASE_0  EQU  0E0000h
+EXE_CACHE_REGION_SIZE_0  EQU  20000h
+
+;; In this sample implementation, the B1 and B2 images are placed next to each
+;; other in the BIOS ROM to help with the maximization of cached code.
+EXE_CACHE_REGION_BASE_1  EQU  AGESA_B1_ADDRESS
+EXE_CACHE_REGION_SIZE_1  EQU  40000h
+
+;; The third region is not needed in our example.
+EXE_CACHE_REGION_BASE_2  EQU  0
+EXE_CACHE_REGION_SIZE_2  EQU  0
+
+
+;----------------------------------------------------------------------------
+;    PERSISTENT SEGMENT
+; This segment is required to be present throughout all BIOS execution.
+;----------------------------------------------------------------------------
+
+AMD_PERSISTENT_START
+
+
+;----------------------------------------------------------------------------
+; Instantiate the global descriptor table
+;----------------------------------------------------------------------------
+
+AMD_BRIDGE_32_GDT AMD_GDT         ; Instantiate the global descriptor table
+                                  ; required by the push-high mechanism.
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the persistent segment
+;----------------------------------------------------------------------------
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRet
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Near stub procedure.  Simply perform a retn instruction.
+;
+EXTERN AmdDfltRet:NEAR
+
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRetFar
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Far stub procedure.  Simply perform a retf instruction.
+;
+EXTERN AmdDfltRetFar:FAR
+
+
+;----------------------------------------------------------------------------
+; Declare the optional external routines in the persistent segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myModuleTypeMismatchHandler (Example)
+;
+;   Entry:
+;     ESI - Pointer to the EVENT_PARAMS structure of the failure.
+;     [ESI].DataParam1 - Socket
+;     [ESI].DataParam2 - DCT
+;     [ESI].DataParam3 - Channel
+;     [ESI].DataParam4 - 0x00000000
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure can be used to react to a memory module type
+;     mismatch error discovered by the AGESA code.  Actions taken
+;     may include, but are not limited to:
+;       Logging the event to NV for display later
+;       Reset, excluding the mismatch on subsequent reboot
+;       Do nothing
+;
+;   Dependencies:
+;     None
+;
+EXTERN myModuleTypeMismatchHandler(AmdDfltRet):NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   oemPlatformConfigInit (Optional)
+;
+;   Entry:
+;     EDI - 32-bit flat pointer to the PLATFORM_CONFIGURATION to be
+;           passed in to the next AGESA entry point.
+;
+;           typedef struct {
+;             IN PERFORMANCE_PROFILE PlatformProfile;
+;             IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList;
+;             IN UINT8               CoreLevelingMode;
+;             IN PLATFORM_C1E_MODES  C1eMode;
+;             IN UINT32              C1ePlatformData;
+;             IN UINT32              C1ePlatformData1;
+;             IN UINT32              C1ePlatformData2;
+;             IN UINT32              C1ePlatformData3;
+;             IN BOOLEAN             UserOptionDmi;
+;             IN BOOLEAN             UserOptionPState;
+;             IN BOOLEAN             UserOptionSrat;
+;             IN BOOLEAN             UserOptionSlit;
+;             IN BOOLEAN             UserOptionWhea;
+;             IN UINT32              PowerCeiling;
+;             IN BOOLEAN             PstateIndependent;
+;           } PLATFORM_CONFIGURATION;
+;
+;           typedef struct {
+;             IN UINT8 Socket;
+;             IN UINT8 Link;
+;             IN UINT8 LoFreq;
+;             IN UINT8 HighFreq;
+;             IN PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;
+;             IN PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;
+;           } CPU_HT_DEEMPHASIS_LEVEL;
+;
+;           typedef struct {
+;             IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;
+;             IN BOOLEAN               UseHtAssist;
+;             IN BOOLEAN               UseAtmMode;
+;             IN BOOLEAN               Use32ByteRefresh;
+;             IN BOOLEAN               UseVariableMctIsocPriority;
+;           } PERFORMANCE_PROFILE;
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Provide a single hook routine to modify the parameters of a
+;     PLATFORM_CONFIGURATION structure before any entry point that
+;     has such a structure as an input.
+;
+;   Dependencies:
+;     None
+;
+;   Example:
+;     If your platform is running in UMA mode, the following code
+;     may be added:
+;       mov  (PLATFORM_CONFIGURATION PTR [edi]).PlatformProfile.PlatformControlFlowMode, UmaDr
+;
+EXTERN oemPlatformConfigInit(AmdDfltRetFar):FAR
+
+;+---------------------------------------------------------------------------
+;
+;   oemCallout (Optional)
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The default call out router function which resides in the same
+;     segment as the push-high bridge code.
+;
+;   Dependencies:
+;     None
+;
+EXTERN oemCallout(AmdDfltRet):NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the persistent segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdBridge32
+;
+;   Entry:
+;     EDX - A Real Mode FAR pointer using seg16:Offset16 format that
+;           points to a local host environment call-out router. If
+;           this pointer is not equal to zero, then this pointer is
+;           used as the call-out router instead of the standard
+;           OemCallout. This may be useful when the call-out router
+;           is not located in the same segment as the AmdBridge32 and
+;           AmdCallout16 routines.
+;     ESI - A Flat Mode pointer (32-bit address) that points to the
+;           configuration block (AMD_CONFIG_PARAMS) for the AGESA
+;           software function.
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Execute an AGESA software function through the Push-High interface.
+;
+;   Dependencies:
+;     This procedure requires a stack. The host environment must use the
+;     provided service function to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdBridge32 PROC FAR PUBLIC
+    AMD_BRIDGE_32 AMD_GDT             ; use the macro for the body
+    ret
+AmdBridge32 ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdEnableStack
+;
+;   Entry:
+;     BX - Return address
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;     SS:ESP - Points to the private stack location for this processor core.
+;     ECX - Upon success, contains this processor core's stack size in bytes.
+;
+;   Modified:
+;     EAX, ECX, EDX, EDI, ESI, ESP, DS, ES
+;
+;   Purpose:
+;     This procedure is used to establish the stack within the host environment.
+;
+;   Dependencies:
+;     The host environment must use this procedure and not rely on any other
+;     sources to create the stack region.
+;
+AmdEnableStack PROC NEAR PUBLIC
+    AMD_ENABLE_STACK
+    ;; EAX = AGESA_SUCCESS, The stack space has been allocated for this core.
+    ;; EAX = AGESA_WARNING, The stack has already been set up.  SS:ESP is set
+    ;;       to stack top, and ECX is the stack size in bytes.
+    jmp   bx
+AmdEnableStack ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdDisableStack
+;
+;   Entry:
+;     BX - Return address
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     EAX, ECX, EDX, ESI, ESP
+;
+;   Purpose:
+;     This procedure is used to remove the pre-memory stack from within the
+;     host environment.
+;     The exit state for the BSP is described as follows:
+;       Memory region 00000-9FFFF MTRRS are set as WB memory.
+;       Processor Cache is enabled (CD bit is cleared).
+;       MTRRs used for execution cache are kept.
+;       Cache content is flushed (invalidated without write-back).
+;       Any family-specific clean-up done.
+;     The exit state for the APs is described as follows:
+;       Memory region 00000-9FFFF MTRRS are set as WB memory.
+;       Memory region A0000-DFFFF MTRRS are set as UC IO.
+;       Memory region E0000-FFFFF MTRRS are set as UC memory.
+;       MTRRs used for execution cache are cleared.
+;       Processor Cache is disabled (CD bit is set).
+;       Top-of-Memory (TOM) set to the system top of memory as determined
+;         by the memory initialization routines.
+;       System lock command is enabled.
+;       Any family-specific clean-up done.
+;
+;   Dependencies:
+;     The host environment must use this procedure and not rely on any other
+;     sources to break down the stack region.
+;     If executing in 16-bit code, the host environment must establish the
+;     "Big Real" mode of 32-bit addressing of data.
+;
+AmdDisableStack PROC NEAR PUBLIC
+    AMD_DISABLE_STACK
+    ;; EAX = AGESA_SUCCESS, The stack space has been disabled for this core.
+    jmp   bx
+AmdDisableStack ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCallout16
+;
+;   Entry:
+;     [esp+8] - Func
+;     [esp+12] - Data
+;     [esp+16] - Configuration Block
+;     [esp+4] - Return address to AGESA
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Execute callback from the push-high interface.
+;
+;   Dependencies:
+;     None
+;
+AmdCallout16 PROC FAR PUBLIC ; declare the procedure
+    AMD_CALLOUT_16 oemCallout ; use the macro for the body
+    ret
+AmdCallout16 ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdProcessAgesaErrors (Optional)
+;
+;   Entry:
+;     AL - Heap status of the AGESA entry point that was just invoked.
+;     EBX - AGESA image base address.
+;     EDX - Segment / Offset of the appropriate callout router function.
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure is used to handle any errors that may have occurred
+;     during an AGESA entry point.
+;
+;   Dependencies:
+;     None
+;
+AmdProcessAgesaErrors PROC FAR PUBLIC
+    LOCAL localCpuInterfaceBlock:EVENT_PARAMS
+
+    pushad
+    xor   edi, edi
+    mov   di, ss
+    shl   edi, 4
+    lea   esi, localCpuInterfaceBlock
+    add   esi, edi
+
+    ; Fill default config block
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.Func, AMD_READ_EVENT_LOG
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.ImageBasePtr, ebx
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.AltImageBasePtr, 0
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.HeapStatus, al
+    mov   edi, SEG AmdCallout16
+    shl   edi, 4
+    add   edi, OFFSET AmdCallout16
+    mov   (EVENT_PARAMS PTR [esi]).StdHeader.CalloutPtr, edi
+
+    ; Flush the event log searching for, and handling all monitored events
+    xor   eax, eax
+    .while (eax == 0)
+        push  edx
+        call  AmdBridge32
+        pop   edx
+        .if (eax == AGESA_SUCCESS)
+            mov   eax, (EVENT_PARAMS PTR [esi]).EventInfo
+            .if (eax != 0)
+                lea   di, cs:AgesaEventTable
+
+loopThruTable:
+                cmp   di, OFFSET cs:AgesaEventTableEnd
+                jae   unhandledEvent
+
+                cmp   eax, cs:[di].sOemEventHandler.ClassCode
+                je    FoundMatch
+                add   di, SIZEOF sOemEventHandler
+                jmp   loopThruTable
+
+FoundMatch:
+                mov   bx, cs:[di].sOemEventHandler.FuncPtr
+                call  bx
+
+unhandledEvent:
+                xor   eax, eax
+            .else
+                mov   al, 1
+            .endif
+        .endif
+    .endw
+    popad
+    ret
+
+AmdProcessAgesaErrors ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the error handler table
+;----------------------------------------------------------------------------
+
+AgesaEventTable LABEL BYTE
+    ;; Add entries as desired
+    ;;---------
+    ;; EXAMPLE
+    ;;---------
+    sOemEventHandler <MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM, OFFSET myModuleTypeMismatchHandler>
+AgesaEventTableEnd LABEL BYTE
+
+
+AMD_PERSISTENT_END
+
+
+
+
+;----------------------------------------------------------------------------
+;    RECOVERY SEGMENT
+; This segment resides in the classic 'boot-block,' and is used
+; for recovery.
+;----------------------------------------------------------------------------
+
+AMD_RECOVERY_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myReadSPDRecovery (Required for proper recovery mode operation)
+;
+;   Entry:
+;     ESI - Pointer to an AGESA_READ_SPD_PARAMS structure.
+;
+;     typedef struct {
+;       IN OUT AMD_CONFIG_PARAMS StdHeader;
+;       IN       UINT8 SocketId;
+;       IN       UINT8 MemChannelId;
+;       IN       UINT8 DimmId;
+;       IN OUT   UINT8 *Buffer;
+;       IN OUT   MEM_DATA_STRUCT *MemData;
+;     } AGESA_READ_SPD_PARAMS;
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS Indicates the SPD block for the indicated
+;                         DIMM was read successfully.
+;           AGESA_BOUNDS_CHK The specified DIMM is not present.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function and no memory initialized.
+;           AGESA_ERROR The DIMM SPD read process has generated
+;                       communication errors.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This call out reads a block of memory SPD data and places it
+;     into the provided buffer.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myReadSPDRecovery:NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitResetWrapper
+;
+;   Entry:
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     A minimal initialization of the processor core is performed. This
+;     procedure must be called by all processor cores. The code path
+;     separates the BSP from the APs and performs a separate and appropriate
+;     list of tasks for each class of core.
+;     For the BSP, the following actions are performed:
+;       Internal heap sub-system initialization
+;       Primary non-coherent HyperTransportT link initialization
+;       Return to the host environment to test for Recovery Mode.
+;     The AP processor cores do not participate in the recovery process.
+;     However, they execute this routine after being released to execute
+;     by the BSP during the main boot process. Their actions include the
+;     following:
+;       Internal heap sub-system initialization
+;       Proceed to a wait loop waiting for commands from the BSP
+;
+;     For the cache regions, up to three regions of execution cache can be
+;     allocated following the following rules:
+;     1. Once a region is allocated, it cannot be de-allocated. However, it
+;        can be expanded.
+;     2. At most, two of the three regions can be located above 1 MByte. A
+;        region failing this rule is ignored.
+;     3. All region addresses must be at or above the 0x000D0000 linear
+;        address. A region failing this rule is ignored.
+;     4. The address is aligned on a 32-KByte boundary. Starting addresses
+;        is rounded down to the nearest 32-Kbyte boundary.
+;     5. The execution cache size must be a multiple of 32 KByte. Size is
+;        rounded up to the next multiple of 32 KByte.
+;     6. A region must not span either the 1-MByte boundary or the 4-GByte
+;        boundary. Allocated size is truncated to not span the boundary.
+;     7. The granted cached execution regions, address, and size are calculated
+;        based on the available cache resources of the processor core.
+;        Allocations are made up to the limit of cache available on the
+;        installed processor.
+;     Warning: Enabling instruction cache outside of this interface can cause
+;              data corruption.
+;
+;   Dependencies:
+;     This procedure is expected to be executed soon after a system reset
+;     for the main boot path or resume path of execution.
+;
+;     This procedure requires a stack.
+;
+;     Because the heap system is not yet operational at the point of the
+;     interface call, the host environment must allocate the storage for
+;     the AMD_RESET_PARAMS structure before making the first call to
+;     AmdCreateStruct.  This is the ByHost method of allocation.
+;
+AmdInitResetWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+    local localResetParams:AMD_RESET_PARAMS
+
+    pushad
+
+    ; Prepare for the call to initialize the input parameters for AmdInitReset
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    ; Use the 'ByHost' allocation method because the heap has not been initialized as of yet.
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESET
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, ByHost
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, sizeof AMD_RESET_PARAMS
+    lea   edx, localResetParams
+    add   edx, eax
+    push  edx
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr, edx
+    mov   dx, SEG AmdCalloutRouterRecovery
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterRecovery
+    push  edx
+    call  AmdBridge32
+    pop   edx
+    pop   esi
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    ; Allocate the execution cache to maximize the amount of code in ROM that is cached.
+    ; Placing the B1 and B2 images near one another is a good way to ensure the AGESA code
+    ; is cached.
+    mov   (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_0
+    mov   (AMD_RESET_PARAMS ptr [esi]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_0
+    mov   (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_1
+    mov   (AMD_RESET_PARAMS ptr [esi + sizeof EXECUTION_CACHE_REGION]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_1
+    mov   (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheStartAddr, EXE_CACHE_REGION_BASE_2
+    mov   (AMD_RESET_PARAMS ptr [esi + (2 * sizeof EXECUTION_CACHE_REGION)]).CacheRegion.ExeCacheSize, EXE_CACHE_REGION_SIZE_2
+
+    ; Call in to the AmdInitReset entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS Early initialization completed successfully.
+    ;;  AGESA_WARNING One or more of the execution cache allocation
+    ;;                rules were violated, but an adjustment was made
+    ;;                and space was allocated.
+    ;;  AGESA_ERROR One or more of the execution cache allocation rules
+    ;;              were violated, which resulted in a requested cache
+    ;;              region to not be allocated.
+    ;;              The storage space allocated for the AMD_RESET_PARAMS
+    ;;              structure is insufficient.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RESET_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B1_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+
+    ;; Here are what the MTRRs should look like based off of the CacheRegions specified above:
+
+    ;; Fixed-Range MTRRs
+    ;; Name                 Address         Value
+    ;; ----------------     --------        ----------------
+    ;; MTRRfix4k_E0000      0000026C        0505050505050505
+    ;; MTRRfix4k_E8000      0000026D        0505050505050505
+    ;; MTRRfix4k_F0000      0000026E        0505050505050505
+    ;; MTRRfix4k_F8000      0000026F        0505050505050505
+    ;; MTRRdefType          000002FF        0000000000000C00
+    ;;
+    ;; Variable-Range MTRRs and IO Range
+    ;;       MTRRphysBase(n)             MTRRphysMask(n)
+    ;;       -----------------           -----------------
+    ;; n=0   0000000000000000            0000000000000000
+    ;; n=1   0000000000000000            0000000000000000
+    ;; n=2   0000000000000000            0000000000000000
+    ;; n=3   0000000000000000            0000000000000000
+    ;; n=4   0000000000000000            0000000000000000
+    ;; n=5   Heap Base (Varies by core)  0000FFFFFFFF0800
+    ;; n=6   AGESA_B1_ADDRESS | 6        0000FFFFFFFC0800
+    ;; n=7   0000000000000000            0000000000000000
+
+
+    ;; Because the allocation method is 'ByHost,' the call to AMD_RELEASE_STRUCT is
+    ;; not necessary.  Stack space reclamation is left up to the host BIOS.
+
+    popad
+    ret
+
+
+AmdInitResetWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitRecoveryWrapper
+;
+;   Entry:
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Perform a minimum initialization of the processor and memory to
+;     support a recovery mode flash ROM update.
+;     For the BSP, the following actions are performed:
+;       Configuration of CPU core for recovery process
+;       Minimal initialization of some memory
+;     The AP processor cores do not participate in the recovery process.
+;     No actions or tasks are performed by the AP cores for this time point.
+;
+;   Dependencies:
+;     This procedure requires a stack. The host environment must use one of
+;     the provided service functions to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdInitRecoveryWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitRecovery
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B1_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RECOVERY
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterRecovery
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterRecovery
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+
+    ; Call in to the AmdInitRecovery entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_WARNING One or more of the allocation rules were violated,
+    ;;                but an adjustment was made and space was allocated.
+    ;;  AGESA_ERROR One or more of the allocation rules were violated,
+    ;;              which resulted in a requested cache region to not be
+    ;;              allocated.
+    ;;  AGESA_FATAL No memory was found in the system.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RECOVERY_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B1_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitRecovery
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+AmdInitRecoveryWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterRecovery
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitReset and
+;     AmdInitRecovery.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterRecovery PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTableRecovery
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTableRecoveryEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterRecovery ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the recovery segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTableRecovery LABEL BYTE
+    ;; Standard B1 implementations only need the SPD reader call out function to be implemented.
+    sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDRecovery>
+CalloutRouterTableRecoveryEnd LABEL BYTE
+
+
+AMD_RECOVERY_END
+
+
+
+;----------------------------------------------------------------------------
+;    PRE-MEMORY SEGMENT
+; This segment must be uncompressed in the ROM image.
+;----------------------------------------------------------------------------
+
+AMD_PREMEM_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the recovery segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myReadSPDPremem (Required)
+;
+;   Entry:
+;     ESI - Pointer to an AGESA_READ_SPD_PARAMS structure
+;
+;     typedef struct {
+;       IN OUT AMD_CONFIG_PARAMS StdHeader;
+;       IN       UINT8 SocketId;
+;       IN       UINT8 MemChannelId;
+;       IN       UINT8 DimmId;
+;       IN OUT   UINT8 *Buffer;
+;       IN OUT   MEM_DATA_STRUCT *MemData;
+;     } AGESA_READ_SPD_PARAMS;
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS Indicates the SPD block for the indicated
+;                         DIMM was read successfully.
+;           AGESA_BOUNDS_CHK The specified DIMM is not present.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function and no memory initialized.
+;           AGESA_ERROR The DIMM SPD read process has generated
+;                       communication errors.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This call out reads a block of memory SPD data and places it
+;     into the provided buffer.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myReadSPDPremem:NEAR
+
+;+-------------------------------------------------------------------------
+;
+;   AmdDfltRetPremem
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     Near stub procedure in the prememory segment.  Simply perform a
+;     retn instruction.
+;
+EXTERN AmdDfltRetPremem:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myDoReset (Required)
+;
+;   Entry:
+;     EDX - Reset type
+;           1 - Warm reset whenever
+;           2 - Cold reset whenever
+;           3 - Warm reset immediately
+;           4 - Cold reset immediately
+;     ESI - Pointer to an AMD_CONFIG_PARAMS structure.
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This host environment function must initiate the specified type
+;     of system reset.
+;
+;     Implementation of this function by the host environment is
+;     REQUIRED. Some host environments may record this as a request
+;     allowing other elements in the system to perform some additional
+;     tasks before the actual reset is issued.
+;
+;   Dependencies:
+;     The AMD processor contains 3 bits (BiosRstDet[2:0]) in a PCI
+;     register (F0x6C Link Initialization Control Register) that
+;     indicate the reset status. These bits are reserved for use by
+;     the AGESA software and should not be modified by the host
+;     environment.
+;
+EXTERN myDoReset:NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myGetNonVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     EBX - Pointer to the non-volatile S3 context block
+;     ECX - Size in bytes of the non-volatile S3 context block
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must return the pointer to the data
+;     saved during the mySaveNonVolatileS3Context routine.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myGetNonVolatileS3Context:NEAR
+
+
+;----------------------------------------------------------------------------
+; Declare the optional external routines in the prememory segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myAgesaHookBeforeExitSelfRefresh (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 44h
+;     ESI - Pointer to a data structure containing the memory information
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display: - AGESA_TESTPOINT - 45h
+;     EAX - Contains the AGESA_STATUS return code
+;           AGESA_SUCCESS The function has completed successfully
+;           AGESA_UNSUPPORTED This function is not implemented by the host environment
+;           AGESA_WARNING A non-critical issue has occued in the host environment
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General purpose hook called before the exiting self refresh
+;     This procedure is called once per channel
+;
+;     Implementation of this function is optional for the host environment
+;     This call-out is an opportunity for the host environment to make dynamic
+;     modifications to the memory timing settings specific to the board or host
+;     environment before exiting self refresh on S3 resume
+;
+;   Dependencies:
+;     This procedure is called before the exit self refresh bit is set in the resume
+;     sequence. The host environment must initiate the OS restart process. This procedure
+;     requires a stack. The host environment must establish the stack environment prior
+;     to making the call to this procedure
+;
+EXTERN myAgesaHookBeforeExitSelfRefresh(AmdDfltRetPremem):NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myHookBeforeDramInit (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 40h
+;     ESI - Pointer to a data structure containing the memory information
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 41h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This function is not implemented by the host environment
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General-purpose hook called before the DRAM_Init bit is set. Called
+;     once per MCT
+;
+;     Implementation of this function is optional for the host environment
+;     This call-out is an opportunity for the host environment to make
+;     dynamic modifications to the memory timing settings specific to the
+;     board or host environment
+;
+;   Dependencies:
+;     None
+;
+EXTERN myHookBeforeDramInit(AmdDfltRetPremem):NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myHookBeforeDQSTraining (Optional)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - 42h
+;     ESI - Pointer to a data structure containing the memory information.
+;
+;   Exit:
+;     After returning control to AGESA, AGESA will display - AGESA_TESTPOINT - 43h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This function is not implemented by the
+;                             host environment.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     General-purpose hook called just before the memory training processes
+;     begin. Called once per MCT.
+;
+;     Implementation of this function is optional for the host environment.
+;     This call-out is an opportunity for the host environment to make
+;     dynamic modifications to the memory timing settings specific to the
+;     board or host environment.
+;
+;     The host environment may also use this call-out for some board-
+;     specific features that should be activated at this time point,
+;     such as:
+;       Low voltage DIMMs-the host environment should set the recommended
+;       voltages found in the memory data structure for each memory
+;       channel. This needs to occur before training begins.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myHookBeforeDQSTraining(AmdDfltRetPremem):NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the prememory segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitEarlyWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C4h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitEarly" AGESA will display AGESA_TESTPOINT - C5h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     A full initialization of the processor is performed. Action details
+;     differ for the BSP and AP processor cores.
+;     For the BSP, the following actions are performed:
+;       Full HyperTransportT link initialization, coherent and non-coherent
+;       Processor register loading
+;       Microcode patch load
+;       Errata workaround processing
+;       Launch all processor cores
+;       Configure the processor power management capabilities
+;       Request a warm reset if needed
+;     For the AP, the following actions are performed:
+;       Processor register loading
+;       Microcode patch load
+;       Errata workaround processing
+;       Configure the processor power management capabilities
+;
+;   Dependencies:
+;     This procedure is expected to be called before main memory initialization
+;     and before the system warm reset. Prior to this, the basic configuration
+;     done by the AmdInitReset routine must be completed.
+;
+;     This procedure requires a stack. The host environment must use one of the
+;     provided service functions to establish the stack environment prior to
+;     making the call to this procedure.
+;
+;     The processes performed at this time point require communication between
+;     processor cores.
+;
+;     The host environment must recognize that all processor cores are running
+;     in parallel and avoid activities that might interfere with the core-to-core
+;     communication, such as modifying the MTRR settings or writing to the APIC
+;     registers.
+;
+AmdInitEarlyWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitEarly
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_EARLY
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + (3 * (SIZEOF EXECUTION_CACHE_REGION)))
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitEarly entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT An HyperTransportT link CRC error was observed.
+    ;;  AGESA_WARNING One of more of the allocation rules were violated,
+    ;;                but an adjustment was made and space was allocated.
+    ;;                Or a HyperTransport device does not have the expected
+    ;;                capabilities, or unusable redundant HyperTransport
+    ;;                links were found.
+    ;;  AGESA_ERROR One or more of the allocation rules were violated, which
+    ;;              resulted in a requested cache region to not be allocated.
+    ;;              Or, a HyperTransport device failed to initialize.
+    ;;  AGESA_CRITICAL An illegal or unsupported mixture of processor types was
+    ;;                 found, or the processors installed were found to have an
+    ;;                 insufficient MP capability rating for this platform.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_EARLY_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitEarly
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitEarlyWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitPostWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitPost" AGESA will display AGESA_TESTPOINT - C6h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitPost" AGESA will display AGESA_TESTPOINT - C7h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The main system memory is located, initialized, and brought on-line.
+;     The processor(s) are prepared for full operation and control by the
+;     host environment. Action details differ for the BSP and AP processor
+;     cores.
+;     For the BSP, the following actions are performed:
+;       Full memory initialization and configuration. BSP is the master for
+;       this process and may delegate some tasks to APs.
+;       AP collection of data for use later.
+;       Transfer the HOBs including the artifact data out of the pre-memory
+;       cache storage into a temporary holding buffer in the main memory.
+;       Check the BIST status of the BSP
+;       Shut down the APs.
+;       Prepare for the host environment to begin main boot activity.
+;       Disable the pre-memory stack.
+;     For the APs, the following actions are performed:
+;       Report core identity information.
+;       Execute indicated memory initialization processes as directed.
+;       Check the BIST status of the AP
+;       Disable the pre-memory stack.
+;       Prepare to halt, giving control to host environment.
+;     The entire range of system memory is enabled for Write-Back cache.
+;     The fixed MTRRs and the variable MTRRs[7:6] are not changed in order
+;     to leave in place any flash ROM region currently set for Write-Protect
+;     execution cache.
+;
+;   Dependencies:
+;     This procedure is called after the host environment has determined that
+;     a normal boot to operating system should be performed after any system
+;     warm reset is completed and after the configuration done by AmdInitEarly
+;     has completed.
+;
+;     This procedure requires a stack. The host environment must use one of the
+;     provided service functions to establish the stack environment prior to
+;     making the call to this procedure.
+;
+;     The processes performed at this time point require communication between
+;     processor cores.  The host environment must recognize that all processor
+;     cores are running in parallel and avoid activities that might interfere
+;     with the core-to-core communication, such as modifying the MTRR settings
+;     or writing to the APIC registers.
+;
+AmdInitPostWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitPost
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_POST
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitPost entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT   A BIST error was found on one of the cores.
+    ;;  AGESA_WARNING HT Assist feature is running sub-optimally.
+    ;;  AGESA_FATAL   Memory initialization failed.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_POST_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitPost
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitPostWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitResumeWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitResume" AGESA will display AGESA_TESTPOINT - D0h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitResume" AGESA will display AGESA_TESTPOINT - D1h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure initializes or re-initializes the silicon components
+;     for the resume boot path.  For the processor, main memory is brought
+;     out of self-refresh mode. This procedure will use the context data
+;     in the NvStorage area of the input structure to re-start the main
+;     memory.  The host environment must fill the AMD_S3_PARAMS NvStorage
+;     and VolatileStorage pointers and related size elements to describe
+;     the location of the context data. Note that for this procedure, the
+;     two data areas do not need to be contained in one buffer zone, they
+;     can be anywhere in the accessible memory address space. If the host
+;     environment uses a non-volatile storage device accessed on the system
+;     address bus such as flashROM, then the context data does not need to
+;     be moved prior to this call. If the host environment uses a non-
+;     volatile storage device not located on the system address bus (e.g.
+;     CMOS or SSEPROM) then the host environment must transfer the context
+;     data to a buffer in main memory prior to calling this procedure.
+;
+;   Dependencies:
+;     The host environment must have determined that the system should take
+;     the resume path prior to calling this procedure. The configuration
+;     done by AmdInitEarly and any necessary warm reset must be complete.
+;     After this procedure, execution proceeds to general system restoration.
+;
+;     This procedure requires a stack. The host environment must use one of
+;     the provided service functions to establish the stack environment prior
+;     to making the call to this procedure.
+;
+AmdInitResumeWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitResume
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_RESUME
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PreMemHeap
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPremem
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPremem
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    call  myGetNonVolatileS3Context
+    mov   (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorage, ebx
+    mov   (AMD_RESUME_PARAMS ptr [esi]).S3DataBlock.NvStorageSize, ecx
+
+    ; Call in to the AmdInitResume entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS Re-initialization has been completed successfully.
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_RESUME_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+
+    ; Allow AGESA to free the space used by AmdInitResume
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitResumeWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterPremem
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitEarly,
+;     AmdInitPost, and AmdInitResume.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterPremem PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTablePremem
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTablePrememEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterPremem ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the prememory segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTablePremem LABEL BYTE
+    ;; Add entries as desired.
+    sOemCallout <AGESA_READ_SPD, OFFSET myReadSPDPremem>
+    sOemCallout <AGESA_HOOKBEFORE_DRAM_INIT, OFFSET myHookBeforeDramInit>
+    sOemCallout <AGESA_HOOKBEFORE_DQS_TRAINING, OFFSET myHookBeforeDQSTraining>
+    sOemCallout <AGESA_HOOKBEFORE_EXIT_SELF_REF, OFFSET myAgesaHookBeforeExitSelfRefresh>
+    sOemCallout <AGESA_DO_RESET, OFFSET myDoReset>
+    sOemCallout <AGESA_EXTERNAL____TRAIN_VREF_CHANGE, OFFSET my__TrainVrefChange>
+CalloutRouterTablePrememEnd LABEL BYTE
+
+
+
+AMD_PREMEM_END
+
+
+;----------------------------------------------------------------------------
+;    POST SEGMENT
+; This segment may be decompressed and run from system RAM.
+;----------------------------------------------------------------------------
+
+AMD_POST_START
+
+
+;----------------------------------------------------------------------------
+; Declare the external routines required in the POST segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   myAllocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E2h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E3h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The requested size of memory has been
+;                         successfully allocated.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;           AGESA_ERROR Less than the requested amount of memory
+;                       was allocated.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function must allocate a buffer of the requested size or
+;     larger. This function is required to be implemented by the host
+;     environment.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;     The host environment may need to reserve a location in the buffer
+;     to store any host environment specific value(s). The returned
+;     pointer must not include this reserved space. The host environment
+;     on the AgesaDeallocateBuffer call needs to account for the reserved
+;     space.  This reserved space may be an identifier or the "handle"
+;     used to identify the specific memory block.
+;
+EXTERN myAllocateBuffer:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myDeallocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E4h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E5h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_BOUNDS_CHK The BufferHandle is invalid. The AGESA
+;                            software continues with its function.
+;           AGESA_UNSUPPORTED This is a required function, so this
+;                             value being returned causes a critical
+;                             error response value from the AGESA
+;                             software function.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function releases a valid working buffer. This function is
+;     required for the host environment to implement.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;
+EXTERN myDeallocateBuffer:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myLocateBuffer (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E6h
+;     ESI - Pointer to an AGESA_BUFFER_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 BufferLength;
+;             IN       UINT32 BufferHandle;
+;                OUT   VOID *BufferPointer;
+;           } AGESA_BUFFER_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E7h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_BOUNDS_CHK The presented handle is invalid or the
+;                            buffer could not be located.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of memory allocation.
+;     This function must locate the buffer related to the indicated
+;     handle and return the address of the buffer and its length.
+;     This function is required to be implemented in the host
+;     environment.
+;
+;   Dependencies:
+;     The following call-outs must work together in the host system.
+;     Parameters of the same name have the same function and must be
+;     treated the same in each function:
+;       AgesaAllocateBuffer
+;       AgesaDeallocateBuffer
+;       AgesaLocateBuffer
+;       AgesaRunFcnOnAp
+;
+EXTERN myLocateBuffer:NEAR
+
+
+;+---------------------------------------------------------------------------
+;
+;   myRunFuncOnAp (Required)
+;
+;   Entry:
+;     EDX - Local APIC ID of the target core.
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must route execution to the target AP and
+;     have that AP call the AmdLateRunApTaskWrapper routine defined
+;     above.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myRunFuncOnAp:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   mySaveNonVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     EBX - Pointer to the non-volatile S3 context block
+;     ECX - Size in bytes of the non-volatile S3 context block
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must save the non-volatile data to an area
+;     that will not lose context while in the ACPI S3 sleep state, but
+;     cannot be placed in system RAM.  This data will need to be
+;     available during the call to AmdInitResume.
+;
+;   Dependencies:
+;     None
+;
+EXTERN mySaveNonVolatileS3Context:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   mySaveVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     EBX - Pointer to the volatile S3 context block
+;     ECX - Size in bytes of the volatile S3 context block
+;
+;   Exit:
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must save the volatile data to an area
+;     that will not lose context while in the ACPI S3 sleep state.
+;     This data will need to be available during the call to
+;     AmdS3LateRestore.
+;
+;   Dependencies:
+;     None
+;
+EXTERN mySaveVolatileS3Context:NEAR
+
+;+---------------------------------------------------------------------------
+;
+;   myGetVolatileS3Context (Required for proper S3 operation)
+;
+;   Entry:
+;     None
+;
+;   Exit:
+;     EBX - Pointer to the volatile S3 context block
+;     ECX - Size in bytes of the volatile S3 context block
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The host environment must return the pointer to the data
+;     saved during the mySaveVolatileS3Context routine.
+;
+;   Dependencies:
+;     None
+;
+EXTERN myGetVolatileS3Context:NEAR
+
+
+;----------------------------------------------------------------------------
+; Define the sample wrapper routines for the POST segment
+;----------------------------------------------------------------------------
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitEnvWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C8h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitEnv" AGESA will display AGESA_TESTPOINT - C9h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure uses the AgesaAllocateBuffer call-out to acquire
+;     permanent buffer space for the UEFI Hand-Off Blocks (HOBs). This
+;     is also known as, or includes, artifact data being used by the
+;     AGESA software. Upon entry to this procedure, the data is being
+;     held in a temporary memory location and it must be moved to a
+;     location controlled and protected by the host environment.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;   Dependencies:
+;     This procedure must be called after full memory is initialized and
+;     the host environment has taken control of main memory allocation.
+;     This procedure should be called before the PCI enumeration takes
+;     place and as soon as possible after the host environment memory
+;     allocation sub-system has started.
+;
+;     This procedure requires a stack. The host environment must use one
+;     of the provided service functions to establish the stack environment
+;     prior to making the call to this procedure.
+;
+AmdInitEnvWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitEnv
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_ENV
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitEnv entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ERROR The artifact data could not be found or the host
+    ;;  environment failed to allocate sufficient buffer space.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_ENV_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitEnv
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+AmdInitEnvWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitMidWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitMid" AGESA will display AGESA_TESTPOINT - CAh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitMid" AGESA will display AGESA_TESTPOINT - CBh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure call performs special configuration requirements for
+;     the graphics display hardware.
+;
+;     These actions are performed by the BSP. The APs are not assigned any
+;     tasks at this time point.
+;
+;   Dependencies:
+;     This procedure must be called after PCI enumeration has allocated
+;     resources, but before the video BIOS call is performed.
+;
+;     This procedure requires a stack. The host environment must use one
+;     of the provided service functions to establish the stack environment
+;     prior to making the call to this procedure.
+;
+AmdInitMidWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitMid
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_MID
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitMid entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_MID_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdInitMid
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+
+    popad
+    ret
+
+AmdInitMidWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdInitLateWrapper
+;
+;   Entry:
+;     On Entry to "AmdInitLate" AGESA will display AGESA_TESTPOINT - CCh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdInitLate" AGESA will display AGESA_TESTPOINT - CDh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The main purpose of this function is to generate informational
+;     data tables used by the operating system. The individual tables
+;     can be selected for generation through the user selection entries
+;     on the input parameters.
+;
+;     This routine uses the Call-Out AgesaAllocateBuffer to allocate a
+;     buffer of the proper size to contain the data.
+;
+;     The code path separates the BSP from the APs and perform a separate
+;     and appropriate list of tasks for each class of core.
+;     For the BSP, the following actions are performed:
+;       Allocate buffer space for the tables.
+;       Generate the table contents.
+;       Make sure that the CPU is in a known good power state before
+;       proceeding to boot the OS.
+;     For the APs, the following actions are performed:
+;       Final register settings preparing for entry to OS.
+;       Establish the final PState for entry to OS.
+;
+;   Dependencies:
+;     This routine is expected to be executed late in the boot sequence
+;     after main memory has been initialized, after PCI enumeration has
+;     completed, after the host environment ACPI sub-system has started,
+;     after the host environment has taken control of the APs, but just
+;     before the start of OS boot.
+;
+;     The host environment must provide the required call-outs listed in
+;     the "Required Call-Out Procedures" section of the AGESA interface
+;     specification to provide the buffer space in main memory and execute
+;     code on the APs. The host environment must register the created ACPI
+;     table in the main ACPI pointer tables. This may require moving the
+;     generated tables to another location in memory.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;     Some functions depend upon the preservation of the heap data across
+;     the shift from pre-memory environment to a post-memory environment.
+;     If that data was not preserved, then those functions cannot complete
+;     and an error is returned.
+;
+AmdInitLateWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdInitLate
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_INIT_LATE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, SIZEOF AMD_CONFIG_PARAMS
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdInitLate entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS The function has completed successfully.
+    ;;  AGESA_ALERT
+    ;;  AGESA_ERROR The system could not allocate the needed amount of
+    ;;  buffer space; or could not locate the artifact data block in
+    ;;  memory. Likely cause: the host environment may not have preserved
+    ;;  the data properly.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    push  es
+    mov   ax, SEG AmdAcpiSratPointer
+    mov   es, ax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSrat
+    mov   es:AmdAcpiSratPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSratSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiSlit
+    mov   es:AmdAcpiSlitPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSlitSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiPState
+    mov   es:AmdAcpiSsdtPointer, ebx
+    mov   eax, DWORD PTR [ebx + 4]
+    mov   es:AmdAcpiSsdtSize, eax
+
+    xor   eax, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
+    mov   es:AmdAcpiWheaMcePointer, ebx
+    mov   ax, WORD PTR [ebx]
+    mov   es:AmdAcpiWheaMceSize, eax
+
+    mov   ebx, (AMD_LATE_PARAMS ptr [esi]).AcpiWheaMce
+    mov   es:AmdAcpiWheaCmcPointer, ebx
+    mov   ax, WORD PTR [ebx]
+    mov   es:AmdAcpiWheaCmcSize, eax
+
+    mov   eax, (AMD_LATE_PARAMS ptr [esi]).DmiTable
+    mov   es:AmdDmiInfoPointer, eax
+    pop   es
+
+
+    ; Allow AGESA to free the space used by AmdInitLate
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdInitLateWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdS3SaveWrapper
+;
+;   Entry:
+;     On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CEh
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Entry to "AmdS3Save" AGESA will display AGESA_TESTPOINT - CFh
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure saves critical registers and/or configuration
+;     information for preservation across a system suspend mode. All
+;     actions needed to prepare the processor for suspend mode is
+;     performed, however this procedure does NOT initiate the suspend
+;     process. The host environment is expected to perform that duty.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;     The initializer routine will NULL out the save area pointers and
+;     sizes. This procedure will determine the size of storage needed
+;     for all the processor context, and make a call out to the environment
+;     for allocation of one buffer to store all of the data. Upon exit, the
+;     pointers and sizes within the AMD_S3_PARAMS structure will be updated
+;     with the appropriate addresses within the buffer that was allocated.
+;     The host environment is expected to then transfer the data pointed to
+;     by NvStorage to a non-volatile storage area, and the data pointed to
+;     by VolatileStorage to either a non-volatile storage area or system
+;     RAM that retains its content across suspend.
+;
+;   Dependencies:
+;     The host environment must initiate the suspend process.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;
+AmdS3SaveWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdS3Save
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3_SAVE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    ; Call in to the AmdS3Save entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS All suspend duties have been completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_S3SAVE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    mov   ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorageSize
+    .if (ecx != 0)
+        mov   ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.NvStorage
+        call  mySaveNonVolatileS3Context
+    .endif
+
+    mov   ecx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize
+    .if (ecx != 0)
+        mov   ebx, (AMD_S3SAVE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage
+        call  mySaveVolatileS3Context
+    .endif
+
+    ; Allow AGESA to free the space used by AmdS3Save
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdS3SaveWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdS3LateRestoreWrapper
+;
+;   Entry:
+;     On Entry to "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D2h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     On Exit from "AmdS3LateRestore" AGESA will display AGESA_TESTPOINT - D3h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This procedure restores the processor state, reloads critical
+;     silicon component registers, and performs any re-initialization
+;     required by the silicon. This procedure will use the context data
+;     in the VolatileStorage area of the input structure to restore the
+;     processor registers.
+;
+;     The host environment must fill the AMD_S3_PARAMS NvStorage and
+;     VolatileStorage pointers and related size elements to describe
+;     the location of the context data. Note that for this procedure,
+;     the two data areas do not need to be contained in one buffer zone,
+;     they can be anywhere in the accessible memory address space. If
+;     the host environment uses a non-volatile storage device accessed
+;     on the system address bus such as flashROM, then the context data
+;     does not need to be moved prior to this call. If the host
+;     environment uses a non-volatile storage device not located on the
+;     system address bus (e.g. CMOS or SSEPROM) then the host environment
+;     must transfer the context data to a buffer in main memory prior to
+;     calling this procedure.
+;
+;     These actions are performed by the BSP. The APs are not assigned
+;     any tasks at this time point.
+;
+;   Dependencies:
+;     This procedure is called late in the resume sequence, after the
+;     PCI control space is restored and just before resuming operating
+;     system execution.
+;
+;     The host environment must initiate the OS restart process.
+;
+;     This procedure requires a stack. The host environment must establish
+;     the stack environment prior to making the call to this procedure.
+;
+AmdS3LateRestoreWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdS3LateRestore
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_S3LATE_RESTORE
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    mov   edi, esi
+    add   edi, (SIZEOF AMD_CONFIG_PARAMS + SIZEOF AMD_S3_PARAMS)
+    call  oemPlatformConfigInit
+
+    call  myGetVolatileS3Context
+    mov   (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorage, ebx
+    mov   (AMD_S3LATE_PARAMS ptr [esi]).S3DataBlock.VolatileStorageSize, ecx
+
+    ; Call in to the AmdS3LateRestore entry point
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    ;;  AGESA_SUCCESS All resume processes have been completed successfully.
+
+    .if (eax != AGESA_SUCCESS)
+        mov   al, (AMD_S3LATE_PARAMS ptr [esi]).StdHeader.HeapStatus
+        mov   ebx, AGESA_B2_ADDRESS
+        call  AmdProcessAgesaErrors
+    .endif
+
+    ; Allow AGESA to free the space used by AmdS3LateRestore
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+AmdS3LateRestoreWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdLateRunApTaskWrapper
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - D4h
+;     DS - 0000 with 4 gigabyte access
+;     ES - 0000 with 4 gigabyte access
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - D5h
+;     None
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     This entry point is tightly connected with the "AgesaRunFcnOnAp"
+;     call out.  The AGESA software will call the call-out "AgesaRunFcnOnAp";
+;     the host environment will then call this entry point to have the AP
+;     execute the requested function. This is needed late in the Post and
+;     Resume branches for running an AP task since the AGESA software has
+;     relinquished control of the APs to the host environment.
+;
+;   Dependencies:
+;     The host environment must implement the"AgesaRunFcnOnAp" call-out
+;     and route execution to the target AP.
+;
+AmdLateRunApTaskWrapper PROC NEAR PUBLIC
+    local localCfgBlock:AMD_INTERFACE_PARAMS
+
+    pushad
+
+    ; Prepare for the call to create and initialize the input parameters for AmdLateRunApTask
+    xor   eax, eax
+    mov   ax, ss
+    shl   eax, 4
+    lea   esi, localCfgBlock
+    add   esi, eax
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.ImageBasePtr, AGESA_B2_ADDRESS
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_CREATE_STRUCT
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.AltImageBasePtr, 0
+    mov   edx, SEG AmdCallout16
+    shl   edx, 4
+    add   edx, OFFSET AmdCallout16
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.CalloutPtr, edx
+
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AgesaFunctionName, AMD_LATE_RUN_AP_TASK
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).AllocationMethod, PostMemDram
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).NewStructSize, 0
+    push  esi
+    mov   dx, SEG AmdCalloutRouterPost
+    shl   edx, 16
+    mov   dx, OFFSET AmdCalloutRouterPost
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    mov   esi, (AMD_INTERFACE_PARAMS ptr [esi]).NewStructPtr
+
+    ; The structure has been initialized.  Now modify the default settings as desired.
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApDataPointer
+    mov   es, ax
+    mov   eax, es:AmdRunCodeOnApDataPointer
+    mov   (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock, eax
+    mov   eax, es:AmdRunCodeOnApDataSize
+    mov   (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength, eax
+    mov   eax, es:AmdRunCodeOnApFunction
+    mov   (AP_EXE_PARAMS PTR [esi]).FunctionNumber, eax
+    pop   es
+
+    ; Call in to the AmdLateRunApTask dispatcher
+    push  edx
+    call  AmdBridge32
+    pop   edx
+
+    ;;  EAX = AGESA_STATUS
+    push  es
+    mov   bx, SEG AmdRunCodeOnApStatus
+    mov   es, bx
+    mov   es:AmdRunCodeOnApStatus, eax
+    pop   es
+
+    ; Allow AGESA to free the space used by AmdLateRunApTask
+    pop   esi
+    mov   (AMD_INTERFACE_PARAMS ptr [esi]).StdHeader.Func, AMD_RELEASE_STRUCT
+    call  AmdBridge32
+
+    popad
+    ret
+
+AmdLateRunApTaskWrapper ENDP
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdRunFuncOnAp (Required)
+;
+;   Entry:
+;     Prior to this hook, AGESA will display - AGESA_TESTPOINT - E8h
+;     EDX - Local APIC ID of the target core.
+;     ESI - Pointer to an AP_EXE_PARAMS structure.
+;
+;           typedef struct {
+;             IN OUT   AMD_CONFIG_PARAMS StdHeader;
+;             IN       UINT32 FunctionNumber;
+;             IN       VOID *RelatedDataBlock;
+;             IN       UINT32 RelatedDataBlockLength;
+;           } AP_EXE_PARAMS;
+;
+;   Exit:
+;     After this hook, AGESA will display - AGESA_TESTPOINT - E9h
+;     EAX - Contains the AGESA_STATUS return code.
+;           AGESA_SUCCESS The function has completed successfully.
+;           AGESA_UNSUPPORTED This is a required function, so this value
+;                             being returned causes a critical error
+;                             response value from the AGESAT software
+;                             function and no memory initialized.
+;           AGESA_WARNING The AP did not respond.
+;
+;   Modified:
+;     EAX
+;
+;   Purpose:
+;     This function is used after main memory has been initialized
+;     and the host environment has taken control of AP task dispatching.
+;     This function must cause the indicated function code to be executed
+;     upon the specified Application Processor. This procedure must be
+;     executed in 32-bit mode. This function is required to be implemented
+;     in the host environment.
+;
+;   Dependencies:
+;     The host environment must route execution to the target AP and
+;     have that AP call the"AmdLateRunApTask" entry point.
+;
+AmdRunFuncOnAp PROC NEAR PUBLIC
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApDataPointer
+    mov   es, ax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).RelatedDataBlock
+    mov   es:AmdRunCodeOnApDataPointer, eax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).RelatedBlockLength
+    mov   es:AmdRunCodeOnApDataSize, eax
+    mov   eax, (AP_EXE_PARAMS PTR [esi]).FunctionNumber
+    mov   es:AmdRunCodeOnApFunction, eax
+    mov   eax, AGESA_UNSUPPORTED
+    mov   es:AmdRunCodeOnApStatus, eax
+    pop   es
+
+    call  myRunFuncOnAp
+
+    push  es
+    mov   ax, SEG AmdRunCodeOnApStatus
+    mov   es, ax
+    mov   eax, es:AmdRunCodeOnApStatus
+    pop   es
+    ret
+AmdRunFuncOnAp ENDP
+
+
+
+;+---------------------------------------------------------------------------
+;
+;   AmdCalloutRouterPost
+;
+;   Entry:
+;     ECX - Callout function number
+;     EDX - Function-specific UINTN
+;     ESI - Pointer to function specific data
+;
+;   Exit:
+;     EAX - Contains the AGESA_STATUS return code.
+;
+;   Modified:
+;     None
+;
+;   Purpose:
+;     The call out router function for AmdInitEnv,
+;     AmdInitMid, AmdInitLate, AmdS3Save, and
+;     AmdS3LateRestore.
+;
+;   Dependencies:
+;     None
+;
+AmdCalloutRouterPost PROC FAR PUBLIC USES ECX EBX ESI BX DI DS ES
+    xor   ax, ax
+    mov   ds, ax
+    mov   es, ax
+    lea   di, cs:CalloutRouterTablePost
+    mov   eax, AGESA_UNSUPPORTED
+
+loopThruTable:
+    cmp   di, OFFSET cs:CalloutRouterTablePostEnd
+    jae   amdCpuCalloutExit ; exit with AGESA_UNSUPPORTED
+    cmp   ecx, cs:[di].sOemCallout.FuncName
+    je    FoundMatch
+    add   di, SIZEOF sOemCallout
+    jmp   loopThruTable
+
+FoundMatch:
+    mov   bx, cs:[di].sOemCallout.FuncPtr
+    call  bx
+
+amdCpuCalloutExit:
+    ret
+AmdCalloutRouterPost ENDP
+
+
+;----------------------------------------------------------------------------
+; Define the callout dispatch table for the POST segment
+;----------------------------------------------------------------------------
+
+CalloutRouterTablePost LABEL BYTE
+    ;; Add entries as desired.
+    sOemCallout <AGESA_ALLOCATE_BUFFER, OFFSET myAllocateBuffer>
+    sOemCallout <AGESA_DEALLOCATE_BUFFER, OFFSET myDeallocateBuffer>
+    sOemCallout <AGESA_LOCATE_BUFFER, OFFSET myLocateBuffer>
+    sOemCallout <AGESA_RUNFUNC_ONAP, OFFSET AmdRunFuncOnAp>
+CalloutRouterTablePostEnd LABEL BYTE
+
+AMD_POST_END
+
+
+;----------------------------------------------------------------------------
+;    CPU DATA SEGMENT
+; This segment must be writable, and present at the time that
+; AmdInitLate is run.
+;----------------------------------------------------------------------------
+
+CPU_DATASEG_START
+
+  ;; Data used to store pointers for later use by the host environment.
+  PUBLIC AmdAcpiSratPointer
+  PUBLIC AmdAcpiSratSize
+  PUBLIC AmdAcpiSlitPointer
+  PUBLIC AmdAcpiSlitSize
+  PUBLIC AmdAcpiSsdtPointer
+  PUBLIC AmdAcpiSsdtSize
+  PUBLIC AmdAcpiWheaMcePointer
+  PUBLIC AmdAcpiWheaMceSize
+  PUBLIC AmdAcpiWheaCmcPointer
+  PUBLIC AmdAcpiWheaCmcSize
+  PUBLIC AmdDmiInfoPointer
+  AmdAcpiSratPointer     DWORD ?
+  AmdAcpiSratSize        DWORD ?
+  AmdAcpiSlitPointer     DWORD ?
+  AmdAcpiSlitSize        DWORD ?
+  AmdAcpiSsdtPointer     DWORD ?
+  AmdAcpiSsdtSize        DWORD ?
+  AmdAcpiWheaMcePointer  DWORD ?
+  AmdAcpiWheaMceSize     DWORD ?
+  AmdAcpiWheaCmcPointer  DWORD ?
+  AmdAcpiWheaCmcSize     DWORD ?
+  AmdDmiInfoPointer      DWORD ?
+
+  ;; Data used for communication between the AP and the BSP.
+  PUBLIC AmdRunCodeOnApDataPointer
+  PUBLIC AmdRunCodeOnApDataSize
+  PUBLIC AmdRunCodeOnApFunction
+  PUBLIC AmdRunCodeOnApStatus
+  AmdRunCodeOnApDataPointer  DWORD ?
+  AmdRunCodeOnApDataSize     DWORD ?
+  AmdRunCodeOnApFunction     DWORD ?
+  AmdRunCodeOnApStatus       DWORD ?
+
+CPU_DATASEG_END
+
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
new file mode 100644
index 0000000..f4482ed
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c
@@ -0,0 +1,393 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Hob Transfer functions.
+ *
+ * Contains code that copy Heap to temp memory or main memory.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 56322 $   @e \$Date: 2011-07-11 16:51:42 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "GeneralServices.h"
+#include "cpuServices.h"
+#include "cpuCacheInit.h"
+#include "cpuFamilyTranslation.h"
+#include "heapManager.h"
+#include "cpuLateInit.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern BUILD_OPT_CFG UserOptions;
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CopyHeapToTempRamAtPost
+ *
+ *     This function copies BSP heap content to RAM
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+CopyHeapToTempRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *BaseAddressInCache;
+  UINT8 *BaseAddressInTempMem;
+  UINT8 *Source;
+  UINT8 *Destination;
+  UINT8  AlignTo16ByteInCache;
+  UINT8  AlignTo16ByteInTempMem;
+  UINT8  Ignored;
+  UINT32 SizeOfNodeData;
+  UINT32 TotalSize;
+  UINT32 HeapRamFixMtrr;
+  UINT32 HeapRamVariableMtrr;
+  UINT32 HeapInCacheOffset;
+  UINT64 MsrData;
+  UINT64 VariableMtrrBase;
+  UINT64 VariableMtrrMask;
+  UINTN  AmdHeapRamAddress;
+  AGESA_STATUS IgnoredStatus;
+  BUFFER_NODE *HeapInCache;
+  BUFFER_NODE *HeapInTempMem;
+  HEAP_MANAGER *HeapManagerInCache;
+  HEAP_MANAGER *HeapManagerInTempMem;
+  CACHE_INFO *CacheInfoPtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
+  //
+  //If the user define address above 1M, Mem Init has already set
+  //whole available memory as WB cacheable.
+  //
+  if (AmdHeapRamAddress < 0x100000) {
+    // Region below 1MB
+    // Fixed MTTR region
+    // turn on modification bit
+    LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+    MsrData |= 0x80000;
+    LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+
+    if (AmdHeapRamAddress >= 0xC0000) {
+      //
+      // 0xC0000 ~ 0xFFFFF
+      //
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
+      MsrData = AMD_MTRR_FIX4K_UC_DRAM;
+      LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
+      LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
+    } else if (AmdHeapRamAddress >= 0x80000) {
+      //
+      // 0x80000~0xBFFFF
+      //
+      HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
+      MsrData = AMD_MTRR_FIX16K_UC_DRAM;
+      LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
+    } else {
+      //
+      // 0x0 ~ 0x7FFFF
+      //
+      LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
+      MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
+      MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
+      LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
+    }
+
+    // Turn on MTTR enable bit and turn off modification bit
+    LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
+    MsrData |= 0x40000;
+    MsrData &= 0xFFFFFFFFFFF7FFFF;
+    LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
+  } else {
+    // Region above 1MB
+    // Variable MTTR region
+    // Get family specific cache Info
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
+
+    // Find an empty MTRRphysBase/MTRRphysMask
+    for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
+         HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
+         HeapRamVariableMtrr--) {
+      LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
+      LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
+      if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
+        break;
+      }
+    }
+    if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
+      // All variable MTRR is used.
+      ASSERT (FALSE);
+    }
+
+    // Set variable MTRR base and mask
+    // If the address ranges of two or more MTRRs overlap
+    // and if at least one of the memory types is UC, the UC memory type is used.
+    VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
+    VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
+    LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
+    LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
+  }
+  // Copying Heap content
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    TotalSize = sizeof (HEAP_MANAGER);
+    SizeOfNodeData = 0;
+    AlignTo16ByteInTempMem = 0;
+    BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr;
+    HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
+    HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
+    HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
+
+    BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
+    HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
+    HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
+
+    // copy heap from cache to temp memory.
+    // only heap with persist great than HEAP_LOCAL_CACHE will be copied.
+    // Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
+    while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
+      if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
+        AlignTo16ByteInCache = HeapInCache->PadSize;
+        AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
+        SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
+        TotalSize = (UINT32) (TotalSize  + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
+        Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
+        Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
+        LibAmdMemCopy  (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
+        LibAmdMemCopy  (Destination, Source, SizeOfNodeData, StdHeader);
+        HeapInTempMem->OffsetOfNextNode = TotalSize;
+        HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
+        HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
+        HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
+      }
+      HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
+      HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
+    }
+    // initialize heap manager
+    if (TotalSize == sizeof (HEAP_MANAGER)) {
+      // heap is empty
+      HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
+      HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
+      HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
+    } else {
+      // heap is NOT empty
+      HeapManagerInTempMem->UsedSize = TotalSize;
+      HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
+      HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
+      HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
+      HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+      HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
+    }
+    // heap signature
+    HeapManagerInCache->Signature = 0x00000000;
+    HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
+    // Free space node
+    HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
+    HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  }
+  return AGESA_SUCCESS;
+}
+
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *  CopyHeapToMainRamAtPost
+ *
+ *    This function copies Temp Ram heap content to Main Ram
+ *
+ *    @param[in,out]   StdHeader   - Pointer to AMD_CONFIG_PARAMS struct.
+ *
+ *    @retval          AGESA_STATUS
+ *
+ */
+AGESA_STATUS
+CopyHeapToMainRamAtPost (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *BaseAddressInTempMem;
+  UINT8 *BaseAddressInMainMem;
+  UINT8 *Source;
+  UINT8 *Destination;
+  UINT8  AlignTo16ByteInTempMem;
+  UINT8  AlignTo16ByteInMainMem;
+  UINT8  Ignored;
+  UINT32 SizeOfNodeData;
+  UINT32 TotalSize;
+  UINT32 HeapInTempMemOffset;
+  UINT32 HeapRamVariableMtrr;
+  UINT64 VariableMtrrBase;
+  UINT64 VariableMtrrMask;
+  AGESA_STATUS IgnoredStatus;
+  BUFFER_NODE *HeapInTempMem;
+  BUFFER_NODE *HeapInMainMem;
+  HEAP_MANAGER *HeapManagerInTempMem;
+  HEAP_MANAGER *HeapManagerInMainMem;
+  AGESA_BUFFER_PARAMS AgesaBuffer;
+  CACHE_INFO *CacheInfoPtr;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  if (IsBsp (StdHeader, &IgnoredStatus)) {
+    TotalSize = sizeof (HEAP_MANAGER);
+    SizeOfNodeData = 0;
+    AlignTo16ByteInMainMem = 0;
+    BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr;
+    HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr;
+    HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
+    HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
+
+    AgesaBuffer.StdHeader = *StdHeader;
+    AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
+    AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
+    if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
+      return AGESA_ERROR;
+    }
+    BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
+    HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
+    HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
+    LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
+    // copy heap from temp memory to main memory.
+    // only heap with persist great than HEAP_TEMP_MEM will be copied.
+    // Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
+    while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
+      if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
+        AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
+        AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem  + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
+        SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
+        TotalSize = (UINT32) (TotalSize  + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
+        Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
+        Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
+        LibAmdMemCopy  (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
+        LibAmdMemCopy  (Destination, Source, SizeOfNodeData, StdHeader);
+        HeapInMainMem->OffsetOfNextNode = TotalSize;
+        HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
+        HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
+        HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
+      }
+      HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
+      HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
+    }
+    // initialize heap manager
+    if (TotalSize == sizeof (HEAP_MANAGER)) {
+      // heap is empty
+      HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
+      HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
+      HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
+    } else {
+      // heap is NOT empty
+      HeapManagerInMainMem->UsedSize = TotalSize;
+      HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
+      HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
+      HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
+      HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+      HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
+    }
+    // heap signature
+    HeapManagerInTempMem->Signature = 0x00000000;
+    HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
+    // Free space node
+    HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
+    HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
+  }
+  // if address of heap in temp memory is above 1M, then we must used one variable MTRR.
+  if (StdHeader->HeapBasePtr >= 0x100000) {
+    // Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
+    GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader);
+    for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
+         HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
+         HeapRamVariableMtrr--) {
+      LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
+      LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
+      if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
+          (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
+        break;
+      }
+    }
+    if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
+      // Clear variable MTRR which set in CopyHeapToTempRamAtPost.
+      VariableMtrrBase = 0;
+      VariableMtrrMask = 0;
+      LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
+      LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
+    }
+  }
+  return AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
new file mode 100644
index 0000000..617be48
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/agesa.inc
@@ -0,0 +1,2989 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 60222 $   @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $
+;
+; ****************************************************************************
+; *
+; * Copyright (C) 2012 Advanced Micro Devices, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; *       its contributors may be used to endorse or promote products derived
+; *       from this software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *
+; **************************************************************************
+
+INCLUDE amd.inc
+UINT64    TEXTEQU     <QWORD>
+UINT32    TEXTEQU     <DWORD>
+UINT16    TEXTEQU     <WORD>
+UINT8     TEXTEQU     <BYTE>
+CHAR8     TEXTEQU     <BYTE>
+BOOLEAN   TEXTEQU     <BYTE>
+POINTER   TEXTEQU     <DWORD>
+
+ ; AGESA Types and Definitions
+
+
+
+ ; AGESA BASIC CALLOUTS
+    AGESA_MEM_RELEASE           EQU    00028000h
+
+ ; AGESA ADVANCED CALLOUTS, Processor
+    AGESA_CHECK_UMA             EQU    00028100h
+    AGESA_DO_RESET              EQU    00028101h
+    AGESA_ALLOCATE_BUFFER       EQU    00028102h
+    AGESA_DEALLOCATE_BUFFER     EQU    00028103h
+    AGESA_LOCATE_BUFFER         EQU    00028104h
+    AGESA_RUNFUNC_ONAP          EQU    00028105h
+
+ ; AGESA ADVANCED CALLOUTS, HyperTransport
+
+ ; AGESA ADVANCED CALLOUTS, Memory
+    AGESA_READ_SPD              EQU    00028140h
+    AGESA_HOOKBEFORE_DRAM_INIT  EQU    00028141h
+    AGESA_HOOKBEFORE_DQS_TRAINING       EQU    00028142h
+    AGESA_READ_SPD_RECOVERY     EQU    00028143h
+    AGESA_HOOKBEFORE_EXIT_SELF_REF      EQU    00028144h
+    AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY      EQU    00028145h
+    AGESA_EXTERNAL____TRAIN_VREF_CHANGE  EQU   00028146h
+
+ ; AGESA IDS CALLOUTS
+    AGESA_GET_IDS_INIT_DATA     EQU    00028200h
+
+ ; AGESA GNB CALLOUTS
+    AGESA_GNB_PCIE_SLOT_RESET   EQU    00028301h
+
+ ; AGESA FCH CALLOUTS
+    AGESA_FCH_OEM_CALLOUT       EQU    00028401h
+
+; ------------------------------------------------------------------------
+
+ ; HyperTransport Interface
+
+
+
+; -----------------------------------------------------------------------------
+                         ; HT DEFINITIONS AND MACROS
+
+; -----------------------------------------------------------------------------
+
+
+ ; Width equates for call backs
+    HT_WIDTH_8_BITS             EQU    8
+    HT_WIDTH_16_BITS            EQU    16
+    HT_WIDTH_4_BITS             EQU    4
+    HT_WIDTH_2_BITS             EQU    2
+    HT_WIDTH_NO_LIMIT           EQU    HT_WIDTH_16_BITS
+
+ ; Frequency Limit equates for call backs which take a frequency supported mask.
+    HT_FREQUENCY_LIMIT_200M     EQU    1
+    HT_FREQUENCY_LIMIT_400M     EQU    7
+    HT_FREQUENCY_LIMIT_600M     EQU    1Fh
+    HT_FREQUENCY_LIMIT_800M     EQU    3Fh
+    HT_FREQUENCY_LIMIT_1000M    EQU    7Fh
+    HT_FREQUENCY_LIMIT_HT1_ONLY EQU    7Fh
+    HT_FREQUENCY_LIMIT_1200M    EQU    0FFh
+    HT_FREQUENCY_LIMIT_1400M    EQU    1FFh
+    HT_FREQUENCY_LIMIT_1600M    EQU    3FFh
+    HT_FREQUENCY_LIMIT_1800M    EQU    7FFh
+    HT_FREQUENCY_LIMIT_2000M    EQU    0FFFh
+    HT_FREQUENCY_LIMIT_2200M    EQU    1FFFh
+    HT_FREQUENCY_LIMIT_2400M    EQU    3FFFh
+    HT_FREQUENCY_LIMIT_2600M    EQU    7FFFh
+    HT_FREQUENCY_LIMIT_2800M    EQU    27FFFh
+    HT_FREQUENCY_LIMIT_3000M    EQU    67FFFh
+    HT_FREQUENCY_LIMIT_3200M    EQU    0E7FFFh
+    HT_FREQUENCY_LIMIT_3600M    EQU    1E7FFFh
+    HT_FREQUENCY_LIMIT_MAX      EQU    HT_FREQUENCY_LIMIT_3600M
+    HT_FREQUENCY_NO_LIMIT       EQU    0FFFFFFFFh
+
+ ; Unit ID Clumping special values
+    HT_CLUMPING_DISABLE         EQU    00000000h
+    HT_CLUMPING_NO_LIMIT        EQU    0FFFFFFFFh
+
+    HT_LIST_TERMINAL            EQU    0FFh
+    HT_LIST_MATCH_ANY           EQU    0FEh
+    HT_LIST_MATCH_INTERNAL_LINK EQU    0FDh
+
+ ; Event Notify definitions
+
+ ; Event definitions.
+
+ ; Coherent subfunction events
+    HT_EVENT_COH_EVENTS         EQU    10001000h
+    HT_EVENT_COH_NO_TOPOLOGY    EQU    10011000h
+    HT_EVENT_COH_OBSOLETE000    EQU    10021000h
+    HT_EVENT_COH_PROCESSOR_TYPE_MIX     EQU    10031000h
+    HT_EVENT_COH_NODE_DISCOVERED        EQU    10041000h
+    HT_EVENT_COH_MPCAP_MISMATCH EQU    10051000h
+
+ ; Non-coherent subfunction events
+    HT_EVENT_NCOH_EVENTS        EQU    10002000h
+    HT_EVENT_NCOH_BUID_EXCEED   EQU    10012000h
+    HT_EVENT_NCOH_OBSOLETE000   EQU    10022000h
+    HT_EVENT_NCOH_BUS_MAX_EXCEED        EQU    10032000h
+    HT_EVENT_NCOH_CFG_MAP_EXCEED        EQU    10042000h
+    HT_EVENT_NCOH_DEVICE_FAILED EQU    10052000h
+    HT_EVENT_NCOH_AUTO_DEPTH    EQU    10062000h
+
+ ; Optimization subfunction events
+    HT_EVENT_OPT_EVENTS         EQU    10003000h
+    HT_EVENT_OPT_REQUIRED_CAP_RETRY     EQU    10013000h
+    HT_EVENT_OPT_REQUIRED_CAP_GEN3      EQU    10023000h
+    HT_EVENT_OPT_UNUSED_LINKS   EQU    10033000h
+    HT_EVENT_OPT_LINK_PAIR_EXCEED       EQU    10043000h
+
+ ; HW Fault events
+    HT_EVENT_HW_EVENTS          EQU    10004000h
+    HT_EVENT_HW_SYNCFLOOD       EQU    10014000h
+    HT_EVENT_HW_HTCRC           EQU    10024000h
+
+ ; The Recovery HT component uses 0x10005000 for events.
+ ; For consistency, we avoid that range here.
+
+    HT_MAX_NC_BUIDS             EQU    32
+; ----------------------------------------------------------------------------
+                         ; HT TYPEDEFS, STRUCTURES, ENUMS
+
+; ----------------------------------------------------------------------------
+MATCHED                 EQU     0               ; < The link matches the requested customization.
+POWERED_OFF             EQU     1               ; < Power the link off.
+UNMATCHED               EQU     2               ; < The link should be processed according to normal defaults.
+MaxFinalLinkState       EQU     3               ; < Not a final link state, use for limit checking.
+FINAL_LINK_STATE        TEXTEQU <DWORD>
+
+ ; Swap a device from its current id to a new one.
+
+BUID_SWAP_ITEM    STRUCT
+  FromId                        UINT8 ?         ; < The device responding to FromId,
+  ToId                          UINT8 ?         ; < will be moved to ToId.
+BUID_SWAP_ITEM    ENDS
+
+
+ ; Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+ ; the final in order list of device ids is provided. (There can be more swaps than devices.)
+ ; The unused entries in both are filled with 0xFF.
+
+BUID_SWAP_LIST    STRUCT
+  Swaps                         BUID_SWAP_ITEM (HT_MAX_NC_BUIDS) DUP ({})       ; < The BUID Swaps to perform
+  FinalIds                      UINT8 (HT_MAX_NC_BUIDS) DUP (?)         ; < The ordered final BUIDs, resulting from the swaps
+BUID_SWAP_LIST    ENDS
+
+
+ ; Control Manual Initialization of Non-Coherent Chains
+
+ ; This interface is checked every time a non-coherent chain is
+ ; processed.  BUID assignment may be controlled explicitly on a
+ ; non-coherent chain. Provide a swap list.  Swaps controls the
+ ; BUID assignment and FinalIds provides the device to device
+ ; Linking.  Device orientation can be detected automatically, or
+ ; explicitly.  See interface documentation for more details.
+
+ ; If a manual swap list is not supplied,
+ ; automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ ; based on each device's unit count.
+
+MANUAL_BUID_SWAP_LIST    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this chain is located
+  Link                          UINT8 ?         ; < The Link on the host for this chain
+   ; Override fields
+  SwapList                      BUID_SWAP_LIST {}       ; < The swap list
+MANUAL_BUID_SWAP_LIST    ENDS
+
+
+ ; Override options for DEVICE_CAP_OVERRIDE.
+
+ ; Specify which override actions should be performed.  For Checks, 1 means to check the item
+ ; and 0 means to skip the check.  For the override options, 1 means to apply the override and
+ ; 0 means to ignore the override.
+
+DEVICE_CAP_OVERRIDE_OPTIONS    STRUCT
+  IsCheckDevVenId               UINT32 ?
+;   IN       UINT32  IsCheckDevVenId:1;        ; < Check Match on Device/Vendor id
+;   IN       UINT32  IsCheckRevision:1;         ; < Check Match on device Revision
+;   IN       UINT32  IsOverrideWidthIn:1;       ; < Override Width In
+;   IN       UINT32  IsOverrideWidthOut:1;      ; < Override Width Out
+;   IN       UINT32  IsOverrideFreq:1;          ; < Override Frequency
+;   IN       UINT32  IsOverrideClumping:1;      ; < Override Clumping
+;   IN       UINT32  IsDoCallout:1;             ; < Make the optional callout
+DEVICE_CAP_OVERRIDE_OPTIONS    ENDS
+
+ ; Override capabilities of a device.
+
+ ; This interface is checked once for every Link on every IO device.
+ ; Provide the width and frequency capability if needed for this device.
+ ; This is used along with device capabilities, the limit interfaces, and northbridge
+ ; limits to compute the default settings.  The components of the device's PCI config
+ ; address are provided, so its settings can be consulted if need be.
+ ; The optional callout is a catch all.
+
+DEVICE_CAP_OVERRIDE    STRUCT
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this chain is located.
+  HostLink                      UINT8 ?         ; < The Link on the host for this chain.
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host.
+  DevVenId                      UINT32 ?        ; < The Device's PCI Vendor + Device ID (offset 0x00).
+  Revision                      UINT8 ?         ; < The Device's PCI Revision field (offset 0x08).
+  Link                          UINT8 ?         ; < The Device's Link number (0 or 1).
+  Options                       DEVICE_CAP_OVERRIDE_OPTIONS {}          ; < The options for this device override.
+   ; Override fields
+  LinkWidthIn                   UINT8 ?         ; < modify to change the Link Width In.
+  LinkWidthOut                  UINT8 ?         ; < modify to change the Link Width Out.
+  FreqCap                       UINT32 ?        ; < modify to change the Link's frequency capability.
+  Clumping                      UINT32 ?        ; < modify to change Unit ID clumping support.
+  Callout                       CALLOUT_ENTRY ?         ; < optional call for really complex cases, or NULL.
+DEVICE_CAP_OVERRIDE    ENDS
+
+ ; Callout param struct for override capabilities of a device.
+
+ ; If the optional callout is implemented this param struct is passed to it.
+
+DEVICE_CAP_CALLOUT_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The header
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this chain is located.
+  HostLink                      UINT8 ?         ; < The Link on the host for this chain.
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host.
+  DevVenId                      UINT32 ?        ; < The Device's PCI Vendor + Device ID (offset 0x00).
+  Revision                      UINT8 ?         ; < The Device's PCI Revision field (offset 0x08).
+  Link                          UINT8 ?         ; < The Device's Link number (0 or 1).
+  PciAddress                    PCI_ADDR {}      ; < The Device's PCI Address.
+   ; Override fields
+     LinkWidthIn                POINTER ?       ; < modify to change the Link Width In.
+     LinkWidthOut               POINTER ?       ; < modify to change the Link Width Out.
+     FreqCap                    POINTER ?       ; < modify to change the Link's frequency capability.
+     Clumping                   POINTER ?       ; < modify to change Unit ID clumping support.
+DEVICE_CAP_CALLOUT_PARAMS    ENDS
+
+  ; Limits for CPU to CPU Links.
+
+  ; For each coherent connection this interface is checked once.
+  ; Provide the frequency and width if needed for this Link (usually based on board
+  ; restriction).  This is used with CPU device capabilities and northbridge limits
+  ; to compute the default settings.
+
+CPU_TO_CPU_PCB_LIMITS    STRUCT
+   ; Match fields
+  SocketA                       UINT8 ?         ; < One Socket on which this Link is located
+  LinkA                         UINT8 ?         ; < The Link on this Node
+  SocketB                       UINT8 ?         ; < The other Socket on which this Link is located
+  LinkB                         UINT8 ?         ; < The Link on that Node
+   ; Limit fields
+  ABLinkWidthLimit              UINT8 ?         ; < modify to change the Link Width A->B
+  BALinkWidthLimit              UINT8 ?         ; < modify to change the Link Width B-<A
+  PcbFreqCap                    UINT32 ?        ; < modify to change the Link's frequency capability
+CPU_TO_CPU_PCB_LIMITS    ENDS
+
+  ; Get limits for non-coherent Links.
+
+ ; For each non-coherent connection this interface is checked once.
+ ; Provide the frequency and width if needed for this Link (usually based on board
+ ; restriction).  This is used with device capabilities, device overrides, and northbridge limits
+ ; to compute the default settings.
+
+IO_PCB_LIMITS    STRUCT
+   ; Match fields
+  HostSocket                    UINT8 ?         ; < The Socket on which this Link is located
+  HostLink                      UINT8 ?         ; < The Link about to be initialized
+  Depth                         UINT8 ?         ; < The Depth in the I/O chain from the Host
+   ; Limit fields
+  DownstreamLinkWidthLimit      UINT8 ?         ; < modify to change the Link Width going away from processor
+  UpstreamLinkWidthLimit        UINT8 ?         ; < modify to change the Link Width moving toward processor
+  PcbFreqCap                    UINT32 ?        ; < modify to change the Link's frequency capability
+IO_PCB_LIMITS    ENDS
+
+  ; Manually control bus number assignment.
+
+ ; This interface is checked every time a non-coherent chain is processed.
+ ; If a system can not use the auto Bus numbering feature for non-coherent chain bus
+ ; assignments, this interface can provide explicit control.  For each chain, provide
+ ; the bus number range to use.
+
+OVERRIDE_BUS_NUMBERS    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this chain is located
+  Link                          UINT8 ?         ; < The Link on the host for this chain
+   ; Override fields
+  SecBus                        UINT8 ?         ; < Secondary Bus number for this non-coherent chain
+  SubBus                        UINT8 ?         ; < Subordinate Bus number
+OVERRIDE_BUS_NUMBERS    ENDS
+
+
+  ; Ignore a Link.
+
+  ; This interface is checked every time a coherent Link is found and then every
+  ; time a non-coherent Link from a CPU is found.
+  ; Any coherent or non-coherent Link from a CPU can be ignored and not used
+  ; for discovery or initialization.  Useful for connection based systems.
+  ; (Note: not checked for IO device to IO Device Links.)
+
+IGNORE_LINK    STRUCT
+   ; Match fields
+  Socket                        UINT8 ?         ; < The Socket on which this Link is located
+  Link                          UINT8 ?         ; < The Link about to be initialized
+   ; Customization fields
+  LinkState                     FINAL_LINK_STATE ? ; < The link may be left unitialized, or powered off.
+IGNORE_LINK    ENDS
+
+
+  ; Skip reganging of subLinks.
+
+  ; This interface is checked whenever two subLinks are both connected to the same CPUs.
+  ; Normally, unganged sublinks between the same two CPUs are reganged.
+  ; Provide a matching structure to leave the Links unganged.
+
+SKIP_REGANG    STRUCT
+   ; Match fields
+  SocketA                       UINT8 ?         ; < One Socket on which this Link is located
+  LinkA                         UINT8 ?         ; < The Link on this Node
+  SocketB                       UINT8 ?         ; < The other Socket on which this Link is located
+  LinkB                         UINT8 ?         ; < The Link on that Node
+   ; Customization fields
+  LinkState                     FINAL_LINK_STATE ? ; < The paired sublink may be active, or powered off.
+SKIP_REGANG    ENDS
+
+  ; The System Socket layout, which sockets are physically connected.
+
+  ; The hardware method for Socket naming is preferred.  Use this software method only
+  ; if required.
+
+SYSTEM_PHYSICAL_SOCKET_MAP    STRUCT
+  CurrentSocket                 UINT8 ?         ; < The socket from which this connection originates.
+  CurrentLink                   UINT8 ?         ; < The Link from the source socket connects to another socket.
+  TargetSocket                  UINT8 ?         ; < The target socket which is connected on that link.
+SYSTEM_PHYSICAL_SOCKET_MAP    ENDS
+
+; ----------------------------------------------------------------------------
+
+ ; This is the input structure for AmdHtInitialize.
+
+AMD_HT_INTERFACE    STRUCT
+   ; Basic level customization
+  AutoBusStart                  UINT8 ?         ; < For automatic bus number assignment, starting bus number usually zero.
+  AutoBusMax                    UINT8 ?         ; < For automatic bus number assignment, do not assign above max.
+  AutoBusIncrement              UINT8 ?         ; < For automatic bus number assignment, each chain gets this many busses.
+
+   ; Advanced Level Customization
+  ManualBuidSwapList            POINTER ?       ; < Provide Manual Swap List, if any.
+  DeviceCapOverrideList         POINTER ?       ; < Provide Device Overrides, if any.
+  CpuToCpuPcbLimitsList         POINTER ?       ; < Provide CPU PCB Limits, if any.
+  IoPcbLimitsList               POINTER ?       ; < Provide IO PCB Limits, if any.
+  OverrideBusNumbersList        POINTER ?       ; < Provide manual Bus Number assignment, if any.
+                                                 ; < Use either auto bus numbering or override bus
+                                                 ; < numbers, not both.
+
+  IgnoreLinkList                POINTER ?       ; < Provide links to ignore, if any.
+  SkipRegangList                POINTER ?       ; < Provide links to remain unganged, if any.
+
+   ; Expert Level Customization
+  Topolist                      POINTER ?       ; < Use this topology list in addition to the built in, if not NULL.
+  SystemPhysicalSocketMap       POINTER ?
+                                                     ; < The hardware socket naming method is preferred,
+                                                     ; <  If it can't be used, this provides a software method.
+AMD_HT_INTERFACE    ENDS
+
+; -----------------------------------------------------------------------------
+
+ ; HT Recovery Interface
+
+
+
+; -----------------------------------------------------------------------------
+; *              HT Recovery DEFINITIONS AND MACROS
+; *
+; *-----------------------------------------------------------------------------
+;
+
+ ; BBHT subfunction events
+    HT_EVENT_BB_EVENTS          EQU    10005000h
+    HT_EVENT_BB_BUID_EXCEED     EQU    10015000h
+    HT_EVENT_BB_DEVICE_FAILED   EQU    10055000h
+    HT_EVENT_BB_AUTO_DEPTH      EQU    10065000h
+
+; ----------------------------------------------------------------------------
+; *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+; *
+; *----------------------------------------------------------------------------
+;
+
+
+ ; The Interface structure to Recovery HT.
+
+AMD_HT_RESET_INTERFACE    STRUCT
+  ManualBuidSwapList            POINTER ?       ; < Option to manually control SB link init
+     Depth                      UINT32 ?        ; < If auto init was used this is set to the depth of the chain,
+                                   ; < else, for manual init unmodified.
+AMD_HT_RESET_INTERFACE    ENDS
+
+
+;-----------------------------------------------------------------------------
+;                     FCH DEFINITIONS AND MACROS
+;
+;-----------------------------------------------------------------------------
+
+; Configuration values for SdConfig
+  SdDisable         EQU     0            ; Disabled
+  SdAmda            EQU     1            ; AMDA,  set 24,18,16,  default
+  SdDma             EQU     2            ; DMA clear 24, 16, set 18
+  SdPio             EQU     3            ; PIO clear 24,18,16
+SD_MODE          TEXTEQU <DWORD>
+
+; Configuration values for SdClockControl
+  Sd50MhzTraceCableLengthWithinSixInches           EQU  4    ; 50Mhz, default
+  Sd40MhzTraceCableLengthSix2ElevenInches          EQU  6    ; 40Mhz
+  Sd25MhzTraceCableLengthEleven2TwentyfourInches   EQU  7    ; 25Mhz
+SD_CLOCK_CONTROL  TEXTEQU <DWORD>
+
+; Configuration values for AzaliaController
+  AzAuto            EQU     0            ; Auto - Detect Azalia controller automatically
+  AzDisable         EQU     1            ; Diable - Disable Azalia controller
+  AzEnable          EQU     2            ; Enable - Enable Azalia controller
+HDA_CONFIG       TEXTEQU <DWORD>
+
+; Configuration values for IrConfig
+  IrDisable         EQU     0            ; Disable
+  IrRxTx0           EQU     1            ; Rx and Tx0
+  IrRxTx1           EQU     2            ; Rx and Tx1
+  IrRxTx0Tx1        EQU     3            ; Rx and both Tx0,Tx1
+IR_CONFIG        TEXTEQU <DWORD>
+
+; Configuration values for SataClass
+  SataNativeIde     EQU     0            ; Native IDE mode
+  SataRaid          EQU     1            ; RAID mode
+  SataAhci          EQU     2            ; AHCI mode
+  SataLegacyIde     EQU     3            ; Legacy IDE mode
+  SataIde2Ahci      EQU     4            ; IDE->AHCI mode
+  SataAhci7804      EQU     5            ; AHCI mode as 7804 ID (AMD driver)
+  SataIde2Ahci7804  EQU     6            ; IDE->AHCI mode as 7804 ID (AMD driver)
+SATA_CLASS       TEXTEQU <DWORD>
+
+; Configuration values for GppLinkConfig
+  PortA4            EQU     0            ; 4:0:0:0
+  PortA2B2          EQU     2            ; 2:2:0:0
+  PortA2B1C1        EQU     3            ; 2:1:1:0
+  PortA1B1C1D1      EQU     4            ; 1:1:1:1
+GPP_LINKMODE       TEXTEQU <DWORD>
+
+; Configuration values for FchPowerFail
+  AlwaysOff         EQU     0            ; Always power off after power resumes
+  AlwaysOn          EQU     1            ; Always power on after power resumes
+  UsePrevious       EQU     3            ; Resume to same setting when power fails
+POWER_FAIL    TEXTEQU <DWORD>
+
+; Configuration values for SATA Link Speed
+  Gen1      EQU   1                      ; SATA port GEN1 speed
+  Gen2      EQU   2                      ; SATA port GEN2 speed
+  Gen3      EQU   3                      ; SATA port GEN3 speed
+SATA_SPEED     TEXTEQU <DWORD>
+
+; Configuration values for GPIO function
+  Function0     EQU     0                ; GPIO Function 1
+  Function1     EQU     1                ; GPIO Function 1
+  Function2     EQU     2                ; GPIO Function 2
+  Function3     EQU     3                ; GPIO Function 3
+GPIO_FUN      TEXTEQU <DWORD>
+
+; Configuration values for GPIO_CFG
+  OwnedByEc     EQU     1                ; This bit can only be written by EC
+  OwnedByHost   EQU     2                ; This bit can only be written by host (BIOS)
+  Sticky        EQU     4                ; If set, [6:3] are sticky
+  PullUpB       EQU     8                ; 0: Pullup enable; 1: Pullup disabled
+  PullDown      EQU     16               ; 0: Pulldown disabled; 1: Pulldown enable
+  GpioOutEnB    EQU     32               ; 0: Output enable; 1: Output disable
+  GpioOut       EQU     64               ; Output state when GpioOutEnB is 0
+  GpioIn        EQU     128              ; This bit is read only - current pin state
+CFG_BYTE      TEXTEQU <DWORD>
+
+; FCH GPIO CONTROL
+GPIO_CONTROL   STRUCT
+  GpioPin        UINT8     ?             ; Gpio Pin, valid range: 0-67, 128-150, 160-228
+  PinFunction    GPIO_FUN  ?             ; Multi-function selection
+  CfgByte        CFG_BYTE  ?             ; GPIO Register value
+GPIO_CONTROL   ENDS
+
+; FCH SCI MAP CONTROL
+SCI_MAP_CONTROL   STRUCT
+  InputPin        UINT8    ?             ; Input Pin, valid range 0-63
+  GpeMap          UINT8    ?             ; Gpe Map, valid range 0-31
+SCI_MAP_CONTROL   ENDS
+
+; FCH SATA PHY CONTROL
+SATA_PHY_CONTROL   STRUCT
+  CommonPhy       BOOLEAN      ?         ; Common PHY or not
+  Gen             SATA_SPEED   ?         ; SATA speed
+  Port            UINT8        ?         ; Port number, valid range: 0-7
+  PhyData         UINT32       ?         ; SATA PHY data, valid range: 0-0xFFFFFFFF
+SATA_PHY_CONTROL   ENDS
+
+;
+; FCH Component Data Structure in InitReset stage
+;
+FCH_RESET_INTERFACE    STRUCT
+  UmiGen2         BOOLEAN    ?      ; Enable Gen2 data rate of UMI
+                                    ;   FALSE - Disable Gen2
+                                    ;   TRUE  - Enable Gen2
+
+  SataEnable      BOOLEAN    ?      ; SATA controller function
+                                    ;   FALSE - SATA controller is disabled
+                                    ;   TRUE  - SATA controller is enabled
+
+  IdeEnable       BOOLEAN    ?      ; SATA IDE controller mode enabled/disabled
+                                    ;   FALSE - IDE controller is disabled
+                                    ;   TRUE  - IDE controller is enabled
+
+  GppEnable       BOOLEAN    ?      ; Master switch of GPP function
+                                    ;   FALSE - GPP disabled
+                                    ;   TRUE  - GPP enabled
+
+  Xhci0Enable     BOOLEAN    ?      ; XHCI0 controller function
+                                    ;   FALSE - XHCI0 controller disabled
+                                    ;   TRUE  - XHCI0 controller enabled
+
+  Xhci1Enable     BOOLEAN    ?      ; XHCI1 controller function
+                                    ;   FALSE - XHCI1 controller disabled
+                                    ;   TRUE  - XHCI1 controller enabled
+
+FCH_RESET_INTERFACE    ENDS
+
+
+;
+; FCH Component Data Structure from InitEnv stage
+;
+FCH_INTERFACE        STRUCT
+  SdConfig             SD_MODE      ?    ; Secure Digital (SD) controller mode
+  AzaliaController     HDA_CONFIG   ?    ; Azalia HD Audio Controller
+  IrConfig             IR_CONFIG    ?    ; Infrared (IR) Configuration
+  UmiGen2              BOOLEAN      ?    ; Enable Gen2 data rate of UMI
+                                         ;   FALSE - Disable Gen2
+                                         ;   TRUE  - Enable Gen2
+  SataClass            SATA_CLASS   ?    ; SATA controller mode
+  SataEnable           BOOLEAN      ?    ; SATA controller function
+                                         ;   FALSE - SATA controller is disabled
+                                         ;   TRUE  - SATA controller is enabled
+  IdeEnable            BOOLEAN      ?    ; SATA IDE controller mode enabled/disabled
+                                         ;   FALSE - IDE controller is disabled
+                                         ;   TRUE  - IDE controller is enabled
+  SataIdeMode          BOOLEAN      ?    ; Native mode of SATA IDE controller
+                                         ;   FALSE - Legacy IDE mode
+                                         ;   TRUE  - Native IDE mode
+  Ohci1Enable          BOOLEAN      ?    ; OHCI controller #1 Function
+                                         ;   FALSE - OHCI1 is disabled
+                                         ;   TRUE  - OHCI1 is enabled
+  Ohci2Enable          BOOLEAN      ?    ; OHCI controller #2 Function
+                                         ;   FALSE - OHCI2 is disabled
+                                         ;   TRUE  - OHCI2 is enabled
+  Ohci3Enable          BOOLEAN      ?    ; OHCI controller #3 Function
+                                         ;   FALSE - OHCI3 is disabled
+                                         ;   TRUE  - OHCI3 is enabled
+  Ohci4Enable          BOOLEAN      ?    ; OHCI controller #4 Function
+                                         ;   FALSE - OHCI4 is disabled
+                                         ;   TRUE  - OHCI4 is enabled
+  XhciSwitch           BOOLEAN      ?    ; XHCI controller Function
+                                         ;   FALSE - XHCI is disabled
+                                         ;   TRUE  - XHCI is enabled
+  GppEnable            BOOLEAN      ?    ; Master switch of GPP function
+                                         ;   FALSE - GPP disabled
+                                         ;   TRUE  - GPP enabled
+  FchPowerFail         POWER_FAIL   ?    ; FCH power failure option
+FCH_INTERFACE        ENDS
+
+
+; ---------------------------------------------------------------------------
+;  CPU Feature related info
+; ---------------------------------------------------------------------------
+ ; Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+  C1eModeDisabled                   EQU    0    ; < Disabled
+  C1eModeAuto                       EQU    1    ; < Auto mode enables the best C1e method for the
+                                                ; < currently installed processor
+  C1eModeHardware                   EQU    2    ; < Hardware method
+  C1eModeMsgBased                   EQU    3    ; < Message-based method
+  C1eModeSoftwareDeprecated         EQU    4    ; < Deprecated software SMI method
+  C1eModeHardwareSoftwareDeprecated EQU    5    ; < Hardware or Deprecated software SMI method
+  MaxC1eMode                        EQU    6    ; < Not a valid value, used for verifying input
+PLATFORM_C1E_MODES TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+  CStateModeDisabled       EQU 0        ; < Disabled
+  CStateModeC6             EQU 1        ; < C6 State
+  MaxCStateMode            EQU 2        ; < Not a valid value, used for verifying input
+PLATFORM_CSTATE_MODES TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+  CpbModeAuto              EQU 0        ; < Auto
+  CpbModeDisabled          EQU 1        ; < Disabled
+  MaxCpbMode               EQU 2        ; < Not a valid value, used for verifying input
+PLATFORM_CPB_MODES TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO       EQU 0        ; < Auto
+  LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE    EQU 1        ; < Disabled
+  MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE   EQU 2        ; < Not a valid value, used for verifying input
+PLATFORM_LOW_POWER_PSTATE_MODES TEXTEQU  <DWORD>
+
+;----------------------------------------------------------------------------
+;   GNB PCIe configuration info
+;----------------------------------------------------------------------------
+
+GNB_EVENT_INVALID_CONFIGURATION                 EQU  20010000h   ; User configuration invalid
+GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION   EQU  20010001h   ; Requested lane allocation for PCIe port can not be supported
+GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION       EQU  20010002h   ; Requested incorrect PCIe port device address
+GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION        EQU  20010003h   ; Incorrect parameter in DDI link configuration
+GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION      EQU  20010004h   ; Invalid with for PCIe port or DDI link
+GNB_EVENT_INVALID_LANES_CONFIGURATION           EQU  20010005h   ; Lane double subscribe lanes
+GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION    EQU  20010006h   ; Requested lane allocation for DDI link(s) can not be supported
+GNB_EVENT_LINK_TRAINING_FAIL                    EQU  20020000h   ; PCIe Link training fail
+GNB_EVENT_BROKEN_LANE_RECOVERY                  EQU  20030000h   ; Broken lane workaround applied to recover link training
+GNB_EVENT_GEN2_SUPPORT_RECOVERY                 EQU  20040000h   ; Scale back to GEN1 to recover link training
+
+DESCRIPTOR_TERMINATE_LIST                       EQU  80000000h
+DESCRIPTOR_IGNORE                               EQU  40000000h
+
+PCIe_PORT_MISC_CONTROL          STRUCT
+  LinkComplianceMode            UINT8  ?
+ ;IN      UINT8  LinkComplianceMode :1;                   ;< Force port into compliance mode (device will not be trained, port output compliance pattern)
+PCIe_PORT_MISC_CONTROL          ENDS
+
+PCIe_PORT_DATA                  STRUCT
+  PortPresent                   UINT8  ?                  ; < Enable PCIe port for initialization.
+  ChannelType                   UINT8  ?                  ; < Channel type.
+                                                          ;  0 - "lowLoss",
+                                                          ;  1 - "highLoss",
+                                                          ;  2 - "mob0db",
+                                                          ;  3 - "mob3db",
+                                                          ;  4 - "extnd6db"
+                                                          ;  5 - "extnd8db"
+                                                          ;
+  DeviceNumber                  UINT8  ?                  ; < Device number for port. Available device numbers may very on different CPUs.
+  FunctionNumber                UINT8  ?                  ; < Reserved for future use
+  LinkSpeedCapability           UINT8  ?                  ; < Advertised Gen Capability
+                                                          ;  0 - Maximum supported by silicon
+                                                          ;  1 - Gen1
+                                                          ;  2 - Gen2
+                                                          ;  3 - Gen3
+                                                          ;
+  LinkAspm                      UINT8  ?                  ; < ASPM control. (see OemPcieLinkAspm for additional option to control ASPM)
+                                                          ;  0 - Disabled
+                                                          ;  1 - L0s only
+                                                          ;  2 - L1 only
+                                                          ;  2 - L0s and L1
+                                                          ;
+  LinkHotplug                   UINT8  ?                  ; < Hotplug control.
+                                                          ;  0 - Disabled
+                                                          ;  1 - Basic
+                                                          ;  2 - Server
+                                                          ;  3 - Enhanced
+                                                          ;
+  ResetId                       UINT8  ?                  ; < Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                          ; identification which control reset for given port.
+                                                          ; Each port with unique GPIO should have unique ResetId assigned.
+                                                          ; All ports use same GPIO to control reset should have same ResetId assigned.
+                                                          ; see AgesaPcieSlotResetControl
+                                                          ;
+  MiscControls                  PCIe_PORT_MISC_CONTROL {} ; < Misc extended controls
+PCIe_PORT_DATA                  ENDS
+
+;DDI channel lane mapping
+
+CHANNEL_MAPPING             STRUCT                    ;
+  Lane0                         UINT8  ?                  ;
+    ;IN      UINT8              Lane0   :2;                 ;
+    ;IN      UINT8              Lane1   :2;                ///< Lane 1 mapping (see "Lane 0 mapping")
+    ;IN      UINT8              Lane2   :2;                ///< Lane 2 mapping (see "Lane 0 mapping")
+    ;IN      UINT8              Lane3   :2;                ///< Lane 3 mapping (see "Lane 0 mapping")
+CHANNEL_MAPPING             ENDS                      ;
+
+CONN_CHANNEL_MAPPING            UNION
+  ChannelMappingValue           UINT8  ?                  ; < Raw lane mapping
+  ChannelMapping                CHANNEL_MAPPING {}    ;
+CONN_CHANNEL_MAPPING            ENDS                      ;
+
+; DDI Configuration
+PCIe_DDI_DATA                   STRUCT
+  ConnectorType                 UINT8  ?                  ; < Display Connector Type
+                                                          ;  0 - DP
+                                                          ;  1 - eDP
+                                                          ;  2 - Single Link DVI
+                                                          ;  3 - Dual  Link DVI
+                                                          ;  4 - HDMI
+                                                          ;  5 - Travis DP-to-VGA
+                                                          ;  6 - Travis DP-to-LVDS
+                                                          ;  7 - Hudson-2 NutMeg DP-to-VGA
+                                                          ;  8 - Single Link DVI-I
+                                                          ;  9 - CRT (VGA)
+                                                          ;  10 - LVDS
+                                                          ;  11 - VBIOS auto detect connector type
+  AuxIndex                      UINT8  ?                  ; < Indicates which AUX or DDC Line is used
+                                                          ;  0 - AUX1
+                                                          ;  1 - AUX2
+                                                          ;  2 - AUX3
+                                                          ;  3 - AUX4
+                                                          ;  4 - AUX5
+                                                          ;  5 - AUX6
+                                                          ;
+  HdpIndex                      UINT8  ?                  ; < Indicates which HDP pin is used
+                                                          ;  0 - HDP1
+                                                          ;  1 - HDP2
+                                                          ;  2 - HDP3
+                                                          ;  3 - HDP4
+                                                          ;  4 - HDP5
+                                                          ;  5 - HDP6
+  Mapping                       CONN_CHANNEL_MAPPING (2) DUP ({})  ;< Set specific mapping of lanes to connector pins
+                                                                   ;Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+                                                                   ;Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only
+                                                                   ;applicable for Dual DDI link)
+                                                                   ;if Mapping[x] set to 0 than default mapping assumed
+  LanePnInversionMask           UINT8  ?                  ; < Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port
+                                                          ;  0 - Do not invert (default)
+                                                          ;  1 - Invert P and N on this lane
+PCIe_DDI_DATA                   ENDS
+
+
+; Engine Configuration
+PCIe_ENGINE_DATA                STRUCT
+  EngineType                    UINT8   ?                 ; < Engine type
+                                                          ;  0 -  Ignore engine configuration
+                                                          ;  1 -  PCIe port
+                                                          ;  2 -  DDI
+  StartLane                     UINT16  ?                 ; < Start lane number (in reversed configuration StartLane > EndLane).
+  EndLane                       UINT16  ?                 ; < End lane number (in reversed configuration StartLane > EndLane).
+PCIe_ENGINE_DATA                ENDS
+
+; PCIe port descriptor
+PCIe_PORT_DESCRIPTOR            STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+                                                          ;  Bit31 - last descriptor in complex
+  EngineData                    PCIe_ENGINE_DATA {}       ; < Engine data
+  Port                          PCIe_PORT_DATA {}         ; < PCIe port specific configuration info
+PCIe_PORT_DESCRIPTOR            ENDS
+
+; DDI descriptor
+PCIe_DDI_DESCRIPTOR             STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+  EngineData                    PCIe_ENGINE_DATA {}       ; < Engine data
+  Ddi                           PCIe_DDI_DATA {}          ; < DDI port specific configuration info
+PCIe_DDI_DESCRIPTOR             ENDS
+
+; Slot Reset Info
+PCIe_SLOT_RESET_INFO            STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}      ; < AGESA Standard Header
+  ResetId                       UINT8  ?                  ; < Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  ResetControl                  UINT8  ?                  ; < Reset control as defined by PCIE_RESET_CONTROL
+PCIe_SLOT_RESET_INFO            ENDS
+
+
+; PCIe Complex descriptor
+PCIe_COMPLEX_DESCRIPTOR         STRUCT
+  Flags                         UINT32  ?                 ; < Descriptor flags
+                                                          ; Bit31 - last descriptor in topology
+                                                          ;
+                                                          ;
+  SocketId                      UINT32  ?                 ; < Socket Id
+  PciePortList                  POINTER ?                 ;< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  DdiLinkList                   POINTER ?                 ;< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  Reserved                      POINTER ?         ;< Reserved for future use
+PCIe_COMPLEX_DESCRIPTOR         ENDS
+
+  AssertSlotReset               EQU  0
+  DeassertSlotReset             EQU  1
+PCIE_RESET_CONTROL TEXTEQU  <DWORD>
+
+  PcieUnusedEngine              EQU  0
+  PciePortEngine                EQU  1
+  PcieDdiEngine                 EQU  2
+  MaxPcieEngine                 EQU  3                    ; < Not a valid value, used for verifying input
+PCIE_ENGINE_TYPE   TEXTEQU  <DWORD>
+
+  PcieGenMaxSupported           EQU  0
+  PcieGen1                      EQU  1
+  PcieGen2                      EQU  2
+  MaxPcieGen                    EQU  3                    ; < Not a valid value, used for verifying input
+PCIE_LINK_SPEED_CAP      TEXTEQU  <DWORD>
+
+  PsppDisabled                  EQU  0
+  PsppPerformance               EQU  1
+  PsppBalanceHigh               EQU  2
+  PsppBalanceLow                EQU  3
+  PsppPowerSaving               EQU  4
+  MaxPspp                       EQU  5                     ; < Not a valid value, used for verifying input
+PCIE_PSPP_POLICY      TEXTEQU  <DWORD>
+
+  ConnectorTypeDP               EQU  0
+  ConnectorTypeEDP              EQU  1
+  ConnectorTypeSingleLinkDVI    EQU  2
+  ConnectorTypeDualLinkDVI      EQU  3
+  ConnectorTypeHDMI             EQU  4
+  ConnectorTypeTravisDpToVga    EQU  5
+  ConnectorTypeTravisDpToLvds   EQU  6
+  ConnectorTypeNutmegDpToVga    EQU  7
+  ConnectorTypeSingleLinkDviI   EQU  8
+  ConnectorTypeCrt              EQU  9
+  ConnectorTypeLvds             EQU  10
+  ConnectorTypeAutoDetect       EQU  11
+  MaxConnectorType              EQU  12                    ; < Not a valid value, used for verifying input
+PCIE_CONNECTOR_TYPE      TEXTEQU  <DWORD>
+
+  ChannelTypeLowLoss            EQU  0
+  ChannelTypeHighLoss           EQU  1
+  ChannelTypeMob0db             EQU  2
+  ChannelTypeMob3db             EQU  3
+  ChannelTypeExt6db             EQU  4
+  ChannelTypeExt8db             EQU  5
+  MaxChannelType                EQU  6                    ; < Not a valid value, used for verifying input
+PCIE_CHANNEL_TYPE  TEXTEQU  <DWORD>
+
+  AspmDisabled                  EQU  0
+  AspmL0s                       EQU  1
+  AspmL1                        EQU  2
+  AspmL0sL1                     EQU  3
+  MaxAspm                       EQU  4                    ; < Not a valid value, used for verifying input
+PCIE_ASPM_TYPE  TEXTEQU  <DWORD>
+
+  HotplugDisabled               EQU  0
+  HotplugBasic                  EQU  1
+  HotplugServer                 EQU  2
+  HotplugEnhanced               EQU  3
+  HotplugInboard                EQU  4
+  MaxHotplug                    EQU  5                    ; < Not a valid value, used for verifying input
+PCIE_HOTPLUG_TYPE TEXTEQU  <DWORD>
+
+  PortDisabled                  EQU  0
+  PortEnabled                   EQU  1
+PCIE_PORT_ENABLE  TEXTEQU  <DWORD>
+
+  Aux1                          EQU  0
+  Aux2                          EQU  1
+  Aux3                          EQU  2
+  Aux4                          EQU  3
+  Aux5                          EQU  4
+  Aux6                          EQU  5
+  MaxAux                        EQU  6                    ; < Not a valid value, used for verifying input
+PCIE_AUX_TYPE TEXTEQU  <DWORD>
+
+  Hdp1                          EQU  0
+  Hdp2                          EQU  1
+  Hdp3                          EQU  2
+  Hdp4                          EQU  3
+  Hdp5                          EQU  4
+  Hdp6                          EQU  5
+  MaxHdp                        EQU  6                   ; < Not a valid value, used for verifying input
+PCIE_HDP_TYPE TEXTEQU  <DWORD>
+
+
+;IOMMU requestor ID
+IOMMU_REQUESTOR_ID STRUCT
+   Bus              UINT16               ?               ; <[15:8] - Bus number, [7:3] - Device number, [2:0] - Function number
+IOMMU_REQUESTOR_ID ENDS
+
+;IVMD exclusion range descriptor
+IOMMU_EXCLUSION_RANGE_DESCRIPTOR STRUCT
+  Flags                  UINT32               ?           ; Descriptor flags
+                                                          ;  @li @b Flags[31] - Terminate descriptor array.
+                                                          ;  @li @b Flags[30] - Ignore descriptor.
+  RequestorIdStart       IOMMU_REQUESTOR_ID   {}          ; Requestor ID start
+  RequestorIdEnd         IOMMU_REQUESTOR_ID   {}          ; Requestor ID end (use same as start for single ID)
+  RangeBaseAddress       UINT64               ?           ; Phisical base address of exclusion range
+  RangeLength            UINT64               ?           ; Length of exclusion range in bytes
+IOMMU_EXCLUSION_RANGE_DESCRIPTOR ENDS
+
+;----------------------------------------------------------------------------
+;   GNB configuration info
+;----------------------------------------------------------------------------
+;
+
+; LVDS Misc Control Field
+LVDS_MISC_CONTROL_FIELD         STRUCT
+  FpdiMode          UINT8       ?
+    ;IN  UINT8     FpdiMode:1;
+    ;IN  UINT8     DlChSwap:1;
+    ;IN  UINT8     VsyncActiveLow:1;
+    ;IN  UINT8     HsyncActiveLow:1;
+    ;IN  UINT8     BLONActiveLow:1;
+    ;IN  UINT8     Reserved:3;
+LVDS_MISC_CONTROL_FIELD         ENDS
+
+; LVDS Misc Control
+LVDS_MISC_CONTROL           UNION
+  Field        LVDS_MISC_CONTROL_FIELD   {}
+  Value        UINT8  ?
+LVDS_MISC_CONTROL           ENDS
+
+; Configuration settings for GNB.
+GNB_ENV_CONFIGURATION          STRUCT
+  Gnb3dStereoPinIndex          UINT8  ?       ;< 3D Stereo Pin ID.
+                                              ;  @li 0 = Stereo 3D is disabled (default).
+                                              ;  @li 1 = Use processor pin HPD1.
+                                              ;  @li 2 = Use processor pin HPD2
+                                              ;  @li 3 = Use processor pin HPD3
+                                              ;  @li 4 = Use processor pin HPD4
+                                              ;  @li 5 = Use processor pin HPD5
+                                              ;  @li 6 = Use processor pin HPD6
+  IommuSupport                 BOOLEAN ?      ; IOMMU support.
+                                              ; TRUE  = Disable and hide IOMMU device.
+                                              ; FLASE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+  LvdsSpreadSpectrum           UINT16  ?      ; Spread spectrum value in 0.01 %
+  LvdsSpreadSpectrumRate       UINT16  ?      ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+  LvdsPowerOnSeqDigonToDe      UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqDeToVaryBl     UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqDeToDigon      UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqVaryBlToDe     UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqOnToOffDelay   UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqVaryBlToBlon   UINT8   ?      ; This item configures panel initialization timing.
+  LvdsPowerOnSeqBlonToVaryBl   UINT8   ?      ; This item configures panel initialization timing.
+  LvdsMaxPixelClockFreq        UINT16  ?      ; This item configures the maximum pixel clock frequency supported.
+  LcdBitDepthControlValue      UINT32  ?      ; This item configures the LCD bit depth control settings.
+  Lvds24bbpPanelMode           UINT8   ?      ; This item configures the LVDS 24 BBP mode.
+  LvdsMiscControl              LVDS_MISC_CONTROL   {}      ; This item configures LVDS swap/Hsync/Vsync/BLON
+  PcieRefClkSpreadSpectrum     UINT16  ?      ; Spread spectrum value in 0.01 %
+  GnbRemoteDisplaySupport      BOOLEAN ?      ; This item enables Wireless Display Support
+GNB_ENV_CONFIGURATION          ENDS
+
+; GNB configuration info
+GNB_CONFIGURATION              STRUCT
+  PcieComplexList              POINTER ?      ; Pointer to array of PCIe_COMPLEX_DESCRIPTOR structures describe PCIe topology on each processor package or NULL.
+                                              ;  Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+                                              ;
+                                              ;
+                                              ;
+                                              ;  Topology organization definition assume PCIe_COMPLEX_DESCRIPTOR defined first following
+                                              ;  PCIe_PORT_DESCRIPTOR and  PCIe_DDI_DESCRIPTOR for given PCIe_COMPLEX_DESCRIPTOR
+                                              ;  defined in arbitrary sequence:
+                                              ;  Example of topology definition for single socket system:
+                                              ;    PlatfromTopology LABEL DWORD
+                                              ;
+                                              ;    Port0_2  PCIe_PORT_DESCRIPTOR <>;
+                                              ;    Port0_3  PCIe_PORT_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST> ;
+                                              ;    ...
+                                              ;    Ddi0_A   PCIe_DDI_DESCRIPTOR <>;
+                                              ;    Ddi0_B   PCIe_DDI_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST,>;
+                                              ;    ...
+                                              ;    Cpu0     PCIe_COMPLEX_DESCRIPTOR <DESCRIPTOR_TERMINATE_LIST, 0, Port0_2, Ddi0_A>
+                                              ;
+                                              ;
+  PsppPolicy                   UINT8  ?       ;< PSPP (PCIe Speed Power Policy)
+                                              ;  @li @b 0 - Disabled
+                                              ;  @li @b 1 - Performance
+                                              ;  @li @b 2 - Balance-High
+                                              ;  @li @b 3 - Balance-Low
+                                              ;  @li @b 4 - Power Saving
+                                              ;
+GNB_CONFIGURATION              ENDS
+
+
+; ---------------------------------------------------------------------------
+
+; MEMORY-SPECIFIC DATA STRUCTURES
+
+; ---------------------------------------------------------------------------
+
+
+ ; AGESA MAXIMIUM VALUES
+
+   ; These Max values are used to define array sizes and associated loop
+   ; counts in the code.  They reflect the maximum values that AGESA
+   ; currently supports and does not necessarily reflect the hardware
+   ; capabilities of configuration.
+
+
+    MAX_SOCKETS_SUPPORTED       EQU    8       ; < Max number of sockets in system
+    MAX_CHANNELS_PER_SOCKET     EQU    4       ; < Max Channels per sockets
+    MAX_DIMMS_PER_CHANNEL       EQU    4       ; < Max DIMMs on a memory channel (independent of platform)
+    NUMBER_OF_DELAY_TABLES      EQU    9       ; < Number of tables defined in CH_DEF_STRUCT.
+                                               ; < Eg: UINT16  *RcvEnDlys;
+                                               ; <     UINT8   *WrDqsDlys;
+                                               ; <     UINT8   *RdDqsDlys;
+                                               ; <     UINT8   *WrDatDlys;
+                                               ; <     UINT8   *RdDqsMinDlys;
+                                               ; <     UINT8   *RdDqsMaxDlys;
+                                               ; <     UINT8   *WrDatMinDlys;
+                                               ; <     UINT8   *WrDatMaxDlys;
+    NUMBER_OF_FAILURE_MASK_TABLES EQU 1        ; < Number of failure mask tables
+    MAX_PLATFORM_TYPES          EQU    16       ; < Platform types per system
+
+    MCT_TRNG_KEEPOUT_START      EQU    00004000h        ; < base [39:8]
+    MCT_TRNG_KEEPOUT_END        EQU    00007FFFh        ; < base [39:8]
+
+    UMA_ATTRIBUTE_INTERLEAVE    EQU    80000000h    ; < Uma Region is interleaved
+    UMA_ATTRIBUTE_ON_DCT0       EQU    40000000h    ; < UMA resides on memory that belongs to DCT0
+    UMA_ATTRIBUTE_ON_DCT1       EQU    20000000h    ; < UMA resides on memory that belongs to DCT1
+
+    PSO_TABLE           TEXTEQU    <UINT8>; < Platform Configuration Table
+
+        ; AGESA DEFINITIONS
+
+        ; Many of these are derived from the platform and hardware specific definitions
+
+ ; EccSymbolSize override value
+    ECCSYMBOLSIZE_USE_BKDG      EQU    0       ; < Use BKDG Recommended Value
+    ECCSYMBOLSIZE_FORCE_X4      EQU    4       ; < Force to x4
+    ECCSYMBOLSIZE_FORCE_X8      EQU    8       ; < Force to x8
+ ; CPU Package Type
+    PT_L1                       EQU    0                     ; < L1 Package type
+    PT_M2                       EQU    1                     ; < AM Package type
+    PT_S1                       EQU    2                     ; < S1 Package type
+
+ ; Structures use to pass system Logical CPU-ID
+CPU_LOGICAL_ID    STRUCT
+  Family                        UINT64 ?        ; < Indicates logical ID Family
+  Revision                      UINT64 ?        ; < Indicates logical ID Family
+CPU_LOGICAL_ID    ENDS
+
+ ; Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+
+  AMD_PLATFORM_SERVER   EQU    8000h    ; < Server
+  AMD_PLATFORM_DESKTOP  EQU    10000h   ; < Desktop
+  AMD_PLATFORM_MOBILE   EQU    20000h   ; < Mobile
+AMD_PLATFORM_TYPE  TEXTEQU  <DWORD>
+
+ ; Dram technology type
+
+  DDR2_TECHNOLOGY       EQU    0        ; < DDR2 technology
+  DDR3_TECHNOLOGY       EQU    1        ; < DDR3 technology
+TECHNOLOGY_TYPE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+
+  DDR400_FREQUENCY      EQU    200      ; < DDR 400
+  DDR533_FREQUENCY      EQU    266      ; < DDR 533
+  DDR667_FREQUENCY      EQU    333      ; < DDR 667
+  DDR800_FREQUENCY      EQU    400      ; < DDR 800
+  DDR1066_FREQUENCY     EQU    533      ; < DDR 1066
+  DDR1333_FREQUENCY     EQU    667      ; < DDR 1333
+  DDR1600_FREQUENCY     EQU    800      ; < DDR 1600
+  DDR1866_FREQUENCY     EQU    933      ; < DDR 1866
+  DDR2100_FREQUENCY     EQU    1050     ; < DDR 2100
+  DDR2133_FREQUENCY     EQU    1066     ; < DDR 2133
+  DDR2400_FREQUENCY     EQU    1200     ; < DDR 2400
+  UNSUPPORTED_DDR_FREQUENCY     EQU    1201      ; < Highest limit of DDR frequency
+MEMORY_BUS_SPEED  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+
+  QUADRANK_REGISTERED   EQU    0
+  QUADRANK_UNBUFFERED   EQU    1
+QUANDRANK_TYPE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+
+  TIMING_MODE_AUTO      EQU    0        ; < Use best rate possible
+  TIMING_MODE_LIMITED   EQU    1        ; < Set user top limit
+  TIMING_MODE_SPECIFIC  EQU    2        ; < Set user specified speed
+USER_MEMORY_TIMING_MODE  TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_POWER_DOWN_MODE
+
+  POWER_DOWN_BY_CHANNEL     EQU 0
+  POWER_DOWN_BY_CHIP_SELECT EQU 1
+  POWER_DOWN_AUTO           EQU 2
+POWER_DOWN_MODE  TEXTEQU  <DWORD>
+
+ ; Low voltage support
+
+  VOLT_INITIAL EQU 0             ; < Initial value for VDDIO
+  VOLT1_5 EQU 1                  ; < 1.5 Volt
+  VOLT1_35 EQU 2                 ; < 1.35 Volt
+  VOLT1_25 EQU 3                 ; < 1.25 Volt
+  VOLT_UNSUPPORTED EQU 0FFh      ; < No common voltage found
+DIMM_VOLTAGE   TEXTEQU  <DWORD>
+
+ ; UMA Mode
+
+  UMA_NONE       EQU    0        ; < UMA None
+  UMA_SPECIFIED  EQU    1        ; < UMA Specified
+  UMA_AUTO       EQU    2        ; < UMA Auto
+UMA_MODE  TEXTEQU  <DWORD>
+
+ ; Force Training Mode
+
+  FORCE_TRAIN_1D       EQU    0        ; < 1D Training only
+  FORCE_TRAIN___       EQU    1        ; <
+  FORCE_TRAIN_AUTO       EQU    2        ; < Auto
+FORCE_TRAIN_MODE  TEXTEQU  <DWORD>
+
+;  The possible DRAM prefetch mode settings.
+  DRAM_PREFETCHER_AUTO             EQU  0           ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_DRAM_PREFETCH_FOR_IO     EQU  1           ; Disable DRAM prefetching for I/O requests only.
+  DISABLE_DRAM_PREFETCH_FOR_CPU    EQU  2           ; Disable DRAM prefetching for requests from processor cores only.
+  DISABLE_DRAM_PREFETCHER          EQU  3           ; Disable DRAM prefetching.
+  MAX_DRAM_FREFETCH_MODE           EQU  4           ; Not a DRAM prefetch mode, use for limit checking.
+DRAM_PREFETCH_MODE     TEXTEQU  <DWORD>
+
+ ; Build Configuration values for BLDCFG_UMA_ALIGNMENT
+
+  NO_UMA_ALIGNED    EQU    00FFFFFFh
+  UMA_4MB_ALIGNED   EQU    00FFFFC0h
+  UMA_128MB_ALIGNED EQU    00FFF800h
+  UMA_256MB_ALIGNED EQU    00FFF000h
+  UMA_512MB_ALIGNED EQU    00FFE000h
+UMA_ALIGNMENT  TEXTEQU  <DWORD>
+ ; ===============================================================================
+   ; Global MCT Configuration Status Word (GStatus)
+ ; ===============================================================================
+
+  GsbMTRRshort          EQU    0        ; < Ran out of MTRRs while mapping memory
+  GsbAllECCDimms        EQU    1        ; < All banks of all Nodes are ECC capable
+  GsbDramECCDis         EQU    2        ; < Dram ECC requested but not enabled.
+  GsbSoftHole           EQU    3        ; < A Node Base gap was created
+  GsbHWHole             EQU    4        ; < A HW dram remap was created
+  GsbNodeIntlv          EQU    5        ; < Node Memory interleaving was enabled
+  GsbSpIntRemapHole     EQU    6        ; < Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW      EQU    7        ; < Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                EQU    8        ; < End of list
+GLOBAL_STATUS_FIELD  TEXTEQU  <DWORD>
+
+; ===============================================================================
+   ; Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+; ===============================================================================
+
+  EsbNoDimms            EQU    0        ; < No DIMMs
+  EsbSpdChkSum          EQU    1        ; < SPD Checksum fail
+  EsbDimmMismatchM      EQU    2        ; < dimm module type(buffer) mismatch
+  EsbDimmMismatchT      EQU    3        ; < dimm CL/T mismatch
+  EsbDimmMismatchO      EQU    4        ; < dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc          EQU    5        ; < SPD missing Trc or Trfc info
+  EsbNoCycTime          EQU    6        ; < SPD missing byte 23 or 25
+  EsbBkIntDis           EQU    7        ; < Bank interleave requested but not enabled
+  EsbDramECCDis         EQU    8        ; < Dram ECC requested but not enabled
+  EsbSpareDis           EQU    9        ; < Online spare requested but not enabled
+  EsbMinimumMode        EQU    10       ; < Running in Minimum Mode
+  EsbNoRcvrEn           EQU    11       ; < No DQS Receiver Enable pass window found
+  EsbSmallRcvr          EQU    12       ; < DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos           EQU    13       ; < No DQS-DQ passing positions
+  EsbSmallDqs           EQU    14       ; < DQS-DQ passing window too small
+  EsbDCBKScrubDis       EQU    15       ; < DCache scrub requested but not enabled
+
+  EsbEMPNotSupported    EQU    16       ; < Processor is not capable for EMP.
+  EsbEMPConflict        EQU    17       ; < EMP requested but cannot be enabled since
+                               ; < channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis             EQU    18       ; < EMP requested but cannot be enabled since
+                               ; < memory size of each DCT is not a power of two.
+
+  EsbEOL                EQU    19       ; < End of list
+ERROR_STATUS_FIELD  TEXTEQU  <DWORD>
+
+; ===============================================================================
+  ; Local Configuration Status (DIE_STRUCT.Status[31:0])
+; ===============================================================================
+
+  SbRegistered          EQU    0        ; < All DIMMs are Registered
+  SbEccDimms            EQU    1        ; < All banks ECC capable
+  SbParDimms            EQU    2        ; < All banks Addr/CMD Parity capable
+  SbDiagClks            EQU    3        ; < Jedec ALL slots clock enable diag mode
+  Sb128bitmode          EQU    4        ; < DCT in 128-bit mode operation
+  Sb64MuxedMode         EQU    5        ; < DCT in 64-bit mux'ed mode.
+  Sb2TMode              EQU    6        ; < 2T CMD timing mode is enabled.
+  SbSWNodeHole          EQU    7        ; < Remapping of Node Base on this Node to create a gap.
+  SbHWHole              EQU    8        ; < Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz          EQU    9        ; < DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2         EQU    10       ; < Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit         EQU    11       ; < Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig           EQU    12       ; < Indicate the default setting for extended PCI configuration support
+  SbLrdimms             EQU    13       ; < All DIMMs are LRDIMMs
+  SbEOL                 EQU    14       ; < End of list
+LOCAL_STATUS_FIELD  TEXTEQU  <DWORD>
+
+
+; < CPU MSR Register definitions ------------------------------------------
+    SYS_CFG                     EQU    0C0010010h
+    TOP_MEM                     EQU    0C001001Ah
+    TOP_MEM2                    EQU    0C001001Dh
+    HWCR                        EQU    0C0010015h
+    NB_CFG                      EQU    0C001001Fh
+
+    FS_BASE                     EQU    0C0000100h
+    IORR0_BASE                  EQU    0C0010016h
+    IORR0_MASK                  EQU    0C0010017h
+    BU_CFG                      EQU    0C0011023h
+    BU_CFG2                     EQU    0C001102Ah
+    COFVID_STAT                 EQU    0C0010071h
+    TSC                         EQU    10h
+
+; ===============================================================================
+ ; SPD Data for each DIMM
+; ===============================================================================
+SPD_DEF_STRUCT    STRUCT
+  DimmPresent                   BOOLEAN ?       ; < Indicates that the DIMM is present and Data is valid
+  Data                          UINT8 (256) DUP (?)     ; < Buffer for 256 Bytes of SPD data from DIMM
+SPD_DEF_STRUCT    ENDS
+
+; ===============================================================================
+ ; Channel Definition Structure
+ ; This data structure defines entries that are specific to the channel initialization
+; ===============================================================================
+CH_DEF_STRUCT    STRUCT
+  ChannelID                     UINT8 ?         ; < Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  TechType                      TECHNOLOGY_TYPE ?       ; < Technology type of this channel
+  ChDimmPresent                 UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is present.
+                                 ; <  DIMM#  Select Signal
+                                 ; <  0      MA0_CS_L[0, 1]
+                                 ; <  1      MB0_CS_L[0, 1]
+                                 ; <  2      MA1_CS_L[0, 1]
+                                 ; <  3      MB1_CS_L[0, 1]
+                                 ; <  4      MA2_CS_L[0, 1]
+                                 ; <  5      MB2_CS_L[0, 1]
+                                 ; <  6      MA3_CS_L[0, 1]
+                                 ; <  7      MB3_CS_L[0, 1]
+
+  DCTPtr                        POINTER ?       ; < Pointer to the DCT data of this channel.
+  MCTPtr                        POINTER ?       ; < Pointer to the node data of this channel.
+  SpdPtr                        POINTER ?       ; < Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  DimmSpdPtr                    POINTER (MAX_DIMMS_PER_CHANNEL) DUP (?)         ; < Array of pointers to
+                                 ; <   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  ChDimmValid                   UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+  RegDimmPresent                UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+  LrDimmPresent                 UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  SODimmPresent                 UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n is a SO-DIMM where 4..7 are reserved.
+  Loads                         UINT8 ?         ; < Number of devices loading bus
+  Dimms                         UINT8 ?         ; < Number of DIMMs loading Channel
+  Ranks                         UINT8 ?         ; < Number of ranks loading Channel DATA
+  SlowMode                      BOOLEAN ?       ; < 1T or 2T CMD mode (slow access mode)
+                                 ; < FALSE = 1T
+                                 ; < TRUE = 2T
+  ; < The following pointers will be pointed to dynamically allocated buffers.
+  ; < Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ; < Example: If DIMM and Byte based training, then
+  ; < XX is a value in Hex
+  ; <                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ; <  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ; <  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  RcvEnDlys                     POINTER ?       ; < DQS Receiver Enable Delays
+  WrDqsDlys                     POINTER ?       ; < Write DQS delays (only valid for DDR3)
+  RdDqsDlys                     POINTER ?       ; < Read Dqs delays
+  WrDatDlys                     POINTER ?       ; < Write Data delays
+  RdDqs__Dlys                   POINTER ?       ; < Read DQS data
+  RdDqsMinDlys                  POINTER ?       ; < Minimum Window for Read DQS
+  RdDqsMaxDlys                  POINTER ?       ; < Maximum Window for Read DQS
+  WrDatMinDlys                  POINTER ?       ; < Minimum Window for Write data
+  WrDatMaxDlys                  POINTER ?       ; < Maximum Window for Write data
+  RcvEnDlysMemPs1               POINTER ?       ; < DQS Receiver Enable Delays for Memory Pstate 1
+  WrDqsDlysMemPs1               POINTER ?       ; < Write DQS delays for Memory Pstate 1 (only valid for DDR3)
+  RdDqsDlysMemPs1               POINTER ?       ; < Read Dqs delays for Memory Pstate 1
+  WrDatDlysMemPs1               POINTER ?       ; < Write Data delays for Memory Pstate 1
+  RdDqs__DlysMemPs1             POINTER ?       ; < Read DQS data for Memory Pstate 1
+  RdDqsMinDlysMemPs1            POINTER ?       ; < Minimum Window for Read DQS for Memory Pstate 1
+  RdDqsMaxDlysMemPs1            POINTER ?       ; < Maximum Window for Read DQS for Memory Pstate 1
+  WrDatMinDlysMemPs1            POINTER ?       ; < Minimum Window for Write data for Memory Pstate 1
+  WrDatMaxDlysMemPs1            POINTER ?       ; < Maximum Window for Write data for Memory Pstate 1
+  RowCount                      UINT8 ?         ; < Number of rows of the allocated buffer.
+  ColumnCount                   UINT8 ?         ; < Number of columns of the allocated buffer.
+
+  FailingBitMask                POINTER ?       ; < Table of masks to Track Failing bits
+  FailingBitMaskMemPs1          POINTER ?       ; < Table of masks to Track Failing bits for Memory Pstate 1
+  DctOdcCtl                     UINT32 ?        ; < Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  DctAddrTmg                    UINT32 ?        ; < Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  PhyRODTCSLow                  UINT32 ?        ; < Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  PhyRODTCSHigh                 UINT32 ?        ; < Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  PhyWODTCSLow                  UINT32 ?        ; < Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  PhyWODTCSHigh                 UINT32 ?        ; < Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  PhyWLODT                      UINT8 (4) DUP (?)       ; < Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  DctEccDqsLike                 UINT16 ?        ; < DCT DQS ECC UINT8 like...
+  DctEccDqsScale                UINT8 ?         ; < DCT DQS ECC UINT8 scale
+  PtrPatternBufA                UINT16 ?        ; < Ptr on stack to aligned DQS testing pattern
+  PtrPatternBufB                UINT16 ?        ; < Ptr on stack to aligned DQS testing pattern
+  ByteLane                      UINT8 ?         ; < Current UINT8 Lane (0..7)
+  Direction                     UINT8 ?         ; < Current DQS-DQ training write direction (0=read, 1=write)
+  Pattern                       UINT8 ?         ; < Current pattern
+  DqsDelay                      UINT8 ?         ; < Current DQS delay value
+  HostBiosSrvc1                 UINT16 ?        ; < UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  HostBiosSrvc2                 UINT32 ?        ; < UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  DctMaxRdLat                   UINT16 (4) DUP (?)      ; < Max Read Latency (ns) for the DCT
+                                                ; < DctMaxRdLat [i] is for NBPstate i  DIMMValidCh                   UINT8 ?         ; < DIMM# in CH
+  DIMMValidCh                   UINT8 ?         ; < DIMM# in CH
+  MaxCh                         UINT8 ?         ; < Max number of CH in system
+  Dct                           UINT8 ?         ; < Dct pointer
+  WrDatGrossH                   UINT8 ?         ; < Write Data Gross delay high value
+  DqsRcvEnGrossL                UINT8 ?         ; < DQS Receive Enable Gross Delay low
+
+  TrwtWB                        UINT8 ?         ; <  Non-SPD timing value for TrwtWB
+  CurrRcvrDctADelay             UINT8 ?         ; < for keep current RcvrEnDly
+  T1000                         UINT16 ?        ; < get the T1000 figure (cycle time (ns) * 1K)
+  DqsRcvEnPass                  UINT8 ?         ; < for TrainRcvrEn UINT8 lane pass flag
+  DqsRcvEnSaved                 UINT8 ?         ; < for TrainRcvrEn UINT8 lane saved flag
+  SeedPass1Remainder            UINT8 ?         ; < for Phy assisted DQS receiver enable training
+
+  ClToNbFlag                    UINT8 ?         ; < is used to restore ClLinesToNbDis bit after memory
+  NodeSysBase                   UINT32 ?        ; < for channel interleave usage
+  RefRawCard                    UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Array of rawcards detected
+  CtrlWrd02                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 2 values per DIMM
+  CtrlWrd03                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 3 values per DIMM
+  CtrlWrd04                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 4 values per DIMM
+  CtrlWrd05                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 5 values per DIMM
+  CtrlWrd08                     UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)           ; < Control Word 8 values per DIMM
+
+  CsPresentDCT                  UINT16 ?        ; < For each bit n 0..7, 1 = Chip-select n is present
+  DimmMirrorPresent             UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n is OnDimmMirror capable
+  DimmSpdCse                    UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n SPD checksum error
+  DimmExclude               UINT8 ?         ; < For each bit n 0..7, 1 = DIMM n gets excluded
+  DimmYr06                      UINT8 ?         ; < Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  DimmWk2406                    UINT8 ?         ; < Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  DimmPlPresent                 UINT8 ?         ; < Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  DimmQrPresent                 UINT8 ?         ; < QuadRank DIMM present?
+  DimmDrPresent                 UINT8 ?         ; < Bitmap indicating that Dual Rank Dimms are present
+  DimmSRPresent                 UINT8 ?         ; < Bitmap indicating that Single Rank Dimms are present
+  Dimmx4Present                 UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+  Dimmx8Present                 UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+  Dimmx16Present                UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+  LrdimmPhysicalRanks           UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)         ; < Number of Physical Ranks for LRDIMMs
+  LrDimmLogicalRanks            UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)         ; < Number of LRDIMM Logical ranks in this configuration
+  LrDimmRankMult                UINT8 (MAX_DIMMS_PER_CHANNEL) DUP (?)         ; < Rank Multipication factor per dimm.
+  DimmNibbleAccess              UINT8 ?         ; < For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+  MemClkDisMap                  POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ; <  base on this array to disable unused MemClk to save power.
+                                  ; <
+                                  ; <  The array must have 8 entries. Each entry, which associates with
+                                  ; <  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ; <    Example:
+                                  ; <    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ; <    is like below:
+                                  ; <         Bit AM3/S1g3 pin name
+                                  ; <         0   M[B,A]_CLK_H/L[0]
+                                  ; <         1   M[B,A]_CLK_H/L[1]
+                                  ; <         2   M[B,A]_CLK_H/L[2]
+                                  ; <         3   M[B,A]_CLK_H/L[3]
+                                  ; <         4   M[B,A]_CLK_H/L[4]
+                                  ; <         5   M[B,A]_CLK_H/L[5]
+                                  ; <         6   M[B,A]_CLK_H/L[6]
+                                  ; <         7   M[B,A]_CLK_H/L[7]
+                                  ; <    And platform has the following routing:
+                                  ; <         CS0   M[B,A]_CLK_H/L[4]
+                                  ; <         CS1   M[B,A]_CLK_H/L[2]
+                                  ; <         CS2   M[B,A]_CLK_H/L[3]
+                                  ; <         CS3   M[B,A]_CLK_H/L[5]
+                                  ; <    Then MemClkDisMap should be pointed to the following array:
+                                  ; <               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ; <    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ; <  Each entry of the array is the bitmask of 8 chip selects.
+
+  CKETriMap                     POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of CKE pins to the DIMMs' ranks.
+                                  ; <  The array must have 2 entries. Each entry, which associates with
+                                  ; <  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ; <  AGESA will base on this array to disable unused CKE pins to save power.
+
+  ODTTriMap                     POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of ODT pins to the DIMMs' ranks.
+                                  ; <  The array must have 4 entries. Each entry, which associates with
+                                  ; <  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ; <  AGESA will base on this array to disable unused ODT pins to save power.
+
+  ChipSelTriMap                 POINTER ?       ; <  This pointer will be set to point to an array that describes
+                                  ; <  the routing of chip select pins to the DIMMs' ranks.
+                                  ; <  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ; <  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  ExtendTmp                     BOOLEAN ?       ; <  If extended temperature is supported on all dimms on a channel.
+
+  MaxVref                        UINT8 ?       ; <  Maximum Vref Value for channel
+
+  Reserved                      UINT8 (100) DUP (?)     ; < Reserved
+CH_DEF_STRUCT    ENDS
+
+; ===============================================================================
+ ; DCT Channel Timing Parameters
+ ; This data structure sets timings that are specific to the channel
+; ===============================================================================
+CH_TIMING_STRUCT    STRUCT
+  DctDimmValid                  UINT16 ?        ; < For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+  DimmMirrorPresent             UINT16 ?        ; < For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  DimmSpdCse                    UINT16 ?        ; < For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+  DimmExclude               UINT16 ?        ; < For each bit n 0..3, 1 = DIMM n gets excluded because of no common voltage is found
+  CsPresent                     UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is present
+  CsEnabled                     UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is enabled
+  CsTestFail                    UINT16 ?        ; < For each bit n 0..7, 1=Chip-select n is present but disabled
+  CsTrainFail                   UINT16 ?        ; < Bitmap showing which chipselects failed training
+  DIMM1KPage                    UINT16 ?        ; < For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved.
+  DimmQrPresent                 UINT16 ?        ; < QuadRank DIMM present?
+  DimmDrPresent                 UINT16 ?        ; < Bitmap indicating that Dual Rank Dimms are present
+  DimmSRPresent                 UINT8 ?         ; < Bitmap indicating that Single Rank Dimms are present
+  Dimmx4Present                 UINT16 ?        ; < For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved.
+  Dimmx8Present                 UINT16 ?        ; < For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved.
+  Dimmx16Present                UINT16 ?        ; < For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved.
+
+  DIMMTrcd                      UINT16 ?        ; < Minimax Trcd*40 (ns) of DIMMs
+  DIMMTrp                       UINT16 ?        ; < Minimax Trp*40 (ns) of DIMMs
+  DIMMTrtp                      UINT16 ?        ; < Minimax Trtp*40 (ns) of DIMMs
+  DIMMTras                      UINT16 ?        ; < Minimax Tras*40 (ns) of DIMMs
+  DIMMTrc                       UINT16 ?        ; < Minimax Trc*40 (ns) of DIMMs
+  DIMMTwr                       UINT16 ?        ; < Minimax Twr*40 (ns) of DIMMs
+  DIMMTrrd                      UINT16 ?        ; < Minimax Trrd*40 (ns) of DIMMs
+  DIMMTwtr                      UINT16 ?        ; < Minimax Twtr*40 (ns) of DIMMs
+  DIMMTfaw                      UINT16 ?        ; < Minimax Tfaw*40 (ns) of DIMMs
+  TargetSpeed                   UINT16 ?        ; < Target DRAM bus speed in MHz
+  Speed                         UINT16 ?        ; < DRAM bus speed in MHz
+                                  ; <  400 (MHz)
+                                  ; <  533 (MHz)
+                                  ; <  667 (MHz)
+                                  ; <  800 (MHz)
+                                  ; <  and so on...
+  CasL                          UINT8 ?         ; < CAS latency DCT setting (busclocks)
+  Trcd                          UINT8 ?         ; < DCT Trcd (busclocks)
+  Trp                           UINT8 ?         ; < DCT Trp (busclocks)
+  Trtp                          UINT8 ?         ; < DCT Trtp (busclocks)
+  Tras                          UINT8 ?         ; < DCT Tras (busclocks)
+  Trc                           UINT8 ?         ; < DCT Trc (busclocks)
+  Twr                           UINT8 ?         ; < DCT Twr (busclocks)
+  Trrd                          UINT8 ?         ; < DCT Trrd (busclocks)
+  Twtr                          UINT8 ?         ; < DCT Twtr (busclocks)
+  Tfaw                          UINT8 ?         ; < DCT Tfaw (busclocks)
+  Trfc0                         UINT8 ?         ; < DCT Logical DIMM0 Trfc
+                                  ; <  0 = 75ns (for 256Mb devs)
+                                  ; <  1 = 105ns (for 512Mb devs)
+                                  ; <  2 = 127.5ns (for 1Gb devs)
+                                  ; < 3 = 195ns (for 2Gb devs)
+                                  ; <  4 = 327.5ns (for 4Gb devs)
+  Trfc1                         UINT8 ?         ; < DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  Trfc2                         UINT8 ?         ; < DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  Trfc3                         UINT8 ?         ; < DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  DctMemSize                    UINT32 ?        ; < Base[47:16], total DRAM size controlled by this DCT.
+  SlowMode                      BOOLEAN ?       ; < 1T or 2T CMD mode (slow access mode)
+                                  ; < FALSE = 1T
+                                  ; < TRUE = 2T
+  TrwtTO                        UINT8 ?         ; < DCT TrwtTO (busclocks)
+  Twrrd                         UINT8 ?         ; < DCT Twrrd (busclocks)
+  Twrwr                         UINT8 ?         ; < DCT Twrwr (busclocks)
+  Trdrd                         UINT8 ?         ; < DCT Trdrd (busclocks)
+  TrwtWB                        UINT8 ?         ; < DCT TrwtWB (busclocks)
+  TrdrdSD                       UINT8 ?         ; < DCT TrdrdSD (busclocks)
+  TwrwrSD                       UINT8 ?         ; < DCT TwrwrSD (busclocks)
+  TwrrdSD                       UINT8 ?         ; < DCT TwrrdSD (busclocks)
+  MaxRdLat                      UINT16 ?        ; < Max Read Latency
+  WrDatGrossH                   UINT8 ?         ; < Temporary variables must be removed
+  DqsRcvEnGrossL                UINT8 ?         ; < Temporary variables must be removed
+CH_TIMING_STRUCT    ENDS
+
+; ===============================================================================
+ ; Data for each DCT
+ ; This data structure defines data used to configure each DRAM controller
+; ===============================================================================
+DCT_STRUCT    STRUCT
+  Dct                           UINT8 ?         ; < Current Dct
+  Timings                       CH_TIMING_STRUCT {}     ; < Channel Timing structure
+  TimingsMemPs1                 POINTER ?       ; < Pointed to channel timing structure for Memory Pstate 1
+  ChData                        POINTER ?       ; < Pointed to a dynamically allocated array of Channel structures
+  ChannelCount                  UINT8 ?         ; < Number of channel per this DCT
+  BkIntDis                      BOOLEAN ?       ; < Bank interleave requested but not enabled on current DCT
+DCT_STRUCT    ENDS
+
+
+; ===============================================================================
+ ; Data Structure defining each Die
+ ; This data structure contains information that is used to configure each Die
+; ===============================================================================
+DIE_STRUCT    STRUCT
+
+   ; Advanced:
+
+  NodeId                        UINT8 ?         ; < Node ID of current controller
+  SocketId                      UINT8 ?         ; < Socket ID of this Die
+  DieId                         UINT8 ?         ; < ID of this die relative to the socket
+  PciAddr                       PCI_ADDR {}      ; < Pci bus and device number of this controller.
+  ErrCode                       AGESA_STATUS ?          ; < Current error condition of Node
+                                   ; <  0x0 = AGESA_SUCCESS
+                                   ; <  0x1 = AGESA_UNSUPPORTED
+                                   ; <  0x2 = AGESA_BOUNDS_CHK
+                                   ; <  0x3 = AGESA_ALERT
+                                   ; <  0x4 = AGESA_WARNING
+                                   ; <  0x5 = AGESA_ERROR
+                                   ; <  0x6 = AGESA_CRITICAL
+                                   ; <  0x7 = AGESA_FATAL
+                                   ; <
+  ErrStatus                     BOOLEAN (EsbEOL) DUP (?)        ; < Error Status bit Field
+  Status                        BOOLEAN (SbEOL) DUP (?)         ; < Status bit Field
+  NodeMemSize                   UINT32 ?        ; < Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+  NodeSysBase                   UINT32 ?        ; < Base[47:16] (system address) DRAM base address of this Node.
+  NodeHoleBase                  UINT32 ?        ; < If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+  NodeSysLimit                  UINT32 ?        ; < Base[47:16] (system address) DRAM limit address of this Node.
+  DimmPresent                   UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is present.
+                                   ; <   DIMM#  Select Signal
+                                   ; <   0      MA0_CS_L[0, 1]
+                                   ; <   1      MB0_CS_L[0, 1]
+                                   ; <   2      MA1_CS_L[0, 1]
+                                   ; <   3      MB1_CS_L[0, 1]
+                                   ; <   4      MA2_CS_L[0, 1]
+                                   ; <   5      MB2_CS_L[0, 1]
+                                   ; <   6      MA3_CS_L[0, 1]
+                                   ; <   7      MB3_CS_L[0, 1]
+  DimmValid                     UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  RegDimmPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is registered DIMM
+  LrDimmPresent                 UINT32 ?        ; < For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  DimmEccPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is ECC capable.
+  DimmParPresent                UINT32 ?        ; < For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+  DimmTrainFail                 UINT16 ?        ; < Bitmap showing which dimms failed training
+  ChannelTrainFail              UINT16 ?        ; < Bitmap showing the channel information about failed Chip Selects
+                                   ; <  0 in any bit field indicates Channel 0
+                                   ; <  1 in any bit field indicates Channel 1
+  Dct                           UINT8 ?         ; <  Need to be removed
+                                   ; <  DCT pointer
+  GangedMode                    BOOLEAN ?       ; < Ganged mode
+                                   ; <  0 = disabled
+                                   ; <  1 = enabled
+  LogicalCpuid                  CPU_LOGICAL_ID {}       ; < The logical CPUID of the node
+  HostBiosSrvc1                 UINT16 ?        ; < UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  HostBiosSrvc2                 UINT32 ?        ; < UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  MLoad                         UINT8 ?         ; < Need to be removed
+                                   ; < Number of devices loading MAA bus
+  MaxAsyncLat                   UINT8 ?         ; < Legacy wrapper
+  ChbD3Rcvrdly                  UINT8 ?         ; < Legacy wrapper
+  ChaMaxRdLat                   UINT16 ?        ; < Max Read Latency (ns) for DCT 0
+  ChbD3BcRcvrdly                UINT8 ?         ; < CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  DctData                       POINTER ?       ; < Pointed to a dynamically allocated array of DCT_STRUCTs
+  DctCount                      UINT8 ?         ; < Number of DCTs per this Die
+  Reserved                      UINT8 (16) DUP (?)      ; < Reserved
+DIE_STRUCT    ENDS
+
+; *********************************************************************
+; * S3 Support structure
+; *********************************************************************
+ ; AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+AMD_S3_PARAMS    STRUCT
+     Signature                  UINT32 ?        ; < "ASTR" for AMD Suspend-To-RAM
+     Version                    UINT16 ?        ; < S3 Params version number
+  Flags                         UINT32 ?        ; < Indicates operation
+  NvStorage                     POINTER ?       ; < Pointer to memory critical save state data
+  NvStorageSize                 UINT32 ?        ; < Size in bytes of the NvStorage region
+  VolatileStorage               POINTER ?       ; < Pointer to remaining AMD save state data
+  VolatileStorageSize           UINT32 ?        ; < Size in bytes of the VolatileStorage region
+AMD_S3_PARAMS    ENDS
+
+; ===============================================================================
+ ; MEM_PARAMETER_STRUCT
+ ; This data structure is used to pass wrapper parameters to the memory configuration code
+; ===============================================================================
+MEM_PARAMETER_STRUCT    STRUCT
+
+   ; Basic (Return parameters)
+   ; (This section contains the outbound parameters from the memory init code)
+
+  GStatus                       BOOLEAN (GsbEOL) DUP (?)        ; < Global Status bitfield
+  HoleBase                      UINT32 ?        ; < If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+  Sub4GCacheTop                 UINT32 ?        ; < If not zero, the 32-bit top of cacheable memory.
+  Sub1THoleBase                 UINT32 ?        ; < If not zero Base[47:16] (system address) of sub 1TB dram hole.
+  SysLimit                      UINT32 ?        ; < Limit[47:16] (system address)
+  DDR3Voltage                   DIMM_VOLTAGE ?    ; < Find support voltage and send back to platform BIOS.
+  ExternalVrefValue             UINT8 ?         ; < Target reference voltage for external Vref for training
+  MemData                       POINTER ?       ; < Pointer to MEM_DATA_STRUCT
+    ; Advanced (Optional parameters)
+    ; Optional (all defaults values will be initialized by the
+    ; 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+    ; to the IBV/OEM to change the defaults after initialization
+    ; but prior to the main entry to the memory code):
+
+   ; Memory Map/Mgt.
+
+  BottomIo                      UINT16 ?        ; < Bottom of 32-bit IO space (8-bits)
+                                   ; <   NV_BOTTOM_IO[7:0]=Addr[31:24]
+  MemHoleRemapping              BOOLEAN ?       ; < Memory Hole Remapping (1-bit)
+                                   ; <  FALSE = disable
+                                   ; <  TRUE  = enable
+  LimitMemoryToBelow1Tb         BOOLEAN ?       ; < Limit memory address space to below 1 TB
+                                                ; <  FALSE = disable
+                                                ; <  TRUE  = enable
+   ; Dram Timing
+
+  UserTimingMode                USER_MEMORY_TIMING_MODE ?       ; < User Memclock Mode
+
+  MemClockValue                 MEMORY_BUS_SPEED ?      ; < Memory Clock Value
+
+   ; Dram Configuration
+
+  EnableBankIntlv               BOOLEAN ?       ; < Dram Bank (chip-select) Interleaving (1-bit)
+                                   ; <   FALSE =disable (AMD default)
+                                   ; <   TRUE =enable
+  EnableNodeIntlv               BOOLEAN ?       ; < Node Memory Interleaving (1-bit)
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+  EnableChannelIntlv            BOOLEAN ?       ; < Channel Interleaving (1-bit)
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+   ; ECC
+
+  EnableEccFeature              BOOLEAN ?       ; < enable ECC error to go into MCE
+                                   ; <   FALSE = disable (AMD default)
+                                   ; <   TRUE = enable
+   ; Dram Power
+
+  EnablePowerDown               BOOLEAN ?       ; < CKE based power down mode (1-bit)
+                                   ; <   FALSE =disable (AMD default)
+                                   ; <   TRUE =enable
+   ; Online Spare
+
+  EnableOnLineSpareCtl          BOOLEAN ?       ; < Chip Select Spare Control bit 0:
+                                   ; <  FALSE = disable Spare (AMD default)
+                                   ; <  TRUE = enable Spare
+  TableBasedAlterations         POINTER ?       ; < Point to an array of data bytes describing desired modifications to register settings.
+
+  PlatformMemoryConfiguration           POINTER ?
+                                   ; < Points to a table that contains platform specific settings
+                                   ; < (i.e. MemClk routing, the number of DIMM slots per channel,...)
+                                   ; < AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ; < contains default conservative settings. Platform BIOS can either tweak
+                                   ; < DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ; <
+  EnableParity                  BOOLEAN ?       ; < Parity control
+                                   ; <  TRUE = enable
+                                   ; <  FALSE = disable (AMD default)
+  EnableBankSwizzle             BOOLEAN ?       ; < BankSwizzle control
+                                   ; <  FALSE = disable
+                                   ; <  TRUE = enable  (AMD default)
+  EnableMemClr                  BOOLEAN ?       ; < Memory Clear functionality control
+                                   ; <  FALSE = disable
+                                   ; <  TRUE = enable  (AMD default)
+  ; Uma Configuration
+
+  UmaMode                       UMA_MODE ?       ; < Uma Mode
+                                   ; <  0 = None
+                                   ; <  1 = Specified
+                                   ; <  2 = Auto
+  UmaSize                       UINT32 ?       ; < The size of shared graphics dram (16-bits)
+                                   ; <  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ; <
+  UmaBase                       UINT32 ?       ; < The allocated Uma base address (32-bits)
+                                   ; <  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ; <
+
+   ; Memory Restore Feature
+
+  MemRestoreCtl                 BOOLEAN ?       ; < Memory context restore control
+                                   ; <   FALSE = perform memory init as normal (AMD default)
+                                   ; <   TRUE = restore memory context and skip training. This requires
+                                   ; <          MemContext is valid before AmdInitPost
+  SaveMemContextCtl             BOOLEAN ?       ; < Control switch to save memory context at the end of MemAuto
+                                   ; <   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ; <   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ; <           expected to call S3Save later in POST if it wants to
+                                   ; <           use memory context restore feature.
+  MemContext                    AMD_S3_PARAMS {}        ; < Memory context block describes the data that platform needs to
+                                   ; < save and restore for memory context restore feature to work.
+                                   ; < It uses the subset of S3Save block to save/restore. Hence platform
+                                   ; < may save only S3 block and uses it for both S3 resume and
+                                   ; < memory context restore.
+                                   ; <  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ; <    before AmdInitPost.
+                                   ; <  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ; <    right after AmdInitPost.
+ ExternalVrefCtl                BOOLEAN ?      ; < Control the use of external Vref
+                                   ; <  TRUE = AGESA will use the function defined in "AGESA_EXTERNAL____TRAIN_VREF_CHANGE" in function list
+                                   ; <          to change the vref
+                                   ; <   FALSE = AGESA will will use the internal vref control.
+ ForceTrainMode                 FORCE_TRAIN_MODE ?       ; < Training Mode
+                                   ; <  0 = Force 1D Training for all configurations
+                                   ; <  1 = Force training for all configurations
+                                   ; <  2 = Auto - AGESA will control
+MEM_PARAMETER_STRUCT    ENDS
+
+
+; ===============================================================================
+ ; Function definition
+ ; This data structure passes function pointers to the memory configuration code.
+ ; The wrapper can use this structure with customized versions
+; ================================================================================
+MEM_FUNCTION_STRUCT    STRUCT
+
+   ; PUBLIC required Internal functions
+
+  amdMemGetPsCfgU       POINTER ?       ; < Proc for Unbuffered DIMMs, platform specific
+  amdMemGetPsCfgR       POINTER ?       ; < Proc for Registered DIMMs, platform specific
+
+   ; PUBLIC optional functions
+
+  amdMemEccInit         POINTER ?       ; < NB proc for ECC feature
+  amdMemChipSelectInterleaveInit        POINTER ?       ; < NB proc for CS interleave feature
+  amdMemDctInterleavingInit     POINTER ?       ; < NB proc for Channel interleave feature
+  amdMemMctInterleavingInit     POINTER ?       ; < NB proc for Node interleave feature
+  amdMemParallelTraining        POINTER ?       ; < NB proc for parallel training feature
+  amdMemEarlySampleSupport      POINTER ?       ; < NB code for early sample support feature
+  amdMemMultiPartInitSupport    POINTER ?       ; < NB code for 'multi-part'
+  amdMemOnlineSpareSupport      POINTER ?       ; < NB code for On-Line Spare feature
+  amdMemUDimmInit       POINTER ?       ; < NB code for UDIMMs
+  amdMemRDimmInit       POINTER ?       ; < NB code for RDIMMs
+  amdMemLrDimmInit       POINTER ?       ; < NB code for LRDIMMs
+  Reserved                      UINT32 (100) DUP (?)    ; < Reserved for later function definition
+MEM_FUNCTION_STRUCT    ENDS
+
+; ===============================================================================
+ ; Socket Structure
+
+; ===============================================================================
+MEM_SOCKET_STRUCT    STRUCT
+  ChannelPtr                    POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?)       ; < Pointers to each channels training data
+
+  TimingsPtr                    POINTER (MAX_CHANNELS_PER_SOCKET) DUP (?)       ; < Pointers to each channels timing data
+
+MEM_SOCKET_STRUCT    ENDS
+
+; ===============================================================================
+ ; MEM_DATA_STRUCT
+; ===============================================================================
+MEM_DATA_STRUCT    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < AGESA Standard Header
+
+  ParameterListPtr              POINTER ?       ; < List of input Parameters
+
+  FunctionList                  MEM_FUNCTION_STRUCT {}          ; < List of function Pointers
+
+  GetPlatformCfg        POINTER (MAX_PLATFORM_TYPES) DUP (?)    ; < look-up platform info
+
+  ErrorHandling         POINTER ?     ; < Error Handling
+
+   ; SocketList is a shortcut for IBVs to retrieve training
+   ; and timing data for each channel indexed by socket/channel,
+   ; eliminating their need to parse die/dct/channel etc.
+   ; It contains pointers to the populated data structures for
+   ; each channel and skips the channel structures that are
+   ; unpopulated. In the case of channels sharing the same DCT,
+   ; the pTimings pointers will point to the same DCT Timing data.
+
+  SocketList                    MEM_SOCKET_STRUCT (MAX_SOCKETS_SUPPORTED) DUP ({})      ; < Socket list for memory code
+
+  DiesPerSystem                 POINTER ?       ; < Pointed to an array of DIE_STRUCTs
+  DieCount                      UINT8 ?         ; < Number of MCTs in the system.
+
+  SpdDataStructure              POINTER ?       ; < Pointer to SPD Data structure
+
+  PlatFormConfig              POINTER ?       ; < Pointer to Platform profile/build option config structure
+
+  IsFlowControlSupported                  BOOLEAN ?       ; < Indicates if flow control is supported
+
+  TscRate                       UINT32 ?        ; < The rate at which the TSC increments in megahertz.
+
+MEM_DATA_STRUCT    ENDS
+
+; ===============================================================================
+; UMA_INFO_STRUCT
+; ===============================================================================
+UMA_INFO      STRUCT
+  UmaBase         UINT64 ?        ; < UmaBase[63:0] = Addr[63:0]
+  UmaSize         UINT32 ?        ; < UmaSize[31:0] = Addr[31:0]
+  UmaAttributes   UINT32 ?        ; < Indicate the attribute of Uma
+  UmaMode         UINT8 ?         ; < Indicate the mode of Uma
+  MemClock        UINT16 ?        ; < Indicate memory running speed in MHz
+  Reserved        UINT8 (3) DUP (?)         ; < Reserved for future usage
+UMA_INFO      ENDS
+
+; ===============================================================================
+; Bitfield for ID
+; ===============================================================================
+ID_FIELD      STRUCT
+  SocketId        UINT16 ?
+;  OUT UINT16 SocketId:8;         ; < Socket ID
+;  OUT UINT16 ModuleId:8;         ; < Module ID
+ID_FIELD      ENDS
+
+; ===============================================================================
+; Union for ID of socket and module that will be passed out in call out
+; ===============================================================================
+ID_INFO      UNION
+  IdField         ID_FIELD {}     ; < Bitfield for ID
+  IdInformation   UINT16 ?        ; < ID information for call out
+ID_INFO      ENDS
+
+  ; AGESA MEMORY ERRORS
+
+ ; AGESA_ALERT Memory Errors
+MEM_ALERT_USER_TMG_MODE_OVERRULED   EQU    04010000h     ; < TIMING_MODE_SPECIFIC is requested but
+                                                       ; < cannot be applied to current configurations.
+MEM_ALERT_ORG_MISMATCH_DIMM         EQU    04010100h     ; < DIMM organization miss-match
+MEM_ALERT_BK_INT_DIS                EQU    04010200h     ; < Bank interleaving disable for internal issue
+
+ ; AGESA_ERROR Memory Errors
+MEM_ERROR_NO_DQS_POS_RD_WINDOW            EQU   04010300h     ; < No DQS Position window for RD DQS
+MEM_ERROR_SMALL_DQS_POS_RD_WINDOW         EQU   04020300h     ; < Small DQS Position window for RD DQS
+MEM_ERROR_NO_DQS_POS_WR_WINDOW            EQU   04030300h     ; < No DQS Position window for WR DQS
+MEM_ERROR_SMALL_DQS_POS_WR_WINDOW         EQU   04040300h     ; < Small DQS Position window for WR DQS
+MEM_ERROR_ECC_DIS                         EQU   04010400h     ; < ECC has been disabled as a result of an internal issue
+MEM_ERROR_DIMM_SPARING_NOT_ENABLED        EQU   04010500h     ; < DIMM sparing has not been enabled for an internal issues
+MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE         EQU   04050300h     ; < Receive Enable value is too large
+MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW       EQU   04060300h     ; < There is no DQS receiver enable window
+MEM_ERROR_DRAM_ENABLED_TIME_OUT           EQU   04010600h     ; < Time out when polling DramEnabled bit
+MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT        EQU   04010700h     ; < Time out when polling DctAccessDone bit
+MEM_ERROR_SEND_CTRL_WORD_TIME_OUT         EQU   04010800h     ; < Time out when polling SendCtrlWord bit
+MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT   EQU   04010900h     ; < Time out when polling PrefDramTrainMode bit
+MEM_ERROR_ENTER_SELF_REF_TIME_OUT         EQU   04010A00h     ; < Time out when polling EnterSelfRef bit
+MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT       EQU   04010B00h     ; < Time out when polling FreqChgInProg bit
+MEM_ERROR_EXIT_SELF_REF_TIME_OUT          EQU   04020A00h     ; < Time out when polling ExitSelfRef bit
+MEM_ERROR_SEND_MRS_CMD_TIME_OUT           EQU   04010C00h     ; < Time out when polling SendMrsCmd bit
+MEM_ERROR_SEND_ZQ_CMD_TIME_OUT            EQU   04010D00h     ; < Time out when polling SendZQCmd bit
+MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT  EQU   04010E00h     ; < Time out when polling DctExtraAccessDone bit
+MEM_ERROR_MEM_CLR_BUSY_TIME_OUT           EQU   04010F00h     ; < Time out when polling MemClrBusy bit
+MEM_ERROR_MEM_CLEARED_TIME_OUT            EQU   04020F00h     ; < Time out when polling MemCleared bit
+MEM_ERROR_FLUSH_WR_TIME_OUT               EQU   04011000h     ; < Time out when polling FlushWr bit
+MEM_ERROR_MAX_LAT_NO_WINDOW               EQU   04070300h     ; < Fail to find pass during Max Rd Latency training
+MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL   EQU   04080300h     ; < Fail to launch training code on an AP
+MEM_ERROR_PARALLEL_TRAINING_TIME_OUT      EQU   04090300h     ; < Fail to finish parallel training
+MEM_ERROR_NO_ADDRESS_MAPPING              EQU   04011100h     ; < No address mapping found for a dimm
+MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  EQU   040A0300h ; < There is no DQS receiver enable window and the value is equal to the largest value
+MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE EQU   040B0300h ; < Receive Enable value is too large and is 1 less than limit
+MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR EQU    04011200h    ; < SPD Checksum error for NV_SPDCHK_RESTRT
+MEM_ERROR_NO_CHIPSELECT                   EQU   04011300h     ; < No chipselects found
+MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM        EQU   04011500h     ; < Unbuffered dimm is not supported at 333MHz
+MEM_ERROR_WL_PRE_OUT_OF_RANGE             EQU   040C0300h     ; < Returned PRE value during write levelization was out of range
+MEM_ERROR_NO____RDDQS_WINDOW              EQU   040D0300h     ; < No RdDqs Window
+MEM_ERROR_NO____RDDQS_HEIGHT              EQU   040E0300h     ; < No RdDqs Height
+MEM_ERROR____DQS_ERROR                    EQU   040F0300h     ; < RdDqs Error
+MEM_ERROR_INVALID____RDDQS_VALUE          EQU   04022400h     ; < RdDqs invalid value found
+MEM_ERROR____DQS_VREF_MARGIN_ERROR        EQU   04023400h     ; < RdDqs Vef Margin error found
+MEM_ERROR_LR_IBT_NOT_FOUND                EQU   04013500h     ; < No LR dimm IBT value is found
+MEM_ERROR_MR0_NOT_FOUND                   EQU   04023500h     ; < No MR0 value is found
+MEM_ERROR_ODT_PATTERN_NOT_FOUND           EQU   04033500h     ; < No odt pattern value is found
+MEM_ERROR_RC2_IBT_NOT_FOUND               EQU   04043500h     ; < No RC2 IBT value is found
+MEM_ERROR_RC10_OP_SPEED_NOT_FOUND         EQU   04053500h     ; < No RC10 op speed is found
+MEM_ERROR_RTT_NOT_FOUND                   EQU   04063500h     ; < No RTT value is found
+MEM_ERROR_P___NOT_FOUND                   EQU   04073500h     ; < No training config value is found
+MEM_ERROR_SAO_NOT_FOUND                   EQU   04083500h     ; < No slow access mode, Address timing and Output driver compensation value is found
+MEM_ERROR_CLK_DIS_MAP_NOT_FOUND           EQU   04093500h     ; < No CLK disable map is found
+MEM_ERROR_CKE_TRI_MAP_NOT_FOUND           EQU   040A3500h     ; < No CKE tristate map is found
+MEM_ERROR_ODT_TRI_MAP_NOT_FOUND           EQU   040B3500h     ; < No ODT tristate map is found
+MEM_ERROR_CS_TRI_MAP_NOT_FOUND            EQU   040C3500h     ; < No CS tristate map is found
+MEM_ERROR_TRAINING_SEED_NOT_FOUND         EQU   040D3500h     ; < No training seed is found
+
+ ; AGESA_WARNING Memory Errors
+    MEM_WARNING_UNSUPPORTED_QRDIMM      EQU    04011600h     ; < QR DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_UDIMM       EQU    04021600h     ; < U DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_SODIMM      EQU    04031600h     ; < SO-DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_X4DIMM      EQU    04041600h     ; < x4 DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_RDIMM       EQU    04051600h     ; < R DIMMs detected but not supported
+    MEM_WARNING_UNSUPPORTED_LRDIMM      EQU    04061600h     ; < LR DIMMs detected but not supported
+
+    MEM_WARNING_EMP_NOT_SUPPORTED       EQU    04011700h     ; < Processor is not capable for EMP
+    MEM_WARNING_EMP_CONFLICT    EQU    04021700h      ; < EMP cannot be enabled if channel interleaving,
+                                                        ; < bank interleaving, or bank swizzle is enabled.
+    MEM_WARNING_EMP_NOT_ENABLED EQU    04031700h      ; < Memory size is not power of two.
+    MEM_WARNING_ECC_DIS         EQU    04041700h      ; < ECC has been disabled as a result of an internal issue
+    MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED EQU 04011800h  ; < Performance has been enabled, but battery life is preferred.
+    MEM_WARNING_NO_SPDTRC_FOUND EQU    04011900h      ; < No Trc timing value found in SPD of a dimm.
+    MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED     EQU     04012000h    ; < Node Interleaveing Requested, but could not be enabled
+    MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED  EQU     04012100h    ; < Channel Interleaveing Requested, but could not be enabled
+    MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED     EQU     04012200h    ; < Bank Interleaveing Requested, but could not be enabled
+    MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED        EQU     04012300h    ; < Voltage 1.35 determined, but could not be supported
+    MEM_WARNING_INITIAL_DDR3VOLT_NONZERO          EQU     04012400h    ; < DDR3 voltage initial value is not 0
+    MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO       EQU     04012500h    ; < Cannot find a commonly supported VDDIO
+
+ ; AGESA_FATAL Memory Errors
+    MEM_ERROR_MINIMUM_MODE      EQU    04011A00h                   ; < Running in minimum mode
+    MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM EQU    04011B00h      ; < DIMM modules are miss-matched
+    MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM    EQU    04011C00h     ; < No DIMMs have been found on system
+    MEM_ERROR_MISMATCH_DIMM_CLOCKS      EQU    04011D00h          ; < DIMM clocks miss-matched
+    MEM_ERROR_NO_CYC_TIME       EQU    04011E00h                    ; < No cycle time found
+    MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   EQU    04011F00h ; < Heap allocation error with dynamic storing of trained timings
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   EQU    04021F00h ; < Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+    MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   EQU    04031F00h ; < Heap allocation error with REMOTE_TRAINING_ENV
+    MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     EQU    04041F00h    ; < Heap allocation error for SPD data
+    MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     EQU    04051F00h    ; < Heap allocation error for RECEIVED_DATA during parallel training
+    MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     EQU    04061F00h    ; < Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+    MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     EQU    04071F00h    ; < Heap allocation error for Training Data
+    MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     EQU    04081F00h   ; < Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+    MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM    EQU    04022300h    ; < No Constructor for DIMM Identify
+    MEM_ERROR_VDDIO_UNSUPPORTED   EQU   04022500h     ; < VDDIO of the dimms on the board is not supported
+    MEM_ERROR_HEAP_ALLOCATE_FOR___   EQU  040B1F00h    ; < Heap allocation error for training data
+    MEM_ERROR_HEAP_DEALLOCATE_FOR___  EQU     040C1F00h  ; < Heap de-allocation error for training data
+
+ ; AGESA_CRITICAL Memory Errors
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     EQU    04091F00h    ; < Heap allocation error for DMI table for DDR3
+    MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     EQU    040A1F00h    ; < Heap allocation error for DMI table for DDR2
+    MEM_ERROR_UNSUPPORTED_DIMM_CONFIG    EQU   04011400h          ; < Dimm population is not supported
+
+
+; ----------------------------------------------------------------------------
+; *
+; *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+; *
+; *----------------------------------------------------------------------------
+;
+
+
+; ----------------------------------------------------------------------------
+; *
+; *                    CPU RELATED DEFINITIONS
+; *
+; *----------------------------------------------------------------------------
+;
+
+; CPU Event definitions.
+
+; Defines used to filter CPU events based on functional blocks
+CPU_EVENT_PM_EVENT_MASK                         EQU   0FF00FF00h
+CPU_EVENT_PM_EVENT_CLASS                        EQU   008000400h
+
+;================================================================
+; CPU General events
+;    Heap allocation                    (AppFunction =     01h)
+CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            EQU   008000100h
+CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           EQU   008010100h
+CPU_ERROR_HEAP_IS_FULL                          EQU   008020100h
+CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    EQU   008030100h
+CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     EQU   008040100h
+;    BrandId                            (AppFunction =     02h)
+CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            EQU   008000200h
+;    Micro code patch                   (AppFunction =     03h)
+CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        EQU   008000300h
+;    Power management                   (AppFunction =     04h)
+CPU_EVENT_PM_PSTATE_OVERCURRENT                 EQU   008000400h
+CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             EQU   008010400h
+CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             EQU   008020400h
+CPU_ERROR_PM_NB_PSTATE_MISMATCH                 EQU   008030400h
+;   Other CPU events                    (AppFunction =     05h)
+CPU_EVENT_BIST_ERROR                            EQU   008000500h
+CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY              EQU   008010500h
+CPU_EVENT_STACK_REENTRY                         EQU   008020500h
+CPU_EVENT_CORE_NOT_IDENTIFIED                   EQU   008030500h
+;=================================================================
+; CPU Feature events
+;    Execution cache                    (AppFunction =     21h)
+;        AGESA_CACHE_SIZE_REDUCED                          2101
+;        AGESA_CACHE_REGIONS_ACROSS_1MB                    2102
+;        AGESA_CACHE_REGIONS_ACROSS_4GB                    2103
+;        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY              2104
+;        AGESA_CACHE_START_ADDRESS_LESS_D0000              2105
+;        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB               2106
+;        AGESA_DEALLOCATE_CACHE_REGIONS                    2107
+CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      EQU   008002100h
+;    Core Leveling                      (AppFunction =     22h)
+CPU_WARNING_ADJUSTED_LEVELING_MODE              EQU   008002200h
+;    HT Assist                          (AppFunction =     23h)
+CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            EQU   008002300h
+
+; CPU Build Configuration structures and definitions
+
+; Build Configuration values for BLDGCFG_AP_MTRR_SETTINGS
+AP_MTRR_SETTINGS  STRUCT
+  MsrAddr       UINT32 ?  ; < Fixed-Sized MTRR address
+  MsrData       UINT64 ?  ; < MTRR Settings
+AP_MTRR_SETTINGS  ENDS
+
+AMD_AP_MTRR_FIX64k_00000    EQU 000000250h
+AMD_AP_MTRR_FIX16k_80000    EQU 000000258h
+AMD_AP_MTRR_FIX16k_A0000    EQU 000000259h
+AMD_AP_MTRR_FIX4k_C0000     EQU 000000268h
+AMD_AP_MTRR_FIX4k_C8000     EQU 000000269h
+AMD_AP_MTRR_FIX4k_D0000     EQU 00000026Ah
+AMD_AP_MTRR_FIX4k_D8000     EQU 00000026Bh
+AMD_AP_MTRR_FIX4k_E0000     EQU 00000026Ch
+AMD_AP_MTRR_FIX4k_E8000     EQU 00000026Dh
+AMD_AP_MTRR_FIX4k_F0000     EQU 00000026Eh
+AMD_AP_MTRR_FIX4k_F8000     EQU 00000026Fh
+CPU_LIST_TERMINAL           EQU 0FFFFFFFFh
+
+; ***********************************************************************
+; *
+; *  AGESA interface Call-Out function parameter structures
+; *
+; **********************************************************************
+
+ ; Parameters structure for interface call-out AgesaAllocateBuffer
+AGESA_BUFFER_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  BufferLength                  UINT32 ?        ; < Size of buffer to allocate
+  BufferHandle                  UINT32 ?        ; < Identifier or name for the buffer
+  BufferPointer                 POINTER ?       ; < location of the created buffer
+AGESA_BUFFER_PARAMS    ENDS
+
+ ; Parameters structure for interface call-out AgesaRunCodeOnAp
+AP_EXE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  FunctionNumber                UINT32 ?        ; < Index of the procedure to execute
+  RelatedDataBlock              POINTER ?       ; < Location of data structure the procedure will use
+  RelatedBlockLength            UINT32 ?        ; < Size of the related data block
+AP_EXE_PARAMS    ENDS
+
+ ; Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+AGESA_READ_SPD_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < standard header
+  SocketId                      UINT8 ?         ; < Address of SPD - socket ID
+  MemChannelId                  UINT8 ?         ; < Address of SPD - memory channel ID
+  DimmId                        UINT8 ?         ; < Address of SPD - DIMM ID
+  Buffer                        POINTER ?       ; < Location where to place the SPD content
+  MemData                       POINTER ?       ; < Location of the MemData structure, for reference
+AGESA_READ_SPD_PARAMS    ENDS
+
+ ; Buffer Handles
+  AMD_DMI_INFO_BUFFER_HANDLE    EQU    000D000h ; < Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE EQU    000D001h ; < Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE EQU    000D002h ; < Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE    EQU    000D003h ; < Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE   EQU    000D004h ; < Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE   EQU    000D005h ; < Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE        EQU    000D006h ; < Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE     EQU    000D007h ; < Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE  EQU    000D008h ; < Assign 0x000D008 buffer handle to S3 NB device info
+  AMD_ACPI_ALIB_BUFFER_HANDLE   EQU    000D009h ; < Assign 0x000D009 buffer handle to ALIB SSDT table
+  AMD_ACPI_IVRS_BUFFER_HANDLE   EQU    000D00Ah ; < Assign 0x000D00A buffer handle to IOMMU IVRS table
+AMD_BUFFER_HANDLE  TEXTEQU  <DWORD>
+; ***********************************************************************
+; *
+; *  AGESA interface Call-Out function prototypes
+; *
+; **********************************************************************
+
+; ***********************************************************************
+; *
+; *  AGESA interface structure definition and function prototypes
+; *
+; **********************************************************************
+
+; *********************************************************************
+; * Platform Configuration:  The parameters in boot branch function
+; *********************************************************************
+
+;   The possible platform control flow settings.
+  Nfcm                          EQU  0            ; < Normal Flow Control Mode.
+  UmaDr                         EQU  1            ; < UMA using Display Refresh flow control.
+  UmaIfcm                       EQU  2            ; < UMA using Isochronous Flow Control.
+  Ifcm                          EQU  3            ; < Isochronous Flow Control Mode (other than for UMA).
+  Iommu                         EQU  4            ; < An IOMMU is in use in the system.
+  MaxControlFlow                EQU  5            ; < Not a control flow mode, use for limit checking.
+PLATFORM_CONTROL_FLOW  TEXTEQU  <DWORD>
+
+;   Platform Deemphasis Levels.
+  DeemphasisLevelNone            EQU  0           ; < No Deemphasis.
+  DeemphasisLevelMinus3          EQU  1           ; < Minus 3 db deemphasis.
+  DeemphasisLevelMinus6          EQU  2           ; < Minus 6 db deemphasis.
+  DeemphasisLevelMinus8          EQU  3           ; < Minus 8 db deemphasis.
+  DeemphasisLevelMinus11         EQU  4           ; < Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8     EQU  5           ; < Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone                   EQU  16          ; < No DCV Deemphasis.
+  DcvLevelMinus2                 EQU  17          ; < Minus 2 db DCV deemphasis.
+  DcvLevelMinus3                 EQU  18          ; < Minus 3 db DCV deemphasis.
+  DcvLevelMinus5                 EQU  19          ; < Minus 5 db DCV deemphasis.
+  DcvLevelMinus6                 EQU  20          ; < Minus 6 db DCV deemphasis.
+  DcvLevelMinus7                 EQU  21          ; < Minus 7 db DCV deemphasis.
+  DcvLevelMinus8                 EQU  22          ; < Minus 8 db DCV deemphasis.
+  DcvLevelMinus9                 EQU  23          ; < Minus 9 db DCV deemphasis.
+  DcvLevelMinus11                EQU  24          ; < Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel     EQU  25          ; < Not a deemphasis level, use for limit checking.
+PLATFORM_DEEMPHASIS_LEVEL  TEXTEQU  <DWORD>
+
+;   Provide Deemphasis Levels for HT Links.
+;
+;   For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+;   be checked for a match. The item matches for a Socket, Link if the link frequency is
+;   is in the inclusive range HighFreq:LoFreq.
+;   AGESA does not set deemphasis in IO devices, only in processors.
+
+CPU_HT_DEEMPHASIS_LEVEL STRUCT
+  ; Match fields
+  Socket                   UINT8  ?               ; < One Socket on which this Link is located
+  Link                     UINT8  ?               ; < The Link on this Processor.
+  LoFreq                   UINT8  ?               ; < If the link is set to this frequency or greater, apply these levels, and
+  HighFreq                 UINT8  ?               ; < If the link is set to this frequency or less, apply these levels.
+  ; Value fields
+  ReceiverDeemphasis       PLATFORM_DEEMPHASIS_LEVEL ? ; < The deemphasis level for this link
+  DcvDeemphasis            PLATFORM_DEEMPHASIS_LEVEL ? ; < The DCV, or far transmitter deemphasis level.
+CPU_HT_DEEMPHASIS_LEVEL ENDS
+
+;  The possible hardware prefetch mode settings.
+  HARDWARE_PREFETCHER_AUTO         EQU  0           ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_L1_PREFETCHER            EQU  1           ; Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
+  DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES  EQU 2  ; Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+  DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES  EQU 3  ; Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
+  DISABLE_HARDWARE_PREFETCH        EQU  4           ; Disable hardware prefetching.
+  MAX_HARDWARE_PREFETCH_MODE       EQU  5           ; Not a hardware prefetch mode, use for limit checking.
+HARDWARE_PREFETCH_MODE  TEXTEQU  <DWORD>
+
+;  The possible software prefetch mode settings.
+  SOFTWARE_PREFETCHES_AUTO         EQU  0           ; Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_SOFTWARE_PREFETCHES      EQU  1           ; Disable software prefetches (convert software prefetch instructions to NOP).
+  MAX_SOFTWARE_PREFETCH_MODE       EQU  2           ; Not a software prefetch mode, use for limit checking.
+SOFTWARE_PREFETCH_MODE TEXTEQU  <DWORD>
+
+; Advanced performance tunings, prefetchers.
+; These settings provide for performance tuning to optimize for specific workloads.
+ADVANCED_PERFORMANCE_PROFILE STRUCT
+  HardwarePrefetchMode          HARDWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+  SoftwarePrefetchMode          SOFTWARE_PREFETCH_MODE ? ; This value provides for advanced performance tuning by controlling the software prefetch instructions.
+  DramPrefetchMode              DRAM_PREFETCH_MODE ?     ; This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+ADVANCED_PERFORMANCE_PROFILE ENDS
+
+;   The possible platform power policy settings.
+  Performance                    EQU  0           ; < Optimize for performance.
+  BatteryLife                    EQU  1           ; < Optimize for battery life.
+  MaxPowerPolicy                 EQU  2           ; < Not a power policy mode, use for limit checking.
+PLATFORM_POWER_POLICY  TEXTEQU  <DWORD>
+
+; Platform performance settings for optimized settings.
+; Several configuration settings for the processor depend upon other parts and
+; general designer choices for the system. The determination of these data points
+; is not standard for all platforms, so the host environment needs to provide these
+; to specify how the system is to be configured.
+PERFORMANCE_PROFILE    STRUCT
+  PlatformControlFlowMode       PLATFORM_CONTROL_FLOW ?  ; < The platform's control flow mode for optimum platform performance.
+  UseHtAssist                   BOOLEAN ?       ; < HyperTransport link traffic optimization.
+  UseAtmMode                    BOOLEAN ?       ; < HyperTransport link traffic optimization.
+  Use32ByteRefresh              BOOLEAN ?       ; < Display Refresh traffic generates 32 byte requests.
+  UseVariableMctIsocPriority    BOOLEAN ?       ; < The Memory controller will be set to Variable Isoc Priority.
+  AdvancedPerformanceProfile ADVANCED_PERFORMANCE_PROFILE {}  ; < The advanced platform performance settings.
+  PlatformPowerPolicy           PLATFORM_POWER_POLICY ?  ; < The platform's desired power policy
+PERFORMANCE_PROFILE    ENDS
+
+; Platform settings that describe the voltage regulator modules of the system.
+; Many power management settings are dependent upon the characteristics of the
+; on-board voltage regulator module (VRM).  The host environment needs to provide
+; these to specify how the system is to be configured.
+PLATFORM_VRM_CONFIGURATION   STRUCT
+  CurrentLimit                  UINT32 ?         ; < Vrm Current Limit.
+  LowPowerThreshold             UINT32 ?         ; < Vrm Low Power Threshold.
+  SlewRate                      UINT32 ?         ; < Vrm Slew Rate.
+  AdditionalDelay               UINT32 ?         ; < Vrm Additional Delay.
+  HiSpeedEnable                 BOOLEAN ?        ; < Select high speed VRM.
+  InrushCurrentLimit            UINT32 ?         ; < Vrm Inrush Current Limit.
+PLATFORM_VRM_CONFIGURATION   ENDS
+
+;   The VRM types to characterize.
+  CoreVrm                        EQU  0           ; < VDD plane.
+  NbVrm                          EQU  1           ; < VDDNB plane.
+  MaxVrmType                     EQU  2           ; < Not a valid VRM type, use for limit checking.
+PLATFORM_VRM_TYPE  TEXTEQU  <DWORD>
+
+; FCH Platform Configuration Policy
+FCH_PLATFORM_POLICY     STRUCT
+  CfgSmbus0BaseAddress          UINT16  ?       ; SMBUS0 Controller Base Address
+  CfgSmbus1BaseAddress          UINT16  ?       ; SMBUS1 Controller Base Address
+  CfgSioPmeBaseAddress          UINT16  ?       ; I/O base address for LPC I/O target range
+  CfgAcpiPm1EvtBlkAddr          UINT16  ?       ; I/O base address of ACPI power management Event Block
+  CfgAcpiPm1CntBlkAddr          UINT16  ?       ; I/O base address of ACPI power management Control Block
+  CfgAcpiPmTmrBlkAddr           UINT16  ?       ; I/O base address of ACPI power management Timer Block
+  CfgCpuControlBlkAddr          UINT16  ?       ; I/O base address of ACPI power management CPU Control Block
+  CfgAcpiGpe0BlkAddr            UINT16  ?       ; I/O base address of ACPI power management General Purpose Event Block
+  CfgSmiCmdPortAddr             UINT16  ?       ; I/O base address of ACPI SMI Command Block
+  CfgAcpiPmaCntBlkAddr          UINT16  ?       ; I/O base address of ACPI power management additional control block
+  CfgGecShadowRomBase           UINT32  ?       ; 32-bit base address to the GEC shadow ROM
+  CfgWatchDogTimerBase          UINT32  ?       ; Watchdog Timer base address
+  CfgSpiRomBaseAddress          UINT32  ?       ; Base address for the SPI ROM controller
+  CfgHpetBaseAddress            UINT32  ?       ; HPET MMIO base address
+  CfgAzaliaSsid                 UINT32  ?       ; Subsystem ID of HD Audio controller
+  CfgSmbusSsid                  UINT32  ?       ; Subsystem ID of SMBUS controller
+  CfgIdeSsid                    UINT32  ?       ; Subsystem ID of IDE controller
+  CfgSataAhciSsid               UINT32  ?       ; Subsystem ID of SATA controller in AHCI mode
+  CfgSataIdeSsid                UINT32  ?       ; Subsystem ID of SATA controller in IDE mode
+  CfgSataRaid5Ssid              UINT32  ?       ; Subsystem ID of SATA controller in RAID5 mode
+  CfgSataRaidSsid               UINT32  ?       ; Subsystem ID of SATA controller in RAID mode
+  CfgEhciSsid                   UINT32  ?       ; Subsystem ID of EHCI
+  CfgOhciSsid                   UINT32  ?       ; Subsystem ID of OHCI
+  CfgLpcSsid                    UINT32  ?       ; Subsystem ID of LPC ISA Bridge
+  CfgSdSsid                     UINT32  ?       ; Subsystem ID of SecureDigital controller
+  CfgXhciSsid                   UINT32  ?       ; Subsystem ID of XHCI
+  CfgFchPort80BehindPcib        BOOLEAN ?       ; Is port80 cycle going to the PCI bridge
+  CfgFchEnableAcpiSleepTrap     BOOLEAN ?       ; ACPI sleep SMI enable/disable
+  CfgFchGppLinkConfig           GPP_LINKMODE ?  ; FCH GPP link configuration
+  CfgFchGppPort0Present         BOOLEAN ?       ; Is FCH GPP port 0 present
+  CfgFchGppPort1Present         BOOLEAN ?       ; Is FCH GPP port 1 present
+  CfgFchGppPort2Present         BOOLEAN ?       ; Is FCH GPP port 2 present
+  CfgFchGppPort3Present         BOOLEAN ?       ; Is FCH GPP port 3 present
+  CfgFchGppPort0HotPlug         BOOLEAN ?       ; Is FCH GPP port 0 hotplug capable
+  CfgFchGppPort1HotPlug         BOOLEAN ?       ; Is FCH GPP port 1 hotplug capable
+  CfgFchGppPort2HotPlug         BOOLEAN ?       ; Is FCH GPP port 2 hotplug capable
+  CfgFchGppPort3HotPlug         BOOLEAN ?       ; Is FCH GPP port 3 hotplug capable
+
+  CfgFchEsataPortBitMap         UINT8 ?         ; ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+  CfgFchIrPinControl            UINT8 ?         ; Register bitfield describing Infrared Pin Control:
+  CfgFchSdClockControl       SD_CLOCK_CONTROL ? ; FCH SD Clock Control
+  CfgFchSciMapControl           POINTER ?       ; FCH SCI Mapping Control
+  CfgFchSataPhyControl          POINTER ?       ; FCH SATA PHY Control
+  CfgFchGpioControl             POINTER ?       ; FCH GPIO Control
+FCH_PLATFORM_POLICY     ENDS
+
+
+; Build Option/Configuration Boolean Structure
+BUILD_OPT_CFG    STRUCT
+  ; Build Option Area
+  VersionString                 AMD_CODE_HEADER {} ; < AMD embedded code version string
+  OptionUDimms                  BOOLEAN ?       ; < UDIMMS
+  OptionRDimms                  BOOLEAN ?       ; < RDIMMS
+  OptionLrDimms                 BOOLEAN ?       ; < LRDIMMS
+  OptionEcc                     BOOLEAN ?       ; < ECC
+  OptionBankInterleave          BOOLEAN ?       ; < BANK_INTERLEAVE
+  OptionDctInterleave           BOOLEAN ?       ; < DCT_INTERLEAVE
+  OptionNodeInterleave          BOOLEAN ?       ; < NODE_INTERLEAVE
+  OptionParallelTraining        BOOLEAN ?       ; < PARALLEL_TRAINING
+  OptionOnlineSpare             BOOLEAN ?       ; < ONLINE_SPARE
+  OptionMemRestore              BOOLEAN ?       ; < MEM CONTEXT RESTORE
+  OptionMultisocket             BOOLEAN ?       ; < MULTISOCKET
+  OptionAcpiPstates             BOOLEAN ?       ; < ACPI_PSTATES
+  OptionPStatesInHpcMode        BOOLEAN ?       ; < PSTATES_HPC_MODE
+  OptionSrat                    BOOLEAN ?       ; < SRAT
+  OptionSlit                    BOOLEAN ?       ; < SLIT
+  OptionWhea                    BOOLEAN ?       ; < WHEA
+  OptionDmi                     BOOLEAN ?       ; < DMI
+  OptionEarlySamples            BOOLEAN ?       ; < EARLY_SAMPLES
+  OptionAddrToCsTranslator      BOOLEAN ?       ; < ADDR_TO_CS_TRANSLATOR
+
+  ; Build Configuration Area
+  CfgPciMmioAddress             UINT64 ?        ; < PciMmioBase
+  CfgPciMmioSize                UINT32 ?        ; < PciMmioSize
+  CfgPlatVrmCfg                 PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({})  ; < Several configuration settings for the voltage regulator modules.
+  CfgPlatNumIoApics             UINT32 ?        ; < PlatformApicIoNumber
+  CfgMemInitPstate              UINT32 ?        ; < MemoryInitPstate
+  CfgPlatformC1eMode            PLATFORM_C1E_MODES ?  ; < PlatformC1eMode
+  CfgPlatformC1eOpData          UINT32 ?        ; < PlatformC1eOpData
+  CfgPlatformC1eOpData1         UINT32 ?        ; < PlatformC1eOpData1
+  CfgPlatformC1eOpData2         UINT32 ?        ; < PlatformC1eOpData2
+  CfgPlatformC1eOpData3         UINT32 ?        ; < PlatformC1eOpData3
+  CfgPlatformCStateMode         PLATFORM_CSTATE_MODES ?  ; < PlatformCStateMode
+  CfgPlatformCStateOpData       UINT32 ?        ; < PlatformCStateOpData
+  CfgPlatformCStateIoBaseAddress UINT16 ?       ; < PlatformCStateIoBaseAddress
+  CfgPlatformCpbMode            PLATFORM_CPB_MODES ?  ; < PlatformCpbMode
+  CfgLowPowerPstateForProcHot   PLATFORM_LOW_POWER_PSTATE_MODES ?  ; < Low power Pstate for PROCHOT mode
+  CfgCoreLevelingMode           UINT32 ?        ; < CoreLevelingCofig
+  CfgPerformanceProfile         PERFORMANCE_PROFILE  {}  ; < The platform's control flow mode and platform performance settings.
+  CfgPlatformDeemphasisList     POINTER  ?      ; < HT Deemphasis
+  CfgAmdPlatformType            UINT32 ?        ; < AmdPlatformType
+  CfgAmdPstateCapValue          UINT32 ?        ; < Amd pstate ceiling enabling deck
+
+  CfgMemoryBusFrequencyLimit    MEMORY_BUS_SPEED ?      ; < Memory Bus Frequency Limit
+  CfgMemoryModeUnganged         BOOLEAN ?       ; < Memory Mode Unganged
+  CfgMemoryQuadRankCapable      BOOLEAN ?       ; < Memory Quad Rank Capable
+  CfgMemoryQuadrankType         QUANDRANK_TYPE ?        ; < Memory Quadrank Type
+  CfgMemoryRDimmCapable         BOOLEAN ?       ; < Memory RDIMM Capable
+  CfgMemoryLRDimmCapable         BOOLEAN ?       ; < Memory LRDIMM Capable
+  CfgMemoryUDimmCapable         BOOLEAN ?       ; < Memory UDIMM Capable
+  CfgMemorySODimmCapable        BOOLEAN ?       ; < Memory SODimm Capable
+  CfgLimitMemoryToBelow1Tb      BOOLEAN ?       ; < Limit memory address space to below 1TB
+  CfgMemoryEnableBankInterleaving       BOOLEAN ?       ; < Memory Enable Bank Interleaving
+  CfgMemoryEnableNodeInterleaving       BOOLEAN ?       ; < Memory Enable Node Interleaving
+  CfgMemoryChannelInterleaving  BOOLEAN ?       ; < Memory Channel Interleaving
+  CfgMemoryPowerDown            BOOLEAN ?       ; < Memory Power Down
+  CfgPowerDownMode              POWER_DOWN_MODE ?       ; < Power Down Mode
+  CfgOnlineSpare                BOOLEAN ?       ; < Online Spare
+  CfgMemoryParityEnable         BOOLEAN ?       ; < Memory Parity Enable
+  CfgBankSwizzle                BOOLEAN ?       ; < Bank Swizzle
+  CfgTimingModeSelect           USER_MEMORY_TIMING_MODE ?       ; < Timing Mode Select
+  CfgMemoryClockSelect          MEMORY_BUS_SPEED ?      ; < Memory Clock Select
+  CfgDqsTrainingControl         BOOLEAN ?       ; < Dqs Training Control
+  CfgIgnoreSpdChecksum          BOOLEAN ?       ; < Ignore Spd Checksum
+  CfgUseBurstMode               BOOLEAN ?       ; < Use Burst Mode
+  CfgMemoryAllClocksOn          BOOLEAN ?       ; < Memory All Clocks On
+  CfgEnableEccFeature           BOOLEAN ?       ; < Enable ECC Feature
+  CfgEccRedirection             BOOLEAN ?       ; < ECC Redirection
+  CfgScrubDramRate              UINT16 ?        ; < Scrub Dram Rate
+  CfgScrubL2Rate                UINT16 ?        ; < Scrub L2Rate
+  CfgScrubL3Rate                UINT16 ?        ; < Scrub L3Rate
+  CfgScrubIcRate                UINT16 ?        ; < Scrub Ic Rate
+  CfgScrubDcRate                UINT16 ?        ; < Scrub Dc Rate
+  CfgEccSyncFlood               BOOLEAN ?       ; < ECC Sync Flood
+  CfgEccSymbolSize              UINT16 ?        ; < ECC Symbol Size
+  CfgHeapDramAddress            UINT64 ?        ; < Heap contents will be temporarily stored in this address during the transition
+  CfgNodeMem1GBAlign            BOOLEAN ?       ; < Node Mem 1GB boundary Alignment
+  CfgS3LateRestore              BOOLEAN ?       ; < S3 Late Restore
+  CfgAcpiPstateIndependent      BOOLEAN ?       ; < PSD method dependent/Independent
+  CfgApMtrrSettingsList         POINTER ?       ; < The AP's MTRR settings before final halt
+  CfgUmaMode                    UMA_MODE ?      ; < Uma Mode
+  CfgUmaSize                    UINT32 ?        ; < Uma Size [31:0]=Addr[47:16]
+  CfgUmaAbove4G                 BOOLEAN ?       ; < Uma Above 4G Support
+  CfgUmaAlignment               UMA_ALIGNMENT ? ; < Uma alignment
+  CfgProcessorScopeInSb         BOOLEAN ?       ; < ACPI Processor Object in \_SB scope
+  CfgProcessorScopeName0        CHAR8 ?         ; < OEM specific 1st character of processor scope name.
+  CfgProcessorScopeName1        CHAR8 ?         ; < OEM specific 2nd character of processor scope name.
+  CfgGnbHdAudio                 UINT8 ?         ; < Gnb HD Audio Enable
+  CfgAbmSupport                 UINT8 ?         ; < ABM support
+  CfgDynamicRefreshRate         UINT8 ?         ; < Dynamic refresh rate
+  CfgLcdBackLightControl        UINT16 ?        ; < Lcd back light control
+  CfgGnb3dStereoPinIndex        UINT8 ?         ; < 3D Stereo Pin ID
+  CfgTempPcieMmioBaseAddress    UINT32 ?        ; < Temp pcie MMIO base address
+  CfgGnbIGPUSSID                UINT32 ?        ; < Gnb internal GPU SSID
+  CfgGnbHDAudioSSID             UINT32 ?        ; < Gnb HD Audio SSID
+  CfgGnbPcieSSID                UINT32 ?        ; < Gnb PCIe SSID
+  CfgLvdsSpreadSpectrum         UINT16  ?       ; < Lvds Spread Spectrum. Build-time customizable only
+  CfgLvdsSpreadSpectrumRate     UINT16  ?       ; < Lvds Spread Spectrum Rate. Build-time customizable only
+  FchBldCfg                     POINTER ?       ; < FCH platform build configuration policy
+  CfgIommuSupport               BOOLEAN ?       ; IOMMU support
+  CfgLvdsPowerOnSeqDigonToDe    UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqDeToVaryBl   UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqDeToDigon    UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqVaryBlToDe   UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqOnToOffDelay UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqVaryBlToBlon UINT8   ?       ; Panel initialization timing
+  CfgLvdsPowerOnSeqBlonToVaryBl UINT8   ?       ; Panel initialization timing
+  CfgLvdsMaxPixelClockFreq      UINT16  ?       ; The maximum pixel clock frequency supported
+  CfgLcdBitDepthControlValue    UINT32  ?       ; The LCD bit depth control settings
+  CfgLvds24bbpPanelMode         UINT8   ?       ; The LVDS 24 BBP mode
+  CfgLvdsMiscControl            LVDS_MISC_CONTROL   {}; THe LVDS Misc control
+  CfgPcieRefClkSpreadSpectrum   UINT16  ?       ; PCIe Reference Clock Spread Spectrum
+  CfgExternalVrefCtlFeature     BOOLEAN ?       ; External Vref control
+  CfgForceTrainMode             FORCE_TRAIN_MODE ?      ; < Force Train Mode
+  CfgGnbRemoteDisplaySupport    BOOLEAN ?       ; Wireless Display Support
+  CfgIvrsExclusionRangeList     POINTER ?       ; IOMMU Exclusion Range List
+  Reserved                      BOOLEAN ?       ; < reserved...
+BUILD_OPT_CFG    ENDS
+
+  ; A structure containing platform specific operational characteristics. This
+  ; structure is initially populated by the initializer with a copy of the same
+  ; structure that was created at build time using the build configuration controls.
+PLATFORM_CONFIGURATION    STRUCT
+  PlatformProfile               PERFORMANCE_PROFILE {}          ; < Several configuration settings for the processor.
+  PlatformDeemphasisList        POINTER ?       ; < Deemphasis levels for the platform's HT links.
+  CoreLevelingMode              UINT8 ?         ; < Indicates how to balance the number of cores per processor.
+  C1eMode                       PLATFORM_C1E_MODES ? ; < Specifies the method of C1e enablement - Disabled, HW, or message based.
+  C1ePlatformData               UINT32 ?        ; < If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+  C1ePlatformData1              UINT32 ?        ; < If C1eMode is SW, specifies the address of chipset's SMI command port.
+  C1ePlatformData2              UINT32 ?        ; < If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+  C1ePlatformData3              UINT32 ?        ; < If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
+  CStateMode                    PLATFORM_CSTATE_MODES ? ; < Specifies the method of C-State enablement - Disabled, or C6.
+  CStatePlatformData            UINT32 ?        ; < This element specifies some pertinent data needed for the operation of the Cstate feature
+                                                ; < If CStateMode is CStateModeC6, this item is reserved
+  CStateIoBaseAddress           UINT16 ?        ; < This item specifies a free block of 8 consecutive bytes of I/O ports that
+                                                ; < can be used to allow the CPU to enter Cstates.
+  CpbMode                       PLATFORM_CPB_MODES ? ; < Specifies the method of core performance boost enablement - Disabled, or Auto.
+  UserOptionDmi                 BOOLEAN ?       ; < When set to TRUE, the DMI data table is generated.
+  UserOptionPState              BOOLEAN ?       ; < When set to TRUE, the PState data tables are generated.
+  UserOptionSrat                BOOLEAN ?       ; < When set to TRUE, the SRAT data table is generated.
+  UserOptionSlit                BOOLEAN ?       ; < When set to TRUE, the SLIT data table is generated.
+  UserOptionWhea                BOOLEAN ?       ; < When set to TRUE, the WHEA data table is generated.
+  LowPowerPstateForProcHot      PLATFORM_LOW_POWER_PSTATE_MODES ? ; < Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+  PowerCeiling                  UINT32 ?        ; < P-State Ceiling Enabling Deck - Max power milli-watts.
+  ForcePstateIndependent        BOOLEAN ?       ; < P-State _PSD independence or dependence.
+  PStatesInHpcMode              BOOLEAN ?       ; < High performance computing (HPC) mode
+  NumberOfIoApics               UINT32 ?        ; < Number of I/O APICs in the system
+  VrmProperties                 PLATFORM_VRM_CONFIGURATION (MaxVrmType) DUP ({})  ; < Several configuration settings for the voltage regulator modules.
+  ProcessorScopeInSb            BOOLEAN ?       ; < ACPI Processor Object in \_SB scope
+  ProcessorScopeName0           CHAR8 ?         ; < OEM specific 1st character of processor scope name.
+  ProcessorScopeName1           CHAR8 ?         ; < OEM specific 2nd character of processor scope name.
+  GnbHdAudio                    UINT8 ?         ; < Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                ; < essentially it enables function 1 of graphics device.
+                                                ; < @li 0 = HD Audio disable
+                                                ; < @li 1 = HD Audio enable
+  AbmSupport                    UINT8 ?         ; < Automatic adjust LVDS/eDP Back light level support.It is
+                                                ; < characteristic specific to display panel which used by platform design.
+                                                ; < @li 0 = ABM support disabled
+                                                ; < @li 1 = ABM support enabled
+  DynamicRefreshRate            UINT8 ?         ; < Adjust refresh rate on LVDS/eDP.
+  LcdBackLightControl           UINT16 ?        ; < The PWM frequency to LCD backlight control.
+                                                ; < If equal to 0 backlight not controlled by iGPU.
+PLATFORM_CONFIGURATION    ENDS
+
+
+; *********************************************************************
+; * Structures for: AmdInitLate
+; *********************************************************************
+    PROC_VERSION_LENGTH         EQU    48
+    MAX_DIMMS_PER_SOCKET        EQU    16
+
+
+  ; Interface Parameter Structures
+ ; DMI Type4 - Processor ID
+TYPE4_PROC_ID    STRUCT
+  ProcIdLsd                     UINT32 ?        ; < Lower half of 64b ID
+  ProcIdMsd                     UINT32 ?        ; < Upper half of 64b ID
+TYPE4_PROC_ID    ENDS
+
+ ; DMI Type 4 - Processor information
+TYPE4_DMI_INFO    STRUCT
+  T4ProcType                    UINT8 ?         ; < CPU Type
+  T4ProcFamily                  UINT8 ?         ; < Family 1
+  T4ProcId                      TYPE4_PROC_ID {}        ; < Id
+  T4Voltage                     UINT8 ?         ; < Voltage
+  T4ExternalClock               UINT16 ?        ; < External clock
+  T4MaxSpeed                    UINT16 ?        ; < Max speed
+  T4CurrentSpeed                UINT16 ?        ; < Current speed
+  T4Status                      UINT8 ?         ; < Status
+  T4ProcUpgrade                 UINT8 ?         ; < Up grade
+  T4CoreCount                   UINT8 ?         ; < Core count
+  T4CoreEnabled                 UINT8 ?         ; < Core Enable
+  T4ThreadCount                 UINT8 ?         ; < Thread count
+  T4ProcCharacteristics         UINT16 ?        ; < Characteristics
+  T4ProcFamily2                 UINT16 ?        ; < Family 2
+  T4ProcVersion                 CHAR8 (PROC_VERSION_LENGTH) DUP (?)     ; < Cpu version
+TYPE4_DMI_INFO    ENDS
+
+ ; DMI Type 7 - Cache information
+TYPE7_DMI_INFO    STRUCT
+  T7CacheCfg                    UINT16 ?        ; < Cache cfg
+  T7MaxCacheSize                UINT16 ?        ; < Max size
+  T7InstallSize                 UINT16 ?        ; < Install size
+  T7SupportedSramType           UINT16 ?        ; < Supported Sram Type
+  T7CurrentSramType             UINT16 ?        ; < Current type
+  T7CacheSpeed                  UINT8 ?         ; < Speed
+  T7ErrorCorrectionType         UINT8 ?         ; < ECC type
+  T7SystemCacheType             UINT8 ?         ; < Cache type
+  T7Associativity               UINT8 ?         ; < Associativity
+TYPE7_DMI_INFO    ENDS
+
+ ; DMI Type 16 offset 04h - Location
+
+  OtherLocation         EQU    01h      ; < Assign 01 to Other
+  UnknownLocation       EQU    2        ; < Assign 02 to Unknown
+  SystemboardOrMotherboard      EQU    3        ; < Assign 03 to systemboard or motherboard
+  IsaAddonCard          EQU    4        ; < Assign 04 to ISA add-on card
+  EisaAddonCard         EQU    5        ; < Assign 05 to EISA add-on card
+  PciAddonCard          EQU    6        ; < Assign 06 to PCI add-on card
+  McaAddonCard          EQU    7        ; < Assign 07 to MCA add-on card
+  PcmciaAddonCard       EQU    8        ; < Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard  EQU    9        ; < Assign 09 to proprietary add-on card
+  NuBus                 EQU    10       ; < Assign 0A to NuBus
+  Pc98C20AddonCard      EQU    11       ; < Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard      EQU    12       ; < Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard        EQU    13       ; < Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard EQU    14       ; < Assign 0A3 to PC-98/Local bus add-on card
+DMI_T16_LOCATION  TEXTEQU  <DWORD> ;} DMI_T16_LOCATION;
+
+ ; DMI Type 16 offset 05h - Memory Error Correction
+
+  OtherUse              EQU    01h      ; < Assign 01 to Other
+  UnknownUse            EQU    2        ; < Assign 02 to Unknown
+  SystemMemory          EQU    3        ; < Assign 03 to system memory
+  VideoMemory           EQU    4        ; < Assign 04 to video memory
+  FlashMemory           EQU    5        ; < Assign 05 to flash memory
+  NonvolatileRam        EQU    6        ; < Assign 06 to non-volatile RAM
+  CacheMemory           EQU    7        ; < Assign 07 to cache memory
+DMI_T16_USE  TEXTEQU  <DWORD> ;} DMI_T16_USE;
+
+ ; DMI Type 16 offset 07h - Maximum Capacity
+
+  Dmi16OtherErrCorrection    EQU    01h ; < Assign 01 to Other
+  Dmi16UnknownErrCorrection  EQU    2   ; < Assign 02 to Unknown
+  Dmi16NoneErrCorrection     EQU    3   ; < Assign 03 to None
+  Dmi16Parity                EQU    4   ; < Assign 04 to parity
+  Dmi16SingleBitEcc          EQU    5   ; < Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc           EQU    6   ; < Assign 06 to Multi-bit ECC
+  Dmi16Crc                   EQU    7   ; < Assign 07 to CRC
+DMI_T16_ERROR_CORRECTION  TEXTEQU  <DWORD> ;} DMI_T16_ERROR_CORRECTION;
+
+ ; DMI Type 16 - Physical Memory Array
+TYPE16_DMI_INFO    STRUCT
+  Location                      DMI_T16_LOCATION ?      ; < The physical location of the Memory Array,
+                                                        ; < whether on the system board or an add-in board.
+  Use                           DMI_T16_USE ?           ; < Identifies the function for which the array
+                                                        ; < is used.
+  MemoryErrorCorrection         DMI_T16_ERROR_CORRECTION ?      ; < The primary hardware error correction or
+                                                        ; < detection method supported by this memory array.
+  MaximumCapacity               UINT32 ?        ; < The maximum memory capacity, in kilobytes,
+                                                        ; < for the array.
+  NumberOfMemoryDevices         UINT16 ?        ; < The number of slots or sockets available
+                                                        ; < for memory devices in this array.
+  ExtMaxCapacity                UINT64 ?                ; < The maximum memory capacity, in bytes,
+                                                        ; < for this array.
+TYPE16_DMI_INFO    ENDS
+
+ ; DMI Type 17 offset 0Eh - Form Factor
+  OtherFormFactor       EQU    01h      ; < Assign 01 to Other
+  UnknowFormFactor      EQU    2        ; < Assign 02 to Unknown
+  SimmFormFactor        EQU    3        ; < Assign 03 to SIMM
+  SipFormFactor         EQU    4        ; < Assign 04 to SIP
+  ChipFormFactor        EQU    5        ; < Assign 05 to Chip
+  DipFormFactor         EQU    6        ; < Assign 06 to DIP
+  ZipFormFactor         EQU    7        ; < Assign 07 to ZIP
+  ProprietaryCardFormFactor     EQU    8        ; < Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor      EQU    9        ; < Assign 09 to DIMM
+  TsopFormFactor        EQU    10       ; < Assign 10 to TSOP
+  RowOfChipsFormFactor  EQU    11       ; < Assign 11 to Row of chips
+  RimmFormFactor        EQU    12       ; < Assign 12 to RIMM
+  SodimmFormFactor      EQU    13       ; < Assign 13 to SODIMM
+  SrimmFormFactor       EQU    14       ; < Assign 14 to SRIMM
+  FbDimmFormFactor      EQU    15       ; < Assign 15 to FB-DIMM
+DMI_T17_FORM_FACTOR  TEXTEQU  <DWORD>
+
+ ; DMI Type 17 offset 12h - Memory Type
+  OtherMemType          EQU    01h      ; < Assign 01 to Other
+  UnknownMemType        EQU    2        ; < Assign 02 to Unknown
+  DramMemType           EQU    3        ; < Assign 03 to DRAM
+  EdramMemType          EQU    4        ; < Assign 04 to EDRAM
+  VramMemType           EQU    5        ; < Assign 05 to VRAM
+  SramMemType           EQU    6        ; < Assign 06 to SRAM
+  RamMemType            EQU    7        ; < Assign 07 to RAM
+  RomMemType            EQU    8        ; < Assign 08 to ROM
+  FlashMemType          EQU    9        ; < Assign 09 to Flash
+  EepromMemType         EQU    10       ; < Assign 10 to EEPROM
+  FepromMemType         EQU    11       ; < Assign 11 to FEPROM
+  EpromMemType          EQU    12       ; < Assign 12 to EPROM
+  CdramMemType          EQU    13       ; < Assign 13 to CDRAM
+  ThreeDramMemType      EQU    14       ; < Assign 14 to 3DRAM
+  SdramMemType          EQU    15       ; < Assign 15 to SDRAM
+  SgramMemType          EQU    16       ; < Assign 16 to SGRAM
+  RdramMemType          EQU    17       ; < Assign 17 to RDRAM
+  DdrMemType            EQU    18       ; < Assign 18 to DDR
+  Ddr2MemType           EQU    19       ; < Assign 19 to DDR2
+  Ddr2FbdimmMemType     EQU    20       ; < Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType           EQU    24       ; < Assign 24 to DDR3
+  Fbd2MemType           EQU    25       ; < Assign 25 to FBD2
+DMI_T17_MEMORY_TYPE  TEXTEQU  <DWORD>
+
+ ; DMI Type 17 offset 13h - Type Detail
+DMI_T17_TYPE_DETAIL    STRUCT
+  Reserved1                     UINT16 ?
+;   OUT UINT16                    Reserved1:1;                  ; < Reserved
+;   OUT UINT16                    Other:1;                      ; < Other
+;   OUT UINT16                    Unknown:1;                    ; < Unknown
+;   OUT UINT16                    FastPaged:1;                  ; < Fast-Paged
+;   OUT UINT16                    StaticColumn:1;               ; < Static column
+;   OUT UINT16                    PseudoStatic:1;               ; < Pseudo-static
+;   OUT UINT16                    Rambus:1;                     ; < RAMBUS
+;   OUT UINT16                    Synchronous:1;                ; < Synchronous
+;   OUT UINT16                    Cmos:1;                       ; < CMOS
+;   OUT UINT16                    Edo:1;                        ; < EDO
+;   OUT UINT16                    WindowDram:1;                 ; < Window DRAM
+;   OUT UINT16                    CacheDram:1;                  ; < Cache Dram
+;   OUT UINT16                    NonVolatile:1;                ; < Non-volatile
+;   OUT UINT16                    Reserved2:3;                  ; < Reserved
+DMI_T17_TYPE_DETAIL    ENDS
+
+ ; DMI Type 17 - Memory Device
+TYPE17_DMI_INFO    STRUCT
+  TotalWidth                    UINT16 ?        ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
+  DataWidth                     UINT16 ?        ; < Data Width, in bits, of this memory device.
+  MemorySize                    UINT16 ?        ; < The size of the memory device.
+  FormFactor                    DMI_T17_FORM_FACTOR ?           ; < The implementation form factor for this memory device.
+  DeviceSet                     UINT8 ?         ; < Identifies when the Memory Device is one of a set of
+                                                        ; < Memory Devices that must be populated with all devices of
+                                                        ; < the same type and size, and the set to which this device belongs.
+  DeviceLocator                 CHAR8 (8) DUP (?)       ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  BankLocator                   CHAR8 (10) DUP (?)      ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
+  MemoryType                    DMI_T17_MEMORY_TYPE ?           ; < The type of memory used in this device.
+  TypeDetail                    DMI_T17_TYPE_DETAIL {}          ; < Additional detail on the memory device type
+  Speed                         UINT16 ?                ; < Identifies the speed of the device, in megahertz (MHz).
+  ManufacturerIdCode            UINT64 ?                ; < Manufacturer ID code.
+  SerialNumber                  CHAR8 (9) DUP (?)       ; < Serial Number.
+  PartNumber                    CHAR8 (19) DUP (?)      ; < Part Number.
+  Attributes                    UINT8 ?                 ; < Bits 7-4: Reserved, Bits 3-0: rank.
+  ExtSize                       UINT32 ?                ; < Extended Size.
+  ConfigSpeed                   UINT16 ?        ; < Configured memory clock speed
+TYPE17_DMI_INFO    ENDS
+
+ ; Memory DMI Type 17 and 20 - for memory use
+MEM_DMI_INFO    STRUCT
+  TotalWidth                    UINT16 ?              ; < Total Width, in bits, of this memory device, including any check or error-correction bits.
+  DataWidth                     UINT16 ?              ; < Data Width, in bits, of this memory device.
+  MemorySize                    UINT16 ?              ; < The size of the memory device.
+  FormFactor                    DMI_T17_FORM_FACTOR ? ; < The implementation form factor for this memory device.
+  DeviceLocator                 UINT8 ?               ; < The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  BankLocator                   UINT8 ?               ; < The string number of the string that identifies the physically labeled bank where the memory device is located.
+  Speed                         UINT16 ?              ; < Identifies the speed of the device, in megahertz (MHz).
+  ManufacturerIdCode            UINT64 ?              ; < Manufacturer ID code.
+  SerialNumber                  UINT8 (4) DUP (?)     ; < Serial Number.
+  PartNumber                    UINT8 (18) DUP (?)    ; < Part Number.
+  Attributes                    UINT8 ?               ; < Bits 7-4: Reserved, Bits 3-0: rank.
+  ExtSize                       UINT32 ?              ; < Extended Size.
+  Socket                        UINT8 ?
+; OUT UINT8                     Socket:3              ; < Socket ID
+; OUT UINT8                     Channel:2             ; < Channel ID
+; OUT UINT8                     Dimm:2                ; < DIMM ID
+; OUT UINT8                     DimmPresent:1         ; < Dimm Present
+  StartingAddr                  UINT32 ?              ; < The physical address, in kilobytes, of a range
+                                                      ; < of memory mapped to the referenced Memory Device.
+  EndingAddr                    UINT32 ?              ; < The handle, or instance number, associated with
+                                                      ; < the Memory Device structure to which this address
+                                                      ; < range is mapped.
+  ConfigSpeed                   UINT16 ?              ; < Configured memory clock speed
+  ExtStartingAddr               UINT64 ?              ; < The physical address, in bytes, of a range of
+                                                      ; < memory mapped to the referenced Memory Device.
+  ExtEndingAddr                 UINT64 ?              ; < The physical ending address, in bytes, of the last of
+                                                      ; < a range of addresses mapped to the referenced Memory Device.
+MEM_DMI_INFO    ENDS
+
+ ; DMI Type 19 - Memory Array Mapped Address
+TYPE19_DMI_INFO    STRUCT
+  StartingAddr                  UINT32 ?        ; < The physical address, in kilobytes,
+                                                        ; < of a range of memory mapped to the
+                                                        ; < specified physical memory array.
+  EndingAddr                    UINT32 ?        ; < The physical ending address of the
+                                                        ; < last kilobyte of a range of addresses
+                                                        ; < mapped to the specified physical memory array.
+  MemoryArrayHandle             UINT16 ?        ; < The handle, or instance number, associated
+                                                        ; < with the physical memory array to which this
+                                                        ; < address range is mapped.
+  PartitionWidth                UINT8 ?         ; < Identifies the number of memory devices that
+                                                        ; < form a single row of memory for the address
+                                                        ; < partition defined by this structure.
+  ExtStartingAddr               UINT64 ?              ; < The physical address, in bytes, of a range of
+                                                      ; < memory mapped to the specified Physical Memory Array.
+  ExtEndingAddr                 UINT64 ?              ; < The physical address, in bytes, of a range of
+                                                      ; < memory mapped to the specified Physical Memory Array.
+TYPE19_DMI_INFO    ENDS
+
+; DMI Type 20 - Memory Device Mapped Address
+TYPE20_DMI_INFO    STRUCT
+  StartingAddr                  UINT32 ?        ; < The physical address, in kilobytes, of a range
+                                                        ; < of memory mapped to the referenced Memory Device.
+  EndingAddr                    UINT32 ?        ; < The handle, or instance number, associated with
+                                                        ; < the Memory Device structure to which this address
+                                                        ; < range is mapped.
+  MemoryDeviceHandle            UINT16 ?        ; < The handle, or instance number, associated with
+                                                        ; < the Memory Device structure to which this address
+                                                        ; < range is mapped.
+  MemoryArrayMappedAddressHandle        UINT16 ?        ; < The handle, or instance number, associated
+                                                        ; < with the Memory Array Mapped Address structure to
+                                                        ; < which this device address range is mapped.
+  PartitionRowPosition          UINT8 ?         ; < Identifies the position of the referenced Memory
+                                                        ; < Device in a row of the address partition.
+  InterleavePosition            UINT8 ?         ; < The position of the referenced Memory Device in
+                                                        ; < an interleave.
+  InterleavedDataDepth          UINT8 ?         ; < The maximum number of consecutive rows from the
+                                                        ; < referenced Memory Device that are accessed in a
+                                                        ; < single interleaved transfer.
+  ExtStartingAddr               UINT64 ?              ; < The physical address, in bytes, of a range of
+                                                      ; < memory mapped to the referenced Memory Device.
+  ExtEndingAddr                 UINT64 ?              ; < The physical ending address, in bytes, of the last of
+                                                      ; < a range of addresses mapped to the referenced Memory Device.
+TYPE20_DMI_INFO    ENDS
+
+ ; Collection of pointers to the DMI records
+DMI_INFO    STRUCT
+  T4                            TYPE4_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 4 struc
+  T7L1                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 1
+  T7L2                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 2
+  T7L3                          TYPE7_DMI_INFO (MAX_SOCKETS_SUPPORTED) DUP ({})         ; < Type 7 struc 3
+  T16                           TYPE16_DMI_INFO {}      ; < Type 16 struc
+  T17                           TYPE17_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({})          ; < Type 17 struc
+  T19                           TYPE19_DMI_INFO {}      ; < Type 19 struc
+  T20                           TYPE20_DMI_INFO (MAX_SOCKETS_SUPPORTED * MAX_CHANNELS_PER_SOCKET * MAX_DIMMS_PER_CHANNEL) DUP ({})          ; < Type 20 struc
+DMI_INFO    ENDS
+
+
+
+; *********************************************************************
+; * Interface call:  AllocateExecutionCache
+; *********************************************************************
+    MAX_CACHE_REGIONS           EQU    3
+
+ ; AllocateExecutionCache sub param structure for cached memory region
+EXECUTION_CACHE_REGION    STRUCT
+  ExeCacheStartAddr             UINT32 ?        ; < Start address
+  ExeCacheSize                  UINT32 ?        ; < Size
+EXECUTION_CACHE_REGION    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdGetAvailableExeCacheSize
+; *********************************************************************
+ ; Get available Cache remain
+AMD_GET_EXE_SIZE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+     AvailableExeCacheSize      UINT32 ?        ; < Remain size
+AMD_GET_EXE_SIZE_PARAMS    ENDS
+
+
+
+
+
+
+ ; Selection type for core leveling
+  CORE_LEVEL_LOWEST     EQU    0        ; < Level to lowest common denominator
+  CORE_LEVEL_TWO        EQU    1        ; < Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO       EQU    2        ; < Level to 1,2,4 or 8
+  CORE_LEVEL_NONE       EQU    3        ; < Do no leveling
+  CORE_LEVEL_COMPUTE_UNIT EQU  4        ; < Level cores to one core per compute unit
+  CORE_LEVEL_ONE        EQU    5        ; < Level to 1 core
+  CORE_LEVEL_THREE      EQU    6        ; < Level to 3 cores
+  CORE_LEVEL_FOUR       EQU    7        ; < Level to 4 cores
+  CORE_LEVEL_FIVE       EQU    8        ; < Level to 5 cores
+  CORE_LEVEL_SIX        EQU    9        ; < Level to 6 cores
+  CORE_LEVEL_SEVEN      EQU    10       ; < Level to 7 cores
+  CORE_LEVEL_EIGHT      EQU    11       ; < Level to 8 cores
+  CORE_LEVEL_NINE       EQU    12       ; < Level to 9 cores
+  CORE_LEVEL_TEN        EQU    13       ; < Level to 10 cores
+  CORE_LEVEL_ELEVEN     EQU    14       ; < Level to 11 cores
+  CORE_LEVEL_TWELVE     EQU    15       ; < Level to 12 cores
+  CORE_LEVEL_THIRTEEN   EQU    16       ; < Level to 13 cores
+  CORE_LEVEL_FOURTEEN   EQU    17       ; < Level to 14 cores
+  CORE_LEVEL_FIFTEEN    EQU    18       ; < Level to 15 cores
+  CoreLevelModeMax      EQU    19       ; < Used for bounds checking
+CORE_LEVELING_TYPE  TEXTEQU  <DWORD>
+
+
+; ***********************************************************************
+; *
+; *  AGESA Basic Level interface structure definition and function prototypes
+; *
+; **********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdCreateStruct
+; *********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdReleaseStruct
+; *********************************************************************
+
+; *********************************************************************
+; * Interface call:  AmdInitReset
+; *********************************************************************
+ ; AmdInitReset param structure
+AMD_RESET_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < The cached memory region
+  HtConfig                      AMD_HT_RESET_INTERFACE {}       ; < The interface for Ht Recovery
+  FchInterface                  FCH_RESET_INTERFACE {}          ; Interface for FCH configuration
+AMD_RESET_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitEarly
+; *********************************************************************
+ ; InitEarly param structure
+
+ ; Provide defaults or customizations to each service performed in AmdInitEarly.
+
+AMD_EARLY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The standard header
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < Execution Map Interface
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  HtConfig                      AMD_HT_INTERFACE {}     ; < HyperTransport Interface
+  GnbConfig                     GNB_CONFIGURATION {}    ; < GNB configuration
+AMD_EARLY_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitPost
+; *********************************************************************
+ ; AmdInitPost param structure
+AMD_POST_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  MemConfig                     MEM_PARAMETER_STRUCT {}         ; < Memory post param
+AMD_POST_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitEnv
+; *********************************************************************
+ ; AmdInitEnv param structure
+AMD_ENV_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  GnbEnvConfiguration           GNB_ENV_CONFIGURATION {}        ; < platform operational characteristics.
+  FchInterface                  FCH_INTERFACE {}                ; FCH configuration
+AMD_ENV_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitMid
+; *********************************************************************
+ ; AmdInitMid param structure
+AMD_MID_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  FchInterface                  FCH_INTERFACE {}                ; FCH configuration
+AMD_MID_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitLate
+; *********************************************************************
+ ; AmdInitLate param structure
+AMD_LATE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}    ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < platform operational characteristics.
+     IvrsExclusionRangeList     POINTER ?       ; < IVMD exclusion range descriptor
+     DmiTable                   POINTER ?       ; < DMI Interface
+     AcpiPState                 POINTER ?       ; < Acpi Pstate SSDT Table
+     AcpiSrat                   POINTER ?       ; < SRAT Table
+     AcpiSlit                   POINTER ?       ; < SLIT Table
+     AcpiWheaMce                POINTER ?       ; < WHEA MCE Table
+     AcpiWheaCmc                POINTER ?       ; < WHEA CMC Table
+     AcpiAlib                   POINTER ?       ; < ALIB Table
+     AcpiIvrs                   POINTER ?       ; < IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+AMD_LATE_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdInitRecovery
+; *********************************************************************
+ ; CPU Recovery Parameters
+AMD_CPU_RECOVERY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard Header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < platform operational characteristics
+AMD_CPU_RECOVERY_PARAMS    ENDS
+
+ ; AmdInitRecovery param structure
+AMD_RECOVERY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  MemConfig                     MEM_PARAMETER_STRUCT {}         ; < Memory post param
+  CacheRegion                   EXECUTION_CACHE_REGION (3) DUP ({})     ; < The cached memory region. And the max cache region is 3
+  CpuRecoveryParams             AMD_CPU_RECOVERY_PARAMS {}      ; < Params for CPU related recovery init.
+AMD_RECOVERY_PARAMS    ENDS
+
+
+; *********************************************************************
+; * Interface call:  AmdInitResume
+; *********************************************************************
+ ; AmdInitResume param structure
+AMD_RESUME_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}      ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {} ; < Platform operational characteristics
+  S3DataBlock                   AMD_S3_PARAMS {}          ; < Save state data
+AMD_RESUME_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdS3LateRestore
+; *********************************************************************
+ ; AmdS3LateRestore param structure
+AMD_S3LATE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  S3DataBlock                   AMD_S3_PARAMS {}        ; < Save state data
+AMD_S3LATE_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface call:  AmdS3Save
+; *********************************************************************
+ ; AmdS3Save param structure
+AMD_S3SAVE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Standard header
+  PlatformConfig                PLATFORM_CONFIGURATION {}       ; < platform operational characteristics.
+  S3DataBlock                   AMD_S3_PARAMS {}        ; < Standard header
+  FchInterface                  FCH_INTERFACE {}        ; FCH configuration
+AMD_S3SAVE_PARAMS    ENDS
+
+ ; General Services API
+
+
+; *********************************************************************
+; * Interface service call:  AmdGetApicId
+; *********************************************************************
+ ; Request the APIC ID of a particular core.
+
+AMD_APIC_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  Socket                        UINT8 ?         ; < The Core's Socket.
+  Core                          UINT8 ?         ; < The Core id.
+     IsPresent                  BOOLEAN ?       ; < The Core is present, and  ApicAddress is valid.
+     ApicAddress                UINT8 ?         ; < The Core's APIC ID.
+AMD_APIC_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdGetPciAddress
+; *********************************************************************
+ ; Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+AMD_GET_PCI_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  Socket                        UINT8 ?         ; < The Processor's socket
+  Module                        UINT8 ?         ; < The Module in that Processor
+     IsPresent                  BOOLEAN ?       ; < The Core is present, and  PciAddress is valid.
+     PciAddress                 PCI_ADDR {}      ; < The Processor's PCI Config Space address (Function 0, Register 0)
+AMD_GET_PCI_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdIdentifyCore
+; *********************************************************************
+ ; Request the identity (Socket, Module, Core) of the current Processor Core
+
+AMD_IDENTIFY_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+     Socket                     UINT8 ?         ; < The current Core's Socket
+     Module                     UINT8 ?         ; < The current Core's Processor Module
+     Core                       UINT8 ?         ; < The current Core's core id.
+AMD_IDENTIFY_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdReadEventLog
+; *********************************************************************
+ ; An Event Log Entry.
+EVENT_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+     EventClass                 UINT32 ?        ; < The severity of this event, matches AGESA_STATUS.
+     EventInfo                  UINT32 ?        ; < The unique event identifier, zero means "no event".
+     DataParam1                 UINT32 ?        ; < Data specific to the Event.
+     DataParam2                 UINT32 ?        ; < Data specific to the Event.
+     DataParam3                 UINT32 ?        ; < Data specific to the Event.
+     DataParam4                 UINT32 ?        ; < Data specific to the Event.
+EVENT_PARAMS    ENDS
+
+; *********************************************************************
+; * Interface service call:  AmdIdentifyDimm
+; *********************************************************************
+ ; Request the identity of dimm from system address
+
+AMD_IDENTIFY_DIMM    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < Header for library and services.
+  MemoryAddress                 UINT64 ?        ; < System Address that needs to be translated to dimm identification.
+  SocketId                      UINT8 ?         ; < The socket on which the targeted address locates.
+  MemChannelId                  UINT8 ?         ; < The channel on which the targeted address locates.
+  DimmId                        UINT8 ?         ; < The dimm on which the targeted address locates.
+AMD_IDENTIFY_DIMM    ENDS
+
+ ; Data structure for the Mapping Item between Unified ID for IDS Setup Option
+ ; and the option value.
+
+IDS_NV_ITEM    STRUCT
+  IdsNvId                       UINT16 ?        ; < Unified ID for IDS Setup Option.
+  IdsNvValue                    UINT16 ?        ; < The value of IDS Setup Option.
+IDS_NV_ITEM    ENDS
+
+ ; Data Structure for IDS CallOut Function
+IDS_CALLOUT_STRUCT    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}     ; < The Standard Header for AGESA Service
+  IdsNvPtr                      POINTER ?       ; < Memory Pointer of IDS NV Table
+  Reserved                      UINT32 ?         ; < reserved
+IDS_CALLOUT_STRUCT    ENDS
+
+  AGESA_IDS_DFT_VAL                            EQU    0FFFFh; <  Default value of every uninitlized NV item, the action for it will be ignored
+  AGESA_IDS_NV_END                             EQU    0FFFFh; <  Flag specify end of option structure
+; WARNING: Don't change the comment below, it used as signature for script
+; AGESA IDS NV ID Definitions
+  AGESA_IDS_EXT_ID_START                            EQU    0000h; <                                                            specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE                                EQU    0001h; <                                                           Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE                        EQU    0002h; <                                                       Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE                           EQU    0003h; <                                          Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_BANK_INTERLEAVE                      EQU    0004h; <                                                              Enable or disable Bank Interleave
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE                   EQU    0005h; <                                                           Enable or disable Channel Interleave
+  AGESA_IDS_NV_NODE_INTERLEAVE                      EQU    0006h; <                                                              Enable or disable Node Interleave
+  AGESA_IDS_NV_MEMHOLE                              EQU    0007h; <                                                                 Enables or disable memory hole
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION                    EQU    0008h; <                                          Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB                           EQU    0009h; <                                                  Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB                         EQU    000Ah; <                                           Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB                             EQU    000Bh; <                                          Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB                             EQU    000Ch; <                                          Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_ICACHE_SCRUB                         EQU    000Dh; <                                            Set the rate of background scrubbing for the Icache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR                    EQU    000Eh; <                                   Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE                      EQU    000Fh; <                                                                            Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS                          EQU    0010h; <                                                     Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE                     EQU    0011h; <                                                                            Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32                  EQU    0012h; <                                                                   Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN                    EQU    0013h; <                                                       Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE               EQU    0014h; <                                                                 Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN                        EQU    0015h; <                                                                  Enable or disable DLLShutdown
+  AGESA_IDS_NV_ONLINE_SPARE                         EQU    0016h; <     Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+  AGESA_IDS_NV_HT_ASSIST                            EQU    0017h; <                                                                    Enable or Disable HT Assist
+  AGESA_IDS_NV_ATMMODE                              EQU    0018h; <                                                                     Enable or Disable ATM mode
+
+  AGESA_IDS_NV_HDTOUT                               EQU    0019h; <                                                               Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET                         EQU    001Ah; <                                                                                 HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT                           EQU    001Bh; <                                                                                   HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ                           EQU    001Ch; <                                                                              HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN                        EQU    001Dh; <                                                                               HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT                       EQU    001Eh; <                                                                              HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN                         EQU    001Fh; <                                                                 Enable or disable GNB HD Audio
+
+  AGESA_IDS_NV_CPB_EN                               EQU    0020h; <                                                                         Core Performance Boost
+
+  AGESA_IDS_NV_HTC_EN                               EQU    0021h; <                                                                                     HTC Enable
+  AGESA_IDS_NV_HTC_OVERRIDE                         EQU    0022h; <                                                                                   HTC Override
+  AGESA_IDS_NV_HTC_PSTATE_LIMIT                     EQU    0023h; <                                                                       HTC P-state limit select
+  AGESA_IDS_NV_HTC_TEMP_HYS                         EQU    0024h; <                                                                     HTC Temperature Hysteresis
+  AGESA_IDS_NV_HTC_ACT_TEMP                         EQU    0025h; <                                                                            HTC Activation Temp
+
+  AGESA_IDS_NV_POWER_POLICY                         EQU    0026h; <                                                                   Select Platform Power Policy
+  AGESA_IDS_EXT_ID_END                              EQU    0027h; <                                                              specify the end of external NV ID
+
+  IDS_EX_NV_ID  TEXTEQU  <DWORD>
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/amd.inc b/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
new file mode 100644
index 0000000..86e3a02
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/amd.inc
@@ -0,0 +1,462 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+;
+; ****************************************************************************
+; *
+; * Copyright (C) 2012 Advanced Micro Devices, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *     * Redistributions of source code must retain the above copyright
+; *       notice, this list of conditions and the following disclaimer.
+; *     * Redistributions in binary form must reproduce the above copyright
+; *       notice, this list of conditions and the following disclaimer in the
+; *       documentation and/or other materials provided with the distribution.
+; *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; *       its contributors may be used to endorse or promote products derived
+; *       from this software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *
+; **************************************************************************
+
+
+UINT64    TEXTEQU     <QWORD>
+UINT32    TEXTEQU     <DWORD>
+UINT16    TEXTEQU     <WORD>
+UINT8     TEXTEQU     <BYTE>
+CHAR8     TEXTEQU     <BYTE>
+BOOLEAN   TEXTEQU     <BYTE>
+POINTER   TEXTEQU     <DWORD>
+
+ ; AGESA Types and Definitions
+
+    AGESA_REVISION              EQU    "Arch2008"
+    AGESA_ID                    EQU    "AGESA"
+
+    LAST_ENTRY                  EQU    0FFFFFFFFh
+    IMAGE_SIGNATURE             EQU    'DMA$'
+    IOCF8                       EQU    0CF8h
+    IOCFC                       EQU    0CFCh
+
+ ; The return status for all AGESA public services.
+
+ ; Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+ ; will have log entries with more detail.
+
+  AGESA_SUCCESS               EQU    0        ; < The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED           EQU    1        ; < The dispatcher or create struct had an unimplemented function requested.
+                                              ; <  Not logged.
+  AGESA_BOUNDS_CHK            EQU    2        ; < A dynamic parameter was out of range and the service was not provided.
+                                              ; < Example, memory address not installed, heap buffer handle not found.
+                                              ; < Not Logged.
+ ; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT                 EQU    3        ; < An observed condition, but no loss of function.
+                                              ; <  See log.  Example, HT CRC.
+  AGESA_WARNING               EQU    4        ; < Possible or minor loss of function.  See Log.
+  AGESA_ERROR                 EQU    5        ; < Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL              EQU    6        ; < Continue boot only to notify user.  See Log.
+  AGESA_FATAL                 EQU    7        ; < Halt booting.  See Log.
+  AgesaStatusMax              EQU    8        ; < Not a status, use for limit checking.
+AGESA_STATUS        TEXTEQU    <DWORD>
+
+; For checking whether a status is at or above the mandatory log level.
+AGESA_STATUS_LOG_LEVEL         EQU   AGESA_ALERT
+
+    CALLOUT_ENTRY       TEXTEQU    <POINTER>
+    IMAGE_ENTRY         TEXTEQU    <POINTER>
+    MODULE_ENTRY        TEXTEQU    <POINTER>
+
+; This allocation type is used by the AmdCreateStruct entry point
+  PreMemHeap            EQU    0        ; < Create heap in cache.
+  PostMemDram           EQU    1        ; < Create heap in memory.
+  ByHost                EQU    2        ; < Create heap by Host.
+ALLOCATION_METHOD  TEXTEQU  <DWORD>
+
+ ; These width descriptors are used by the library function, and others, to specify the data size
+  AccessWidth8          EQU    1        ; < Access width is 8 bits.
+  AccessWidth16         EQU    2        ; < Access width is 16 bits.
+  AccessWidth32         EQU    3        ; < Access width is 32 bits.
+  AccessWidth64         EQU    4        ; < Access width is 64 bits.
+
+  AccessS3SaveWidth8    EQU    81h      ; < Save 8 bits data.
+  AccessS3SaveWidth16   EQU    130      ; < Save 16 bits data.
+  AccessS3SaveWidth32   EQU    131      ; < Save 32 bits data.
+  AccessS3SaveWidth64   EQU    132      ; < Save 64 bits data.
+ACCESS_WIDTH  TEXTEQU  <DWORD>
+
+ ; AGESA struct name
+
+   ; AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY     EQU    00020000h
+  AMD_CREATE_STRUCT     EQU    00020001h
+  AMD_INIT_EARLY        EQU    00020002h
+  AMD_INIT_ENV          EQU    00020003h
+  AMD_INIT_LATE         EQU    00020004h
+  AMD_INIT_MID          EQU    00020005h
+  AMD_INIT_POST         EQU    00020006h
+  AMD_INIT_RESET        EQU    00020007h
+  AMD_INIT_RESUME       EQU    00020008h
+  AMD_RELEASE_STRUCT    EQU    00020009h
+  AMD_S3LATE_RESTORE    EQU    0002000Ah
+  AMD_S3_SAVE           EQU    0002000Bh
+  AMD_GET_APIC_ID       EQU    0002000Ch
+  AMD_GET_PCI_ADDRESS   EQU    0002000Dh
+  AMD_IDENTIFY_CORE     EQU    0002000Eh
+  AMD_READ_EVENT_LOG    EQU    0002000Fh
+  AMD_GET_EXECACHE_SIZE EQU    00020010h
+  AMD_LATE_RUN_AP_TASK  EQU    00020011h
+  AMD_IDENTIFY_DIMMS    EQU    00020012h
+AGESA_STRUCT_NAME  TEXTEQU  <DWORD>
+
+
+  ; ResetType constant values
+    WARM_RESET_WHENEVER         EQU    1
+    COLD_RESET_WHENEVER         EQU    2
+    WARM_RESET_IMMEDIATELY      EQU    3
+    COLD_RESET_IMMEDIATELY      EQU    4
+
+
+ ; AGESA Structures
+
+ ; The standard header for all AGESA services.
+AMD_CONFIG_PARAMS    STRUCT
+  ImageBasePtr                  UINT32 ?        ; < The AGESA Image base address.
+  Func                          UINT32 ?        ; < The service desired, @sa dispatch.h.
+  AltImageBasePtr               UINT32 ?        ; < Alternate Image location
+  CalloutPtr                    CALLOUT_ENTRY ?         ; < For Callout from AGESA
+  HeapStatus                    UINT8 ?         ; < For heap status from boot time slide.
+  HeapBasePtr                   UINT64 ?        ; < Location of the heap
+  Reserved                      UINT8 (7) DUP (?)      ; < This space is reserved for future use.
+AMD_CONFIG_PARAMS    ENDS
+
+
+ ; Create Struct Interface.
+AMD_INTERFACE_PARAMS    STRUCT
+  StdHeader                     AMD_CONFIG_PARAMS {}    ; < Config header
+  AgesaFunctionName             AGESA_STRUCT_NAME ?     ; < The service to init, @sa dispatch.h
+  AllocationMethod              ALLOCATION_METHOD ?     ; < How to handle buffer allocation
+  NewStructSize                 UINT32 ?        ; < The size of the allocated data, in for ByHost, else out only.
+  NewStructPtr                  POINTER ?       ; < The struct for the service.
+                                                   ; < The struct to init for ByHost allocation,
+                                                   ; < the initialized struct on return.
+AMD_INTERFACE_PARAMS    ENDS
+
+    FUNC_0                      EQU    0        ; bit-placed for PCI address creation
+    FUNC_1                      EQU    1
+    FUNC_2                      EQU    2
+    FUNC_3                      EQU    3
+    FUNC_4                      EQU    4
+    FUNC_5                      EQU    5
+    FUNC_6                      EQU    6
+    FUNC_7                      EQU    7
+
+ ; AGESA Binary module header structure
+AMD_IMAGE_HEADER    STRUCT
+  Signature                     UINT32 ?        ; < Binary Signature
+  CreatorID                     CHAR8 (8) DUP (?)       ; < 8 characters ID
+  Version                       CHAR8 (12) DUP (?)      ; < 12 characters version
+  ModuleInfoOffset              UINT32 ?        ; < Offset of module
+  EntryPointAddress             UINT32 ?        ; < Entry address
+  ImageBase                     UINT32 ?        ; < Image base
+  RelocTableOffset              UINT32 ?        ; < Relocate Table offset
+  ImageSize                     UINT32 ?        ; < Size
+  Checksum                      UINT16 ?        ; < Checksum
+  ImageType                     UINT8 ?         ; < Type
+  V_Reserved                    UINT8 ?         ; < Reserved
+AMD_IMAGE_HEADER    ENDS
+ ; AGESA Binary module header structure
+AMD_MODULE_HEADER    STRUCT
+  ModuleHeaderSignature         UINT32 ?        ; < Module signature
+  ModuleIdentifier              CHAR8 (8) DUP (?)       ; < 8 characters ID
+  ModuleVersion                 CHAR8 (12) DUP (?)      ; < 12 characters version
+  ModuleDispatcher              POINTER ?       ; < A pointer point to dispatcher
+  NextBlock                     POINTER ?       ; < Next module header link
+AMD_MODULE_HEADER    ENDS
+
+; AMD_CODE_HEADER Signatures.
+AGESA_CODE_SIGNATURE    TEXTEQU  <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
+CIMXNB_CODE_SIGNATURE   TEXTEQU  <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
+CIMXSB_CODE_SIGNATURE   TEXTEQU  <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
+
+; AGESA_CODE_SIGNATURE
+AMD_CODE_HEADER    STRUCT
+  Signature             CHAR8 (8) DUP (?)           ; < code header Signature
+  ComponentName         CHAR8 (8) DUP (?)           ; < 8 character name of the code module
+  Version               CHAR8 (12) DUP (?)          ; < 12 character version string
+  TerminatorNull        CHAR8 ?                     ; < null terminated string
+  VerReserved           CHAR8 (7) DUP (?)           ; < reserved space
+AMD_CODE_HEADER    ENDS
+
+ ; Extended PCI address format
+EXT_PCI_ADDR    STRUCT
+  Register                      UINT32 ?
+;   IN OUT  UINT32      Register:12;                           ; < Register offset
+;   IN OUT  UINT32      Function:3;                     ; < Function number
+;   IN OUT  UINT32      Device:5;                       ; < Device number
+;   IN OUT  UINT32      Bus:8;                          ; < Bus number
+;   IN OUT  UINT32      Segment:4;                      ; < Segment
+EXT_PCI_ADDR    ENDS
+
+ ; Union type for PCI address
+PCI_ADDR    UNION
+  AddressValue                  UINT32 ?        ; < Formal address
+  Address                       EXT_PCI_ADDR {}         ; < Extended address
+PCI_ADDR    ENDS
+
+   ; SBDFO - Segment Bus Device Function Offset
+   ; 31:28   Segment (4-bits)
+   ; 27:20   Bus     (8-bits)
+   ; 19:15   Device  (5-bits)
+   ; 14:12   Function(3-bits)
+   ; 11:00   Offset  (12-bits)
+
+
+
+    ILLEGAL_SBDFO               EQU    0FFFFFFFFh
+
+ ; CPUID data received registers format
+CPUID_DATA    STRUCT
+  EAX_Reg                       UINT32 ?        ; < CPUID instruction result in EAX
+  EBX_Reg                       UINT32 ?        ; < CPUID instruction result in EBX
+  ECX_Reg                       UINT32 ?        ; < CPUID instruction result in ECX
+  EDX_Reg                       UINT32 ?        ; < CPUID instruction result in EDX
+CPUID_DATA    ENDS
+
+ ; HT frequency for external callbacks
+;typedef enum {
+  HT_FREQUENCY_200M     EQU    0        ; < HT speed 200 for external callbacks
+  HT_FREQUENCY_400M     EQU    2        ; < HT speed 400 for external callbacks
+  HT_FREQUENCY_600M     EQU    4        ; < HT speed 600 for external callbacks
+  HT_FREQUENCY_800M     EQU    5        ; < HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M    EQU    6        ; < HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M    EQU    7        ; < HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M    EQU    8        ; < HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M    EQU    9        ; < HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M    EQU    10       ; < HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M    EQU    11       ; < HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M    EQU    12       ; < HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M    EQU    13       ; < HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M    EQU    14       ; < HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M    EQU    17       ; < HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M    EQU    18       ; < HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M    EQU    19       ; < HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX      EQU    20       ; < Limit Check.
+HT_FREQUENCIES  TEXTEQU  <DWORD> ;} HT_FREQUENCIES;
+
+HT3_FREQUENCY_MIN     EQU    HT_FREQUENCY_1200M
+
+IFNDEF   BIT0
+    BIT0                        EQU    0000000000000001h
+ENDIF
+IFNDEF   BIT1
+    BIT1                        EQU    0000000000000002h
+ENDIF
+IFNDEF   BIT2
+    BIT2                        EQU    0000000000000004h
+ENDIF
+IFNDEF   BIT3
+    BIT3                        EQU    0000000000000008h
+ENDIF
+IFNDEF   BIT4
+    BIT4                        EQU    0000000000000010h
+ENDIF
+IFNDEF   BIT5
+    BIT5                        EQU    0000000000000020h
+ENDIF
+IFNDEF   BIT6
+    BIT6                        EQU    0000000000000040h
+ENDIF
+IFNDEF   BIT7
+    BIT7                        EQU    0000000000000080h
+ENDIF
+IFNDEF   BIT8
+    BIT8                        EQU    0000000000000100h
+ENDIF
+IFNDEF   BIT9
+    BIT9                        EQU    0000000000000200h
+ENDIF
+IFNDEF   BIT10
+    BIT10                       EQU    0000000000000400h
+ENDIF
+IFNDEF   BIT11
+    BIT11                       EQU    0000000000000800h
+ENDIF
+IFNDEF   BIT12
+    BIT12                       EQU    0000000000001000h
+ENDIF
+IFNDEF   BIT13
+    BIT13                       EQU    0000000000002000h
+ENDIF
+IFNDEF   BIT14
+    BIT14                       EQU    0000000000004000h
+ENDIF
+IFNDEF   BIT15
+    BIT15                       EQU    0000000000008000h
+ENDIF
+IFNDEF   BIT16
+    BIT16                       EQU    0000000000010000h
+ENDIF
+IFNDEF   BIT17
+    BIT17                       EQU    0000000000020000h
+ENDIF
+IFNDEF   BIT18
+    BIT18                       EQU    0000000000040000h
+ENDIF
+IFNDEF   BIT19
+    BIT19                       EQU    0000000000080000h
+ENDIF
+IFNDEF   BIT20
+    BIT20                       EQU    0000000000100000h
+ENDIF
+IFNDEF   BIT21
+    BIT21                       EQU    0000000000200000h
+ENDIF
+IFNDEF   BIT22
+    BIT22                       EQU    0000000000400000h
+ENDIF
+IFNDEF   BIT23
+    BIT23                       EQU    0000000000800000h
+ENDIF
+IFNDEF   BIT24
+    BIT24                       EQU    0000000001000000h
+ENDIF
+IFNDEF   BIT25
+    BIT25                       EQU    0000000002000000h
+ENDIF
+IFNDEF   BIT26
+    BIT26                       EQU    0000000004000000h
+ENDIF
+IFNDEF   BIT27
+    BIT27                       EQU    0000000008000000h
+ENDIF
+IFNDEF   BIT28
+    BIT28                       EQU    0000000010000000h
+ENDIF
+IFNDEF   BIT29
+    BIT29                       EQU    0000000020000000h
+ENDIF
+IFNDEF   BIT30
+    BIT30                       EQU    0000000040000000h
+ENDIF
+IFNDEF   BIT31
+    BIT31                       EQU    0000000080000000h
+ENDIF
+IFNDEF   BIT32
+    BIT32                       EQU    0000000100000000h
+ENDIF
+IFNDEF   BIT33
+    BIT33                       EQU    0000000200000000h
+ENDIF
+IFNDEF   BIT34
+    BIT34                       EQU    0000000400000000h
+ENDIF
+IFNDEF   BIT35
+    BIT35                       EQU    0000000800000000h
+ENDIF
+IFNDEF   BIT36
+    BIT36                       EQU    0000001000000000h
+ENDIF
+IFNDEF   BIT37
+    BIT37                       EQU    0000002000000000h
+ENDIF
+IFNDEF   BIT38
+    BIT38                       EQU    0000004000000000h
+ENDIF
+IFNDEF   BIT39
+    BIT39                       EQU    0000008000000000h
+ENDIF
+IFNDEF   BIT40
+    BIT40                       EQU    0000010000000000h
+ENDIF
+IFNDEF   BIT41
+    BIT41                       EQU    0000020000000000h
+ENDIF
+IFNDEF   BIT42
+    BIT42                       EQU    0000040000000000h
+ENDIF
+IFNDEF   BIT43
+    BIT43                       EQU    0000080000000000h
+ENDIF
+IFNDEF   BIT44
+    BIT44                       EQU    0000100000000000h
+ENDIF
+IFNDEF   BIT45
+    BIT45                       EQU    0000200000000000h
+ENDIF
+IFNDEF   BIT46
+    BIT46                       EQU    0000400000000000h
+ENDIF
+IFNDEF   BIT47
+    BIT47                       EQU    0000800000000000h
+ENDIF
+IFNDEF   BIT48
+    BIT48                       EQU    0001000000000000h
+ENDIF
+IFNDEF   BIT49
+    BIT49                       EQU    0002000000000000h
+ENDIF
+IFNDEF   BIT50
+    BIT50                       EQU    0004000000000000h
+ENDIF
+IFNDEF   BIT51
+    BIT51                       EQU    0008000000000000h
+ENDIF
+IFNDEF   BIT52
+    BIT52                       EQU    0010000000000000h
+ENDIF
+IFNDEF   BIT53
+    BIT53                       EQU    0020000000000000h
+ENDIF
+IFNDEF   BIT54
+    BIT54                       EQU    0040000000000000h
+ENDIF
+IFNDEF   BIT55
+    BIT55                       EQU    0080000000000000h
+ENDIF
+IFNDEF   BIT56
+    BIT56                       EQU    0100000000000000h
+ENDIF
+IFNDEF   BIT57
+    BIT57                       EQU    0200000000000000h
+ENDIF
+IFNDEF   BIT58
+    BIT58                       EQU    0400000000000000h
+ENDIF
+IFNDEF   BIT59
+    BIT59                       EQU    0800000000000000h
+ENDIF
+IFNDEF   BIT60
+    BIT60                       EQU    1000000000000000h
+ENDIF
+IFNDEF   BIT61
+    BIT61                       EQU    2000000000000000h
+ENDIF
+IFNDEF   BIT62
+    BIT62                       EQU    4000000000000000h
+ENDIF
+IFNDEF   BIT63
+    BIT63                       EQU    8000000000000000h
+ENDIF
+
diff --git a/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc b/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc
new file mode 100644
index 0000000..e6b9538
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc
@@ -0,0 +1,577 @@
+; ****************************************************************************
+; *
+; * @file
+; *
+; * Agesa structures and definitions
+; *
+; * Contains AMD AGESA core interface
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Include
+; * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+;
+; ****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+PARAM1          textequ <[bp+8]>
+PARAM2          textequ <[bp+12]>
+PARAM3          textequ <[bp+16]>
+RETAddress      textequ <[bp+4]>
+
+AMD_PRIVATE_PARAMS STRUCT
+    Gate16_CS   DW ?                ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
+    Gate16_SS   DW ?                ; RM stack segment
+    Router_Seg  DW ?                ; Segment of oem router
+    Router_Off  DW ?                ; Offset of oem router
+AMD_PRIVATE_PARAMS ENDS
+
+; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
+IFNDEF  AGESA_SELECTOR_GDT
+        AGESA_SELECTOR_GDT         EQU 00h
+ENDIF
+IFNDEF  AGESA_SELECTOR_CODE16
+        AGESA_SELECTOR_CODE16      EQU 08h
+ENDIF
+IFNDEF  AGESA_SELECTOR_DATA16
+        AGESA_SELECTOR_DATA16      EQU 10h
+ENDIF
+IFNDEF  AGESA_SELECTOR_CODE32
+        AGESA_SELECTOR_CODE32      EQU 18h
+ENDIF
+IFNDEF  AGESA_SELECTOR_DATA32
+        AGESA_SELECTOR_DATA32      EQU 20h
+ENDIF
+
+
+AMD_BRIDGE_32_GDT MACRO  GDT_Name:REQ
+
+        GDT_Name LABEL BYTE
+            DD 000000000h, 000000000h       ; NULL descriptor
+            DD 00000ffffh, 000009b00h       ; 16-bit code, fixed up
+            DD 00000ffffh, 000009300h       ; 16-bit data, fixed up
+            DD 00000ffffh, 000CF9B00h       ; 32-bit protected mode code
+            DD 00000ffffh, 000CF9300h       ; 32-bit protected mode data
+        GDT_Length EQU ($-GDT_Name)
+
+ENDM
+
+;+-------------------------------------------------------------------------
+;
+;       AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
+;
+;   Processing:
+;       The following steps are taken:
+;       1) Enter 32bit Protected Mode (PM32)
+;       2) Run AGESA code
+;       3) Restore Real Mode (RM)
+;
+; Entry:
+;       [big real mode] : ds, es set to base 0 limit 4G segment
+;       EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
+;       ESI - configuration block pointer
+;
+; Exit:
+;       EAX - return value
+;       ESI - configuration block pointer
+;       ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
+;
+; Modified:
+;      None
+;
+
+AMD_BRIDGE_32 MACRO GDT_Name
+
+        local   copyGDT
+        local   flushTo16PM
+        local   agesaReturnAddress
+        local   leave32bitPM
+        local   flush2RM
+
+        push    gs
+        push    fs
+        push    ebx
+        push    ecx
+        push    edi
+        mov     eax, esp
+        push    eax
+        movzx   esp, sp
+;
+; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
+;
+        pushf
+        cli                         ; Disable interrupts during AGESA
+        cld                         ; Need known direction flag during AGESA
+
+;
+; Save the FAR PTR input parameter
+;
+        mov     gs, dx                  ; Offset
+        shr     edx, 16
+        mov     fs, dx                  ; Segment
+;
+; Determine where our binary file is and get entry point
+;
+        mov     edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
+        add     edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
+;
+; Figure out the return address we will use after calling AGESA
+; and store it in ebx until we have our stack set up properly
+;
+        mov     ebx, cs
+        shl     ebx, 4
+        add     ebx, OFFSET agesaReturnAddress
+;
+; Save our current RM stack AND entry EBP
+;
+        push    ebp
+;       push    esp
+        push    ss
+
+;
+; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
+;
+; Copy the GDT onto the stack for modification
+;
+        mov     cx, GDT_Length
+        sub     sp, cx
+        mov     bp, sp
+        lea     di, GDT_Name
+copyGDT:
+        mov     al, cs:[di]
+        mov     [bp], al
+        inc     di
+        inc     bp
+        loop    copyGDT
+;
+; Patch 16-bit code and data descriptors on stack.  We will
+; fix up CS and SS for PM16 during the callout if applicable.
+;
+        mov     bp, sp
+
+        mov     eax, cs
+        shl     eax, 4
+        mov     [bp+AGESA_SELECTOR_CODE16+2], ax
+        shr     eax, 16
+        mov     [bp+AGESA_SELECTOR_CODE16+4], al
+
+        mov     eax, ss
+        shl     eax, 4
+        mov     [bp+AGESA_SELECTOR_DATA16+2], ax
+        shr     eax, 16
+        mov     [bp+AGESA_SELECTOR_DATA16+4], al
+;
+; Need to place Length and Address on GDT
+;
+        mov     eax, ss
+        shl     eax, 4
+        add     eax, esp
+        push    eax
+        push    WORD PTR (GDT_Length-1)
+;
+; Load the GDT
+;
+        mov     bp, sp
+        lgdt    FWORD PTR [bp]
+;
+; TABLE 1
+;
+; Place PRIVATE DATA on stack DIRECTLY following GDT
+; During this routine, stack data is critical.  If
+; order is changed or additional added, bad things
+; will happen!
+;
+; HIGHEST PHYSICAL ADDRESS
+;
+; | ...                  |
+; ------------------------
+; | old RM SP            |
+; | old RM SS            |
+; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
+; | GDT_DATA32           |
+; | ...                  |
+; | GDT_NULL             |
+; | GDT Addr, Length     |
+; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
+; | Priv.Gate16_SS       |
+; | Priv.Gate16_CS       |
+; ------------------------ sp
+; ------ THEN PUSH -------
+; | Return to 16-bit CS  |
+; | Return to 16-bit Off |
+; | ...                  |
+;
+; LOWEST  PHYSICAL ADDRESS
+;
+        mov     edi, esp
+        sub     edi, SIZEOF AMD_PRIVATE_PARAMS
+        mov     ax, cs
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
+        mov     ax, ss
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
+        mov     (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
+
+        mov     esp, edi
+;
+; Save an address for returning to 16 bit real mode on stack,
+; we'll use it in a far ret after turning off CR0.PE so that
+; we can take our address off and force a far jump.  Be sure
+; no unexpected data is on the stack after this!
+;
+        mov     ax, cs
+        push    cs
+        lea     ax, flush2RM
+        push    ax
+;
+; Convert ss:esp to "flat"
+;
+
+        mov     ax, sp
+        push    ax
+        mov     eax, ss
+        shl     eax, 4
+        add     eax, esp
+        mov     esp, eax                ; Load the zero based ESP
+
+;
+; Set CR0.PE
+;
+        mov     eax, CR0                ; Get CPU control word 0
+        or      al, 01                  ; Enable CPU protected mode
+        mov     CR0, eax                ; Write back to CPU control word 0
+        jmp     flushTo16PM
+
+flushTo16PM:
+;
+; 16-bit protected mode
+;
+        mov     ax, AGESA_SELECTOR_DATA32
+        mov     ds, ax
+        mov     es, ax
+        mov     fs, ax
+        mov     gs, ax
+        mov     ss, ax
+;
+; Push our parameters RIGHT TO LEFT, and then return address
+;
+        push    esi                     ; AGESA configuration block pointer (data)
+        push    ebx                     ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
+        pushd   AGESA_SELECTOR_CODE32   ; AGESA entry selector (32PM flat)
+        push    edx                     ; AGESA entry point (32PM flat)
+
+        DB      066h
+        retf                            ; <><><> Enter AGESA 32-bit code!!! <><><>
+
+agesaReturnAddress:
+;
+; Returns from the Agesa 32-bit code still PM32
+;
+        DB      0EAh
+        DD      OFFSET leave32bitPM
+        DW      AGESA_SELECTOR_CODE16
+
+leave32bitPM:
+;
+; Now in 16-bit PM
+;
+        add     esp, 4                  ; +4 to remove our config block pointer
+;
+; Eax reserve AGESA_STATUS return code, save it
+;
+        mov     ebx, eax
+;
+; Turn off CR0.PE, restore 64K stack limit
+;
+        pop     ax
+        mov     sp, ax
+        mov     ax, AGESA_SELECTOR_DATA16
+        mov     ss, ax
+
+        mov     eax, CR0
+        and     al, NOT 1               ; Disable protected mode
+        mov     CR0, eax                ; Write back CR0.PE
+;
+; Jump far to enter RM, we saved this address on the stack
+; already.  Hopefully stack is balanced through AGESA
+; nor were any params added by pushing them on the stack and
+; not removing them between BEGIN-END comments.
+;
+        retf
+
+flush2RM:
+;
+; Set segments registers for big real mode before returning
+;
+        xor     ax, ax
+        mov     ds, ax
+        mov     es, ax
+        mov     fs, ax
+        mov     gs, ax
+;
+; Discard GDT, +6 for GDT pointer/size, privates
+;
+        add     esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
+;
+; Restore real mode stack and entry EBP
+;
+        pop     cx
+;       mov     esp, [esp]
+        mov     ss, cx
+        pop     ebp
+;
+; Restore AGESA_STATUS return code to eax
+;
+        mov     eax, ebx
+;
+; END --- STACK MUST BE BALANCED TO THIS POINT --- END
+;
+
+        popf
+        pop     ebx
+        mov     esp, ebx
+        pop     edi
+        pop     ecx
+        pop     ebx
+        pop     fs
+        pop     gs
+                            ; EXIT AMD_BRIDGE_32
+ENDM
+;+-------------------------------------------------------------------------
+;
+; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
+;
+;   Processing:
+;       The following steps are taken:
+;       1) Enter PM16
+;       2) Setup stack, get private params
+;       3) Enter RM
+;       4) Get 3 params
+;       5) Call oemCallout OR oem router
+;       6) Enter PM32
+;       7) Return to Agesa PH
+;
+; Entry:
+;       [32-bit protected mode]
+;       [esp+8] Func
+;       [esp+12] Data
+;       [esp+16] Configuration Block
+;       [esp+4] return address to Agesa
+;
+; Exit:
+;       [32-bit protected mode]
+;
+; Modified:
+;     None
+;
+AMD_CALLOUT_16 MACRO  LocalOemCalloutRouter
+;
+; Note that we are still PM32, so MASM may work strangely
+;
+
+        push    bp                     ; Save our original SP to access params
+        mov     bp, sp
+        push    bx
+        push    si
+        push    di
+        push    cx
+        push    dx
+        push    di
+
+        DB      066h, 0EAh
+        DW      OFFSET PM16Entry
+        DW      AGESA_SELECTOR_CODE16
+
+PM16Entry:
+;
+; PM16 CS, but still PM32 SS, as we need to access our private params
+; before we enter RM.
+;
+; Note: we are working below the stack temporarily, and and it will
+; not affect our ability to get entry params
+;
+        xor     ecx, ecx
+        xor     edx, edx
+;
+; SGDT will give us the original location of the GDT on our CAS stack.
+; We need this value because our private parameters are located just
+; below the GDT.
+;
+        mov     edi, esp
+        sub     edi, GDT_Length + 6
+        sgdt    FWORD PTR [edi]        ; [edi] = word size, dword address
+        mov     edi, DWORD PTR [edi+2]  ; Get the PM32 address only
+        sub     edi, SIZEOF AMD_PRIVATE_PARAMS + 6
+;
+; cx = code segment of this code in RM
+; dx = stack segment of CAS in RM
+; fs = code segment of oem router (save for later)
+; gs = offset of oem router (save for later)
+; fs and gs are loaded after switch to real mode because we can't
+; use them as scratch pad registers in protected mode
+;
+        mov     cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
+        mov     dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
+
+        mov     eax, edi             ; Save edi in eax for after RM switch
+        mov     edi, esp             ; Save our current ESP for RM
+
+        movzx   ebx, dx
+        shl     ebx, 4
+        sub     esp, ebx
+
+;
+; We had been accessing the stack in PM32, we will now change to PM16 so we
+; will make the stack segment 64KB limit so SP needs to be fixed made PM16
+; compatible.
+;
+        mov     bx, AGESA_SELECTOR_DATA16
+        mov     ss, bx
+
+;
+; Save the RM segment and RM offset of the jump we will need to make in
+; order to enter RM so that code in this segment is relocatable.
+;
+; BEGIN --- Don't unbalance the stack --- BEGIN
+;
+        push    cx
+        pushw   OFFSET RMEntry
+
+        mov     ebx, CR0
+        and     bl, NOT 1
+        mov     CR0, ebx                ; CR0.PE cleared
+;
+; Far jump to clear segment descriptor cache and enter RM
+;
+        retf
+
+RMEntry:
+;
+; We are in RM, setup RM stack
+;
+        movzx   ebx, dx               ; Get RM SS in ebx
+        shl     ebx, 4                  ; Get our stack top on entry in EBP to
+        sub     ebp, ebx                ; access our entry parameters
+        sub     eax, ebx                ; save copy of parameters address
+        mov     ss, dx                  ; Set stack segment
+;
+; We are going to figure out the address to use when we return
+; and have to go back into PM32 while we have access to it
+;
+        movzx   ebx, cx               ; Get original CS in ebx
+        shl     ebx, 4
+        add     ebx, OFFSET PM32Entry
+;
+; Now we put our data, func, block params into calling convention
+; for our hook
+;
+; ECX = Func
+; EDX = Data
+; ESI = config pointer
+;
+        mov     ecx, PARAM1             ; Func
+        mov     edx, PARAM2             ; Data
+        mov     esi, PARAM3             ; pointer
+
+        push    ebx                    ; Save PM32 mode switch address
+        push    edi                    ; Save PM32 stack pointer
+        pushf
+;
+; Get Router Function Address
+;
+        mov     edi, eax
+        mov     ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
+        mov     fs, ax
+        mov     ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
+        mov     gs, ax
+
+        mov     eax, AGESA_UNSUPPORTED  ; Default return value
+;
+; If AMD_BRIDGE_32 EDX == 0 call oemCallout
+; otherwise call FAR PTR EDX
+;
+; Critical:
+;   sp+2 - EDI aka PM32 stack address
+;   sp+4 - address of PM32Entry in PM32
+;
+        mov     bx, fs
+        shl     ebx, 16
+        mov     bx, gs
+
+        .if (ebx == 0)
+            call        LocalOemCalloutRouter
+        .else
+;
+; Make far call to Router function
+;
+        push    cs
+        push    offset CalloutReturn
+        push    ebx
+        retf
+CalloutReturn:
+    .endif
+;
+; Restore PM32 esp from RM stack
+;
+        popf
+        pop     edi                     ; Our PM32 stack pointer
+        pop     edx                     ; Our PM32 mode switch address
+
+        mov     ebx, CR0
+        or      bl, 1                   ; CR0.PE set
+        mov     CR0, ebx
+
+        mov     ebx, AGESA_SELECTOR_DATA32
+        pushd   AGESA_SELECTOR_CODE32 ; PM32 selector
+        push    edx                    ; PM32 entry point
+
+        DB      066h
+        retf                        ; Far jump to enter PM32
+
+PM32Entry:
+;
+; END --- Don't unbalance the stack --- END
+; We are now PM32, so remember MASM is assembling in 16-bit again
+;
+        mov     ss, bx
+        mov     ds, bx
+        mov     es, bx
+        mov     fs, bx
+        mov     gs, bx
+
+        mov     sp, di
+        pop     di
+        pop     dx
+        pop     cx
+        pop     di
+        pop     si
+        pop     bx
+        pop     bp
+                            ; EXIT AMD_CALLOUT_16
+ENDM
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm
new file mode 100644
index 0000000..5bebc1a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm
@@ -0,0 +1,671 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 17071 $   @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+.586p
+.xmm
+.model  flat
+ASSUME FS:NOTHING
+.code
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO byte
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+
+public  WriteIo8
+WriteIo8        PROC NEAR C USES DX AX Address:WORD, Data:Byte
+        mov     dx, Address
+        mov     al, Data
+        out     dx, al
+        ret
+WriteIo8        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO word
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+public WriteIo16
+WriteIo16       PROC NEAR C USES DX AX Address:WORD, Data:WORD
+        mov     dx, Address
+        mov     ax, Data
+        out     dx, ax
+        ret
+WriteIo16       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO dword
+; *
+; *  @param[in]   Address IO port address
+; *  @param[in]   Data    IO port Value
+; */
+
+public WriteIo32
+WriteIo32       PROC NEAR C USES DX EAX Address:WORD, Data:DWORD
+        mov     dx, Address
+        mov     eax, Data
+        out     dx, eax
+        ret
+WriteIo32       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO byte
+; *
+; *  @param[in] - IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo8
+ReadIo8 PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      al, dx
+        ret
+ReadIo8 ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO word
+; *
+; *  @param[in]   Address IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo16
+ReadIo16        PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      ax, dx
+        ret
+ReadIo16        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO dword
+; *
+; *  @param[in]   Address  IO port address
+; *  @retval      IO port Value
+; */
+public ReadIo32
+ReadIo32        PROC NEAR C USES DX Address:WORD
+        mov     dx, Address
+        in      eax, dx
+        ret
+ReadIo32        ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read MSR
+; *
+; *  @param[in]  Address  MSR Address
+; *  @param[in]  Data     Pointer to data
+; *  @param[in]  ConfigPtr (Optional)
+; */
+public LibAmdMsrRead
+LibAmdMsrRead  PROC NEAR C USES ECX ESI EDX Address:DWORD, Value:PTR, ConfigPtr:PTR
+        mov     esi, ConfigPtr        ;Dummy read to avoid compilation warning
+        mov     ecx, Address
+        rdmsr
+        mov     esi, Value
+        mov     [esi],   eax
+        mov     [esi+4], edx
+        ret
+LibAmdMsrRead  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write MSR
+; *
+; *  @param[in]  Address    MSR Address
+; *  @param[in]  Data       Pointer to data
+; *  @param[in]  ConfigPtr  (Optional)
+; */
+public LibAmdMsrWrite
+LibAmdMsrWrite                PROC NEAR C USES ECX ESI EDX Address:DWORD, Data:PTR, ConfigPtr:PTR
+        mov     esi, ConfigPtr         ;Dummy read to avoid compilation warning
+        mov     ecx, Address
+        mov     esi, Data
+        mov     eax, [esi]
+        mov     edx, [esi+4]
+        wrmsr
+        ret
+LibAmdMsrWrite                ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read CPUID
+; *
+; *  @param[in]  Func   CPUID function
+; *  @param[in]  DATA   Pointer to CPUID_DATA to save cpuid data
+; *  @param[in]  ConfigPtr (Optional)
+; */
+public LibAmdCpuidRead
+LibAmdCpuidRead       PROC NEAR C  Func:DWORD, DATA:PTR, ConfigPtr:PTR
+        pushad
+        mov     esi, ConfigPtr           ;Dummy read to avoid compilation warning
+        mov     eax, Func
+        cpuid
+        mov     esi, DATA
+        mov     [esi],   eax
+        mov     [esi+4], ebx
+        mov     [esi+8], ecx
+        mov     [esi+12],edx
+        popad
+        ret
+LibAmdCpuidRead              ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read TSC
+; *
+; *
+; *
+; */
+
+public ReadTSC
+ReadTSC  PROC    NEAR C
+        rdtsc
+        ret
+ReadTSC  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Set FS_BASE
+; *
+; *
+; *
+; * @param[in]  esi - Low Dword of physical address
+; * @param[in]  edi - High Dword of physical address
+; */
+SetFsBase  PROC NEAR PUBLIC USES EAX EBX ECX EDX EDI
+
+        mov     eax, ecx
+        mov     ecx, 0C0010015h ; HWCR
+        rdmsr
+        mov     ebx, eax
+        bts     eax, 17         ; HWCR.Wrap32Dis
+        wrmsr
+        xchg    edx, edi
+        mov     eax, esi
+        mov     esi, ebx
+
+        mov     ecx, 0C0000100h ; FS_BASE
+        wrmsr
+        ret
+
+SetFsBase  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Restore MSR0C001_0015
+; *
+; * @param[in]  esi - Low Dword
+; * @param[in]  edi - High Dword
+; */
+RestoreHwcr PROC NEAR PUBLIC USES EAX ECX EDX
+
+        mov     ecx, 0C0010015h
+        mov     eax, esi
+        mov     edx, edi
+        wrmsr
+        ret
+
+RestoreHwcr ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO byte
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory byte at given address
+; */
+Read64Mem8  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     al, fs:[ebx]
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     al, ds:[esi]
+Done:
+        ret
+
+Read64Mem8  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO word
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory word at given address
+; */
+Read64Mem16  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     ax, fs:[ebx]
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     ax, ds:[esi]
+Done:
+
+        ret
+
+Read64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO dword
+; *
+; * @param[in]  Address - Memory Address
+; * @retval     Memory dword at given address
+; */
+Read64Mem32  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     eax, fs:[ebx]
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     eax, ds:[esi]
+Done:
+        ret
+
+Read64Mem32  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO byte
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+
+Write64Mem8  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:BYTE
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     al, Data
+        mov     fs:[ebx], al
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     al, Data
+        mov     ds:[esi], al
+Done:
+
+        ret
+
+Write64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO word
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+Write64Mem16  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:WORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     ax, Data
+        mov     fs:[ebx], ax
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     ax, Data
+        mov     ds:[esi], ax
+Done:
+        ret
+
+Write64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO dword
+; *
+; * @param[in]  Address - Memory Address
+; * @param[in]  Value   - Value to write
+; */
+Write64Mem32  PROC NEAR C PUBLIC USES EBX EDI ESI Address:QWORD, Data:DWORD
+
+        mov     esi, DWORD PTR Address[0]
+        mov     edi, DWORD PTR Address[4]
+        test    edi, edi
+        jz      AccesBelow4G
+
+        push    fs
+        call    SetFsBase
+        xor     ebx, ebx
+        mov     eax, Data
+        mov     fs:[ebx], eax
+        call    RestoreHwcr
+        pop     fs
+        jmp     Done
+AccesBelow4G:
+        mov     eax, Data
+        mov     ds:[esi], eax
+
+Done:
+
+        ret
+
+Write64Mem32  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read various CPU registers
+; *
+; * @param[in]  Reg     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  Value   Value to write
+; */
+
+LibAmdReadCpuReg PROC NEAR C Reg:BYTE, Value:NEAR PTR DWORD
+    pushad
+    push ds
+
+    .if(Reg == 00h)
+        mov eax, cr0
+    .elseif(Reg == 04h)
+        mov eax, cr4
+    .elseif(Reg == 10h)
+        mov eax, dr0
+    .elseif(Reg == 11h)
+        mov eax, dr1
+    .elseif(Reg == 12h)
+        mov eax, dr2
+    .elseif(Reg == 13h)
+        mov eax, dr3
+    .elseif(Reg == 17h)
+        mov eax, dr7
+    .else
+        xor eax,eax
+    .endif
+
+    mov edi, Value
+    mov [edi], eax
+
+    pop ds
+    popad
+    ret
+LibAmdReadCpuReg ENDP
+
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write various CPU registers
+; *
+; * @param[in]  Reg     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  Value   Value to write
+; */
+
+LibAmdWriteCpuReg PROC NEAR C Reg:BYTE, Value:DWORD
+    mov eax, Value
+
+    .if(Reg == 00h)
+        mov cr0, eax
+    .elseif(Reg == 4)
+        mov cr4, eax
+    .elseif(Reg == 10h)
+        mov dr0, eax
+    .elseif(Reg == 11h)
+        mov dr1, eax
+    .elseif(Reg == 12h)
+        mov dr2, eax
+    .elseif(Reg == 13h)
+        mov dr3, eax
+    .elseif(Reg == 17h)
+        mov dr7, eax
+    .endif
+    ret
+LibAmdWriteCpuReg ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write back invalidate caches using wbinvd.
+; *
+; *
+; *
+; */
+
+PUBLIC LibAmdWriteBackInvalidateCache
+LibAmdWriteBackInvalidateCache PROC NEAR C
+    wbinvd
+    ret
+LibAmdWriteBackInvalidateCache ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+
+PUBLIC StopHere
+StopHere PROC NEAR C
+@@:
+    jmp short @b
+StopHere ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Enter debugger on SimNow
+; *
+; *
+; *
+; */
+PUBLIC LibAmdSimNowEnterDebugger
+LibAmdSimNowEnterDebugger PROC NEAR C
+    pushad
+    mov     eax, 0BACCD00Bh         ; Backdoor in SimNow
+    mov     ebx, 2                  ; Select breakpoint feature
+    cpuid
+@@:
+    jmp short @b
+    popad
+    ret
+LibAmdSimNowEnterDebugger ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  IDS IO port write
+; *
+; * @param[in]  Address     IO Port Address
+; * @param[in]  Value       Value to write
+; * @param[in]  Flag        IDS flags
+; *
+; */
+
+PUBLIC IdsOutPort
+IdsOutPort PROC NEAR C Address:DWORD, Value:DWORD ,Flag:DWORD
+    push edx
+    push eax
+    push ebx
+    mov edx, Address
+    mov eax, Value
+    mov ebx, Flag
+    out dx, eax
+    pop ebx
+    pop eax
+    pop edx
+    ret
+IdsOutPort  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Force breakpoint on HDT
+; *
+; *
+; */
+PUBLIC LibAmdHDTBreakPoint
+LibAmdHDTBreakPoint PROC NEAR C
+
+    pushad
+
+    mov ecx, 0C001100Ah             ;bit 0 = HDT redirect
+    mov edi, 09C5A203Ah             ;Password
+    RDMSR                           ;
+    or al, 1                        ;
+    WRMSR                           ;
+    mov al, 0B2h                    ;Marker = B2
+    db 0F1h                         ;ICEBP
+
+    popad
+    ret
+
+LibAmdHDTBreakPoint ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most right hand side non-zero bit with .
+; *
+; * @param[in]  Value       Value
+; */
+PUBLIC LibAmdBitScanForward
+LibAmdBitScanForward PROC NEAR C Value:DWORD
+    mov eax, Value
+    bsf eax, Value
+    .if (Zero?)
+      mov al,32
+    .endif
+    ret
+LibAmdBitScanForward  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most left hand side non-zero bit.
+; *
+; * @param[in]  Value       Value
+; */
+PUBLIC LibAmdBitScanReverse
+LibAmdBitScanReverse PROC NEAR C Value:DWORD
+    mov eax, Value
+    bsr eax, Value
+    .if (Zero?)
+      mov al,0FFh
+    .endif
+    ret
+LibAmdBitScanReverse  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Flush specified number of cache line
+; *
+; *  @param[in]  Address      Physical address to be flushed
+; *  @param[in]  Count        number of cachelines to be flushed
+; */
+PUBLIC LibAmdCLFlush
+LibAmdCLFlush  PROC NEAR C Address:QWORD, Count:BYTE
+    pushad
+    mov ecx, 0C0010015h ; HWCR
+    rdmsr
+    mov esi, eax
+    mov edi, edx
+    bts eax, 17         ; HWCR.Wrap32Dis
+    wrmsr
+    xor eax, eax
+    mov edx, DWORD PTR Address[4]
+    mov ecx, 0C0000100h ; FS_BASE
+    wrmsr
+    mov eax, DWORD PTR Address[0]
+    movzx ecx, Count
+    @@:
+    mfence
+    clflush fs:[eax]
+    mfence
+    add eax,64
+    loop @B
+    call RestoreHwcr
+    popad
+    ret
+LibAmdCLFlush  ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm
new file mode 100644
index 0000000..18b8ee4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm
@@ -0,0 +1,110 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 9201 $   @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+;/*++
+;
+;Routine Description:
+;
+;  Shifts a UINT64 to the right.
+;
+;Arguments:
+;
+;  EDX:EAX - UINT64 value to be shifted
+;  CL -      Shift count
+;
+;Returns:
+;
+;  EDX:EAX - shifted value
+;
+;--*/
+_aullshr  PROC NEAR C PUBLIC
+        .if (cl < 64)
+            .if (cl >= 32)
+                sub    cl, 32
+                mov    eax, edx
+                xor    edx, edx
+            .endif
+            shrd   eax, edx, cl
+            shr    edx, cl
+        .else
+            xor    eax, eax
+            xor    edx, edx
+        .endif
+        ret
+_aullshr ENDP
+
+;/*++
+;
+;Routine Description:
+;
+;  Shifts a UINT64 to the left.
+;
+;Arguments:
+;
+;  EDX:EAX - UINT64 value to be shifted
+;  CL -      Shift count
+;
+;Returns:
+;
+;  EDX:EAX - shifted value
+;
+;--*/
+_allshl  PROC NEAR C PUBLIC USES CX
+        .if (cl < 64)
+            .if (cl >= 32)
+                sub    cl, 32
+                mov    edx, eax
+                xor    eax, eax
+            .endif
+            shld   edx, eax, cl
+            shl    eax, cl
+        .else
+            xor    eax, eax
+            xor    edx, edx
+        .endif
+        ret
+_allshl ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm b/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm
new file mode 100644
index 0000000..9c098a6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm
@@ -0,0 +1,84 @@
+;/**
+; * @file
+; *
+; * Agesa library 32bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 9201 $   @e \$Date: 2008-10-31 03:36:20 -0500 (Fri, 31 Oct 2008) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+.586p
+.model  flat
+ASSUME FS:NOTHING
+.code
+; void *memcpy( void *dest, void *src, size_t count );
+;
+; Copy count bytes from src to dest, returning dest.
+; ("c" is not legal as an assembly parameter name, replaced with value.)
+; Assume ES is set appropriately, 32 bit flat.
+;
+public memcpy
+memcpy  PROC NEAR C PUBLIC USES ECX EDI ESI dest:DWORD, src:DWORD, count:DWORD
+        pushf
+        cld     ; We will increment through *dest
+        mov     edi, dest
+        mov     esi, src
+        mov     ecx, count
+        rep movsb
+        mov eax, dest
+        popf
+        ret
+memcpy ENDP
+
+; void *memset( void *dest, int c, size_t count );
+;
+; At dest, set count bytes to byte value, returning dest.
+; ("c" is not legal as an assembly parameter name, replaced with value.)
+; Assume ES is set appropriately, 32 bit flat.
+;
+public memset
+memset  PROC NEAR C PUBLIC USES ECX EDI dest:DWORD, value:DWORD, count:DWORD
+        pushf
+        cld     ; We will increment through *dest
+        mov     edi, dest
+        mov     eax, value
+        mov     ecx, count
+        rep stosb
+        mov     eax, edi
+        popf
+        ret
+memset ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.c b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
new file mode 100644
index 0000000..ca268ee
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.c
@@ -0,0 +1,1355 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Library
+ *
+ * Contains interface to the AMD AGESA library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Lib
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "amdlib.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE LIB_AMDLIB_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+BOOLEAN
+STATIC
+GetPciMmioAddress (
+     OUT   UINT64            *MmioAddress,
+     OUT   UINT32            *MmioSize,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+LibAmdGetDataFromPtr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       VOID         *Data,
+  IN       VOID         *DataMask,
+     OUT   UINT32       *TemData,
+     OUT   UINT32       *TempDataMask
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT8
+ReadIo8 (
+  IN       UINT16 Address
+  )
+{
+  return __inbyte (Address);
+}
+UINT16
+ReadIo16 (
+  IN       UINT16 Address
+  )
+{
+  return __inword (Address);
+}
+UINT32
+ReadIo32 (
+  IN       UINT16 Address
+  )
+{
+  return __indword (Address);
+}
+VOID
+WriteIo8 (
+  IN       UINT16 Address,
+  IN       UINT8 Data
+  )
+{
+  __outbyte (Address, Data);
+}
+VOID
+WriteIo16 (
+  IN       UINT16 Address,
+  IN       UINT16 Data
+  )
+{
+  __outword (Address, Data);
+}
+VOID
+WriteIo32 (
+  IN       UINT16 Address,
+  IN       UINT32 Data
+  )
+{
+   __outdword (Address, Data);
+}
+STATIC
+UINT64 SetFsBase (
+  UINT64 address
+  )
+{
+  UINT64 hwcr;
+  hwcr = __readmsr (0xC0010015);
+  __writemsr (0xC0010015, hwcr | 1 << 17);
+  __writemsr (0xC0000100, address);
+  return hwcr;
+}
+STATIC
+VOID
+RestoreHwcr (
+  UINT64
+  value
+  )
+{
+  __writemsr (0xC0010015, value);
+}
+UINT8
+Read64Mem8 (
+  IN       UINT64 Address
+  )
+{
+  UINT8 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT8 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsbyte (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+}
+UINT16
+Read64Mem16 (
+  IN       UINT64 Address
+  )
+{
+  UINT16 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT16 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsword (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+}
+UINT32
+Read64Mem32 (
+  IN       UINT64 Address
+  )
+{
+  UINT32 dataRead;
+  UINT64 hwcrSave;
+  if ((Address >> 32) == 0) {
+    return *(volatile UINT32 *) (UINTN) Address;
+  }
+  hwcrSave = SetFsBase (Address);
+  dataRead = __readfsdword (0);
+  RestoreHwcr (hwcrSave);
+  return dataRead;
+  }
+VOID
+Write64Mem8 (
+  IN       UINT64 Address,
+  IN       UINT8 Data
+  )
+{
+  if ((Address >> 32) == 0){
+    *(volatile UINT8 *) (UINTN) Address = Data;
+  }
+  else {
+    UINT64 hwcrSave;
+    hwcrSave = SetFsBase (Address);
+    __writefsbyte (0, Data);
+    RestoreHwcr (hwcrSave);
+  }
+}
+VOID
+Write64Mem16 (
+  IN       UINT64 Address,
+  IN       UINT16 Data
+  )
+{
+ if ((Address >> 32) == 0){
+   *(volatile UINT16 *) (UINTN) Address = Data;
+ }
+ else {
+   UINT64 hwcrSave;
+   hwcrSave = SetFsBase (Address);
+   __writefsword (0, Data);
+   RestoreHwcr (hwcrSave);
+ }
+}
+VOID
+Write64Mem32 (
+  IN       UINT64 Address,
+  IN       UINT32 Data
+  )
+{
+  if ((Address >> 32) == 0){
+    *(volatile UINT32 *) (UINTN) Address = Data;
+  }
+  else {
+    UINT64 hwcrSave;
+    hwcrSave = SetFsBase (Address);
+    __writefsdword (0, Data);
+    RestoreHwcr (hwcrSave);
+  }
+}
+VOID
+LibAmdReadCpuReg (
+  IN       UINT8 RegNum,
+     OUT   UINT32 *Value
+  )
+{
+    *Value = 0;
+    switch (RegNum){
+    case CR4_REG:
+      *Value = __readcr4 ();
+      break;
+    case DR0_REG:
+      *Value = __readdr (0);
+      break;
+    case DR1_REG:
+      *Value = __readdr (1);
+      break;
+    case DR2_REG:
+      *Value = __readdr (2);
+      break;
+    case DR3_REG:
+      *Value = __readdr (3);
+      break;
+    case DR7_REG:
+      *Value = __readdr (7);
+      break;
+    default:
+      *Value = -1;
+  }
+}
+VOID
+LibAmdWriteCpuReg (
+  IN       UINT8 RegNum,
+  IN       UINT32 Value
+  )
+{
+   switch (RegNum){
+    case CR4_REG:
+      __writecr4 (Value);
+      break;
+    case DR0_REG:
+      __writedr (0, Value);
+      break;
+    case DR1_REG:
+      __writedr (1, Value);
+      break;
+    case DR2_REG:
+      __writedr (2, Value);
+      break;
+    case DR3_REG:
+      __writedr (3, Value);
+      break;
+    case DR7_REG:
+      __writedr (7, Value);
+      break;
+    default:
+      ;
+  }
+}
+VOID
+LibAmdWriteBackInvalidateCache (
+  IN       VOID
+  )
+{
+  __wbinvd ();
+}
+VOID
+LibAmdHDTBreakPoint (
+  VOID
+  )
+{
+  __writemsr (0xC001100A, __readmsr (0xC001100A) | 1);
+  __debugbreak (); // do you really need icebp? If so, go back to asm code
+}
+UINT8
+LibAmdBitScanForward (
+  IN       UINT32 value
+  )
+{
+  UINTN Index;
+  for (Index = 0; Index < 32; Index++){
+    if (value & (1 << Index)) break;
+  }
+  return (UINT8) Index;
+}
+UINT8
+LibAmdBitScanReverse (
+  IN       UINT32 value
+)
+{
+  UINTN Index;
+  for (Index = 31; Index >= 0; Index--){
+      if (value & (1 << Index)) break;
+  }
+  return (UINT8) Index;
+}
+
+UINT64
+MsrRead (
+  IN       UINT32 MsrAddress
+  )
+{
+  return __readmsr (MsrAddress);
+}
+
+VOID
+MsrWrite (
+  IN       UINT32 MsrAddress,
+  IN			 UINT64 Value
+  )
+{
+  __writemsr (MsrAddress, Value);
+}
+
+VOID
+LibAmdMsrRead (
+  IN       UINT32 MsrAddress,
+     OUT   UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  *Value = __readmsr (MsrAddress);
+}
+VOID
+LibAmdMsrWrite (
+  IN       UINT32 MsrAddress,
+  IN       UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  __writemsr (MsrAddress, *Value);
+}
+void LibAmdCpuidRead (
+  IN       UINT32 CpuidFcnAddress,
+     OUT   CPUID_DATA* Value,
+  IN OUT   AMD_CONFIG_PARAMS *ConfigPtr
+  )
+{
+  __cpuid ((int *)Value, CpuidFcnAddress);
+}
+UINT64
+ReadTSC (
+  VOID
+  )
+{
+  return __rdtsc ();
+}
+VOID
+LibAmdSimNowEnterDebugger (
+  VOID
+  )
+{
+  STATIC CONST UINT8 opcode [] = {0x60,                             // pushad
+                                   0xBB, 0x02, 0x00, 0x00, 0x00,     // mov ebx, 2
+                                   0xB8, 0x0B, 0xD0, 0xCC, 0xBA,     // mov eax, 0xBACCD00B
+                                   0x0F, 0xA2,                       // cpuid
+                                   0x61,                             // popad
+                                   0xC3                              // ret
+                                 };
+  ((VOID (*)(VOID)) (size_t) opcode) (); // call the function
+}
+VOID F10RevDProbeFilterCritical (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT32   PciRegister
+  )
+{
+  UINT64 msrsave;
+  msrsave = __readmsr (0xC001001F);
+  __writemsr (0xC001001F, msrsave | 1ULL << 46);  // EnableCf8ExtCfg
+  _mm_mfence ();
+  __outdword (0xCF8, PciAddress.AddressValue);
+  _mm_mfence ();
+  __outdword (0xCFC, PciRegister | 2);
+  _mm_mfence ();
+  __writemsr (0xC001001F, msrsave);
+}
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  )
+{
+  __outdword ((UINT16) Addr, Value);
+}
+VOID
+StopHere (
+  VOID
+  )
+{
+  VOLATILE UINTN x = 1;
+  while (x);
+}
+VOID
+LibAmdCLFlush (
+  IN       UINT64 Address,
+  IN       UINT8  Count
+  )
+{
+  UINT64 hwcrSave;
+  UINT8  *address32;
+  UINTN  Index;
+  address32 = 0;
+  hwcrSave = SetFsBase (Address);
+  for (Index = 0; Index < Count; Index++){
+    _mm_mfence ();
+    _mm_clflush_fs (&address32 [Index * 64]);
+  }
+  RestoreHwcr (hwcrSave);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read IO port
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO port address
+ * @param[in] Value         Pointer to save data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *(UINT8 *) Value = ReadIo8 (IoAddress);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *(UINT16 *) Value = ReadIo16 (IoAddress);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *(UINT32 *) Value = ReadIo32 (IoAddress);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write IO port
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO port address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    WriteIo8 (IoAddress, *(UINT8 *) Value);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    WriteIo16 (IoAddress, *(UINT16 *) Value);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    WriteIo32 (IoAddress, *(UINT32 *) Value);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * IO read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO address
+ * @param[in] Data          OR data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdIoWrite (AccessWidth, IoAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll IO register
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] IoAddress     IO address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      And mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdIoPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdIoRead (AccessWidth, IoAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read memory/MMIO
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *(UINT8 *) Value = Read64Mem8 (MemAddress);
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *(UINT16 *) Value = Read64Mem16 (MemAddress);
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *(UINT32 *) Value = Read64Mem32 (MemAddress);
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write memory/MMIO
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    Write64Mem8 (MemAddress, *((UINT8 *) Value));
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    Write64Mem16 (MemAddress, *((UINT16 *) Value));
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    Write64Mem32 (MemAddress, *((UINT32 *) Value));
+    break;
+  default:
+    ASSERT (FALSE);
+  }
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Memory/MMIO read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Data          OR data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdMemWrite (AccessWidth, MemAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll Mmio
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] MemAddress    Memory address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdMemPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdMemRead (AccessWidth, MemAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read PCI config space
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 LegacyPciAccess;
+  UINT32 MMIOSize;
+  UINT64 RMWrite;
+  UINT64 RMWritePrevious;
+  UINT64 MMIOAddress;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
+  if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
+    // We need to convert our "portable" PCI address into a "real" PCI access
+    LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+    if (PciAddress.Address.Register <= 0xFF) {
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+    } else {
+      LibAmdMsrRead  (NB_CFG, &RMWritePrevious, StdHeader);
+      RMWrite = RMWritePrevious | 0x0000400000000000;
+      LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoRead (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+      LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
+    }
+    IDS_HDT_CONSOLE (LIB_PCI_RD, "~PCI RD %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
+  } else {
+    // Setup the MMIO address
+    ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
+    MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
+    LibAmdMemRead (AccessWidth, MMIOAddress, Value, StdHeader);
+    IDS_HDT_CONSOLE (LIB_PCI_RD, "~MMIO RD %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write PCI config space
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Value         Pointer to data
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 LegacyPciAccess;
+  UINT32 MMIOSize;
+  UINT64 RMWrite;
+  UINT64 RMWritePrevious;
+  UINT64 MMIOAddress;
+
+  ASSERT (StdHeader != NULL);
+  ASSERT (PciAddress.AddressValue != ILLEGAL_SBDFO);
+  if (!GetPciMmioAddress (&MMIOAddress, &MMIOSize, StdHeader)) {
+    // We need to convert our "portable" PCI address into a "real" PCI access
+    LegacyPciAccess = ((1 << 31) + (PciAddress.Address.Register & 0xFC) + (PciAddress.Address.Function << 8) + (PciAddress.Address.Device << 11) + (PciAddress.Address.Bus << 16) + ((PciAddress.Address.Register & 0xF00) << (24 - 8)));
+    if (PciAddress.Address.Register <= 0xFF) {
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+    } else {
+      LibAmdMsrRead  (NB_CFG, &RMWritePrevious, StdHeader);
+      RMWrite = RMWritePrevious | 0x0000400000000000;
+      LibAmdMsrWrite (NB_CFG, &RMWrite, StdHeader);
+      LibAmdIoWrite (AccessWidth32, IOCF8, &LegacyPciAccess, StdHeader);
+      LibAmdIoWrite (AccessWidth, IOCFC + (UINT16) (PciAddress.Address.Register & 0x3), Value, StdHeader);
+      LibAmdMsrWrite (NB_CFG, &RMWritePrevious, StdHeader);
+    }
+    IDS_HDT_CONSOLE (LIB_PCI_WR, "~PCI WR %08x = %08x\n", LegacyPciAccess, *(UINT32 *)Value);
+  } else {
+    // Setup the MMIO address
+    ASSERT ((MMIOAddress + MMIOSize) > (MMIOAddress + (PciAddress.AddressValue & 0x0FFFFFFF)));
+    MMIOAddress += (PciAddress.AddressValue & 0x0FFFFFFF);
+    LibAmdMemWrite (AccessWidth, MMIOAddress, Value, StdHeader);
+    IDS_HDT_CONSOLE (LIB_PCI_WR, "~MMIO WR %08x = %08x\n", (UINT32) MMIOAddress, *(UINT32 *)Value);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * PCI read modify write
+ *
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Data          OR Data
+ * @param[in] DataMask      Mask to be used before data write back to register.
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
+  Value = (Value & (~TempMask)) | TempData;
+  LibAmdPciWrite (AccessWidth, PciAddress, &Value, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Poll PCI config space register
+ *
+ *  Poll register until (RegisterValue & DataMask) ==  Data
+ *
+ * @param[in] AccessWidth   Access width
+ * @param[in] PciAddress    Pci address
+ * @param[in] Data          Data to compare
+ * @param[in] DataMask      AND mask
+ * @param[in] Delay         Poll for time in 100ns (not supported)
+ * @param[in] StdHeader     Standard configuration header
+ *
+ */
+VOID
+LibAmdPciPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32  TempData;
+  UINT32  TempMask;
+  UINT32  Value;
+  LibAmdGetDataFromPtr (AccessWidth, Data,  DataMask, &TempData, &TempMask);
+  do {
+    LibAmdPciRead (AccessWidth, PciAddress, &Value, StdHeader);
+  } while (TempData != (Value & TempMask));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get MMIO base address for PCI accesses
+ *
+ * @param[out] MmioAddress   PCI MMIO base address
+ * @param[out] MmioSize      Size of region in bytes
+ * @param[in]  StdHeader     Standard configuration header
+ *
+ * @retval    TRUE          MmioAddress/MmioSize are valid
+ */
+BOOLEAN
+STATIC
+GetPciMmioAddress (
+     OUT   UINT64            *MmioAddress,
+     OUT   UINT32            *MmioSize,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN MmioIsEnabled;
+  UINT32  EncodedSize;
+  UINT64  LocalMsrRegister;
+
+  ASSERT (StdHeader != NULL);
+
+  MmioIsEnabled = FALSE;
+  LibAmdMsrRead (MSR_MMIO_Cfg_Base, &LocalMsrRegister, StdHeader);
+  if ((LocalMsrRegister & BIT0) != 0) {
+    *MmioAddress = LocalMsrRegister & 0xFFFFFFFFFFF00000;
+    EncodedSize = (UINT32) ((LocalMsrRegister & 0x3C) >> 2);
+    *MmioSize = ((1 << EncodedSize) * 0x100000);
+    MmioIsEnabled = TRUE;
+  }
+  return MmioIsEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Read field of PCI config register.
+ *
+ *
+ *
+ * @param[in]   Address       Pci address  (register must be DWORD aligned)
+ * @param[in]   Highbit       High bit position of the field in DWORD
+ * @param[in]   Lowbit        Low bit position of the field in DWORD
+ * @param[out]  Value         Pointer to data
+ * @param[in]   StdHeader     Standard configuration header
+ */
+VOID
+LibAmdPciReadBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+     OUT   UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
+
+  LibAmdPciRead (AccessWidth32, Address, Value, StdHeader);
+  *Value >>= Lowbit;  // Shift
+
+  // A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
+
+  if ((Highbit - Lowbit) != 31) {
+    *Value &= (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Write field of PCI config register.
+ *
+ *
+ *
+ * @param[in]   Address       Pci address  (register must be DWORD aligned)
+ * @param[in]   Highbit       High bit position of the field in DWORD
+ * @param[in]   Lowbit        Low bit position of the field in DWORD
+ * @param[in]   Value         Pointer to data
+ * @param[in]   StdHeader     Standard configuration header
+ */
+VOID
+LibAmdPciWriteBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 Temp;
+  UINT32 Mask;
+
+  ASSERT (Highbit < 32 && Lowbit < 32 && Highbit >= Lowbit && (Address.AddressValue & 3) == 0);
+
+  // A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
+
+  if ((Highbit - Lowbit) != 31) {
+    Mask = (((UINT32) 1 << (Highbit - Lowbit + 1)) - 1);
+  } else {
+    Mask = (UINT32) 0xFFFFFFFF;
+  }
+
+  LibAmdPciRead (AccessWidth32, Address, &Temp, StdHeader);
+  Temp &= ~(Mask << Lowbit);
+  Temp |= (*Value & Mask) << Lowbit;
+  LibAmdPciWrite (AccessWidth32, Address, &Temp, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locate next capability pointer
+ *
+ *  Given a SBDFO this routine will find the next PCI capabilities list entry.
+ *  if the end of the list is reached, or if a problem is detected, then ILLEGAL_SBDFO is
+ *  returned.
+ *  To start a new search from the head of the list, specify a SBDFO with an offset of zero.
+ *
+ * @param[in,out] Address       Pci address
+ * @param[in]     StdHeader     Standard configuration header
+ */
+
+VOID
+LibAmdPciFindNextCap (
+  IN OUT   PCI_ADDR *Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  PCI_ADDR Base;
+  UINT32 Offset;
+  UINT32 Temp;
+  PCI_ADDR TempAddress;
+
+  ASSERT (Address != NULL);
+  ASSERT (*(UINT32 *) Address != ILLEGAL_SBDFO);
+
+  Base.AddressValue = Address->AddressValue;
+  Offset = Base.Address.Register;
+  Base.Address.Register = 0;
+
+  Address->AddressValue = (UINT32) ILLEGAL_SBDFO;
+
+  // Verify that the SBDFO points to a valid PCI device SANITY CHECK
+  LibAmdPciRead (AccessWidth32, Base, &Temp, StdHeader);
+  if (Temp == 0xFFFFFFFF) {
+    ASSERT (FALSE);
+    return; // There is no device at this address
+  }
+
+  // Verify that the device supports a capability list
+  TempAddress.AddressValue = Base.AddressValue + 0x04;
+  LibAmdPciReadBits (TempAddress, 20, 20, &Temp, StdHeader);
+  if (Temp == 0) {
+    return; // This PCI device does not support capability lists
+  }
+
+  if (Offset != 0) {
+    // If we are continuing on an existing list
+    TempAddress.AddressValue = Base.AddressValue + Offset;
+    LibAmdPciReadBits (TempAddress, 15, 8, &Temp, StdHeader);
+  } else {
+    // We are starting on a new list
+    TempAddress.AddressValue = Base.AddressValue + 0x34;
+    LibAmdPciReadBits (TempAddress, 7, 0, &Temp, StdHeader);
+  }
+
+  if (Temp == 0) {
+    return; // We have reached the end of the capabilities list
+  }
+
+  // Error detection and recovery- The statement below protects against
+  //   PCI devices with broken PCI capabilities lists.  Detect a pointer
+  //   that is not uint32 aligned, points into the first 64 reserved DWORDs
+  //   or points back to itself.
+  if (((Temp & 3) != 0) || (Temp == Offset) || (Temp < 0x40)) {
+    ASSERT (FALSE);
+    return;
+  }
+
+  Address->AddressValue = Base.AddressValue + Temp;
+  return;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set memory with value
+ *
+ *
+ * @param[in,out] Destination   Pointer to memory range
+ * @param[in]     Value         Value to set memory with
+ * @param[in]     FillLength    Size of the memory range
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+VOID
+LibAmdMemFill (
+  IN       VOID *Destination,
+  IN       UINT8 Value,
+  IN       UINTN FillLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *Dest;
+  ASSERT (StdHeader != NULL);
+  Dest = Destination;
+  while ((FillLength--) != 0) {
+    *Dest++ = Value;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Copy memory
+ *
+ *
+ * @param[in,out] Destination   Pointer to destination buffer
+ * @param[in]     Source        Pointer to source buffer
+ * @param[in]     CopyLength    buffer length
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+VOID
+LibAmdMemCopy (
+  IN       VOID *Destination,
+  IN       VOID *Source,
+  IN       UINTN CopyLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8 *Dest;
+  UINT8 *SourcePtr;
+  ASSERT (StdHeader != NULL);
+  Dest = Destination;
+  SourcePtr = Source;
+  while ((CopyLength--) != 0) {
+    *Dest++ = *SourcePtr++;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Verify checksum of binary image (B1/B2/B3)
+ *
+ *
+ * @param[in]   ImagePtr      Pointer to image  start
+ * @retval      TRUE          Checksum valid
+ * @retval      FALSE         Checksum invalid
+ */
+BOOLEAN
+LibAmdVerifyImageChecksum (
+  IN       VOID *ImagePtr
+  )
+{
+  // Assume ImagePtr points to the binary start ($AMD)
+  // Checksum is on an even boundary in AMD_IMAGE_HEADER
+
+  UINT16 Sum;
+  UINT32 i;
+
+  Sum = 0;
+
+  i = ((AMD_IMAGE_HEADER*) ImagePtr)->ImageSize;
+
+  while (i > 1) {
+    Sum = Sum + *((UINT16 *)ImagePtr);
+    ImagePtr = (VOID *) ((UINT8 *)ImagePtr + 2);
+    i = i - 2;
+  }
+  if (i > 0) {
+    Sum = Sum + *((UINT8 *) ImagePtr);
+  }
+
+  return (Sum == 0)?TRUE:FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Locate AMD binary image that contain specific module
+ *
+ *
+ * @param[in]   StartAddress    Pointer to start range
+ * @param[in]   EndAddress      Pointer to end range
+ * @param[in]   Alignment       Image address alignment
+ * @param[in]   ModuleSignature Module signature.
+ * @retval     NULL  if image not found
+ * @retval     pointer to image header
+ */
+VOID *
+LibAmdLocateImage (
+  IN       VOID *StartAddress,
+  IN       VOID *EndAddress,
+  IN       UINT32 Alignment,
+  IN       CHAR8 ModuleSignature[8]
+  )
+
+{
+  UINT8 *CurrentPtr;
+  AMD_MODULE_HEADER *ModuleHeaderPtr;
+  UINT64 *SearchStr;
+  UINT64 *InputStr;
+
+  CurrentPtr = StartAddress;
+  InputStr = (UINT64 *)ModuleSignature;
+
+  // Search from start to end incrementing by alignment
+  while ((CurrentPtr >= (UINT8 *) StartAddress) && (CurrentPtr < (UINT8 *) EndAddress)) {
+    // First find a binary image
+    if (*((UINT32 *) CurrentPtr) == IMAGE_SIGNATURE) {
+      if (LibAmdVerifyImageChecksum (CurrentPtr)) {
+        // If we have a valid image, search module linked list for a match
+        ModuleHeaderPtr = (AMD_MODULE_HEADER*) ((UINT8 *)CurrentPtr + ((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset);
+        while (ModuleHeaderPtr != NULL) {
+          SearchStr = (UINT64 *)&ModuleHeaderPtr->ModuleIdentifier;
+          if (*InputStr == *SearchStr) {
+            return  CurrentPtr;
+          }
+          ModuleHeaderPtr = (AMD_MODULE_HEADER *)ModuleHeaderPtr->NextBlock;
+        }
+      }
+    }
+    CurrentPtr += Alignment;
+  }
+  return NULL;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     StdHeader     Standard configuration header (Optional)
+ */
+
+//  Returns the package type mask for the processor
+UINT32
+LibAmdGetPackageType (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32      ProcessorPackageType;
+  CPUID_DATA  CpuId;
+
+  LibAmdCpuidRead (0x80000001, &CpuId, StdHeader);
+  ProcessorPackageType = (UINT32) (CpuId.EBX_Reg >> 28) & 0xF; // bit 31:28
+  return (UINT32) (1 << ProcessorPackageType);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     AccessWidth     Access width
+ * @param[in]     Data            data
+ * @param[in]     DataMask        data
+ * @param[out]    TemData         typecast data
+ * @param[out]    TempDataMask    typecast data
+ */
+
+
+VOID
+STATIC
+LibAmdGetDataFromPtr (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       VOID         *Data,
+  IN       VOID         *DataMask,
+     OUT   UINT32       *TemData,
+     OUT   UINT32       *TempDataMask
+  )
+{
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    *TemData = (UINT32)*(UINT8 *) Data;
+    *TempDataMask = (UINT32)*(UINT8 *) DataMask;
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    *TemData = (UINT32)*(UINT16 *) Data;
+    *TempDataMask = (UINT32)*(UINT16 *) DataMask;
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    *TemData = *(UINT32 *) Data;
+    *TempDataMask = *(UINT32 *) DataMask;
+    break;
+  default:
+    IDS_ERROR_TRAP;
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the package type mask for the processor
+ *
+ *
+ * @param[in]     AccessWidth     Access width
+ * @retval        Width in number of bytes
+ */
+
+
+UINT8
+LibAmdAccessWidth (
+  IN       ACCESS_WIDTH AccessWidth
+  )
+{
+  UINT8 Width;
+
+  switch (AccessWidth) {
+  case AccessWidth8:
+  case AccessS3SaveWidth8:
+    Width = 1;
+    break;
+  case AccessWidth16:
+  case AccessS3SaveWidth16:
+    Width = 2;
+    break;
+  case AccessWidth32:
+  case AccessS3SaveWidth32:
+    Width = 4;
+    break;
+  case AccessWidth64:
+  case AccessS3SaveWidth64:
+    Width = 8;
+    break;
+  default:
+    Width = 0;
+    IDS_ERROR_TRAP;
+  }
+  return Width;
+}
+VOID
+CpuidRead (
+  IN        UINT32      CpuidFcnAddress,
+  OUT       CPUID_DATA  *Value
+  )
+{
+  __cpuid ((int *)Value, CpuidFcnAddress);
+}
+UINT8
+ReadNumberOfCpuCores(
+  VOID
+  )
+{
+  CPUID_DATA  Value;
+  CpuidRead (0x80000008, &Value);
+  return   Value.ECX_Reg & 0xff;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Lib/amdlib.h b/src/vendorcode/amd/agesa/f15/Lib/amdlib.h
new file mode 100644
index 0000000..a9a722f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/amdlib.h
@@ -0,0 +1,403 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Library
+ *
+ * Contains interface to the AMD AGESA library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Lib
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ **/
+
+#ifndef _AMD_LIB_H_
+#define _AMD_LIB_H_
+
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+// Reg Values for ReadCpuReg and WriteCpuReg
+#define    CR4_REG  0x04
+#define    DR0_REG  0x10
+#define    DR1_REG  0x11
+#define    DR2_REG  0x12
+#define    DR3_REG  0x13
+#define    DR7_REG  0x17
+
+// PROTOTYPES FOR amdlib32.asm
+UINT8
+ReadIo8 (
+  IN       UINT16 Address
+  );
+
+UINT16
+ReadIo16 (
+  IN       UINT16 Address
+  );
+
+UINT32
+ReadIo32 (
+  IN       UINT16 Address
+  );
+
+VOID
+WriteIo8 (
+  IN       UINT16 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+WriteIo16 (
+  IN       UINT16 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+WriteIo32 (
+  IN       UINT16 Address,
+  IN       UINT32 Data
+  );
+
+UINT8
+Read64Mem8 (
+  IN       UINT64 Address
+  );
+
+UINT16
+Read64Mem16 (
+  IN       UINT64 Address
+  );
+
+UINT32
+Read64Mem32 (
+  IN       UINT64 Address
+  );
+
+VOID
+Write64Mem8 (
+  IN       UINT64 Address,
+  IN       UINT8 Data
+  );
+
+VOID
+Write64Mem16 (
+  IN       UINT64 Address,
+  IN       UINT16 Data
+  );
+
+VOID
+Write64Mem32 (
+  IN       UINT64 Address,
+  IN       UINT32 Data
+  );
+
+UINT64
+ReadTSC (
+  VOID
+  );
+
+// MSR
+
+UINT64
+MsrRead (
+  IN       UINT32 MsrAddress
+  );
+
+VOID
+MsrWrite (
+  IN       UINT32 MsrAddress,
+  IN			 UINT64 Value
+  );
+
+VOID
+LibAmdMsrRead (
+  IN       UINT32 MsrAddress,
+     OUT   UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMsrWrite (
+  IN       UINT32 MsrAddress,
+  IN       UINT64 *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// IO
+VOID
+LibAmdIoRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdIoPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT16 IoAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Memory or MMIO
+VOID
+LibAmdMemRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       UINT64 MemAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// PCI
+VOID
+LibAmdPciRead (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+     OUT   VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWrite (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciRMW (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciPoll (
+  IN       ACCESS_WIDTH AccessWidth,
+  IN       PCI_ADDR PciAddress,
+  IN       VOID *Data,
+  IN       VOID *DataMask,
+  IN       UINT64 Delay,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciReadBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+     OUT   UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciWriteBits (
+  IN       PCI_ADDR Address,
+  IN       UINT8 Highbit,
+  IN       UINT8 Lowbit,
+  IN       UINT32 *Value,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdPciFindNextCap (
+  IN OUT   PCI_ADDR *Address,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// CPUID
+VOID
+LibAmdCpuidRead (
+  IN       UINT32 CpuidFcnAddress,
+     OUT   CPUID_DATA *Value,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+// Utility Functions
+VOID
+LibAmdMemFill (
+  IN       VOID *Destination,
+  IN       UINT8 Value,
+  IN       UINTN FillLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+LibAmdMemCopy (
+  IN       VOID *Destination,
+  IN       VOID *Source,
+  IN       UINTN CopyLength,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID *
+LibAmdLocateImage (
+  IN       VOID *StartAddress,
+  IN       VOID *EndAddress,
+  IN       UINT32 Alignment,
+  IN       CHAR8 ModuleSignature[8]
+  );
+
+UINT32
+LibAmdGetPackageType (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+LibAmdVerifyImageChecksum (
+  IN       VOID *ImagePtr
+  );
+
+UINT8
+LibAmdBitScanReverse (
+  IN       UINT32 value
+  );
+UINT8
+LibAmdBitScanForward (
+  IN       UINT32 value
+  );
+
+VOID
+LibAmdReadCpuReg (
+  IN       UINT8 RegNum,
+     OUT   UINT32 *Value
+  );
+VOID
+LibAmdWriteCpuReg (
+  IN       UINT8 RegNum,
+  IN       UINT32 Value
+  );
+
+VOID
+LibAmdWriteBackInvalidateCache (
+  IN       VOID
+  );
+
+VOID
+LibAmdSimNowEnterDebugger (VOID);
+
+VOID
+LibAmdHDTBreakPoint (VOID);
+
+UINT8
+LibAmdAccessWidth (
+  IN       ACCESS_WIDTH AccessWidth
+  );
+
+VOID
+LibAmdCLFlush (
+  IN       UINT64 Address,
+  IN       UINT8  Count
+  );
+
+VOID F10RevDProbeFilterCritical (
+  IN       PCI_ADDR PciAddress,
+  IN       UINT32   PciRegister
+  );
+VOID
+IdsOutPort (
+  IN       UINT32 Addr,
+  IN       UINT32 Value,
+  IN       UINT32 Flag
+  );
+
+VOID
+StopHere (
+  VOID
+  );
+
+VOID
+CpuidRead (
+  IN        UINT32      CpuidFcnAddress,
+  OUT       CPUID_DATA  *Value
+  );
+
+UINT8
+ReadNumberOfCpuCores(
+  VOID
+  );
+
+#endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/agesa/f15/Lib/helper.c b/src/vendorcode/amd/agesa/f15/Lib/helper.c
new file mode 100644
index 0000000..8c9e1d4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/helper.c
@@ -0,0 +1,68 @@
+/*
+ *****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ *
+ */
+
+// helper.c - these functions are compiled separately because they redefine
+//            functions invoked directly by the compiler code generator.
+//            The Microsoft tools do not allow such functions to be compiled
+//            with the "Enable link-time code generation (/GL)" option. Compile
+//            this module without /GL to avoid a build failure LNK1237.
+//
+
+#if defined (_MSC_VER)
+
+#include "Porting.h"
+
+//---------------------------------------------------------------------------
+void *memcpy (void *dest, const void *src, size_t bytes)
+   {
+   // Rep movsb is faster than a byte loop, but still quite slow
+   // for large operations. However, it is a good choice here because
+   // this function is intended for use by the compiler only. For
+   // large copy operations, call LibAmdMemCopy.
+   __movsb (dest, src, bytes);
+   return dest;
+   }
+
+//---------------------------------------------------------------------------
+
+void *memset (void *dest, int value, size_t bytes)
+   {
+   // Rep stosb is faster than a byte loop, but still quite slow
+   // for large operations. However, it is a good choice here because
+   // this function is intended for use by the compiler only. For
+   // large fill operations, call LibAmdMemFill.
+   __stosb (dest, value, bytes);
+   return dest;
+   }
+//---------------------------------------------------------------------------
+
+#endif
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm b/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm
new file mode 100644
index 0000000..8ec78d1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm
@@ -0,0 +1,591 @@
+;/**
+; * @file
+; *
+; * Agesa library 64bit
+; *
+; * Contains AMD AGESA Library
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  Lib
+; * @e \$Revision: 17071 $   @e \$Date: 2009-07-30 10:13:11 -0700 (Thu, 30 Jul 2009) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+.code
+;/*++
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO byte
+; *
+; *  @param[in]   CX    IO port address
+; *  @param[in]   DL    IO port Value
+; */
+
+PUBLIC  WriteIo8
+WriteIo8        PROC
+        mov     al, dl
+        mov     dx, cx
+        out     dx, al
+        ret
+WriteIo8        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO word
+; *
+; *  @param[in]   CX      IO port address
+; *  @param[in]   DX      IO port Value
+; */
+PUBLIC  WriteIo16
+WriteIo16       PROC
+        mov     ax, dx
+        mov     dx, cx
+        out     dx, ax
+        ret
+WriteIo16       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write IO dword
+; *
+; *  @param[in]   CX      IO port address
+; *  @param[in]   EDX     IO port Value
+; */
+
+PUBLIC WriteIo32
+WriteIo32       PROC
+        mov     eax, edx
+        mov     dx, cx
+        out     dx, eax
+        ret
+WriteIo32       ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO byte
+; *
+; *  @param[in] CX  IO port address
+; *  @retval    AL  IO port Value
+; */
+PUBLIC ReadIo8
+ReadIo8 PROC
+        mov     dx, cx
+        in      al, dx
+        ret
+ReadIo8 ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO word
+; *
+; *  @param[in]   CX  IO port address
+; *  @retval      AX  IO port Value
+; */
+PUBLIC ReadIo16
+ReadIo16        PROC
+        mov     dx, cx
+        in      ax, dx
+        ret
+ReadIo16        ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read IO dword
+; *
+; *  @param[in]   CX  IO port address
+; *  @retval      EAX IO port Value
+; */
+PUBLIC ReadIo32
+ReadIo32        PROC
+        mov     dx, cx
+        in      eax, dx
+        ret
+ReadIo32        ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read MSR
+; *
+; *  @param[in]  RCX      MSR Address
+; *  @param[in]  RDX      Pointer to data
+; *  @param[in]  R8D      ConfigPtr (Optional)
+; */
+PUBLIC LibAmdMsrRead
+LibAmdMsrRead  PROC
+    push rsi
+    mov     rsi, rdx
+    rdmsr
+    mov     [rsi], eax
+    mov     [rsi+4], edx
+    pop rsi
+    ret
+LibAmdMsrRead  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write MSR
+; *
+; *  @param[in]  RCX        MSR Address
+; *  @param[in]  RDX        Pointer to data
+; *  @param[in]  R8D        ConfigPtr  (Optional)
+; */
+PUBLIC LibAmdMsrWrite
+LibAmdMsrWrite                PROC
+    push rsi
+    mov rsi, rdx
+    mov eax, [rsi]
+    and rax, 0ffffffffh
+    mov edx, [rsi+4]
+    and rdx, 0ffffffffh
+    wrmsr
+    pop rsi
+    ret
+LibAmdMsrWrite                ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read CPUID
+; *
+; *  @param[in]  RCX    CPUID function
+; *  @param[in]  RDX    Pointer to CPUID_DATA to save cpuid data
+; *  @param[in]  R8D    ConfigPtr (Optional)
+; */
+PUBLIC LibAmdCpuidRead
+LibAmdCpuidRead       PROC
+
+    push rbx
+    push rsi
+    mov  rsi, rdx
+    mov  rax, rcx
+    cpuid
+    mov [rsi],   eax
+    mov [rsi+4], ebx
+    mov [rsi+8], ecx
+    mov [rsi+12],edx
+    pop rsi
+    pop rbx
+    ret
+
+LibAmdCpuidRead              ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read TSC
+; *
+; *
+; * @retval     RAX Time stamp counter value
+; */
+
+PUBLIC ReadTSC
+ReadTSC  PROC
+    rdtsc
+    and  rax, 0ffffffffh
+    shl  rdx, 32
+    or   rax, rdx
+    ret
+ReadTSC  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO byte
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory byte at given address
+; */
+PUBLIC  Read64Mem8
+Read64Mem8  PROC
+
+     xor  rax, rax
+     mov  al, [rcx]
+     ret
+
+Read64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO word
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory word at given address
+; */
+PUBLIC  Read64Mem16
+Read64Mem16  PROC
+
+        xor     rax, rax
+        mov     ax, [rcx]
+        ret
+
+Read64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read memory/MMIO dword
+; *
+; * @param[in]  RCX - Memory Address
+; * @retval     Memory dword at given address
+; */
+PUBLIC  Read64Mem32
+Read64Mem32  PROC
+
+        xor     rax, rax
+        mov     eax, [rcx]
+        ret
+
+Read64Mem32  ENDP
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO byte
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  DL    Value to write
+; */
+
+PUBLIC  Write64Mem8
+Write64Mem8  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], al
+        ret
+
+Write64Mem8  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO word
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  DX    Value to write
+; */
+PUBLIC  Write64Mem16
+Write64Mem16  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], ax
+        ret
+
+Write64Mem16  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write memory/MMIO dword
+; *
+; * @param[in]  RCX   Memory Address
+; * @param[in]  EDX   Value to write
+; */
+PUBLIC  Write64Mem32
+Write64Mem32  PROC
+
+        xor     rax, rax
+        mov     rax, rdx
+        mov     [rcx], eax
+        ret
+
+Write64Mem32  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Read various CPU registers
+; *
+; * @param[in]  CL     Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  RDX    Pointer to value
+; */
+
+PUBLIC  LibAmdReadCpuReg
+LibAmdReadCpuReg PROC
+
+        push    rax
+        xor     rax, rax
+Reg00h:
+        cmp     cl, 00h
+        jne     Reg04h
+        mov     rax, cr0
+        jmp     RegRead
+Reg04h:
+        cmp     cl, 04h
+        jne     Reg10h
+        mov     rax, cr4
+        jmp     RegRead
+Reg10h:
+        cmp     cl, 10h
+        jne     Reg11h
+        mov     rax, dr0
+        jmp     RegRead
+Reg11h:
+        cmp     cl, 11h
+        jne     Reg12h
+        mov     rax, dr1
+        jmp     RegRead
+Reg12h:
+        cmp     cl, 12h
+        jne     Reg13h
+        mov     rax, dr2
+        jmp     RegRead
+Reg13h:
+        cmp     cl, 13h
+        jne     Reg17h
+        mov     rax, dr3
+        jmp     RegRead
+Reg17h:
+        cmp     cl, 17h
+        jne     RegRead
+        mov     rax, dr7
+RegRead:
+        mov     [rdx], eax
+        pop     rax
+        ret
+LibAmdReadCpuReg ENDP
+
+
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write various CPU registers
+; *
+; * @param[in]  CL    Register ID (0/4 - CR0/CR4, 10h/11h/12h/13h/17h - DR0/DR1/DR2/DR3/DR7)
+; * @param[in]  RDX   Value to write
+; */
+
+PUBLIC  LibAmdWriteCpuReg
+LibAmdWriteCpuReg PROC
+
+        push    rax
+Reg00h:
+        cmp     cl, 00h
+        jne     Reg04h
+        mov     rax, cr0
+        mov     eax, edx
+        mov     cr0, rax
+        jmp     Done
+Reg04h:
+        cmp     cl, 04h
+        jne     Reg10h
+        mov     rax, cr4
+        mov     eax, edx
+        mov     cr4, rax
+        jmp     Done
+Reg10h:
+        cmp     cl, 10h
+        jne     Reg11h
+        mov     rax, dr0
+        mov     eax, edx
+        mov     dr0, rax
+        jmp     Done
+Reg11h:
+        cmp     cl, 11h
+        jne     Reg12h
+        mov     rax, dr1
+        mov     eax, edx
+        mov     dr1, rax
+        jmp     Done
+Reg12h:
+        cmp     cl, 12h
+        jne     Reg13h
+        mov     rax, dr2
+        mov     eax, edx
+        mov     dr2, rax
+        jmp     Done
+Reg13h:
+        cmp     cl, 13h
+        jne     Reg17h
+        mov     rax, dr3
+        mov     eax, edx
+        mov     dr3, rax
+        jmp     Done
+Reg17h:
+        cmp     cl, 17h
+        jne     Done
+        mov     rax, dr7
+        mov     eax, edx
+        mov     dr7, rax
+Done:
+        pop     rax
+        ret
+LibAmdWriteCpuReg ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Write back invalidate caches using wbinvd.
+; *
+; *
+; *
+; */
+
+PUBLIC LibAmdWriteBackInvalidateCache
+LibAmdWriteBackInvalidateCache PROC
+    wbinvd
+    ret
+LibAmdWriteBackInvalidateCache ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Stop CPU
+; *
+; *
+; *
+; */
+
+PUBLIC StopHere
+StopHere PROC
+@@:
+    jmp short @b
+StopHere ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Enter debugger on SimNow
+; *
+; *
+; *
+; */
+PUBLIC LibAmdSimNowEnterDebugger
+LibAmdSimNowEnterDebugger PROC
+    pushfq
+    mov     rax, 0BACCD00Bh         ; Backdoor in SimNow
+    mov     rbx, 2                  ; Select breakpoint feature
+    cpuid
+@@:
+    jmp short @b
+    popfq
+    ret
+LibAmdSimNowEnterDebugger ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  IDS IO port write
+; *
+; * @param[in]  ECX     IO Port Address
+; * @param[in]  EDX     Value to write
+; * @param[in]  R8D     IDS flags
+; *
+; */
+
+PUBLIC IdsOutPort
+IdsOutPort PROC
+    push rbx
+    push rax
+
+    mov ebx, r8d
+    mov eax, edx
+    mov edx, ecx
+    out dx, eax
+
+    pop rax
+    pop rbx
+    ret
+IdsOutPort  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Force breakpoint on HDT
+; *
+; *
+; */
+PUBLIC LibAmdHDTBreakPoint
+LibAmdHDTBreakPoint PROC
+
+    push rbx
+
+    mov rcx, 0C001100Ah             ;bit 0 = HDT redirect
+    mov rdi, 09C5A203Ah             ;Password
+    rdmsr
+    and rax, 0ffffffffh
+    or rax, 1
+
+    wrmsr
+
+    mov rax, 0B2h                  ;Marker = B2
+    db 0F1h                        ;ICEBP
+
+    pop rbx
+    ret
+
+LibAmdHDTBreakPoint ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most right hand side non-zero bit with
+; *
+; * @param[in]  ECX       Value
+; */
+PUBLIC LibAmdBitScanForward
+LibAmdBitScanForward PROC
+    bsf eax, ecx
+    jnz nonZeroSource
+    mov al,32
+nonZeroSource:
+    ret
+LibAmdBitScanForward  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Find the most left hand side non-zero bit.
+; *
+; * @param[in]  ECX       Value
+; */
+PUBLIC LibAmdBitScanReverse
+LibAmdBitScanReverse PROC
+    bsr eax, ecx
+    jnz nonZeroSource
+    mov al,0FFh
+nonZeroSource:
+    ret
+LibAmdBitScanReverse  ENDP
+
+;/*---------------------------------------------------------------------------------------*/
+;/**
+; *  Flush specified number of cache line
+; *
+; *  @param[in]  RCX      Physical address to be flushed
+; *  @param[in]  DL       number of cachelines to be flushed
+; */
+PUBLIC LibAmdCLFlush
+LibAmdCLFlush  PROC
+    push rax
+    mov rax, rcx
+    movzx rcx, dl
+    @@:
+    mfence
+    clflush [rax]
+    mfence
+    add rax,64
+    loop @B
+    pop rax
+    ret
+LibAmdCLFlush  ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/MainPage.h b/src/vendorcode/amd/agesa/f15/MainPage.h
new file mode 100644
index 0000000..1e61de5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/MainPage.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/**
+ * @mainpage
+ *
+ * The design and maintenance documentation for AGESA Sample Code is organized as
+ * follows.  On this page, you can reference design guides, maintenance guides, and
+ * general documentation.  Detailed Data Structure, Function, and Interface documentation
+ * may be found using the Data Structures or Files tabs.  See Related Pages for a
+ * Release content summary, and, if this is not a production release, lists of To Do's,
+ * Deprecated items, etc.
+ *
+ * @subpage starthere "Start Here - Initial Porting and Integration."
+ *
+ * @subpage optionmain "Build Configuration and Options Guides and Documentation."
+ *
+ * @subpage commonmain "Processor Common Component Guides and Documentation."
+ *
+ * @subpage cpumain "CPU Component Guides and Documentation."
+ *
+ * @subpage htmain "HT Component Guides and Documentation."
+ *
+ * @subpage memmain "MEM Component Guides and Documentation."
+ *
+ * @subpage gnbmain "GNB Component Documentation."
+ *
+ * @subpage idsmain "IDS Component Guides and Documentation."
+ *
+ * @subpage recoverymain "Recovery Component Guides and Documentation."
+ *
+ */
+
+/**
+ * @page starthere Initial Porting and Integration
+ *
+ * @par Basic Check List
+ *
+ * <ul>
+ * <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
+ * AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
+ * <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
+ * and make changes to enable the IDS support desired. It is highly recommended to set the following for
+ * initial integration and development:@n
+ * @code
+ * #define IDSOPT_IDS_ENABLED TRUE
+ * #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ * #define IDSOPT_ASSERT_ENABLED TRUE
+ * @endcode
+ * <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
+ * <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
+ * <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
+ * <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
+ * </ul>
+ *
+ * @par Debugging Using ASSERT and IDS_ERROR_TRAP
+ *
+ * While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
+ * catch and assist debug of wrapper and platform BIOS issues.
+ *
+ * When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
+ * Stop Code.  A Stop Code is eight hex digits.  The first (most significant) four are the FILECODE.
+ * FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro.  Each file has a
+ * unique code value.
+ * The least significant digits are the line number in that file.
+ * For example, 0210 means the macro is on line two hundred ten.
+ * (see ::IdsErrorStop for more details on stop code display.)
+ *
+ * Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
+ * Comments near each macro use will describe the nature of the error and typical wrapper errors or other
+ * root causes.
+ *
+ * After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
+ * OptionsIds.h, except for regression testing.  IDS is not expected to be enabled in production BIOS builds.
+ *
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc
new file mode 100644
index 0000000..1f3ba51
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Makefile.inc
@@ -0,0 +1,532 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+## ABSOLUTE AGESA V5 ROOT PATH ##
+AGESA_ROOT ?= $(PWD)
+
+AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR)
+AGESA_INC += -I$(AGESA_ROOT)
+AGESA_INC += -I$(AGESA_ROOT)/Include
+AGESA_INC += -I$(AGESA_ROOT)/Lib
+AGESA_INC += -I$(AGESA_ROOT)/Legacy
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x15/OR
+AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/Fam10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/Fam15
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/Fam15Mod1x
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/Features
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/NbCommon
+AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/htGraph
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Control
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug/
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x10/HY
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x15/OR
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal/Family/
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal/Family/0x10
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal/Family/0x15/
+AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal/Family/0x15/OR/
+
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/OR
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/C32
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/HY
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/DA
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/PH
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/RB
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
+AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem
+
+
+
+agesa_lib_src  += ./Legacy/Proc/agesaCallouts.c
+agesa_lib_src  += ./Legacy/Proc/Dispatcher.c
+agesa_lib_src  += ./Legacy/Proc/hobTransfer.c
+agesa_lib_src  += ./Lib/amdlib.c
+agesa_lib_src  += ./Lib/helper.c
+agesa_lib_src  += ./Proc/Common/AmdInitEarly.c
+agesa_lib_src  += ./Proc/Common/AmdInitEnv.c
+agesa_lib_src  += ./Proc/Common/AmdInitLate.c
+agesa_lib_src  += ./Proc/Common/AmdInitMid.c
+agesa_lib_src  += ./Proc/Common/AmdInitPost.c
+agesa_lib_src  += ./Proc/Common/AmdInitReset.c
+agesa_lib_src  += ./Proc/Common/AmdInitResume.c
+agesa_lib_src  += ./Proc/Common/AmdLateRunApTask.c
+agesa_lib_src  += ./Proc/Common/AmdS3LateRestore.c
+agesa_lib_src  += ./Proc/Common/AmdS3Save.c
+agesa_lib_src  += ./Proc/Common/CommonInits.c
+agesa_lib_src  += ./Proc/Common/CommonReturns.c
+agesa_lib_src  += ./Proc/Common/CreateStruct.c
+agesa_lib_src  += ./Proc/Common/S3RestoreState.c
+agesa_lib_src  += ./Proc/Common/S3SaveState.c
+agesa_lib_src  += ./Proc/CPU/cahalt.c
+agesa_lib_src  += ./Proc/CPU/cpuApicUtilities.c
+agesa_lib_src  += ./Proc/CPU/cpuBist.c
+agesa_lib_src  += ./Proc/CPU/cpuBrandId.c
+agesa_lib_src  += ./Proc/CPU/cpuEarlyInit.c
+agesa_lib_src  += ./Proc/CPU/cpuEventLog.c
+agesa_lib_src  += ./Proc/CPU/cpuFamilyTranslation.c
+agesa_lib_src  += ./Proc/CPU/cpuGeneralServices.c
+agesa_lib_src  += ./Proc/CPU/cpuInitEarlyTable.c
+agesa_lib_src  += ./Proc/CPU/cpuLateInit.c
+agesa_lib_src  += ./Proc/CPU/cpuMicrocodePatch.c
+agesa_lib_src  += ./Proc/CPU/cpuPostInit.c
+agesa_lib_src  += ./Proc/CPU/cpuPowerMgmt.c
+agesa_lib_src  += ./Proc/CPU/cpuPowerMgmtMultiSocket.c
+agesa_lib_src  += ./Proc/CPU/cpuPowerMgmtSingleSocket.c
+agesa_lib_src  += ./Proc/CPU/cpuWarmReset.c
+agesa_lib_src  += ./Proc/CPU/heapManager.c
+agesa_lib_src  += ./Proc/CPU/S3.c
+agesa_lib_src  += ./Proc/CPU/Table.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuCommonF10Utilities.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandId.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdC32.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdG34.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10CacheDefaults.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10Cpb.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10Dmi.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10EarlyInit.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10HtPhyTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10MsrTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10PciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10PowerCheck.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10PowerPlane.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10Pstate.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10Utilities.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10InitEarlyTable.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10IoCstate.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10PmNbPstateInit.c
+agesa_lib_src  += ./Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuCommonF15Utilities.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15Apm.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15BrandId.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15CacheDefaults.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15Dmi.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15MsrTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15PciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15PowerCheck.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15Utilities.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/F15PstateHpcMode.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrC6State.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrCpb.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrEquivalenceTable.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrIoCstate.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrL3Features.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMsrTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrPciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrPowerMgmtSystemTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrUtilities.c
+agesa_lib_src  += ./Proc/CPU/Family/0x15/OR/F15OrWorkaroundsTable.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuApm.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuC6State.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuCacheFlushOnHalt.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuCacheInit.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuCoreLeveling.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuCpb.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuDmi.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuFeatureLeveling.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuFeatures.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuHwC1e.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuIoCstate.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuL3Features.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuLowPwrPstate.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuMsgBasedC1e.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuPstateGather.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuPstateHpcMode.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuPstateLeveling.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuPstateTables.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuSlit.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuSrat.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuSwC1e.c
+agesa_lib_src  += ./Proc/CPU/Feature/cpuWhea.c
+agesa_lib_src  += ./Proc/CPU/Feature/PreserveMailbox.c
+agesa_lib_src  += ./Proc/HT/htFeat.c
+agesa_lib_src  += ./Proc/HT/htInterface.c
+agesa_lib_src  += ./Proc/HT/htInterfaceCoherent.c
+agesa_lib_src  += ./Proc/HT/htInterfaceGeneral.c
+agesa_lib_src  += ./Proc/HT/htInterfaceNonCoherent.c
+agesa_lib_src  += ./Proc/HT/htMain.c
+agesa_lib_src  += ./Proc/HT/htNb.c
+agesa_lib_src  += ./Proc/HT/htNotify.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbCoherentFam10.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbFam10.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbNonCoherentFam10.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbOptimizationFam10.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbSystemFam10.c
+agesa_lib_src  += ./Proc/HT/Fam10/htNbUtilitiesFam10.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbCoherentFam15.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbFam15.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbNonCoherentFam15.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbOptimizationFam15.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbSystemFam15.c
+agesa_lib_src  += ./Proc/HT/Fam15/htNbUtilitiesFam15.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatDynamicDiscovery.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatGanging.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatNoncoherent.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatOptimization.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatRouting.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatSets.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatSublinks.c
+agesa_lib_src  += ./Proc/HT/Features/htFeatTrafficDistribution.c
+agesa_lib_src  += ./Proc/HT/Features/htIds.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph1.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph2.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph3Line.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph3Triangle.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4Degenerate.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4FullyConnected.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4Kite.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4Line.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4Square.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph4Star.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph5FullyConnected.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph5TwistedLadder.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph6DoubloonLower.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph6DoubloonUpper.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph6FullyConnected.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph6TwinTriangles.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph6TwistedLadder.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph7FullyConnected.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph7TwistedLadder.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph8DoubloonM.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph8FullyConnected.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph8Ladder.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
+agesa_lib_src  += ./Proc/HT/htGraph/htGraph8TwistedLadder.c
+agesa_lib_src  += ./Proc/HT/NbCommon/htNbCoherent.c
+agesa_lib_src  += ./Proc/HT/NbCommon/htNbNonCoherent.c
+agesa_lib_src  += ./Proc/HT/NbCommon/htNbOptimization.c
+agesa_lib_src  += ./Proc/HT/NbCommon/htNbUtilities.c
+agesa_lib_src  += ./Proc/Mem/Ardk/ma.c
+agesa_lib_src  += ./Proc/Mem/Ardk/C32/marc32_3.c
+agesa_lib_src  += ./Proc/Mem/Ardk/C32/mauc32_3.c
+agesa_lib_src  += ./Proc/Mem/Ardk/HY/marhy3.c
+agesa_lib_src  += ./Proc/Mem/Ardk/HY/mauhy3.c
+agesa_lib_src  += ./Proc/Mem/Ardk/OR/maror3.c
+agesa_lib_src  += ./Proc/Mem/Ardk/OR/mauor3.c
+agesa_lib_src  += ./Proc/Mem/Feat/CHINTLV/mfchi.c
+agesa_lib_src  += ./Proc/Mem/Feat/CSINTLV/mfcsi.c
+agesa_lib_src  += ./Proc/Mem/Feat/DMI/mfDMI.c
+agesa_lib_src  += ./Proc/Mem/Feat/ECC/mfecc.c
+agesa_lib_src  += ./Proc/Mem/Feat/ECC/mfemp.c
+agesa_lib_src  += ./Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c
+agesa_lib_src  += ./Proc/Mem/Feat/IDENDIMM/mfidendimm.c
+agesa_lib_src  += ./Proc/Mem/Feat/INTLVRN/mfintlvrn.c
+agesa_lib_src  += ./Proc/Mem/Feat/LVDDR3/mflvddr3.c
+agesa_lib_src  += ./Proc/Mem/Feat/MEMCLR/mfmemclr.c
+agesa_lib_src  += ./Proc/Mem/Feat/NDINTLV/mfndi.c
+agesa_lib_src  += ./Proc/Mem/Feat/ODTHERMAL/mfodthermal.c
+agesa_lib_src  += ./Proc/Mem/Feat/OLSPARE/mfspr.c
+agesa_lib_src  += ./Proc/Mem/Feat/PARTRN/mfParallelTraining.c
+agesa_lib_src  += ./Proc/Mem/Feat/PARTRN/mfStandardTraining.c
+agesa_lib_src  += ./Proc/Mem/Feat/S3/mfs3.c
+agesa_lib_src  += ./Proc/Mem/Feat/TABLE/mftds.c
+agesa_lib_src  += ./Proc/Mem/Main/mdef.c
+agesa_lib_src  += ./Proc/Mem/Main/merrhdl.c
+agesa_lib_src  += ./Proc/Mem/Main/minit.c
+agesa_lib_src  += ./Proc/Mem/Main/mm.c
+agesa_lib_src  += ./Proc/Mem/Main/mmConditionalPso.c
+agesa_lib_src  += ./Proc/Mem/Main/mmEcc.c
+agesa_lib_src  += ./Proc/Mem/Main/mmExcludeDimm.c
+agesa_lib_src  += ./Proc/Mem/Main/mmLvDdr3.c
+agesa_lib_src  += ./Proc/Mem/Main/mmMemClr.c
+agesa_lib_src  += ./Proc/Mem/Main/mmMemRestore.c
+agesa_lib_src  += ./Proc/Mem/Main/mmNodeInterleave.c
+agesa_lib_src  += ./Proc/Mem/Main/mmOnlineSpare.c
+agesa_lib_src  += ./Proc/Mem/Main/mmParallelTraining.c
+agesa_lib_src  += ./Proc/Mem/Main/mmStandardTraining.c
+agesa_lib_src  += ./Proc/Mem/Main/mmUmaAlloc.c
+agesa_lib_src  += ./Proc/Mem/Main/mu.c
+agesa_lib_src  += ./Proc/Mem/Main/muc.c
+agesa_lib_src  += ./Proc/Mem/NB/mn.c
+agesa_lib_src  += ./Proc/Mem/NB/mndct.c
+agesa_lib_src  += ./Proc/Mem/NB/mnfeat.c
+agesa_lib_src  += ./Proc/Mem/NB/mnflow.c
+agesa_lib_src  += ./Proc/Mem/NB/mnmct.c
+agesa_lib_src  += ./Proc/Mem/NB/mnphy.c
+agesa_lib_src  += ./Proc/Mem/NB/mnreg.c
+agesa_lib_src  += ./Proc/Mem/NB/mnS3.c
+agesa_lib_src  += ./Proc/Mem/NB/mntrain3.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mndctc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnflowc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnidendimmc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnmctc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnotc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnParTrainc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnphyc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnprotoc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnregc32.c
+agesa_lib_src  += ./Proc/Mem/NB/C32/mnS3c32.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mndcthy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnflowhy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnhy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnidendimmhy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnmcthy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnothy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnParTrainHy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnphyhy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnprotohy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnreghy.c
+agesa_lib_src  += ./Proc/Mem/NB/HY/mnS3hy.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mndctor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnflowor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnidendimmor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnmctor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnotor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnpartrainor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnphyor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnprotoor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mnregor.c
+agesa_lib_src  += ./Proc/Mem/NB/OR/mns3or.c
+agesa_lib_src  += ./Proc/Mem/Ps/mp.c
+agesa_lib_src  += ./Proc/Mem/Ps/mplribt.c
+agesa_lib_src  += ./Proc/Mem/Ps/mplrnlr.c
+agesa_lib_src  += ./Proc/Mem/Ps/mplrnpr.c
+agesa_lib_src  += ./Proc/Mem/Ps/mpmaxfreq.c
+agesa_lib_src  += ./Proc/Mem/Ps/mpmr0.c
+agesa_lib_src  += ./Proc/Mem/Ps/mpodtpat.c
+agesa_lib_src  += ./Proc/Mem/Ps/mprc10opspd.c
+agesa_lib_src  += ./Proc/Mem/Ps/mprc2ibt.c
+agesa_lib_src  += ./Proc/Mem/Ps/mprtt.c
+agesa_lib_src  += ./Proc/Mem/Ps/mps2d.c
+agesa_lib_src  += ./Proc/Mem/Ps/mpsao.c
+agesa_lib_src  += ./Proc/Mem/Ps/mpseeds.c
+agesa_lib_src  += ./Proc/Mem/Ps/C32/mprc32_3.c
+agesa_lib_src  += ./Proc/Mem/Ps/C32/mpuc32_3.c
+agesa_lib_src  += ./Proc/Mem/Ps/HY/mprhy3.c
+agesa_lib_src  += ./Proc/Mem/Ps/HY/mpshy3.c
+agesa_lib_src  += ./Proc/Mem/Ps/HY/mpuhy3.c
+agesa_lib_src  += ./Proc/Mem/Tech/mt.c
+agesa_lib_src  += ./Proc/Mem/Tech/mthdi.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttdimbt.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttecc.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttEdgeDetect.c
+agesa_lib_src  += ./Proc/Mem/Tech/mtthrc.c
+agesa_lib_src  += ./Proc/Mem/Tech/mtthrcSeedTrain.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttml.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttoptsrc.c
+agesa_lib_src  += ./Proc/Mem/Tech/mttsrc.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mt3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mtlrdimm3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mtot3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mtrci3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mtsdi3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mtspd3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mttecc3.c
+agesa_lib_src  += ./Proc/Mem/Tech/DDR3/mttwl3.c
+agesa_lib_src  += ./Proc/Recovery/HT/htInitRecovery.c
+agesa_lib_src  += ./Proc/Recovery/HT/htInitReset.c
+
+agesa_lib_src  += ./Proc/Mem/Main/mmflow.c
+agesa_lib_src  += ./Proc/Mem/Main/OR/mmflowor.c
+agesa_lib_src  += ./Proc/Mem/Ps/OR/mpor3.c
+ifeq ($(CONFIG_CPU_AMD_SOCKET_C32), y)
+	agesa_lib_src  += ./Proc/Mem/Main/C32/mmflowC32.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/C32/mpLorC3.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/C32/mpRorC3.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/C32/mpUorC3.c
+
+#	agesa_lib_src  += ./Proc/Mem/Main/HY/mmflowhy.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_G34), y)
+	agesa_lib_src  += ./Proc/Mem/Main/HY/mmflowhy.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/G34/mpLorG3.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/G34/mpRorG3.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/G34/mpUorG3.c
+
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMicrocodePatchTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c
+	agesa_lib_src  += ./Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c
+endif
+
+ifeq ($(CONFIG_CPU_AMD_SOCKET_AM3R2), y)
+	agesa_lib_src += ./Proc/Mem/Main/DA/mmflowda.c
+	agesa_lib_src += ./Proc/Mem/Main/RB/mmflowRb.c
+	agesa_lib_src += ./Proc/Mem/Main/PH/mmflowPh.c
+
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/AM3/mpUorA3.c
+	agesa_lib_src  += ./Proc/Mem/Ps/OR/AM3/mpSorA3.c
+
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
+
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhMicrocodePatchTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhEquivalenceTable.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c
+	agesa_lib_src += ./Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c
+
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnidendimmda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnregda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnS3da.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnprotoda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mndctda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnmctda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnflowda.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnParTrainDa.c
+	agesa_lib_src += ./Proc/Mem/NB/DA/mnotda.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnS3Ph.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnflowPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnidendimmPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnmctPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnmctPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnflowPh.c
+	agesa_lib_src += ./Proc/Mem/NB/PH/mnidendimmPh.c
+	agesa_lib_src += ./Proc/Mem/NB/RB/mnidendimmRb.c
+	agesa_lib_src += ./Proc/Mem/NB/RB/mnRb.c
+	agesa_lib_src += ./Proc/Mem/NB/RB/mnflowRb.c
+	agesa_lib_src += ./Proc/Mem/NB/RB/mnS3Rb.c
+
+	agesa_lib_src += ./Proc/Mem/Ardk/DA/masda2.c
+	agesa_lib_src += ./Proc/Mem/Ardk/DA/masda3.c
+	agesa_lib_src += ./Proc/Mem/Ardk/DA/mauda3.c
+	agesa_lib_src += ./Proc/Mem/Ardk/PH/mauPh3.c
+	agesa_lib_src += ./Proc/Mem/Ardk/PH/masph3.c
+	agesa_lib_src += ./Proc/Mem/Ardk/RB/mauRb3.c
+	agesa_lib_src += ./Proc/Mem/Ardk/RB/masRb3.c
+
+	agesa_lib_src += ./Proc/Mem/Ps/DA/mpuda3.c
+	agesa_lib_src += ./Proc/Mem/Ps/DA/mpsda3.c
+	agesa_lib_src += ./Proc/Mem/Ps/DA/mpsda2.c
+	agesa_lib_src += ./Proc/Mem/Ps/PH/mpuph3.c
+	agesa_lib_src += ./Proc/Mem/Ps/PH/mpsph3.c
+	agesa_lib_src += ./Proc/Mem/Ps/RB/mpuRb3.c
+	agesa_lib_src += ./Proc/Mem/Ps/RB/mpsRb3.c
+endif
+
+romstage-y += $(agesa_lib_src)
+ramstage-y += $(agesa_lib_src)
+
+## AGESA need sse feature ##
+AGESA_CFLAGS = -msse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
+
+export AGESA_ROOT
+export AGESA_INC
+export AGESA_CFLAGS
+CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
+
diff --git a/src/vendorcode/amd/agesa/f15/Porting.h b/src/vendorcode/amd/agesa/f15/Porting.h
new file mode 100644
index 0000000..48ac390
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Porting.h
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Describes compiler dependencies - to support several compile time environments
+ *
+ * Contains compiler environment porting descriptions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Includes
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _PORTING_H_
+#define _PORTING_H_
+
+#if defined (_MSC_VER)
+  #include <intrin.h>
+  void _disable (void);
+  void _enable (void);
+  #pragma warning(disable: 4103 4001 4733)
+  #pragma intrinsic (_disable, _enable)
+#pragma warning(push)
+  // -----------------------------------------------------------------------
+  //   Define a code_seg MACRO
+  //
+  #define MAKE_AS_A_STRING(arg) #arg
+
+  #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
+
+  #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
+
+  //#include <intrin.h>  // MS has built-in functions
+
+  #if _MSC_VER < 900
+    // -----------------------------------------------------------------------
+    //    Assume MSVC 1.52C (16-bit)
+    //
+    //    NOTE: When using MSVC 1.52C use the following command line:
+    //
+    //       CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
+    //
+    //    This will produce 32-bit code in USE16 segment that is optimized for code
+    //    size.
+    typedef void          VOID;
+
+    // Create the universal 32, 16, and 8-bit data types
+    typedef unsigned long   UINTN;
+    typedef          long   INT32;
+    typedef unsigned long   UINT32;
+    typedef          int    INT16;
+    typedef unsigned int    UINT16;
+    typedef          char   INT8;
+    typedef unsigned char   UINT8;
+    typedef          char   CHAR8;
+    typedef unsigned short  CHAR16;
+
+    /// struct for 16-bit environment handling of 64-bit value
+    typedef struct _UINT64 {
+      IN OUT  UINT32 lo;      ///< lower 32-bits of 64-bit value
+      IN OUT  UINT32 hi;      ///< highest 32-bits of 64-bit value
+    } UINT64;
+
+    // Create the Boolean type
+    #define TRUE  1
+    #define FALSE 0
+    typedef unsigned char BOOLEAN;
+
+    #define CONST const
+    #define STATIC static
+    #define VOLATILE volatile
+    #define CALLCONV __pascal
+    #define ROMDATA __based( __segname( "_CODE" ) )
+    #define _16BYTE_ALIGN   __declspec(align(16))
+
+    // Force tight packing of structures
+    // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+    #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
+    #pragma pack(1)
+
+    //   Disable WORD->BYTE automatic conversion warnings.  Example:
+    //   BYTE LocalByte;
+    //   void MyFunc(BYTE val);
+    //
+    //   MyFunc(LocalByte*2+1); // Warning, automatic conversion
+    //
+    //   The problem is any time math is performed on a BYTE, it is converted to a
+    //   WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
+    //   is generated.  Disable warning C4761
+    #pragma warning( disable : 4761 )
+
+  #else
+    // -----------------------------------------------------------------------
+    //   Assume a 32-bit MSVC++
+    //
+    // Disable the following warnings:
+    // 4100 - 'identifier' : unreferenced formal parameter
+    // 4276 - 'function' : no prototype provided; assumed no parameters
+    // 4214 - non standard extension used : bit field types other than int
+    // 4001 - nonstandard extension 'single line comment' was used
+    // 4142 - benign redefinition of type for following declaration
+    //      - typedef char    INT8
+    #if defined (_M_IX86)
+      #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
+
+      #ifndef VOID
+        typedef void VOID;
+      #endif
+    // Create the universal 32, 16, and 8-bit data types
+      #ifndef UINTN
+        typedef unsigned __w64 UINTN;
+      #endif
+      typedef          __int64 INT64;
+      typedef unsigned __int64 UINT64;
+      typedef          int   INT32;
+      typedef unsigned int   UINT32;
+      typedef          short INT16;
+      typedef unsigned short UINT16;
+      typedef          char  INT8;
+      typedef unsigned char  UINT8;
+      typedef          char  CHAR8;
+      typedef unsigned short CHAR16;
+
+    // Create the Boolean type
+      #ifndef TRUE
+        #define TRUE  1
+      #endif
+      #ifndef FALSE
+        #define FALSE 0
+      #endif
+      typedef unsigned char BOOLEAN;
+
+      // Force tight packing of structures
+      // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+      #pragma pack(1)
+
+      #define CONST const
+      #define STATIC static
+      #define VOLATILE volatile
+      #define CALLCONV
+      #define ROMDATA
+      #define _16BYTE_ALIGN __declspec(align(64))
+      // 64 bit of compiler
+    #else
+      #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
+
+      #ifndef VOID
+        typedef void VOID;
+      #endif
+      // Create the universal 32, 16, and 8-bit data types
+      #ifndef UINTN
+        typedef unsigned __int64 UINTN;
+      #endif
+      typedef          __int64 INT64;
+      typedef unsigned __int64 UINT64;
+      typedef          int   INT32;
+      typedef unsigned int   UINT32;
+      typedef          short INT16;
+      typedef unsigned short UINT16;
+      typedef          char  INT8;
+      typedef unsigned char  UINT8;
+      typedef          char  CHAR8;
+      typedef unsigned short CHAR16;
+
+      // Create the Boolean type
+      #ifndef TRUE
+        #define TRUE  1
+      #endif
+      #ifndef FALSE
+        #define FALSE 0
+      #endif
+      typedef unsigned char BOOLEAN;
+
+      // Force tight packing of structures
+      // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+      #pragma pack(1)
+
+      #define CONST const
+      #define STATIC static
+      #define VOLATILE volatile
+      #define CALLCONV
+      #define ROMDATA
+    #endif
+  #endif
+  // -----------------------------------------------------------------------
+  // End of MS compiler versions
+
+
+#elif defined __GNUC__
+
+  #define IN
+  #define OUT
+  #define STATIC static
+  #define VOLATILE volatile
+  #define TRUE 1
+  #define FALSE 0
+  #define CONST const
+  #define ROMDATA
+  #define CALLCONV
+  #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
+
+  typedef unsigned char  BOOLEAN;
+  typedef   signed char  INT8;
+  typedef   signed short INT16;
+  typedef   signed long  INT32;
+  typedef unsigned char  CHAR8;
+  typedef unsigned char  UINT8;
+  typedef unsigned short UINT16;
+  typedef unsigned long  UINT32;
+  typedef unsigned long  UINTN;
+  typedef unsigned long  long UINT64;
+  typedef void VOID;
+  //typedef unsigned long  size_t;
+//typedef unsigned int   uintptr_t;
+// Force tight packing of structures
+// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+#pragma pack(1)
+
+  #define CODE_GROUP(arg)
+  #define RDATA_GROUP(arg)
+
+#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
+#define MAKE_AS_A_STRING(arg) #arg
+
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+#include <stddef.h>
+#include "gcc-intrin.h"
+
+#include <assert.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+#ifndef NULL
+  #define NULL              (void *)0
+#endif
+
+#else
+  // -----------------------------------------------------------------------
+  // Unknown or unsupported compiler
+  //
+  #error "Unknown compiler in use"
+#endif
+
+
+
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+
+//Support forward reference construct
+#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
+
+
+// The following are use in conformance to the UEFI style guide
+#define IN
+#define OUT
+
+#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
new file mode 100644
index 0000000..c545373
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Initialize the Family 10h specific way of running early initialization.
+ *
+ * Returns the table of initialization steps to perform at
+ * AmdInitEarly.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GetF10EarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
+extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
+
+CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
+{
+  {McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
+  {LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
+  {NULL, 0}
+};
+
+/*------------------------------------------------------------------------------------*/
+/**
+ * Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
+ * processor that uses the standard initialization steps should take.
+ *
+ *  @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
+ *
+ * @param[in]       FamilyServices    The current Family Specific Services.
+ * @param[out]      Table             Table of appropriate init steps for the executing core.
+ * @param[in]       EarlyParams       Service Interface structure to initialize.
+ * @param[in]       StdHeader         Opaque handle to standard config header.
+ *
+ */
+VOID
+GetF10EarlyInitOnCoreTable (
+  IN       CPU_SPECIFIC_SERVICES                *FamilyServices,
+     OUT   CONST S_PERFORM_EARLY_INIT_ON_CORE   **Table,
+  IN       AMD_CPU_EARLY_PARAMS                 *EarlyParams,
+  IN       AMD_CONFIG_PARAMS                    *StdHeader
+  )
+{
+  *Table = F10EarlyInitOnCoreTable;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
new file mode 100644
index 0000000..904e60b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c
@@ -0,0 +1,300 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 IO C-state feature support functions.
+ *
+ * Provides the functions necessary to initialize the IO C-state feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuFeatures.h"
+#include "cpuIoCstate.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuApicUtilities.h"
+#include "cpuFamilyTranslation.h"
+#include "CommonReturns.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F10IsIoCstateFeatureSupported (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT32                    Socket,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern CPU_FAMILY_SUPPORT_TABLE            IoCstateFamilyServiceTable;
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable IO Cstate on a family 10h CPU.
+ *
+ * @param[in]    IoCstateServices   Pointer to this CPU's IO Cstate family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeIoCstate (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT64                    EntryPoint,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64   LocalMsrRegister;
+  AP_TASK  TaskPtr;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
+    // Initialize MSRC001_0073[CstateAddr] on each core to a region of
+    // the IO address map with 8 consecutive available addresses.
+    LocalMsrRegister = 0;
+
+    ((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
+
+    TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 2;
+    TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable CState on a family 10h core.
+ *
+ * @param[in]    CstateBaseMsr      MSR value to write to C001_0073 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeIoCstateOnCore (
+  IN       VOID *CstateBaseMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  // Initialize MSRC001_0073[CstateAddr] on each core
+  LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the size of CST object
+ *
+ * @param[in]    IoCstateServices   IO Cstate services.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       CstObjSize         Size of CST Object
+ *
+ */
+UINT32
+STATIC
+F10GetAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       PLATFORM_CONFIGURATION    *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  return (CST_HEADER_SIZE + CST_BODY_SIZE);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Routine to generate the C-State ACPI objects
+ *
+ * @param[in]      IoCstateServices       IO Cstate services.
+ * @param[in]      LocalApicId            Local Apic Id for each core.
+ * @param[in, out] **PstateAcpiBufferPtr  Pointer to the Acpi Buffer Pointer.
+ * @param[in]      StdHeader              Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10CreateAcpiCstObj (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT8                     LocalApicId,
+  IN OUT   VOID                      **PstateAcpiBufferPtr,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64            MsrData;
+  CST_HEADER_STRUCT *CstHeaderPtr;
+  CST_BODY_STRUCT   *CstBodyPtr;
+
+  // Read from MSR C0010073 to obtain CstateAddr
+  LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
+  ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
+          (((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
+
+  // Typecast the pointer
+  CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
+
+  // Set CST Header
+  CstHeaderPtr->NameOpcode  = NAME_OPCODE;
+  CstHeaderPtr->CstName_a__ = CST_NAME__;
+  CstHeaderPtr->CstName_a_C = CST_NAME_C;
+  CstHeaderPtr->CstName_a_S = CST_NAME_S;
+  CstHeaderPtr->CstName_a_T = CST_NAME_T;
+
+  // Typecast the pointer
+  CstHeaderPtr++;
+  CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
+
+  // Set CST Body
+  CstBodyPtr->PkgOpcode      = PACKAGE_OPCODE;
+  CstBodyPtr->PkgLength      = CST_LENGTH;
+  CstBodyPtr->PkgElements    = CST_NUM_OF_ELEMENTS;
+  CstBodyPtr->BytePrefix     = BYTE_PREFIX_OPCODE;
+  CstBodyPtr->Count          = CST_COUNT;
+  CstBodyPtr->PkgOpcode2     = PACKAGE_OPCODE;
+  CstBodyPtr->PkgLength2     = CST_PKG_LENGTH;
+  CstBodyPtr->PkgElements2   = CST_PKG_ELEMENTS;
+  CstBodyPtr->BufferOpcode   = BUFFER_OPCODE;
+  CstBodyPtr->BufferLength   = CST_SUBPKG_LENGTH;
+  CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
+  CstBodyPtr->BufferOpcode2  = BUFFER_OPCODE;
+  CstBodyPtr->GdrOpcode      = GENERIC_REG_DESCRIPTION;
+  CstBodyPtr->GdrLength      = CST_GDR_LENGTH;
+  CstBodyPtr->AddrSpaceId    = GDR_ASI_SYSTEM_IO;
+  CstBodyPtr->RegBitWidth    = 0x08;
+  CstBodyPtr->RegBitOffset   = 0x00;
+  CstBodyPtr->AddressSize    = GDR_ASZ_BYTE_ACCESS;
+  CstBodyPtr->RegisterAddr   = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
+  CstBodyPtr->EndTag         = 0x0079;
+  CstBodyPtr->BytePrefix2    = BYTE_PREFIX_OPCODE;
+  CstBodyPtr->Type           = CST_C2_TYPE;
+  CstBodyPtr->WordPrefix     = WORD_PREFIX_OPCODE;
+  CstBodyPtr->Latency        = 0x4B;
+  CstBodyPtr->DWordPrefix    = DWORD_PREFIX_OPCODE;
+  CstBodyPtr->Power          = 0;
+
+  CstBodyPtr++;
+
+  //Update the pointer
+  *PstateAcpiBufferPtr = CstBodyPtr;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Routine to check whether IO Cstate should be supported.
+ *
+ * @param[in]      IoCstateServices      IO Cstate services.
+ * @param[in]      Socket                Zero-based socket number.
+ * @param[in]      StdHeader             Config Handle for library, services.
+ *
+ * @retval         TRUE                  Support IO Cstate.
+ * @retval         FALSE                 Do not support IO Cstate.
+ *
+ */
+BOOLEAN
+F10IsIoCstateFeatureSupported (
+  IN       IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
+  IN       UINT32                    Socket,
+  IN       AMD_CONFIG_PARAMS         *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+  CPUID_DATA     CpuId;
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  // Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
+  // MSR_C001_0073 can be programmed
+  if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
+    LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
+    if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
+      LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader);
+      if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) {
+        return TRUE;
+      }
+    }
+  }
+  return FALSE;
+}
+
+CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
+{
+  0,
+  F10IsIoCstateFeatureSupported,
+  F10InitializeIoCstate,
+  F10GetAcpiCstObj,
+  F10CreateAcpiCstObj,
+  (PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
new file mode 100644
index 0000000..61914a6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c
@@ -0,0 +1,1537 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables from Multi-Link BKDG paragraph recommended settings.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 59564 $   @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10MultiLinkPciRegisters[] =
+{
+  // Function 0
+
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 02h
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      (AMD_F10_ALL & ~AMD_F10_Dx),          // CpuRevision  rev C or less.
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 2
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 9
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x048A9944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 4
+  // 4:0 NpReqCmd: 18
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x04850292,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 16
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502D0,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 3
+  // 17:16 NpReqData: 2
+  // 15:12 ProbeCmd: 8
+  // 11:8 RspCmd: 9
+  // 7:5 PReq: 2
+  // 4:0 NpReqCmd: 4
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x10,                               // address
+      0x008E8944,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x10,                               // address
+      0x008502CF,                         // data
+      0x0FFFFFFF                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+{
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00000000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 1
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_COHERENT,              // link features
+      0x14,                               // address
+      0x02010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      HT_HOST_FEAT_NONCOHERENT,           // link features
+      0x14,                               // address
+      0x00010000,                         // data
+      0x1FFF0000                          // mask
+    }}
+  },
+
+// Function 3 - Misc. Control
+
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// XBAR buffer settings
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 2
+// bits[30:28] IsocRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO(0, 0, 24, FUNC_3, 0x6C),   // Address
+      0x00028052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00051153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10151153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00181111,                           // regData
+      0x00FF7777,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 24
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A18,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090A16,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 23
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                          // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (COUNT_RANGE_LOW, 4) | COUNT_RANGE_NONE),   // 4 or fewer cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090917,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 21
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+// bits[30:28] Xbar2SriFreeListCBInc = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Dx                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),  // greater than 4, ex. 6.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090915,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = A
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | PROCESSOR_RANGE_1 (3, COUNT_RANGE_HIGH)),  // anything but two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A00755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    ProcCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),   // exactly two.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 10
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00A11755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 9
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),     // 2 Socket, half populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00911755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 5
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00511755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 7
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (3, 3) | COUNT_RANGE_NONE),     // 2 Socket, fully populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00711555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = ]
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (2, 2) | COUNT_RANGE_NONE),     // 4 Socket, half populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 2
+// bits[23:20] FreeTok = 2
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00211755,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 1
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 1
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 6
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      (DEGREE_RANGE_0 (4, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),     // 4 Socket, fully populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00611555,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00811756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// All non probe filter configs
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 4
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (COUNT_RANGE_LOW, 1) | DEGREE_RANGE_1 (4, COUNT_RANGE_HIGH)),     // 2 Socket, half populated, or 4 Socket, fully populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000014,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    TokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,              // Features
+      (DEGREE_RANGE_0 (2, 2) | DEGREE_RANGE_1 (3, 3)),     // 2 Socket, fully populated, or 4 Socket, half populated.
+      PACKAGE_TYPE_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 5
+// bits[7:4] ProbeTok = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      PERFORMANCE_PROBEFILTER,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000015,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_GANGED,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x000000AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x00550055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x00550055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_UNGANGED,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x00554055,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000012A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000016A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (COUNT_RANGE_LOW, 1) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x01550155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x01550155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 2
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000022A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 1
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 1
+// bits[7:6] ProbeTok0 = 1
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 1
+// bits[17:16] ReqTok1 = 1
+// bits[19:18] PReqTok1 = 1
+// bits[21:20] RspTok1 = 1
+// bits[23:22] ProbeTok1= 1
+// bits[24] IsocReqTok1 = 1
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (2, 2) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_UNGANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x01554155,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x000001A6,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 1
+// bits[5:4] RspTok0 =1
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (PROCESSOR_RANGE_0 (3, COUNT_RANGE_HIGH) | COUNT_RANGE_NONE),
+      PERFORMANCE_PROBEFILTER,
+      (HT_HOST_AND | HT_HOST_FEAT_COHERENT | HT_HOST_FEAT_GANGED),
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x00000196,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_NFCM) },  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEATURES_ALL,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_NONCOHERENT,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000812A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    HtTokenPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C32_ALL                     // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_MULTI_LINK | AMD_PF_IOMMU) },  // platformFeatures
+    {{
+      (COUNT_RANGE_ALL | COUNT_RANGE_NONE),
+      PERFORMANCE_PROFILE_ALL,
+      HT_HOST_FEAT_COHERENT,
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x000081AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10MultiLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10MultiLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h
new file mode 100644
index 0000000..b8a3fe2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PackageType.h
@@ -0,0 +1,84 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Package Type Definitions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _F10_PACKAGE_TYPE_H_
+#define _F10_PACKAGE_TYPE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+// Below equates are defined to cooperate with LibAmdGetPackageType.
+#define PACKAGE_TYPE_FR2_FR5_FR6            (1 << 0)
+#define PACKAGE_TYPE_AM2R2_AM3              (1 << 1)
+#define PACKAGE_TYPE_S1G3_S1G4              (1 << 2)
+#define PACKAGE_TYPE_G34                    (1 << 3)
+#define PACKAGE_TYPE_ASB2                   (1 << 4)
+#define PACKAGE_TYPE_C32                    (1 << 5)
+
+#define PACKAGE_TYPE_FR2                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR5                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_FR6                    PACKAGE_TYPE_FR2_FR5_FR6
+#define PACKAGE_TYPE_S1G3                   PACKAGE_TYPE_S1G3_S1G4
+#define PACKAGE_TYPE_S1G4                   PACKAGE_TYPE_S1G3_S1G4
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+#endif  // _F10_PACKAGE_TYPE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
new file mode 100644
index 0000000..8c31a4d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c
@@ -0,0 +1,176 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Asymmetric Boost Initialization
+ *
+ * Performs the "BIOS Configuration for Asymmetric Boost" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "F10PmAsymBoostInit.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+SetAsymBoost (
+  IN       VOID *AsymBoostRegister,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the "Asymmetric Boost
+ * Configuration" algorithm.
+ *
+ * The algorithm is as follows:
+ *    // Determine whether the processor support boost
+ *    if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
+ *        Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
+ *        Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
+ *        Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
+ *        Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
+ *        Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
+ *        Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
+ *    }
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmAsymBoostInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  LocalPciRegister;
+  PCI_ADDR                PciAddress;
+  CPUID_DATA              CpuidData;
+
+  // Check if CPB is supported. if yes, skip boosted p-state.
+  LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
+  if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
+    LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
+    if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
+      OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+      // Read F3x10C [Boost Offset]
+      PciAddress.AddressValue = F3x10C_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.DataTransfer.DataSizeInDwords = 1;
+      TaskPtr.DataTransfer.DataPtr = &LocalPciRegister;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+    }
+  }
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set Asymmetric Boost.
+ *
+ * This function set Asymmetric Boost.
+ *
+ * @param[in]  AsymBoostRegister Contains the value of Asymmetric Boost register
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ */
+VOID
+STATIC
+SetAsymBoost (
+  IN       VOID *AsymBoostRegister,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  ControlByte;
+  UINT32 Core;
+  UINT32 Ignored;
+  UINT64 MsrValue;
+  AGESA_STATUS IgnoredSts;
+
+  IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
+  ControlByte = (UINT8) ((Core & 0xFF) * 2);
+  LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
+  // Bits 5:0
+  ((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
+  LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
new file mode 100644
index 0000000..d03d676
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Asymmetric Boost Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_ASYM_BOOST_H_
+#define _CPU_F10_ASYM_BOOST_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmAsymBoostInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_ASYM_BOOST_H_
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
new file mode 100644
index 0000000..0fc1631
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c
@@ -0,0 +1,243 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Dual-plane Only Support
+ *
+ * Performs the "BIOS Configuration for Dual-plane Only Support" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "F10PmDualPlaneOnlySupport.h"
+#include "F10PackageType.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+UINT32
+STATIC
+SetPstateMSR (
+  IN       VOID  *CPB,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
+ *
+ * The algorithm is as follows:
+ *    // Determine whether algorithm applies to this processor
+ *    if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) {
+ *        // Determine whether processor is supported in this infrastructure
+ *        if (((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform))
+ *            || ((F3x1FC[AM3r2Only] == 1) && (this is an AM3r2 platform))) {
+ *            // Fixup the P-state MSRs
+ *            for (each core in the system) {
+ *            if (CPUID Fn8000_0007[CPB]) {
+ *                Copy MSRC001_0065 as MinPstate;
+ *                Copy MSRC001_0068 to MSRC001_0065;
+ *                Copy MinPstate to MSRC001_0068;
+ *            } else {
+ *                Copy MSRC001_0068 to MSRC001_0064;
+ *                Program MSRC001_0068 = 0;
+ *            } // endif
+ *            for (each MSR in MSRC001_00[68:64]) {
+ *                if (value in MSRC001_00[68:64][IddValue] != 0) {
+ *                    Set PstateEn in current MSR to 1;
+ *                } // endif
+ *            } // endfor
+ *        } // endfor
+ *        Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state;
+ *        Set F3xA8[PopDownPstate] = lowest-performance enabled P-state;
+ *        Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state;
+ *        } // endif
+ *    } // endif
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmDualPlaneOnlySupport (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  AP_TASK                 TaskPtr;
+  UINT32                  CPB;
+  UINT32                  Core;
+  UINT32                  Pvimode;
+  UINT32                  LowestPsEn;
+  UINT32                  LocalPciRegister;
+  UINT32                  ActiveCores;
+  UINT32                  ProcessorPackageType;
+  PCI_ADDR                PciAddress;
+  CPUID_DATA              CpuidData;
+  CPU_LOGICAL_ID          LogicalId;
+
+  OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+
+  // get the package type
+  ProcessorPackageType = LibAmdGetPackageType (StdHeader);
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) {
+    PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
+    LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader);
+    if ((((LocalPciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0))
+      || ((LocalPciRegister & 0x04000000) != 0)) {
+      CPB = 0;
+      LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
+      if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
+        CPB = 1;
+      }
+
+      TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR;
+      TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.DataTransfer.DataSizeInDwords = 1;
+      TaskPtr.DataTransfer.DataPtr = &CPB;
+
+      GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
+      for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
+        ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader);
+      }
+      LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
+
+      PciAddress.AddressValue = CPTC2_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = LowestPsEn;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((POPUP_PSTATE_REGISTER *) &LocalPciRegister)->PopDownPstate = LowestPsEn;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      PciAddress.AddressValue = HTC_PCI_ADDR;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = LowestPsEn;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    }
+  }
+}
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set P-State MSR.
+ *
+ * This function set the P-state MSRs per each core in the system.
+ *
+ * @param[in]  CPB               Contains the value of Asymmetric Boost register
+ * @param[in]  StdHeader         Config handle for library and services
+ *
+ * @return         Return the lowest-performance enabled P-state
+ */
+UINT32
+STATIC
+SetPstateMSR (
+  IN       VOID  *CPB,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 dtemp;
+  UINT32 LowestPsEn;
+  UINT64 MsrValue;
+  UINT64 MinMsrValue;
+
+  if (*(UINT32*) CPB != 0) {
+    LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader);
+    LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
+    LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
+    LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader);
+  } else {
+    LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
+    LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
+    MsrValue = 0;
+    LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader);
+  }
+
+  LowestPsEn = 0;
+  for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) {
+    LibAmdMsrRead (dtemp, &MsrValue, StdHeader);
+    if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) {
+      MsrValue = MsrValue | BIT63;
+      LibAmdMsrWrite (dtemp, &MsrValue, StdHeader);
+      LowestPsEn =  dtemp - MSR_PSTATE_0;
+    }
+  }
+  return (LowestPsEn);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
new file mode 100644
index 0000000..53ba399
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h
@@ -0,0 +1,78 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BIOS Configuration for Dual-plane Only Support
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
+#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmDualPlaneOnlySupport (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
new file mode 100644
index 0000000..515484c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c
@@ -0,0 +1,296 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * Performs the "BIOS Northbridge COF and VID Configuration" as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "OptionMultiSocket.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10Utilities.h"
+#include "F10PmNbCofVidInit.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for performing the steps outlined in
+/// the NB COFVID configuration sequence
+typedef struct {
+  UINT8   NewNbVid;           ///< Destination NB VID code
+  BOOLEAN NbVidUpdateAll;     ///< Status of NbVidUpdateAll
+} NB_COF_VID_INIT_WARM;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the "Northbridge COF and
+ * VID Configuration" algorithm.
+ *
+ * The steps are as follows:
+ *    1. Determine if the algorithm is necessary by checking if all NB FIDs
+ *       match in the coherent fabric.  If so, check to see if NbCofVidUpdate
+ *       is zero for all CPUs.  If that is also true, no further steps are
+ *       necessary.  If not + cold reset, proceed to step 2.  If not + warm
+ *       reset, proceed to step 8.
+ *    2. Determine NewNbVid & NewNbFid.
+ *    3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
+ *    4. Copy NewNbVid to P0 NbVid on all local cores.
+ *    5. Transition to P1 on all local cores.
+ *    6. Transition to P0 on local core 0 only.
+ *    7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
+ *    8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
+ *       on all local cores.
+ *    9. Transition to Startup Pstate on all local cores.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  BOOLEAN   PerformNbCofVidCfg;
+  BOOLEAN   NotUsed;
+  BOOLEAN   SystemNbCofsMatch;
+  UINT8     NewNbFid;
+  UINT8     NewNbVid;
+  UINT32    Core;
+  UINT32    SystemNbCof;
+  UINT32    AndMask;
+  UINT32    OrMask;
+  UINT32    Ignored;
+  UINT32    NewNbVoltage;
+  UINT32    FrequencyDivisor;
+  WARM_RESET_REQUEST Request;
+  AP_TASK   TaskPtr;
+  PCI_ADDR  PciAddress;
+  NB_COF_VID_INIT_WARM FunctionData;
+
+  PerformNbCofVidCfg = TRUE;
+  OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
+  if (SystemNbCofsMatch) {
+    if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
+      PerformNbCofVidCfg = FALSE;
+    }
+  }
+  if (PerformNbCofVidCfg) {
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+
+    GetCurrentCore (&Core, StdHeader);
+    ASSERT (Core == 0);
+
+    // get NewNbVid
+    FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
+                                             &CpuEarlyParamsPtr->PlatformConfig,
+                                             &PciAddress,
+                                             (UINT32) 0,
+                                             &Ignored,
+                                             &Ignored,
+                                             &NewNbVoltage,
+                                             StdHeader);
+    ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
+    NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
+    ASSERT (NewNbVid < 0x80);
+
+    if (!(IsWarmReset (StdHeader))) {
+
+      // determine NewNbFid
+      NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
+      TaskPtr.DataTransfer.DataSizeInDwords = 1;
+      TaskPtr.DataTransfer.DataPtr = &NewNbVid;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = 0;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      // Transition core 0 to P0 and wait for change to complete
+      FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
+
+      PciAddress.Address.Register = CPTC0_REG;
+      AndMask = 0xFFFFFFFF;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
+      OrMask = 0x00000000;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
+      ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
+      OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
+
+      // warm reset request
+      GetWarmResetFlag (StdHeader, &Request);
+      Request.RequestBit = TRUE;
+      Request.StateBits = Request.PostStage - 1;
+      SetWarmResetFlag (StdHeader, &Request);
+    } else {
+      // warm reset path
+
+      FunctionData.NewNbVid = NewNbVid;
+      FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
+
+      TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
+      TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
+      TaskPtr.DataTransfer.DataPtr = &FunctionData;
+      TaskPtr.DataTransfer.DataTransferFlags = 0;
+      TaskPtr.ExeFlags = WAIT_FOR_CORE;
+      ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+    }
+  } // skip whole algorithm
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Cold reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 3, 4, & 5 on each core.
+ *
+ * @param[in]  NewNbVid           NewNbVid determined by core 0 in step 2.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitP0P1Core (
+  IN       VOID *NewNbVid,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT8  NumBoostStates;
+  UINT32 MsrAddress;
+  UINT64 LocalMsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+  MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE);
+  LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
+  LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader);
+  ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid;
+  LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader);
+  FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Warm reset support routine for F10PmNbCofVidInit.
+ *
+ * This function implements steps 8 & 9 on each core.
+ *
+ * @param[in]  FunctionData       Contains NewNbVid determined by core 0 in step
+ *                                2, and NbVidUpdateAll.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbCofVidInitWarmCore (
+  IN       VOID *FunctionData,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 LocalMsrRegister;
+  CPU_SPECIFIC_SERVICES *FamilySpecificServices;
+
+  GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+  for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) {
+      if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
+        ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
+        LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
+      }
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
new file mode 100644
index 0000000..94aad6d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h
@@ -0,0 +1,77 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 NB COF VID Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
+#define _CPU_F10_PM_NB_COF_VID_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbCofVidInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_COF_VID_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
new file mode 100644
index 0000000..bf3f4bd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c
@@ -0,0 +1,185 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 NB Pstate Initialization
+ *
+ * Performs the action described in F3x1F0[NbPstate] as
+ * described in the BKDG.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuApicUtilities.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PmNbPstateInit.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+/// Structure used for modifying the P-state
+/// MSRs on fuse enable CPUs.
+typedef struct {
+  UINT8   NbVid1;             ///< Destination NB VID code
+  UINT8   NbPstate;           ///< Status of NbVidUpdateAll
+} NB_PSTATE_INIT;
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Family 10h core 0 entry point for performing the actions described in the
+ * description of F3x1F0[NbPstate].
+ *
+ * If F3x1F0[NbPstate] is non zero, it specifies the highest performance
+ * P-state in which to enable NbDid.  Each core must loop through their
+ * P-state MSRs, enabling NbDid and changing NbVid to a lower voltage.
+ *
+ * @param[in]  FamilySpecificServices  The current Family Specific Services.
+ * @param[in]  CpuEarlyParamsPtr       Service related parameters (unused).
+ * @param[in]  StdHeader               Config handle for library and services.
+ *
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  )
+{
+  UINT32         Core;
+  UINT32         LocalPciRegister;
+  AP_TASK        TaskPtr;
+  PCI_ADDR       PciAddress;
+  NB_PSTATE_INIT ApParams;
+
+  if (FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, &CpuEarlyParamsPtr->PlatformConfig, StdHeader)) {
+    if (CpuEarlyParamsPtr->PlatformConfig.PlatformProfile.PlatformPowerPolicy == BatteryLife) {
+      OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+      GetCurrentCore (&Core, StdHeader);
+      ASSERT (Core == 0);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = 0x1F0;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if ((LocalPciRegister & 0x00070000) != 0) {
+        ApParams.NbPstate = (UINT8) ((LocalPciRegister & 0x00070000) >> 16);
+        ASSERT (ApParams.NbPstate < NM_PS_REG);
+
+        PciAddress.Address.Function = FUNC_4;
+        PciAddress.Address.Register = 0x1F4;
+        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+        ApParams.NbVid1 = (UINT8) ((LocalPciRegister & 0x00003F80) >> 7);
+
+        TaskPtr.FuncAddress.PfApTaskI = PmNbPstateInitCore;
+        TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_PSTATE_INIT);
+        TaskPtr.DataTransfer.DataPtr = &ApParams;
+        TaskPtr.DataTransfer.DataTransferFlags = 0;
+        TaskPtr.ExeFlags = WAIT_FOR_CORE;
+        ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
+
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Support routine for F10PmNbPstateInit.
+ *
+ * This function modifies NbVid and NbDid on each core.
+ *
+ * @param[in]  NbPstateParams     Appropriate NbVid1 and NbPstate as determined by core 0.
+ * @param[in]  StdHeader          Config handle for library and services.
+ *
+ */
+VOID
+STATIC
+PmNbPstateInitCore (
+  IN       VOID *NbPstateParams,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 MsrAddress;
+  UINT64 LocalMsrRegister;
+
+  for (MsrAddress = (PS_REG_BASE + ((NB_PSTATE_INIT *) NbPstateParams)->NbPstate); MsrAddress <= PS_MAX_REG; MsrAddress++) {
+    LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
+    if (((PSTATE_MSR *) &LocalMsrRegister)->PsEnable == 1) {
+      ((PSTATE_MSR *) &LocalMsrRegister)->NbDid = 1;
+      ((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_PSTATE_INIT *) NbPstateParams)->NbVid1;
+      LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
+    }
+  }
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
new file mode 100644
index 0000000..1701ee4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h
@@ -0,0 +1,77 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 NB P-State Initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _CPU_F10_PM_NB_PSTATE_INIT_H_
+#define _CPU_F10_PM_NB_PSTATE_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+VOID
+F10PmNbPstateInit (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       AMD_CPU_EARLY_PARAMS  *CpuEarlyParamsPtr,
+  IN       AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#endif  // _CPU_F10_PM_NB_PSTATE_INIT_H_
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
new file mode 100644
index 0000000..7a3a3ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/F10SingleLinkPciTables.c
@@ -0,0 +1,2251 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 PCI tables in Recommended Settings for Single Link Processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 59564 $   @e \$Date: 2011-09-26 12:33:51 -0600 (Mon, 26 Sep 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10SingleLinkPciRegisters[] =
+{
+// F0x68 - Link Transaction Control
+// bit[14:13], BufPriRel = 01b
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                     // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00002000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x00000000,                           // regData
+      0x01000000,                           // regMask
+    }}
+  },
+// F0x68 - Link Transaction Control
+// bit[24], DispRefModeEn = 1 for UMA, but can only set it on the warm reset.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {AMD_PF_UMA},                     // platform Features
+    {{
+      PERFORMANCE_IS_WARM_RESET,
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68),  // Address
+      0x01000000,                           // regData
+      0x01000000,                           // regMask
+    }}
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 4
+  // 4:0 NpReqCmd: 18
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x04850292,                           // Data
+      0x0FFFFFFF                            // Mask
+    }},
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 4
+  // 4:0 NpReqCmd: 18
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x04850292,                           // Data
+      0x0FFFFFFF                            // Mask
+    }},
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 3
+  // 4:0 NpReqCmd: 11
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x0485026B,                           // Data
+      0x0FFFFFFF                            // Mask
+    }},
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 2
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x008502CF,                           // Data
+      0x0FFFFFFF                            // Mask
+    }},
+  },
+  // F0x[F0,D0,B0,90] Link Base Buffer Count Register
+  // 27:25 FreeData: 0
+  // 24:20 FreeCmd: 8
+  // 19:18 RspData: 1
+  // 17:16 NpReqData: 1
+  // 15:12 ProbeCmd: 0
+  // 11:8 RspCmd: 2
+  // 7:5 PReq: 6
+  // 4:0 NpReqCmd: 15
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x10,                                 // Address
+      0x808502CF,                           // Data
+      0x0FFFFFFF                            // Mask
+    }},
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00000000,                           // Data
+      0x1FFF0000                            // Mask
+    }},
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 0
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00000000,                           // Data
+      0x1FFF0000                            // Mask
+    }},
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 1
+  // 18:16 IsocNpReqCmd: 7
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x000F0000,                           // Data
+      0x1FFF0000                            // Mask
+    }},
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00010000,                           // Data
+      0x1FFF0000                            // Mask
+    }},
+  },
+  // F0x[F4,D4,B4,94] Link Base Buffer Count Register
+  // 28:27 IsocRspData: 0
+  // 26:25 IsocNpReqData: 0
+  // 24:22 IsocRspCmd: 0
+  // 21:19 IsocPReq: 0
+  // 18:16 IsocNpReqCmd: 1
+  {
+    HtHostPciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },
+    {{
+      HT_HOST_FEATURES_ALL,                 // Link Features
+      0x14,                                 // Address
+      0x00010000,                           // Data
+      0x1FFF0000                            // Mask
+    }},
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// bit[8] LS2En = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_ALL                           // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                     // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000100,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 10b
+// bits[31:28] MctVarPriCntLmt = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x00002000,                           // regData
+      0xF0003000,                           // regMask
+    }}
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 00b
+// bits[31:28] MctVarPriCntLmt = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },        // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x00000000,                           // regData
+      0xF0000000,                           // regMask
+    }}
+  },
+// F2x118 - Memory Controller Configuration Low Register
+// bits[13:12] MctPriIsoc = 11b
+// bits[31:28] MctVarPriCntLmt = 1
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },       // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x118),  // Address
+      0x10003000,                           // regData
+      0xF0003000,                           // regMask
+    }}
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32  0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }}
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 0
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000000,                           // regData
+      0x00000400,                           // regMask
+    }}
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x90),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }}
+  },
+// F2x[1,0]90 - DRAM Configuration Low Register
+// bits [10] BurstLength32 = 1
+// It is okay to write both channels, if one is disabled, this bit has no effect on that channel.
+// If the channels are ganged for 128 bit operation, the memory init code will resolve any conflict with this setting.
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA | AMD_PF_UMA_IFCM) },        // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x190),  // Address
+      0x00000400,                           // regData
+      0x00000400,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x00018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 1
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x60018051,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x6C - Data Buffer Control
+// bits[2:0]   UpReqDBC = 2
+// bits[5:4]   DnReqDBC = 1
+// bits[7:6]   DnRspDBC = 1
+// bit[15]     DatBuf24 = 1
+// bits[18:16] UpRspDBC = 1
+// bits[30:28] IsocRspDBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x6C),  // Address
+      0x10018052,                           // regData
+      0x700780F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x00041153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 2
+// bits[22:20] IsocReqCBC = 2
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x61221151,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 4
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[30:28] IsocRspCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x11141153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x70 - SRI_to_XBAR Command Buffer Count
+// bits[2:0]   UpReqCBC = 3
+// bits[5:4]   DnReqCBC = 1
+// bits[7:6]   DnRspCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[18:16] UpRspCBC = 5
+// bits[22:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[30:28] IsocRspCBC = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70),  // Address
+      0x10151153,                           // regData
+      0x777777F7,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 0
+// bits[26:24] IsocPreqCBC = 0
+// bits[31:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00081111,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 9
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x91180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 1
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC =1
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 0
+// bits[31:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x00181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 8
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,  // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x81180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 8
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,  // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x81180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 7
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,  // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x71180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 7
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,  // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x71180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = C
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xC1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = B
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xB1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = A
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xA1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = B
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xB1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = A
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xA1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = F
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xF1181111,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = B
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xB1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = B
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xB1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = A
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xA1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = A
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xA1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = E
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xE1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = E
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xE1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = D
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xD1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 1
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = D
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) }, // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6-cores
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0xD1180101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+
+// F3x74 - XBAR_to_SRI Command Buffer Count
+// bits[2:0]   UpReqCBC = 1
+// bits[6:4]   DnReqCBC = 0
+// bits[10:8]  UpPreqCBC = 1
+// bits[14:12] DnPreqCBC = 0
+// bits[19:16] ProbeCBC = 8
+// bits[23:20] IsocReqCBC = 8
+// bits[26:24] IsocPreqCBC = 1
+// bits[31:28] DRReqCBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) }, // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74),  // Address
+      0x01880101,                           // regData
+      0xF7FF7777,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080C,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 9
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070809,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 17
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070811,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20
+// bits[11:8] Sri2XbarFreeXreqCBC = 9
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 9
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00090914,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 14
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080E,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 14
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080E,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 13
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080D,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// No Mct Variable Priority or 32 byte requests.
+// bits[4:0]  Xbar2SriFreeListCBC = 13
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080D,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 11
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080B,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 11
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080B,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 10
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080A,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 10
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_MCT_ISOC_VARIABLE,        // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080A,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 8
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070808,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 8
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070808,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 7
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B,              // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070807,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 7
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_REFRESH_REQUEST_32B ,              // Features
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070807,                           // regData
+      0x007FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 16
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE),  // 5 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x00070810,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 15
+// bits[11:8] Sri2XbarFreeXreqCBC = 8
+// bits[15:12] Sri2XbarFreeRspCBC = 0
+// bits[19:16] Sri2XbarFreeXreqDBC = 7
+// bits[22:20] Sri2XbarFreeRspDBC = 0
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      PERFORMANCE_PROFILE_ALL,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE),  // 6 cores.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),  // Address
+      0x0007080F,                           // regData
+      0x707FFF1F,                           // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 22, 1-core without L3 cache is 22
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (1, 1) | COUNT_RANGE_NONE), // 1 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000016,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 20, 2-core is 20
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (2, 2) | COUNT_RANGE_NONE), // 2 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000014,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 18, 3-core without L3 cache is 18.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (3, 3) | COUNT_RANGE_NONE), // 3 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000012,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 4-core without L3 cache is 16.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (4, 4) | COUNT_RANGE_NONE), // 4 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x00000010,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 14, 5-core without L3 cache is 14.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (5, 5) | COUNT_RANGE_NONE), // 5 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000E,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x7C - Free List Buffer Count
+// bits[4:0]  Xbar2SriFreeListCBC = 12, 6-core without L3 cache is 12.
+  {
+    CoreCountsPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      PERFORMANCE_NO_L3_CACHE,
+      (CORE_RANGE_0 (6, 6) | COUNT_RANGE_NONE), // 6 core.
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C),      // Address
+      0x0000000C,                               // regData
+      0x0000001F,                               // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 0
+// bits[15:14] IsocPreqTok = 0
+// bits[17:16] IsocRspTok = 0
+// bits[23:20] FreeTok = 8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00800756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 2
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 3
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 3
+// bits[23:20] FreeTok = 12
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00C37656,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x140 - SRI_to_XCS Token Count
+// bits[1:0] UpReqTok = 2
+// bits[3:2] DnReqTok = 1
+// bits[5:4] UpPreqTokC = 1
+// bits[7:6] DnPreqTok = 1
+// bits[9:8] UpRspTok = 3
+// bits[11:10] DnRspTok = 1
+// bits[13:12] IsocReqTok = 1
+// bits[15:14] IsocPreqTok = 1
+// bits[17:16] IsocRspTok = 1
+// bits[23:20] FreeTok = 8
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
+      0x00815756,                           // regData
+      0x00F3FFFF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 6
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000036,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x144 - MCT to XCS Token Count
+// bits[3:0] RspTok = 3
+// bits[7:4] ProbeTok = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
+      0x00000033,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_NFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000052A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 0
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 2
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_UMA_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x8000052A,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 2
+// bits[9:8] IsocReqTok0 = 0
+// bits[11:10] IsocPreqTok0 = 0
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 3
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 0
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IFCM) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0000C0AA,                           // regData
+      0xD5FFFFFF,                           // regMask
+    }}
+  },
+// F3x148 - Link to XCS Token Count
+// bits[1:0] ReqTok0 = 2
+// bits[3:2] PReqTok0 = 2
+// bits[5:4] RspTok0 = 2
+// bits[7:6] ProbeTok0 = 0
+// bits[9:8] IsocReqTok0 = 1
+// bits[11:10] IsocPreqTok0 = 1
+// bits[13:12] IsocRspTok0 = 0
+// bits[15:14] FreeTok[1:0] = 2
+// bits[17:16] ReqTok1 = 0
+// bits[19:18] PReqTok1 = 0
+// bits[21:20] RspTok1 = 0
+// bits[23:22] ProbeTok1= 3
+// bits[24] IsocReqTok1 = 0
+// bits[25] IsocPreqTok1 = 0
+// bits[28] IsocRspTok1 = 0
+// bits[31:30] FreeTok[3:2] = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_AND | AMD_PF_SINGLE_LINK | AMD_PF_IOMMU) },  // platform Features
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
+      0x0500852A,                           // regData
+      0xC000FFFF,                           // regMask
+    }}
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_NFCM | AMD_PF_IFCM | AMD_PF_IOMMU) },
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000000,
+      0x0000000F
+    }}
+  },
+  // F3x158 - Link to XCS Token Count Registers
+  // bits [3:0]LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_ALL                         // CpuRevision
+    },
+    { (AMD_PF_UMA_IFCM | AMD_PF_UMA) },
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,
+      0x0000000F
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10SingleLinkPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10SingleLinkPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
new file mode 100644
index 0000000..ad3b28f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c
@@ -0,0 +1,151 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to initialize Cache Flush On Halt feature for Family 10h BL.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/BL
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "cpuFeatures.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable BL-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       EntryPoint               Timepoint designator.
+ *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
+ *    @param[in]       StdHeader                Config Handle for library, services.
+ */
+VOID
+SetF10BlCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32       AndMask;
+  UINT32       OrMask;
+  UINT32       CoreCount;
+  PCI_ADDR     PciAddress;
+  CPU_LOGICAL_ID        CpuFamilyRevision;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
+    GetLogicalIdOfCurrentCore (&CpuFamilyRevision, StdHeader);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+    if (CpuFamilyRevision.Revision == AMD_F10_BL_C3) {
+      // F3xDC[25:19] = 04h
+      // F3xDC[18:16] = 111b
+      AndMask = 0xFC00FFFF;
+      OrMask = 0x00270000;
+    } else {
+      // F3xDC[25:19] = 28h
+      // F3xDC[18:16] = 111b
+      AndMask = 0xFC00FFFF;
+      OrMask = 0x01470000;
+
+      //For BL_C2 single Core, F3xDC[18:16] = 0
+      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+      if (CoreCount == 1) {
+        if (CpuFamilyRevision.Revision == AMD_F10_BL_C2) {
+          OrMask = 0x01400000;
+        }
+      }
+    }
+
+    // Get the Or Mask value from IDS
+    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); //F3xDC
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt =
+{
+  0,
+  SetF10BlCacheFlushOnHaltRegister
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
new file mode 100644
index 0000000..cbbb43f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlEquivalenceTable.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10BlMicrocodeEquivalenceTable[] =
+{
+  0x1052, 0x1041,
+  0x1053, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10BlMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *BlEquivalenceTablePtr = CpuF10BlMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
new file mode 100644
index 0000000..3f1b5dd
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c
@@ -0,0 +1,122 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT  Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlHtPhyRegisters[] =
+{
+
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+//
+// Deemphasis Settings
+//
+
+// For BL-C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_BL_C3                         // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
new file mode 100644
index 0000000..ed0ad17
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10BlLogicalIdAndRevArray[] =
+{
+  {
+    0x1052,
+    AMD_F10_BL_C2
+  },
+  {
+    0x1053,
+    AMD_F10_BL_C3
+  }
+};
+
+VOID
+GetF10BlLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **BlIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *BlIdPtr = CpuF10BlLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_BL;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10BlLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10BlLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10BlLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
new file mode 100644
index 0000000..4cf0507
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMicrocodePatchTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[];
+extern CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches;
+
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  BlUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10BlMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **BlUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = CpuF10BlNumberOfMicrocodePatches;
+  *BlUcodePtr = &CpuF10BlMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
new file mode 100644
index 0000000..b56d290
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10BlMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10BlMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10BlMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
new file mode 100644
index 0000000..e6c15cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c
@@ -0,0 +1,196 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 BL PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10BlPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[9] RXCalEn = 1
+// bit[5:0] T0Time = 0x26
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                      // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C226,                           // regData
+      0x0000E23F,                           // regMask
+    }}
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C2                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+
+
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] NbCofChg = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_Cx                       // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_BL_C3                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10BlPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10BlPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
new file mode 100644
index 0000000..4ca87cb
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c
@@ -0,0 +1,144 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Cache Flush On Halt Function.
+ *
+ * Contains code to initialize Cache Flush On Halt feature for Family 10h DA.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/DA
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *----------------------------------------------------------------------------
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuPostInit.h"
+#include "cpuFeatures.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          P U B L I C     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *    Enable DA-C Cpu Cache Flush On Halt Function
+ *
+ *    @param[in]       FamilySpecificServices   The current Family Specific Services.
+ *    @param[in]       EntryPoint               Timepoint designator.
+ *    @param[in]       PlatformConfig           Contains the runtime modifiable feature input data.
+ *    @param[in]       StdHeader                Config Handle for library, services.
+ */
+VOID
+SetF10DaCacheFlushOnHaltRegister (
+  IN       CPU_CFOH_FAMILY_SERVICES     *FamilySpecificServices,
+  IN       UINT64                       EntryPoint,
+  IN       PLATFORM_CONFIGURATION       *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS            *StdHeader
+  )
+{
+  UINT32       CoreCount;
+  UINT32       AndMask;
+  UINT32       OrMask;
+  PCI_ADDR     PciAddress;
+  CPU_LOGICAL_ID LogicalId;
+
+  if ((EntryPoint & CPU_FEAT_AFTER_POST_MTRR_SYNC) != 0) {
+    // F3xDC[25:19] = 04h
+    // F3xDC[18:16] = 111b
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = CLOCK_POWER_TIMING_CTRL2_REG;
+    AndMask = 0xFC00FFFF;
+    OrMask = 0x00270000;
+
+    GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+    if (LogicalId.Revision == AMD_F10_DA_C2) {
+      //For DA_C2 single Core, F3xDC[18:16] = 0
+      GetActiveCoresInCurrentSocket (&CoreCount, StdHeader);
+      if (CoreCount == 1) {
+        OrMask = 0x00200000;
+      }
+    }
+
+    IDS_OPTION_HOOK (IDS_CACHE_FLUSH_HLT, &OrMask, StdHeader);
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xDC
+  }
+}
+
+CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt =
+{
+  0,
+  SetF10DaCacheFlushOnHaltRegister
+};
\ No newline at end of file
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
new file mode 100644
index 0000000..4405135
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaEquivalenceTable.c
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10DaMicrocodeEquivalenceTable[] =
+{
+  0x1062, 0x1062,
+  0x1063, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10DaMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *DaEquivalenceTablePtr = CpuF10DaMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
new file mode 100644
index 0000000..ca135db
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c
@@ -0,0 +1,283 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaHtPhyRegisters[] =
+{
+
+//
+// Deemphasis Settings
+//
+
+// For DA, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C2                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
new file mode 100644
index 0000000..b828ff4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c
@@ -0,0 +1,107 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10DaLogicalIdAndRevArray[] =
+{
+  {
+    0x1062,
+    AMD_F10_DA_C2
+  },
+  {
+    0x1063,
+    AMD_F10_DA_C3
+  }
+};
+
+VOID
+GetF10DaLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **DaIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *DaIdPtr = CpuF10DaLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_DA;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10DaLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10DaLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10DaLogicalIdAndRevArray
+//};
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
new file mode 100644
index 0000000..2e77327
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMicrocodePatchTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G2_PEI)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[];
+extern CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  DaUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10DaMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **DaUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = CpuF10DaNumberOfMicrocodePatches;
+  *DaUcodePtr = &CpuF10DaMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
new file mode 100644
index 0000000..261f432a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10DaMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+//
+// NOTE: This entry is here for making this array not to be empty.
+//       This entry should be removed after adding another.
+//
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10DaMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10DaMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
new file mode 100644
index 0000000..45e9194
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c
@@ -0,0 +1,192 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 DA PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10DaPciRegisters[] =
+{
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[9] RXCalEn = 1
+// bit[5:0] T0Time = 0x26
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C226,                           // regData
+      0x0000E23F,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI FIDVID Change
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 0
+// bits[3] NbCofChg = 1
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 0
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      HT_HOST_FEATURES_ALL,                 // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x000B0000,                           // regData
+      0x00FF0000,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 1
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000800,                           // regData
+      0x10003800,                           // regMask
+    }}
+  },
+// F3xD4 - Clock Power/Timing Control 0 Register
+// bits[30:28] NbClkDiv = 5
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_C2                       // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      HT_HOST_FEAT_HT3,                     // link feats
+      PACKAGE_TYPE_S1G3_S1G4,               // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4),  // Address
+      0x50000000,                           // regData
+      0x70000000,                           // regMask
+    }}
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bits[4] EnStpGntOnFlushMaskWakeup = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_DA_Cx                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00000010,                           // regData
+      0x00000010,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10DaPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10DaPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
new file mode 100644
index 0000000..414c716
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c
@@ -0,0 +1,1037 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 01000085 for 1040 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 01000085 for 1040 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085 =
+{{
+0x08,
+0x20,
+0x01,
+0x05,
+0x85,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xc1,
+0xb9,
+0x5d,
+0x3d,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x40,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x2f,
+0x02,
+0x00,
+0x00,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xcf,
+0xf8,
+0xff,
+0x2a,
+0xc3,
+0x3f,
+0xd5,
+0xfd,
+0xbc,
+0xff,
+0xff,
+0xb3,
+0x0f,
+0xff,
+0x58,
+0xd5,
+0xf0,
+0x35,
+0x95,
+0x03,
+0x1d,
+0xf8,
+0x63,
+0x7b,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x80,
+0x77,
+0xff,
+0x7f,
+0xfe,
+0xe1,
+0x98,
+0x8a,
+0x54,
+0xfe,
+0xaf,
+0xff,
+0xff,
+0x87,
+0x7f,
+0xa9,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x1f,
+0xc0,
+0x65,
+0xf4,
+0x0d,
+0xf0,
+0xe0,
+0x8f,
+0xfe,
+0x04,
+0xde,
+0x04,
+0x03,
+0xad,
+0xc3,
+0x2f,
+0xfe,
+0xa9,
+0xfc,
+0x07,
+0x00,
+0x3f,
+0x0f,
+0xff,
+0x15,
+0x00,
+0xb0,
+0x00,
+0xf8,
+0xaf,
+0xe4,
+0x3f,
+0x07,
+0xf8,
+0x79,
+0xf8,
+0xfe,
+0xff,
+0x97,
+0xa7,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0xbf,
+0xf1,
+0x00,
+0xfe,
+0x7f,
+0x6f,
+0x80,
+0x03,
+0x4a,
+0x1a,
+0x00,
+0xc8,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xc3,
+0x3f,
+0x80,
+0x7f,
+0xfc,
+0x7f,
+0x0f,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x03,
+0x00,
+0xff,
+0xdf,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xcf,
+0x56,
+0x0e,
+0x80,
+0xe0,
+0x0f,
+0xe8,
+0x75,
+0xf6,
+0xff,
+0xff,
+0x00,
+0xc3,
+0xbb,
+0x16,
+0xf2,
+0x04,
+0x37,
+0xf8,
+0x13,
+0x0e,
+0x7f,
+0x0c,
+0xb8,
+0xe0,
+0xdc,
+0x35,
+0x00,
+0x60,
+0xff,
+0xff,
+0x1f,
+0x7f,
+0x78,
+0xc7,
+0xa2,
+0x95,
+0xff,
+0xe9,
+0x3f,
+0xdf,
+0xe0,
+0xcf,
+0x2a,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0xff,
+0xf2,
+0xbf,
+0xff,
+0xfd,
+0x1f,
+0xfc,
+0x7b,
+0x0f,
+0xc0,
+0x23,
+0xd0,
+0xed,
+0xf5,
+0xe0,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfe,
+0x03,
+0xf9,
+0x5f,
+0x01,
+0x7e,
+0x1e,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x4c,
+0x06,
+0x00,
+0xbc,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
new file mode 100644
index 0000000..8bda08c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c
@@ -0,0 +1,1037 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c6 for 1041 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c6 for 1041 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6 =
+{{
+0x10,
+0x20,
+0x11,
+0x03,
+0xc6,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xb5,
+0x66,
+0x0e,
+0x84,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x41,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0xa0,
+0x09,
+0x00,
+0x00,
+0xa5,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xa1,
+0x09,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x97,
+0xd1,
+0x7f,
+0x00,
+0x83,
+0x3f,
+0x36,
+0xc0,
+0xa0,
+0x1b,
+0xf8,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb4,
+0xf2,
+0x1f,
+0xf8,
+0xa7,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0x40,
+0x03,
+0x54,
+0x00,
+0x92,
+0xff,
+0xe0,
+0xbf,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x5f,
+0x9e,
+0xfa,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x03,
+0xf8,
+0xff,
+0xc6,
+0x01,
+0x0e,
+0xfc,
+0xbd,
+0x00,
+0xa0,
+0x2a,
+0x69,
+0x0e,
+0x40,
+0xbd,
+0x55,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x00,
+0xe0,
+0xff,
+0x13,
+0xf2,
+0xc3,
+0xbb,
+0xff,
+0x8b,
+0xf8,
+0xff,
+0x44,
+0x59,
+0x0e,
+0x7f,
+0x34,
+0x00,
+0x00,
+0x5a,
+0xfb,
+0x07,
+0xe0,
+0xfb,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0xfe,
+0x7f,
+0x94,
+0x9b,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xe8,
+0xff,
+0x8c,
+0x07,
+0xf0,
+0xf4,
+0x43,
+0xf9,
+0x3c,
+0x7e,
+0x33,
+0x0e,
+0xc0,
+0xd0,
+0x0f,
+0xe5,
+0xf3,
+0xf7,
+0xcb,
+0x38,
+0x00,
+0x43,
+0x3f,
+0x94,
+0xcf,
+0x1c,
+0x9c,
+0x0c,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x03,
+0xf4,
+0xff,
+0xff,
+0xc8,
+0x0f,
+0xef,
+0x52,
+0x4f,
+0xf0,
+0xbf,
+0xe0,
+0xe0,
+0x3a,
+0xfc,
+0x31,
+0x0f,
+0xc0,
+0xd3,
+0xd5,
+0x0c,
+0x70,
+0xe0,
+0xcf,
+0x03,
+0x00,
+0x5c,
+0x56,
+0x7f,
+0x00,
+0xae,
+0x97,
+0x6c,
+0x80,
+0x03,
+0x7f,
+0xfe,
+0x01,
+0x78,
+0x6e,
+0xb1,
+0x01,
+0x0e,
+0xfc,
+0xf9,
+0x07,
+0xe0,
+0xf7,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0x8b,
+0x01,
+0x00,
+0x61,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xfb,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfd,
+0x6b,
+0x00,
+0xa0,
+0xff,
+0xfe,
+0xff,
+0xcb,
+0xf0,
+0xef,
+0xf5,
+0x7f,
+0x8f,
+0x40,
+0x3f,
+0x00,
+0x83,
+0xbf,
+0xb7,
+0xd7,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe4,
+0x7f,
+0xf9,
+0x0f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x00,
+0xf0,
+0x32,
+0x19,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x1f,
+0xc0,
+0x7f,
+0xe0,
+0xe0,
+0xdf,
+0xf0,
+0x0f,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0x7f,
+0xe0,
+0x1f,
+0xc0,
+0xf0,
+0x0f,
+0xe0,
+0xdf,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
new file mode 100644
index 0000000..3f1ec05
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c
@@ -0,0 +1,1037 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c7 for 1062 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c7 for 1062 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7 =
+{{
+0x10,
+0x20,
+0x11,
+0x03,
+0xc7,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0xb8,
+0x53,
+0x63,
+0x1d,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x62,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x9a,
+0x0b,
+0x00,
+0x00,
+0x16,
+0x0c,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x6f,
+0x58,
+0x39,
+0x00,
+0x81,
+0x3f,
+0xa0,
+0xd7,
+0x04,
+0x00,
+0xfc,
+0xb7,
+0x0f,
+0xff,
+0x58,
+0xf7,
+0x72,
+0xc0,
+0xff,
+0x6f,
+0x3c,
+0xfc,
+0x03,
+0xfc,
+0xc0,
+0x18,
+0xd5,
+0x00,
+0x80,
+0xff,
+0x66,
+0x3c,
+0xeb,
+0xc0,
+0x9f,
+0xd9,
+0x4d,
+0xee,
+0xf8,
+0xff,
+0xff,
+0x83,
+0x7f,
+0xa6,
+0x07,
+0xe8,
+0xff,
+0xff,
+0xe8,
+0x1f,
+0xbe,
+0xb5,
+0x00,
+0x60,
+0x2f,
+0x6a,
+0xbf,
+0xe8,
+0x04,
+0xff,
+0xf5,
+0xf3,
+0xf0,
+0xaf,
+0x7a,
+0x00,
+0xff,
+0xd9,
+0x31,
+0xc0,
+0x83,
+0x3f,
+0xff,
+0x03,
+0x88,
+0xff,
+0x58,
+0xc8,
+0x0f,
+0xef,
+0x35,
+0x00,
+0xd0,
+0x00,
+0xfb,
+0xbf,
+0x85,
+0xff,
+0x03,
+0xd8,
+0x72,
+0xf8,
+0xad,
+0x1c,
+0x80,
+0xfb,
+0x1f,
+0xc0,
+0xe7,
+0xa0,
+0xbe,
+0x71,
+0x00,
+0x86,
+0x7f,
+0x40,
+0xaf,
+0x07,
+0xff,
+0x1e,
+0x00,
+0xf8,
+0x6f,
+0x95,
+0x03,
+0x50,
+0xf4,
+0x03,
+0xf8,
+0x1c,
+0xf8,
+0xff,
+0x3f,
+0x00,
+0xf0,
+0xee,
+0x84,
+0xfc,
+0xfe,
+0xff,
+0xff,
+0x22,
+0xc3,
+0x1f,
+0x51,
+0x96,
+0x50,
+0x16,
+0x0d,
+0x00,
+0xf8,
+0xfe,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0xe5,
+0xa6,
+0xff,
+0x1f,
+0x79,
+0xf8,
+0x07,
+0xf8,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfa,
+0xbf,
+0x07,
+0x01,
+0xfc,
+0x3f,
+0xe3,
+0x3e,
+0x0f,
+0xfd,
+0x50,
+0x03,
+0xb0,
+0xdf,
+0x8c,
+0xf9,
+0x3c,
+0xf4,
+0x43,
+0x0e,
+0xc0,
+0xfd,
+0x32,
+0xe5,
+0xf3,
+0xd0,
+0x0f,
+0x03,
+0x00,
+0xfb,
+0x24,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0xf0,
+0x0f,
+0xe0,
+0x3f,
+0x07,
+0xf0,
+0x6f,
+0xf8,
+0xef,
+0x01,
+0x80,
+0xff,
+0xff,
+0xff,
+0x00,
+0xfd,
+0xbb,
+0x14,
+0xf2,
+0xc3,
+0x2f,
+0xf8,
+0x13,
+0xcc,
+0x7f,
+0x0c,
+0xb8,
+0x0e,
+0x74,
+0xf5,
+0x03,
+0xf0,
+0xf8,
+0x33,
+0x03,
+0x1c,
+0x2b,
+0xd7,
+0x00,
+0x00,
+0xeb,
+0xe5,
+0x1f,
+0x80,
+0xc0,
+0x1f,
+0x1b,
+0xe0,
+0x9e,
+0x9b,
+0x7f,
+0x00,
+0x03,
+0x7f,
+0x6c,
+0x80,
+0xf8,
+0x7d,
+0xfe,
+0x01,
+0x0e,
+0xfc,
+0xb1,
+0x01,
+0xe0,
+0x6d,
+0x62,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x00,
+0xfa,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0xe0,
+0xfc,
+0xff,
+0x3f,
+0xcb,
+0xf0,
+0x8f,
+0x75,
+0xff,
+0xe5,
+0xff,
+0xff,
+0x2c,
+0xc3,
+0x3f,
+0xd6,
+0xf5,
+0x1c,
+0xf0,
+0xff,
+0x8b,
+0x0f,
+0xff,
+0x00,
+0x3f,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0xe0,
+0xbf,
+0x18,
+0x0f,
+0x3a,
+0xf0,
+0x27,
+0xf6,
+0xd1,
+0x35,
+0xfe,
+0x7f,
+0xe7,
+0xe1,
+0x9f,
+0xe8,
+0x5f,
+0xc6,
+0xff,
+0xff,
+0xeb,
+0x87,
+0x7f,
+0xaf,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0xbf,
+0xad,
+0x03,
+0x3c,
+0xf8,
+0x13,
+0x1f,
+0xc0,
+0x7f,
+0xf6,
+0x45,
+0xff,
+0xf0,
+0xad,
+0xff,
+0x04,
+0xff,
+0xff,
+0x83,
+0xad,
+0xc3,
+0x2f,
+0x04,
+0x00,
+0x2c,
+0x80,
+0xfe,
+0x03,
+0xf8,
+0xff,
+0xb5,
+0xe8,
+0x1f,
+0xbe,
+0xff,
+0xdf,
+0x65,
+0xfc,
+0x07,
+0x38,
+0x6b,
+0xf8,
+0xee,
+0xbf,
+0x96,
+0xff,
+0x5f,
+0xeb,
+0xff,
+0xe1,
+0xbf,
+0x07,
+0x00,
+0xfe,
+0x07,
+0xfe,
+0xb5,
+0xfc,
+0xbf,
+0x5a,
+0x57,
+0x0e,
+0xbf,
+0xad,
+0x07,
+0xf0,
+0xf4,
+0x13,
+0xf9,
+0x3c,
+0xf8,
+0x80,
+0x3f,
+0x81,
+0xf0,
+0xcb,
+0x60,
+0xeb,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0xb7,
+0xf5,
+0x00,
+0x07,
+0x7f,
+0x62,
+0x80,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1f,
+0xbe,
+0xb5,
+0xe8,
+0x60,
+0x7c,
+0xc0,
+0x9f,
+0x75,
+0xf8,
+0x65,
+0xb0,
+0x00,
+0x04,
+0x90,
+0x00,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x07,
+0xf0,
+0x1f,
+0xf8,
+0xf8,
+0x37,
+0xfc,
+0x03,
+0x00,
+0xc0,
+0xff,
+0xf7,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
new file mode 100644
index 0000000..46ab18d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c
@@ -0,0 +1,1037 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c8 for 1043 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVC
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c8 for 1043 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8 =
+{{
+0x10,
+0x20,
+0x11,
+0x03,
+0xc8,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x6a,
+0x99,
+0x77,
+0xef,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x43,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x10,
+0x0c,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0x51,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0xff,
+0x18,
+0x80,
+0x38,
+0xc0,
+0x83,
+0x37,
+0x80,
+0xff,
+0xb8,
+0xff,
+0xff,
+0x13,
+0x0e,
+0xbf,
+0x0c,
+0xb6,
+0x7a,
+0xc4,
+0xff,
+0x2f,
+0x3c,
+0xfc,
+0x6b,
+0xfd,
+0x40,
+0x03,
+0xd4,
+0x00,
+0x97,
+0xff,
+0xff,
+0xff,
+0xe7,
+0xe1,
+0x1f,
+0xe0,
+0x00,
+0xfe,
+0xbf,
+0xf5,
+0x9f,
+0x87,
+0x7e,
+0x22,
+0x01,
+0xc6,
+0x00,
+0xc4,
+0x7c,
+0x1e,
+0xfa,
+0x01,
+0x00,
+0xe0,
+0xff,
+0x7b,
+0x0e,
+0x40,
+0xbd,
+0x55,
+0xe0,
+0x73,
+0xd0,
+0x0f,
+0xff,
+0x00,
+0xe0,
+0xff,
+0x13,
+0xf2,
+0xc3,
+0xbb,
+0xff,
+0x8b,
+0xf8,
+0xff,
+0x44,
+0x59,
+0x0e,
+0x7f,
+0x34,
+0x00,
+0x70,
+0x59,
+0xfb,
+0x07,
+0xe0,
+0xfb,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0xfe,
+0x7f,
+0x94,
+0x9b,
+0x1f,
+0xe0,
+0xe7,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0xff,
+0x1e,
+0x00,
+0xe8,
+0xff,
+0x8c,
+0x07,
+0xf0,
+0xf4,
+0x43,
+0xf9,
+0x3c,
+0x7e,
+0x33,
+0x0e,
+0xc0,
+0xd0,
+0x0f,
+0xe5,
+0xf3,
+0xf7,
+0xcb,
+0x38,
+0x00,
+0x43,
+0x3f,
+0x94,
+0xcf,
+0xec,
+0x93,
+0x0c,
+0x00,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0x3f,
+0xf0,
+0x0f,
+0x6f,
+0xf8,
+0x07,
+0xf0,
+0x80,
+0xff,
+0xc0,
+0x3f,
+0xbf,
+0xe1,
+0x1f,
+0xc0,
+0x00,
+0xfe,
+0xbf,
+0x07,
+0x03,
+0xf4,
+0xff,
+0xff,
+0xc8,
+0x0f,
+0xef,
+0x52,
+0x4f,
+0x70,
+0xbf,
+0xe0,
+0xe0,
+0x3a,
+0xfc,
+0x31,
+0x0f,
+0xc0,
+0xd3,
+0xd5,
+0x0c,
+0x70,
+0xe0,
+0xcf,
+0x03,
+0x00,
+0xac,
+0x5c,
+0x7f,
+0x00,
+0xae,
+0x97,
+0x6c,
+0x80,
+0x03,
+0x7f,
+0xfe,
+0x01,
+0x78,
+0x6e,
+0xb1,
+0x01,
+0x0e,
+0xfc,
+0xf9,
+0x07,
+0xe0,
+0xf7,
+0xc7,
+0x06,
+0x38,
+0xf0,
+0x8b,
+0x01,
+0x00,
+0x5e,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0x1f,
+0xf8,
+0x07,
+0xf0,
+0xfc,
+0x03,
+0xf8,
+0x37,
+0xff,
+0xf7,
+0x00,
+0xc0,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0x0f,
+0xfc,
+0x03,
+0x1b,
+0xfe,
+0x01,
+0xfc,
+0xe0,
+0xff,
+0x7b,
+0x00,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xfe,
+0x0d,
+0xff,
+0x00,
+0x00,
+0xf0,
+0xff,
+0x3d,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0x1e,
+0x00,
+0xf8,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x7f,
+0x0f,
+0x00,
+0xfc,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0xbf,
+0x07,
+0x00,
+0xfc,
+0x07,
+0xfe,
+0x01,
+0x0d,
+0xff,
+0x00,
+0xfe,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0xff,
+0x86,
+0x7f,
+0x00,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x01,
+0x80,
+0xff,
+0xef,
+0x7f,
+0x00,
+0xff,
+0x81,
+0x80,
+0x7f,
+0xc3,
+0x3f,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xd7,
+0x00,
+0x80,
+0xf8,
+0xc0,
+0x3f,
+0x80,
+0xff,
+0x1f,
+0xc0,
+0xbf,
+0xe1,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0xfc,
+0x6b,
+0x00,
+0x20,
+0x04,
+0xff,
+0xbf,
+0xe8,
+0xf0,
+0xaf,
+0xf5,
+0xf3,
+0xff,
+0xd9,
+0x7a,
+0x00,
+0x83,
+0x3f,
+0x31,
+0xc0,
+0x0c,
+0x7d,
+0xe3,
+0x00,
+0x0f,
+0xfe,
+0x80,
+0x5e,
+0xf0,
+0xff,
+0x3d,
+0x00,
+0x65,
+0xfe,
+0xff,
+0x9f,
+0x7f,
+0xf8,
+0xc7,
+0xba,
+0x96,
+0xf2,
+0xff,
+0x7f,
+0xfa,
+0xe1,
+0x1f,
+0xeb,
+0x45,
+0x0e,
+0xf8,
+0xff,
+0x9f,
+0x87,
+0x7f,
+0x80,
+0x00,
+0xf8,
+0xff,
+0x1e,
+0x07,
+0xf0,
+0x5f,
+0x8c,
+0x7b,
+0x1d,
+0xf8,
+0x13,
+0xbf,
+0xe8,
+0x1a,
+0xff,
+0xf4,
+0xf3,
+0xf0,
+0x4f,
+0xff,
+0x2f,
+0xe3,
+0xff,
+0xd7,
+0xf5,
+0xc3,
+0xbf,
+0x0f,
+0x00,
+0xfc,
+0x7f,
+0xd6,
+0x03,
+0xf8,
+0xdf,
+0x89,
+0x01,
+0x1e,
+0xfc,
+0xfb,
+0x0f,
+0xe0,
+0x3f,
+0xd6,
+0xa2,
+0x7f,
+0xf8,
+0xff,
+0x7f,
+0x82,
+0xff,
+0x97,
+0xc1,
+0xd6,
+0xe1,
+0x40,
+0x02,
+0x00,
+0x14,
+0x7f,
+0xff,
+0x01,
+0xfc,
+0xdf,
+0x5a,
+0xf4,
+0x0f,
+0xfe,
+0xff,
+0xef,
+0x32,
+0xfc,
+0x03,
+0x9c,
+0x35,
+0x7f,
+0xf7,
+0x5f,
+0xcb,
+0xf0,
+0xaf,
+0xf5,
+0xff,
+0xff,
+0xdf,
+0x03,
+0x00,
+0xfe,
+0x03,
+0xff,
+0x5a,
+0x87,
+0x5f,
+0xad,
+0x2b,
+0xf8,
+0xdf,
+0xd6,
+0x03,
+0x1e,
+0xfa,
+0x89,
+0x7c,
+0x20,
+0x7d,
+0xc0,
+0x9f,
+0x75,
+0xf8,
+0x65,
+0xb0,
+0x80,
+0xff,
+0xef,
+0x01,
+0x00,
+0xff,
+0xdb,
+0x7a,
+0xc0,
+0x83,
+0x3f,
+0x31,
+0x01,
+0xfc,
+0x07,
+0xfe,
+0xf4,
+0x0f,
+0xdf,
+0x5a,
+0x4f,
+0xa0,
+0x3e,
+0xe0,
+0xd8,
+0x3a,
+0xfc,
+0x32,
+0x00,
+0xc0,
+0x01,
+0x48,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0xff,
+0x00,
+0xfe,
+0x03,
+0x00,
+0xff,
+0x86,
+0x7f,
+0xfc,
+0x03,
+0xf8,
+0x0f,
+0x01,
+0xfc,
+0x1b,
+0xfe,
+0x7b,
+0x00,
+0xe0,
+0xff,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0x81,
+0x7f,
+0x00,
+0xff,
+0x3f,
+0x80,
+0x7f,
+0xc3,
+0x07,
+0xfe,
+0x01,
+0xfc,
+0xff,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0x3d,
+0x00,
+0xf0,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xc0,
+0x3f,
+0x80,
+0xe1,
+0x1f,
+0xc0,
+0xbf,
+0xfe,
+0x03,
+0xff,
+0x00,
+0x86,
+0x7f,
+0x00,
+0xff,
+0xf8,
+0xff,
+0x1e,
+0x00,
+0xf0,
+0x1f,
+0xf8,
+0x07,
+0x37,
+0xfc,
+0x03,
+0xf8,
+0xc0,
+0x7f,
+0xe0,
+0x1f,
+0xdf,
+0xf0,
+0x0f,
+0xe0,
+0x00,
+0xff,
+0x81,
+0x7f,
+0x7f,
+0xc3,
+0x3f,
+0x80,
+0x00,
+0xfc,
+0x7f,
+0x0f,
+0x03,
+0xf8,
+0x0f,
+0xfc,
+0xfc,
+0x1b,
+0xfe,
+0x01,
+0x0f,
+0xe0,
+0x3f,
+0xf0,
+0xf0,
+0x6f,
+0xf8,
+0x07,
+0x3f,
+0x80,
+0xff,
+0xc0,
+0xc0,
+0xbf,
+0xe1,
+0x1f,
+0x07,
+0x00,
+0xfe,
+0xbf,
+0xfe,
+0x01,
+0xfc,
+0x07,
+0x00,
+0xfe,
+0x0d,
+0xff,
+0xf8,
+0x07,
+0xf0,
+0x1f,
+0x03,
+0xf8,
+0x37,
+0xfc,
+0xe0,
+0x1f,
+0xc0,
+0x7f,
+0x0f,
+0xe0,
+0xdf,
+0xf0,
+0xdf,
+0x03,
+0x00,
+0xff,
+0x03,
+0xff,
+0x00,
+0xfe,
+0x7f,
+0x00,
+0xff,
+0x86,
+0x0f,
+0xfc,
+0x03,
+0xf8,
+0xfe,
+0x01,
+0xfc,
+0x1b,
+0x3f,
+0xf0,
+0x0f,
+0xe0,
+0xf8,
+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
new file mode 100644
index 0000000..7b413ac
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c
@@ -0,0 +1,439 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address range
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// Erratum 354
+// 0x40:48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_C2 | AMD_F10_C3)          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }}
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }}
+  },
+// 0xCF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// FIFO_PTR_OPT_VALUE
+  {
+    HtPhyProfileRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      PERFORMANCE_NB_PSTATES_ENABLE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000004A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0x520A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,                   //
+      0x520A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+// 0x530A
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                           // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,                   //
+      0x530A,                               // Address
+      0x00004000,                           // regData
+      0x00006000,                           // regMask
+    }}
+  },
+
+
+
+
+//
+// Deemphasis Settings
+//
+
+// For C3, also set [7]TxLs23ClkGateEn.
+//deemphasis level        DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
+// No deemphasis            00h        00h          00h     0                0             0             0
+// -3dB postcursor          12h        00h          00h     1                0             0             0
+// -6dB postcursor          1Fh        00h          00h     1                0             0             0
+// -8dB postcursor          1Fh        06h          00h     1                1             0             1
+// -11dB postcursor         1Fh        0Dh          00h     1                1             0             1
+// -11dB postcursor with
+// -8dB precursor           1Fh        06h          07h     1                1             1             1
+
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL_NONE,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x00000080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__3,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x80120080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__6,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0x801F0080,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F06C0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xC01F0DC0,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xC5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+  {
+    DeemphasisRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C3                               // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      DEEMPHASIS_LEVEL__11_8,
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xD5,                                 // Address
+      0xE01F06C7,                           // regData
+      0xE01F1FDF,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCHtPhyRegisters
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
new file mode 100644
index 0000000..3f99c9d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c
@@ -0,0 +1,205 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 HW C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the hardware C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuHwC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuFamilyTranslation.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should hardware C1e be enabled
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHwC1eSupported (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 PackageType;
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+
+  if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) {
+    return FALSE;
+  }
+
+  // Check if it is BL C2 (not S1g3)
+  if ((LogicalId.Revision & AMD_F10_BL_C2) != 0) {
+    PackageType = LibAmdGetPackageType (StdHeader);
+    if (PackageType != PACKAGE_TYPE_S1G3) {
+      return FALSE;
+    }
+  }
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h CPU.
+ *
+ * @param[in]    HwC1eServices      Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeHwC1e (
+  IN       HW_C1E_FAMILY_SERVICES *HwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 C1eData;
+  UINT64 LocalMsrRegister;
+  AP_TASK TaskPtr;
+
+  LocalMsrRegister = 0;
+  C1eData     = PlatformConfig->C1ePlatformData;
+
+  if (PlatformConfig->C1eMode == C1eModeAuto) {
+    C1eData = PlatformConfig->C1ePlatformData3;
+  }
+
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = C1eData;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 1;
+  ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 1;
+  ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
+
+  TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Hardware C1e on a family 10h core.
+ *
+ * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeHwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  LocalMsrRegister;
+
+  // Enable C1e
+  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
+
+  // Set OS Visible Workaround Status BIT1 to indicate that C1e
+  // is enabled.
+  LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
+  LocalMsrRegister |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
+}
+
+
+CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
+{
+  0,
+  F10IsHwC1eSupported,
+  F10InitializeHwC1e
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
new file mode 100644
index 0000000..f77841c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c
@@ -0,0 +1,133 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+// MSR_LS_CFG (0xC0011020)
+// bit[1] = 0
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_LS_CFG,                           // MSR Address
+      0x0000000000000000,                   // OR Mask
+      (1 << 1),                             // NAND Mask
+    }}
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// bit[21] = 1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_B0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_BU_CFG,                           // MSR Address
+      (1 << 21),                            // OR Mask
+      (1 << 21),                            // NAND Mask
+    }}
+  },
+
+// MSR_BU_CFG2 (0xC001102A)
+// bit[50] = 1
+// For GH rev C1 and later [RdMmExtCfgQwEn]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MSR_BU_CFG2,                          // MSR Address
+      0x0004000000000000,                   // OR Mask
+      0x0004000000000000,                   // NAND Mask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
new file mode 100644
index 0000000..266dd21
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c
@@ -0,0 +1,265 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Rev C PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/RevC
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
+{
+// Function 2 - DRAM Controller
+
+// F2x1B0 - Extended Memory Controller Configuration Low Register
+//
+// bit[5:4], AdapPrefNegativeStep = 0
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
+      0x00000000,                           // regData
+      0x00000030,                           // regMask
+    }}
+  },
+// Function 3 - Misc. Control
+
+// F3x158 - Link to XCS Token Count
+// bits[3:0] LnkToXcsDRToken = 3
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_A2                       // CpuRevision
+    },
+    {AMD_PF_UMA},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
+      0x00000003,                           // regData
+      0x0000000F,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C2
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 0
+// bits[2] NbGateEn = 0
+// bits[3] NbCofChg = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 1
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] NbCofChg = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 7
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000E681,                           // regData
+      0x0000FFFF,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] NbCofChg = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ASB2,                    // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 0
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] NbCofChg = 0
+// bits[4] AltVidEn = 1
+// bits[7:5] ClkDivisor = 7
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                           // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_VRM_HIGH_SPEED_ENABLE,    // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x0000F600,                           // regData
+      0x0000FF00,                           // regMask
+    }}
+  },
+// F3x80 - ACPI Power State Control
+// ACPI State C3, C1E or Link init
+// bits[0] CpuPrbEn = 1
+// bits[1] NbLowPwrEn = 1
+// bits[2] NbGateEn = 1
+// bits[3] NbCofChg = 0
+// bits[4] AltVidEn = 0
+// bits[7:5] ClkDivisor = 4
+  {
+    HtFeatPciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      HT_HOST_FEAT_HT1,                     // link feats
+      PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2),  // package type
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80),  // Address
+      0x00008700,                           // regData
+      0x0000FF00,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3x180 - NB Extended Configuration
+// bits[23] SyncFloodOnDramTempErr = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
+      0x00800000,                           // regData
+      0x00800000,                           // regMask
+    }}
+  },
+// F3x188 - NB Extended Configuration Low Register
+// bit[22] = DisHldReg2
+// Errata #346
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_Cx                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
+      0x00400000,                           // regData
+      0x00400000,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RevCPciRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
new file mode 100644
index 0000000..104d3a1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c
@@ -0,0 +1,181 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 SW C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the software C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuSwC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeSwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should software C1e be enabled
+ *
+ * @param[in]    SwC1eServices      Pointer to this CPU's SW C1e family services.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               SW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsSwC1eSupported (
+  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return TRUE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Software C1e on a family 10h CPU.
+ *
+ * @param[in]    SwC1eServices      Pointer to this CPU's SW C1e family services.
+ * @param[in]    EntryPoint         Timepoint designator.
+ * @param[in]    PlatformConfig     Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeSwC1e (
+  IN       SW_C1E_FAMILY_SERVICES *SwC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+  AP_TASK TaskPtr;
+
+  LocalMsrRegister = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 1;
+
+  TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
+  TaskPtr.DataTransfer.DataSizeInDwords = 2;
+  TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
+  TaskPtr.DataTransfer.DataTransferFlags = 0;
+  TaskPtr.ExeFlags = WAIT_FOR_CORE;
+  ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable Software C1e on a family 10h core.
+ *
+ * @param[in]    IntPendMsr         MSR value to write to C001_0055 as determined by core 0.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeSwC1eOnCore (
+  IN       VOID *IntPendMsr,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  LocalMsrRegister;
+
+  // Enable C1e
+  LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
+
+  // Set OS Visible Workaround Status BIT1 to indicate that C1e
+  // is enabled.
+  LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
+  LocalMsrRegister |= BIT1;
+  LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
+}
+
+
+CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e =
+{
+  0,
+  F10IsSwC1eSupported,
+  F10InitializeSwC1e
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
new file mode 100644
index 0000000..dd87ad3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c
@@ -0,0 +1,495 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 revision Cx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev C.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuPostInit.h"
+#include "cpuFeatures.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision C processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   CoreLevelMode            Core level mode.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ * @retval      TRUE                     Down Core register is updated.
+ * @retval      FALSE                    Down Core register is not updated.
+ */
+BOOLEAN
+F10CommonRevCSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   IsUpdated;
+  AGESA_STATUS AgesaStatus;
+
+  IsUpdated = FALSE;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = (TempVar32_a >> 12) & 0x3;
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
+        TempVar32_a |= CoreDisableBits;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+        IsUpdated = TRUE;
+      }
+    }
+  }
+
+  return IsUpdated;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
+{
+  0,
+  F10CommonRevCSetDownCoreRegister
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision C processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevCGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       LocalPciRegister;
+  UINT32       MsrAddress;
+  UINT32       SinglePlaneNbIdd;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
+    CmpCap++;
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      ASSERT (FALSE);
+      IddDiv = 10;
+      break;
+    }
+
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
+    if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) {
+      *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
+    } else {
+      PciAddress.Address.Register = PRCT_INFO_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
+      SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->SinglePlaneNbIdd;
+      SinglePlaneNbIdd <<= 1;
+      *ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
+    }
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevCGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 ProductInfoRegister;
+
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  PciAddress->Address.Function = FUNC_3;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+  *NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
+  return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[in]     NbPstate                The NB P-state number to check.
+ *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
+ *  @param[out]    FreqDivisor             The desired node's frequency divisor.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    NbPstate is valid
+ *  @retval        FALSE                   NbPstate is disabled or invalid
+ */
+BOOLEAN
+F10CommonRevCGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   NbFid;
+  UINT32   NbVid;
+  UINT32   LocalPciRegister;
+  UINT32   ProductInfoRegister;
+  UINT64   LocalMsrRegister;
+  BOOLEAN  PstateIsValid;
+
+  PstateIsValid = TRUE;
+  if (NbPstate == 0) {
+    *FreqDivisor = 1;
+  } else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
+    *FreqDivisor = 2;
+  } else {
+    PstateIsValid = FALSE;
+  }
+  if (PstateIsValid) {
+    PciAddress->Address.Function = FUNC_3;
+    PciAddress->Address.Register = PRCT_INFO_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+    if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
+      PciAddress->Address.Register = CPTC0_REG;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+      NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
+      LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+      NbVid = (UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid;
+    } else {
+      NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
+      NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
+      PciAddress->Address.Register = PW_CTL_MISC_REG;
+      LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+      if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
+        NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
+        NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
+      }
+    }
+    *FreqNumeratorInMHz = ((NbFid + 4) * 200);
+    *VoltageInuV = (1550000 - (12500 * NbVid));
+  }
+  return PstateIsValid;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the node's minimum and maximum northbridge frequency.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[out]    MinFreqInMHz            The node's miminum northbridge frequency.
+ *  @param[out]    MaxFreqInMHz            The node's maximum northbridge frequency.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_STATUS            Northbridge frequency is valid
+ */
+AGESA_STATUS
+F10RevCGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *MinFreqInMHz,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32         NbPstateEn;
+  UINT32         NbFid;
+  UINT32         FreqDivisor;
+  UINT32         FreqNumerator;
+  UINT32         LocalPciRegister;
+  UINT32         ProductInfoRegister;
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+
+  FreqDivisor = 1;
+
+  // If NB P-state is supported, return the frequency of NB P-state 1
+  if ((PlatformConfig->PlatformProfile.PlatformPowerPolicy != Performance) &&
+     ((LogicalId.Revision & AMD_F10_C3) != 0)) {
+    PciAddress->Address.Function = FUNC_3;
+    PciAddress->Address.Register = 0x1F0;
+    LibAmdPciReadBits (*PciAddress, 18, 16, &NbPstateEn, StdHeader);
+
+    if (NbPstateEn != 0) {
+      FreqDivisor = 2;
+    }
+  }
+
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = PRCT_INFO_REG;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
+
+  if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
+    PciAddress->Address.Register = CPTC0_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+    NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
+  } else {
+    NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
+    PciAddress->Address.Register = PW_CTL_MISC_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+    if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
+      NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
+    }
+  }
+
+  FreqNumerator = ((NbFid + 4) * 200);
+  *MaxFreqInMHz = FreqNumerator;
+  *MinFreqInMHz = (FreqNumerator / FreqDivisor);
+
+  return AGESA_SUCCESS;
+
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is the Northbridge PState feature enabled?
+ *
+ * @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      PlatformConfig                 Platform profile/build option config structure.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @retval         TRUE                           The NB PState feature is enabled.
+ * @retval         FALSE                          The NB PState feature is not enabled.
+ */
+BOOLEAN
+F10CommonRevCIsNbPstateEnabled (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32         NbPstate;
+  PCI_ADDR       PciAddress;
+  CPU_LOGICAL_ID LogicalId;
+  BOOLEAN        Result;
+
+  Result = FALSE;
+
+  GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
+  if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) {
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = 0x1F0;
+    LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
+    if (NbPstate != 0) {
+      Result = TRUE;
+    }
+  }
+  return Result;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of physical cores of current processor.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of physical cores.
+ */
+UINT8
+F10CommonRevCGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       LocalPciRegister;
+  PCI_ADDR     PciAddress;
+
+  OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = NB_CAPS_REG;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
new file mode 100644
index 0000000..0f773a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbEquivalenceTable.c
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST UINT16 ROMDATA CpuF10RbMicrocodeEquivalenceTable[] =
+{
+  0x1040, 0x1040,
+  0x1041, 0x1041,
+  0x1042, 0x1041,
+  0x1043, 0x1043
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10RbMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *RbEquivalenceTablePtr = CpuF10RbMicrocodeEquivalenceTable;
+}
+
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
new file mode 100644
index 0000000..646ab56
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbHtPhyRegisters[] =
+{
+// Erratum 354
+// 0x40:0x48
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0x40, 0x48,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0x50:0x58
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C1)                     // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0x50, 0x58,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbHtPhyRegisters
+};
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
new file mode 100644
index 0000000..bca98a4
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c
@@ -0,0 +1,114 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB Logical ID Table
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+STATIC CONST CPU_LOGICAL_ID_XLAT ROMDATA CpuF10RbLogicalIdAndRevArray[] =
+{
+  {
+    0x1040,
+    AMD_F10_RB_C0
+  },
+  {
+    0x1041,
+    AMD_F10_RB_C1
+  },
+  {
+    0x1042,
+    AMD_F10_RB_C2
+  },
+  {
+    0x1043,
+    AMD_F10_RB_C3
+  }
+};
+
+VOID
+GetF10RbLogicalIdAndRev (
+     OUT   CONST CPU_LOGICAL_ID_XLAT **RbIdPtr,
+     OUT   UINT8 *NumberOfElements,
+     OUT   UINT64 *LogicalFamily,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT));
+  *RbIdPtr = CpuF10RbLogicalIdAndRevArray;
+  *LogicalFamily = AMD_FAMILY_10_RB;
+}
+
+//CONST LOGICAL_ID_TABLE ROMDATA CpuF10RbLogicalIdAndRev =
+//{
+//  (sizeof (CpuF10RbLogicalIdAndRevArray) / sizeof (CPU_LOGICAL_ID_XLAT)),
+//  (CPU_LOGICAL_ID_XLAT *) &CpuF10RbLogicalIdAndRevArray
+//};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
new file mode 100644
index 0000000..d4c65d1
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMicrocodePatchTables.c
@@ -0,0 +1,106 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB microcode patches
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+extern CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[];
+extern CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches;
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns a table containing the appropriate microcode patches.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  RbUcodePtr               Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10RbMicroCodePatchesStruct (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **RbUcodePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = CpuF10RbNumberOfMicrocodePatches;
+  *RbUcodePtr = &CpuF10RbMicroCodePatchArray[0];
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
new file mode 100644
index 0000000..9c6b0c3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB, MSR tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RbMsrRegisters[] =
+{
+//  M S R    T a b l e s
+// ----------------------
+
+// MSR_DC_CFG (0xC0011022)
+// bits[43:42] = 0
+// Errata #326
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                       // CpuFamily
+      AMD_F10_RB_C0                        // CpuRevision
+    },
+    {AMD_PF_MULTI_LINK},                     // platformFeatures
+    {{
+      MSR_DC_CFG,                            // MSR Address
+      0x0000000000000000,                    // OR Mask
+      0x00000C0000000000,                    // NAND Mask
+    }}
+  },
+
+// MSR_BU_CFG (0xC0011023)
+// Erratum #309 BU_CFG[23]=1
+  {
+    MsrRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                            // platformFeatures
+    {{
+      MSR_BU_CFG,                            // MSR Address
+      (1 << 23),                             // OR Mask
+      (1 << 23),                             // NAND Mask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable = {
+  AllCores,
+  (sizeof (F10RbMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  (TABLE_ENTRY_FIELDS *) &F10RbMsrRegisters,
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
new file mode 100644
index 0000000..35042a2
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c
@@ -0,0 +1,234 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RB PCI tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  P C I    T a b l e s
+// ----------------------
+
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RbPciRegisters[] =
+{
+  // Function 0
+
+// F0x16C - Link Global Extended Control Register, Errata 351
+// bit[15:13] ForceFullT0 = 0
+// bit[5:0] T0Time = 0x14
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000014,                           // regData
+      0x0000E03F,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[7:6] InLnSt = 0x01
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x00000040,                           // regData
+      0x000000C0,                           // regMask
+    }}
+  },
+// F0x16C - Link Global Extended Control Register
+// bit[15:13] ForceFullT0 = 6
+// bit[9] RXCalEn = 1
+// bit[5:0] T0Time = 0x26
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                      // CpuRevision
+    },
+    {AMD_PF_SINGLE_LINK},                   // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
+      0x0000C226,                           // regData
+      0x0000E23F,                           // regMask
+    }}
+  },
+// F0x170 - Link Extended Control Register - Link 0, sublink 0
+// Errata 351 (only need to override single link case.)
+// bit[8] LS2En = 0,
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+     (AMD_F10_RB_C0 | AMD_F10_RB_C1 | AMD_F10_RB_C2)     // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_0, 0x170), // Address
+      0x00000000,                           // regData
+      0x00000100,                           // regMask
+    }}
+  },
+
+
+// F3xA0 - Power Control Miscellaneous
+// bits[13:11] PllLockTime = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x00002800,                           // regData
+      0x00003800,                           // regMask
+    }}
+  },
+// F3xA0 - Power Control Miscellaneous
+// bits[28] NbPstateForce = 1
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_C3                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0),  // Address
+      0x10000000,                           // regData
+      0x10000000,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 6
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_RB_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00006000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    PciRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_C0                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  },
+// F3xDC - Clock Power Timing Control 2
+// bits[14:12] NbsynPtrAdj = 5
+  {
+    ProfileFixup,
+    {
+      AMD_FAMILY_10,                        // CpuFamily
+      AMD_F10_C3                            // CpuRevision
+    },
+    {AMD_PF_ALL},                             // platformFeatures
+    {{
+      PERFORMANCE_NB_PSTATES_ENABLE,        // PerformanceFeatures
+      MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC),  // Address
+      0x00005000,                           // regData
+      0x00007000,                           // regMask
+    }}
+  }
+};
+
+CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable = {
+  PrimaryCores,
+  (sizeof (F10RbPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
+  F10RbPciRegisters,
+};
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
new file mode 100644
index 0000000..81e2c58
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c
@@ -0,0 +1,1039 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000c5 for 1080 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10/REVD
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+// Patch code 010000c5 for 1080 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5 =
+{{
+0x10,
+0x20,
+0x05,
+0x03,
+0xc5,
+0x00,
+0x00,
+0x01,
+0x00,
+0x80,
+0x20,
+0x00,
+0x83,
+0xc5,
+0x93,
+0xcd,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x00,
+0x80,
+0x10,
+0x00,
+0x00,
+0x00,
+0xaa,
+0xaa,
+0xaa,
+0x89,
+0x0b,
+0x00,
+0x00,
+0x55,
+0x03,
+0x00,
+0x00,
+0xff,
+0xff,
+0xff,
+0xff,
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+0x07,
+0xf0,
+0x6f,
+0xff,
+0xef,
+0x01,
+0x80
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c
new file mode 100644
index 0000000..534f0e8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c
@@ -0,0 +1,1066 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Microcode patch.
+ *
+ * Fam10 Microcode Patch rev 010000D9 for 1081 or equivalent.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10/RevD
+ * @e \$Revision: 60726 $   @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC.  All Rights Reserved.
+ *
+ * AMD is granting you permission to use this software (the Materials)
+ * pursuant to the terms and conditions of your Software License Agreement
+ * with AMD.  This header does *NOT* give you permission to use the Materials
+ * or any rights under AMD's intellectual property.  Your use of any portion
+ * of these Materials shall constitute your acceptance of those terms and
+ * conditions.  If you do not agree to the terms and conditions of the Software
+ * License Agreement, please do not use any portion of these Materials.
+ *
+ * CONFIDENTIALITY:  The Materials and all other information, identified as
+ * confidential and provided to you by AMD shall be kept confidential in
+ * accordance with the terms and conditions of the Software License Agreement.
+ *
+ * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION
+ * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
+ * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE,
+ * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE.
+ * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER
+ * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
+ * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE,
+ * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER
+ * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.  BECAUSE SOME JURISDICTIONS PROHIBIT THE
+ * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES,
+ * THE ABOVE LIMITATION MAY NOT APPLY TO YOU.
+ *
+ * AMD does not assume any responsibility for any errors which may appear in
+ * the Materials or any other related information provided to you by AMD, or
+ * result from use of the Materials or any related information.
+ *
+ * You agree that you will not reverse engineer or decompile the Materials.
+ *
+ * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any
+ * further information, software, technical information, know-how, or show-how
+ * available to you.  Additionally, AMD retains the right to modify the
+ * Materials at any time, without notice, and is not obligated to provide such
+ * modified Materials to you.
+ *
+ * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with
+ * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is
+ * subject to the restrictions as set forth in FAR 52.227-14 and
+ * DFAR252.227-7013, et seq., or its successor.  Use of the Materials by the
+ * Government constitutes acknowledgement of AMD's proprietary rights in them.
+ *
+ * EXPORT ASSURANCE:  You agree and certify that neither the Materials, nor any
+ * direct product thereof will be exported directly or indirectly, into any
+ * country prohibited by the United States Export Administration Act and the
+ * regulations thereunder, without the required authorization from the U.S.
+ * government nor will be used for any purpose prohibited by the same.
+ *
+ ***************************************************************************/
+
+
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "cpuEarlyInit.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+// Patch code 010000d9 for 1081 and equivalent
+CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9 =
+{{
+  0x11,
+  0x20,
+  0x12,
+  0x10,
+  0xd9,
+  0x00,
+  0x00,
+  0x01,
+  0x00,
+  0x80,
+  0x20,
+  0x00,
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+  0x1f,
+  0x40,
+  0xfc,
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+  0x07,
+  0x00,
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+  0xbf,
+  0xfc,
+  0xbb,
+  0x00,
+  0x00,
+  0x5c,
+  0xf7,
+  0x0f,
+  0xff,
+  0xf0,
+  0x9f,
+  0x32,
+  0x20,
+  0x03,
+  0xfc,
+  0x3c,
+  0xfc,
+  0xff,
+  0x7f,
+  0xca,
+  0xf9,
+  0x2f,
+  0x75,
+  0x7d,
+  0xf0,
+  0x5e,
+  0x03,
+  0x00,
+  0x3d,
+  0xbb,
+  0xff,
+  0x52,
+  0xff,
+  0x7f,
+  0xa9,
+  0x9f,
+  0x87,
+  0xff,
+  0xff,
+  0x77,
+  0x79,
+  0xfe,
+  0x01,
+  0x7e,
+  0x1e,
+  0xbf,
+  0xbb,
+  0x0f,
+  0xf0,
+  0xe8,
+  0x97,
+  0xf2,
+  0x79,
+  0xff,
+  0xef,
+  0x01,
+  0x80,
+}};
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
new file mode 100644
index 0000000..2ac72ad
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm
@@ -0,0 +1,113 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+    .586P
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .MODEL flat
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress          Full PCI address of the node to init
+;       LocalPciRegister    Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+F10RevDProbeFilterCritical PROC NEAR C PUBLIC USES EAX ECX EDX, PciAddress:DWORD, LocalPciRegister:DWORD
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   eax
+  push   ecx
+  push   edx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, LocalPciRegister
+  mov    edx, PciAddress
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  out    dx, eax          ; move data to return position
+  db     0Fh, 0AEh, 0F0h  ; MFENCE
+
+  pop    edx
+  pop    ecx
+  pop    eax
+  wrmsr
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
new file mode 100644
index 0000000..4e531ea
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm
@@ -0,0 +1,127 @@
+;/**
+; * @file
+; *
+; * AGESA Family 10h Revision D support routines.
+; *
+; * @xrefitem bom "File Content Label" "Release Content"
+; * @e project:      AGESA
+; * @e sub-project:  CPU/F10
+; * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+; */
+;*****************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*****************************************************************************
+
+    .XLIST
+    .LIST
+
+;===============================================
+;===============================================
+;==
+;== M E M O R Y   P R E S E N T   S E G M E N T
+;==
+;===============================================
+;===============================================
+    .CODE
+
+;======================================================================
+; F10RevDProbeFilterCritical:  Performs critical sequence for probe
+;                              filter initialization.
+;
+;   In:
+;       PciAddress           Full PCI address of the node to init
+;       LocalPciRegister     Current value of F3x1D4
+;
+;
+;   Out:
+;       None
+;
+;   Destroyed:
+;       None
+;
+;======================================================================
+PUBLIC F10RevDProbeFilterCritical
+F10RevDProbeFilterCritical PROC
+
+  push   rax
+  push   rcx
+  push   rdx
+  push   rsi
+  push   rdi
+
+  mov    esi, ecx
+  mov    edi, edx
+
+  mov    ecx, 0C001001Fh
+  rdmsr
+  push   rax
+  push   rcx
+  push   rdx
+  or     dh, 40h
+  wrmsr
+
+  mov    eax, 810003D4h
+
+  mov    ecx, edi
+  mov    edx, esi
+
+  shr    edx, 4
+  and    dh, 0F8h
+  or     ah, dh
+
+  or     cl, 2
+  mfence
+
+  mov    dx, 0CF8h        ; Set Reg Config Space
+  mfence
+
+  out    dx, eax
+  mfence
+
+  mov    dl, 0FCh         ; Set DX to Pci Config Data
+  mov    eax, ecx         ;Set config Reg data
+  mfence
+
+  out    dx, eax          ; move data to return position
+  mfence
+
+  pop    rdx
+  pop    rcx
+  pop    rax
+  wrmsr
+
+  pop    rdi
+  pop    rsi
+  pop    rdx
+  pop    rcx
+  pop    rax
+  ret
+
+F10RevDProbeFilterCritical ENDP
+
+END
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
new file mode 100644
index 0000000..d16b4e7
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c
@@ -0,0 +1,516 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RevD L3 dependent feature support functions.
+ *
+ * Provides the functions necessary to initialize L3 dependent feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 60552 $   @e \$Date: 2011-10-17 18:50:55 -0600 (Mon, 17 Oct 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/*
+ *----------------------------------------------------------------------------
+ *                                MODULES USED
+ *
+ *----------------------------------------------------------------------------
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "CommonReturns.h"
+#include "cpuRegisters.h"
+#include "cpuF10PowerMgmt.h"
+#include "cpuLateInit.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuL3Features.h"
+#include "F10PackageType.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE
+/*----------------------------------------------------------------------------
+ *                          DEFINITIONS AND MACROS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------
+ *                           TYPEDEFS AND STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * The family 10h background scrubber context structure.
+ *
+ * These fields need to be saved, modified, then restored
+ * per die as part of HT Assist initialization.
+ */
+typedef struct {
+  UINT32  DramScrub:5;               ///< DRAM scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  L3Scrub:5;                 ///< L3 scrub rate
+  UINT32  :3;                        ///< Reserved
+  UINT32  Redirect:1;                ///< DRAM scrubber redirect enable
+  UINT32  :15;                       ///< Reserved
+} F10_SCRUB_CONTEXT;
+
+
+/*----------------------------------------------------------------------------
+ *                        PROTOTYPES OF LOCAL FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+BOOLEAN
+F10IsNonOptimalConfig (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------
+ *                            EXPORTED FUNCTIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU supports L3 dependent features.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ *
+ * @retval       TRUE                L3 dependent features are supported.
+ * @retval       FALSE               L3 dependent features are not supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsL3FeatureSupported (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig
+  )
+{
+  UINT32       Module;
+  UINT32       LocalPciRegister;
+  BOOLEAN      IsSupported;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsSupported = FALSE;
+
+  if (PlatformConfig->PlatformProfile.UseHtAssist) {
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if (((NB_CAPS_REGISTER *) &LocalPciRegister)->L3Capable == 1) {
+        IsSupported = TRUE;
+      }
+      break;
+    }
+  }
+  }
+  return IsSupported;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU supports HT Assist.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE                HT Assist is supported.
+ * @retval       FALSE               HT Assist cannot be enabled.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsHtAssistSupported (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN          IsSupported;
+  UINT32           CpuCount;
+  AP_MAILBOXES     ApMailboxes;
+
+  IsSupported = FALSE;
+
+  if (PlatformConfig->PlatformProfile.UseHtAssist) {
+    CpuCount = GetNumberOfProcessors (StdHeader);
+    ASSERT (CpuCount != 0);
+
+    if (CpuCount == 1) {
+      GetApMailbox (&ApMailboxes.ApMailInfo.Info, StdHeader);
+      if (ApMailboxes.ApMailInfo.Fields.ModuleType != 0) {
+        IsSupported = TRUE;
+      }
+    } else if (CpuCount > 1) {
+      IsSupported = TRUE;
+    }
+  }
+  return IsSupported;
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable the Probe filter feature.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HtAssistInit (
+  IN       L3_FEATURE_FAMILY_SERVICES  *L3FeatureServices,
+  IN       UINT32  Socket,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32                     Module;
+  UINT32                     LocalPciRegister;
+  PCI_ADDR                   PciAddress;
+  AGESA_STATUS               IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = L3_CACHE_PARAM_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit = 1;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      } while (((L3_CACHE_PARAM_REGISTER *) &LocalPciRegister)->L3TagInit != 0);
+
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFMode = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      F10RevDProbeFilterCritical (PciAddress, LocalPciRegister);
+
+      do {
+        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      } while (((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFInitDone != 1);
+      IDS_OPTION_HOOK (IDS_HT_ASSIST, &PciAddress, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Save the current settings of the scrubbers, and disabled them.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10GetL3ScrubCtrl (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       ScrubCtrl;
+  UINT32       ScrubAddr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub =
+        ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub;
+      ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect =
+        ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn;
+
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->DramScrub = 0;
+      ((SCRUB_RATE_CTRL_REGISTER *) &ScrubCtrl)->L3Scrub = 0;
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &ScrubAddr)->ScrubReDirEn = 0;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubCtrl, StdHeader);
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &ScrubAddr, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Restore the initial settings for the scrubbers.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    ScrubSettings       Location to store current L3 scrubber settings.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10SetL3ScrubCtrl (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       UINT32 ScrubSettings[L3_SCRUBBER_CONTEXT_ARRAY_SIZE],
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       Module;
+  UINT32       LocalPciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+
+      ASSERT (Module < L3_SCRUBBER_CONTEXT_ARRAY_SIZE);
+
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = SCRUB_RATE_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->DramScrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->DramScrub;
+      ((SCRUB_RATE_CTRL_REGISTER *) &LocalPciRegister)->L3Scrub =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->L3Scrub;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      PciAddress.Address.Register = DRAM_SCRUB_ADDR_LOW_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      ((DRAM_SCRUB_ADDR_LOW_REGISTER *) &LocalPciRegister)->ScrubReDirEn =
+        ((F10_SCRUB_CONTEXT *) &ScrubSettings[Module])->Redirect;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Set MSR bits required for L3 dependent features on each core.
+ *
+ * @param[in]    L3FeatureServices   L3 feature family services.
+ * @param[in]    HtAssistEnabled     Indicates whether Ht Assist is enabled.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookDisableCache (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       BOOLEAN HtAssistEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64  LocalMsrRegister;
+
+  LibAmdMsrRead (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
+  LocalMsrRegister |= BIT42;
+  LibAmdMsrWrite (MSR_BU_CFG2, &LocalMsrRegister, StdHeader);
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Hook before L3 features initialization sequence.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10HookBeforeInit (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32          Module;
+  UINT32          LocalPciRegister;
+  UINT32          PfCtrlRegister;
+  PCI_ADDR        PciAddress;
+  CPU_LOGICAL_ID  LogicalId;
+  AGESA_STATUS    IgnoredStatus;
+  UINT32          PackageType;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  PackageType = LibAmdGetPackageType (StdHeader);
+
+  LocalPciRegister = 0;
+  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFWayNum = 2;
+  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFSubCacheEn = 15;
+  ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFLoIndexHashEn = 1;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = PROBE_FILTER_CTRL_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &PfCtrlRegister, StdHeader);
+      ((PROBE_FILTER_CTRL_REGISTER *) &LocalPciRegister)->PFPreferredSORepl =
+        ((PROBE_FILTER_CTRL_REGISTER *) &PfCtrlRegister)->PFPreferredSORepl;
+      LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+
+      // Assumption: all socket use the same CPU package.
+      if (((LogicalId.Revision & AMD_F10_D0) != 0) && (PackageType == PACKAGE_TYPE_C32)) {
+        // Apply erratum #384
+        // Set F2x11C[13:12] = 11b
+        PciAddress.Address.Function = FUNC_2;
+        PciAddress.Address.Register = 0x11C;
+        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+        LocalPciRegister |= 0x3000;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      }
+    }
+  }
+}
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the input CPU is running in the optimal configuration.
+ *
+ * @param[in]    L3FeatureServices   L3 Feature family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HT Assist is running sub-optimally.
+ * @retval       FALSE              HT Assist is running optimally.
+ *
+ */
+BOOLEAN
+F10IsNonOptimalConfig (
+  IN       L3_FEATURE_FAMILY_SERVICES *L3FeatureServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  BOOLEAN      IsNonOptimal;
+  BOOLEAN      IsMemoryPresent;
+  UINT32       Module;
+  UINT32       LocalPciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredStatus;
+
+  IsNonOptimal = FALSE;
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredStatus)) {
+      IsMemoryPresent = FALSE;
+      PciAddress.Address.Function = FUNC_2;
+      PciAddress.Address.Register = DRAM_CFG_HI_REG0;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+
+      PciAddress.Address.Register = DRAM_CFG_HI_REG1;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreqVal == 1) {
+        IsMemoryPresent = TRUE;
+        if (((DRAM_CFG_HI_REGISTER *) &LocalPciRegister)->MemClkFreq < 4) {
+          IsNonOptimal = TRUE;
+          break;
+        }
+      }
+      if (!IsMemoryPresent) {
+        IsNonOptimal = TRUE;
+        break;
+      }
+    }
+  }
+  return IsNonOptimal;
+}
+
+
+CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features =
+{
+  0,
+  F10IsL3FeatureSupported,
+  F10GetL3ScrubCtrl,
+  F10SetL3ScrubCtrl,
+  F10HookBeforeInit,
+  (PF_L3_FEATURE_AFTER_INIT) CommonVoid,
+  F10HookDisableCache,
+  (PF_L3_FEATURE_ENABLE_CACHE) CommonVoid,
+  F10IsHtAssistSupported,
+  F10HtAssistInit,
+  F10IsNonOptimalConfig,
+  (PF_ATM_MODE_IS_SUPPORTED) CommonReturnFalse,
+  (PF_ATM_MODE_INIT) CommonVoid
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
new file mode 100644
index 0000000..1467537
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c
@@ -0,0 +1,282 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 RevD Message-Based C1e feature support functions.
+ *
+ * Provides the functions necessary to initialize the message-based C1e feature.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuFeatures.h"
+#include "cpuServices.h"
+#include "GeneralServices.h"
+#include "cpuMsgBasedC1e.h"
+#include "cpuApicUtilities.h"
+#include "cpuF10PowerMgmt.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Should message-based C1e be enabled
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    Socket              Processor socket to check.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @retval       TRUE               HW C1e is supported.
+ *
+ */
+BOOLEAN
+STATIC
+F10IsMsgBasedC1eSupported (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT32 Socket,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  CPU_LOGICAL_ID LogicalId;
+
+  GetLogicalIdOfSocket (Socket, &LogicalId, StdHeader);
+  return ((BOOLEAN) (((LogicalId.Revision) & AMD_F10_GT_D0) != 0));
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Core 0 task to enable message-based C1e on a family 10h CPU.
+ *
+ * @param[in]    MsgBasedC1eServices Pointer to this CPU's HW C1e family services.
+ * @param[in]    EntryPoint          Timepoint designator.
+ * @param[in]    PlatformConfig      Contains the runtime modifiable feature input data.
+ * @param[in]    StdHeader           Config Handle for library, services.
+ *
+ * @return       AGESA_SUCCESS      Always succeeds.
+ *
+ */
+AGESA_STATUS
+STATIC
+F10InitializeMsgBasedC1e (
+  IN       MSG_BASED_C1E_FAMILY_SERVICES *MsgBasedC1eServices,
+  IN       UINT64 EntryPoint,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32       AndMask;
+  UINT32       Core;
+  UINT32       Module;
+  UINT32       OrMask;
+  UINT32       LocalPciRegister;
+  UINT32       Socket;
+  AP_TASK      TaskPtr;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  if ((EntryPoint & (CPU_FEAT_AFTER_POST_MTRR_SYNC | CPU_FEAT_AFTER_RESUME_MTRR_SYNC)) != 0) {
+    // Note that this core 0 does NOT have the ability to launch
+    // any of its cores.  Attempting to do so could lead to a system
+    // hang.
+
+    // Set F3xA0[IdleExitEn] = 1
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = PW_CTL_MISC_REG;
+    AndMask = 0xFFFFFFFF;
+    OrMask = 0;
+    ((POWER_CTRL_MISC_REGISTER *) &OrMask)->IdleExitEn = 1;
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3xA0
+
+    // Erratum #610, BIOS should set F3x1B8[5]
+    PciAddress.Address.Register = 0x1B8;
+    OrMask = 0x00000020;
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x1B8
+
+    // Set F3x188[EnStpGntOnFlushMaskWakeup] = 1
+    PciAddress.Address.Register = NB_EXT_CFG_LO_REG;
+    OrMask = 0;
+    ((NB_EXT_CFG_LO_REGISTER *) &OrMask)->EnStpGntOnFlushMaskWakeup = 1;
+    OptionMultiSocketConfiguration.ModifyCurrSocketPci (&PciAddress, AndMask, OrMask, StdHeader); // F3x188
+
+    // Set F3xD4[MTC1eEn] = 1, F3xD4[CacheFlushImmOnAllHalt] = 1
+    // Set F3xD4[StutterScrubEn] = 1 if scrubbing is enabled
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->StutterScrubEn = 0;
+    OrMask = 0;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->MTC1eEn = 1;
+    ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->CacheFlushImmOnAllHalt = 1;
+
+    IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+
+    for (Module = 0; Module < (UINT8)GetPlatformNumberOfModules (); Module++) {
+      if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+        PciAddress.Address.Function = FUNC_3;
+        PciAddress.Address.Register = CPTC0_REG;
+        if (IsDramScrubberEnabled (PciAddress, StdHeader)) {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 1;
+        } else {
+          ((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->StutterScrubEn = 0;
+        }
+        LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+        LocalPciRegister &= AndMask;
+        LocalPciRegister |= OrMask;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      }
+    }
+
+  } else if (EntryPoint == CPU_FEAT_AFTER_PM_INIT) {
+    // At early, this core 0 can launch its subordinate cores.
+    TaskPtr.FuncAddress.PfApTaskI = F10InitializeMsgBasedC1eOnCore;
+    TaskPtr.DataTransfer.DataSizeInDwords = 1;
+    TaskPtr.DataTransfer.DataPtr = &PlatformConfig->C1ePlatformData;
+    TaskPtr.DataTransfer.DataTransferFlags = 0;
+    TaskPtr.ExeFlags = WAIT_FOR_CORE;
+    ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
+  }
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Enable message-based C1e on a family 10h core.
+ *
+ * @param[in]    BmStsAddress       System I/O address of the bus master status bit.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ */
+VOID
+STATIC
+F10InitializeMsgBasedC1eOnCore (
+  IN       VOID              *BmStsAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT64 LocalMsrRegister;
+
+  // Set MSRC001_0055[SmiOnCmpHalt] = 0, MSRC001_0055[C1eOnCmpHalt] = 0
+  LibAmdMsrRead (MSR_INTPEND, &LocalMsrRegister, StdHeader);
+  ((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->BmStsClrOnHltEn = 1;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsgDis = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IntrPndMsg = 0;
+  ((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = (UINT64) *((UINT32 *) BmStsAddress);
+  LibAmdMsrWrite (MSR_INTPEND, &LocalMsrRegister, StdHeader);
+
+  // Set MSRC001_0015[HltXSpCycEn] = 1
+  LibAmdMsrRead (MSR_HWCR, &LocalMsrRegister, StdHeader);
+  LocalMsrRegister |= BIT12;
+  LibAmdMsrWrite (MSR_HWCR, &LocalMsrRegister, StdHeader);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Check to see if the DRAM background scrubbers are enabled or not.
+ *
+ * @param[in]    PciAddress         Address of F10 socket/module to check.
+ * @param[in]    StdHeader          Config Handle for library, services.
+ *
+ * @retval       TRUE               Memory scrubbers are enabled on the current node.
+ * @retval       FALSE              Memory scrubbers are disabled on the current node.
+ */
+BOOLEAN
+STATIC
+IsDramScrubberEnabled (
+  IN       PCI_ADDR PciAddress,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32 LocalPciRegister;
+
+  PciAddress.Address.Function = FUNC_3;
+  PciAddress.Address.Register = 0x58;
+  LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+  return ((BOOLEAN) ((LocalPciRegister & 0x1F) != 0));
+}
+
+
+CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e =
+{
+  0,
+  F10IsMsgBasedC1eSupported,
+  F10InitializeMsgBasedC1e
+};
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
new file mode 100644
index 0000000..2b1efc6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c
@@ -0,0 +1,455 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 revision Dx specific utility functions.
+ *
+ * Provides numerous utility functions specific to family 10h rev D.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/F10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "amdlib.h"
+#include "Ids.h"
+#include "cpuRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "cpuF10PowerMgmt.h"
+#include "GeneralServices.h"
+#include "cpuEarlyInit.h"
+#include "cpuRegisters.h"
+#include "OptionMultiSocket.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+BOOLEAN
+F10CommonRevDSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+BOOLEAN
+F10CommonRevDGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+AGESA_STATUS
+F10RevDGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *MinFreqInMHz,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+UINT8
+F10CommonRevDGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Set down core register on a revision D processor.
+ *
+ * This function set F3x190 Downcore Control Register[5:0]
+ *
+ * @param[in]   FamilySpecificServices   The current Family Specific Services.
+ * @param[in]   Socket                   Socket ID.
+ * @param[in]   Module                   Module ID in socket.
+ * @param[in]   LeveledCores             Number of core.
+ * @param[in]   CoreLevelMode            Core level mode.
+ * @param[in]   StdHeader                Header for library and services.
+ *
+ * @retval      TRUE                     Down Core register is updated.
+ * @retval      FALSE                    Down Core register is not updated.
+ */
+BOOLEAN
+F10CommonRevDSetDownCoreRegister (
+  IN       CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+  IN       UINT32 *Socket,
+  IN       UINT32 *Module,
+  IN       UINT32 *LeveledCores,
+  IN       CORE_LEVELING_TYPE CoreLevelMode,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  UINT32    TempVar32_a;
+  UINT32    CoreDisableBits;
+  PCI_ADDR  PciAddress;
+  BOOLEAN   IsUpdated;
+  AGESA_STATUS AgesaStatus;
+
+  IsUpdated = FALSE;
+
+  switch (*LeveledCores) {
+  case 1:
+    CoreDisableBits = DOWNCORE_MASK_SINGLE;
+    break;
+  case 2:
+    CoreDisableBits = DOWNCORE_MASK_DUAL;
+    break;
+  case 3:
+    CoreDisableBits = DOWNCORE_MASK_TRI;
+    break;
+  case 4:
+    CoreDisableBits = DOWNCORE_MASK_FOUR;
+    break;
+  case 5:
+    CoreDisableBits = DOWNCORE_MASK_FIVE;
+    break;
+  default:
+    CoreDisableBits = 0;
+    break;
+  }
+
+  if (CoreDisableBits != 0) {
+    if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
+
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
+      if (TempVar32_a == 0) {
+        CoreDisableBits &= 0x1;
+      } else if (TempVar32_a == 1) {
+        CoreDisableBits &= 0x3;
+      } else if (TempVar32_a == 2) {
+        CoreDisableBits &= 0x7;
+      } else if (TempVar32_a == 3) {
+        CoreDisableBits &= 0x0F;
+      } else if (TempVar32_a == 4) {
+        CoreDisableBits &= 0x1F;
+      } else if (TempVar32_a == 5) {
+        CoreDisableBits &= 0x3F;
+      }
+      PciAddress.Address.Register = DOWNCORE_CTRL;
+      LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+      if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
+        TempVar32_a |= CoreDisableBits;
+        LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
+        IsUpdated = TRUE;
+      }
+    }
+  }
+
+  return IsUpdated;
+}
+
+
+CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling =
+{
+  0,
+  F10CommonRevDSetDownCoreRegister
+};
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Get CPU pstate current on a revision D processor.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
+ *
+ *    This function returns the ProcIddMax.
+ *
+ *  @param[in]     FamilySpecificServices    The current Family Specific Services.
+ *  @param[in]     Pstate                    The P-state to check.
+ *  @param[out]    ProcIddMax                P-state current in mA.
+ *  @param[in]     StdHeader                 Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                      P-state is enabled
+ *  @retval        FALSE                     P-state is disabled
+ */
+BOOLEAN
+F10CommonRevDGetProcIddMax (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       UINT8                  Pstate,
+     OUT   UINT32                 *ProcIddMax,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       IddDiv;
+  UINT32       CmpCap;
+  UINT32       MultiNodeCpu;
+  UINT32       NbCaps;
+  UINT32       MsrAddress;
+  UINT64       PstateMsr;
+  BOOLEAN      IsPstateEnabled;
+  PCI_ADDR     PciAddress;
+
+  IsPstateEnabled = FALSE;
+
+  MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
+  ASSERT (MsrAddress <= PS_MAX_REG);
+
+  LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
+  if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
+    OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
+    PciAddress.Address.Function = FUNC_3;
+    PciAddress.Address.Register = NB_CAPS_REG;
+    LibAmdPciRead (AccessWidth32, PciAddress, &NbCaps, StdHeader); // F3xE8
+
+    switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
+    case 0:
+      IddDiv = 1000;
+      break;
+    case 1:
+      IddDiv = 100;
+      break;
+    case 2:
+      IddDiv = 10;
+      break;
+    default:  // IddDiv = 3 is reserved. Use 10
+      IddDiv = 10;
+      break;
+    }
+    MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->MultiNodeCpu + 1);
+    CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapHi << 2);
+    CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &NbCaps)->CmpCapLo);
+    CmpCap++;
+    *ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
+    IsPstateEnabled = TRUE;
+  }
+  return IsPstateEnabled;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns whether or not BIOS is responsible for configuring the NB COFVID.
+ *
+ *  @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[in]   PciAddress               The northbridge to query by pci base address.
+ *  @param[out]  NbVidUpdateAll           Do all NbVids need to be updated
+ *  @param[in]   StdHeader                Header for library and services
+ *
+ *  @retval      TRUE                    Perform northbridge frequency and voltage config.
+ *  @retval      FALSE                   Do not configure them.
+ */
+BOOLEAN
+F10CommonRevDGetNbCofVidUpdate (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+  IN       PCI_ADDR *PciAddress,
+     OUT   BOOLEAN *NbVidUpdateAll,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NbVidUpdateAll = FALSE;
+  return FALSE;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Determines the NB clock on the desired node.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[in]     NbPstate                The NB P-state number to check.
+ *  @param[out]    FreqNumeratorInMHz      The desired node's frequency numerator in megahertz.
+ *  @param[out]    FreqDivisor             The desired node's frequency divisor.
+ *  @param[out]    VoltageInuV             The desired node's voltage in microvolts.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        TRUE                    NbPstate is valid
+ *  @retval        FALSE                   NbPstate is disabled or invalid
+ */
+BOOLEAN
+F10CommonRevDGetNbPstateInfo (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+  IN       UINT32                 NbPstate,
+     OUT   UINT32                 *FreqNumeratorInMHz,
+     OUT   UINT32                 *FreqDivisor,
+     OUT   UINT32                 *VoltageInuV,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32   LocalPciRegister;
+  UINT64   LocalMsrRegister;
+  BOOLEAN  PstateIsValid;
+
+  PstateIsValid = FALSE;
+  if (NbPstate == 0) {
+    PciAddress->Address.Function = FUNC_3;
+    PciAddress->Address.Register = CPTC0_REG;
+    LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+    *FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
+    *FreqDivisor = 1;
+    LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
+    *VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid)));
+    PstateIsValid = TRUE;
+  }
+  return PstateIsValid;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the node's minimum and maximum northbridge frequency.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
+ *
+ *  @param[in]     FamilySpecificServices  The current Family Specific Services.
+ *  @param[in]     PlatformConfig          Platform profile/build option config structure.
+ *  @param[in]     PciAddress              The segment, bus, and device numbers of the CPU in question.
+ *  @param[out]    MinFreqInMHz            The node's minimum northbridge frequency.
+ *  @param[out]    MaxFreqInMHz            The node's maximum northbridge frequency.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ *  @retval        AGESA_STATUS            Northbridge frequency is valid
+ */
+AGESA_STATUS
+F10RevDGetMinMaxNbFrequency (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       PLATFORM_CONFIGURATION *PlatformConfig,
+  IN       PCI_ADDR               *PciAddress,
+     OUT   UINT32                 *MinFreqInMHz,
+     OUT   UINT32                 *MaxFreqInMHz,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       LocalPciRegister;
+
+  PciAddress->Address.Function = FUNC_3;
+  PciAddress->Address.Register = CPTC0_REG;
+  LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
+  *MinFreqInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
+  *MaxFreqInMHz = *MinFreqInMHz;
+
+  return AGESA_SUCCESS;
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Get the number of physical cores of current processor.
+ *
+ * @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
+ *
+ * @param[in]      FamilySpecificServices         The current Family Specific Services.
+ * @param[in]      StdHeader                      Handle of Header for calling lib functions and services.
+ *
+ * @return         The number of physical cores.
+ */
+UINT8
+F10CommonRevDGetNumberOfPhysicalCores (
+  IN       CPU_SPECIFIC_SERVICES  *FamilySpecificServices,
+  IN       AMD_CONFIG_PARAMS      *StdHeader
+  )
+{
+  UINT32       CmpCap;
+  UINT32       CmpCapOnNode;
+  UINT32       Socket;
+  UINT32       Module;
+  UINT32       Core;
+  UINT32       LocalPciRegister;
+  PCI_ADDR     PciAddress;
+  AGESA_STATUS IgnoredSts;
+
+  CmpCap = 0;
+  IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
+  for (Module = 0; Module < GetPlatformNumberOfModules (); Module++) {
+    if (GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts)) {
+      PciAddress.Address.Function = FUNC_3;
+      PciAddress.Address.Register = NB_CAPS_REG;
+      LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
+      CmpCapOnNode = (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
+      CmpCapOnNode |= (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
+      CmpCapOnNode++;
+      CmpCap += CmpCapOnNode;
+    }
+  }
+  return ((UINT8) CmpCap);
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
new file mode 100644
index 0000000..1b4a1b8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyEquivalenceTable.c
@@ -0,0 +1,114 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Equivalence Table related data
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/Family/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuFamilyTranslation.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+STATIC CONST UINT16 ROMDATA CpuF10HyMicrocodeEquivalenceTable[] =
+{
+  0x1080, 0x1080,
+  0x1081, 0x1081,
+  0x1091, 0x1081
+};
+
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *  Returns the appropriate microcode patch equivalent ID table.
+ *
+ *  @CpuServiceMethod{::F_CPU_GET_FAMILY_SPECIFIC_ARRAY}.
+ *
+ *  @param[in]   FamilySpecificServices   The current Family Specific Services.
+ *  @param[out]  HyEquivalenceTablePtr    Points to the first entry in the table.
+ *  @param[out]  NumberOfElements         Number of valid entries in the table.
+ *  @param[in]   StdHeader                Header for library and services.
+ *
+ */
+VOID
+GetF10HyMicrocodeEquivalenceTable (
+  IN       CPU_SPECIFIC_SERVICES *FamilySpecificServices,
+     OUT   CONST VOID **HyEquivalenceTablePtr,
+     OUT   UINT8 *NumberOfElements,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  *NumberOfElements = ((sizeof (CpuF10HyMicrocodeEquivalenceTable) / sizeof (UINT16)) / 2);
+  *HyEquivalenceTablePtr = CpuF10HyMicrocodeEquivalenceTable;
+}
+
diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
new file mode 100644
index 0000000..02f65c9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c
@@ -0,0 +1,1294 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Family_10 Hydra Ht Phy tables with values as defined in BKDG
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  CPU/FAMILY/0x10
+ * @e \$Revision: 56279 $   @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "cpuRegisters.h"
+#include "Table.h"
+#include "Filecode.h"
+CODE_GROUP (G1_PEICC)
+RDATA_GROUP (G2_PEI)
+
+#define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                          E X P O R T E D    F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+//  HT   Phy   T a b l e s
+// -------------------------
+STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10HyHtPhyRegisters[] =
+{
+// 0x60:0x68
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0x60, 0x68,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0x70:0x78
+  {
+    HtPhyRangeRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_GT_C0                       // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0x70, 0x78,                           // Address
+      0x00000040,                           // regData
+      0x00000040,                           // regMask
+    }}
+  },
+// 0xC0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_ALL,               //
+      0xC0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }}
+  },
+// 0xD0
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                      // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_ALL,               //
+      0xD0,                                 // Address
+      0x40040000,                           // regData
+      0xe01F0000,                           // regMask
+    }}
+  },
+// 0xCF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL0_HT3,               //
+      0xCF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+// 0xDF
+// Default for HT3, unless overridden below.
+  {
+    HtPhyRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                         // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      HTPHY_LINKTYPE_SL1_HT3,               //
+      0xDF,                                 // Address
+      0x0000002A,                           // regData
+      0x000000FF,                           // regMask
+    }}
+  },
+
+//
+// All the entries for XmtRdPtr 6
+//
+
+// 0xCF
+// For HT frequencies 1200-1600 and NB Freq 1600, 1800
+  {
+    HtPhyFreqRegister,
+    {
+      AMD_FAMILY_10,                      // CpuFamily
+      AMD_F10_HY_ALL                          // CpuRevision
+    },
+    {AMD_PF_ALL},                           // platformFeatures
+    {{
+      (FREQ_RANGE_0 (HT_FREQUENCY_1200M, HT_FREQUENCY_1600M) | COUNT_RANGE_NONE),
+      (FREQ_RANGE_0 (HT_FREQUENCY_1600M, HT_FREQUENCY_1800M) | COUNT_RANGE_NONE),
+      (HTPHY_LINKTYPE_SL0_LINK0 | HTPHY_LINKTYPE_SL0_LINK2 | HTPHY_LINKTYPE_SL0_LINK3),
+      0xCF,                                 // Address
+      0x0000006A,                           // regData
+      0x000000FF,