[coreboot] New patch to review for coreboot: 30a4932 AGESA F15: AMD family15 AGESA code

Kerry Sheh (shekairui@gmail.com) gerrit at coreboot.org
Fri Jan 20 06:44:33 CET 2012


Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/554

-gerrit

commit 30a493289ad120f0556c7b8d167e9a09470d1929
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Fri Jan 20 13:57:48 2012 +0800

    AGESA F15: AMD family15 AGESA code
    
    AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
    AMD C32, G34, and AM3r2 Sockets are supported.
    
    Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/vendorcode/amd/agesa/Makefile.inc              |    1 +
 src/vendorcode/amd/agesa/f15/AGESA.h               | 3566 ++++++++++++++++++
 src/vendorcode/amd/agesa/f15/AMD.h                 |  480 +++
 src/vendorcode/amd/agesa/f15/Dispatcher.h          |   52 +
 src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h |  167 +
 .../amd/agesa/f15/Include/CommonReturns.h          |  125 +
 src/vendorcode/amd/agesa/f15/Include/Filecode.h    | 1174 ++++++
 .../amd/agesa/f15/Include/GeneralServices.h        |  202 ++
 .../amd/agesa/f15/Include/GnbInterface.h           |  100 +
 .../amd/agesa/f15/Include/GnbInterfaceStub.h       |  301 ++
 src/vendorcode/amd/agesa/f15/Include/GnbPage.h     | 1972 ++++++++++
 src/vendorcode/amd/agesa/f15/Include/Ids.h         | 1178 ++++++
 src/vendorcode/amd/agesa/f15/Include/IdsHt.h       |  124 +
 .../amd/agesa/f15/Include/MaranelloInstall.h       |  116 +
 .../amd/agesa/f15/Include/OptionApmInstall.h       |   87 +
 .../amd/agesa/f15/Include/OptionC6Install.h        |  164 +
 .../amd/agesa/f15/Include/OptionCpbInstall.h       |  170 +
 .../f15/Include/OptionCpuCacheFlushOnHaltInstall.h |  126 +
 .../f15/Include/OptionCpuCoreLevelingInstall.h     |  120 +
 .../agesa/f15/Include/OptionCpuFamiliesInstall.h   |  407 +++
 .../agesa/f15/Include/OptionCpuFeaturesInstall.h   |   80 +
 src/vendorcode/amd/agesa/f15/Include/OptionDmi.h   |   90 +
 .../amd/agesa/f15/Include/OptionDmiInstall.h       |  215 ++
 .../amd/agesa/f15/Include/OptionFamily10hInstall.h | 2058 +++++++++++
 .../agesa/f15/Include/OptionFamily15hEarlySample.h |  231 ++
 .../amd/agesa/f15/Include/OptionFamily15hInstall.h | 1570 ++++++++
 .../amd/agesa/f15/Include/OptionFchInstall.h       |  988 +++++
 .../amd/agesa/f15/Include/OptionGfxRecovery.h      |   82 +
 .../agesa/f15/Include/OptionGfxRecoveryInstall.h   |   54 +
 src/vendorcode/amd/agesa/f15/Include/OptionGnb.h   |  109 +
 .../amd/agesa/f15/Include/OptionGnbInstall.h       |  591 +++
 .../amd/agesa/f15/Include/OptionHtInstall.h        |  319 ++
 .../amd/agesa/f15/Include/OptionHwC1eInstall.h     |   81 +
 .../amd/agesa/f15/Include/OptionIdsInstall.h       |  588 +++
 .../amd/agesa/f15/Include/OptionIoCstateInstall.h  |  133 +
 .../agesa/f15/Include/OptionL3FeaturesInstall.h    |  119 +
 .../agesa/f15/Include/OptionLowPwrPstateInstall.h  |   89 +
 .../amd/agesa/f15/Include/OptionMemory.h           |  358 ++
 .../amd/agesa/f15/Include/OptionMemoryInstall.h    | 3778 ++++++++++++++++++++
 .../amd/agesa/f15/Include/OptionMemoryRecovery.h   |   63 +
 .../f15/Include/OptionMemoryRecoveryInstall.h      |  263 ++
 .../agesa/f15/Include/OptionMsgBasedC1eInstall.h   |  116 +
 .../amd/agesa/f15/Include/OptionMultiSocket.h      |  214 ++
 .../agesa/f15/Include/OptionMultiSocketInstall.h   |  105 +
 .../f15/Include/OptionPreserveMailboxInstall.h     |  123 +
 .../amd/agesa/f15/Include/OptionPstate.h           |  116 +
 .../agesa/f15/Include/OptionPstateHpcModeInstall.h |   88 +
 .../amd/agesa/f15/Include/OptionPstateInstall.h    |  264 ++
 .../amd/agesa/f15/Include/OptionS3ScriptInstall.h  |   92 +
 src/vendorcode/amd/agesa/f15/Include/OptionSlit.h  |   97 +
 .../amd/agesa/f15/Include/OptionSlitInstall.h      |   80 +
 src/vendorcode/amd/agesa/f15/Include/OptionSrat.h  |   83 +
 .../amd/agesa/f15/Include/OptionSratInstall.h      |   74 +
 .../amd/agesa/f15/Include/OptionSwC1eInstall.h     |   81 +
 src/vendorcode/amd/agesa/f15/Include/OptionWhea.h  |   84 +
 .../amd/agesa/f15/Include/OptionWheaInstall.h      |   75 +
 src/vendorcode/amd/agesa/f15/Include/Options.h     |   98 +
 src/vendorcode/amd/agesa/f15/Include/OptionsHt.h   |  110 +
 src/vendorcode/amd/agesa/f15/Include/OptionsPage.h |  378 ++
 .../amd/agesa/f15/Include/PlatformInstall.h        | 2837 +++++++++++++++
 .../f15/Include/PlatformMemoryConfiguration.h      |  499 +++
 .../amd/agesa/f15/Include/SanMarinoInstall.h       |  116 +
 .../amd/agesa/f15/Include/ScorpiusInstall.h        |  115 +
 src/vendorcode/amd/agesa/f15/Include/Topology.h    |  163 +
 src/vendorcode/amd/agesa/f15/Include/gcc-intrin.h  |  628 ++++
 .../f15/Legacy/PlatformMemoryConfiguration.inc     |  670 ++++
 .../amd/agesa/f15/Legacy/Proc/Dispatcher.c         |  159 +
 .../amd/agesa/f15/Legacy/Proc/agesaCallouts.c      |  441 +++
 .../amd/agesa/f15/Legacy/Proc/arch2008.asm         | 2676 ++++++++++++++
 .../amd/agesa/f15/Legacy/Proc/hobTransfer.c        |  393 ++
 src/vendorcode/amd/agesa/f15/Legacy/agesa.inc      | 2989 ++++++++++++++++
 src/vendorcode/amd/agesa/f15/Legacy/amd.inc        |  462 +++
 src/vendorcode/amd/agesa/f15/Legacy/bridge32.inc   |  577 +++
 src/vendorcode/amd/agesa/f15/Lib/IA32/amdlib32.asm |  671 ++++
 src/vendorcode/amd/agesa/f15/Lib/IA32/ms_shift.asm |  110 +
 src/vendorcode/amd/agesa/f15/Lib/IA32/msmemcpy.asm |   84 +
 src/vendorcode/amd/agesa/f15/Lib/amdlib.c          | 1355 +++++++
 src/vendorcode/amd/agesa/f15/Lib/amdlib.h          |  403 +++
 src/vendorcode/amd/agesa/f15/Lib/helper.c          |   68 +
 src/vendorcode/amd/agesa/f15/Lib/x64/amdlib64.asm  |  591 +++
 src/vendorcode/amd/agesa/f15/MainPage.h            |  120 +
 src/vendorcode/amd/agesa/f15/Makefile.inc          |  532 +++
 src/vendorcode/amd/agesa/f15/Porting.h             |  289 ++
 .../f15/Proc/CPU/Family/0x10/F10InitEarlyTable.c   |  126 +
 .../agesa/f15/Proc/CPU/Family/0x10/F10IoCstate.c   |  300 ++
 .../Proc/CPU/Family/0x10/F10MultiLinkPciTables.c   | 1537 ++++++++
 .../f15/Proc/CPU/Family/0x10/F10PackageType.h      |   84 +
 .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c  |  176 +
 .../f15/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h  |   78 +
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.c    |  243 ++
 .../CPU/Family/0x10/F10PmDualPlaneOnlySupport.h    |   78 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c   |  296 ++
 .../f15/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h   |   77 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.c   |  185 +
 .../f15/Proc/CPU/Family/0x10/F10PmNbPstateInit.h   |   77 +
 .../Proc/CPU/Family/0x10/F10SingleLinkPciTables.c  | 2251 ++++++++++++
 .../Family/0x10/RevC/BL/F10BlCacheFlushOnHalt.c    |  151 +
 .../Family/0x10/RevC/BL/F10BlEquivalenceTable.c    |  106 +
 .../CPU/Family/0x10/RevC/BL/F10BlHtPhyTables.c     |  122 +
 .../CPU/Family/0x10/RevC/BL/F10BlLogicalIdTables.c |  106 +
 .../0x10/RevC/BL/F10BlMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlMsrTables.c  |  106 +
 .../Proc/CPU/Family/0x10/RevC/BL/F10BlPciTables.c  |  196 +
 .../Family/0x10/RevC/DA/F10DaCacheFlushOnHalt.c    |  144 +
 .../Family/0x10/RevC/DA/F10DaEquivalenceTable.c    |  107 +
 .../CPU/Family/0x10/RevC/DA/F10DaHtPhyTables.c     |  283 ++
 .../CPU/Family/0x10/RevC/DA/F10DaLogicalIdTables.c |  107 +
 .../0x10/RevC/DA/F10DaMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaMsrTables.c  |  106 +
 .../Proc/CPU/Family/0x10/RevC/DA/F10DaPciTables.c  |  192 +
 .../Family/0x10/RevC/F10MicrocodePatch01000085.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c6.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c7.c   | 1037 ++++++
 .../Family/0x10/RevC/F10MicrocodePatch010000c8.c   | 1037 ++++++
 .../Proc/CPU/Family/0x10/RevC/F10RevCHtPhyTables.c |  439 +++
 .../f15/Proc/CPU/Family/0x10/RevC/F10RevCHwC1e.c   |  205 ++
 .../Proc/CPU/Family/0x10/RevC/F10RevCMsrTables.c   |  133 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCPciTables.c   |  265 ++
 .../f15/Proc/CPU/Family/0x10/RevC/F10RevCSwC1e.c   |  181 +
 .../Proc/CPU/Family/0x10/RevC/F10RevCUtilities.c   |  495 +++
 .../Family/0x10/RevC/RB/F10RbEquivalenceTable.c    |  110 +
 .../CPU/Family/0x10/RevC/RB/F10RbHtPhyTables.c     |  120 +
 .../CPU/Family/0x10/RevC/RB/F10RbLogicalIdTables.c |  114 +
 .../0x10/RevC/RB/F10RbMicrocodePatchTables.c       |  106 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbMsrTables.c  |  120 +
 .../Proc/CPU/Family/0x10/RevC/RB/F10RbPciTables.c  |  234 ++
 .../Family/0x10/RevD/F10MicrocodePatch010000c5.c   | 1039 ++++++
 .../Family/0x10/RevD/F10MicrocodePatch010000d9.c   | 1066 ++++++
 .../f15/Proc/CPU/Family/0x10/RevD/F10RevD32.asm    |  113 +
 .../f15/Proc/CPU/Family/0x10/RevD/F10RevD64.asm    |  127 +
 .../Proc/CPU/Family/0x10/RevD/F10RevDL3Features.c  |  516 +++
 .../Proc/CPU/Family/0x10/RevD/F10RevDMsgBasedC1e.c |  282 ++
 .../Proc/CPU/Family/0x10/RevD/F10RevDUtilities.c   |  455 +++
 .../Family/0x10/RevD/HY/F10HyEquivalenceTable.c    |  114 +
 .../CPU/Family/0x10/RevD/HY/F10HyHtPhyTables.c     | 1294 +++++++
 .../CPU/Family/0x10/RevD/HY/F10HyInitEarlyTable.c  |  144 +
 .../CPU/Family/0x10/RevD/HY/F10HyLogicalIdTables.c |  116 +
 .../0x10/RevD/HY/F10HyMicrocodePatchTables.c       |  114 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c  |  137 +
 .../Proc/CPU/Family/0x10/RevD/HY/F10HyPciTables.c  |  384 ++
 .../Family/0x10/RevE/F10MicrocodePatch010000bf.c   | 1039 ++++++
 .../Proc/CPU/Family/0x10/RevE/F10RevEHtPhyTables.c |  373 ++
 .../Proc/CPU/Family/0x10/RevE/F10RevEMsrTables.c   |  134 +
 .../Proc/CPU/Family/0x10/RevE/F10RevEPciTables.c   |  225 ++
 .../Proc/CPU/Family/0x10/RevE/F10RevEUtilities.c   |  396 ++
 .../Family/0x10/RevE/PH/F10PhEquivalenceTable.c    |  105 +
 .../CPU/Family/0x10/RevE/PH/F10PhHtPhyTables.c     |  117 +
 .../CPU/Family/0x10/RevE/PH/F10PhLogicalIdTables.c |   96 +
 .../0x10/RevE/PH/F10PhMicrocodePatchTables.c       |  105 +
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.c   |  329 ++
 .../Proc/CPU/Family/0x10/cpuCommonF10Utilities.h   |  120 +
 .../agesa/f15/Proc/CPU/Family/0x10/cpuF10BrandId.c |  160 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAm3.c    |  335 ++
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdAsb2.c   |  136 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdC32.c    |  135 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdFr1207.c |  179 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdG34.c    |  127 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g3.c   |  128 +
 .../f15/Proc/CPU/Family/0x10/cpuF10BrandIdS1g4.c   |  142 +
 .../f15/Proc/CPU/Family/0x10/cpuF10CacheDefaults.c |  131 +
 .../Proc/CPU/Family/0x10/cpuF10CacheFlushOnHalt.c  |  167 +
 .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Cpb.c |  169 +
 .../amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c |  519 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.c     |  454 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10EarlyInit.h     |   79 +
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.c   |  393 ++
 .../Proc/CPU/Family/0x10/cpuF10FeatureLeveling.h   |  195 +
 .../f15/Proc/CPU/Family/0x10/cpuF10HtPhyTables.c   |  751 ++++
 .../f15/Proc/CPU/Family/0x10/cpuF10MsrTables.c     |  289 ++
 .../f15/Proc/CPU/Family/0x10/cpuF10PciTables.c     |  772 ++++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.c    |  411 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerCheck.h    |   83 +
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerMgmt.h     |  547 +++
 .../CPU/Family/0x10/cpuF10PowerMgmtSystemTables.c  |  182 +
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.c    |  485 +++
 .../f15/Proc/CPU/Family/0x10/cpuF10PowerPlane.h    |   77 +
 .../agesa/f15/Proc/CPU/Family/0x10/cpuF10Pstate.c  |  894 +++++
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.c   |  124 +
 .../Proc/CPU/Family/0x10/cpuF10SoftwareThermal.h   |   79 +
 .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.c     | 1176 ++++++
 .../f15/Proc/CPU/Family/0x10/cpuF10Utilities.h     |  206 ++
 .../CPU/Family/0x10/cpuF10WheaInitDataTables.c     |  128 +
 .../Proc/CPU/Family/0x10/cpuF10WorkaroundsTable.c  |  184 +
 .../f15/Proc/CPU/Family/0x15/F15PackageType.h      |   79 +
 .../f15/Proc/CPU/Family/0x15/F15PstateHpcMode.c    |  208 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrC6State.c     |  186 +
 .../agesa/f15/Proc/CPU/Family/0x15/OR/F15OrCpb.c   |  183 +
 .../Proc/CPU/Family/0x15/OR/F15OrEarlySamples.c    |  834 +++++
 .../CPU/Family/0x15/OR/F15OrEquivalenceTable.c     |  135 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrHtPhyTables.c |  833 +++++
 .../Proc/CPU/Family/0x15/OR/F15OrInitEarlyTable.c  |  187 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrIoCstate.c    |  377 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrL3Features.c  |  549 +++
 .../Proc/CPU/Family/0x15/OR/F15OrLogicalIdTables.c |  120 +
 .../Proc/CPU/Family/0x15/OR/F15OrLowPwrPstate.c    |  234 ++
 .../Family/0x15/OR/F15OrMicrocodePatch06000425.c   | 2674 ++++++++++++++
 .../0x15/OR/F15OrMicrocodePatch0600050D_Enc.c      | 2675 ++++++++++++++
 .../0x15/OR/F15OrMicrocodePatch06000624_Enc.c      | 2701 ++++++++++++++
 .../CPU/Family/0x15/OR/F15OrMicrocodePatchTables.c |  112 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrMsgBasedC1e.c |  305 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrMsrTables.c   |  234 ++
 .../CPU/Family/0x15/OR/F15OrMultiLinkPciTables.c   |  749 ++++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPciTables.c   |  962 +++++
 .../Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.c  |  317 ++
 .../Proc/CPU/Family/0x15/OR/F15OrPmNbCofVidInit.h  |   77 +
 .../Family/0x15/OR/F15OrPowerMgmtSystemTables.c    |  177 +
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.c  |  236 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrPowerPlane.h  |   77 +
 .../Proc/CPU/Family/0x15/OR/F15OrSharedMsrTable.c  |  376 ++
 .../CPU/Family/0x15/OR/F15OrSingleLinkPciTables.c  |  321 ++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.c   |  939 +++++
 .../f15/Proc/CPU/Family/0x15/OR/F15OrUtilities.h   |  169 +
 .../CPU/Family/0x15/OR/F15OrWorkaroundsTable.c     |  134 +
 .../CPU/Family/0x15/OR/cpuF15OrCacheFlushOnHalt.c  |  184 +
 .../CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.c    |  250 ++
 .../CPU/Family/0x15/OR/cpuF15OrCoreAfterReset.h    |   79 +
 .../f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c      |  419 +++
 .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.c   |  422 +++
 .../CPU/Family/0x15/OR/cpuF15OrFeatureLeveling.h   |  211 ++
 .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.c |  349 ++
 .../Proc/CPU/Family/0x15/OR/cpuF15OrNbAfterReset.h |   79 +
 .../Proc/CPU/Family/0x15/OR/cpuF15OrPowerMgmt.h    |  534 +++
 .../f15/Proc/CPU/Family/0x15/OR/cpuF15OrPstate.c   |  920 +++++
 .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.c   |  128 +
 .../CPU/Family/0x15/OR/cpuF15OrSoftwareThermal.h   |   79 +
 .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.c   |  181 +
 .../Proc/CPU/Family/0x15/cpuCommonF15Utilities.h   |   92 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Apm.c |  126 +
 .../agesa/f15/Proc/CPU/Family/0x15/cpuF15BrandId.c |  223 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15CacheDefaults.c |  198 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.c |  124 +
 .../amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15Dmi.h |   77 +
 .../f15/Proc/CPU/Family/0x15/cpuF15MsrTables.c     |  136 +
 .../f15/Proc/CPU/Family/0x15/cpuF15PciTables.c     |  206 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.c    |  441 +++
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerCheck.h    |   82 +
 .../f15/Proc/CPU/Family/0x15/cpuF15PowerMgmt.h     |  293 ++
 .../f15/Proc/CPU/Family/0x15/cpuF15Utilities.c     | 1178 ++++++
 .../f15/Proc/CPU/Family/0x15/cpuF15Utilities.h     |  160 +
 .../CPU/Family/0x15/cpuF15WheaInitDataTables.c     |  128 +
 .../agesa/f15/Proc/CPU/Family/cpuFamRegisters.h    |  259 ++
 .../agesa/f15/Proc/CPU/Feature/PreserveMailbox.c   |  219 ++
 .../agesa/f15/Proc/CPU/Feature/PreserveMailbox.h   |   98 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuApm.c        |  205 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuApm.h        |  130 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.c    |  261 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuC6State.h    |  157 +
 .../f15/Proc/CPU/Feature/cpuCacheFlushOnHalt.c     |  200 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c  |  752 ++++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.h  |  139 +
 .../agesa/f15/Proc/CPU/Feature/cpuCoreLeveling.c   |  363 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.c        |  176 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuCpb.h        |  134 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuDmi.c        |  862 +++++
 .../f15/Proc/CPU/Feature/cpuFeatureLeveling.c      |  266 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.c   |  199 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuFeatures.h   |  269 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.c      |  181 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuHwC1e.h      |  126 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.c   |  208 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuIoCstate.h   |  284 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.c |  350 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuL3Features.h |  361 ++
 .../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.c   |  224 ++
 .../agesa/f15/Proc/CPU/Feature/cpuLowPwrPstate.h   |  130 +
 .../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.c    |  212 ++
 .../agesa/f15/Proc/CPU/Feature/cpuMsgBasedC1e.h    |  128 +
 .../agesa/f15/Proc/CPU/Feature/cpuPstateGather.c   |  411 +++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.c  |  221 ++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateHpcMode.h  |  101 +
 .../agesa/f15/Proc/CPU/Feature/cpuPstateLeveling.c | 1099 ++++++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateTables.c   |  891 +++++
 .../agesa/f15/Proc/CPU/Feature/cpuPstateTables.h   |  331 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSlit.c       |  397 ++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSrat.c       |  617 ++++
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.c      |  178 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuSwC1e.h      |  120 +
 .../amd/agesa/f15/Proc/CPU/Feature/cpuWhea.c       |  284 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/S3.c         | 1233 +++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/S3.h         |  395 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/Table.c      | 1734 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/Table.h      | 1296 +++++++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.asm   |  362 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt.c     |  306 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cahalt64.asm |  174 +
 .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c      | 1443 ++++++++
 .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.h      |  304 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBist.c    |  172 +
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuBrandId.c |  313 ++
 .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.c          |  411 +++
 .../amd/agesa/f15/Proc/CPU/cpuEarlyInit.h          |  305 ++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEnvInit.h |   74 +
 .../amd/agesa/f15/Proc/CPU/cpuEventLog.c           |  397 ++
 .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.c  |  484 +++
 .../amd/agesa/f15/Proc/CPU/cpuFamilyTranslation.h  | 1008 ++++++
 .../amd/agesa/f15/Proc/CPU/cpuGeneralServices.c    | 1237 +++++++
 .../amd/agesa/f15/Proc/CPU/cpuInitEarlyTable.c     |  125 +
 .../amd/agesa/f15/Proc/CPU/cpuLateInit.c           |  394 ++
 .../amd/agesa/f15/Proc/CPU/cpuLateInit.h           |  888 +++++
 .../amd/agesa/f15/Proc/CPU/cpuMicrocodePatch.c     |  420 +++
 src/vendorcode/amd/agesa/f15/Proc/CPU/cpuPage.h    |   62 +
 .../amd/agesa/f15/Proc/CPU/cpuPostInit.c           |  493 +++
 .../amd/agesa/f15/Proc/CPU/cpuPostInit.h           |  239 ++
 .../amd/agesa/f15/Proc/CPU/cpuPowerMgmt.c          |  252 ++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.c   |  570 +++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtMultiSocket.h   |  127 +
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.c  |  325 ++
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSingleSocket.h  |  128 +
 .../agesa/f15/Proc/CPU/cpuPowerMgmtSystemTables.h  |   93 +
 .../amd/agesa/f15/Proc/CPU/cpuRegisters.h          |  407 +++
 .../amd/agesa/f15/Proc/CPU/cpuServices.h           |  334 ++
 .../amd/agesa/f15/Proc/CPU/cpuWarmReset.c          |  235 ++
 .../amd/agesa/f15/Proc/CPU/heapManager.c           |  885 +++++
 .../amd/agesa/f15/Proc/CPU/heapManager.h           |  243 ++
 src/vendorcode/amd/agesa/f15/Proc/Common/AmdFch.h  |   66 +
 .../amd/agesa/f15/Proc/Common/AmdInitEarly.c       |  316 ++
 .../amd/agesa/f15/Proc/Common/AmdInitEnv.c         |  182 +
 .../amd/agesa/f15/Proc/Common/AmdInitLate.c        |  296 ++
 .../amd/agesa/f15/Proc/Common/AmdInitMid.c         |  170 +
 .../amd/agesa/f15/Proc/Common/AmdInitPost.c        |  341 ++
 .../amd/agesa/f15/Proc/Common/AmdInitRecovery.c    |  169 +
 .../amd/agesa/f15/Proc/Common/AmdInitReset.c       |  253 ++
 .../amd/agesa/f15/Proc/Common/AmdInitResume.c      |  239 ++
 .../amd/agesa/f15/Proc/Common/AmdLateRunApTask.c   |  160 +
 .../amd/agesa/f15/Proc/Common/AmdS3LateRestore.c   |  218 ++
 .../amd/agesa/f15/Proc/Common/AmdS3Save.c          |  388 ++
 .../amd/agesa/f15/Proc/Common/CommonInits.c        |  139 +
 .../amd/agesa/f15/Proc/Common/CommonInits.h        |   66 +
 .../amd/agesa/f15/Proc/Common/CommonPage.h         |  117 +
 .../amd/agesa/f15/Proc/Common/CommonReturns.c      |  213 ++
 .../amd/agesa/f15/Proc/Common/CreateStruct.c       |  314 ++
 .../amd/agesa/f15/Proc/Common/CreateStruct.h       |  196 +
 .../amd/agesa/f15/Proc/Common/S3RestoreState.c     |  442 +++
 .../amd/agesa/f15/Proc/Common/S3SaveState.c        |  652 ++++
 .../amd/agesa/f15/Proc/Common/S3SaveState.h        |  361 ++
 .../agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.c    |  163 +
 .../agesa/f15/Proc/HT/Fam10/htNbCoherentFam10.h    |   67 +
 .../amd/agesa/f15/Proc/HT/Fam10/htNbFam10.c        |  485 +++
 .../agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.c |  121 +
 .../agesa/f15/Proc/HT/Fam10/htNbNonCoherentFam10.h |   58 +
 .../f15/Proc/HT/Fam10/htNbOptimizationFam10.c      |  222 ++
 .../f15/Proc/HT/Fam10/htNbOptimizationFam10.h      |   74 +
 .../amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.c  |  402 +++
 .../amd/agesa/f15/Proc/HT/Fam10/htNbSystemFam10.h  |   91 +
 .../agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.c   |  445 +++
 .../agesa/f15/Proc/HT/Fam10/htNbUtilitiesFam10.h   |  129 +
 .../agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.c    |  162 +
 .../agesa/f15/Proc/HT/Fam15/htNbCoherentFam15.h    |   67 +
 .../amd/agesa/f15/Proc/HT/Fam15/htNbFam15.c        |  248 ++
 .../agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.c |  120 +
 .../agesa/f15/Proc/HT/Fam15/htNbNonCoherentFam15.h |   58 +
 .../f15/Proc/HT/Fam15/htNbOptimizationFam15.c      |  148 +
 .../f15/Proc/HT/Fam15/htNbOptimizationFam15.h      |   63 +
 .../amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.c  |  373 ++
 .../amd/agesa/f15/Proc/HT/Fam15/htNbSystemFam15.h  |   93 +
 .../agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.c   |  453 +++
 .../agesa/f15/Proc/HT/Fam15/htNbUtilitiesFam15.h   |  137 +
 .../f15/Proc/HT/Features/htFeatDynamicDiscovery.c  |  783 ++++
 .../f15/Proc/HT/Features/htFeatDynamicDiscovery.h  |   80 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatGanging.c |  218 ++
 .../amd/agesa/f15/Proc/HT/Features/htFeatGanging.h |   81 +
 .../agesa/f15/Proc/HT/Features/htFeatNoncoherent.c |  375 ++
 .../agesa/f15/Proc/HT/Features/htFeatNoncoherent.h |   81 +
 .../f15/Proc/HT/Features/htFeatOptimization.c      |  890 +++++
 .../f15/Proc/HT/Features/htFeatOptimization.h      |  140 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatRouting.c |  493 +++
 .../amd/agesa/f15/Proc/HT/Features/htFeatRouting.h |   90 +
 .../amd/agesa/f15/Proc/HT/Features/htFeatSets.c    |  135 +
 .../agesa/f15/Proc/HT/Features/htFeatSublinks.c    |  232 ++
 .../agesa/f15/Proc/HT/Features/htFeatSublinks.h    |   80 +
 .../Proc/HT/Features/htFeatTrafficDistribution.c   |  420 +++
 .../Proc/HT/Features/htFeatTrafficDistribution.h   |   79 +
 .../amd/agesa/f15/Proc/HT/Features/htIds.c         |  150 +
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.c  |  492 +++
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbCoherent.h  |  178 +
 .../agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.c   |  142 +
 .../agesa/f15/Proc/HT/NbCommon/htNbNonCoherent.h   |   62 +
 .../agesa/f15/Proc/HT/NbCommon/htNbOptimization.c  |  258 ++
 .../agesa/f15/Proc/HT/NbCommon/htNbOptimization.h  |   91 +
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.c |  335 ++
 .../amd/agesa/f15/Proc/HT/NbCommon/htNbUtilities.h |  108 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.c      |  112 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htFeat.h      |  562 +++
 src/vendorcode/amd/agesa/f15/Proc/HT/htGraph.h     |  144 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph.c        |  199 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph1.c       |   70 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph2.c       |   71 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph3Line.c   |   76 +
 .../agesa/f15/Proc/HT/htGraph/htGraph3Triangle.c   |   77 +
 .../agesa/f15/Proc/HT/htGraph/htGraph4Degenerate.c |   80 +
 .../f15/Proc/HT/htGraph/htGraph4FullyConnected.c   |   83 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Kite.c   |   81 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Line.c   |   80 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Square.c |   80 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph4Star.c   |   80 +
 .../f15/Proc/HT/htGraph/htGraph5FullyConnected.c   |   80 +
 .../f15/Proc/HT/htGraph/htGraph5TwistedLadder.c    |   89 +
 .../f15/Proc/HT/htGraph/htGraph6DoubloonLower.c    |   75 +
 .../f15/Proc/HT/htGraph/htGraph6DoubloonUpper.c    |   75 +
 .../f15/Proc/HT/htGraph/htGraph6FullyConnected.c   |   86 +
 .../f15/Proc/HT/htGraph/htGraph6TwinTriangles.c    |   92 +
 .../f15/Proc/HT/htGraph/htGraph6TwistedLadder.c    |   92 +
 .../f15/Proc/HT/htGraph/htGraph7FullyConnected.c   |   78 +
 .../f15/Proc/HT/htGraph/htGraph7TwistedLadder.c    |   95 +
 .../agesa/f15/Proc/HT/htGraph/htGraph8DoubloonM.c  |   76 +
 .../f15/Proc/HT/htGraph/htGraph8FullyConnected.c   |   79 +
 .../amd/agesa/f15/Proc/HT/htGraph/htGraph8Ladder.c |   96 +
 .../Proc/HT/htGraph/htGraph8TwinFullyFourWays.c    |   96 +
 .../f15/Proc/HT/htGraph/htGraph8TwistedLadder.c    |   95 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.c |  263 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htInterface.h |  490 +++
 .../amd/agesa/f15/Proc/HT/htInterfaceCoherent.c    |  264 ++
 .../amd/agesa/f15/Proc/HT/htInterfaceCoherent.h    |  115 +
 .../amd/agesa/f15/Proc/HT/htInterfaceGeneral.c     |  539 +++
 .../amd/agesa/f15/Proc/HT/htInterfaceGeneral.h     |  162 +
 .../amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.c |  394 ++
 .../amd/agesa/f15/Proc/HT/htInterfaceNonCoherent.h |  138 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htMain.c      |  579 +++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNb.c        |  248 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNb.h        | 1134 ++++++
 .../amd/agesa/f15/Proc/HT/htNbCommonHardware.h     |  123 +
 src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.c    |  670 ++++
 src/vendorcode/amd/agesa/f15/Proc/HT/htNotify.h    |  298 ++
 src/vendorcode/amd/agesa/f15/Proc/HT/htPage.h      |   65 +
 .../amd/agesa/f15/Proc/HT/htTopologies.h           |   72 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/IdsLib.h     |  125 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/IdsPage.h    |   58 +
 src/vendorcode/amd/agesa/f15/Proc/IDS/OptionsIds.h |   80 +
 .../amd/agesa/f15/Proc/Mem/Ardk/C32/marc32_3.c     |  593 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/C32/mauc32_3.c     |  356 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/masda2.c        |  206 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/masda3.c        |  260 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DA/mauda3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr2.c        |  273 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/mardr3.c        |  428 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/DR/maudr3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/HY/marhy3.c        |  577 +++
 .../amd/agesa/f15/Proc/Mem/Ardk/HY/mauhy3.c        |  356 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/OR/maror3.c        |  105 +
 .../amd/agesa/f15/Proc/Mem/Ardk/OR/mauor3.c        |  106 +
 .../amd/agesa/f15/Proc/Mem/Ardk/PH/masph3.c        |  260 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/PH/mauPh3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/RB/masRb3.c        |  259 ++
 .../amd/agesa/f15/Proc/Mem/Ardk/RB/mauRb3.c        |  258 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ardk/ma.c    |  146 +
 .../amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.c    |  212 ++
 .../amd/agesa/f15/Proc/Mem/Feat/CHINTLV/mfchi.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.c    |  356 ++
 .../amd/agesa/f15/Proc/Mem/Feat/CSINTLV/mfcsi.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c        |  623 ++++
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.c        |  290 ++
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfecc.h        |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/ECC/mfemp.c        |  178 +
 .../f15/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c     |  207 ++
 .../agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.c  |  549 +++
 .../agesa/f15/Proc/Mem/Feat/IDENDIMM/mfidendimm.h  |  108 +
 .../agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.c    |  164 +
 .../agesa/f15/Proc/Mem/Feat/INTLVRN/mfintlvrn.h    |   81 +
 .../amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.c  |  173 +
 .../amd/agesa/f15/Proc/Mem/Feat/LVDDR3/mflvddr3.h  |   79 +
 .../amd/agesa/f15/Proc/Mem/Feat/MEMCLR/mfmemclr.c  |  152 +
 .../amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.c    |  244 ++
 .../amd/agesa/f15/Proc/Mem/Feat/NDINTLV/mfndi.h    |   79 +
 .../f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c      |  175 +
 .../f15/Proc/Mem/Feat/ODTHERMAL/mfodthermal.h      |   78 +
 .../amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.c    |  170 +
 .../amd/agesa/f15/Proc/Mem/Feat/OLSPARE/mfspr.h    |   80 +
 .../f15/Proc/Mem/Feat/PARTRN/mfParallelTraining.c  |  289 ++
 .../f15/Proc/Mem/Feat/PARTRN/mfStandardTraining.c  |   86 +
 .../amd/agesa/f15/Proc/Mem/Feat/S3/mfs3.c          |  719 ++++
 .../amd/agesa/f15/Proc/Mem/Feat/TABLE/mftds.c      |  398 ++
 .../amd/agesa/f15/Proc/Mem/Main/C32/mmflowC32.c    |  380 ++
 .../amd/agesa/f15/Proc/Mem/Main/DA/mmflowda.c      |  382 ++
 .../amd/agesa/f15/Proc/Mem/Main/DR/mmflowdr.c      |  376 ++
 .../amd/agesa/f15/Proc/Mem/Main/HY/mmflowhy.c      |  380 ++
 .../amd/agesa/f15/Proc/Mem/Main/OR/mmflowor.c      |  423 +++
 .../amd/agesa/f15/Proc/Mem/Main/PH/mmflowPh.c      |  382 ++
 .../amd/agesa/f15/Proc/Mem/Main/RB/mmflowRb.c      |  382 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mdef.c  |  147 +
 .../amd/agesa/f15/Proc/Mem/Main/merrhdl.c          |  188 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/minit.c |  138 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mm.c    |  253 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmConditionalPso.c |  696 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mmEcc.c |  136 +
 .../amd/agesa/f15/Proc/Mem/Main/mmExcludeDimm.c    |  245 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.c         |  292 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmLvDdr3.h         |   86 +
 .../amd/agesa/f15/Proc/Mem/Main/mmMemClr.c         |  119 +
 .../amd/agesa/f15/Proc/Mem/Main/mmMemRestore.c     |  607 ++++
 .../amd/agesa/f15/Proc/Mem/Main/mmNodeInterleave.c |  147 +
 .../amd/agesa/f15/Proc/Mem/Main/mmOnlineSpare.c    |  166 +
 .../agesa/f15/Proc/Mem/Main/mmParallelTraining.c   |  289 ++
 .../agesa/f15/Proc/Mem/Main/mmStandardTraining.c   |  241 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmUmaAlloc.c       |  246 ++
 .../amd/agesa/f15/Proc/Mem/Main/mmflow.c           |  395 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.asm  |  497 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/mu.c    |  256 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c   |  721 ++++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnParTrainc32.c  |  228 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.c        |  746 ++++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnS3c32.h        |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnc32.c          |  493 +++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnc32.h          |  212 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mndctc32.c       |  454 +++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnflowc32.c      |  135 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnidendimmc32.c  |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnmctc32.c       |  214 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnotc32.c        |  246 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnphyc32.c       |  222 ++
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnprotoc32.c     |   66 +
 .../amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c       |  636 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnParTrainDa.c    |  225 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.c          |  747 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnS3da.h          |   84 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.c |  498 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnda.h |  209 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mndctda.c         |  468 +++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnflowda.c        |  139 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnidendimmda.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnmctda.c         |  208 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnotda.c          |  200 ++
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnprotoda.c       |   86 +
 .../amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c         |  584 +++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnParTrainDr.c    |  225 ++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.c          |  715 ++++
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnS3dr.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mndctdr.c         |  514 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.c |  491 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mndr.h |  198 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnflowdr.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnidendimmdr.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnmctdr.c         |  194 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnotdr.c          |  199 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnprotodr.c       |  169 +
 .../amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c         |  554 +++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnParTrainHy.c    |  228 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.c          |  746 ++++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnS3hy.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mndcthy.c         |  456 +++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnflowhy.c        |  134 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.c |  496 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnhy.h |  212 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnidendimmhy.c    |  140 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnmcthy.c         |  213 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnothy.c          |  247 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnphyhy.c         |  238 ++
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnprotohy.c       |   66 +
 .../amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c         |  639 ++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnS3or.h          |   85 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mndctor.c         |  975 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnflowor.c        |  134 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnidendimmor.c    |  218 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnmctor.c         |  340 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.c |  640 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnor.h |  361 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnotor.c          |  280 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnpartrainor.c    |  219 ++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnphyor.c         |  849 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnprotoor.c       |   99 +
 .../amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c         |  922 +++++
 .../amd/agesa/f15/Proc/Mem/NB/OR/mns3or.c          | 1257 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.c |  503 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/PH/mnPh.h |  129 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.c          |  775 ++++
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnS3Ph.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnflowPh.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnidendimmPh.c    |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/PH/mnmctPh.c         |  177 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.c |  503 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/RB/mnRb.h |  124 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.c          |  775 ++++
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnS3Rb.h          |   84 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnflowRb.c        |  141 +
 .../amd/agesa/f15/Proc/Mem/NB/RB/mnidendimmRb.c    |  141 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mn.c      |  530 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnS3.c    | 1356 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mndct.c   | 3453 ++++++++++++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnfeat.c  | 1737 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnflow.c  |  333 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnmct.c   | 1286 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnphy.c   | 2041 +++++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/NB/mnreg.c   |  551 +++
 .../amd/agesa/f15/Proc/Mem/NB/mntrain2.c           |  132 +
 .../amd/agesa/f15/Proc/Mem/NB/mntrain3.c           |  244 ++
 .../amd/agesa/f15/Proc/Mem/Ps/C32/mprc32_3.c       |  325 ++
 .../amd/agesa/f15/Proc/Mem/Ps/C32/mpuc32_3.c       |  204 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda2.c          |  160 +
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpsda3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DA/mpuda3.c          |  208 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr2.c          |  165 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mprdr3.c          |  204 ++
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpsdr3.c          |  191 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr2.c          |  165 +
 .../amd/agesa/f15/Proc/Mem/Ps/DR/mpudr3.c          |  160 +
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mprhy3.c          |  324 ++
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mpshy3.c          |  220 ++
 .../amd/agesa/f15/Proc/Mem/Ps/HY/mpuhy3.c          |  198 +
 .../amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpSorA3.c     |  223 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/AM3/mpUorA3.c     |  278 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpLorC3.c     |  320 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpRorC3.c     |  653 ++++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/C32/mpUorC3.c     |  343 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpLorG3.c     |  336 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpRorG3.c     |  743 ++++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/G34/mpUorG3.c     |  351 ++
 .../amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c           |  228 ++
 .../amd/agesa/f15/Proc/Mem/Ps/PH/mpsph3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/PH/mpuph3.c          |  209 ++
 .../amd/agesa/f15/Proc/Mem/Ps/RB/mpsRb3.c          |  255 ++
 .../amd/agesa/f15/Proc/Mem/Ps/RB/mpuRb3.c          |  209 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mp.c      | 1225 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplribt.c |  206 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnlr.c |  117 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mplrnpr.c |  117 +
 .../amd/agesa/f15/Proc/Mem/Ps/mpmaxfreq.c          |  303 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpmr0.c   |  196 +
 .../amd/agesa/f15/Proc/Mem/Ps/mpodtpat.c           |  213 ++
 .../amd/agesa/f15/Proc/Mem/Ps/mprc10opspd.c        |  184 +
 .../amd/agesa/f15/Proc/Mem/Ps/mprc2ibt.c           |  236 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mprtt.c   |  270 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mps2d.c   |  220 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpsao.c   |  227 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/mpseeds.c |  211 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.c         |  233 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mt2.h         |  125 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.c       |  163 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtot2.h       |   89 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.c      | 1118 ++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR2/mtspd2.h      |  183 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.c         |  236 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mt3.h         |  135 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c   | 1448 ++++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.h   |  133 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.c       |  168 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtot3.h       |   91 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.c      |  319 ++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtrci3.h      |   88 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.c      |  503 +++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtsdi3.h      |   97 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c      | 1191 ++++++
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.h      |  177 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttecc3.c     |  164 +
 .../amd/agesa/f15/Proc/Mem/Tech/DDR3/mttwl3.c      |  719 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mt.c    |  263 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mthdi.c |  125 +
 .../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.c    |  916 +++++
 .../amd/agesa/f15/Proc/Mem/Tech/mttEdgeDetect.h    |  118 +
 .../amd/agesa/f15/Proc/Mem/Tech/mttdimbt.c         | 1424 ++++++++
 .../amd/agesa/f15/Proc/Mem/Tech/mttecc.c           |  226 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mtthrc.c           |  311 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mtthrcSeedTrain.c  |  624 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/mttml.c |  259 ++
 .../amd/agesa/f15/Proc/Mem/Tech/mttoptsrc.c        |  428 +++
 .../amd/agesa/f15/Proc/Mem/Tech/mttsrc.c           |  346 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/ma.h         |  317 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/memPage.h    |   58 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/merrhdl.h    |  104 +
 .../amd/agesa/f15/Proc/Mem/mfParallelTraining.h    |  114 +
 .../amd/agesa/f15/Proc/Mem/mfStandardTraining.h    |   82 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mfmemclr.h   |   84 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mfs3.h       |  356 ++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mftds.h      |   81 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mm.h         | 1307 +++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mn.h         | 1743 +++++++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mp.h         |  607 ++++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mport.h      |   71 +
 src/vendorcode/amd/agesa/f15/Proc/Mem/mt.h         |  510 +++
 src/vendorcode/amd/agesa/f15/Proc/Mem/mu.h         |  245 ++
 .../amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.c  |  103 +
 .../amd/agesa/f15/Proc/Recovery/CPU/cpuRecovery.h  |   76 +
 .../agesa/f15/Proc/Recovery/HT/htInitRecovery.c    |  168 +
 .../amd/agesa/f15/Proc/Recovery/HT/htInitReset.c   |  332 ++
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.c    |  725 ++++
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnc32.h    |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/C32/mrnmctc32.c |  161 +
 .../f15/Proc/Recovery/Mem/NB/C32/mrnprotoc32.c     |   61 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.c  |  665 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DA/mrnda.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/DA/mrnmctda.c   |  164 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.c  |  669 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/DR/mrndr.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/DR/mrnmctdr.c   |  166 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrndcthy.c   |   75 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.c  |  725 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/HY/mrnhy.h  |  109 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrnmcthy.c   |  161 +
 .../agesa/f15/Proc/Recovery/Mem/NB/HY/mrnprotohy.c |   61 +
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrndctor.c   |  341 ++
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrnmctor.c   |  145 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c  |  798 +++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.h  |  129 +
 .../agesa/f15/Proc/Recovery/Mem/NB/OR/mrnprotoor.c |   61 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.c  |  666 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/PH/mrnPh.h  |   96 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.c  |  665 ++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/RB/mrnRb.h  |   96 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrn.c       |  189 +
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrndct.c    | 1577 ++++++++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrnmct.c    |  296 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/NB/mrntrain3.c |  158 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrp.c       |  258 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplribt.c  |  182 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnlr.c  |  110 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrplrnpr.c  |  110 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpmr0.c    |  177 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpodtpat.c |  182 +
 .../agesa/f15/Proc/Recovery/Mem/Ps/mrprc10opspd.c  |   92 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprc2ibt.c |  198 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrprtt.c    |  217 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Ps/mrpsao.c    |  187 +
 .../agesa/f15/Proc/Recovery/Mem/Tech/DDR3/mrt3.c   |  188 +
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtrci3.c      |  243 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtsdi3.c      |  361 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.c      |  325 ++
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrtspd3.h      |  131 +
 .../f15/Proc/Recovery/Mem/Tech/DDR3/mrttwl3.c      |  369 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrtthrc.c |  329 ++
 .../f15/Proc/Recovery/Mem/Tech/mrtthrcSeedTrain.c  |  315 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttpos.c |  114 +
 .../amd/agesa/f15/Proc/Recovery/Mem/Tech/mrttsrc.c |  437 +++
 .../amd/agesa/f15/Proc/Recovery/Mem/mrdef.c        |  128 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrinit.c       |  125 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrm.c          |  288 ++
 .../amd/agesa/f15/Proc/Recovery/Mem/mrport.h       |   86 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mrt3.h         |  120 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mru.asm        |  187 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mru.h          |  140 +
 .../amd/agesa/f15/Proc/Recovery/Mem/mruc.c         |  270 ++
 .../amd/agesa/f15/Proc/Recovery/recoveryPage.h     |   58 +
 src/vendorcode/amd/agesa/f15/cpcar.inc             | 1470 ++++++++
 src/vendorcode/amd/agesa/f15/cpcarmac.inc          |  457 +++
 src/vendorcode/amd/agesa/f15/errno.h               |   38 +
 src/vendorcode/amd/agesa/f15/gcccar.inc            | 1612 +++++++++
 733 files changed, 257251 insertions(+), 0 deletions(-)

diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc
index 5516888..b0e5ddf 100644
--- a/src/vendorcode/amd/agesa/Makefile.inc
+++ b/src/vendorcode/amd/agesa/Makefile.inc
@@ -1,3 +1,4 @@
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14
+subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15
diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h
new file mode 100644
index 0000000..b18659e
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/AGESA.h
@@ -0,0 +1,3566 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 60222 $   @e \$Date: 2011-10-10 23:39:36 -0600 (Mon, 10 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include  "Porting.h"
+#include  "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE              0x00028000
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA                0x00028100
+#define AGESA_DO_RESET                 0x00028101
+#define AGESA_ALLOCATE_BUFFER          0x00028102
+#define AGESA_DEALLOCATE_BUFFER        0x00028103
+#define AGESA_LOCATE_BUFFER            0x00028104
+#define AGESA_RUNFUNC_ONAP             0x00028105
+
+// AGESA ADVANCED CALLOUTS, HyperTransport
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD                 0x00028140
+#define AGESA_HOOKBEFORE_DRAM_INIT     0x00028141
+#define AGESA_HOOKBEFORE_DQS_TRAINING  0x00028142
+#define AGESA_READ_SPD_RECOVERY        0x00028143
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY     0x00028145
+#define AGESA_EXTERNAL____TRAIN_VREF_CHANGE     0x00028146
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA       0x00028200
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET      0x00028301
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT          0x00028401
+
+//------------------------------------------------------------------------
+//
+// HyperTransport Interface
+
+
+
+//-----------------------------------------------------------------------------
+//                         HT DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+
+// Width equates for call backs
+#define HT_WIDTH_8_BITS              8                          ///< Specifies 8 bit, or up to 8 bit widths.
+#define HT_WIDTH_16_BITS             16                         ///< Specifies 16 bit, or up to 16 bit widths.
+#define HT_WIDTH_4_BITS              4
+#define HT_WIDTH_2_BITS              2
+#define HT_WIDTH_NO_LIMIT            HT_WIDTH_16_BITS
+
+// Frequency Limit equates for call backs which take a frequency supported mask.
+#define HT_FREQUENCY_LIMIT_200M      1                           ///< Specifies a limit of no more than 200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_400M      7                           ///< Specifies a limit of no more than 400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_600M      0x1F                        ///< Specifies a limit of no more than 600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_800M      0x3F                        ///< Specifies a limit of no more than 800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1000M     0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_HT1_ONLY  0x7F                        ///< Specifies a limit of no more than 1000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1200M     0xFF                        ///< Specifies a limit of no more than 1200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1400M     0x1FF                       ///< Specifies a limit of no more than 1400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1600M     0x3FF                       ///< Specifies a limit of no more than 1600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_1800M     0x7FF                       ///< Specifies a limit of no more than 1800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2000M     0xFFF                       ///< Specifies a limit of no more than 2000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2200M     0x1FFF                      ///< Specifies a limit of no more than 2200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2400M     0x3FFF                      ///< Specifies a limit of no more than 2400 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2600M     0x7FFF                      ///< Specifies a limit of no more than 2600 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_2800M     0x27FFF                     ///< Specifies a limit of no more than 2800 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3000M     0x67FFF                     ///< Specifies a limit of no more than 3000 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3200M     0xE7FFF                     ///< Specifies a limit of no more than 3200 MHz HT frequency.
+#define HT_FREQUENCY_LIMIT_3600M     0x1E7FFF
+#define HT_FREQUENCY_LIMIT_MAX       HT_FREQUENCY_LIMIT_3600M
+#define HT_FREQUENCY_NO_LIMIT        0xFFFFFFFF                  ///< Specifies a no limit of HT frequency.
+
+// Unit ID Clumping special values
+#define HT_CLUMPING_DISABLE          0x00000000
+#define HT_CLUMPING_NO_LIMIT         0xFFFFFFFF
+
+#define HT_LIST_TERMINAL             0xFF             ///< End of list.
+#define HT_LIST_MATCH_ANY            0xFE             ///< Match Any value, used for Sockets, Links, IO Chain Depth.
+#define HT_LIST_MATCH_INTERNAL_LINK  0xFD             ///< Match all of the internal links.
+
+// Event Notify definitions
+
+// Event definitions.
+
+// Coherent subfunction events
+#define HT_EVENT_COH_EVENTS             0x10001000
+#define HT_EVENT_COH_NO_TOPOLOGY        0x10011000    ///< See ::HT_EVENT_DATA_COH_NO_TOPOLOGY.
+#define HT_EVENT_COH_OBSOLETE000        0x10021000    //   No longer used.
+#define HT_EVENT_COH_PROCESSOR_TYPE_MIX 0x10031000    ///< See ::HT_EVENT_DATA_COH_PROCESSOR_TYPE_MIX.
+#define HT_EVENT_COH_NODE_DISCOVERED    0x10041000    ///< See ::HT_EVENT_COH_NODE_DISCOVERED.
+#define HT_EVENT_COH_MPCAP_MISMATCH     0x10051000    ///< See ::HT_EVENT_COH_MPCAP_MISMATCH.
+
+// Non-coherent subfunction events
+#define HT_EVENT_NCOH_EVENTS         0x10002000
+#define HT_EVENT_NCOH_BUID_EXCEED    0x10012000       ///< See ::HT_EVENT_DATA_NCOH_BUID_EXCEED
+#define HT_EVENT_NCOH_OBSOLETE000    0x10022000       //   No longer used.
+#define HT_EVENT_NCOH_BUS_MAX_EXCEED 0x10032000       ///< See ::HT_EVENT_DATA_NCOH_BUS_MAX_EXCEED.
+#define HT_EVENT_NCOH_CFG_MAP_EXCEED 0x10042000       ///< See ::HT_EVENT_DATA_NCOH_CFG_MAP_EXCEED.
+#define HT_EVENT_NCOH_DEVICE_FAILED  0x10052000       ///< See ::HT_EVENT_DATA_NCOH_DEVICE_FAILED
+#define HT_EVENT_NCOH_AUTO_DEPTH     0x10062000       ///< See ::HT_EVENT_NCOH_AUTO_DEPTH
+
+// Optimization subfunction events
+#define HT_EVENT_OPT_EVENTS               0x10003000
+#define HT_EVENT_OPT_REQUIRED_CAP_RETRY   0x10013000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_REQUIRED_CAP_GEN3    0x10023000  ///< See ::HT_EVENT_DATA_OPT_REQUIRED_CAP.
+#define HT_EVENT_OPT_UNUSED_LINKS         0x10033000  ///< See ::HT_EVENT_DATA_OPT_UNUSED_LINKS.
+#define HT_EVENT_OPT_LINK_PAIR_EXCEED     0x10043000  ///< See ::HT_EVENT_DATA_OPT_LINK_PAIR_EXCEED.
+
+// HW Fault events
+#define HT_EVENT_HW_EVENTS           0x10004000
+#define HT_EVENT_HW_SYNCFLOOD        0x10014000       ///< See ::HT_EVENT_DATA_HW_SYNCFLOOD.
+#define HT_EVENT_HW_HTCRC            0x10024000       ///< See ::HT_EVENT_DATA_HW_HT_CRC.
+
+// The Recovery HT component uses 0x10005000 for events.
+// For consistency, we avoid that range here.
+
+#define HT_MAX_NC_BUIDS 32
+//----------------------------------------------------------------------------
+//                         HT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// Specify the state redundant links are to be left in after match.
+///
+/// After matching a link for IGNORE_LINK or SKIP_REGANG, the link may be left alone,
+/// or powered off.
+
+typedef enum {
+  MATCHED,                               ///< The link matches the requested customization.
+                                         ///< When used with IGNORE_LINK,
+                                         ///< this will generally require other software to initialize the link.
+                                         ///< When used with SKIP_REGANG,
+                                         ///< the two unganged links will be available for distribution.
+
+  POWERED_OFF,                           ///< Power the link off.  Support may vary based on processor model.
+                                         ///< Power Off is only supported for coherent links.
+                                         ///< Link power off may occur at a warm reset rather than immediately.
+                                         ///< When used with SKIP_REGANG, the paired sublink is powered off, not the matching link.
+
+  UNMATCHED,                             ///< The link should be processed according to normal defaults.
+                                         ///< Effectively, the link does not match the requested customization.
+                                         ///< This can be used to exclude links from a following match any.
+
+  MaxFinalLinkState                      ///< Not a final link state, use for limit checking.
+} FINAL_LINK_STATE;
+
+/// Swap a device from its current id to a new one.
+
+typedef struct {
+  IN       UINT8 FromId;                 ///< The device responding to FromId,
+  IN       UINT8 ToId;                   ///< will be moved to ToId.
+} BUID_SWAP_ITEM;
+
+
+/// Each Non-coherent chain may have a list of device swaps.  After performing the swaps,
+/// the final in order list of device ids is provided. (There can be more swaps than devices.)
+/// The unused entries in both are filled with 0xFF.
+
+typedef struct {
+  IN       BUID_SWAP_ITEM Swaps[HT_MAX_NC_BUIDS]; ///< The BUID Swaps to perform
+  IN       UINT8 FinalIds[HT_MAX_NC_BUIDS];       ///< The ordered final BUIDs, resulting from the swaps
+} BUID_SWAP_LIST;
+
+
+/// Control Manual Initialization of Non-Coherent Chains
+///
+/// This interface is checked every time a non-coherent chain is
+/// processed.  BUID assignment may be controlled explicitly on a
+/// non-coherent chain. Provide a swap list.  Swaps controls the
+/// BUID assignment and FinalIds provides the device to device
+/// Linking.  Device orientation can be detected automatically, or
+/// explicitly.  See interface documentation for more details.
+///
+/// If a manual swap list is not supplied,
+/// automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+/// based on each device's unit count.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                       ///< The Socket on which this chain is located
+  IN       UINT8 Link;                         ///< The Link on the host for this chain
+  // Override fields
+  IN       BUID_SWAP_LIST SwapList;            ///< The swap list
+} MANUAL_BUID_SWAP_LIST;
+
+
+/// Override options for DEVICE_CAP_OVERRIDE.
+///
+/// Specify which override actions should be performed.  For Checks, 1 means to check the item
+/// and 0 means to skip the check.  For the override options, 1 means to apply the override and
+/// 0 means to ignore the override.
+
+typedef struct {
+  IN       UINT32  IsCheckDevVenId:1;     ///< Check Match on Device/Vendor id
+  IN       UINT32  IsCheckRevision:1;     ///< Check Match on device Revision
+  IN       UINT32  IsOverrideWidthIn:1;   ///< Override Width In
+  IN       UINT32  IsOverrideWidthOut:1;  ///< Override Width Out
+  IN       UINT32  IsOverrideFreq:1;      ///< Override Frequency
+  IN       UINT32  IsOverrideClumping:1;  ///< Override Clumping
+  IN       UINT32  IsDoCallout:1;         ///< Make the optional callout
+} DEVICE_CAP_OVERRIDE_OPTIONS;
+
+/// Override capabilities of a device.
+///
+/// This interface is checked once for every Link on every IO device.
+/// Provide the width and frequency capability if needed for this device.
+/// This is used along with device capabilities, the limit interfaces, and northbridge
+/// limits to compute the default settings.  The components of the device's PCI config
+/// address are provided, so its settings can be consulted if need be.
+/// The optional callout is a catch all.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       DEVICE_CAP_OVERRIDE_OPTIONS Options; ///< The options for this device override.
+  // Override fields
+  IN       UINT8 LinkWidthIn;          ///< modify to change the Link Width In.
+  IN       UINT8 LinkWidthOut;         ///< modify to change the Link Width Out.
+  IN       UINT32 FreqCap;             ///< modify to change the Link's frequency capability.
+  IN       UINT32 Clumping;            ///< modify to change Unit ID clumping support.
+  IN       CALLOUT_ENTRY Callout;      ///< optional call for really complex cases, or NULL.
+} DEVICE_CAP_OVERRIDE;
+
+/// Callout param struct for override capabilities of a device.
+///
+/// If the optional callout is implemented this param struct is passed to it.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+  // Match fields
+  IN       UINT8 HostSocket;           ///< The Socket on which this chain is located.
+  IN       UINT8 HostLink;             ///< The Link on the host for this chain.
+  IN       UINT8 Depth;                ///< The Depth in the I/O chain from the Host.
+  IN       UINT32 DevVenId;            ///< The Device's PCI Vendor + Device ID (offset 0x00).
+  IN       UINT8 Revision;             ///< The Device's PCI Revision field (offset 0x08).
+  IN       UINT8 Link;                 ///< The Device's Link number (0 or 1).
+  IN       PCI_ADDR PciAddress;        ///< The Device's PCI Address.
+  // Override fields
+     OUT   UINT8 *LinkWidthIn;          ///< modify to change the Link Width In.
+     OUT   UINT8 *LinkWidthOut;         ///< modify to change the Link Width Out.
+     OUT   UINT32 *FreqCap;             ///< modify to change the Link's frequency capability.
+     OUT   UINT32 *Clumping;            ///< modify to change Unit ID clumping support.
+} DEVICE_CAP_CALLOUT_PARAMS;
+
+///  Limits for CPU to CPU Links.
+///
+///  For each coherent connection this interface is checked once.
+///  Provide the frequency and width if needed for this Link (usually based on board
+///  restriction).  This is used with CPU device capabilities and northbridge limits
+///  to compute the default settings.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Limit fields
+  IN       UINT8 ABLinkWidthLimit;       ///< modify to change the Link Width A->B
+  IN       UINT8 BALinkWidthLimit;       ///< modify to change the Link Width B-<A
+  IN       UINT32 PcbFreqCap;            ///< modify to change the Link's frequency capability
+} CPU_TO_CPU_PCB_LIMITS;
+
+///  Get limits for non-coherent Links.
+///
+/// For each non-coherent connection this interface is checked once.
+/// Provide the frequency and width if needed for this Link (usually based on board
+/// restriction).  This is used with device capabilities, device overrides, and northbridge limits
+/// to compute the default settings.
+///
+typedef struct {
+  // Match fields
+  IN       UINT8 HostSocket;               ///< The Socket on which this Link is located
+  IN       UINT8 HostLink;                 ///< The Link about to be initialized
+  IN       UINT8 Depth;                    ///< The Depth in the I/O chain from the Host
+  // Limit fields
+  IN       UINT8 DownstreamLinkWidthLimit; ///< modify to change the Link Width going away from processor
+  IN       UINT8 UpstreamLinkWidthLimit;   ///< modify to change the Link Width moving toward processor
+  IN       UINT32 PcbFreqCap;              ///< modify to change the Link's frequency capability
+} IO_PCB_LIMITS;
+
+///  Manually control bus number assignment.
+///
+/// This interface is checked every time a non-coherent chain is processed.
+/// If a system can not use the auto Bus numbering feature for non-coherent chain bus
+/// assignments, this interface can provide explicit control.  For each chain, provide
+/// the bus number range to use.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this chain is located
+  IN       UINT8 Link;                   ///< The Link on the host for this chain
+  // Override fields
+  IN       UINT8 SecBus;                 ///< Secondary Bus number for this non-coherent chain
+  IN       UINT8 SubBus;                 ///< Subordinate Bus number
+} OVERRIDE_BUS_NUMBERS;
+
+
+///  Ignore a Link.
+///
+///  This interface is checked every time a coherent Link is found and then every
+///  time a non-coherent Link from a CPU is found.
+///  Any coherent or non-coherent Link from a CPU can be ignored and not used
+///  for discovery or initialization.  Useful for connection based systems.
+///  (Note: not checked for IO device to IO Device Links.)
+///  (Note: not usable for internal links (MCM processors).)
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                 ///< The Socket on which this Link is located
+  IN       UINT8 Link;                   ///< The Link about to be initialized
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The link may be left unitialized, or powered off.
+} IGNORE_LINK;
+
+
+///  Skip reganging of subLinks.
+///
+///  This interface is checked whenever two subLinks are both connected to the same CPUs.
+///  Normally, unganged sublinks between the same two CPUs are reganged.
+///  Provide a matching structure to leave the Links unganged.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 SocketA;                ///< One Socket on which this Link is located
+  IN       UINT8 LinkA;                  ///< The Link on this Node
+  IN       UINT8 SocketB;                ///< The other Socket on which this Link is located
+  IN       UINT8 LinkB;                  ///< The Link on that Node
+  // Customization fields
+  IN       FINAL_LINK_STATE LinkState;   ///< The paired sublink may be active, or powered off.
+} SKIP_REGANG;
+
+///  The System Socket layout, which sockets are physically connected.
+///
+///  The hardware method for Socket naming is preferred.  Use this software method only
+///  if required.
+
+typedef struct {
+  IN       UINT8 CurrentSocket;    ///< The socket from which this connection originates.
+  IN       UINT8 CurrentLink;      ///< The Link from the source socket connects to another socket.
+  IN       UINT8 TargetSocket;     ///< The target socket which is connected on that link.
+} SYSTEM_PHYSICAL_SOCKET_MAP;
+
+//----------------------------------------------------------------------------
+///
+/// This is the input structure for AmdHtInitialize.
+///
+typedef struct {
+  // Basic level customization
+  IN       UINT8 AutoBusStart;           ///< For automatic bus number assignment, starting bus number - usually zero.
+                                         ///< @BldCfgItem{BLDCFG_STARTING_BUSNUM}
+  IN       UINT8 AutoBusMax;             ///< For automatic bus number assignment, do not assign above max.
+                                         ///< @BldCfgItem{BLDCFG_MAXIMUM_BUSNUM}
+  IN       UINT8 AutoBusIncrement;       ///< For automatic bus number assignment, each chain gets this many busses.
+                                         ///< @BldCfgItem{BLDCFG_ALLOCATED_BUSNUM}
+
+  // Advanced Level Customization
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;     ///< Provide Manual Swap List, if any.
+                                                          ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+  IN       DEVICE_CAP_OVERRIDE *DeviceCapOverrideList;    ///< Provide Device Overrides, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST}
+  IN       CPU_TO_CPU_PCB_LIMITS *CpuToCpuPcbLimitsList;   ///< Provide CPU PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTFABRIC_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       IO_PCB_LIMITS *IoPcbLimitsList;                ///< Provide IO PCB Limits, if any.
+                                                          ///< @BldCfgItem{BLDCFG_HTCHAIN_LIMITS_LIST}.
+                                                          ///< @n @e Examples: See @ref FrequencyLimitExamples "Frequency Limit Examples".
+  IN       OVERRIDE_BUS_NUMBERS *OverrideBusNumbersList;  ///< Provide manual Bus Number assignment, if any.
+                                                          ///< Use either auto bus numbering or override bus
+                                                          ///< numbers, not both.
+                                                          ///< @BldCfgItem{BLDCFG_BUS_NUMBERS_LIST}
+
+  IN       IGNORE_LINK *IgnoreLinkList;                   ///< Provide links to ignore, if any.
+                                                          ///< @BldCfgItem{BLDCFG_IGNORE_LINK_LIST}
+  IN       SKIP_REGANG *SkipRegangList;                   ///< Provide links to remain unganged, if any.
+                                                          ///< @BldCfgItem{BLDCFG_LINK_SKIP_REGANG_LIST}
+                                                          ///< @n @e Examples: See @ref PerfPerWattHt "Performance-per-watt Optimization".
+
+  // Expert Level Customization
+  IN       UINT8 **Topolist;                         ///< Use this topology list in addition to the built in, if not NULL.
+                                                     ///< @BldCfgItem{BLDCFG_ADDITIONAL_TOPOLOGIES_LIST}
+  IN       SYSTEM_PHYSICAL_SOCKET_MAP *SystemPhysicalSocketMap;
+                                                     ///< The hardware socket naming method is preferred,
+                                                     ///<  If it can't be used, this provides a software method.
+                                                     ///< @BldCfgItem{BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP}
+} AMD_HT_INTERFACE;
+
+//-----------------------------------------------------------------------------
+//
+// HT Recovery Interface
+//
+
+
+/*-----------------------------------------------------------------------------
+ *              HT Recovery DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+// BBHT subfunction events
+#define HT_EVENT_BB_EVENTS         0x10005000
+#define HT_EVENT_BB_BUID_EXCEED    0x10015000
+#define HT_EVENT_BB_DEVICE_FAILED  0x10055000
+#define HT_EVENT_BB_AUTO_DEPTH     0x10065000
+
+/*----------------------------------------------------------------------------
+ *                      HT Recovery   TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+/// The Interface structure to Recovery HT.
+
+typedef struct {
+  IN       MANUAL_BUID_SWAP_LIST *ManualBuidSwapList;  ///< Option to manually control SB link init
+                                                       ///< @BldCfgItem{BLDCFG_BUID_SWAP_LIST}
+     OUT   UINT32 Depth;           ///< If auto init was used this is set to the depth of the chain,
+                                   ///< else, for manual init unmodified.
+} AMD_HT_RESET_INTERFACE;
+
+
+//-----------------------------------------------------------------------------
+//                     FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+  SdDisable = 0,                      ///< Disabled
+  SdAmda,                             ///< AMDA,  set 24,18,16,  default
+  SdDma,                              ///< DMA clear 24, 16, set 18
+  SdPio                               ///< PIO clear 24,18,16
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+  Sd50MhzTraceCableLengthWithinSixInches = 4,           ///< 50Mhz, default
+  Sd40MhzTraceCableLengthSix2ElevenInches = 6,          ///< 40Mhz
+  Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7,   ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for AzaliaController
+typedef enum {
+  AzAuto = 0,                         ///< Auto - Detect Azalia controller automatically
+  AzDisable,                          ///< Diable - Disable Azalia controller
+  AzEnable                            ///< Enable - Enable Azalia controller
+} HDA_CONFIG;
+
+/// Configuration values for IrConfig
+typedef enum {
+  IrDisable  = 0,                     ///< Disable
+  IrRxTx0    = 1,                     ///< Rx and Tx0
+  IrRxTx1    = 2,                     ///< Rx and Tx1
+  IrRxTx0Tx1 = 3                      ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+  SataNativeIde = 0,                  ///< Native IDE mode
+  SataRaid,                           ///< RAID mode
+  SataAhci,                           ///< AHCI mode
+  SataLegacyIde,                      ///< Legacy IDE mode
+  SataIde2Ahci,                       ///< IDE->AHCI mode
+  SataAhci7804,                       ///< AHCI mode as 7804 ID (AMD driver)
+  SataIde2Ahci7804                    ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+  PortA4       = 0,                   ///< 4:0:0:0
+  PortA2B2     = 2,                   ///< 2:2:0:0
+  PortA2B1C1   = 3,                   ///< 2:1:1:0
+  PortA1B1C1D1 = 4                    ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+  AlwaysOff   = 0,                    ///< Always power off after power resumes
+  AlwaysOn    = 1,                    ///< Always power on after power resumes
+  UsePrevious = 3,                    ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+  Gen1   = 1,                         ///< SATA port GEN1 speed
+  Gen2   = 2,                         ///< SATA port GEN2 speed
+  Gen3   = 3,                         ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+  Function0   = 0,                    ///< GPIO Function 1
+  Function1   = 1,                    ///< GPIO Function 1
+  Function2   = 2,                    ///< GPIO Function 2
+  Function3   = 3,                    ///< GPIO Function 3
+} GPIO_FUN;
+
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+  OwnedByEc   = 1 << 0,               ///< This bit can only be written by EC
+  OwnedByHost = 1 << 1,               ///< This bit can only be written by host (BIOS)
+  Sticky      = 1 << 2,               ///< If set, [6:3] are sticky
+  PullUpB     = 1 << 3,               ///< 0: Pullup enable; 1: Pullup disabled
+  PullDown    = 1 << 4,               ///< 0: Pulldown disabled; 1: Pulldown enable
+  GpioOutEnB  = 1 << 5,               ///< 0: Output enable; 1: Output disable
+  GpioOut     = 1 << 6,               ///< Output state when GpioOutEnB is 0
+  GpioIn      = 1 << 7,               ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+  IN         UINT8        GpioPin;               ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+  IN         GPIO_FUN     PinFunction;           ///< Multi-function selection
+  IN         CFG_BYTE     CfgByte;               ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+  IN         UINT8        InputPin;              ///< Input Pin, valid range 0-63
+  IN         UINT8        GpeMap;                ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+  IN         BOOLEAN      CommonPhy;             ///< Common PHY or not
+                                      ///<   @li <b>FALSE</b> - Only applied to specified port
+                                      ///<   @li <b>TRUE</b>  - Apply to all SATA ports
+  IN         SATA_SPEED   Gen;                   ///< SATA speed
+  IN         UINT8        Port;                  ///< Port number, valid range: 0-7
+  IN         UINT32       PhyData;               ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       BOOLEAN      Xhci0Enable;         ///< XHCI0 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI0 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI0 controller enabled
+
+  IN       BOOLEAN      Xhci1Enable;         ///< XHCI1 controller function
+                                             ///<   @li <b>FALSE</b> - XHCI1 controller disabled
+                                             ///<   @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+  IN       SD_MODE      SdConfig;            ///< Secure Digital (SD) controller mode
+  IN       HDA_CONFIG   AzaliaController;    ///< Azalia HD Audio Controller
+
+  IN       IR_CONFIG    IrConfig;            ///< Infrared (IR) Configuration
+  IN       BOOLEAN      UmiGen2;             ///< Enable Gen2 data rate of UMI
+                                             ///<   @li <b>FALSE</b> - Disable Gen2
+                                             ///<   @li <b>TRUE</b>  - Enable Gen2
+
+  IN       SATA_CLASS   SataClass;           ///< SATA controller mode
+  IN       BOOLEAN      SataEnable;          ///< SATA controller function
+                                             ///<   @li <b>FALSE</b> - SATA controller is disabled
+                                             ///<   @li <b>TRUE</b> - SATA controller is enabled
+
+  IN       BOOLEAN      IdeEnable;           ///< SATA IDE controller mode enabled/disabled
+                                             ///<   @li <b>FALSE</b> - IDE controller is disabled
+                                             ///<   @li <b>TRUE</b> - IDE controller is enabled
+
+  IN       BOOLEAN      SataIdeMode;         ///< Native mode of SATA IDE controller
+                                             ///<   @li <b>FALSE</b> - Legacy IDE mode
+                                             ///<   @li <b>TRUE</b> - Native IDE mode
+
+  IN       BOOLEAN      Ohci1Enable;         ///< OHCI controller #1 Function
+                                             ///<   @li <b>FALSE</b> - OHCI1 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI1 is enabled
+
+  IN       BOOLEAN      Ohci2Enable;         ///< OHCI controller #2 Function
+                                             ///<   @li <b>FALSE</b> - OHCI2 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI2 is enabled
+
+  IN       BOOLEAN      Ohci3Enable;         ///< OHCI controller #3 Function
+                                             ///<   @li <b>FALSE</b> - OHCI3 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI3 is enabled
+
+  IN       BOOLEAN      Ohci4Enable;         ///< OHCI controller #4 Function
+                                             ///<   @li <b>FALSE</b> - OHCI4 is disabled
+                                             ///<   @li <b>TRUE</b> - OHCI4 is enabled
+
+  IN       BOOLEAN      XhciSwitch;          ///< XHCI controller Function
+                                             ///<   @li <b>FALSE</b> - XHCI is disabled
+                                             ///<   @li <b>TRUE</b> - XHCI is enabled
+
+  IN       BOOLEAN      GppEnable;           ///< Master switch of GPP function
+                                             ///<   @li <b>FALSE</b> - GPP disabled
+                                             ///<   @li <b>TRUE</b> - GPP enabled
+
+  IN       POWER_FAIL   FchPowerFail;        ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ *   CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+
+/// Build Configuration values for BLDCFG_PLATFORM_C1E_MODE
+typedef enum {
+  C1eModeDisabled                   = 0,   ///< Disabled
+  C1eModeAuto                       = 1,   ///< Auto mode enables the best C1e method for the
+                                           ///< currently installed processor
+  C1eModeHardware                   = 2,   ///< Hardware method
+  C1eModeMsgBased                   = 3,   ///< Message-based method
+  C1eModeSoftwareDeprecated         = 4,   ///< Deprecated software SMI method.
+                                           ///< Refer to "Addendum\Examples\C1eSMMHandler.asm" for
+                                           ///< example host BIOS SMM Handler implementation
+  C1eModeHardwareSoftwareDeprecated = 5,   ///< Hardware or deprecated software SMI method
+  MaxC1eMode                        = 6    ///< Not a valid value, used for verifying input
+} PLATFORM_C1E_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+  CStateModeDisabled = 0,           ///< Disabled
+  CStateModeC6       = 1,           ///< C6 State
+  MaxCStateMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+  CpbModeAuto     = 0,           ///< Auto
+  CpbModeDisabled = 1,           ///< Disabled
+  MaxCpbMode      = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+typedef enum {
+  LOW_POWER_PSTATE_FOR_PROCHOT_AUTO      = 0,           ///< Auto
+  LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE   = 1,           ///< Disabled
+  MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE  = 2            ///< Not a valid value, used for verifying input
+} PLATFORM_LOW_POWER_PSTATE_MODES;
+
+/*----------------------------------------------------------------------------
+ *   GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+
+#define GNB_EVENT_INVALID_CONFIGURATION               0x20010000   // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001   // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION     0x20010002   // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION      0x20010003   // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION    0x20010004   // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION         0x20010005   // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION  0x20010006   // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL                  0x20020000   // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY                0x20030000   // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY               0x20040000   // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST           0x80000000ull
+#define DESCRIPTOR_IGNORE                   0x40000000ull
+
+/// PCIe port misc extended controls
+typedef struct  {
+  IN      UINT8                     LinkComplianceMode :1;  ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+  IN      UINT8                     LinkSafeMode       :2;  /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+                                                             *  @li @b 0 - port can advertize muximum supported capability
+                                                             *  @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+                                                             */
+  IN      UINT8                     SbLink             :1;  /**< PCIe link type
+                                                             *  @li @b 0 - General purpose port
+                                                             *  @li @b 1 - Port connected to SB
+                                                             */
+} PCIe_PORT_MISC_CONTROL;
+
+
+/// PCIe port configuration data
+typedef struct  {
+  IN       UINT8                   PortPresent;              ///< Enable PCIe port for initialization.
+  IN       UINT8                   ChannelType;              /**< Channel type.
+                                                               *  @li @b 0 - "lowLoss",
+                                                               *  @li @b 1 - "highLoss",
+                                                               *  @li @b 2 - "mob0db",
+                                                               *  @li @b 3 - "mob3db",
+                                                               *  @li @b 4 - "extnd6db"
+                                                               *  @li @b 5 - "extnd8db"
+                                                               */
+  IN       UINT8                   DeviceNumber;             /**< PCI Device number for port.
+                                                               *   @li @b 0 - Native port device number
+                                                               *   @li @b N - Port device number (See available configurations @ref F12LaneConfigurations "Family 0x12",  @ref F14ONLaneConfigurations "Family 0x14(ON)")
+                                                               */
+  IN       UINT8                   FunctionNumber;           ///< Reserved for future use
+  IN       UINT8                   LinkSpeedCapability;      /**< PCIe link speed/
+                                                               *  @li @b 0 - Maximum supported by silicon
+                                                               *  @li @b 1 - Gen1
+                                                               *  @li @b 2 - Gen2
+                                                               *  @li @b 3 - Gen3
+                                                               */
+  IN       UINT8                   LinkAspm;                 /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - L0s only
+                                                               *  @li @b 2 - L1 only
+                                                               *  @li @b 3 - L0s and L1
+                                                               */
+  IN       UINT8                   LinkHotplug;              /**< Hotplug control.
+                                                               *  @li @b 0 - Disabled
+                                                               *  @li @b 1 - Basic
+                                                               *  @li @b 2 - Server
+                                                               *  @li @b 3 - Enhanced
+                                                               */
+  IN       UINT8                   ResetId;                  /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+                                                               *   identification which control reset for given port.
+                                                               *   Each port with unique GPIO should have unique ResetId assigned.
+                                                               *   All ports use same GPIO to control reset should have same ResetId assigned.
+                                                               *   see AgesaPcieSlotResetContol.
+                                                               */
+  IN       PCIe_PORT_MISC_CONTROL  MiscControls;             ///< Misc extended controls
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct {                                          ///< Structure that discribe lane mapping
+  IN      UINT8              Lane0   :2;                  /**< Lane 0 mapping
+                                                           *  @li @b 0 - Map to lane 0
+                                                           *  @li @b 1 - Map to lane 1
+                                                           *  @li @b 2 - Map to lane 2
+                                                           *  @li @b 2 - Map to lane 3
+                                                           */
+  IN      UINT8              Lane1   :2;                  ///< Lane 1 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane2   :2;                  ///< Lane 2 mapping (see "Lane 0 mapping")
+  IN      UINT8              Lane3   :2;                  ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING;                                        ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+  IN      UINT8                ChannelMappingValue;       ///< Raw lane mapping
+  IN      CHANNEL_MAPPING      ChannelMapping;            ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct  {
+  IN       UINT8                ConnectorType;            /**< Display Connector Type
+                                                            *  @li @b 0 - DP
+                                                            *  @li @b 1 - eDP
+                                                            *  @li @b 2 - Single Link DVI-D
+                                                            *  @li @b 3 - Dual  Link DVI-D (see @ref F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description")
+                                                            *  @li @b 4 - HDMI
+                                                            *  @li @b 5 - Travis DP-to-VGA
+                                                            *  @li @b 6 - Travis DP-to-LVDS
+                                                            *  @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+                                                            *  @li @b 8 - Single Link DVI-I
+                                                            *  @li @b 9 - Native CRT (Family 0x14)
+                                                            *  @li @b 10 - Native LVDS (Family 0x14)
+                                                            *  @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or Travis-LVDS
+                                                            *              The auto detection method only support panel with EDID.
+                                                            */
+  IN       UINT8                AuxIndex;                 /**< Indicates which AUX or DDC Line is used
+                                                            *  @li @b 0 - AUX1
+                                                            *  @li @b 1 - AUX2
+                                                            *  @li @b 2 - AUX3
+                                                            *  @li @b 3 - AUX4
+                                                            *  @li @b 4 - AUX5
+                                                            *  @li @b 5 - AUX6
+                                                            */
+  IN       UINT8                HdpIndex;                 /**< Indicates which HDP pin is used
+                                                            *  @li @b 0 - HDP1
+                                                            *  @li @b 1 - HDP2
+                                                            *  @li @b 2 - HDP3
+                                                            *  @li @b 3 - HDP4
+                                                            *  @li @b 4 - HDP5
+                                                            *  @li @b 5 - HDP6
+                                                            */
+  IN       CONN_CHANNEL_MAPPING Mapping[2];               /**< Set specific mapping of lanes to connector pins
+                                                            *  @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+                                                            *  @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+                                                            *  if Mapping[x] set to 0 than default mapping assumed
+                                                            */
+  IN       UINT8                LanePnInversionMask;      /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+                                                            *  @li 0 - Do not invert (default)
+                                                            *  @li 1 - Invert P and N on this lane
+                                                            */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+  IN       UINT8                EngineType;               /**< Engine type
+                                                           *  @li @b 0 -  Ignore engine configuration
+                                                           *  @li @b 1 -  PCIe port
+                                                           *  @li @b 2 -  DDI
+                                                           */
+  IN       UINT16               StartLane;                /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12"
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+  IN       UINT16               EndLane;                  /**< End lane ID (in reversed configuration StartLane > EndLane)
+                                                           * See lane description for @ref F12PcieLaneDescription "Family 0x12",
+                                                           * @ref F14ONPcieLaneDescription "Family 0x14(ON)".
+                                                           * See lane configurations for @ref F12LaneConfigurations "Family 0x12"
+                                                           * @ref F14ONLaneConfigurations "Family 0x14(ON)".
+                                                           */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_PORT_DATA       Port;                     ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in complex
+                                                           */
+  IN       PCIe_ENGINE_DATA     EngineData;               ///< Engine data
+  IN       PCIe_DDI_DATA        Ddi;                      ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Bit31 - last descriptor in topology
+                                                           */
+  IN       UINT32               SocketId;                 ///< Socket Id
+  IN       PCIe_PORT_DESCRIPTOR *PciePortList;            ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       PCIe_DDI_DESCRIPTOR  *DdiLinkList;             ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+  IN       VOID                 *Reserved;                ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+  AssertSlotReset,                                        ///< Assert slot reset
+  DeassertSlotReset                                       ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+  IN      AMD_CONFIG_PARAMS     StdHeader;                ///< Standard configuration header
+  IN      UINT8                 ResetId;                  ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+  IN      UINT8                 ResetControl;             ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+/// Engine descriptor type
+typedef enum {
+  PcieUnusedEngine = 0,                                   ///< Unused descriptor
+  PciePortEngine = 1,                                     ///< PCIe port
+  PcieDdiEngine = 2,                                      ///< DDI
+  MaxPcieEngine                                           ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum  {
+  PcieGenMaxSupported,                                    ///< Maximum supported
+  PcieGen1 = 1,                                           ///< Gen1
+  PcieGen2,                                               ///< Gen2
+  MaxPcieGen                                              ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum  {
+  PsppDisabled,                                           ///< PSPP disabled
+  PsppPerformance = 1,                                    ///< Performance
+  PsppBalanceHigh,                                        ///< Balance-High
+  PsppBalanceLow,                                         ///< Balance-Low
+  PsppPowerSaving,                                        ///< Power Saving
+  MaxPspp                                                 ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+  ConnectorTypeDP,                                        ///< DP
+  ConnectorTypeEDP,                                       ///< eDP
+  ConnectorTypeSingleLinkDVI,                             ///< Single Link DVI-D
+  ConnectorTypeDualLinkDVI,                               ///< Dual  Link DVI-D
+  ConnectorTypeHDMI,                                      ///< HDMI
+  ConnectorTypeTravisDpToVga,                             ///< Travis DP-to-VGA
+  ConnectorTypeTravisDpToLvds,                            ///< Travis DP-to-LVDS
+  ConnectorTypeNutmegDpToVga,                             ///< Hudson-2 NutMeg DP-to-VGA
+  ConnectorTypeSingleLinkDviI,                            ///< Single Link DVI-I
+  ConnectorTypeCrt,                                       ///< CRT (VGA)
+  ConnectorTypeLvds,                                      ///< LVDS
+  ConnectorTypeAutoDetect,                                ///< VBIOS auto detect connector type (native LVDS, eDP or Travis-LVDS)
+  MaxConnectorType                                        ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+  ChannelTypeLowLoss,                                     ///< Low Loss
+  ChannelTypeHighLoss,                                    ///< High Loss
+  ChannelTypeMob0db,                                      ///< Mobile 0dB
+  ChannelTypeMob3db,                                      ///< Mobile 3dB
+  ChannelTypeExt6db,                                      ///< Extended 6dB
+  ChannelTypeExt8db,                                      ///< Extended 8dB
+  MaxChannelType                                          ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+  AspmDisabled,                                           ///< Disabled
+  AspmL0s,                                                ///< PCIe L0s link state
+  AspmL1,                                                 ///< PCIe L1 link state
+  AspmL0sL1,                                              ///< PCIe L0s & L1 link state
+  MaxAspm                                                 ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+  HotplugDisabled,                                        ///< Hotplug disable
+  HotplugBasic,                                           ///< Basic Hotplug
+  HotplugServer,                                          ///< Server Hotplug
+  HotplugEnhanced,                                        ///< Enhanced
+  HotplugInboard,                                         ///< Inboard
+  MaxHotplug                                              ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+  PortDisabled,                                           ///< Disable
+  PortEnabled                                             ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+  Aux1,                                                   ///< Aux1
+  Aux2,                                                   ///< Aux2
+  Aux3,                                                   ///< Aux3
+  Aux4,                                                   ///< Aux4
+  Aux5,                                                   ///< Aux5
+  Aux6,                                                   ///< Aux6
+  MaxAux                                                  ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+  Hdp1,                                                   ///< Hdp1
+  Hdp2,                                                   ///< Hdp2
+  Hdp3,                                                   ///< Hdp3
+  Hdp4,                                                   ///< Hdp4
+  Hdp5,                                                   ///< Hdp5
+  Hdp6,                                                   ///< Hdp6
+  MaxHdp                                                  ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+// Macro for statically initialization of various structures
+#define  PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define  PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} }
+#define  PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}, 0}
+#define  PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion}
+
+///IOMMU requestor ID
+typedef struct {
+  IN       UINT16     Bus       :8;                                ///< Bus
+  IN       UINT16     Device    :5;                                ///< Device
+  IN       UINT16     Function  :3;                                ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+  IN       UINT32               Flags;                    /**< Descriptor flags
+                                                           * @li @b Flags[31] - Terminate descriptor array.
+                                                           * @li @b Flags[30] - Ignore descriptor.
+                                                           */
+  IN       IOMMU_REQUESTOR_ID   RequestorIdStart;         ///< Requestor ID start
+  IN       IOMMU_REQUESTOR_ID   RequestorIdEnd;           ///< Requestor ID end (use same as start for single ID)
+  IN       UINT64               RangeBaseAddress;         ///< Phisical base address of exclusion range
+  IN       UINT64               RangeLength;              ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ *   GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+  IN  UINT8     FpdiMode:1;          ///< This item configures LVDS 888bit panel mode
+                                     ///< @li FALSE = LVDS 888 panel in LDI mode
+                                     ///< @li TRUE =  LVDS 888 panel in FPDI mode
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+  IN  UINT8     DlChSwap:1;          ///< This item configures LVDS panel lower and upper link mapping
+                                     ///< @li FALSE = Lower link and upper link not swap
+                                     ///< @li TRUE = Lower link and upper link are swapped
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+  IN  UINT8     VsyncActiveLow:1;    ///< This item configures polarity of frame pulse encoded in lvds data stream
+                                     ///< @li FALSE = Active high Frame Pulse/Vsync
+                                     ///< @li TRUE = Active low Frame Pulse/Vsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+  IN  UINT8     HsyncActiveLow:1;    ///< This item configures polarity of line pulse encoded in lvds data
+                                     ///< @li FALSE = Active high Line Pulse
+                                     ///< @li TRUE = Active low Line Pulse / Hsync
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+  IN  UINT8     BLONActiveLow:1;     ///< This item configures polarity of signal sent to digital BLON output pin
+                                     ///< @li FALSE = Not inverted(active high)
+                                     ///< @li TRUE = Inverted (active low)
+                                     ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+  IN  UINT8     Reserved:3;          ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+  IN LVDS_MISC_CONTROL_FIELD Field;  ///< LVDS_MISC_CONTROL_FIELD
+  IN UINT8   Value;                  ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Configuration settings for GNB.
+typedef struct {
+  IN  UINT8     Gnb3dStereoPinIndex;      ///< 3D Stereo Pin ID.
+                                          ///< @li 0 = Stereo 3D is disabled (default).
+                                          ///< @li 1 = Use processor pin HPD1.
+                                          ///< @li 2 = Use processor pin HPD2
+                                          ///< @li 3 = Use processor pin HPD3
+                                          ///< @li 4 = Use processor pin HPD4
+                                          ///< @li 5 = Use processor pin HPD5
+                                          ///< @li 6 = Use processor pin HPD6
+                                          ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+  IN  BOOLEAN    IommuSupport;            ///< IOMMU support.
+                                          ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+                                          ///< @li TRUE  = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+                                          ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+  IN  UINT16     LvdsSpreadSpectrum;      ///< Spread spectrum value in 0.01 %
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN  UINT16     LvdsSpreadSpectrumRate;  ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+                                          ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN  UINT8      LvdsPowerOnSeqDigonToDe;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqDeToVaryBl;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+  IN  UINT8      LvdsPowerOnSeqDeToDigon;    ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToDe;   ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+  IN  UINT8      LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+  IN  UINT8      LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+  IN  UINT8      LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+  IN  UINT16     LvdsMaxPixelClockFreq;      ///< This item configures the maximum pixel clock frequency supported.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+  IN  UINT32     LcdBitDepthControlValue;    ///< This item configures the LCD bit depth control settings.
+                                             ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+  IN  UINT8      Lvds24bbpPanelMode;         ///< This item configures the LVDS 24 BBP mode.
+                                             ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+  IN  LVDS_MISC_CONTROL      LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+  IN  UINT16     PcieRefClkSpreadSpectrum;   ///< Spread spectrum value in 0.01 %
+                                             ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN  BOOLEAN    GnbRemoteDisplaySupport;    ///< This item enables Wireless Display Support
+                                             ///< @li TRUE  = Enable Wireless Display Support
+                                             ///< @li FALSE = Disable Wireless Display Support
+                                             ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+} GNB_ENV_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+  IN       PCIe_COMPLEX_DESCRIPTOR  *PcieComplexList;  /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+                                                        * Last element of array must ne terminated with DESCRIPTOR_TERMINATE_LIST
+                                                        * Example of topology definition for single socket system:
+                                                        * @code
+                                                        *  PCIe_PORT_DESCRIPTOR PortList [] = {
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    },
+                                                        *    // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+                                                        *      PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+                                                        *    }
+                                                        *  };
+                                                        *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+                                                        *    {
+                                                        *      0,   //Descriptor flags
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+                                                        *    },
+                                                        *    // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+                                                        *    {
+                                                        *      DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate last element of array
+                                                        *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+                                                        *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+                                                        *    }
+                                                        *  };
+                                                        * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+                                                        *   DESCRIPTOR_TERMINATE_LIST, //Descriptor flags  !!!IMPORTANT!!! Terminate complexes list
+                                                        *   0,  //Socket ID
+                                                        *   &PortList[0],
+                                                        *   &DdiList[0],
+                                                        * }
+                                                        * @endcode
+                                                        */
+  IN       UINT8                    PsppPolicy;         /**< PSPP (PCIe Speed Power Policy)
+                                                         *  @li @b 0 - Disabled
+                                                         *  @li @b 1 - Performance
+                                                         *  @li @b 2 - Balance-High
+                                                         *  @li @b 3 - Balance-Low
+                                                         *  @li @b 4 - Power Saving
+                                                         */
+
+} GNB_CONFIGURATION;
+//
+//  MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+//   These Max values are used to define array sizes and associated loop
+//   counts in the code.  They reflect the maximum values that AGESA
+//   currently supports and does not necessarily reflect the hardware
+//   capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED   8   ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4   ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL   4   ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES  9   ///< Number of tables defined in CH_DEF_STRUCT.
+                                    ///< Eg: UINT16  *RcvEnDlys;
+                                    ///<     UINT8   *WrDqsDlys;
+                                    ///<     UINT8   *RdDqsDlys;
+                                    ///<     UINT8   *WrDatDlys;
+                                    ///<     UINT8   *RdDqsMinDlys;
+                                    ///<     UINT8   *RdDqsMaxDlys;
+                                    ///<     UINT8   *WrDatMinDlys;
+                                    ///<     UINT8   *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES     16   ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START  0x00004000    ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END    0x00007FFF    ///< base [39:8]
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000   ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0    0x40000000   ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1    0x20000000   ///< UMA resides on memory that belongs to DCT1
+
+typedef UINT8 PSO_TABLE;            ///< Platform Configuration Table
+
+//        AGESA DEFINITIONS
+//
+//        Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG      0   ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4      4   ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8      8   ///< Force to x8
+/// CPU Package Type
+#define PT_L1       0                 ///< L1 Package type
+#define PT_M2       1                 ///< AM Package type
+#define PT_S1       2                 ///< S1 Package type
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+  IN OUT   UINT64 Family;             ///< Indicates logical ID Family
+  IN OUT   UINT64 Revision;           ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+  AMD_PLATFORM_SERVER = 0x8000,     ///< Server
+  AMD_PLATFORM_DESKTOP = 0x10000,   ///< Desktop
+  AMD_PLATFORM_MOBILE = 0x20000,    ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+  DDR2_TECHNOLOGY,      ///< DDR2 technology
+  DDR3_TECHNOLOGY       ///< DDR3 technology
+} TECHNOLOGY_TYPE;
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+typedef enum {
+  DDR400_FREQUENCY = 200,     ///< DDR 400
+  DDR533_FREQUENCY = 266,     ///< DDR 533
+  DDR667_FREQUENCY = 333,     ///< DDR 667
+  DDR800_FREQUENCY = 400,     ///< DDR 800
+  DDR1066_FREQUENCY = 533,    ///< DDR 1066
+  DDR1333_FREQUENCY = 667,    ///< DDR 1333
+  DDR1600_FREQUENCY = 800,    ///< DDR 1600
+  DDR1866_FREQUENCY = 933,    ///< DDR 1866
+  DDR2100_FREQUENCY = 1050,   ///< DDR 2100
+  DDR2133_FREQUENCY = 1066,   ///< DDR 2133
+  DDR2400_FREQUENCY = 1200,   ///< DDR 2400
+  UNSUPPORTED_DDR_FREQUENCY   ///< Highest limit of DDR frequency
+} MEMORY_BUS_SPEED;
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+typedef enum {
+  QUADRANK_REGISTERED,        ///< Quadrank registered DIMM
+  QUADRANK_UNBUFFERED         ///< Quadrank unbuffered DIMM
+} QUANDRANK_TYPE;
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+typedef enum {
+  TIMING_MODE_AUTO,           ///< Use best rate possible
+  TIMING_MODE_LIMITED,        ///< Set user top limit
+  TIMING_MODE_SPECIFIC        ///< Set user specified speed
+} USER_MEMORY_TIMING_MODE;
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+typedef enum {
+  POWER_DOWN_BY_CHANNEL,      ///< Channel power down mode
+  POWER_DOWN_BY_CHIP_SELECT,  ///< Chip select power down mode
+  POWER_DOWN_MODE_AUTO        ///< AGESA to select power down mode
+} POWER_DOWN_MODE;
+
+/// Low voltage support
+typedef enum {
+  VOLT_INITIAL,              ///< Initial value for VDDIO
+  VOLT1_5,                   ///< 1.5 Volt
+  VOLT1_35,                  ///< 1.35 Volt
+  VOLT1_25,                  ///< 1.25 Volt
+  VOLT_UNSUPPORTED = 0xFF    ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// UMA Mode
+typedef enum {
+  UMA_NONE = 0,              ///< UMA None
+  UMA_SPECIFIED = 1,         ///< UMA Specified
+  UMA_AUTO = 2               ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+  FORCE_TRAIN_1D = 0,              ///< 1D Training only
+  FORCE_TRAIN___ = 1,              ///<
+  FORCE_TRAIN_AUTO = 2             ///<  Auto
+} FORCE_TRAIN_MODE;
+
+///  The possible DRAM prefetch mode settings.
+typedef enum  {
+  DRAM_PREFETCHER_AUTO,                         ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_DRAM_PREFETCH_FOR_IO,                 ///< Disable DRAM prefetching for I/O requests only.
+  DISABLE_DRAM_PREFETCH_FOR_CPU,                ///< Disable DRAM prefetching for requests from processor cores only.
+  DISABLE_DRAM_PREFETCHER,                      ///< Disable DRAM prefetching.
+  MAX_DRAM_FREFETCH_MODE                        ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+  NO_UMA_ALIGNED = 0x00FFFFFF,           ///< NO UMA aligned
+  UMA_4MB_ALIGNED = 0x00FFFFC0,          ///< UMA 4MB aligned
+  UMA_128MB_ALIGNED = 0x00FFF800,        ///< UMA 128MB aligned
+  UMA_256MB_ALIGNED = 0x00FFF000,        ///< UMA 256MB aligned
+  UMA_512MB_ALIGNED = 0x00FFE000,        ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+///   Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+  GsbMTRRshort,              ///< Ran out of MTRRs while mapping memory
+  GsbAllECCDimms,            ///< All banks of all Nodes are ECC capable
+  GsbDramECCDis,             ///< Dram ECC requested but not enabled.
+  GsbSoftHole,               ///< A Node Base gap was created
+  GsbHWHole,                 ///< A HW dram remap was created
+  GsbNodeIntlv,              ///< Node Memory interleaving was enabled
+  GsbSpIntRemapHole,         ///< Special condition for Node Interleave and HW remapping
+  GsbEnDIMMSpareNW,          ///< Indicates that DIMM Spare can be used without a warm reset
+
+  GsbEOL                     ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+///   Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+  EsbNoDimms,                  ///< No DIMMs
+  EsbSpdChkSum,                ///< SPD Checksum fail
+  EsbDimmMismatchM,            ///< dimm module type(buffer) mismatch
+  EsbDimmMismatchT,            ///< dimm CL/T mismatch
+  EsbDimmMismatchO,            ///< dimm organization mismatch (128-bit)
+  EsbNoTrcTrfc,                ///< SPD missing Trc or Trfc info
+  EsbNoCycTime,                ///< SPD missing byte 23 or 25
+  EsbBkIntDis,                 ///< Bank interleave requested but not enabled
+  EsbDramECCDis,               ///< Dram ECC requested but not enabled
+  EsbSpareDis,                 ///< Online spare requested but not enabled
+  EsbMinimumMode,              ///< Running in Minimum Mode
+  EsbNoRcvrEn,                 ///< No DQS Receiver Enable pass window found
+  EsbSmallRcvr,                ///< DQS Rcvr En pass window too small (far right of dynamic range)
+  EsbNoDqsPos,                 ///< No DQS-DQ passing positions
+  EsbSmallDqs,                 ///< DQS-DQ passing window too small
+  EsbDCBKScrubDis,             ///< DCache scrub requested but not enabled
+
+  EsbEMPNotSupported,          ///< Processor is not capable for EMP.
+  EsbEMPConflict,               ///< EMP requested but cannot be enabled since
+                               ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+  EsbEMPDis,                   ///< EMP requested but cannot be enabled since
+                               ///< memory size of each DCT is not a power of two.
+
+  EsbEOL                       ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+///  Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+  SbRegistered,                ///< All DIMMs are Registered
+  SbEccDimms,                  ///< All banks ECC capable
+  SbParDimms,                  ///< All banks Addr/CMD Parity capable
+  SbDiagClks,                  ///< Jedec ALL slots clock enable diag mode
+  Sb128bitmode,                ///< DCT in 128-bit mode operation
+  Sb64MuxedMode,               ///< DCT in 64-bit mux'ed mode.
+  Sb2TMode,                    ///< 2T CMD timing mode is enabled.
+  SbSWNodeHole,                ///< Remapping of Node Base on this Node to create a gap.
+  SbHWHole,                    ///< Memory Hole created on this Node using HW remapping.
+  SbOver400Mhz,                ///< DCT freq greater than or equal to 400MHz flag
+  SbDQSPosPass2,               ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+  SbDQSRcvLimit,               ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+  SbExtConfig,                 ///< Indicate the default setting for extended PCI configuration support
+  SbLrdimms,                   ///< All DIMMs are LRDIMMs
+
+  SbEOL                        ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG     0xC0010010
+//#define TOP_MEM     0xC001001A
+//#define TOP_MEM2    0xC001001D
+#ifndef TOP_MEM
+  #define TOP_MEM			0xC001001A
+#endif
+#ifndef TOP_MEM2
+  #define TOP_MEM2			0xC001001D
+#endif
+#define HWCR        0xC0010015
+#define NB_CFG      0xC001001F
+
+#define FS_BASE     0xC0000100
+#define IORR0_BASE  0xC0010016
+#define IORR0_MASK  0xC0010017
+#define BU_CFG      0xC0011023
+#define BU_CFG2     0xC001102A
+#define COFVID_STAT 0xC0010071
+#define TSC         0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+  IN BOOLEAN DimmPresent;       ///< Indicates that the DIMM is present and Data is valid
+  IN UINT8 Data[256];           ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+  OUT UINT8   ChannelID;         ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+  OUT TECHNOLOGY_TYPE TechType;  ///< Technology type of this channel
+  OUT UINT8   ChDimmPresent;     ///< For each bit n 0..7, 1 = DIMM n is present.
+                                 ///<  DIMM#  Select Signal
+                                 ///<  0      MA0_CS_L[0, 1]
+                                 ///<  1      MB0_CS_L[0, 1]
+                                 ///<  2      MA1_CS_L[0, 1]
+                                 ///<  3      MB1_CS_L[0, 1]
+                                 ///<  4      MA2_CS_L[0, 1]
+                                 ///<  5      MB2_CS_L[0, 1]
+                                 ///<  6      MA3_CS_L[0, 1]
+                                 ///<  7      MB3_CS_L[0, 1]
+
+  OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+  OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+  OUT SPD_DEF_STRUCT *SpdPtr;    ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+  OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+                                 ///<   SPD Data for each Dimm. (Setup by Tech Block Constructor)
+  OUT UINT8   ChDimmValid;       ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+                                 ///<
+  OUT UINT8   RegDimmPresent;    ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+  OUT UINT8   LrDimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+  OUT UINT8   SODimmPresent;     ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+  OUT UINT8   Loads;             ///< Number of devices loading bus
+  OUT UINT8   Dimms;             ///< Number of DIMMs loading Channel
+  OUT UINT8   Ranks;             ///< Number of ranks loading Channel DATA
+  OUT BOOLEAN SlowMode;          ///< 1T or 2T CMD mode (slow access mode)
+                                 ///< FALSE = 1T
+                                 ///< TRUE = 2T
+  ///< The following pointers will be pointed to dynamically allocated buffers.
+  ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+  ///< Example: If DIMM and Byte based training, then
+  ///< XX is a value in Hex
+  ///<                        BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+  ///<  Row1 -  Logical DIMM0    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  ///<  Row2 -  Logical DIMM1    XX      XX      XX      XX      XX      XX      XX      XX      XX
+  OUT UINT16  *RcvEnDlys;       ///< DQS Receiver Enable Delays
+  OUT UINT8   *WrDqsDlys;       ///< Write DQS delays (only valid for DDR3)
+  OUT UINT8   *RdDqsDlys;       ///< Read Dqs delays
+  OUT UINT8   *WrDatDlys;       ///< Write Data delays
+  OUT UINT8   *RdDqs__Dlys;     ///< Read DQS data
+  OUT UINT8   *RdDqsMinDlys;    ///< Minimum Window for Read DQS
+  OUT UINT8   *RdDqsMaxDlys;    ///< Maximum Window for Read DQS
+  OUT UINT8   *WrDatMinDlys;    ///< Minimum Window for Write data
+  OUT UINT8   *WrDatMaxDlys;    ///< Maximum Window for Write data
+  OUT UINT16  *RcvEnDlysMemPs1;       ///< DQS Receiver Enable Delays for Mem Pstate 1
+  OUT UINT8   *WrDqsDlysMemPs1;       ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+  OUT UINT8   *RdDqsDlysMemPs1;       ///< Read Dqs delays for Memory Pstate 1
+  OUT UINT8   *WrDatDlysMemPs1;       ///< Write Data delays for Memory Pstate 1
+  OUT UINT8   *RdDqs__DlysMemPs1;     ///< Read DQS data for Memory Pstate 1
+  OUT UINT8   *RdDqsMinDlysMemPs1;    ///< Minimum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *RdDqsMaxDlysMemPs1;    ///< Maximum Window for Read DQS for Memory Pstate 1
+  OUT UINT8   *WrDatMinDlysMemPs1;    ///< Minimum Window for Write data for Memory Pstate 1
+  OUT UINT8   *WrDatMaxDlysMemPs1;    ///< Maximum Window for Write data for Memory Pstate 1
+  OUT UINT8   RowCount;         ///< Number of rows of the allocated buffer.
+  OUT UINT8   ColumnCount;      ///< Number of columns of the allocated buffer.
+  OUT UINT8   *FailingBitMask;    ///< Table of masks to Track Failing bits
+  OUT UINT8   *FailingBitMaskMemPs1;    ///< Table of masks to Track Failing bits for Memory Pstate 1
+  OUT UINT32  DctOdcCtl;          ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+  OUT UINT32  DctAddrTmg;         ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+  OUT UINT32  PhyRODTCSLow;       ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+  OUT UINT32  PhyRODTCSHigh;      ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+  OUT UINT32  PhyWODTCSLow;       ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+  OUT UINT32  PhyWODTCSHigh;      ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+  OUT UINT8   PhyWLODT[4];        ///< Write Levelization ODT Pattern for Dimm 0-3 (see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+  OUT UINT16  DctEccDqsLike;      ///< DCT DQS ECC UINT8 like...
+  OUT UINT8   DctEccDqsScale;     ///< DCT DQS ECC UINT8 scale
+  OUT UINT16  PtrPatternBufA;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT16  PtrPatternBufB;     ///< Ptr on stack to aligned DQS testing pattern
+  OUT UINT8   ByteLane;           ///< Current UINT8 Lane (0..7)
+  OUT UINT8   Direction;          ///< Current DQS-DQ training write direction (0=read, 1=write)
+  OUT UINT8   Pattern;            ///< Current pattern
+  OUT UINT8   DqsDelay;           ///< Current DQS delay value
+  OUT UINT16  HostBiosSrvc1;      ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT32  HostBiosSrvc2;      ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+  OUT UINT16  DctMaxRdLat[4];     ///< Max Read Latency (ns) for the DCT
+                                  ///< DctMaxRdLat [i] is for NBPstate i
+  OUT UINT8   DIMMValidCh;        ///< DIMM# in CH
+  OUT UINT8   MaxCh;              ///< Max number of CH in system
+  OUT UINT8   Dct;                ///< Dct pointer
+  OUT UINT8   WrDatGrossH;        ///< Write Data Gross delay high value
+  OUT UINT8   DqsRcvEnGrossL;     ///< DQS Receive Enable Gross Delay low
+
+  OUT UINT8   TrwtWB;             ///<  Non-SPD timing value for TrwtWB
+  OUT UINT8   CurrRcvrDctADelay;  ///< for keep current RcvrEnDly
+  OUT UINT16  T1000;              ///< get the T1000 figure (cycle time (ns) * 1K)
+  OUT UINT8   DqsRcvEnPass;       ///< for TrainRcvrEn UINT8 lane pass flag
+  OUT UINT8   DqsRcvEnSaved;      ///< for TrainRcvrEn UINT8 lane saved flag
+  OUT UINT8   SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+  OUT UINT8   ClToNbFlag;         ///< is used to restore ClLinesToNbDis bit after memory
+  OUT UINT32  NodeSysBase;        ///< for channel interleave usage
+  OUT UINT8   RefRawCard[MAX_DIMMS_PER_CHANNEL];   ///< Array of rawcards detected
+  OUT UINT8   CtrlWrd02[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 2 values per DIMM
+  OUT UINT8   CtrlWrd03[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 3 values per DIMM
+  OUT UINT8   CtrlWrd04[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 4 values per DIMM
+  OUT UINT8   CtrlWrd05[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 5 values per DIMM
+  OUT UINT8   CtrlWrd08[MAX_DIMMS_PER_CHANNEL];    ///< Control Word 8 values per DIMM
+
+  OUT UINT16  CsPresentDCT;       ///< For each bit n 0..7, 1 = Chip-select n is present
+  OUT UINT8   DimmMirrorPresent;  ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT8   DimmSpdCse;         ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT8   DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT8   DimmYr06;           ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+  OUT UINT8   DimmWk2406;         ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+  OUT UINT8   DimmPlPresent;      ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+  OUT UINT8   DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT8   DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present
+  OUT UINT8   Dimmx4Present;      ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx8Present;      ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+  OUT UINT8   Dimmx16Present;     ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+  OUT UINT8   LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+  OUT UINT8   LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+  OUT UINT8   LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+  OUT UINT8   DimmNibbleAccess;   ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+  OUT UINT8   *MemClkDisMap;      ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+                                  ///<  base on this array to disable unused MemClk to save power.
+                                  ///<
+                                  ///<  The array must have 8 entries. Each entry, which associates with
+                                  ///<  one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+                                  ///<    Example:
+                                  ///<    BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+                                  ///<    is like below:
+                                  ///<         Bit AM3/S1g3 pin name
+                                  ///<         0   M[B,A]_CLK_H/L[0]
+                                  ///<         1   M[B,A]_CLK_H/L[1]
+                                  ///<         2   M[B,A]_CLK_H/L[2]
+                                  ///<         3   M[B,A]_CLK_H/L[3]
+                                  ///<         4   M[B,A]_CLK_H/L[4]
+                                  ///<         5   M[B,A]_CLK_H/L[5]
+                                  ///<         6   M[B,A]_CLK_H/L[6]
+                                  ///<         7   M[B,A]_CLK_H/L[7]
+                                  ///<    And platform has the following routing:
+                                  ///<         CS0   M[B,A]_CLK_H/L[4]
+                                  ///<         CS1   M[B,A]_CLK_H/L[2]
+                                  ///<         CS2   M[B,A]_CLK_H/L[3]
+                                  ///<         CS3   M[B,A]_CLK_H/L[5]
+                                  ///<    Then MemClkDisMap should be pointed to the following array:
+                                  ///<               CLK_2 CLK_3 CLK_4 CLK_5
+                                  ///<    0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+                                  ///<  Each entry of the array is the bitmask of 8 chip selects.
+
+  OUT UINT8   *CKETriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of CKE pins to the DIMMs' ranks.
+                                  ///<  The array must have 2 entries. Each entry, which associates with
+                                  ///<  one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+                                  ///<  AGESA will base on this array to disable unused CKE pins to save power.
+
+  OUT UINT8   *ODTTriMap;         ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of ODT pins to the DIMMs' ranks.
+                                  ///<  The array must have 4 entries. Each entry, which associates with
+                                  ///<  one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+                                  ///<  AGESA will base on this array to disable unused ODT pins to save power.
+
+  OUT UINT8   *ChipSelTriMap;     ///<  This pointer will be set to point to an array that describes
+                                  ///<  the routing of chip select pins to the DIMMs' ranks.
+                                  ///<  The array must have 8 entries. Each entry is a bitmap of 8 CS.
+                                  ///<  AGESA will base on this array to disable unused Chip select pins to save power.
+
+  OUT BOOLEAN   ExtendTmp;        ///<  If extended temperature is supported on all dimms on a channel.
+
+  OUT UINT8   MaxVref;            ///<  Maximum Vref Value for channel
+
+  OUT UINT8   Reserved[100];      ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+  OUT UINT16  DctDimmValid;       ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+  OUT UINT16  DimmMirrorPresent;  ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+  OUT UINT16  DimmSpdCse;         ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+  OUT UINT16  DimmExclude;        ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+  OUT UINT16  CsPresent;          ///< For each bit n 0..7, 1=Chip-select n is present
+  OUT UINT16  CsEnabled;          ///< For each bit n 0..7, 1=Chip-select n is enabled
+  OUT UINT16  CsTestFail;         ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+  OUT UINT16  CsTrainFail;        ///< Bitmap showing which chipselects failed training
+  OUT UINT16  DIMM1KPage;         ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+  OUT UINT16  DimmQrPresent;      ///< QuadRank DIMM present?
+  OUT UINT16  DimmDrPresent;      ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+  OUT UINT8   DimmSRPresent;      ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+  OUT UINT16  Dimmx4Present;      ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx8Present;      ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+  OUT UINT16  Dimmx16Present;     ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+  OUT UINT16  DIMMTrcd;           ///< Minimax Trcd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrp;            ///< Minimax Trp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrtp;           ///< Minimax Trtp*40 (ns) of DIMMs
+  OUT UINT16  DIMMTras;           ///< Minimax Tras*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrc;            ///< Minimax Trc*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwr;            ///< Minimax Twr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTrrd;           ///< Minimax Trrd*40 (ns) of DIMMs
+  OUT UINT16  DIMMTwtr;           ///< Minimax Twtr*40 (ns) of DIMMs
+  OUT UINT16  DIMMTfaw;           ///< Minimax Tfaw*40 (ns) of DIMMs
+  OUT UINT16  TargetSpeed;        ///< Target DRAM bus speed in MHz
+  OUT UINT16  Speed;              ///< DRAM bus speed in MHz
+                                  ///<  400 (MHz)
+                                  ///<  533 (MHz)
+                                  ///<  667 (MHz)
+                                  ///<  800 (MHz)
+                                  ///<  and so on...
+  OUT UINT8   CasL;               ///< CAS latency DCT setting (busclocks)
+  OUT UINT8   Trcd;               ///< DCT Trcd (busclocks)
+  OUT UINT8   Trp;                ///< DCT Trp (busclocks)
+  OUT UINT8   Trtp;               ///< DCT Trtp (busclocks)
+  OUT UINT8   Tras;               ///< DCT Tras (busclocks)
+  OUT UINT8   Trc;                ///< DCT Trc (busclocks)
+  OUT UINT8   Twr;                ///< DCT Twr (busclocks)
+  OUT UINT8   Trrd;               ///< DCT Trrd (busclocks)
+  OUT UINT8   Twtr;               ///< DCT Twtr (busclocks)
+  OUT UINT8   Tfaw;               ///< DCT Tfaw (busclocks)
+  OUT UINT8   Trfc0;              ///< DCT Logical DIMM0 Trfc
+                                  ///<  0 = 75ns (for 256Mb devs)
+                                  ///<  1 = 105ns (for 512Mb devs)
+                                  ///<  2 = 127.5ns (for 1Gb devs)
+                                  ///<  3 = 195ns (for 2Gb devs)
+                                  ///<  4 = 327.5ns (for 4Gb devs)
+  OUT UINT8   Trfc1;              ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc2;              ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+  OUT UINT8   Trfc3;              ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+  OUT UINT32  DctMemSize;         ///< Base[47:16], total DRAM size controlled by this DCT.
+                                  ///<
+  OUT BOOLEAN SlowMode;           ///< 1T or 2T CMD mode (slow access mode)
+                                  ///< FALSE = 1T
+                                  ///< TRUE = 2T
+  OUT UINT8   TrwtTO;             ///< DCT TrwtTO (busclocks)
+  OUT UINT8   Twrrd;              ///< DCT Twrrd (busclocks)
+  OUT UINT8   Twrwr;              ///< DCT Twrwr (busclocks)
+  OUT UINT8   Trdrd;              ///< DCT Trdrd (busclocks)
+  OUT UINT8   TrwtWB;             ///< DCT TrwtWB (busclocks)
+  OUT UINT8   TrdrdSD;            ///< DCT TrdrdSD (busclocks)
+  OUT UINT8   TwrwrSD;            ///< DCT TwrwrSD (busclocks)
+  OUT UINT8   TwrrdSD;            ///< DCT TwrrdSD (busclocks)
+  OUT UINT16  MaxRdLat;           ///< Max Read Latency
+  OUT UINT8   WrDatGrossH;        ///< Temporary variables must be removed
+  OUT UINT8   DqsRcvEnGrossL;     ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+  OUT UINT8   Dct;                ///< Current Dct
+  OUT CH_TIMING_STRUCT Timings;   ///< Channel Timing structure
+  OUT CH_TIMING_STRUCT *TimingsMemPs1;   ///< Pointed to channel timing structure for memory Pstate 1
+  OUT CH_DEF_STRUCT    *ChData;   ///< Pointed to a dynamically allocated array of Channel structures
+  OUT UINT8   ChannelCount;       ///< Number of channel per this DCT
+  OUT BOOLEAN BkIntDis;           ///< Bank interleave requested but not enabled on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+  /// Advanced:
+
+  OUT UINT8   NodeId;              ///< Node ID of current controller
+  OUT UINT8   SocketId;            ///< Socket ID of this Die
+  OUT UINT8   DieId;               ///< ID of this die relative to the socket
+  OUT PCI_ADDR      PciAddr;       ///< Pci bus and device number of this controller.
+  OUT AGESA_STATUS  ErrCode;       ///< Current error condition of Node
+                                   ///<  0x0 = AGESA_SUCCESS
+                                   ///<  0x1 = AGESA_UNSUPPORTED
+                                   ///<  0x2 = AGESA_BOUNDS_CHK
+                                   ///<  0x3 = AGESA_ALERT
+                                   ///<  0x4 = AGESA_WARNING
+                                   ///<  0x5 = AGESA_ERROR
+                                   ///<  0x6 = AGESA_CRITICAL
+                                   ///<  0x7 = AGESA_FATAL
+                                   ///<
+  OUT BOOLEAN ErrStatus[EsbEOL];   ///< Error Status bit Field
+                                   ///<
+  OUT BOOLEAN Status[SbEOL];       ///< Status bit Field
+                                   ///<
+  OUT UINT32  NodeMemSize;         ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+                                   ///<
+  OUT UINT32  NodeSysBase;         ///< Base[47:16] (system address) DRAM base address of this Node.
+                                   ///<
+  OUT UINT32  NodeHoleBase;        ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping.  Dram hole exists on this Node
+                                   ///<
+  OUT UINT32  NodeSysLimit;        ///< Base[47:16] (system address) DRAM limit address of this Node.
+                                   ///<
+  OUT UINT32  DimmPresent;         ///< For each bit n 0..7, 1 = DIMM n is present.
+                                   ///<   DIMM#  Select Signal
+                                   ///<   0      MA0_CS_L[0, 1]
+                                   ///<   1      MB0_CS_L[0, 1]
+                                   ///<   2      MA1_CS_L[0, 1]
+                                   ///<   3      MB1_CS_L[0, 1]
+                                   ///<   4      MA2_CS_L[0, 1]
+                                   ///<   5      MB2_CS_L[0, 1]
+                                   ///<   6      MA3_CS_L[0, 1]
+                                   ///<   7      MB3_CS_L[0, 1]
+                                   ///<
+  OUT UINT32  DimmValid;           ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+  OUT UINT32  RegDimmPresent;      ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+  OUT UINT32  LrDimmPresent;       ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+  OUT UINT32  DimmEccPresent;      ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+  OUT UINT32  DimmParPresent;      ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+                                   ///<
+  OUT UINT16  DimmTrainFail;       ///< Bitmap showing which dimms failed training
+  OUT UINT16  ChannelTrainFail;    ///< Bitmap showing the channel information about failed Chip Selects
+                                   ///<  0 in any bit field indicates Channel 0
+                                   ///<  1 in any bit field indicates Channel 1
+  OUT UINT8   Dct;                 ///<  Need to be removed
+                                   ///<  DCT pointer
+  OUT BOOLEAN GangedMode;          ///< Ganged mode
+                                   ///<  0 = disabled
+                                   ///<  1 = enabled
+  OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+                                   ///<
+  OUT UINT16  HostBiosSrvc1;       ///< UINT16 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT32  HostBiosSrvc2;       ///< UINT32 sized general purpose field for use by host BIOS.  Scratch space.
+                                   ///<
+  OUT UINT8   MLoad;               ///< Need to be removed
+                                   ///< Number of devices loading MAA bus
+                                   ///<
+  OUT UINT8   MaxAsyncLat;         ///< Legacy wrapper
+                                   ///<
+  OUT UINT8   ChbD3Rcvrdly;        ///< Legacy wrapper
+                                   ///<
+  OUT UINT16  ChaMaxRdLat;         ///< Max Read Latency (ns) for DCT 0
+                                   ///<
+  OUT UINT8   ChbD3BcRcvrdly;      ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+  OUT DCT_STRUCT *DctData;         ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+  OUT UINT8   DctCount;            ///< Number of DCTs per this Die
+  OUT UINT8   Reserved[16];        ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+     OUT   UINT32 Signature;           ///< "ASTR" for AMD Suspend-To-RAM
+     OUT   UINT16 Version;             ///< S3 Params version number
+  IN OUT   UINT32 Flags;               ///< Indicates operation
+  IN OUT   VOID   *NvStorage;          ///< Pointer to memory critical save state data
+  IN OUT   UINT32 NvStorageSize;       ///< Size in bytes of the NvStorage region
+  IN OUT   VOID   *VolatileStorage;    ///< Pointer to remaining AMD save state data
+  IN OUT   UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+  // Basic (Return parameters)
+  // (This section contains the outbound parameters from the memory init code)
+
+  OUT BOOLEAN GStatus[GsbEOL];    ///< Global Status bitfield.
+                                  ///<
+  OUT UINT32 HoleBase;            ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+                                  ///<
+  OUT UINT32 Sub4GCacheTop;       ///< If not zero, the 32-bit top of cacheable memory.
+                                  ///<
+  OUT UINT32 Sub1THoleBase;       ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+                                  ///<
+  OUT UINT32 SysLimit;            ///< Limit[47:16] (system address).
+                                  ///<
+  OUT DIMM_VOLTAGE DDR3Voltage;   ///< Find support voltage and send back to platform BIOS.
+                                  ///<
+  OUT UINT8 ExternalVrefValue;    ///< Target reference voltage for external Vref for training
+                                  ///<
+  OUT struct _MEM_DATA_STRUCT *MemData;   ///< Access to global memory init data.
+
+  //  Advanced (Optional parameters)
+  //  Optional (all defaults values will be initialized by the
+  //  'AmdMemInitDataStructDef' based on AMD defaults. It is up
+  //  to the IBV/OEM to change the defaults after initialization
+  //  but prior to the main entry to the memory code):
+
+  // Memory Map/Mgt.
+
+  IN UINT16  BottomIo;             ///< Bottom of 32-bit IO space (8-bits).
+                                   ///<   NV_BOTTOM_IO[7:0]=Addr[31:24]
+                                   ///<
+  IN BOOLEAN MemHoleRemapping;     ///< Memory Hole Remapping (1-bit).
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+  IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+                                   ///<  FALSE = disable
+                                   ///<  TRUE  = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+  // Dram Timing
+
+  IN USER_MEMORY_TIMING_MODE   UserTimingMode;  ///< User Memclock Mode.
+                                                ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+  IN MEMORY_BUS_SPEED          MemClockValue;   ///< Memory Clock Value.
+                                                ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+  // Dram Configuration
+
+  IN BOOLEAN EnableBankIntlv;      ///< Dram Bank (chip-select) Interleaving (1-bit).
+                                   ///<  - FALSE =disable (default)
+                                   ///<  - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+  IN BOOLEAN EnableNodeIntlv;      ///< Node Memory Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+  IN BOOLEAN EnableChannelIntlv;   ///< Channel Interleaving (1-bit).
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+  // ECC
+
+  IN BOOLEAN EnableEccFeature;     ///< enable ECC error to go into MCE.
+                                   ///<   - FALSE = disable (default)
+                                   ///<   - TRUE = enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+  // Dram Power
+
+  IN BOOLEAN EnablePowerDown;      ///< CKE based power down mode (1-bit).
+                                   ///<   - FALSE =disable (default)
+                                   ///<   - TRUE =enable
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+  // Online Spare
+
+  IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+                                   ///<  - FALSE = disable Spare (default)
+                                   ///<  - TRUE = enable Spare
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+  IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+  IN PSO_TABLE *PlatformMemoryConfiguration;
+                                   ///< A table that contains platform specific settings.
+                                   ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+                                   ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+                                   ///< contains default conservative settings. Platform BIOS can either tweak
+                                   ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+                                   ///<
+  IN BOOLEAN EnableParity;         ///< Parity control.
+                                   ///<  - TRUE = enable
+                                   ///<  - FALSE = disable (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+  IN BOOLEAN EnableBankSwizzle;    ///< BankSwizzle control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+                                   ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+                                   ///<
+
+  IN BOOLEAN EnableMemClr;         ///< Memory Clear functionality control.
+                                   ///<  - FALSE = disable
+                                   ///<  - TRUE = enable  (default)
+                                   ///<
+
+  // Uma Configuration
+
+  IN UMA_MODE UmaMode;             ///<  Uma Mode
+                                   ///<  0 = None
+                                   ///<  1 = Specified
+                                   ///<  2 = Auto
+  IN OUT UINT32 UmaSize;           ///<  The size of shared graphics dram (16-bits)
+                                   ///<  NV_UMA_Size[31:0]=Addr[47:16]
+                                   ///<
+  OUT UINT32 UmaBase;              ///<  The allocated Uma base address (32-bits)
+                                   ///<  NV_UMA_Base[31:0]=Addr[47:16]
+                                   ///<
+
+  /// Memory Restore Feature
+
+  IN BOOLEAN MemRestoreCtl;        ///< Memory context restore control
+                                   ///<   FALSE = perform memory init as normal (AMD default)
+                                   ///<   TRUE = restore memory context and skip training. This requires
+                                   ///<          MemContext is valid before AmdInitPost
+                                   ///<
+  IN BOOLEAN SaveMemContextCtl;    ///< Control switch to save memory context at the end of MemAuto
+                                   ///<   TRUE = AGESA will setup MemContext block before exit AmdInitPost
+                                   ///<   FALSE = AGESA will not setup MemContext block. Platform is
+                                   ///<           expected to call S3Save later in POST if it wants to
+                                   ///<           use memory context restore feature.
+                                   ///<
+  IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+                                   ///< save and restore for memory context restore feature to work.
+                                   ///< It uses the subset of S3Save block to save/restore. Hence platform
+                                   ///< may save only S3 block and uses it for both S3 resume and
+                                   ///< memory context restore.
+                                   ///<  - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+                                   ///<    before AmdInitPost.
+                                   ///<  - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+                                   ///<    right after AmdInitPost.
+                                   ///<
+  IN BOOLEAN ExternalVrefCtl;      ///< Control the use of external Vref
+                                   ///<   TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+                                   ///<          to change the vref
+                                   ///<   FALSE = AGESA will will use the internal vref control.
+                                   ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+                                   ///<
+  IN FORCE_TRAIN_MODE ForceTrainMode;   ///<  Training Mode
+                                   ///<  0 = Force 1D Training for all configurations
+                                   ///<  1 = Force training for all configurations
+                                   ///<  2 = Auto - AGESA will control
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+  // PUBLIC required Internal functions
+
+  IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData);  ///< Proc for Unbuffered DIMMs, platform specific
+  IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData);   ///< Proc for Registered DIMMs, platform specific
+
+  // PUBLIC optional functions
+
+  IN OUT VOID (*amdMemEccInit) (VOID *pMemData);                  ///< NB proc for ECC feature
+  IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+  IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData);      ///< NB proc for Channel interleave feature
+  IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData);      ///< NB proc for Node interleave feature
+  IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData);         ///< NB proc for parallel training feature
+  IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData);       ///< NB code for early sample support feature
+  IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData);     ///< NB code for 'multi-part'
+  IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData);       ///< NB code for On-Line Spare feature
+  IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData);                ///< NB code for UDIMMs
+  IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData);                ///< NB code for RDIMMs
+  IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData);               ///< NB code for LRDIMMs
+  IN OUT UINT32   Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+  OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels training data
+
+  OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET];  ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+  IN AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+
+  IN MEM_PARAMETER_STRUCT *ParameterListPtr;  ///< List of input Parameters
+
+  OUT MEM_FUNCTION_STRUCT FunctionList;       ///< List of function Pointers
+
+  IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+  IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+  OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED];  ///< Socket list for memory code.
+                                   ///< SocketList is a shortcut for IBVs to retrieve training
+                                   ///< and timing data for each channel indexed by socket/channel,
+                                   ///< eliminating their need to parse die/dct/channel etc.
+                                   ///< It contains pointers to the populated data structures for
+                                   ///< each channel and skips the channel structures that are
+                                   ///< unpopulated. In the case of channels sharing the same DCT,
+                                   ///< the pTimings pointers will point to the same DCT Timing data.
+
+  OUT DIE_STRUCT *DiesPerSystem;  ///< Pointed to an array of DIE_STRUCTs
+  OUT UINT8      DieCount;        ///< Number of MCTs in the system.
+
+  IN SPD_DEF_STRUCT *SpdDataStructure;              ///< Pointer to SPD Data structure
+
+  IN OUT  struct _PLATFORM_CONFIGURATION   *PlatFormConfig;    ///< Platform profile/build option config structure
+
+  IN OUT BOOLEAN IsFlowControlSupported;    ///< Indicates if flow control is supported
+
+  OUT UINT32 TscRate;             ///< The rate at which the TSC increments in megahertz.
+
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+  OUT UINT64 UmaBase;          ///< UmaBase[63:0] = Addr[63:0]
+  OUT UINT32 UmaSize;          ///< UmaSize[31:0] = Addr[31:0]
+  OUT UINT32 UmaAttributes;    ///< Indicate the attribute of Uma
+  OUT UINT8 UmaMode;           ///< Indicate the mode of Uma
+  OUT UINT16 MemClock;         ///< Indicate memory running speed in MHz
+  OUT UINT8 Reserved[3];       ///< Reserved for future usage
+} UMA_INFO;
+
+/// Bitfield for ID
+typedef struct {
+  OUT UINT16 SocketId:8;       ///< Socket ID
+  OUT UINT16 ModuleId:8;       ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+  OUT ID_FIELD IdField;         ///< Bitfield for ID
+  OUT UINT16 IdInformation;     ///< ID information for call out
+} ID_INFO;
+
+//  AGESA MEMORY ERRORS
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED   0x04010000 ///< TIMING_MODE_SPECIFIC is requested but
+                                                       ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100          ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200                 ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300     ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300  ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300     ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300  ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500 ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300 ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300 ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600 ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700 ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800 ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900 ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00 ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00 ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00 ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00 ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00 ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00 ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00 ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00 ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000 ///< Time out when polling FlushWr bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300 ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300 ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300 ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100 ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT  0x040A0300 ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300 ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR  0x04011200    ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300              ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500   ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300   ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO____RDDQS_WINDOW 0x040D0300           ///< No RdDqs Window
+#define MEM_ERROR_NO____RDDQS_HEIGHT 0x040E0300  ///< No RdDqs Height
+#define MEM_ERROR____DQS_ERROR  0x040F0300 ///< RdDqs Error
+#define MEM_ERROR_INVALID____RDDQS_VALUE  0x04022400 ///< RdDqs invalid value found
+#define MEM_ERROR____DQS_VREF_MARGIN_ERROR  0x04023400 ///< RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND  0x04013500 ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND  0x04023500 ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND  0x04033500 ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND  0x04043500 ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND  0x04053500 ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND  0x04063500 ///< No RTT value is found
+#define MEM_ERROR_P___NOT_FOUND  0x04073500 ///< No training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND  0x04083500 ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND  0x04093500 ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND  0x040A3500 ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND  0x040B3500 ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND  0x040C3500 ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND  0x040D3500 ///< No training seed is found
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM      0x04011600 ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM       0x04021600 ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM      0x04031600 ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM      0x04041600 ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM       0x04051600 ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM      0x04061600 ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED       0x04011700 ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT            0x04021700  ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED         0x04031700  ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS                 0x04041700  ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800  ///< Performance has been enabled, but battery life is preferred.
+                                                        ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND         0x04011900  ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000    ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100 ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200 ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300 ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO   0x04012400 ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO   0x04012500 ///< Cannot find a commonly supported VDDIO
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00               ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00  ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00    ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS  0x04011D00      ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00                ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS   0x04011F00 ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs   0x04021F00 ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV   0x04031F00 ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD     0x04041F00    ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA     0x04051F00    ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS     0x04061F00    ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA     0x04071F00   ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK     0x04081F00    ///< Heap allocation error for  DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM     0x04022300   ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED      0x04022500     ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR___     0x040B1F00    ///< Heap allocation error for training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR___     0x040C1F00    ///< Heap de-allocation error for training data
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3     0x04091F00    ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2     0x040A1F00    ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG              0x04011400    ///< Dimm population is not supported
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ *                    CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK                         0xFF00FF00
+#define CPU_EVENT_PM_EVENT_CLASS                        0x08000400
+
+//================================================================
+// CPU General events
+//    Heap allocation                     (AppFunction =      01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT            0x08000100
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED           0x08010100
+#define CPU_ERROR_HEAP_IS_FULL                          0x08020100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED    0x08030100
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100
+//    BrandId                             (AppFunction =      02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE            0x08000200
+//    Micro code patch                    (AppFunction =      03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED        0x08000300
+//    Power management                    (AppFunction =      04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT                 0x08000400
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT             0x08010400
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE             0x08020400
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH                 0x08030400
+//    Other CPU events                    (AppFunction =      05h)
+#define CPU_EVENT_BIST_ERROR                            0x08000500
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY              0x08010500
+#define CPU_EVENT_STACK_REENTRY                         0x08020500
+#define CPU_EVENT_CORE_NOT_IDENTIFIED                   0x08030500
+
+//=================================================================
+// CPU Feature events
+//    Execution cache                     (AppFunction =      21h)
+//        AGESA_CACHE_SIZE_REDUCED                            2101
+//        AGESA_CACHE_REGIONS_ACROSS_1MB                      2102
+//        AGESA_CACHE_REGIONS_ACROSS_4GB                      2103
+//        AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY                2104
+//        AGESA_CACHE_START_ADDRESS_LESS_D0000                2105
+//        AGESA_THREE_CACHE_REGIONS_ABOVE_1MB                 2106
+//        AGESA_DEALLOCATE_CACHE_REGIONS                      2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR      0x08002100
+//    Core Leveling                       (AppFunction =      22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE              0x08002200
+//    HT Assist                           (AppFunction =      23h)
+#define CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG            0x08002300
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+  IN  UINT32 MsrAddr;     ///< Fixed-Sized MTRR address
+  IN  UINT64 MsrData;     ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000    0x00000250
+#define AMD_AP_MTRR_FIX16k_80000    0x00000258
+#define AMD_AP_MTRR_FIX16k_A0000    0x00000259
+#define AMD_AP_MTRR_FIX4k_C0000     0x00000268
+#define AMD_AP_MTRR_FIX4k_C8000     0x00000269
+#define AMD_AP_MTRR_FIX4k_D0000     0x0000026A
+#define AMD_AP_MTRR_FIX4k_D8000     0x0000026B
+#define AMD_AP_MTRR_FIX4k_E0000     0x0000026C
+#define AMD_AP_MTRR_FIX4k_E8000     0x0000026D
+#define AMD_AP_MTRR_FIX4k_F0000     0x0000026E
+#define AMD_AP_MTRR_FIX4k_F8000     0x0000026F
+#define CPU_LIST_TERMINAL           0xFFFFFFFF
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+  IN    UINT16 IdsNvId;           ///< Unified ID for IDS Setup Option.
+  OUT UINT16 IdsNvValue;        ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+  IN    AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN    IDS_NV_ITEM *IdsNvPtr;              ///< Memory Pointer of IDS NV Table
+  IN OUT UINTN Reserved;              ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN OUT    UINT32              BufferLength;   ///< Size of buffer to allocate
+  IN        UINT32              BufferHandle;   ///< Identifier or name for the buffer
+  OUT       VOID                *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;            ///< Standard configuration header
+  IN        UINT32              FunctionNumber;       ///< Index of the procedure to execute
+  IN        VOID                *RelatedDataBlock;    ///< Location of data structure the procedure will use
+  IN        UINT32              RelatedBlockLength;   ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+  IN OUT    AMD_CONFIG_PARAMS   StdHeader;      ///< Standard configuration header
+  IN        UINT8               SocketId;       ///< Address of SPD - socket ID
+  IN        UINT8               MemChannelId;   ///< Address of SPD - memory channel ID
+  IN        UINT8               DimmId;         ///< Address of SPD - DIMM ID
+  IN OUT    UINT8               *Buffer;        ///< Location where to place the SPD content
+  IN OUT    MEM_DATA_STRUCT     *MemData;       ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// Buffer Handles
+typedef enum {
+  AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000,       ///< Assign 0x000D000 buffer handle to DMI function
+  AMD_PSTATE_DATA_BUFFER_HANDLE,                ///< Assign 0x000D001 buffer handle to Pstate data
+  AMD_PSTATE_ACPI_BUFFER_HANDLE,                ///< Assign 0x000D002 buffer handle to Pstate table
+  AMD_BRAND_ID_BUFFER_HANDLE,                   ///< Assign 0x000D003 buffer handle to Brand ID
+  AMD_ACPI_SLIT_BUFFER_HANDLE,                  ///< Assign 0x000D004 buffer handle to SLIT function
+  AMD_SRAT_INFO_BUFFER_HANDLE,                  ///< Assign 0x000D005 buffer handle to SRAT function
+  AMD_WHEA_BUFFER_HANDLE,                       ///< Assign 0x000D006 buffer handle to WHEA function
+  AMD_S3_INFO_BUFFER_HANDLE,                    ///< Assign 0x000D007 buffer handle to S3 function
+  AMD_S3_NB_INFO_BUFFER_HANDLE,                 ///< Assign 0x000D008 buffer handle to S3 NB device info
+  AMD_ACPI_ALIB_BUFFER_HANDLE,                  ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+  AMD_ACPI_IVRS_BUFFER_HANDLE                   ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
+} AMD_BUFFER_HANDLE;
+/************************************************************************
+ *
+ *  AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+  IN        UINTN               ResetType,
+  IN OUT    AMD_CONFIG_PARAMS   *StdHeader
+  );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *AllocParams
+  );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *DeallocParams
+  );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+  IN      UINTN                 FcnData,
+  IN OUT  AGESA_BUFFER_PARAMS   *LocateParams
+  );
+
+AGESA_STATUS
+AgesaReadSpd (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+  IN        UINTN                 FcnData,
+  IN OUT    AGESA_READ_SPD_PARAMS *ReadSpd
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+  IN       UINTN           FcnData,
+  IN OUT   MEM_DATA_STRUCT *MemData
+  );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+  IN        UINTN               ApicIdOfCore,
+  IN        AP_EXE_PARAMS       *LaunchApParams
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+  IN        UINTN               FcnData,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+  IN      UINTN                 FcnData,
+  IN      PCIe_SLOT_RESET_INFO  *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+  IN      VOID                  *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal__TrainVrefChange (
+  IN        UINTN               SocketIdModuleId,
+  IN OUT    MEM_DATA_STRUCT     *MemData
+  );
+
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+/************************************************************************
+ *
+ *  AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration:  The parameters in boot branch function
+ **********************************************************************/
+
+///  The possible platform control flow settings.
+typedef enum  {
+  Nfcm,                                          ///< Normal Flow Control Mode.
+  UmaDr,                                         ///< UMA using Display Refresh flow control.
+  UmaIfcm,                                       ///< UMA using Isochronous Flow Control.
+  Ifcm,                                          ///< Isochronous Flow Control Mode (other than for UMA).
+  Iommu,                                         ///< An IOMMU is in use in the system.
+  MaxControlFlow                                 ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+///  Platform Deemphasis Levels.
+///
+/// The deemphasis level is set for the receiver, based on link characterization.  The DCV level is
+/// set based on the level of the far transmitter.
+typedef enum {
+  DeemphasisLevelNone,                           ///< No Deemphasis.
+  DeemphasisLevelMinus3,                         ///< Minus 3 db deemphasis.
+  DeemphasisLevelMinus6,                         ///< Minus 6 db deemphasis.
+  DeemphasisLevelMinus8,                         ///< Minus 8 db deemphasis.
+  DeemphasisLevelMinus11,                        ///< Minus 11 db deemphasis.
+  DeemphasisLevelMinus11pre8,                    ///< Minus 11, Minus 8 precursor db deemphasis.
+  DcvLevelNone = 16,                             ///< No DCV Deemphasis.
+  DcvLevelMinus2,                                ///< Minus 2 db DCV deemphasis.
+  DcvLevelMinus3,                                ///< Minus 3 db DCV deemphasis.
+  DcvLevelMinus5,                                ///< Minus 5 db DCV deemphasis.
+  DcvLevelMinus6,                                ///< Minus 6 db DCV deemphasis.
+  DcvLevelMinus7,                                ///< Minus 7 db DCV deemphasis.
+  DcvLevelMinus8,                                ///< Minus 8 db DCV deemphasis.
+  DcvLevelMinus9,                                ///< Minus 9 db DCV deemphasis.
+  DcvLevelMinus11,                               ///< Minus 11 db DCV deemphasis.
+  MaxPlatformDeemphasisLevel                     ///< Not a deemphasis level, use for limit checking.
+} PLATFORM_DEEMPHASIS_LEVEL;
+
+///  Provide Deemphasis Levels for HT Links.
+///
+///  For each CPU to CPU or CPU to IO device HT link, the list of Deemphasis Levels will
+///  be checked for a match.  The item matches for a Socket, Link if the link frequency is
+///  is in the inclusive range HighFreq:LoFreq.
+///  AGESA does not set deemphasis in IO devices, only in processors.
+
+typedef struct {
+  // Match fields
+  IN       UINT8 Socket;                                        ///< One Socket on which this Link is located
+  IN       UINT8 Link;                                          ///< The Link on this Processor.
+  IN       UINT8 LoFreq;                                        ///< If the link is set to this frequency or greater, apply these levels, and
+  IN       UINT8 HighFreq;                                      ///< If the link is set to this frequency or less, apply these levels.
+  // Value fields
+  IN       PLATFORM_DEEMPHASIS_LEVEL     ReceiverDeemphasis;    ///< The deemphasis level for this link
+  IN       PLATFORM_DEEMPHASIS_LEVEL     DcvDeemphasis;         ///< The DCV, or far transmitter deemphasis level.
+} CPU_HT_DEEMPHASIS_LEVEL;
+
+
+///  The possible hardware prefetch mode settings.
+typedef enum  {
+  HARDWARE_PREFETCHER_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_L1_PREFETCHER,                        ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching.
+  DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+  DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES,  ///< Use the recommended settings for the hardware prefetcher, but disable both the L1 prefetcher and training on software prefetches.
+  DISABLE_HARDWARE_PREFETCH,                    ///< Disable hardware prefetching.
+  MAX_HARDWARE_PREFETCH_MODE                    ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+///  The possible software prefetch mode settings.
+typedef enum  {
+  SOFTWARE_PREFETCHES_AUTO,                     ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+  DISABLE_SOFTWARE_PREFETCHES,                  ///< Disable software prefetches (convert software prefetch instructions to NOP).
+  MAX_SOFTWARE_PREFETCH_MODE                    ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+  IN HARDWARE_PREFETCH_MODE  HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+  IN SOFTWARE_PREFETCH_MODE  SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+  IN DRAM_PREFETCH_MODE      DramPrefetchMode;     ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+///  The possible platform power policy settings.
+typedef enum  {
+  Performance,                                   ///< Optimize for performance.
+  BatteryLife,                                   ///< Optimize for battery life.
+  MaxPowerPolicy                                 ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+///  Platform performance settings for optimized settings.
+///  Several configuration settings for the processor depend upon other parts and
+///  general designer choices for the system. The determination of these data points
+///  is not standard for all platforms, so the host environment needs to provide these
+///  to specify how the system is to be configured.
+typedef struct {
+  IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode;    ///< The platform's control flow mode for optimum platform performance.
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+  IN BOOLEAN               UseHtAssist;                ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_HT_ASSIST}
+  IN BOOLEAN               UseAtmMode;                 ///< HyperTransport link traffic optimization.
+                                                       ///< @BldCfgItem{BLDCFG_USE_ATM_MODE}
+  IN BOOLEAN               Use32ByteRefresh;           ///< Display Refresh traffic generates 32 byte requests.
+                                                       ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+  IN BOOLEAN               UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+                                                       ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+  IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile;   ///< The advanced platform performance settings.
+  IN PLATFORM_POWER_POLICY PlatformPowerPolicy;        ///< The platform's desired power policy
+                                                       ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+} PERFORMANCE_PROFILE;
+
+///  Platform settings that describe the voltage regulator modules of the system.
+///  Many power management settings are dependent upon the characteristics of the
+///  on-board voltage regulator module (VRM).  The host environment needs to provide
+///  these to specify how the system is to be configured.
+typedef struct {
+  IN UINT32  CurrentLimit;                         ///< Vrm Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+  IN UINT32  LowPowerThreshold;                    ///< Vrm Low Power Threshold.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+  IN UINT32  SlewRate;                             ///< Vrm Slew Rate.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+  IN UINT32  AdditionalDelay;                      ///< Vrm Additional Delay.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_ADDITIONAL_DELAY}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_ADDITIONAL_DELAY}
+  IN BOOLEAN HiSpeedEnable;                        ///< Select high speed VRM.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+  IN UINT32  InrushCurrentLimit;                   ///< Vrm Inrush Current Limit.
+                                                   ///< @BldCfgItem{BLDCFG_VRM_INRUSH_CURRENT_LIMIT}
+                                                   ///< @BldCfgItem{BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT}
+} PLATFORM_VRM_CONFIGURATION;
+
+///  The VRM types to characterize.
+typedef enum  {
+  CoreVrm,                                       ///< VDD plane.
+  NbVrm,                                         ///< VDDNB plane.
+  MaxVrmType                                     ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// FCH Platform Configuration Policy
+typedef struct {
+  IN UINT16     CfgSmbus0BaseAddress;             ///< SMBUS0 Controller Base Address
+  IN UINT16     CfgSmbus1BaseAddress;             ///< SMBUS1 Controller Base Address
+  IN UINT16     CfgSioPmeBaseAddress;             ///< I/O base address for LPC I/O target range
+  IN UINT16     CfgAcpiPm1EvtBlkAddr;             ///< I/O base address of ACPI power management Event Block
+  IN UINT16     CfgAcpiPm1CntBlkAddr;             ///< I/O base address of ACPI power management Control Block
+  IN UINT16     CfgAcpiPmTmrBlkAddr;              ///< I/O base address of ACPI power management Timer Block
+  IN UINT16     CfgCpuControlBlkAddr;             ///< I/O base address of ACPI power management CPU Control Block
+  IN UINT16     CfgAcpiGpe0BlkAddr;               ///< I/O base address of ACPI power management General Purpose Event Block
+  IN UINT16     CfgSmiCmdPortAddr;                ///< I/O base address of ACPI SMI Command Block
+  IN UINT16     CfgAcpiPmaCntBlkAddr;             ///< I/O base address of ACPI power management additional control block
+  IN UINT32     CfgGecShadowRomBase;              ///< 32-bit base address to the GEC shadow ROM
+  IN UINT32     CfgWatchDogTimerBase;             ///< Watchdog Timer base address
+  IN UINT32     CfgSpiRomBaseAddress;             ///< Base address for the SPI ROM controller
+  IN UINT32     CfgHpetBaseAddress;               ///< HPET MMIO base address
+  IN UINT32     CfgAzaliaSsid;                    ///< Subsystem ID of HD Audio controller
+  IN UINT32     CfgSmbusSsid;                     ///< Subsystem ID of SMBUS controller
+  IN UINT32     CfgIdeSsid;                       ///< Subsystem ID of IDE controller
+  IN UINT32     CfgSataAhciSsid;                  ///< Subsystem ID of SATA controller in AHCI mode
+  IN UINT32     CfgSataIdeSsid;                   ///< Subsystem ID of SATA controller in IDE mode
+  IN UINT32     CfgSataRaid5Ssid;                 ///< Subsystem ID of SATA controller in RAID5 mode
+  IN UINT32     CfgSataRaidSsid;                  ///< Subsystem ID of SATA controller in RAID mode
+  IN UINT32     CfgEhciSsid;                      ///< Subsystem ID of EHCI
+  IN UINT32     CfgOhciSsid;                      ///< Subsystem ID of OHCI
+  IN UINT32     CfgLpcSsid;                       ///< Subsystem ID of LPC ISA Bridge
+  IN UINT32     CfgSdSsid;                        ///< Subsystem ID of SecureDigital controller
+  IN UINT32     CfgXhciSsid;                      ///< Subsystem ID of XHCI
+  IN BOOLEAN    CfgFchPort80BehindPcib;           ///< Is port80 cycle going to the PCI bridge
+  IN BOOLEAN    CfgFchEnableAcpiSleepTrap;        ///< ACPI sleep SMI enable/disable
+  IN GPP_LINKMODE CfgFchGppLinkConfig;            ///< GPP link configuration
+  IN BOOLEAN    CfgFchGppPort0Present;            ///< Is FCH GPP port 0 present
+  IN BOOLEAN    CfgFchGppPort1Present;            ///< Is FCH GPP port 1 present
+  IN BOOLEAN    CfgFchGppPort2Present;            ///< Is FCH GPP port 2 present
+  IN BOOLEAN    CfgFchGppPort3Present;            ///< Is FCH GPP port 3 present
+  IN BOOLEAN    CfgFchGppPort0HotPlug;            ///< Is FCH GPP port 0 hotplug capable
+  IN BOOLEAN    CfgFchGppPort1HotPlug;            ///< Is FCH GPP port 1 hotplug capable
+  IN BOOLEAN    CfgFchGppPort2HotPlug;            ///< Is FCH GPP port 2 hotplug capable
+  IN BOOLEAN    CfgFchGppPort3HotPlug;            ///< Is FCH GPP port 3 hotplug capable
+
+  IN UINT8   CfgFchEsataPortBitMap;               ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+  IN UINT8   CfgFchIrPinControl;                  ///< Register bitfield describing Infrared Pin Control:
+                                                  ///<   [0] - IR Enable 0
+                                                  ///<   [1] - IR Enable 1
+                                                  ///<   [2] - IR Tx0
+                                                  ///<   [3] - IR Tx1
+                                                  ///<   [4] - IR Open Drain
+                                                  ///<   [5] - IR Enable LED
+  IN SD_CLOCK_CONTROL CfgFchSdClockControl;       ///< FCH SD Clock Control
+  IN SCI_MAP_CONTROL  *CfgFchSciMapControl;       ///< FCH SCI Mapping Control
+  IN SATA_PHY_CONTROL *CfgFchSataPhyControl;      ///< FCH SATA PHY Control
+  IN GPIO_CONTROL     *CfgFchGpioControl;         ///< FCH GPIO Control
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+  IN  AMD_CODE_HEADER VersionString;              ///< AMD embedded code version string
+
+  //Build Option Area
+  IN BOOLEAN OptionUDimms;                        ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+  IN BOOLEAN OptionRDimms;                        ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+  IN BOOLEAN OptionLrDimms;                      ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+  IN BOOLEAN OptionEcc;                           ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+  IN BOOLEAN OptionBankInterleave;                ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+  IN BOOLEAN OptionDctInterleave;                 ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+  IN BOOLEAN OptionNodeInterleave;                ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+  IN BOOLEAN OptionParallelTraining;              ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+  IN BOOLEAN OptionOnlineSpare;                   ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+  IN BOOLEAN OptionMemRestore;                    ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+  IN BOOLEAN OptionMultisocket;                   ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+  IN BOOLEAN OptionAcpiPstates;                   ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+  IN BOOLEAN OptionPStatesInHpcMode;              ///< @ref BLDCFG_PSTATE_HPC_MODE "BLDCFG_PSTATE_HPC_MODE"
+  IN BOOLEAN OptionSrat;                          ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+  IN BOOLEAN OptionSlit;                          ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+  IN BOOLEAN OptionWhea;                          ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+  IN BOOLEAN OptionDmi;                           ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+  IN BOOLEAN OptionEarlySamples;                  ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+  IN BOOLEAN OptionAddrToCsTranslator;            ///< ADDR_TO_CS_TRANSLATOR
+
+  //Build Configuration Area
+  IN UINT64 CfgPciMmioAddress;                    ///< Pci Mmio Base Address to use for PCI Config accesses.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+  IN UINT32 CfgPciMmioSize;                       ///< Pci Mmio region Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+  IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN UINT32 CfgPlatNumIoApics;                    ///< The number of IO APICS for the platform.
+  IN UINT32 CfgMemInitPstate;                     ///< Memory Init Pstate.
+  IN PLATFORM_C1E_MODES CfgPlatformC1eMode;       ///< Select the C1e Mode that will used.
+  IN UINT32 CfgPlatformC1eOpData;                 ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData1;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData2;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN UINT32 CfgPlatformC1eOpData3;                ///< An IO port or additional C1e setup data, depends on C1e mode.
+  IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+  IN UINT32 CfgPlatformCStateOpData;              ///< An IO port or additional C-State setup data, depends on C-State mode.
+  IN UINT16 CfgPlatformCStateIoBaseAddress;       ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+  IN PLATFORM_CPB_MODES CfgPlatformCpbMode;       ///< Enable or disable core performance boost
+  IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
+  IN UINT32 CfgCoreLevelingMode;                  ///< Apply any downcoring or core count leveling as specified.
+  IN PERFORMANCE_PROFILE CfgPerformanceProfile;   ///< The platform's control flow mode and platform performance settings.
+  IN CPU_HT_DEEMPHASIS_LEVEL *CfgPlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+
+  IN UINT32 CfgAmdPlatformType;                   ///< Designate the platform as a Server, Desktop, or Mobile.
+  IN UINT32 CfgAmdPstateCapValue;                 ///< Amd pstate ceiling enabling deck
+
+  IN MEMORY_BUS_SPEED CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+  IN BOOLEAN CfgMemoryModeUnganged;               ///< Memory Mode Unganged.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+  IN BOOLEAN CfgMemoryQuadRankCapable;            ///< Memory Quad Rank Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+  IN QUANDRANK_TYPE CfgMemoryQuadrankType;        ///< Memory Quadrank Type.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+  IN BOOLEAN CfgMemoryRDimmCapable;               ///< Memory RDIMM Capable.
+  IN BOOLEAN CfgMemoryLRDimmCapable;              ///< Memory LRDIMM Capable.
+  IN BOOLEAN CfgMemoryUDimmCapable;               ///< Memory UDIMM Capable.
+  IN BOOLEAN CfgMemorySODimmCapable;              ///< Memory SODimm Capable.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+  IN BOOLEAN CfgLimitMemoryToBelow1Tb;            ///< Limit memory address space to below 1TB
+  IN BOOLEAN CfgMemoryEnableBankInterleaving;     ///< Memory Enable Bank Interleaving.
+  IN BOOLEAN CfgMemoryEnableNodeInterleaving;     ///< Memory Enable Node Interleaving.
+  IN BOOLEAN CfgMemoryChannelInterleaving;        ///< Memory Channel Interleaving.
+  IN BOOLEAN CfgMemoryPowerDown;                  ///< Memory Power Down.
+  IN POWER_DOWN_MODE CfgPowerDownMode;            ///< Power Down Mode.
+  IN BOOLEAN CfgOnlineSpare;                      ///< Online Spare.
+  IN BOOLEAN CfgMemoryParityEnable;               ///< Memory Parity Enable.
+  IN BOOLEAN CfgBankSwizzle;                      ///< Bank Swizzle.
+  IN USER_MEMORY_TIMING_MODE CfgTimingModeSelect; ///< Timing Mode Select.
+  IN MEMORY_BUS_SPEED CfgMemoryClockSelect;       ///< Memory Clock Select.
+  IN BOOLEAN CfgDqsTrainingControl;               ///< Dqs Training Control.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+  IN BOOLEAN CfgIgnoreSpdChecksum;                ///< Ignore Spd Checksum.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+  IN BOOLEAN CfgUseBurstMode;                     ///< Use Burst Mode.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+  IN BOOLEAN CfgMemoryAllClocksOn;                ///< Memory All Clocks On.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+  IN BOOLEAN CfgEnableEccFeature;                 ///< Enable ECC Feature.
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+  IN UINT16  CfgEccSymbolSize;                    ///< ECC Symbol Size.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+  IN UINT64  CfgHeapDramAddress;                  ///< Heap contents will be temporarily stored in this address during the transition.
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+  IN BOOLEAN CfgNodeMem1GBAlign;                  ///< Node Mem 1GB boundary Alignment
+  IN BOOLEAN CfgS3LateRestore;                    ///< S3 Late Restore
+  IN BOOLEAN CfgAcpiPstateIndependent;            ///< PSD method dependent/Independent
+  IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList;     ///< The AP's MTRR settings before final halt
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+  IN UMA_MODE CfgUmaMode;                         ///< Uma Mode
+  IN UINT32 CfgUmaSize;                           ///< Uma Size [31:0]=Addr[47:16]
+  IN BOOLEAN CfgUmaAbove4G;                       ///< Uma Above 4G Support
+  IN UMA_ALIGNMENT CfgUmaAlignment;               ///< Uma alignment
+  IN BOOLEAN CfgProcessorScopeInSb;               ///< ACPI Processor Object in \\_SB scope
+  IN CHAR8   CfgProcessorScopeName0;              ///< OEM specific 1st character of processor scope name.
+  IN CHAR8   CfgProcessorScopeName1;              ///< OEM specific 2nd character of processor scope name.
+  IN UINT8   CfgGnbHdAudio;                       ///< GNB HD Audio
+  IN UINT8   CfgAbmSupport;                       ///< Abm Support
+  IN UINT8   CfgDynamicRefreshRate;               ///< DRR Dynamic Refresh Rate
+  IN UINT16  CfgLcdBackLightControl;              ///< LCD Backlight Control
+  IN UINT8   CfgGnb3dStereoPinIndex;                ///< 3D Stereo Pin ID.
+  IN UINT32  CfgTempPcieMmioBaseAddress;          ///< Temp pcie MMIO base Address
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+  IN UINT32  CfgGnbIGPUSSID;                      ///< Gnb internal GPU SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbHDAudioSSID;                   ///< Gnb HD Audio SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+  IN UINT32  CfgGnbPcieSSID;                      ///< Gnb PCIe SSID
+                                                  ///< Build-time customizable only - @BldCfgItem{BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+  IN UINT16  CfgLvdsSpreadSpectrum;               ///< Lvds Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+  IN UINT16  CfgLvdsSpreadSpectrumRate;           ///< Lvds Spread Spectrum Rate
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+  IN FCH_PLATFORM_POLICY  *FchBldCfg;             ///< FCH platform build configuration policy
+
+  IN BOOLEAN    CfgIommuSupport;                  ///< IOMMU support
+  IN UINT8      CfgLvdsPowerOnSeqDigonToDe;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToVaryBl;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqDeToDigon;       ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToDe;      ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqOnToOffDelay;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqVaryBlToBlon;    ///< Panel initialization timing
+  IN UINT8      CfgLvdsPowerOnSeqBlonToVaryBl;    ///< Panel initialization timing
+  IN UINT16     CfgLvdsMaxPixelClockFreq;         ///< The maximum pixel clock frequency supported
+  IN UINT32     CfgLcdBitDepthControlValue;       ///< The LCD bit depth control settings
+  IN UINT8      CfgLvds24bbpPanelMode;            ///< The LVDS 24 BBP mode
+  IN LVDS_MISC_CONTROL CfgLvdsMiscControl;        ///< THe LVDS Misc control
+  IN UINT16     CfgPcieRefClkSpreadSpectrum;      ///< PCIe Reference Clock Spread Spectrum
+                                                  ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+  IN BOOLEAN    CfgExternalVrefCtlFeature;        ///< External Vref control
+  IN FORCE_TRAIN_MODE   CfgForceTrainMode;        ///< Force Train Mode
+  IN BOOLEAN    CfgGnbRemoteDisplaySupport;       ///< Wireless Display Support
+  IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+  IN BOOLEAN Reserved;                            ///< reserved...
+} BUILD_OPT_CFG;
+
+///  A structure containing platform specific operational characteristics. This
+///  structure is initially populated by the initializer with a copy of the same
+///  structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+  IN PERFORMANCE_PROFILE PlatformProfile;             ///< Several configuration settings for the processor.
+  IN CPU_HT_DEEMPHASIS_LEVEL *PlatformDeemphasisList; ///< Deemphasis levels for the platform's HT links.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_DEEMPHASIS_LIST}.
+                                                      ///< @n @e Examples: See @ref DeemphasisExamples "Deemphasis List Examples".
+  IN UINT8               CoreLevelingMode;            ///< Indicates how to balance the number of cores per processor.
+                                                      ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+  IN PLATFORM_C1E_MODES  C1eMode;                     ///< Specifies the method of C1e enablement - Disabled, HW, or message based.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_MODE}
+  IN UINT32              C1ePlatformData;             ///< If C1eMode is HW, specifies the P_LVL3 I/O port of the platform.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA}
+  IN UINT32              C1ePlatformData1;            ///< If C1eMode is SW, specifies the address of chipset's SMI command port.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA1}
+  IN UINT32              C1ePlatformData2;            ///< If C1eMode is SW, specifies the unique number used by the SMI handler to identify SMI source.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA2}
+  IN UINT32              C1ePlatformData3;            ///< If C1eMode is Auto, specifies the P_LVL3 I/O port of the platform for HW C1e
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_C1E_OPDATA3}
+  IN PLATFORM_CSTATE_MODES  CStateMode;               ///< Specifies the method of C-State enablement - Disabled, or C6.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+  IN UINT32              CStatePlatformData;          ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+                                                      ///< If CStateMode is CStateModeC6, this item is reserved
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+  IN UINT16              CStateIoBaseAddress;         ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+                                                      ///< can be used to allow the CPU to enter Cstates.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+  IN PLATFORM_CPB_MODES  CpbMode;                     ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+  IN BOOLEAN             UserOptionDmi;               ///< When set to TRUE, the DMI data table is generated.
+  IN BOOLEAN             UserOptionPState;            ///< When set to TRUE, the PState data tables are generated.
+  IN BOOLEAN             UserOptionSrat;              ///< When set to TRUE, the SRAT data table is generated.
+  IN BOOLEAN             UserOptionSlit;              ///< When set to TRUE, the SLIT data table is generated.
+  IN BOOLEAN             UserOptionWhea;              ///< When set to TRUE, the WHEA data table is generated.
+  IN PLATFORM_LOW_POWER_PSTATE_MODES  LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+  IN UINT32              PowerCeiling;                ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+  IN BOOLEAN             ForcePstateIndependent;      ///< P-State _PSD independence or dependence.
+                                                      ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+  IN BOOLEAN             PStatesInHpcMode;            ///< @BldCfgItem{BLDCFG_PSTATE_HPC_MODE}
+  IN UINT32              NumberOfIoApics;             ///< Number of I/O APICs in the system
+                                                      ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+  IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+  IN BOOLEAN             ProcessorScopeInSb;          ///< ACPI Processor Object in \\_SB scope
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+  IN CHAR8               ProcessorScopeName0;         ///< OEM specific 1st character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+  IN CHAR8               ProcessorScopeName1;         ///< OEM specific 2nd character of processor scope name.
+                                                      ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+  IN UINT8               GnbHdAudio;                  ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+                                                      ///< essentially it enables function 1 of graphics device.
+                                                      ///< @li 0 = HD Audio disable
+                                                      ///< @li 1 = HD Audio enable
+                                                      ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+  IN UINT8               AbmSupport;                  ///< Automatic adjust LVDS/eDP Back light level support.It is
+                                                      ///< characteristic specific to display panel which used by platform design.
+                                                      ///< @li 0 = ABM support disabled
+                                                      ///< @li 1 = ABM support enabled
+                                                      ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+  IN UINT8               DynamicRefreshRate;          ///< Adjust refresh rate on LVDS/eDP.
+                                                      ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+  IN UINT16              LcdBackLightControl;         ///< The PWM frequency to LCD backlight control.
+                                                      ///< If equal to 0 backlight not controlled by iGPU
+                                                      ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+
+/*  Interface Parameter Structures  */
+/// DMI Type4 - Processor ID
+typedef struct {
+  OUT UINT32                    ProcIdLsd;              ///< Lower half of 64b ID
+  OUT UINT32                    ProcIdMsd;              ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+  OUT UINT8                     T4ProcType;             ///< CPU Type
+  OUT UINT8                     T4ProcFamily;           ///< Family 1
+  OUT TYPE4_PROC_ID             T4ProcId;               ///< Id
+  OUT UINT8                     T4Voltage;              ///< Voltage
+  OUT UINT16                    T4ExternalClock;        ///< External clock
+  OUT UINT16                    T4MaxSpeed;             ///< Max speed
+  OUT UINT16                    T4CurrentSpeed;         ///< Current speed
+  OUT UINT8                     T4Status;               ///< Status
+  OUT UINT8                     T4ProcUpgrade;          ///< Up grade
+  OUT UINT8                     T4CoreCount;            ///< Core count
+  OUT UINT8                     T4CoreEnabled;          ///< Core Enable
+  OUT UINT8                     T4ThreadCount;          ///< Thread count
+  OUT UINT16                    T4ProcCharacteristics;  ///< Characteristics
+  OUT UINT16                    T4ProcFamily2;          ///< Family 2
+  OUT CHAR8                     T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+  OUT UINT16                    T7CacheCfg;             ///< Cache cfg
+  OUT UINT16                    T7MaxCacheSize;         ///< Max size
+  OUT UINT16                    T7InstallSize;          ///< Install size
+  OUT UINT16                    T7SupportedSramType;    ///< Supported Sram Type
+  OUT UINT16                    T7CurrentSramType;      ///< Current type
+  OUT UINT8                     T7CacheSpeed;           ///< Speed
+  OUT UINT8                     T7ErrorCorrectionType;  ///< ECC type
+  OUT UINT8                     T7SystemCacheType;      ///< Cache type
+  OUT UINT8                     T7Associativity;        ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+  OtherLocation = 0x01,                                 ///< Assign 01 to Other
+  UnknownLocation,                                      ///< Assign 02 to Unknown
+  SystemboardOrMotherboard,                             ///< Assign 03 to systemboard or motherboard
+  IsaAddonCard,                                         ///< Assign 04 to ISA add-on card
+  EisaAddonCard,                                        ///< Assign 05 to EISA add-on card
+  PciAddonCard,                                         ///< Assign 06 to PCI add-on card
+  McaAddonCard,                                         ///< Assign 07 to MCA add-on card
+  PcmciaAddonCard,                                      ///< Assign 08 to PCMCIA add-on card
+  ProprietaryAddonCard,                                 ///< Assign 09 to proprietary add-on card
+  NuBus,                                                ///< Assign 0A to NuBus
+  Pc98C20AddonCard,                                     ///< Assign 0A0 to PC-98/C20 add-on card
+  Pc98C24AddonCard,                                     ///< Assign 0A1 to PC-98/C24 add-on card
+  Pc98EAddoncard,                                       ///< Assign 0A2 to PC-98/E add-on card
+  Pc98LocalBusAddonCard                                 ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+  OtherUse = 0x01,                                      ///< Assign 01 to Other
+  UnknownUse,                                           ///< Assign 02 to Unknown
+  SystemMemory,                                         ///< Assign 03 to system memory
+  VideoMemory,                                          ///< Assign 04 to video memory
+  FlashMemory,                                          ///< Assign 05 to flash memory
+  NonvolatileRam,                                       ///< Assign 06 to non-volatile RAM
+  CacheMemory                                           ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+  Dmi16OtherErrCorrection = 0x01,                       ///< Assign 01 to Other
+  Dmi16UnknownErrCorrection,                            ///< Assign 02 to Unknown
+  Dmi16NoneErrCorrection,                               ///< Assign 03 to None
+  Dmi16Parity,                                          ///< Assign 04 to parity
+  Dmi16SingleBitEcc,                                    ///< Assign 05 to Single-bit ECC
+  Dmi16MultiBitEcc,                                     ///< Assign 06 to Multi-bit ECC
+  Dmi16Crc                                              ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+  OUT DMI_T16_LOCATION          Location;               ///< The physical location of the Memory Array,
+                                                        ///< whether on the system board or an add-in board.
+  OUT DMI_T16_USE               Use;                    ///< Identifies the function for which the array
+                                                        ///< is used.
+  OUT DMI_T16_ERROR_CORRECTION  MemoryErrorCorrection;  ///< The primary hardware error correction or
+                                                        ///< detection method supported by this memory array.
+  OUT UINT32                    MaximumCapacity;        ///< The maximum memory capacity, in kilobytes,
+                                                        ///< for the array.
+  OUT UINT16                    NumberOfMemoryDevices;  ///< The number of slots or sockets available
+                                                        ///< for memory devices in this array.
+  OUT UINT64                    ExtMaxCapacity;         ///< The maximum memory capacity, in bytes,
+                                                        ///< for this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+  OtherFormFactor = 0x01,                               ///< Assign 01 to Other
+  UnknowFormFactor,                                     ///< Assign 02 to Unknown
+  SimmFormFactor,                                       ///< Assign 03 to SIMM
+  SipFormFactor,                                        ///< Assign 04 to SIP
+  ChipFormFactor,                                       ///< Assign 05 to Chip
+  DipFormFactor,                                        ///< Assign 06 to DIP
+  ZipFormFactor,                                        ///< Assign 07 to ZIP
+  ProprietaryCardFormFactor,                            ///< Assign 08 to Proprietary Card
+  DimmFormFactorFormFactor,                             ///< Assign 09 to DIMM
+  TsopFormFactor,                                       ///< Assign 10 to TSOP
+  RowOfChipsFormFactor,                                 ///< Assign 11 to Row of chips
+  RimmFormFactor,                                       ///< Assign 12 to RIMM
+  SodimmFormFactor,                                     ///< Assign 13 to SODIMM
+  SrimmFormFactor,                                      ///< Assign 14 to SRIMM
+  FbDimmFormFactor                                      ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+  OtherMemType = 0x01,                                  ///< Assign 01 to Other
+  UnknownMemType,                                       ///< Assign 02 to Unknown
+  DramMemType,                                          ///< Assign 03 to DRAM
+  EdramMemType,                                         ///< Assign 04 to EDRAM
+  VramMemType,                                          ///< Assign 05 to VRAM
+  SramMemType,                                          ///< Assign 06 to SRAM
+  RamMemType,                                           ///< Assign 07 to RAM
+  RomMemType,                                           ///< Assign 08 to ROM
+  FlashMemType,                                         ///< Assign 09 to Flash
+  EepromMemType,                                        ///< Assign 10 to EEPROM
+  FepromMemType,                                        ///< Assign 11 to FEPROM
+  EpromMemType,                                         ///< Assign 12 to EPROM
+  CdramMemType,                                         ///< Assign 13 to CDRAM
+  ThreeDramMemType,                                     ///< Assign 14 to 3DRAM
+  SdramMemType,                                         ///< Assign 15 to SDRAM
+  SgramMemType,                                         ///< Assign 16 to SGRAM
+  RdramMemType,                                         ///< Assign 17 to RDRAM
+  DdrMemType,                                           ///< Assign 18 to DDR
+  Ddr2MemType,                                          ///< Assign 19 to DDR2
+  Ddr2FbdimmMemType,                                    ///< Assign 20 to DDR2 FB-DIMM
+  Ddr3MemType = 0x18,                                   ///< Assign 24 to DDR3
+  Fbd2MemType                                           ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+  OUT UINT16                    Reserved1:1;            ///< Reserved
+  OUT UINT16                    Other:1;                ///< Other
+  OUT UINT16                    Unknown:1;              ///< Unknown
+  OUT UINT16                    FastPaged:1;            ///< Fast-Paged
+  OUT UINT16                    StaticColumn:1;         ///< Static column
+  OUT UINT16                    PseudoStatic:1;         ///< Pseudo-static
+  OUT UINT16                    Rambus:1;               ///< RAMBUS
+  OUT UINT16                    Synchronous:1;          ///< Synchronous
+  OUT UINT16                    Cmos:1;                 ///< CMOS
+  OUT UINT16                    Edo:1;                  ///< EDO
+  OUT UINT16                    WindowDram:1;           ///< Window DRAM
+  OUT UINT16                    CacheDram:1;            ///< Cache Dram
+  OUT UINT16                    NonVolatile:1;          ///< Non-volatile
+  OUT UINT16                    Reserved2:3;            ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceSet;              ///< Identifies when the Memory Device is one of a set of
+                                                        ///< Memory Devices that must be populated with all devices of
+                                                        ///< the same type and size, and the set to which this device belongs.
+  OUT CHAR8                     DeviceLocator[8];       ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT CHAR8                     BankLocator[10];        ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT DMI_T17_MEMORY_TYPE       MemoryType;             ///< The type of memory used in this device.
+  OUT DMI_T17_TYPE_DETAIL       TypeDetail;             ///< Additional detail on the memory device type
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT CHAR8                     SerialNumber[9];        ///< Serial Number.
+  OUT CHAR8                     PartNumber[19];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 and 20 - for memory use
+typedef struct {
+  OUT UINT16                    TotalWidth;             ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+  OUT UINT16                    DataWidth;              ///< Data Width, in bits, of this memory device.
+  OUT UINT16                    MemorySize;             ///< The size of the memory device.
+  OUT DMI_T17_FORM_FACTOR       FormFactor;             ///< The implementation form factor for this memory device.
+  OUT UINT8                     DeviceLocator;          ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+  OUT UINT8                     BankLocator;            ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+  OUT UINT16                    Speed;                  ///< Identifies the speed of the device, in megahertz (MHz).
+  OUT UINT64                    ManufacturerIdCode;     ///< Manufacturer ID code.
+  OUT UINT8                     SerialNumber[4];        ///< Serial Number.
+  OUT UINT8                     PartNumber[18];         ///< Part Number.
+  OUT UINT8                     Attributes;             ///< Bits 7-4: Reserved, Bits 3-0: rank.
+  OUT UINT32                    ExtSize;                ///< Extended Size.
+  OUT UINT8                     Socket:3;               ///< Socket ID
+  OUT UINT8                     Channel:2;              ///< Channel ID
+  OUT UINT8                     Dimm:2;                 ///< DIMM ID
+  OUT UINT8                     DimmPresent:1;          ///< Dimm Present
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    ConfigSpeed;            ///< Configured memory clock speed
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes,
+                                                        ///< of a range of memory mapped to the
+                                                        ///< specified physical memory array.
+  OUT UINT32                    EndingAddr;             ///< The physical ending address of the
+                                                        ///< last kilobyte of a range of addresses
+                                                        ///< mapped to the specified physical memory array.
+  OUT UINT16                    MemoryArrayHandle;      ///< The handle, or instance number, associated
+                                                        ///< with the physical memory array to which this
+                                                        ///< address range is mapped.
+  OUT UINT8                     PartitionWidth;         ///< Identifies the number of memory devices that
+                                                        ///< form a single row of memory for the address
+                                                        ///< partition defined by this structure.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+  OUT UINT32                    StartingAddr;           ///< The physical address, in kilobytes, of a range
+                                                        ///< of memory mapped to the referenced Memory Device.
+  OUT UINT32                    EndingAddr;             ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryDeviceHandle;     ///< The handle, or instance number, associated with
+                                                        ///< the Memory Device structure to which this address
+                                                        ///< range is mapped.
+  OUT UINT16                    MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+                                                        ///< with the Memory Array Mapped Address structure to
+                                                        ///< which this device address range is mapped.
+  OUT UINT8                     PartitionRowPosition;   ///< Identifies the position of the referenced Memory
+                                                        ///< Device in a row of the address partition.
+  OUT UINT8                     InterleavePosition;     ///< The position of the referenced Memory Device in
+                                                        ///< an interleave.
+  OUT UINT8                     InterleavedDataDepth;   ///< The maximum number of consecutive rows from the
+                                                        ///< referenced Memory Device that are accessed in a
+                                                        ///< single interleaved transfer.
+  OUT UINT64                    ExtStartingAddr;        ///< The physical address, in bytes, of a range of
+                                                        ///< memory mapped to the referenced Memory Device.
+  OUT UINT64                    ExtEndingAddr;          ///< The physical ending address, in bytes, of the last of
+                                                        ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+  OUT TYPE4_DMI_INFO            T4[MAX_SOCKETS_SUPPORTED];    ///< Type 4 struc
+  OUT TYPE7_DMI_INFO            T7L1[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 1
+  OUT TYPE7_DMI_INFO            T7L2[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 2
+  OUT TYPE7_DMI_INFO            T7L3[MAX_SOCKETS_SUPPORTED];  ///< Type 7 struc 3
+  OUT TYPE16_DMI_INFO           T16;                          ///< Type 16 struc
+  OUT TYPE17_DMI_INFO           T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+  OUT TYPE19_DMI_INFO           T19;                          ///< Type 19 struc
+  OUT TYPE20_DMI_INFO           T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call:  AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS    3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+  IN OUT   UINT32               ExeCacheStartAddr;      ///< Start address
+  IN OUT   UINT32               ExeCacheSize;           ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call:  AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;              ///< Standard configuration header
+     OUT   UINT32               AvailableExeCacheSize;  ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+  IN OUT   AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+  );
+
+/// Selection type for core leveling
+typedef enum {
+  CORE_LEVEL_LOWEST,            ///< Level to lowest common denominator
+  CORE_LEVEL_TWO,               ///< Level to 2 cores
+  CORE_LEVEL_POWER_OF_TWO,      ///< Level to 1,2,4 or 8
+  CORE_LEVEL_NONE,              ///< Do no leveling
+  CORE_LEVEL_COMPUTE_UNIT,      ///< Level cores to one core per compute unit
+  CORE_LEVEL_ONE,               ///< Level to 1 core
+  CORE_LEVEL_THREE,             ///< Level to 3 cores
+  CORE_LEVEL_FOUR,              ///< Level to 4 cores
+  CORE_LEVEL_FIVE,              ///< Level to 5 cores
+  CORE_LEVEL_SIX,               ///< Level to 6 cores
+  CORE_LEVEL_SEVEN,             ///< Level to 7 cores
+  CORE_LEVEL_EIGHT,             ///< Level to 8 cores
+  CORE_LEVEL_NINE,              ///< Level to 9 cores
+  CORE_LEVEL_TEN,               ///< Level to 10 cores
+  CORE_LEVEL_ELEVEN,            ///< Level to 11 cores
+  CORE_LEVEL_TWELVE,            ///< Level to 12 cores
+  CORE_LEVEL_THIRTEEN,          ///< Level to 13 cores
+  CORE_LEVEL_FOURTEEN,          ///< Level to 14 cores
+  CORE_LEVEL_FIFTEEN,           ///< Level to 15 cores
+  CoreLevelModeMax              ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ *  AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call:  AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+  IN OUT   AMD_INTERFACE_PARAMS *InterfaceParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+  IN       AMD_CONFIG_PARAMS         StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION    CacheRegion[3];   ///< The cached memory region
+  IN       AMD_HT_RESET_INTERFACE    HtConfig;         ///< The interface for Ht Recovery
+  IN       FCH_RESET_INTERFACE       FchInterface;     ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+  IN OUT   AMD_RESET_PARAMS     *ResetParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       EXECUTION_CACHE_REGION CacheRegion[3];   ///< Execution Map Interface
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_HT_INTERFACE       HtConfig;         ///< HyperTransport Interface
+  IN       GNB_CONFIGURATION      GnbConfig;        ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+  IN OUT   AMD_EARLY_PARAMS     *EarlyParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       MEM_PARAMETER_STRUCT   MemConfig;        ///< Memory post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+  IN OUT   AMD_POST_PARAMS      *PostParams         ///< Amd Cpu init param
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;            ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;       ///< platform operational characteristics.
+  IN       GNB_ENV_CONFIGURATION  GnbEnvConfiguration;  ///< platform operational characteristics.
+  IN       FCH_INTERFACE          FchInterface;         ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+  IN OUT   AMD_ENV_PARAMS       *EnvParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;        ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+  IN OUT   AMD_MID_PARAMS       *MidParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;              ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;         ///< platform operational characteristics.
+  IN       IOMMU_EXCLUSION_RANGE_DESCRIPTOR  *IvrsExclusionRangeList;   ///< Pointer to array of exclusion ranges
+     OUT   DMI_INFO               *DmiTable;              ///< DMI Interface
+     OUT   VOID                   *AcpiPState;            ///< Acpi Pstate SSDT Table
+     OUT   VOID                   *AcpiSrat;              ///< SRAT Table
+     OUT   VOID                   *AcpiSlit;              ///< SLIT Table
+     OUT   VOID                   *AcpiWheaMce;           ///< WHEA MCE Table
+     OUT   VOID                   *AcpiWheaCmc;           ///< WHEA CMC Table
+     OUT   VOID                   *AcpiAlib;              ///< ACPI SSDT table with ALIB implementation
+     OUT   VOID                   *AcpiIvrs;              ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+  IN OUT   AMD_LATE_PARAMS      *LateParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;             ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS        StdHeader;            ///< Standard configuration header
+  IN       MEM_PARAMETER_STRUCT     MemConfig;            ///< Memory post param
+  IN       EXECUTION_CACHE_REGION   CacheRegion[3];       ///< The cached memory region. And the max cache region is 3
+  IN       AMD_CPU_RECOVERY_PARAMS  CpuRecoveryParams;    ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+  IN OUT   AMD_RECOVERY_PARAMS    *RecoveryParams
+  );
+
+/**********************************************************************
+ * Interface call:  AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS      StdHeader;      ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+  IN       AMD_S3_PARAMS          S3DataBlock;    ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+  IN       AMD_RESUME_PARAMS    *ResumeParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+  IN       AMD_S3_PARAMS          S3DataBlock;      ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+  IN OUT   AMD_S3LATE_PARAMS    *S3LateParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS    StdHeader;          ///< Standard configuration header
+  IN       PLATFORM_CONFIGURATION PlatformConfig;   ///< platform operational characteristics.
+     OUT   AMD_S3_PARAMS          S3DataBlock;      ///< Standard header
+  IN       FCH_INTERFACE          FchInterface;     ///< FCH configuration
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+  IN OUT   AMD_S3SAVE_PARAMS    *AmdS3SaveParams
+  );
+
+
+/**********************************************************************
+ * Interface call:  AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call:  AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Core's Socket.
+  IN       UINT8             Core;             ///< The Core id.
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  ApicAddress is valid.
+     OUT   UINT8             ApicAddress;      ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+  IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call:  AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;        ///< Standard configuration header
+  IN       UINT8             Socket;           ///< The Processor's socket
+  IN       UINT8             Module;           ///< The Module in that Processor
+     OUT   BOOLEAN           IsPresent;        ///< The Core is present, and  PciAddress is valid.
+     OUT   PCI_ADDR          PciAddress;       ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+  IN OUT   AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT8             Socket;            ///< The current Core's Socket
+     OUT   UINT8             Module;            ///< The current Core's Processor Module
+     OUT   UINT8             Core;              ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+  IN OUT  AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call:  AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS StdHeader;         ///< Standard configuration header
+     OUT   UINT32            EventClass;        ///< The severity of this event, matches AGESA_STATUS.
+     OUT   UINT32            EventInfo;         ///< The unique event identifier, zero means "no event".
+     OUT   UINT32            DataParam1;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam2;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam3;        ///< Data specific to the Event.
+     OUT   UINT32            DataParam4;        ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+  IN       EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call:  AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+  IN OUT   AMD_CONFIG_PARAMS StdHeader;            ///< Standard configuration header
+  IN       UINT64            MemoryAddress;        ///< System Address that needs to be translated to dimm identification.
+  OUT      UINT8             SocketId;             ///< The socket on which the targeted address locates.
+  OUT      UINT8             MemChannelId;         ///< The channel on which the targeted address locates.
+  OUT      UINT8             DimmId;               ///< The dimm on which the targeted address locates.
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+  IN OUT   AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+  IN       AP_EXE_PARAMS  *AmdApExeParams
+  );
+
+
+#define AGESA_IDS_DFT_VAL   0xFFFF                  ///<  Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END    0xFFFF                  ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+  AGESA_IDS_EXT_ID_START                   = 0x0000,///< 0x0000                                                             specify the start of external NV id
+
+  AGESA_IDS_NV_UCODE,                               ///< 0x0001                                                            Enable or disable microcode patching
+
+  AGESA_IDS_NV_TARGET_PSTATE,                       ///< 0x0002                                                        Set the P-state required to be activated
+  AGESA_IDS_NV_POSTPSTATE,                          ///< 0x0003                                           Set the P-state required to be activated through POST
+
+  AGESA_IDS_NV_BANK_INTERLEAVE,                     ///< 0x0004                                                               Enable or disable Bank Interleave
+  AGESA_IDS_NV_CHANNEL_INTERLEAVE,                  ///< 0x0005                                                            Enable or disable Channel Interleave
+  AGESA_IDS_NV_NODE_INTERLEAVE,                     ///< 0x0006                                                               Enable or disable Node Interleave
+  AGESA_IDS_NV_MEMHOLE,                             ///< 0x0007                                                                  Enables or disable memory hole
+
+  AGESA_IDS_NV_SCRUB_REDIRECTION,                   ///< 0x0008                                           Enable or disable a write to dram with corrected data
+  AGESA_IDS_NV_DRAM_SCRUB,                          ///< 0x0009                                                   Set the rate of background scrubbing for DRAM
+  AGESA_IDS_NV_DCACHE_SCRUB,                        ///< 0x000A                                            Set the rate of background scrubbing for the DCache.
+  AGESA_IDS_NV_L2_SCRUB,                            ///< 0x000B                                           Set the rate of background scrubbing for the L2 cache
+  AGESA_IDS_NV_L3_SCRUB,                            ///< 0x000C                                           Set the rate of background scrubbing for the L3 cache
+  AGESA_IDS_NV_ICACHE_SCRUB,                        ///< 0x000D                                             Set the rate of background scrubbing for the Icache
+  AGESA_IDS_NV_SYNC_ON_ECC_ERROR,                   ///< 0x000E                                    Enable or disable the sync flood on un-correctable ECC error
+  AGESA_IDS_NV_ECC_SYMBOL_SIZE,                     ///< 0x000F                                                                             Set ECC symbol size
+
+  AGESA_IDS_NV_ALL_MEMCLKS,                         ///< 0x0010                                                      Enable or disable all memory clocks enable
+  AGESA_IDS_NV_DCT_GANGING_MODE,                    ///< 0x0011                                                                             Set the Ganged mode
+  AGESA_IDS_NV_DRAM_BURST_LENGTH32,                 ///< 0x0012                                                                    Set the DRAM Burst Length 32
+  AGESA_IDS_NV_MEMORY_POWER_DOWN,                   ///< 0x0013                                                        Enable or disable Memory power down mode
+  AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE,              ///< 0x0014                                                                  Set the Memory power down mode
+  AGESA_IDS_NV_DLL_SHUT_DOWN,                       ///< 0x0015                                                                   Enable or disable DLLShutdown
+  AGESA_IDS_NV_ONLINE_SPARE,                        ///< 0x0016      Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+  AGESA_IDS_NV_HT_ASSIST,                           ///< 0x0017                                                                     Enable or Disable HT Assist
+  AGESA_IDS_NV_ATMMODE,                             ///< 0x0018                                                                      Enable or Disable ATM mode
+
+  AGESA_IDS_NV_HDTOUT,                              ///< 0x0019                                                                Enable or disable HDTOUT feature
+
+  AGESA_IDS_NV_HTLINKSOCKET,                        ///< 0x001A                                                                                  HT Link Socket
+  AGESA_IDS_NV_HTLINKPORT,                          ///< 0x001B                                                                                    HT Link Port
+  AGESA_IDS_NV_HTLINKFREQ,                          ///< 0x001C                                                                               HT Link Frequency
+  AGESA_IDS_NV_HTLINKWIDTHIN,                       ///< 0x001D                                                                                HT Link In Width
+  AGESA_IDS_NV_HTLINKWIDTHOUT,                      ///< 0x001E                                                                               HT Link Out Width
+
+  AGESA_IDS_NV_GNBHDAUDIOEN,                        ///< 0x001F                                                                  Enable or disable GNB HD Audio
+
+  AGESA_IDS_NV_CPB_EN,                              ///< 0x0020                                                                          Core Performance Boost
+
+  AGESA_IDS_NV_HTC_EN,                              ///< 0x0021                                                                                      HTC Enable
+  AGESA_IDS_NV_HTC_OVERRIDE,                        ///< 0x0022                                                                                    HTC Override
+  AGESA_IDS_NV_HTC_PSTATE_LIMIT,                    ///< 0x0023                                                                        HTC P-state limit select
+  AGESA_IDS_NV_HTC_TEMP_HYS,                        ///< 0x0024                                                                      HTC Temperature Hysteresis
+  AGESA_IDS_NV_HTC_ACT_TEMP,                        ///< 0x0025                                                                             HTC Activation Temp
+
+  AGESA_IDS_NV_POWER_POLICY,                        ///< 0x0026                                                                    Select Platform Power Policy
+  AGESA_IDS_EXT_ID_END,                             ///< 0x0027                                                               specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/agesa/f15/AMD.h b/src/vendorcode/amd/agesa/f15/AMD.h
new file mode 100644
index 0000000..d1092c6
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/AMD.h
@@ -0,0 +1,480 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define AGESA_REVISION  "Arch2008"
+#define AGESA_ID        "AGESA"
+
+#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY          0xFFFFFFFF
+#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event.  Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+  AGESA_SUCCESS = 0,             ///< The service completed normally. Info may be logged.
+  AGESA_UNSUPPORTED,             ///< The dispatcher or create struct had an unimplemented function requested.
+                                 ///<  Not logged.
+  AGESA_BOUNDS_CHK,              ///< A dynamic parameter was out of range and the service was not provided.
+                                 ///< Example, memory address not installed, heap buffer handle not found.
+                                 ///< Not Logged.
+  // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+  AGESA_ALERT,                   ///< An observed condition, but no loss of function.
+                                 ///<  See log.  Example, HT CRC.
+  AGESA_WARNING,                 ///< Possible or minor loss of function.  See Log.
+  AGESA_ERROR,                   ///< Significant loss of function, boot may be possible.  See Log.
+  AGESA_CRITICAL,                ///< Continue boot only to notify user.  See Log.
+  AGESA_FATAL,                   ///< Halt booting.  See Log, however Fatal errors pertaining to heap problems
+                                 ///< may not be able to reliably produce log events.
+  AgesaStatusMax                 ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in]        Function      The specific callout function being invoked.
+ * @param[in]        FcnData       Function specific data item.
+ * @param[in,out]    ConfigPtr     Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+  IN       UINT32  Function,
+  IN       UINTN   FcnData,
+  IN OUT   VOID    *ConfigPtr
+  );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+  PreMemHeap = 0,                                           ///< Create heap in cache.
+  PostMemDram,                                              ///< Create heap in memory.
+  ByHost                                                    ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
+  AccessWidth16,                                            ///< Access width is 16 bits.
+  AccessWidth32,                                            ///< Access width is 32 bits.
+  AccessWidth64,                                            ///< Access width is 64 bits.
+
+  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
+  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
+  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
+  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+  // AGESA BASIC FUNCTIONS
+  AMD_INIT_RECOVERY = 0x00020000,                           ///< AmdInitRecovery entry point handle
+  AMD_CREATE_STRUCT,                                        ///< AmdCreateStruct handle
+  AMD_INIT_EARLY,                                           ///< AmdInitEarly entry point handle
+  AMD_INIT_ENV,                                             ///< AmdInitEnv entry point handle
+  AMD_INIT_LATE,                                            ///< AmdInitLate entry point handle
+  AMD_INIT_MID,                                             ///< AmdInitMid entry point handle
+  AMD_INIT_POST,                                            ///< AmdInitPost entry point handle
+  AMD_INIT_RESET,                                           ///< AmdInitReset entry point handle
+  AMD_INIT_RESUME,                                          ///< AmdInitResume entry point handle
+  AMD_RELEASE_STRUCT,                                       ///< AmdReleaseStruct handle
+  AMD_S3LATE_RESTORE,                                       ///< AmdS3LateRestore entry point handle
+  AMD_S3_SAVE,                                              ///< AmdS3Save entry point handle
+  AMD_GET_APIC_ID,                                          ///< AmdGetApicId entry point handle
+  AMD_GET_PCI_ADDRESS,                                      ///< AmdGetPciAddress entry point handle
+  AMD_IDENTIFY_CORE,                                        ///< AmdIdentifyCore general service handle
+  AMD_READ_EVENT_LOG,                                       ///< AmdReadEventLog general service handle
+  AMD_GET_EXECACHE_SIZE,                                    ///< AmdGetAvailableExeCacheSize general service handle
+  AMD_LATE_RUN_AP_TASK,                                     ///< AmdLateRunApTask entry point handle
+  AMD_IDENTIFY_DIMMS                                        ///< AmdIdentifyDimm general service handle
+} AGESA_STRUCT_NAME;
+
+  /*  ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+  IN       UINT32          ImageBasePtr;     ///< The AGESA Image base address.
+  IN       UINT32          Func;             ///< The service desired
+  IN       UINT32          AltImageBasePtr;  ///< Alternate Image location
+  IN       CALLOUT_ENTRY   CalloutPtr;       ///< For Callout from AGESA
+  IN       UINT8           HeapStatus;       ///< For heap status from boot time slide.
+  IN       UINT64          HeapBasePtr;      ///< Location of the heap
+  IN OUT   UINT8           Reserved[7];      ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+  IN       AMD_CONFIG_PARAMS   StdHeader;          ///< Standard configuration header
+  IN       AGESA_STRUCT_NAME   AgesaFunctionName;  ///< The service to init
+  IN       ALLOCATION_METHOD   AllocationMethod;   ///< How to handle buffer allocation
+  IN OUT   UINT32              NewStructSize;      ///< The size of the allocated data, in for ByHost, else out only.
+  IN OUT   VOID                *NewStructPtr;      ///< The struct for the service.
+                                                   ///< The struct to init for ByHost allocation,
+                                                   ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0    0   // bit-placed for PCI address creation
+#define FUNC_1    1
+#define FUNC_2    2
+#define FUNC_3    3
+#define FUNC_4    4
+#define FUNC_5    5
+#define FUNC_6    6
+#define FUNC_7    7
+
+/// AGESA Binary module header structure
+typedef struct {
+  IN  UINT32  Signature;                          ///< Binary Signature
+  IN  CHAR8   CreatorID[8];                       ///< 8 characters ID
+  IN  CHAR8   Version[12];                        ///< 12 characters version
+  IN  UINT32  ModuleInfoOffset;                   ///< Offset of module
+  IN  UINT32  EntryPointAddress;                  ///< Entry address
+  IN  UINT32  ImageBase;                          ///< Image base
+  IN  UINT32  RelocTableOffset;                   ///< Relocate Table offset
+  IN  UINT32  ImageSize;                          ///< Size
+  IN  UINT16  Checksum;                           ///< Checksum
+  IN  UINT8   ImageType;                          ///< Type
+  IN  UINT8   V_Reserved;                         ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+  IN  UINT32          ModuleHeaderSignature;      ///< Module signature
+  IN  CHAR8           ModuleIdentifier[8];        ///< 8 characters ID
+  IN  CHAR8           ModuleVersion[12];          ///< 12 characters version
+  IN  VOID            *ModuleDispatcher;          ///< A pointer point to dispatcher
+  IN  struct _AMD_MODULE_HEADER  *NextBlock;      ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE  {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+  IN  CHAR8   Signature[8];                       ///< code header Signature
+  IN  CHAR8   ComponentName[8];                   ///< 8 character name of the code module
+  IN  CHAR8   Version[12];                        ///< 12 character version string
+  IN  CHAR8   TerminatorNull;                     ///< null terminated string
+  IN  CHAR8   VerReserved[7];                     ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+  IN OUT  UINT32      Register:12;                ///< Register offset
+  IN OUT  UINT32      Function:3;                 ///< Function number
+  IN OUT  UINT32      Device:5;                   ///< Device number
+  IN OUT  UINT32      Bus:8;                      ///< Bus number
+  IN OUT  UINT32      Segment:4;                  ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+  IN  UINT32          AddressValue;               ///< Formal address
+  IN  EXT_PCI_ADDR    Address;                    ///< Extended address
+} PCI_ADDR;
+
+//   SBDFO - Segment Bus Device Function Offset
+//   31:28   Segment (4-bits)
+//   27:20   Bus     (8-bits)
+//   19:15   Device  (5-bits)
+//   14:12   Function(3-bits)
+//   11:00   Offset  (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+                   (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFF
+
+/// CPUID data received registers format
+typedef struct {
+  OUT UINT32          EAX_Reg;                    ///< CPUID instruction result in EAX
+  OUT UINT32          EBX_Reg;                    ///< CPUID instruction result in EBX
+  OUT UINT32          ECX_Reg;                    ///< CPUID instruction result in ECX
+  OUT UINT32          EDX_Reg;                    ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+/// HT frequency for external callbacks
+typedef enum {
+  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
+  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
+  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
+  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
+  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
+  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
+  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
+  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
+  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
+  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
+  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
+  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
+  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
+  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
+  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
+  HT_FREQUENCY_3200M         = 19,                ///< HT speed 3200 for external callbacks
+  HT_FREQUENCY_MAX                                ///< Limit check.
+} HT_FREQUENCIES;
+// The minimum HT3 frequency
+#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
+
+#ifndef BIT0
+  #define BIT0        0x0000000000000001ull
+#endif
+#ifndef BIT1
+  #define BIT1        0x0000000000000002ull
+#endif
+#ifndef BIT2
+  #define BIT2        0x0000000000000004ull
+#endif
+#ifndef BIT3
+  #define BIT3        0x0000000000000008ull
+#endif
+#ifndef BIT4
+  #define BIT4        0x0000000000000010ull
+#endif
+#ifndef BIT5
+  #define BIT5        0x0000000000000020ull
+#endif
+#ifndef BIT6
+  #define BIT6        0x0000000000000040ull
+#endif
+#ifndef BIT7
+  #define BIT7        0x0000000000000080ull
+#endif
+#ifndef BIT8
+  #define BIT8        0x0000000000000100ull
+#endif
+#ifndef BIT9
+  #define BIT9        0x0000000000000200ull
+#endif
+#ifndef BIT10
+  #define BIT10       0x0000000000000400ull
+#endif
+#ifndef BIT11
+  #define BIT11       0x0000000000000800ull
+#endif
+#ifndef BIT12
+  #define BIT12       0x0000000000001000ull
+#endif
+#ifndef BIT13
+  #define BIT13       0x0000000000002000ull
+#endif
+#ifndef BIT14
+  #define BIT14       0x0000000000004000ull
+#endif
+#ifndef BIT15
+  #define BIT15       0x0000000000008000ull
+#endif
+#ifndef BIT16
+  #define BIT16       0x0000000000010000ull
+#endif
+#ifndef BIT17
+  #define BIT17       0x0000000000020000ull
+#endif
+#ifndef BIT18
+  #define BIT18       0x0000000000040000ull
+#endif
+#ifndef BIT19
+  #define BIT19       0x0000000000080000ull
+#endif
+#ifndef BIT20
+  #define BIT20       0x0000000000100000ull
+#endif
+#ifndef BIT21
+  #define BIT21       0x0000000000200000ull
+#endif
+#ifndef BIT22
+  #define BIT22       0x0000000000400000ull
+#endif
+#ifndef BIT23
+  #define BIT23       0x0000000000800000ull
+#endif
+#ifndef BIT24
+  #define BIT24       0x0000000001000000ull
+#endif
+#ifndef BIT25
+  #define BIT25       0x0000000002000000ull
+#endif
+#ifndef BIT26
+  #define BIT26       0x0000000004000000ull
+#endif
+#ifndef BIT27
+  #define BIT27       0x0000000008000000ull
+#endif
+#ifndef BIT28
+  #define BIT28       0x0000000010000000ull
+#endif
+#ifndef BIT29
+  #define BIT29       0x0000000020000000ull
+#endif
+#ifndef BIT30
+  #define BIT30       0x0000000040000000ull
+#endif
+#ifndef BIT31
+  #define BIT31       0x0000000080000000ull
+#endif
+#ifndef BIT32
+  #define BIT32       0x0000000100000000ull
+#endif
+#ifndef BIT33
+  #define BIT33       0x0000000200000000ull
+#endif
+#ifndef BIT34
+  #define BIT34       0x0000000400000000ull
+#endif
+#ifndef BIT35
+  #define BIT35       0x0000000800000000ull
+#endif
+#ifndef BIT36
+  #define BIT36       0x0000001000000000ull
+#endif
+#ifndef BIT37
+  #define BIT37       0x0000002000000000ull
+#endif
+#ifndef BIT38
+  #define BIT38       0x0000004000000000ull
+#endif
+#ifndef BIT39
+  #define BIT39       0x0000008000000000ull
+#endif
+#ifndef BIT40
+  #define BIT40       0x0000010000000000ull
+#endif
+#ifndef BIT41
+  #define BIT41       0x0000020000000000ull
+#endif
+#ifndef BIT42
+  #define BIT42       0x0000040000000000ull
+#endif
+#ifndef BIT43
+  #define BIT43       0x0000080000000000ull
+#endif
+#ifndef BIT44
+  #define BIT44       0x0000100000000000ull
+#endif
+#ifndef BIT45
+  #define BIT45       0x0000200000000000ull
+#endif
+#ifndef BIT46
+  #define BIT46       0x0000400000000000ull
+#endif
+#ifndef BIT47
+  #define BIT47       0x0000800000000000ull
+#endif
+#ifndef BIT48
+  #define BIT48       0x0001000000000000ull
+#endif
+#ifndef BIT49
+  #define BIT49       0x0002000000000000ull
+#endif
+#ifndef BIT50
+  #define BIT50       0x0004000000000000ull
+#endif
+#ifndef BIT51
+  #define BIT51       0x0008000000000000ull
+#endif
+#ifndef BIT52
+  #define BIT52       0x0010000000000000ull
+#endif
+#ifndef BIT53
+  #define BIT53       0x0020000000000000ull
+#endif
+#ifndef BIT54
+  #define BIT54       0x0040000000000000ull
+#endif
+#ifndef BIT55
+  #define BIT55       0x0080000000000000ull
+#endif
+#ifndef BIT56
+  #define BIT56       0x0100000000000000ull
+#endif
+#ifndef BIT57
+  #define BIT57       0x0200000000000000ull
+#endif
+#ifndef BIT58
+  #define BIT58       0x0400000000000000ull
+#endif
+#ifndef BIT59
+  #define BIT59       0x0800000000000000ull
+#endif
+#ifndef BIT60
+  #define BIT60       0x1000000000000000ull
+#endif
+#ifndef BIT61
+  #define BIT61       0x2000000000000000ull
+#endif
+#ifndef BIT62
+  #define BIT62       0x4000000000000000ull
+#endif
+#ifndef BIT63
+  #define BIT63       0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/agesa/f15/Dispatcher.h b/src/vendorcode/amd/agesa/f15/Dispatcher.h
new file mode 100644
index 0000000..b99ae77
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Dispatcher.h
@@ -0,0 +1,52 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Legacy
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h
new file mode 100644
index 0000000..6860897
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/AdvancedApi.h
@@ -0,0 +1,167 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Advanced API Interface for HT, Memory and CPU
+ *
+ * Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
+ * would be required by the basic interface implementations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 52180 $   @e \$Date: 2011-05-03 05:17:25 -0600 (Tue, 03 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#ifndef _ADVANCED_API_H_
+#define _ADVANCED_API_H_
+
+/*----------------------------------------------------------------------------
+ *                           HT FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ * Sets inputs to valid, basic level, defaults.
+ *
+ * @param[in]   StdHeader       Opaque handle to standard config header
+ * @param[in]   AmdHtInterface  HT Interface structure to initialize.
+ *
+ * @retval AGESA_SUCCESS      Constructors are not allowed to fail
+*/
+AGESA_STATUS
+AmdHtInterfaceConstructor (
+  IN       AMD_CONFIG_PARAMS    *StdHeader,
+  IN       AMD_HT_INTERFACE     *AmdHtInterface
+  );
+
+/**
+ * The top level external interface for Hypertransport Initialization.
+ *
+ * Create our initial internal state, initialize the coherent fabric,
+ * initialize the non-coherent chains, and perform any required fabric tuning or
+ * optimization.
+ *
+ * @param[in]   StdHeader              Opaque handle to standard config header
+ * @param[in]   PlatformConfiguration  The platform configuration options.
+ * @param[in]   AmdHtInterface         HT Interface structure.
+ *
+ * @retval      AGESA_SUCCESS     Only information events logged.
+ * @retval      AGESA_ALERT       Sync Flood or CRC error logged.
+ * @retval      AGESA_WARNING     Example: expected capability not found
+ * @retval      AGESA_ERROR       logged events indicating some devices may not be available
+ * @retval      AGESA_FATAL       Mixed Family or MP capability mismatch
+ *
+ */
+AGESA_STATUS
+AmdHtInitialize (
+  IN       AMD_CONFIG_PARAMS      *StdHeader,
+  IN       PLATFORM_CONFIGURATION *PlatformConfiguration,
+  IN       AMD_HT_INTERFACE       *AmdHtInterface
+  );
+
+/*----------------------------------------------------------------------------
+ *                        HT Recovery   FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/**
+ * A constructor for the HyperTransport input structure.
+ *
+ */
+AGESA_STATUS
+AmdHtResetConstructor (
+  IN       AMD_CONFIG_PARAMS         *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE    *AmdHtResetInterface
+  );
+
+/**
+ * Initialize HT at Reset for both Normal and Recovery.
+ *
+ */
+AGESA_STATUS
+AmdHtInitReset (
+  IN       AMD_CONFIG_PARAMS        *StdHeader,
+  IN       AMD_HT_RESET_INTERFACE   *AmdHtResetInterface
+  );
+
+/**
+ * Initialize the Node and Socket maps for an AP Core.
+ *
+ */
+AGESA_STATUS
+AmdHtInitRecovery (
+  IN       AMD_CONFIG_PARAMS           *StdHeader
+  );
+
+///----------------------------------------------------------------------------
+///                          MEMORY FUNCTIONS PROTOTYPE
+///
+///----------------------------------------------------------------------------
+
+AGESA_STATUS
+AmdMemRecovery (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+AGESA_STATUS
+AmdMemAuto (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+  );
+
+VOID
+AmdMemInitDataStructDef (
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN OUT  PLATFORM_CONFIGURATION   *PlatFormConfig
+  );
+
+VOID
+memDefRet ( VOID );
+
+BOOLEAN
+memDefTrue ( VOID );
+
+BOOLEAN
+memDefFalse ( VOID );
+
+VOID
+MemRecDefRet ( VOID );
+
+BOOLEAN
+MemRecDefTrue ( VOID );
+
+#endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h b/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h
new file mode 100644
index 0000000..b59de4b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/CommonReturns.h
@@ -0,0 +1,125 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Common Return routines.
+ *
+ * Routines which do nothing, returning a result (preferably some version of zero) which
+ * is consistent with "do nothing" or "default".  Useful for function pointer tables.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 54372 $   @e \$Date: 2011-06-07 22:22:22 -0600 (Tue, 07 Jun 2011) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+#ifndef _COMMON_RETURNS_H_
+#define _COMMON_RETURNS_H_
+
+
+/**
+* Return True
+*
+* @retval True    Default case, no special action
+*/
+BOOLEAN
+CommonReturnTrue ( VOID );
+
+/**
+* Return False.
+*
+* @retval FALSE    Default case, no special action
+*/
+BOOLEAN
+CommonReturnFalse ( VOID );
+
+/**
+ * Return (UINT8)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT8
+CommonReturnZero8 ( VOID );
+
+/**
+ * Return (UINT32)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT32
+CommonReturnZero32 ( VOID );
+
+/**
+ * Return (UINT64)zero.
+ *
+ *
+ * @retval zero    None, or only case zero.
+ */
+UINT64
+CommonReturnZero64 ( VOID );
+
+/**
+ * Return NULL
+ *
+ * @retval NULL    pointer to nothing
+ */
+VOID *
+CommonReturnNULL ( VOID );
+
+/**
+* Return AGESA_SUCCESS.
+*
+* @retval AGESA_SUCCESS Success.
+*/
+AGESA_STATUS
+CommonReturnAgesaSuccess ( VOID );
+
+/**
+ * Do Nothing.
+ *
+ */
+VOID
+CommonVoid ( VOID );
+
+/**
+ * ASSERT if this routine is called.
+ *
+ */
+VOID
+CommonAssert ( VOID );
+
+#endif // _COMMON_RETURNS_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/Filecode.h b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
new file mode 100644
index 0000000..0d9f67a
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Filecode.h
@@ -0,0 +1,1174 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Include
+ * @e \$Revision: 56033 $   @e \$Date: 2011-07-06 01:12:20 -0600 (Wed, 06 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE                                         (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE                               (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE                          (0xA001)
+#define PROC_GNB_GFX_FAMILY_LN_F12GFXSERVICES_FILECODE                   (0xA002)
+#define PROC_GNB_GFX_FAMILY_ON_F14GFXSERVICES_FILECODE                   (0xA003)
+#define PROC_GNB_GFX_GFXCONFIGDATA_FILECODE                              (0xA004)
+#define PROC_GNB_GFX_GFXGMCINIT_FILECODE                                 (0xA006)
+#define PROC_GNB_GFX_GFXINITATENVPOST_FILECODE                           (0xA010)
+#define PROC_GNB_GFX_GFXINITATMIDPOST_FILECODE                           (0xA011)
+#define PROC_GNB_GFX_GFXINITATPOST_FILECODE                              (0xA012)
+#define PROC_GNB_GFX_GFXINTEGRATEDINFOTABLEINIT_FILECODE                 (0xA013)
+#define PROC_GNB_GFX_GFXLIB_FILECODE                                     (0xA014)
+#define PROC_GNB_GFX_GFXREGISTERACC_FILECODE                             (0xA015)
+#define PROC_GNB_GFX_GFXSTRAPSINIT_FILECODE                              (0xA016)
+#define PROC_GNB_GNBINITATEARLY_FILECODE                                 (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE                                   (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE                                  (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE                                   (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE                                  (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE                                 (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE                    (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE              (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE                (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE               (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE              (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE                 (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE              (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE            (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE      (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE      (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE          (0xA034)
+#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE                 (0xA035)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE           (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE            (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE          (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE          (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPM_FILECODE              (0xA03A)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE     (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE   (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE       (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE       (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE        (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE      (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE         (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE   (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE             (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE  (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE        (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE     (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE         (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE      (0xA04B)
+#define PROC_GNB_NB_FAMILY_LN_F12NBPOWERGATE_FILECODE                  (0xA04C)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSERVICES_FILECODE                   (0xA04D)
+#define PROC_GNB_NB_FAMILY_LN_F12NBSMU_FILECODE                        (0xA04E)
+#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKNCLKRATIO_FILECODE                (0xA04F)
+#define PROC_GNB_NB_FAMILY_ON_F14NBPOWERGATE_FILECODE                    (0xA050)
+#define PROC_GNB_NB_FAMILY_ON_F14NBSERVICES_FILECODE                     (0xA051)
+#define PROC_GNB_NB_FAMILY_ON_F14NBSMU_FILECODE                          (0xA052)
+#define PROC_GNB_NB_FEATURE_NBFUSETABLE_FILECODE                         (0xA053)
+#define PROC_GNB_NB_FEATURE_NBLCLKDPM_FILECODE                           (0xA054)
+#define PROC_GNB_NB_FAMILY_LN_F12NBLCLKDPM_FILECODE                    (0xA055)
+#define PROC_GNB_NB_FAMILY_ON_F14NBLCLKDPM_FILECODE                      (0xA056)
+#define PROC_GNB_NB_NBCONFIGDATA_FILECODE                                (0xA060)
+#define PROC_GNB_NB_NBINIT_FILECODE                                      (0xA061)
+#define PROC_GNB_NB_NBINITATEARLY_FILECODE                               (0xA062)
+#define PROC_GNB_NB_NBINITATENV_FILECODE                                 (0xA063)
+#define PROC_GNB_NB_NBINITATLATEPOST_FILECODE                            (0xA070)
+#define PROC_GNB_NB_NBINITATPOST_FILECODE                                (0xA071)
+#define PROC_GNB_NB_NBINITATRESET_FILECODE                               (0xA072)
+#define PROC_GNB_NB_NBPOWERMGMT_FILECODE                                 (0xA073)
+#define PROC_GNB_NB_NBSMULIB_FILECODE                                    (0xA074)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEALIB_FILECODE                   (0xA075)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXCONFIG_FILECODE          (0xA076)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIECOMPLEXSERVICES_FILECODE        (0xA077)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPHYSERVICES_FILECODE            (0xA078)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEPIFSERVICES_FILECODE            (0xA079)
+#define PROC_GNB_PCIE_FAMILY_LN_F12PCIEWRAPPERSERVICES_FILECODE        (0xA07A)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEALIB_FILECODE                     (0xA07D)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXCONFIG_FILECODE            (0xA07E)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIECOMPLEXSERVICES_FILECODE          (0xA07F)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPHYSERVICES_FILECODE              (0xA080)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEPIFSERVICES_FILECODE              (0xA081)
+#define PROC_GNB_PCIE_FAMILY_ON_F14PCIEWRAPPERSERVICES_FILECODE          (0xA082)
+#define PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE                     (0xA083)
+#define PROC_GNB_PCIE_PCIEINIT_FILECODE                                  (0xA084)
+#define PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE                       (0xA085)
+#define PROC_GNB_PCIE_PCIEINITATENV_FILECODE                             (0xA086)
+#define PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE                        (0xA087)
+#define PROC_GNB_PCIE_PCIEINITATPOST_FILECODE                            (0xA088)
+#define PROC_GNB_PCIE_PCIELATEINIT_FILECODE                              (0xA089)
+#define PROC_GNB_PCIE_PCIEPORTINIT_FILECODE                              (0xA08B)
+#define PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE                          (0xA08C)
+#define PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE              (0xA08D)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE              (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE             (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE                      (0xA090)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE        (0xA091)
+#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE                 (0xA092)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE              (0xA093)
+#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE                 (0xA094)
+#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE     (0xA095)
+#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE                     (0xA096)
+#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE                 (0xA097)
+#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE                (0xA098)
+#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE               (0xA09A)
+#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE                 (0xA09B)
+#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE               (0xA09C)
+#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE                 (0xA09D)
+#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE                (0xA09E)
+#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE             (0xA09F)
+#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE                 (0xA0A0)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE              (0xA0A1)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE                (0xA0A2)
+#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE                    (0xA0A3)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE                (0xA0A4)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE               (0xA0A5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
+#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE              (0xA0A7)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE                  (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE          (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE   (0xA0AA)
+#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE               (0xA0AB)
+#define PROC_GNB_GFX_FAMILY_KR_KRGFXSERVICES_FILECODE                    (0xA0AC)
+#define PROC_GNB_NB_FAMILY_KR_KRNBSMU_FILECODE                           (0xA0AD)
+#define PROC_GNB_NB_FAMILY_KR_KRNBPOWERGATE_FILECODE                     (0xA0AE)
+#define PROC_GNB_NB_FAMILY_KR_KRNBSERVICES_FILECODE                      (0xA0AF)
+#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKNCLKRATIO_FILECODE                 (0xA0B0)
+#define PROC_GNB_NB_FAMILY_KR_KRNBLCLKDPM_FILECODE                       (0xA0B1)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEALIB_FILECODE                      (0xA0B2)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXCONFIG_FILECODE             (0xA0B3)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIECOMPLEXSERVICES_FILECODE           (0xA0B4)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPHYSERVICES_FILECODE               (0xA0B5)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEWRAPPERSERVICES_FILECODE           (0xA0B6)
+#define PROC_GNB_PCIE_FAMILY_KR_KRPCIEPIFSERVICES_FILECODE               (0xA0B7)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE              (0xA0B8)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTN_FILECODE                   (0xA0B9)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE                     (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE                      (0xA0BB)
+#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE            (0xA0BC)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBSTALL_FILECODE               (0xA0BD)
+#define PROC_GNB_MODULES_GNBMSOCKETLIB_GNBMSOCKETLIB_FILECODE            (0xA0BE)
+#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE            (0xA0BF)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE             (0xA0C0)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPHYSERVICESV5_FILECODE     (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE     (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE    (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE       (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE          (0xA0CB)
+
+#define PROC_GNB_MODULES_GNBINITKM_GNBEARLYINITKM_FILECODE               (0xA0CC)
+#define PROC_GNB_MODULES_GNBINITKM_GNBENVINITKM_FILECODE                 (0xA0CD)
+#define PROC_GNB_MODULES_GNBINITKM_GNBIOMMUIVRSKM_FILECODE               (0xA0CE)
+#define PROC_GNB_MODULES_GNBINITKM_GNBMIDINITKM_FILECODE                 (0xA0CF)
+#define PROC_GNB_MODULES_GNBINITKM_GNBPOSTINITKM_FILECODE                (0xA0D0)
+#define PROC_GNB_MODULES_GNBINITKM_GNBREGISTERACCKM_FILECODE             (0xA0D1)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMC2012_FILECODE       (0xA0D2)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMFM2_FILECODE         (0xA0D3)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECOMPLEXDATAKMG2012_FILECODE       (0xA0D4)
+#define PROC_GNB_MODULES_GNBINITKM_PCIECONFIGKM_FILECODE                 (0xA0D5)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEEARLYINITKM_FILECODE              (0xA0D6)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEENVINITKM_FILECODE                (0xA0D7)
+#define PROC_GNB_MODULES_GNBINITKM_PCIELIBKM_FILECODE                    (0xA0D8)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEMIDINITKM_FILECODE                (0xA0D9)
+#define PROC_GNB_MODULES_GNBINITKM_PCIEPOSTINITKM_FILECODE               (0xA0DA)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE       (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE       (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE    (0xA0DD)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE                           (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE                        (0xAE02)
+
+// FCH
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE                             (0xB001)
+#define PROC_FCH_AZALIA_AZALIAENV_FILECODE                               (0xB002)
+#define PROC_FCH_AZALIA_AZALIAMID_FILECODE                               (0xB003)
+#define PROC_FCH_AZALIA_AZALIALATE_FILECODE                              (0xB004)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE                                 (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE                                  (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE                               (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE                            (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE                                  (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE                                  (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE                                (0xB016)
+#define PROC_FCH_GEC_GECRESET_FILECODE                                   (0xB020)
+#define PROC_FCH_GEC_GECENV_FILECODE                                     (0xB021)
+#define PROC_FCH_GEC_GECMID_FILECODE                                     (0xB022)
+#define PROC_FCH_GEC_GECLATE_FILECODE                                    (0xB023)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE           (0xB024)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE        (0xB025)
+#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECSERVICE_FILECODE                 (0xB026)
+#define PROC_FCH_GEC_FAMILY_YUBA_YUBAGECENVSERVICE_FILECODE              (0xB027)
+#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE                             (0xB030)
+#define PROC_FCH_HWACPI_HWACPIENV_FILECODE                               (0xB031)
+#define PROC_FCH_HWACPI_HWACPIMID_FILECODE                               (0xB032)
+#define PROC_FCH_HWACPI_HWACPILATE_FILECODE                              (0xB033)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE  (0xB034)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE  (0xB035)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE         (0xB037)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIENVSERVICE_FILECODE        (0xB038)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPIMIDSERVICE_FILECODE        (0xB039)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBAHWACPILATESERVICE_FILECODE       (0xB03A)
+#define PROC_FCH_HWACPI_FAMILY_YUBA_YUBASSSERVICE_FILECODE               (0xB03B)
+#define PROC_FCH_HWM_HWMRESET_FILECODE                                   (0xB040)
+#define PROC_FCH_HWM_HWMENV_FILECODE                                     (0xB041)
+#define PROC_FCH_HWM_HWMMID_FILECODE                                     (0xB042)
+#define PROC_FCH_HWM_HWMLATE_FILECODE                                    (0xB043)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE        (0xB044)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE        (0xB045)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE       (0xB046)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMENVSERVICE_FILECODE              (0xB047)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMMIDSERVICE_FILECODE              (0xB048)
+#define PROC_FCH_HWM_FAMILY_YUBA_YUBAHWMLATESERVICE_FILECODE             (0xB049)
+#define PROC_FCH_IDE_IDEENV_FILECODE                                     (0xB050)
+#define PROC_FCH_IDE_IDEMID_FILECODE                                     (0xB051)
+#define PROC_FCH_IDE_IDELATE_FILECODE                                    (0xB052)
+#define PROC_FCH_IMC_IMCENV_FILECODE                                     (0xB060)
+#define PROC_FCH_IMC_IMCMID_FILECODE                                     (0xB061)
+#define PROC_FCH_IMC_IMCLATE_FILECODE                                    (0xB062)
+#define PROC_FCH_IMC_IMCLIB_FILECODE                                     (0xB063)
+#define PROC_FCH_IMC_IMCRESET_FILECODE                                   (0xB064)
+#define PROC_FCH_IMC_FCHECENV_FILECODE                                   (0xB065)
+#define PROC_FCH_IMC_FCHECMID_FILECODE                                   (0xB066)
+#define PROC_FCH_IMC_FCHECLATE_FILECODE                                  (0xB067)
+#define PROC_FCH_IMC_FCHECRESET_FILECODE                                 (0xB068)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE           (0xB069)
+#define PROC_FCH_IMC_FAMILY_YUBA_YUBAIMCSERVICE_FILECODE                 (0xB06A)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE                         (0xB070)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE                           (0xB071)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE                         (0xB072)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE                           (0xB073)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE                          (0xB074)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE                           (0xB075)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE                            (0xB076)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE                      (0xB077)
+#define PROC_FCH_IR_IRENV_FILECODE                                       (0xB080)
+#define PROC_FCH_IR_IRMID_FILECODE                                       (0xB081)
+#define PROC_FCH_IR_IRLATE_FILECODE                                      (0xB082)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE                                 (0xB090)
+#define PROC_FCH_PCIB_PCIBENV_FILECODE                                   (0xB091)
+#define PROC_FCH_PCIB_PCIBMID_FILECODE                                   (0xB092)
+#define PROC_FCH_PCIB_PCIBLATE_FILECODE                                  (0xB093)
+#define PROC_FCH_PCIE_ABRESET_FILECODE                                   (0xB0A0)
+#define PROC_FCH_PCIE_ABENV_FILECODE                                     (0xB0A1)
+#define PROC_FCH_PCIE_ABMID_FILECODE                                     (0xB0A2)
+#define PROC_FCH_PCIE_ABLATE_FILECODE                                    (0xB0A3)
+#define PROC_FCH_PCIE_GPPHP_FILECODE                                     (0xB0A4)
+#define PROC_FCH_PCIE_GPPLIB_FILECODE                                    (0xB0A5)
+#define PROC_FCH_PCIE_GPPRESET_FILECODE                                  (0xB0A6)
+#define PROC_FCH_PCIE_GPPENV_FILECODE                                    (0xB0A7)
+#define PROC_FCH_PCIE_GPPMID_FILECODE                                    (0xB0A8)
+#define PROC_FCH_PCIE_GPPLATE_FILECODE                                   (0xB0A9)
+#define PROC_FCH_PCIE_PCIERESET_FILECODE                                 (0xB0AA)
+#define PROC_FCH_PCIE_PCIEENV_FILECODE                                   (0xB0AB)
+#define PROC_FCH_PCIE_PCIEMID_FILECODE                                   (0xB0AC)
+#define PROC_FCH_PCIE_PCIELATE_FILECODE                                  (0xB0AD)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE      (0xB0AE)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE        (0xB0AF)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE           (0xB0B0)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE     (0xB0B1)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE          (0xB0B2)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE      (0xB0B3)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE         (0xB0B4)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABRESETSERVICE_FILECODE            (0xB0B5)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABENVSERVICE_FILECODE              (0xB0B6)
+#define PROC_FCH_PCIE_FAMILY_YUBA_YUBAABSERVICE_FILECODE                 (0xB0B7)
+#define PROC_FCH_SATA_AHCIENV_FILECODE                                   (0xB0C0)
+#define PROC_FCH_SATA_AHCIMID_FILECODE                                   (0xB0C1)
+#define PROC_FCH_SATA_AHCILATE_FILECODE                                  (0xB0C2)
+#define PROC_FCH_SATA_AHCILIB_FILECODE                                   (0xB0C3)
+#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE                               (0xB0C4)
+#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE                               (0xB0C5)
+#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE                              (0xB0C6)
+#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE                               (0xB0C7)
+#define PROC_FCH_SATA_RAIDENV_FILECODE                                   (0xB0C8)
+#define PROC_FCH_SATA_RAIDMID_FILECODE                                   (0xB0C9)
+#define PROC_FCH_SATA_RAIDLATE_FILECODE                                  (0xB0CA)
+#define PROC_FCH_SATA_RAIDLIB_FILECODE                                   (0xB0CB)
+#define PROC_FCH_SATA_SATAENV_FILECODE                                   (0xB0CC)
+#define PROC_FCH_SATA_SATAENVLIB_FILECODE                                (0xB0CD)
+#define PROC_FCH_SATA_SATAIDEENV_FILECODE                                (0xB0CE)
+#define PROC_FCH_SATA_SATAIDEMID_FILECODE                                (0xB0CF)
+#define PROC_FCH_SATA_SATAIDELATE_FILECODE                               (0xB0D0)
+#define PROC_FCH_SATA_SATAIDELIB_FILECODE                                (0xB0D1)
+#define PROC_FCH_SATA_SATAMID_FILECODE                                   (0xB0D2)
+#define PROC_FCH_SATA_SATALATE_FILECODE                                  (0xB0D3)
+#define PROC_FCH_SATA_SATALIB_FILECODE                                   (0xB0D4)
+#define PROC_FCH_SATA_SATARESET_FILECODE                                 (0xB0D5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE    (0xB0D6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE      (0xB0D7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE         (0xB0D8)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATARESETSERVICE_FILECODE          (0xB0D9)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATAENVSERVICE_FILECODE            (0xB0DA)
+#define PROC_FCH_SATA_FAMILY_YUBA_YUBASATASERVICE_FILECODE               (0xB0DB)
+#define PROC_FCH_SD_SDENV_FILECODE                                       (0xB0E0)
+#define PROC_FCH_SD_SDMID_FILECODE                                       (0xB0E1)
+#define PROC_FCH_SD_SDLATE_FILECODE                                      (0xB0E2)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE             (0xB0E3)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE        (0xB0E4)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE          (0xB0E5)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDSERVICE_FILECODE                   (0xB0E6)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDRESETSERVICE_FILECODE              (0xB0E7)
+#define PROC_FCH_SD_FAMILY_YUBA_YUBASDENVSERVICE_FILECODE                (0xB0E8)
+#define PROC_FCH_SPI_LPCRESET_FILECODE                                   (0xB0F0)
+#define PROC_FCH_SPI_LPCENV_FILECODE                                     (0xB0F1)
+#define PROC_FCH_SPI_LPCMID_FILECODE                                     (0xB0F2)
+#define PROC_FCH_SPI_LPCLATE_FILECODE                                    (0xB0F3)
+#define PROC_FCH_SPI_SPIRESET_FILECODE                                   (0xB0F4)
+#define PROC_FCH_SPI_SPIENV_FILECODE                                     (0xB0F5)
+#define PROC_FCH_SPI_SPIMID_FILECODE                                     (0xB0F6)
+#define PROC_FCH_SPI_SPILATE_FILECODE                                    (0xB0F7)
+#define PROC_FCH_USB_EHCIRESET_FILECODE                                  (0xB100)
+#define PROC_FCH_USB_EHCIENV_FILECODE                                    (0xB101)
+#define PROC_FCH_USB_EHCIMID_FILECODE                                    (0xB102)
+#define PROC_FCH_USB_EHCILATE_FILECODE                                   (0xB103)
+#define PROC_FCH_USB_OHCIRESET_FILECODE                                  (0xB104)
+#define PROC_FCH_USB_OHCIENV_FILECODE                                    (0xB105)
+#define PROC_FCH_USB_OHCIMID_FILECODE                                    (0xB106)
+#define PROC_FCH_USB_OHCILATE_FILECODE                                   (0xB107)
+#define PROC_FCH_USB_USBRESET_FILECODE                                   (0xB108)
+#define PROC_FCH_USB_USBENV_FILECODE                                     (0xB109)
+#define PROC_FCH_USB_USBMID_FILECODE                                     (0xB10A)
+#define PROC_FCH_USB_USBLATE_FILECODE                                    (0xB10B)
+#define PROC_FCH_USB_XHCIRESET_FILECODE                                  (0xB10C)
+#define PROC_FCH_USB_XHCIENV_FILECODE                                    (0xB10D)
+#define PROC_FCH_USB_XHCIMID_FILECODE                                    (0xB10E)
+#define PROC_FCH_USB_XHCILATE_FILECODE                                   (0xB10F)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE       (0xB110)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE       (0xB111)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE      (0xB112)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE       (0xB113)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE       (0xB114)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE      (0xB115)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE     (0xB116)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE       (0xB117)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE       (0xB118)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE      (0xB119)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIENVSERVICE_FILECODE          (0xB11A)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCIMIDSERVICE_FILECODE          (0xB11B)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAEHCILATESERVICE_FILECODE         (0xB11C)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIENVSERVICE_FILECODE          (0xB11D)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCIMIDSERVICE_FILECODE          (0xB11E)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAOHCILATESERVICE_FILECODE         (0xB11F)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIRESETSERVICE_FILECODE        (0xB120)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIENVSERVICE_FILECODE          (0xB121)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCIMIDSERVICE_FILECODE          (0xB122)
+#define PROC_FCH_USB_FAMILY_YUBA_YUBAXHCILATESERVICE_FILECODE         (0xB123)
+#define PROC_FCH_USB_XHCIRECOVERY_FILECODE                            (0xB124)
+#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE                            (0xB125)
+
+#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE                              (0xB200)
+#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE                              (0xB220)
+#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE                     (0xB221)
+#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE                       (0xB222)
+#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE                (0xB230)
+#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE                          (0xB240)
+#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE              (0xB250)
+#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE                 (0xB251)
+#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE                        (0xB252)
+#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE                              (0xB260)
+#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE                               (0xB261)
+#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE                               (0xB262)
+#define UEFI_PEI_FCHPEI_LIBAMDPEI_FILECODE                              (0xB263)
+#define UEFI_PEI_SMBUS_SMBUS_FILECODE                                   (0xB270)
+#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE                              (0xB280)
+#define UEFI_SMM_FCHSMM_GPESMI_FILECODE                                (0xB282)
+#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE                             (0xB283)
+#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE                               (0xB284)
+#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE                      (0xB285)
+#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE                        (0xB286)
+#define UEFI_SMM_FCHSMM_SWSMI_FILECODE                                 (0xB287)
+#define UEFI_SMM_FCHSMM_SXSMI_FILECODE                                 (0xB288)
+#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE                               (0xB2A0)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE                     (0xB290)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE        (0xB292)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE  (0xB293)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE      (0xB294)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB295)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE  (0xB296)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE          (0xB297)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE          (0xB298)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE        (0xB299)
+
+#define LIB_AMDLIB_FILECODE                                              (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE                               (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE                                 (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE                                  (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE            (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE                (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE      (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE                (0xC142)
+#define UEFI_PROC_HOBTRANSFERUEFI_FILECODE                               (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE                                (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE                                  (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE                                 (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE                                  (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE                                 (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE                             (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE                                (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE                               (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE                            (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE                                   (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE                            (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE                               (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE                                (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE                                 (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE                              (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE                                 (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE                               (0xC401)
+#define PROC_CPU_CPUBRANDID_FILECODE                                     (0xC402)
+#define PROC_CPU_TABLE_FILECODE                                          (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE                                   (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE                                    (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE                           (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE                             (0xC408)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE                              (0xC409)
+#define PROC_CPU_CPULATEINIT_FILECODE                                    (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE                              (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE                                   (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE                                    (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE                                        (0xC40E)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE                                    (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE                                   (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE                        (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE                       (0xC432)
+#define PROC_CPU_S3_FILECODE                                             (0xC460)
+
+// Family 10h
+#define PROC_CPU_FAMILY_0X10_CPUCOMMONF10UTILITIES_FILECODE              (0xC801)
+#define PROC_CPU_FAMILY_0X10_CPUF10BRANDID_FILECODE                      (0xC802)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEDEFAULTS_FILECODE                (0xC803)
+#define PROC_CPU_FAMILY_0X10_CPUF10CACHEFLUSHONHALT_FILECODE             (0xC804)
+#define PROC_CPU_FAMILY_0X10_CPUF10DMI_FILECODE                          (0xC805)
+#define PROC_CPU_FAMILY_0X10_CPUF10EARLYINIT_FILECODE                    (0xC806)
+#define PROC_CPU_FAMILY_0X10_CPUF10FEATURELEVELING_FILECODE              (0xC807)
+#define PROC_CPU_FAMILY_0X10_CPUF10HTPHYTABLES_FILECODE                  (0xC808)
+#define PROC_CPU_FAMILY_0X10_CPUF10MSRTABLES_FILECODE                    (0xC809)
+#define PROC_CPU_FAMILY_0X10_CPUF10PCITABLES_FILECODE                    (0xC80A)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERCHECK_FILECODE                   (0xC80B)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERMGMTSYSTEMTABLES_FILECODE        (0xC80C)
+#define PROC_CPU_FAMILY_0X10_CPUF10POWERPLANE_FILECODE                   (0xC80D)
+#define PROC_CPU_FAMILY_0X10_CPUF10SOFTWARETHERMAL_FILECODE              (0xC80E)
+#define PROC_CPU_FAMILY_0X10_CPUF10UTILITIES_FILECODE                    (0xC80F)
+#define PROC_CPU_FAMILY_0X10_CPUF10WHEAINITDATATABLES_FILECODE           (0xC810)
+#define PROC_CPU_FAMILY_0X10_CPUF10PSTATE_FILECODE                       (0xC811)
+#define PROC_CPU_FAMILY_0X10_CPUF10CPB_FILECODE                          (0xC812)
+#define PROC_CPU_FAMILY_0X10_CPUF10WORKAROUNDSTABLE_FILECODE             (0xC813)
+#define PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE                  (0xC820)
+#define PROC_CPU_FAMILY_0X10_F10SINGLELINKPCITABLES_FILECODE             (0xC821)
+#define PROC_CPU_FAMILY_0X10_F10MULTILINKPCITABLES_FILECODE              (0xC822)
+#define PROC_CPU_FAMILY_0X10_F10PMNBPSTATEINIT_FILECODE                  (0xC823)
+#define PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE                 (0xC824)
+#define PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE                  (0xC825)
+#define PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE          (0xC826)
+#define PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE                        (0xC827)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE              (0xC830)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE                  (0xC831)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE                  (0xC832)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE              (0xC833)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE              (0xC834)
+#define PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE            (0xC835)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLHTPHYTABLES_FILECODE           (0xC836)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLLOGICALIDTABLES_FILECODE       (0xC837)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMICROCODEPATCHTABLES_FILECODE  (0xC838)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLMSRTABLES_FILECODE             (0xC839)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLEQUIVALENCETABLE_FILECODE      (0xC83A)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLPCITABLES_FILECODE             (0xC83B)
+#define PROC_CPU_FAMILY_0X10_REVC_BL_F10BLCACHEFLUSHONHALT_FILECODE      (0xC83C)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAHTPHYTABLES_FILECODE           (0xC83D)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DALOGICALIDTABLES_FILECODE       (0xC83E)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMICROCODEPATCHTABLES_FILECODE  (0xC83F)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAMSRTABLES_FILECODE             (0xC840)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAEQUIVALENCETABLE_FILECODE      (0xC841)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DAPCITABLES_FILECODE             (0xC842)
+#define PROC_CPU_FAMILY_0X10_REVC_DA_F10DACACHEFLUSHONHALT_FILECODE      (0xC843)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBHTPHYTABLES_FILECODE           (0xC844)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBLOGICALIDTABLES_FILECODE       (0xC845)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMICROCODEPATCHTABLES_FILECODE  (0xC846)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBMSRTABLES_FILECODE             (0xC847)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBEQUIVALENCETABLE_FILECODE      (0xC848)
+#define PROC_CPU_FAMILY_0X10_REVC_RB_F10RBPCITABLES_FILECODE             (0xC849)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDUTILITIES_FILECODE              (0xC850)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDMSGBASEDC1E_FILECODE            (0xC851)
+#define PROC_CPU_FAMILY_0X10_REVD_F10REVDL3FEATURES_FILECODE             (0xC852)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYHTPHYTABLES_FILECODE           (0xC853)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYINITEARLYTABLE_FILECODE        (0xC854)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYLOGICALIDTABLES_FILECODE       (0xC855)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMICROCODEPATCHTABLES_FILECODE  (0xC856)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE             (0xC857)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYEQUIVALENCETABLE_FILECODE      (0xC858)
+#define PROC_CPU_FAMILY_0X10_REVD_HY_F10HYPCITABLES_FILECODE             (0xC859)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE              (0xC860)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE              (0xC861)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE              (0xC862)
+#define PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE            (0xC863)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHEQUIVALENCETABLE_FILECODE      (0xC864)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHHTPHYTABLES_FILECODE           (0xC865)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHLOGICALIDTABLES_FILECODE       (0xC866)
+#define PROC_CPU_FAMILY_0X10_REVE_PH_F10PHMICROCODEPATCHTABLES_FILECODE  (0xC867)
+
+// Family 12h
+#define PROC_CPU_FAMILY_0X12_CPUCOMMONF12UTILITIES_FILECODE              (0xC901)
+#define PROC_CPU_FAMILY_0X12_CPUF12BRANDID_FILECODE                      (0xC902)
+#define PROC_CPU_FAMILY_0X12_CPUF12CACHEDEFAULTS_FILECODE                (0xC903)
+#define PROC_CPU_FAMILY_0X12_CPUF12DMI_FILECODE                          (0xC904)
+#define PROC_CPU_FAMILY_0X12_CPUF12MSRTABLES_FILECODE                    (0xC905)
+#define PROC_CPU_FAMILY_0X12_CPUF12EARLYNBPSTATEINIT_FILECODE            (0xC906)
+#define PROC_CPU_FAMILY_0X12_CPUF12PCITABLES_FILECODE                    (0xC907)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERCHECK_FILECODE                   (0xC908)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERMGMTSYSTEMTABLES_FILECODE        (0xC909)
+#define PROC_CPU_FAMILY_0X12_CPUF12POWERPLANE_FILECODE                   (0xC90A)
+#define PROC_CPU_FAMILY_0X12_CPUF12SOFTWARETHERMAL_FILECODE              (0xC90B)
+#define PROC_CPU_FAMILY_0X12_CPUF12UTILITIES_FILECODE                    (0xC90C)
+#define PROC_CPU_FAMILY_0X12_CPUF12WHEAINITDATATABLES_FILECODE           (0xC90D)
+#define PROC_CPU_FAMILY_0X12_CPUF12PSTATE_FILECODE                       (0xC90E)
+#define PROC_CPU_FAMILY_0X12_F12C6STATE_FILECODE                         (0xC90F)
+#define PROC_CPU_FAMILY_0X12_F12CPB_FILECODE                             (0xC910)
+#define PROC_CPU_FAMILY_0X12_F12IOCSTATE_FILECODE                        (0xC911)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNLOGICALIDTABLES_FILECODE            (0xC921)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNMICROCODEPATCHTABLES_FILECODE       (0xC922)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEQUIVALENCETABLE_FILECODE           (0xC923)
+#define PROC_CPU_FAMILY_0X12_CPUF12PERCOREPCITABLES_FILECODE             (0xC924)
+#define PROC_CPU_FAMILY_0X12_LN_F12LNEARLYSAMPLES_FILECODE               (0xC925)
+
+// Family 14h
+#define PROC_CPU_FAMILY_0X14_CPUCOMMONF14UTILITIES_FILECODE              (0xCA01)
+#define PROC_CPU_FAMILY_0X14_CPUF14BRANDID_FILECODE                      (0xCA02)
+#define PROC_CPU_FAMILY_0X14_CPUF14CACHEDEFAULTS_FILECODE                (0xCA03)
+#define PROC_CPU_FAMILY_0X14_CPUF14DMI_FILECODE                          (0xCA04)
+#define PROC_CPU_FAMILY_0X14_CPUF14MSRTABLES_FILECODE                    (0xCA05)
+#define PROC_CPU_FAMILY_0X14_CPUF14PCITABLES_FILECODE                    (0xCA06)
+#define PROC_CPU_FAMILY_0X14_CPUF14UTILITIES_FILECODE                    (0xCA07)
+#define PROC_CPU_FAMILY_0X14_CPUF14WHEAINITDATATABLES_FILECODE           (0xCA08)
+#define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0xCA09)
+#define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE                        (0xCA0A)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA0B)
+
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERPLANE_FILECODE                 (0xCA21)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONC6STATE_FILECODE                    (0xCA22)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA23)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA24)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA25)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE             (0xCA26)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE               (0xCA27)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONMSRTABLES_FILECODE                  (0xCA28)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONUTILITIES_FILECODE                  (0xCA29)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERMGMTSYSTEMTABLES_FILECODE      (0xCA2A)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONLOWPOWERINIT_FILECODE               (0xCA2B)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE                        (0xCA2C)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONSOFTWARETHERMAL_FILECODE            (0xCA2D)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPOWERCHECK_FILECODE                 (0xCA2E)
+
+#define PROC_CPU_FAMILY_0X14_KR_F14KREQUIVALENCETABLE_FILECODE           (0xCA41)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRINITEARLYTABLE_FILECODE             (0xCA42)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRLOGICALIDTABLES_FILECODE            (0xCA43)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRMICROCODEPATCHTABLES_FILECODE       (0xCA44)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRCPB_FILECODE                        (0xCA45)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRC6STATE_FILECODE                    (0xCA46)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRUTILITIES_FILECODE                  (0xCA47)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERPLANE_FILECODE                 (0xCA48)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERMGMTSYSTEMTABLES_FILECODE      (0xCA49)
+#define PROC_CPU_FAMILY_0X14_KR_F14KREARLYNBPSTATEINIT_FILECODE          (0xCA4A)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRMSRTABLES_FILECODE                  (0xCA4B)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPCITABLES_FILECODE                  (0xCA4C)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRSOFTWARETHERMAL_FILECODE            (0xCA4D)
+#define PROC_CPU_FAMILY_0X14_KR_F14KRPOWERCHECK_FILECODE                 (0xCA4E)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE              (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE                      (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE                (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE                          (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE                    (0xCB05)
+#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE                    (0xCB06)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE                   (0xCB07)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE                    (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE           (0xCB09)
+#define PROC_CPU_FAMILY_0X15_F15PSTATEHPCMODE_FILECODE                   (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE                          (0xCB0B)
+
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCOREAFTERRESET_FILECODE          (0xCB20)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORDMI_FILECODE                     (0xCB21)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORNBAFTERRESET_FILECODE            (0xCB22)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORPSTATE_FILECODE                  (0xCB23)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORL3FEATURES_FILECODE                 (0xCB24)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSGBASEDC1E_FILECODE                (0xCB25)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOGICALIDTABLES_FILECODE            (0xCB26)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMICROCODEPATCHTABLES_FILECODE       (0xCB27)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMSRTABLES_FILECODE                  (0xCB28)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSHAREDMSRTABLE_FILECODE             (0xCB29)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREQUIVALENCETABLE_FILECODE           (0xCB2A)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPCITABLES_FILECODE                  (0xCB2B)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB2C)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPOWERPLANE_FILECODE                 (0xCB2D)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORUTILITIES_FILECODE                  (0xCB2E)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORWORKAROUNDSTABLE_FILECODE           (0xCB2F)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORPMNBCOFVIDINIT_FILECODE             (0xCB30)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORLOWPWRPSTATE_FILECODE               (0xCB31)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORSINGLELINKPCITABLES_FILECODE        (0xCB32)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORMULTILINKPCITABLES_FILECODE         (0xCB33)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORC6STATE_FILECODE                    (0xCB34)
+#define PROC_CPU_FAMILY_0X15_OR_F15OREARLYSAMPLES_FILECODE               (0xCB35)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORCPB_FILECODE                        (0xCB36)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORIOCSTATE_FILECODE                   (0xCB37)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORCACHEFLUSHONHALT_FILECODE        (0xCB38)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORFEATURELEVELING_FILECODE         (0xCB39)
+#define PROC_CPU_FAMILY_0X15_OR_CPUF15ORSOFTWARETHERMAL_FILECODE         (0xCB3A)
+#define PROC_CPU_FAMILY_0X15_OR_F15ORINITEARLYTABLE_FILECODE             (0xCB3B)
+
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE          (0xCB50)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE                     (0xCB51)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE            (0xCB52)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE                  (0xCB53)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE            (0xCB54)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE       (0xCB55)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE                  (0xCB56)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE             (0xCB57)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE           (0xCB58)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE                  (0xCB59)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB5A)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE                 (0xCB5B)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE                  (0xCB5C)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE                    (0xCB5D)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE                        (0xCB5E)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE                   (0xCB5F)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE        (0xCB60)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNSOFTWARETHERMAL_FILECODE         (0xCB61)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE             (0xCB62)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE               (0xCB63)
+
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCOREAFTERRESET_FILECODE          (0xCB80)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMDMI_FILECODE                     (0xCB81)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMNBAFTERRESET_FILECODE            (0xCB82)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMPSTATE_FILECODE                  (0xCB83)
+#define PROC_CPU_FAMILY_0X15_KM_F15KML3FEATURES_FILECODE                 (0xCB84)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMSGBASEDC1E_FILECODE                (0xCB85)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMLOGICALIDTABLES_FILECODE            (0xCB86)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMICROCODEPATCHTABLES_FILECODE       (0xCB87)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMSRTABLES_FILECODE                  (0xCB88)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMSHAREDMSRTABLE_FILECODE             (0xCB89)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMEQUIVALENCETABLE_FILECODE           (0xCB8A)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPCITABLES_FILECODE                  (0xCB8B)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERMGMTSYSTEMTABLES_FILECODE      (0xCB8C)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPOWERPLANE_FILECODE                 (0xCB8D)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMUTILITIES_FILECODE                  (0xCB8E)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMWORKAROUNDSTABLE_FILECODE           (0xCB8F)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMPMNBCOFVIDINIT_FILECODE             (0xCB90)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMLOWPWRPSTATE_FILECODE               (0xCB91)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMSINGLELINKPCITABLES_FILECODE        (0xCB92)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMMULTILINKPCITABLES_FILECODE         (0xCB93)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMC6STATE_FILECODE                    (0xCB94)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMCPB_FILECODE                        (0xCB95)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMIOCSTATE_FILECODE                   (0xCB96)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMCACHEFLUSHONHALT_FILECODE        (0xCB97)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMFEATURELEVELING_FILECODE         (0xCB98)
+#define PROC_CPU_FAMILY_0X15_KM_CPUF15KMSOFTWARETHERMAL_FILECODE         (0xCB99)
+#define PROC_CPU_FAMILY_0X15_KM_F15KMINITEARLYTABLE_FILECODE             (0xCB9A)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE                    (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE                           (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE                                 (0xDC10)
+#define PROC_CPU_FEATURE_CPUFEATURELEVELING_FILECODE                     (0xDC20)
+#define PROC_CPU_FEATURE_CPUL3FEATURES_FILECODE                          (0xDC30)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE                        (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE                      (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE                        (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE                                (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE                                (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE                                (0xDC70)
+#define PROC_CPU_FEATURE_CPUHWC1E_FILECODE                               (0xDC80)
+#define PROC_CPU_FEATURE_CPUSWC1E_FILECODE                               (0xDC81)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE                             (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE                                 (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE                        (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE                            (0xDC85)
+#define PROC_CPU_FEATURE_CPUPSTATEHPCMODE_FILECODE                       (0xDC86)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE                                 (0xDC87)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE                            (0xDC90)
+#define PROC_CPU_FEATURE_CPUMSGBASEDC1E_FILECODE                         (0xDCA0)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE                        (0xDCB0)
+#define PROC_CPU_FEATURE_PRESERVEMAILBOX_FILECODE                        (0xDCC0)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE                           (0xDE01)
+
+#define PROC_HT_FEATURES_HTFEATSETS_FILECODE                             (0xE001)
+#define PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE                 (0xE002)
+#define PROC_HT_FEATURES_HTFEATGANGING_FILECODE                          (0xE003)
+#define PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE                      (0xE004)
+#define PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE                     (0xE005)
+#define PROC_HT_FEATURES_HTFEATROUTING_FILECODE                          (0xE006)
+#define PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE                         (0xE007)
+#define PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE              (0xE008)
+#define PROC_HT_FEATURES_HTIDS_FILECODE                                  (0xE009)
+#define PROC_HT_HTFEAT_FILECODE                                          (0xE021)
+#define PROC_HT_HTINTERFACE_FILECODE                                     (0xE022)
+#define PROC_HT_HTINTERFACECOHERENT_FILECODE                             (0xE023)
+#define PROC_HT_HTINTERFACEGENERAL_FILECODE                              (0xE024)
+#define PROC_HT_HTINTERFACENONCOHERENT_FILECODE                          (0xE025)
+#define PROC_HT_HTMAIN_FILECODE                                          (0xE026)
+#define PROC_HT_HTNOTIFY_FILECODE                                        (0xE027)
+#define PROC_HT_HTGRAPH_HTGRAPH_FILECODE                                 (0xE028)
+#define PROC_HT_HTNB_FILECODE                                            (0xE081)
+#define PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE                           (0xE082)
+#define PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE                        (0xE083)
+#define PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE                       (0xE084)
+#define PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE                          (0xE085)
+#define PROC_HT_FAM10_HTNBFAM10_FILECODE                                 (0xE0C1)
+#define PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE                         (0xE0C2)
+#define PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE                      (0xE0C3)
+#define PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE                     (0xE0C4)
+#define PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE                           (0xE0C5)
+#define PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE                        (0xE0C6)
+#define PROC_HT_FAM12_HTNBFAM12_FILECODE                                 (0xE101)
+#define PROC_HT_FAM12_HTNBUTILITIESFAM12_FILECODE                        (0xE102)
+#define PROC_HT_FAM14_HTNBFAM14_FILECODE                                 (0xE141)
+#define PROC_HT_FAM14_HTNBUTILITIESFAM14_FILECODE                        (0xE142)
+#define PROC_HT_FAM15_HTNBFAM15_FILECODE                                 (0xE181)
+#define PROC_HT_FAM15_HTNBCOHERENTFAM15_FILECODE                         (0xE182)
+#define PROC_HT_FAM15_HTNBNONCOHERENTFAM15_FILECODE                      (0xE183)
+#define PROC_HT_FAM15_HTNBOPTIMIZATIONFAM15_FILECODE                     (0xE184)
+#define PROC_HT_FAM15_HTNBSYSTEMFAM15_FILECODE                           (0xE185)
+#define PROC_HT_FAM15_HTNBUTILITIESFAM15_FILECODE                        (0xE186)
+#define PROC_HT_FAM15MOD1X_HTNBFAM15MOD1X_FILECODE                       (0xE187)
+#define PROC_HT_FAM15MOD1X_HTNBUTILITIESFAM15MOD1X_FILECODE              (0xE188)
+#define PROC_HT_FAM14MOD1X_HTNBFAM14MOD1X_FILECODE                       (0xE189)
+#define PROC_HT_FAM14MOD1X_HTNBUTILITIESFAM14MOD1X_FILECODE              (0xE18A)
+#define PROC_HT_FAM15MOD2X_HTNBFAM15MOD2X_FILECODE                             (0xE191)
+#define PROC_HT_FAM15MOD2X_HTNBCOHERENTFAM15MOD2X_FILECODE                     (0xE192)
+#define PROC_HT_FAM15MOD2X_HTNBNONCOHERENTFAM15MOD2X_FILECODE                  (0xE193)
+#define PROC_HT_FAM15MOD2X_HTNBOPTIMIZATIONFAM15MOD2X_FILECODE                 (0xE194)
+#define PROC_HT_FAM15MOD2X_HTNBSYSTEMFAM15MOD2X_FILECODE                       (0xE195)
+#define PROC_HT_FAM15MOD2X_HTNBUTILITIESFAM15MOD2X_FILECODE                    (0xE196)
+
+#define PROC_RECOVERY_HT_HTINITRECOVERY_FILECODE                         (0xE302)
+#define PROC_RECOVERY_HT_HTINITRESET_FILECODE                            (0xE301)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE                                (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE                                 (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE                                 (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE                                   (0xE804)
+#define PROC_IDS_FAMILY_0X10_IDSF10ALLSERVICE_FILECODE                   (0xE805)
+#define PROC_IDS_FAMILY_0X10_BL_IDSF10BLSERVICE_FILECODE                 (0xE806)
+#define PROC_IDS_FAMILY_0X10_DA_IDSF10DASERVICE_FILECODE                 (0xE807)
+#define PROC_IDS_FAMILY_0X10_HY_IDSF10HYSERVICE_FILECODE                 (0xE808)
+#define PROC_IDS_FAMILY_0X10_RB_IDSF10RBSERVICE_FILECODE                 (0xE809)
+#define PROC_IDS_FAMILY_0X12_IDSF12ALLSERVICE_FILECODE                   (0xE80A)
+#define PROC_IDS_FAMILY_0X14_IDSF14ALLSERVICE_FILECODE                   (0xE80B)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE                   (0xE80C)
+#define PROC_IDS_FAMILY_0X14_KR_IDSF14KRALLSERVICE_FILECODE              (0xE80D)
+#define PROC_IDS_FAMILY_0X15_OR_IDSF15ORALLSERVICE_FILECODE              (0xE80E)
+#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE              (0xE80F)
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE                              (0xE810)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE                              (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE                            (0xE81F)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE                                    (0xF001)
+#define PROC_MEM_ARDK_DR_MARDR2_FILECODE                             (0xF002)
+#define PROC_MEM_ARDK_DR_MARDR3_FILECODE                             (0xF003)
+#define PROC_MEM_ARDK_HY_MARHY3_FILECODE                             (0xF004)
+#define PROC_MEM_ARDK_LN_MASLN3_FILECODE                             (0xF005)
+#define PROC_MEM_ARDK_DR_MAUDR3_FILECODE                             (0xF006)
+#define PROC_MEM_ARDK_HY_MAUHY3_FILECODE                             (0xF007)
+#define PROC_MEM_ARDK_LN_MAULN3_FILECODE                             (0xF008)
+#define PROC_MEM_ARDK_DA_MAUDA3_FILECODE                             (0xF009)
+#define PROC_MEM_ARDK_DA_MASDA2_FILECODE                             (0xF00A)
+#define PROC_MEM_ARDK_DA_MASDA3_FILECODE                             (0xF00B)
+#define PROC_MEM_ARDK_NI_MASNI3_FILECODE                             (0xF00C)
+#define PROC_MEM_ARDK_C32_MARC32_3_FILECODE                          (0xF00D)
+#define PROC_MEM_ARDK_C32_MAUC32_3_FILECODE                          (0xF00E)
+#define PROC_MEM_ARDK_NI_MAUNI3_FILECODE                             (0xF00F)
+#define PROC_MEM_ARDK_ON_MASON3_FILECODE                             (0xF010)
+#define PROC_MEM_ARDK_ON_MAUON3_FILECODE                             (0xF011)
+#define PROC_MEM_ARDK_PH_MASPH3_FILECODE                             (0xF012)
+#define PROC_MEM_ARDK_PH_MAUPH3_FILECODE                             (0xF013)
+#define PROC_MEM_ARDK_OR_MAROR3_FILECODE                             (0xF014)
+#define PROC_MEM_ARDK_OR_MAUOR3_FILECODE                             (0xF017)
+#define PROC_MEM_ARDK_RB_MASRB3_FILECODE                             (0xF018)
+#define PROC_MEM_ARDK_RB_MAURB3_FILECODE                             (0xF019)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE                         (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE                         (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE                             (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE                             (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE                (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE                   (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE                     (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE                       (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE                       (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE                         (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE                 (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE                         (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE             (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE             (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE                               (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE                           (0xF093)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE                                  (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE                                 (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE                                    (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE                             (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE                                 (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE                         (0xF106)
+#define PROC_MEM_MAIN_DR_MMFLOWDR_FILECODE                           (0xF107)
+#define PROC_MEM_MAIN_HY_MMFLOWHY_FILECODE                           (0xF108)
+#define PROC_MEM_MAIN_LN_MMFLOWLN_FILECODE                           (0xF109)
+#define PROC_MEM_MAIN_ON_MMFLOWON_FILECODE                           (0xF10A)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE                      (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE                         (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE                    (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE                    (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE                                   (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE                              (0xF110)
+#define PROC_MEM_MAIN_DA_MMFLOWDA_FILECODE                           (0xF111)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE                                (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE                               (0xF113)
+#define PROC_MEM_MAIN_C32_MMFLOWC32_FILECODE                         (0xF114)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE                              (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE                            (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE                          (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE                      (0xF118)
+#define PROC_MEM_MAIN_OR_MMFLOWOR_FILECODE                           (0xF119)
+#define PROC_MEM_MAIN_RB_MMFLOWRB_FILECODE                           (0xF11A)
+#define PROC_MEM_MAIN_PH_MMFLOWPH_FILECODE                           (0xF11B)
+#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE                           (0xF11C)
+#define PROC_MEM_MAIN_KR_MMFLOWKR_FILECODE                           (0xF11D)
+
+#define PROC_MEM_NB_DR_MNDR_FILECODE                                 (0XF213)
+#define PROC_MEM_NB_DR_MNFLOWDR_FILECODE                             (0XF214)
+#define PROC_MEM_NB_DR_MNIDENDIMMDR_FILECODE                         (0XF216)
+#define PROC_MEM_NB_DR_MNMCTDR_FILECODE                              (0XF217)
+#define PROC_MEM_NB_DR_MNDCTDR_FILECODE                              (0XF218)
+#define PROC_MEM_NB_DR_MNOTDR_FILECODE                               (0XF219)
+#define PROC_MEM_NB_DR_MNPARTRAINDR_FILECODE                         (0XF21A)
+#define PROC_MEM_NB_DR_MNPROTODR_FILECODE                            (0XF21C)
+#define PROC_MEM_NB_DR_MNS3DR_FILECODE                               (0XF21D)
+#define PROC_MEM_NB_DR_MNREGDR_FILECODE                              (0XF21E)
+#define PROC_MEM_NB_RB_MNRB_FILECODE                                 (0XF220)
+#define PROC_MEM_NB_RB_MNFLOWRB_FILECODE                             (0XF221)
+#define PROC_MEM_NB_RB_MNS3RB_FILECODE                               (0XF222)
+#define PROC_MEM_NB_RB_MNIDENDIMMRB_FILECODE                         (0XF223)
+#define PROC_MEM_NB_HY_MNFLOWHY_FILECODE                             (0XF233)
+#define PROC_MEM_NB_HY_MNHY_FILECODE                                 (0XF235)
+#define PROC_MEM_NB_HY_MNIDENDIMMHY_FILECODE                         (0XF236)
+#define PROC_MEM_NB_HY_MNMCTHY_FILECODE                              (0XF237)
+#define PROC_MEM_NB_HY_MNDCTHY_FILECODE                              (0XF238)
+#define PROC_MEM_NB_HY_MNOTHY_FILECODE                               (0XF239)
+#define PROC_MEM_NB_HY_MNPARTRAINHY_FILECODE                         (0XF23A)
+#define PROC_MEM_NB_HY_MNPHYHY_FILECODE                              (0XF23B)
+#define PROC_MEM_NB_HY_MNPROTOHY_FILECODE                            (0XF23C)
+#define PROC_MEM_NB_HY_MNS3HY_FILECODE                               (0XF23D)
+#define PROC_MEM_NB_HY_MNREGHY_FILECODE                              (0XF23E)
+#define PROC_MEM_NB_ON_MNON_FILECODE                                 (0xF240)
+#define PROC_MEM_NB_ON_MNREGON_FILECODE                              (0xF241)
+#define PROC_MEM_NB_ON_MNDCTON_FILECODE                              (0xF242)
+#define PROC_MEM_NB_ON_MNIDENDIMMON_FILECODE                         (0xF244)
+#define PROC_MEM_NB_ON_MNMCTON_FILECODE                              (0xF245)
+#define PROC_MEM_NB_ON_MNOTON_FILECODE                               (0xF246)
+#define PROC_MEM_NB_ON_MNPHYON_FILECODE                              (0xF247)
+#define PROC_MEM_NB_ON_MNS3ON_FILECODE                               (0xF248)
+#define PROC_MEM_NB_ON_MNFLOWON_FILECODE                             (0xF249)
+#define PROC_MEM_NB_ON_MNPROTOON_FILECODE                            (0xF24A)
+#define PROC_MEM_NB_LN_MNDCTLN_FILECODE                              (0XF252)
+#define PROC_MEM_NB_LN_MNFLOWLN_FILECODE                             (0XF253)
+#define PROC_MEM_NB_LN_MNIDENDIMMLN_FILECODE                         (0XF254)
+#define PROC_MEM_NB_LN_MNMCTLN_FILECODE                              (0XF255)
+#define PROC_MEM_NB_LN_MNOTLN_FILECODE                               (0XF256)
+#define PROC_MEM_NB_LN_MNPHYLN_FILECODE                              (0XF257)
+#define PROC_MEM_NB_LN_MNPROTOLN_FILECODE                            (0XF258)
+#define PROC_MEM_NB_LN_MNLN_FILECODE                                 (0XF259)
+#define PROC_MEM_NB_LN_MNS3LN_FILECODE                               (0XF25A)
+#define PROC_MEM_NB_LN_MNREGLN_FILECODE                              (0XF25B)
+#define PROC_MEM_NB_DA_MNDA_FILECODE                                 (0XF260)
+#define PROC_MEM_NB_DA_MNFLOWDA_FILECODE                             (0XF261)
+#define PROC_MEM_NB_DA_MNIDENDIMMDA_FILECODE                         (0XF263)
+#define PROC_MEM_NB_DA_MNMCTDA_FILECODE                              (0XF264)
+#define PROC_MEM_NB_DA_MNDCTDA_FILECODE                              (0XF265)
+#define PROC_MEM_NB_DA_MNOTDA_FILECODE                               (0XF266)
+#define PROC_MEM_NB_DA_MNPARTRAINDA_FILECODE                         (0XF267)
+#define PROC_MEM_NB_DA_MNPROTODA_FILECODE                            (0XF269)
+#define PROC_MEM_NB_DA_MNS3DA_FILECODE                               (0XF26A)
+#define PROC_MEM_NB_DA_MNREGDA_FILECODE                              (0XF26B)
+#define PROC_MEM_NB_C32_MNC32_FILECODE                               (0XF26C)
+#define PROC_MEM_NB_C32_MNDCTC32_FILECODE                            (0XF26D)
+#define PROC_MEM_NB_C32_MNFLOWC32_FILECODE                           (0XF26E)
+#define PROC_MEM_NB_C32_MNIDENDIMMC32_FILECODE                       (0XF26F)
+#define PROC_MEM_NB_C32_MNMCTC32_FILECODE                            (0XF270)
+#define PROC_MEM_NB_C32_MNOTC32_FILECODE                             (0XF271)
+#define PROC_MEM_NB_C32_MNPARTRAINC32_FILECODE                       (0XF272)
+#define PROC_MEM_NB_C32_MNPHYC32_FILECODE                            (0XF273)
+#define PROC_MEM_NB_C32_MNPROTOC32_FILECODE                          (0XF274)
+#define PROC_MEM_NB_C32_MNS3C32_FILECODE                             (0XF275)
+#define PROC_MEM_NB_C32_MNREGC32_FILECODE                            (0XF277)
+#define PROC_MEM_NB_MN_FILECODE                                      (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE                                   (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE                                   (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE                                   (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE                                    (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE                                  (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE                                  (0XF282)
+#define PROC_MEM_NB_MNTRAIN2_FILECODE                                (0XF283)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE                                (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE                                   (0XF285)
+#define PROC_MEM_NB_NI_MNNI_FILECODE                                 (0XF286)
+#define PROC_MEM_NB_NI_MNS3NI_FILECODE                               (0XF287)
+#define PROC_MEM_NB_NI_MNFLOWNI_FILECODE                             (0XF288)
+#define PROC_MEM_NB_PH_MNFLOWPH_FILECODE                             (0XF289)
+#define PROC_MEM_NB_PH_MNPH_FILECODE                                 (0XF28A)
+#define PROC_MEM_NB_PH_MNS3PH_FILECODE                               (0XF28B)
+#define PROC_MEM_NB_PH_MNIDENDIMMPH_FILECODE                         (0XF28C)
+#define PROC_MEM_NB_PH_MNMCTPH_FILECODE                              (0XF28D)
+#define PROC_MEM_NB_OR_MNFLOWOR_FILECODE                             (0XF290)
+#define PROC_MEM_NB_OR_MNOR_FILECODE                                 (0XF291)
+#define PROC_MEM_NB_OR_MNIDENDIMMOR_FILECODE                         (0XF292)
+#define PROC_MEM_NB_OR_MNMCTOR_FILECODE                              (0XF293)
+#define PROC_MEM_NB_OR_MNDCTOR_FILECODE                              (0XF294)
+#define PROC_MEM_NB_OR_MNOTOR_FILECODE                               (0XF295)
+#define PROC_MEM_NB_OR_MNPARTRAINOR_FILECODE                         (0XF296)
+#define PROC_MEM_NB_OR_MNPHYOR_FILECODE                              (0XF297)
+#define PROC_MEM_NB_OR_MNPROTOOR_FILECODE                            (0XF298)
+#define PROC_MEM_NB_OR_MNS3OR_FILECODE                               (0XF299)
+#define PROC_MEM_NB_OR_MNREGOR_FILECODE                              (0XF29A)
+#define PROC_MEM_NB_TN_MNREGTN_FILECODE                              (0XF29B)
+#define PROC_MEM_NB_TN_MNTN_FILECODE                                 (0XF29C)
+#define PROC_MEM_NB_TN_MNMCTTN_FILECODE                              (0XF29D)
+#define PROC_MEM_NB_TN_MNOTTN_FILECODE                               (0XF29E)
+#define PROC_MEM_NB_TN_MNDCTTN_FILECODE                              (0XF29F)
+#define PROC_MEM_NB_TN_MNPHYTN_FILECODE                              (0XF2A0)
+#define PROC_MEM_NB_TN_MNS3TN_FILECODE                               (0XF2A1)
+#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE                         (0XF2A2)
+#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE                             (0XF2A3)
+#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE                            (0XF2A4)
+#define PROC_MEM_NB_KR_MNREGKR_FILECODE                              (0xF2A5)
+#define PROC_MEM_NB_KR_MNDCTKR_FILECODE                              (0xF2A6)
+#define PROC_MEM_NB_KR_MNIDENDIMMKR_FILECODE                         (0xF2A7)
+#define PROC_MEM_NB_KR_MNMCTKR_FILECODE                              (0xF2A8)
+#define PROC_MEM_NB_KR_MNOTKR_FILECODE                               (0xF2A9)
+#define PROC_MEM_NB_KR_MNPHYKR_FILECODE                              (0xF2AA)
+#define PROC_MEM_NB_KR_MNS3KR_FILECODE                               (0xF2AB)
+#define PROC_MEM_NB_KR_MNFLOWKR_FILECODE                             (0xF2AC)
+#define PROC_MEM_NB_KR_MNPROTOKR_FILECODE                            (0xF2AD)
+#define PROC_MEM_NB_KR_MNKR_FILECODE                                 (0xF2AE)
+#define PROC_MEM_NB_KM_MNREGKM_FILECODE                              (0XF2AF)
+#define PROC_MEM_NB_KM_MNKM_FILECODE                                 (0XF2B0)
+#define PROC_MEM_NB_KM_MNMCTKM_FILECODE                              (0XF2B1)
+#define PROC_MEM_NB_KM_MNOTKM_FILECODE                               (0XF2B2)
+#define PROC_MEM_NB_KM_MNDCTKM_FILECODE                              (0XF2B3)
+#define PROC_MEM_NB_KM_MNPHYKM_FILECODE                              (0XF2B4)
+#define PROC_MEM_NB_KM_MNS3KM_FILECODE                               (0XF2B5)
+#define PROC_MEM_NB_KM_MNIDENDIMMKM_FILECODE                         (0XF2B6)
+#define PROC_MEM_NB_KM_MNFLOWKM_FILECODE                             (0XF2B7)
+#define PROC_MEM_NB_KM_MNPROTOKM_FILECODE                            (0XF2B8)
+
+
+#define PROC_MEM_PS_MP_FILECODE                                      (0XF401)
+#define PROC_MEM_PS_DR_MPRDR3_FILECODE                               (0XF402)
+#define PROC_MEM_PS_HY_MPRHY3_FILECODE                               (0XF403)
+#define PROC_MEM_PS_LN_MPRLN3_FILECODE                               (0XF404)
+#define PROC_MEM_PS_DR_MPSDR3_FILECODE                               (0XF405)
+#define PROC_MEM_PS_HY_MPSHY3_FILECODE                               (0XF406)
+#define PROC_MEM_PS_LN_MPSLN3_FILECODE                               (0XF407)
+#define PROC_MEM_PS_DR_MPUDR3_FILECODE                               (0XF408)
+#define PROC_MEM_PS_HY_MPUHY3_FILECODE                               (0XF409)
+#define PROC_MEM_PS_LN_MPULN3_FILECODE                               (0XF40A)
+#define PROC_MEM_PS_DA_MPUDA3_FILECODE                               (0XF40B)
+#define PROC_MEM_PS_DA_MPSDA2_FILECODE                               (0XF40C)
+#define PROC_MEM_PS_DA_MPSDA3_FILECODE                               (0XF40D)
+#define PROC_MEM_PS_DR_MPRDR2_FILECODE                               (0XF40E)
+#define PROC_MEM_PS_DR_MPUDR2_FILECODE                               (0XF40F)
+#define PROC_MEM_PS_C32_MPRC32_3_FILECODE                            (0XF410)
+#define PROC_MEM_PS_C32_MPUC32_3_FILECODE                            (0XF411)
+#define PROC_MEM_PS_NI_MPSNI3_FILECODE                               (0XF412)
+#define PROC_MEM_PS_NI_MPUNI3_FILECODE                               (0XF413)
+#define PROC_MEM_PS_ON_MPSON3_FILECODE                               (0XF414)
+#define PROC_MEM_PS_ON_MPUON3_FILECODE                               (0XF415)
+#define PROC_MEM_PS_PH_MPSPH3_FILECODE                               (0XF416)
+#define PROC_MEM_PS_PH_MPUPH3_FILECODE                               (0XF417)
+#define PROC_MEM_PS_RB_MPSRB3_FILECODE                               (0XF418)
+#define PROC_MEM_PS_RB_MPURB3_FILECODE                               (0XF419)
+#define PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE                          (0XF41A)
+#define PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE                          (0XF41B)
+#define PROC_MEM_PS_OR_C32_MPRORC3_FILECODE                          (0XF41C)
+#define PROC_MEM_PS_OR_C32_MPUORC3_FILECODE                          (0XF41D)
+#define PROC_MEM_PS_OR_C32_MPLORC3_FILECODE                          (0XF41E)
+#define PROC_MEM_PS_OR_G34_MPRORG3_FILECODE                          (0XF41F)
+#define PROC_MEM_PS_OR_G34_MPUORG3_FILECODE                          (0XF420)
+#define PROC_MEM_PS_OR_G34_MPLORG3_FILECODE                          (0XF421)
+#define PROC_MEM_PS_MPRTT_FILECODE                                   (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE                               (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE                                (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE                                   (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE                                   (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE                                (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE                             (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE                                 (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE                                 (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE                                 (0XF42B)
+#define PROC_MEM_PS_OR_MPOR3_FILECODE                                (0XF42C)
+#define PROC_MEM_PS_TN_MPSTN3_FILECODE                               (0XF42D)
+#define PROC_MEM_PS_TN_MPTN3_FILECODE                                (0XF42E)
+#define PROC_MEM_PS_TN_MPUTN3_FILECODE                               (0XF42F)
+#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE                         (0XF430)
+#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE                         (0XF431)
+#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE                         (0XF432)
+#define PROC_MEM_PS_KR_MPKR3_FILECODE                                (0XF433)
+#define PROC_MEM_PS_KR_MPUKR3_FILECODE                               (0XF434)
+#define PROC_MEM_PS_KR_MPSKR3_FILECODE                               (0XF435)
+#define PROC_MEM_PS_MPS___FILECODE                                   (0XF436)
+#define PROC_MEM_PS_KM_FM2_MPUKMFM2_FILECODE                         (0XF437)
+#define PROC_MEM_PS_KM_FM2_MPSKMFM2_FILECODE                         (0XF438)
+#define PROC_MEM_PS_KM_C2012_MPRKMC3_FILECODE                        (0XF439)
+#define PROC_MEM_PS_KM_C2012_MPUKMC3_FILECODE                        (0XF43A)
+#define PROC_MEM_PS_KM_C2012_MPLKMC3_FILECODE                        (0XF43B)
+#define PROC_MEM_PS_KM_G2012_MPRKMG3_FILECODE                        (0XF43C)
+#define PROC_MEM_PS_KM_G2012_MPUKMG3_FILECODE                        (0XF43D)
+#define PROC_MEM_PS_KM_G2012_MPLKMG3_FILECODE                        (0XF43E)
+#define PROC_MEM_PS_KM_MPKM3_FILECODE                                (0XF43F)
+#define PROC_MEM_PS_MPSEEDS_FILECODE                                 (0XF440)
+
+#define PROC_MEM_TECH_MT_FILECODE                                    (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE                                 (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE                              (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE                                (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE                                (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE                                 (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE                             (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE                                (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE                         (0XF50C)
+#define PROC_MEM_TECH_DDR2_MT2_FILECODE                              (0XF541)
+#define PROC_MEM_TECH_DDR2_MTOT2_FILECODE                            (0XF543)
+#define PROC_MEM_TECH_DDR2_MTSPD2_FILECODE                           (0XF544)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE                              (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE                            (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE                           (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE                           (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE                           (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE                           (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE                          (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE                        (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE                       (0XF58A)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE                             (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE                            (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE                               (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE                              (0XF804)
+#define PROC_RECOVERY_MEM_NB_DR_MRNDR_FILECODE                       (0XF812)
+#define PROC_RECOVERY_MEM_NB_DR_MRNMCTDR_FILECODE                    (0XF813)
+#define PROC_RECOVERY_MEM_NB_HY_MRNDCTHY_FILECODE                    (0XF821)
+#define PROC_RECOVERY_MEM_NB_HY_MRNHY_FILECODE                       (0XF822)
+#define PROC_RECOVERY_MEM_NB_HY_MRNMCTHY_FILECODE                    (0XF823)
+#define PROC_RECOVERY_MEM_NB_HY_MRNPROTOHY_FILECODE                  (0XF825)
+#define PROC_RECOVERY_MEM_NB_LN_MRNDCTLN_FILECODE                    (0XF831)
+#define PROC_RECOVERY_MEM_NB_LN_MRNMCTLN_FILECODE                    (0XF832)
+#define PROC_RECOVERY_MEM_NB_LN_MRNLN_FILECODE                       (0XF833)
+#define PROC_RECOVERY_MEM_NB_DA_MRNDA_FILECODE                       (0XF842)
+#define PROC_RECOVERY_MEM_NB_DA_MRNMCTDA_FILECODE                    (0XF843)
+#define PROC_RECOVERY_MEM_NB_NI_MRNNI_FILECODE                       (0XF845)
+#define PROC_RECOVERY_MEM_NB_C32_MRNC32_FILECODE                     (0XF851)
+#define PROC_RECOVERY_MEM_NB_C32_MRNMCTC32_FILECODE                  (0XF852)
+#define PROC_RECOVERY_MEM_NB_C32_MRNPROTOC32_FILECODE                (0XF853)
+#define PROC_RECOVERY_MEM_NB_ON_MRNDCTON_FILECODE                    (0xF861)
+#define PROC_RECOVERY_MEM_NB_ON_MRNMCTON_FILECODE                    (0xF862)
+#define PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE                       (0xF863)
+#define PROC_RECOVERY_MEM_NB_PH_MRNPH_FILECODE                       (0xF871)
+#define PROC_RECOVERY_MEM_NB_RB_MRNRB_FILECODE                       (0xF881)
+#define PROC_RECOVERY_MEM_NB_KR_MRNDCTKR_FILECODE                    (0xF891)
+#define PROC_RECOVERY_MEM_NB_KR_MRNMCTKR_FILECODE                    (0xF892)
+#define PROC_RECOVERY_MEM_NB_KR_MRNKR_FILECODE                       (0xF893)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE                      (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE                      (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE                    (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE                 (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE                 (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE                 (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE                 (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE                            (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE                         (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE                         (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE                      (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE                      (0XF8CC)
+#define PROC_RECOVERY_MEM_NB_OR_MRNDCTOR_FILECODE                    (0XF8CD)
+#define PROC_RECOVERY_MEM_NB_OR_MRNOR_FILECODE                       (0XF8CE)
+#define PROC_RECOVERY_MEM_NB_OR_MRNMCTOR_FILECODE                    (0XF8CF)
+#define PROC_RECOVERY_MEM_NB_OR_MRNPROTOOR_FILECODE                  (0XF8D0)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE                            (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE                         (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE                      (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE                         (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE                         (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE                      (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE                   (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE                       (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE                       (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE                       (0XF8E9)
+#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE                    (0XF8F3)
+#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE                       (0XF8F4)
+#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE                    (0XF8F5)
+#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE                  (0XF8F6)
+#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE                     (0XF8F7)
+#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE                      (0XF8F8)
+#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE                     (0XF8F9)
+#define PROC_RECOVERY_MEM_NB_KM_MRNDCTKM_FILECODE                    (0XF8FA)
+#define PROC_RECOVERY_MEM_NB_KM_MRNKM_FILECODE                       (0XF8FB)
+#define PROC_RECOVERY_MEM_NB_KM_MRNMCTKM_FILECODE                    (0XF8FC)
+#define PROC_RECOVERY_MEM_NB_KM_MRNPROTOKM_FILECODE                  (0XF8FD)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE             (0XF8FE)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
new file mode 100644
index 0000000..3b2bc80
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GeneralServices.h
@@ -0,0 +1,202 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components.  Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Common
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+  AGESA_STATUS EventClass;   ///< The severity of the event, its associated AGESA_STATUS.
+  UINT32   EventInfo;        ///< Uniquely identifies the event.
+  UINT32   DataParam1;       ///< Event specific additional data
+  UINT32   DataParam2;       ///< Event specific additional data
+  UINT32   DataParam3;       ///< Event specific additional data
+  UINT32   DataParam4;       ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Core         The Core id.
+ * @param[out]   ApicAddress  The Core's APIC ID.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, APIC Id valid
+ * @retval       FALSE        The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Core,
+     OUT   UINT8             *ApicAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[in]    Socket       The Core's Socket.
+ * @param[in]    Module       The Module in that Processor
+ * @param[out]   PciAddress   The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval       TRUE         The core is present, PCI Address valid
+ * @retval       FALSE        The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT32            Socket,
+  IN       UINT32            Module,
+     OUT   PCI_ADDR          *PciAddress,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in]    StdHeader    Header for library and services.
+ * @param[out]   Socket       The current Core's Socket
+ * @param[out]   Module       The current Core's Processor Module
+ * @param[out]   Core         The current Core's core id.
+ * @param[out]   AgesaStatus  Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+  IN       AMD_CONFIG_PARAMS *StdHeader,
+     OUT   UINT32            *Socket,
+     OUT   UINT32            *Module,
+     OUT   UINT32            *Core,
+     OUT   AGESA_STATUS      *AgesaStatus
+);
+
+/**
+ *  A boolean function determine executed CPU is BSP core.
+ */
+BOOLEAN
+IsBsp (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+     OUT   AGESA_STATUS      *AgesaStatus
+  );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+  IN       AGESA_STATUS EventClass,
+  IN       UINT32 EventInfo,
+  IN       UINT32 DataParam1,
+  IN       UINT32 DataParam2,
+  IN       UINT32 DataParam3,
+  IN       UINT32 DataParam4,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+     OUT   AGESA_EVENT *EventRecord,
+  IN       UINT16 Index,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#endif  // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h
new file mode 100644
index 0000000..ca53656
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbInterface.h
@@ -0,0 +1,100 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * GNB API definition.
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:     AGESA
+ * @e sub-project: GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+#ifndef _GNBINTERFACE_H_
+#define _GNBINTERFACE_H_
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT  AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS        *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
new file mode 100644
index 0000000..e4f89d8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbInterfaceStub.h
@@ -0,0 +1,301 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ *
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  GNB
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+*****************************************************************************
+*
+* Copyright (C) 2012 Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+*       its contributors may be used to endorse or promote products derived
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
+
+/*----------------------------------------------------------------------------------------
+ *                             M O D U L E S    U S E D
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                   D E F I N I T I O N S    A N D    M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *                  T Y P E D E F S     A N D     S T R U C T U  R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *           P R O T O T Y P E S     O F     L O C A L     F U  N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  );
+
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  );
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  );
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Reset Stub
+ *
+ *
+ *
+ * @param[in] StdHeader           Standard configuration header
+ * @retval    AGESA_SUCCESS       Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtReset (
+  IN      AMD_CONFIG_PARAMS       *StdHeader
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarly (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Default constructor of GNB configuration at Env
+ *
+ *
+ *
+ * @param[in] GnbEnvConfigPtr     Pointer to gnb env configuration params.
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+ */
+VOID
+GnbInitDataStructAtEnvDef (
+  IN OUT  GNB_ENV_CONFIGURATION   *GnbEnvConfigPtr,
+  IN      AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Env
+ *
+ *
+ *
+ * @param[in] EnvParamsPtr        Pointer to env configuration params.
+* @retval     AGESA_SUCCESS       Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEnv (
+  IN       AMD_ENV_PARAMS          *EnvParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post
+ *
+ *
+ *
+ * @param[in,out] PostParamsPtr    Pointer to Post configuration params.
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPost (
+  IN OUT  AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Mid post
+ *
+ *
+ *
+ * @param[in,out] MidParamsPtr    Pointer to mid configuration params.
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtMid (
+  IN OUT   AMD_MID_PARAMS          *MidParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Late post
+ *
+ *
+ *
+ * @param[in,out] LateParamsPtr     Pointer to late configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtLate (
+  IN OUT   AMD_LATE_PARAMS         *LateParamsPtr
+  )
+{
+
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * AmdGnbRecovery
+ *
+ *
+ *
+ * @param[in] StdHeader       Standard configuration header
+ * @retval    AGESA_SUCCESS   Always succeeds
+ */
+AGESA_STATUS
+AmdGnbRecovery (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Post after DRAM init
+ *
+ *
+ *
+ * @param[in]     PostParamsPtr   Pointer to post configuration parameters
+ * @retval        AGESA_SUCCESS   Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtPostAfterDram (
+  IN OUT   AMD_POST_PARAMS         *PostParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Init GNB at Early Before CPU Stub
+ *
+ *
+ *
+ * @param[in,out] EarlyParamsPtr    Pointer to early configuration params.
+ * @retval        AGESA_SUCCESS     Always succeeds
+ */
+
+AGESA_STATUS
+GnbInitAtEarlier (
+  IN OUT   AMD_EARLY_PARAMS        *EarlyParamsPtr
+  )
+{
+  return  AGESA_SUCCESS;
+}
diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
new file mode 100644
index 0000000..2ccdfc5
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h
@@ -0,0 +1,1972 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Create outline and references for GNB Component mainpage documentation.
+ *
+ * Design guides, maintenance guides, and general documentation, are
+ * collected using this file onto the documentation mainpage.
+ * This file contains doxygen comment blocks, only.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Documentation
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 01:16:51 -0800 (Wed, 22 Dec 2010) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/**
+ * @page gnbmain GNB Component Documentation
+ *
+ * Additional documentation for the GNB component consists of
+ *
+ * - Maintenance Guides:
+ *   - @subpage F12PcieLaneDescription    "Family 0x12 PCIe/DDI Lane description table"
+ *   - @subpage F14ONPcieLaneDescription  "Family 0x14(ON) PCIe/DDI Lane description table"
+ *   - @subpage F12LaneConfigurations     "Family 0x12 PCIe port/DDI link configurations"
+ *   - @subpage F14ONLaneConfigurations   "Family 0x14(ON) PCIe port/DDI link configurations"
+ *   - @subpage F12DualLinkDviDescription "Family 0x12 Dual Link DVI connector description"
+ *   - add here >>>
+ * - Design Guides:
+ *   - add here >>>
+ *
+ */
+
+
+/**
+ *  @page F12PcieLaneDescription Family 0x12 PCIe/DDI Lanes
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
+ *     <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 8 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 9 </TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][4]</TD></TR>
+ *     <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][5]</TD></TR>
+ *     <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][6]</TD></TR>
+ *     <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][7]</TD></TR>
+ *     <TR><TD class="indexvalue" > 16</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][8]</TD></TR>
+ *     <TR><TD class="indexvalue" > 17</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][9]</TD></TR>
+ *     <TR><TD class="indexvalue" > 18</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][10]</TD></TR>
+ *     <TR><TD class="indexvalue" > 19</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][11]</TD></TR>
+ *     <TR><TD class="indexvalue" > 20</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][12]</TD></TR>
+ *     <TR><TD class="indexvalue" > 21</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][13]</TD></TR>
+ *     <TR><TD class="indexvalue" > 22</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][14]</TD></TR>
+ *     <TR><TD class="indexvalue" > 23</TD><TD class="indexvalue">GFX</TD><TD class="indexvalue">P_GFX_RX[P/N]/TX[P/N][15]</TD></TR>
+ *     <TR><TD class="indexvalue" > 24</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 25</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 26</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 27</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 28</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 29</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 30</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 31</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
+ *  </TABLE>
+ *
+ */
+
+
+/**
+ *  @page F14ONPcieLaneDescription Family 0x14(ON) PCIe/DDI Lanes
+ *  <TABLE border="0">
+ *     <TR><TD class="indexkey" width=160> Lane ID</TD><TD class="indexkey">Lane group</TD><TD class="indexkey">Pin</TD></TR>
+ *     <TR><TD class="indexvalue" > 0 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 1 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 2 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 3 </TD><TD class="indexvalue">SB </TD><TD class="indexvalue">P_SB_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 4 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 5 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 6 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 7 </TD><TD class="indexvalue">GPP</TD><TD class="indexvalue">P_GPP_RX[P/N]/TX[P/N][3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 8</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 9</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 10</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 11</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP0_TXP/N[3]</TD></TR>
+ *     <TR><TD class="indexvalue" > 12</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[0]</TD></TR>
+ *     <TR><TD class="indexvalue" > 13</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[1]</TD></TR>
+ *     <TR><TD class="indexvalue" > 14</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[2]</TD></TR>
+ *     <TR><TD class="indexvalue" > 15</TD><TD class="indexvalue">DDI</TD><TD class="indexvalue">DP1_TXP/N[3]</TD></TR>
+ *  </TABLE>
+ *
+ */
+
+
+/**
+ *  @page F12DualLinkDviDescription Family 0x12 Dual Link DVI connector description
+ *  Examples of various Dual Link DVI descriptors.
+ *  @code
+ *  // Dual Link DVI on dedicated display lanes. DP1_TXP/N[0]..DP1_TXP/N[3] - master, DP0_TXP/N[0]..DP0_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave.
+ *  PCIe_PORT_DESCRIPTOR DdiList [] = {
+ *    {
+ *      DESCRIPTOR_TERMINATE_LIST,   //Descriptor flags
+ *      PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16),
+ *      PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0)
+ *    }
+ *  }
+ * @endcode
+ */
+
+/**
+ * @page F12LaneConfigurations Family 0x12 PCIe port/DDI link configurations
+ * <div class=WordSection1>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 8 through 23. </span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.25pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Configuration</p>
+ *   </td>
+ *   <td width=132 valign=top style='width:99.0pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=29 valign=top style='width:125.25pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Config A*</p>
+ *   </td>
+ *   <td width=132 rowspan=15 valign=top style='width:99.0pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>2</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'> </p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(9)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>9(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>10(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(10)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(13)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>13(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>14(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(14)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(17)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>17(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>18(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(18)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(21)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>21(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>22(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(22)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=132 rowspan=14 valign=top style='width:99.0pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>3</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'> </p>
+ *   </td>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(9)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>9(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>10(11)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11(10)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12(13)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>13(12)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>14(15)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(14)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:15.25pt'>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:15.25pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(17)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>17(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>18(19)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19(18)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20(21)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>21(20)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=180 valign=top style='width:135.0pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>22(23)</p>
+ *   </td>
+ *   <td width=162 valign=top style='width:121.5pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(22)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=641 colspan=4 valign=top style='width:480.75pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>* Lanes selection for port 2/3 should not overlap in port configuration</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 4 through 7.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(6)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6 or 7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link
+ * configurations for lanes 24 through 31.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:28.35pt'>
+ *   <td width=167 valign=top style='width:125.0pt;border-top:none;border-left:
+ *   solid windowtext 1.5pt;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>24(31)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:28.35pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>31(24)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=2 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>24</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>27</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>28</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>31</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>DDI link
+ * configurations for lanes 8 through 23.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:17.85pt'>
+ *   <td width=167 rowspan=2 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:17.85pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:16.5pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:16.5pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8(15)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:16.5pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15(8)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:93.0pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:93.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:18.3pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Dual Link DVI-D</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16(23)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:18.3pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23(16)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>20</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>23</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *  </div>
+ */
+
+/**
+ * @page F14ONLaneConfigurations Family 0x14(ON) PCIe port/DDI link configurations
+ * <div class=WordSection1>
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>PCIe port
+ * configurations for lane 4 through 7.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>PCIe Port Device Number</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 rowspan=3 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config B</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6(7)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7(6)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config C</p>
+ *   </td>
+ *   <td width=135 rowspan=2 valign=top style='width:100.9pt;border-top:none;
+ *   border-left:none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4(5)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5(4)</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5 or 6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6 or 7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=167 rowspan=4 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config D</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>4</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>5</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>6</p>
+ *   </td>
+ *  </tr>
+ *  <tr>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>7</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * <p class=MsoNormal><span style='font-size:14.0pt;line-height:115%'>CRT/DDI link
+ * configurations for lanes 8 through 19.</span></p>
+ *
+ * <table class=MsoTableGrid border=1 cellspacing=0 cellpadding=0
+ *  style='border-collapse:collapse;border:none'>
+ *  <tr>
+ *   <td width=167 valign=top style='width:125.0pt;border:solid windowtext 1.5pt;
+ *   background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Configuration</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Connector type</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Start Lane (Start Lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border:solid windowtext 1.5pt;
+ *   border-left:none;background:#C6D9F1;padding:0in 5.4pt 0in 5.4pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>End Line (End lane in reverse
+ *   configuration)</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=167 rowspan=3 valign=top style='width:125.0pt;border-top:none;
+ *   border-left:solid windowtext 1.5pt;border-bottom:solid black 1.0pt;
+ *   border-right:solid windowtext 1.5pt;padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>Config A</p>
+ *   </td>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-I*</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT </p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>8</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid black 1.0pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>11</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>HDMI</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-D</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Single Link DVI-I*</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>DP </p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>eDP</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-CRT</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Travis DP-to-LVDS</p>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>Hudson2 DP-to-CRT</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>12</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>15</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:95.0pt'>
+ *   <td width=135 valign=top style='width:100.9pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>CRT*</p>
+ *   </td>
+ *   <td width=179 valign=top style='width:134.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>16</p>
+ *   </td>
+ *   <td width=158 valign=top style='width:118.45pt;border-top:none;border-left:
+ *   none;border-bottom:solid windowtext 1.5pt;border-right:solid windowtext 1.5pt;
+ *   padding:0in 5.4pt 0in 5.4pt;height:95.0pt'>
+ *   <p class=MsoNormal align=center style='margin-bottom:0in;margin-bottom:.0001pt;
+ *   text-align:center;line-height:normal'>19</p>
+ *   </td>
+ *  </tr>
+ *  <tr style='height:35.85pt'>
+ *   <td width=638 colspan=4 valign=top style='width:6.65in;border:solid windowtext 1.5pt;
+ *   border-top:none;padding:0in 5.4pt 0in 5.4pt;height:35.85pt'>
+ *   <p class=MsoNormal style='margin-bottom:0in;margin-bottom:.0001pt;line-height:
+ *   normal'>* - Only one connector of this time can exist in configuration</p>
+ *   </td>
+ *  </tr>
+ * </table>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * <p class=MsoNormal> </p>
+ *
+ * </div>
+ */
diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h
new file mode 100644
index 0000000..b8d5091
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/Ids.h
@@ -0,0 +1,1178 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 55079 $   @e \$Date: 2011-06-16 03:48:27 -0600 (Thu, 16 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+  /* Macros to aid debugging */
+  /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE  1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS;  ///< Status of IDS function.
+#define IDS_SUCCESS         ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED     ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+  #define IDS_DEADLOOP()    { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ *  IDS Option Hook Points
+ *
+ *  These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum {                        //vv- for debug reference only
+  IDS_INIT_EARLY_BEFORE,              ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+                                          ///<   IDS Object is initialized.
+                                          ///<   Override CPU Core Leveling Mode.
+                                          ///<   Set P-State in Post
+  IDS_INIT_EARLY_AFTER,               ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+  IDS_INIT_LATE_BEFORE,               ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+                                          ///< It will be used to control the following tables.
+                                          ///<   ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+                                          ///<   ACPI SRAT Table
+                                          ///<   ACPI SLIT Table
+                                          ///<   ACPI WHEA Table
+                                          ///<   DMI Table
+  IDS_INIT_LATE_AFTER,                ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+  IDS_INIT_MID_BEFORE,                ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+  IDS_INIT_MID_AFTER,                 ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+  IDS_INIT_POST_BEFORE,               ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+                                          ///<   Control Interleaving and DRAM memory hole
+                                          ///<   Override the setting of ECC Control
+                                          ///<   Override the setting of Online Spare Rank
+  IDS_INIT_POST_AFTER,                ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_INIT_RESET_BEFORE,              ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+  IDS_INIT_RESET_AFTER,               ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+  IDS_INIT_POST_MID,                  ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+  IDS_BEFORE_S3_SAVE,                 ///< 0b override any settings before S3 save.
+  IDS_BEFORE_S3_RESTORE,              ///< 0c  override any settings before S3 restore
+  IDS_AFTER_S3_SAVE,                  ///< 0d Override any settings after S3 save
+  IDS_AFTER_S3_RESTORE,               ///< 0e Override any settings after S3 restore
+  IDS_BEFORE_DQS_TRAINING,            ///< 0f override any settings before DQS training
+  IDS_BEFORE_DRAM_INIT,               ///< 10 override any settings before Dram initialization
+  IDS_BEFORE_MEM_FREQ_CHG,            ///< 11 override settings before MemClk frequency change
+  IDS_BEFORE_WARM_RESET ,             ///< 12 Override PCI or MSR Registers Before Warm Reset
+  IDS_BEFORE_PCI_INIT,                ///< 13 Override PCI or MSR Registers Before PCI Init
+  IDS_BEFORE_AP_EARLY_HALT,           ///< 14 Option Hook Point before AP early halt
+  IDS_BEFORE_S3_RESUME,               ///< 15 Option Hook Point before s3 resume
+  IDS_AFTER_S3_RESUME,                ///< 16 Option Hook Point after s3 resume
+  IDS_BEFORE_PM_INIT,                 ///< 17 Option Hook Point Before Pm Init
+
+  IDS_MT_BASE = 0x20,                 ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+  IDS_PLATFORM_RSVD1 = 0x38,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD2 = 0x39,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD3 = 0x3a,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD4 = 0x3b,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD5 = 0x3c,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD6 = 0x3d,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD7 = 0x3e,          ///< from 0x38 to 0x3f will reserved for platform used
+  IDS_PLATFORM_RSVD8 = 0x3f,          ///< from 0x38 to 0x3f will reserved for platform used
+
+  // All the above timing point is used by BVM, their value should never be changed
+  IDS_HT_CONTROL,                     ///< 40 Override the setting of HT Link Control
+  IDS_HT_TRISTATE,                    ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
+  IDS_INIT_DRAM_TABLE,                ///< 42 Generate override table for Dram Timing
+                                          ///< Dram Controller, Drive Strength and DQS Timing
+  IDS_GET_DRAM_TABLE,                 ///< 43 Generate override table for Dram Timing
+  IDS_GANGING_MODE,                   ///< 44 override Memory Mode Unganged
+  IDS_POWERDOWN_MODE,                 ///< 45 override Power Down Mode
+  IDS_BURST_LENGTH32,                 ///< 46 override Burst Length32
+  IDS_ALL_MEMORY_CLOCK,               ///< 47 override All Memory Clks Enable
+  IDS_ECC,                            ///< 48 override ECC parameter
+  IDS_ECCSYMBOLSIZE,                  ///< 49 override ECC symbol size
+  IDS_CPU_Early_Override,             ///< 4a override CPU early parameter
+  IDS_CACHE_FLUSH_HLT,                ///< 4b override Cache Flush Hlt
+  IDS_CHANNEL_INTERLEAVE,             ///< 4c override Channel Interleave
+  IDS_MEM_ERROR_RECOVERY,             ///< 4d override memory error recovery
+  IDS_MEM_RETRAIN_TIMES,              ///< 4e override memory retrain times
+  IDS_MEM_SIZE_OVERLAY,               ///< 4f Override the syslimit
+  IDS_HT_ASSIST,                      ///< 50 Override Probe Filter
+  IDS_CHECK_NEGATIVE_WL,              ///< 51 Check for negative write leveling result
+  IDS_DLL_SHUT_DOWN,                  ///< 52 Check for Dll Shut Down
+  IDS_POR_MEM_FREQ,                   ///< 53 Entry to enable/disable MemClk frequency enforcement
+  IDS_PHY_DLL_STANDBY_CTRL,           ///< 54 Enable/Disable Phy DLL standby feature
+  IDS_PLATFORMCFG_OVERRIDE,           ///< 55 Hook for Override PlatformConfig structure
+  IDS_LOADCARD_ERROR_RECOVERY,        ///< 56 Special error handling for load card support
+  IDS_MEM_IGNORE_ERROR,               ///< 57 Ignore error and do not do fatal exit in memory
+  IDS_GNB_SMU_SERVICE_CONFIG,         ///< 58 Config GNB SMU service
+  IDS_GNB_ORBDYNAMIC_WAKE,            ///< 59 config GNB dynamic wake
+  IDS_GNB_PLATFORMCFG_OVERRIDE,       ///< 5a override ids gnb platform config
+  IDS_GNB_LCLK_DPM_EN,                ///< 5b override GNB LCLK DPM configuration
+  IDS_GNB_LCLK_DEEP_SLEEP,            ///< 5c override GNB LCLK DPM deep sleep
+  IDS_GNB_CLOCK_GATING,               ///< 5d Override GNB Clock gating config
+  IDS_NB_PSTATE_DIDVID,               ///< 5e Override NB P-state settings
+  IDS_CPB_CTRL,                       ///< 5f Config the Core peformance boost feature
+  IDS_HTC_CTRL,                       ///< 60 Hook for Hardware Thermal Control
+  IDS_CC6_WORKAROUND,                 ///< 61 Hook for skip CC6 work around
+  IDS_MEM_MR0,                        ///< 62 Hook for override Memory Mr0 register
+  IDS_REG_TABLE,                      ///< 63 Hook for add IDS register table to the loop
+  IDS_NBBUFFERALLOCATIONATEARLY,      ///< 64 Hook for override North bridge bufer allocation
+  IDS_BEFORE_S3_SPECIAL,              ///< 65 Hook to bypass S3 special functions
+  IDS_SET_PCI_REGISTER_ENTRY,         ///< 66 Hook to SetRegisterForPciEntry
+  IDS_ERRATUM463_WORKAROUND,          ///< 67 Hook to Erratum 463 workaround
+  IDS_BEFORE_MEMCLR,                  ///< 68 Hook before set Memclr bit
+  IDS_OVERRIDE_IO_CSTATE,             ///< 69 Hook for override io C-state setting
+  IDS_NBPSDIS_OVERRIDE,               ///< 6a Hook for override NB pstate disable setting
+  IDS_NBPS_REG_OVERRIDE,              ///< 6b Hook for override Memory NBps reg
+  IDS_LOW_POWER_PSTATE,               ///< 6c Hook for disalbe Low power_Pstates feature
+  IDS_CST_CREATE,                     ///< 6d Hook for create _CST
+  IDS_CST_SIZE,                       ///< 6e Hook for get _CST size
+  IDS_ENFORCE_VDDIO,                  ///< 6f Hook to override VDDIO
+  IDS_STRETCH_FREQUENCY_LIMIT,        ///< 70 Hook for enforcing memory stretch frequency limit
+  IDS_INIT_MEM_REG_TABLE,             ///< 71 Hook for init memory register table
+  IDS_SKIP_FUSED_MAX_RATE,            ///< 72 Hook to skip fused max rate cap
+  IDS_FCH_INIT_AT_RESET,              ///< 73 Hook for FCH reset parameter
+  IDS_FCH_INIT_AT_ENV,                ///< 74 Hook for FCH ENV parameter
+  IDS_ENFORCE_PLAT_TABLES,            ///< 75 Hook to enforce platform specific tables
+  IDS_NBPS_MIN_FREQ,                  ///< 76 Hook for override MIN nb ps freq
+  IDS_GNB_FORCE_CABLESAFE,            ///< 77 Hook for override Force Cable Safe
+  IDS_SKIP_PM_TRANSITION_STEP,        ///< 78 Hook for provide IDS ability to skip this PM step
+  IDS_GNB_PROPERTY,                   ///< 79 Hook for GNB Property
+  IDS_GNB_PCIE_POWER_GATING,          ///< 7A Hook for GNB PCIe Power Gating
+  IDS_MEM_DYN_DRAM_TERM,              ///< 7B Hook for Override Dynamic Dram Term
+  IDS_MEM_DRAM_TERM,                  ///< 7C Hook for Override Dram Term
+  IDS_TRACE_MODE,                     ///< 7D Trace Mode
+  IDS_GNB_ALTVDDNB,                   ///< 7E Hook for Override AltVddNB
+  IDS_UCODE,                          ///< 7F Enable or Disable microcode patching
+  IDS_FAM_REG_GMMX,                   ///< 80 GMMX register access
+  IDS_MEMORY_POWER_POLICY,            ///< 81 Memory power policy
+  IDS_GET_STRETCH_FREQUENCY_LIMIT,    ///< 82 Hook for enforcing memory stretch frequency limit
+  IDS_CPU_FEAT,                       ///< 83 Hook for runtime force cpu feature disable
+  IDS_OPTION_END,                     ///< 84 End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+  #define IDSOPT_IDS_ENABLED        FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+  #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+  #define IDSOPT_TRACING_ENABLED    FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+  #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+  #define IDSOPT_HEAP_CHECKING           FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+  #define IDSOPT_ASSERT_ENABLED         FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+  #define IDSOPT_DEBUG_CODE_ENABLED   FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+  #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+  #define IDSOPT_C_OPTIMIZATION_DISABLED   FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef  IDSOPT_CONTROL_ENABLED
+  #undef  IDSOPT_TRACING_ENABLED
+  #undef  IDSOPT_PERF_ANALYSIS
+  #undef  IDSOPT_HEAP_CHECKING
+  #undef  IDSOPT_ASSERT_ENABLED
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #undef  IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+  #undef  IDSOPT_DEBUG_CODE_ENABLED
+  #undef  IDSOPT_TRACE_USER_OPTIONS
+
+  #define IDSOPT_CONTROL_ENABLED    FALSE
+  #define IDSOPT_TRACING_ENABLED    FALSE
+  #define IDSOPT_PERF_ANALYSIS      FALSE
+  #define IDSOPT_HEAP_CHECKING      FALSE
+  #define IDSOPT_ASSERT_ENABLED     FALSE
+  #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+  #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+  #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+  #define IDSOPT_TRACE_USER_OPTIONS FALSE
+#endif
+
+/**
+ *  Make a Progress Report to the User.
+ *
+ *  This Macro is always enabled. The default action is to write the TestPoint value
+ *  to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ *  IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ *  in OptionsIds.h in their build tip.
+ *
+ *  @param[in]      TestPoint       The value for display indicating progress
+ *  @param[in,out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader)
+
+#ifndef IDS_DEBUG_PORT
+  #define IDS_DEBUG_PORT  0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ *  (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ *  Causes the program to halt and display the file number of the source of the
+ *  halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+  #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+  #define STOP_HERE  STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ *  Test an assertion that the given statement is True.
+ *
+ *  The statement is evaluated to a boolean value. If the statement is True,
+ *  then no action is taken (no error). If the statement is False, a error stop
+ *  is generated to halt the program. Used for testing for fatal errors that
+ *  must be resolved before production. This is used to do parameter checks,
+ *  bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in]   conditional    Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+  #if IDSOPT_ASSERT_ENABLED == TRUE
+    #ifdef STOP_CODE
+      #undef STOP_CODE
+    #endif
+    #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                        ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                        (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+    #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+  #else
+    #define ASSERT(conditional)
+  #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+  #undef  IDSOPT_ERROR_TRAP_ENABLED
+  #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#else
+  #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+
+#ifndef DEBUG_CODE
+  #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+    #define  DEBUG_CODE(Code)
+  #else
+    #define  DEBUG_CODE(Code)
+  #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+  #ifdef STOP_CODE
+    #undef STOP_CODE
+  #endif
+  #define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
+                      ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+                      (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+  #define IDS_ERROR_TRAP  IdsErrorStop (STOP_CODE)
+#else
+  #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+  #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+  #define IDS_INITIAL_F10_PM_STEP
+  #define IDS_INITIAL_F12_PM_STEP
+  #define IDS_INITIAL_F14_PM_STEP
+  #define IDS_INITIAL_F15_OR_PM_STEP
+  #define IDS_INITIAL_F15_TN_PM_STEP
+  #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+  #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+  #define IDS_EXTENDED_HEAP_SIZE 0
+  #define IDS_EXT_INCLUDE_F10(file)
+  #define IDS_EXT_INCLUDE_F12(file)
+  #define IDS_EXT_INCLUDE_F14(file)
+  #define IDS_EXT_INCLUDE_F15(file)
+  #define IDS_EXT_INCLUDE(file)
+  #define IDS_PAD_4K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+  #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
+  #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+    #undef IDS_AP_GET_NV_FROM_CMOS
+    #define IDS_AP_GET_NV_FROM_CMOS(x)
+    #ifdef IDS_OPT_CMOS_INDEX_PORT
+      #undef IDS_CMOS_INDEX_PORT
+      #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_DATA_PORT
+      #undef IDS_CMOS_DATA_PORT
+      #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_START
+      #undef IDS_CMOS_REGION_START
+      #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+    #endif
+
+    #ifdef IDS_OPT_CMOS_REGION_END
+      #undef IDS_CMOS_REGION_END
+      #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+    #endif
+  #endif
+#else
+  #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+  #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
+#endif
+
+/**
+ *  Macro to add a *skip* hook for IDS options
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, IDS dispatcher function will be called to perform
+ *  the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in]       IdsOption       IDS Option ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#else
+  #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ *  Macro to add a heap manager routine
+ *
+ *  when memory is allocated the heap manager actually allocates two extra dwords of data,
+ *  one dword buffer before the actual memory, and one dword afterwards.
+ *  a complete heap walk and check to be performed at any time.
+ *  it would ASSERT if the heap is corrupt
+ *
+ * @param[in]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548    // "Head"
+#define SENTINEL_AFTER_VALUE  0x6C696154    // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_HEAP_CHECKING == TRUE
+    #define SIZE_OF_SENTINEL  4
+    #define NUM_OF_SENTINEL   2             // Before ("Head") and After ("Tail")
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+    #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+    #define Heap_Check(stdheader)
+  #else
+    #define SIZE_OF_SENTINEL  0
+    #define NUM_OF_SENTINEL   0
+    #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+    #define SET_SENTINEL_AFTER(NodePtr)
+    #define Heap_Check(stdheader)
+  #endif
+#else
+  #define SIZE_OF_SENTINEL    0
+  #define NUM_OF_SENTINEL     0
+  #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+  #define SET_SENTINEL_AFTER(NodePtr)
+  #define Heap_Check(stdheader)
+#endif
+
+/**
+ *  Macro to add IDT for debugging exception.
+ *
+ *  A debug feature. Adding a 'jmp $' into every exception handler.
+ *  So debugger could use HDT to skip 'jmp $' and execute the iret,
+ *  then they could find which instruction cause the exception.
+ *
+ * @param[in]       FunctionId      IDS Function ID for this hook point
+ * @param[in, out]  DataPtr         Data Pointer to override
+ * @param[in, out]  StdHeader       Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+  #else
+    #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+  #endif
+#else
+  #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+
+
+/**
+ *  Macro to add HDT OUT
+ *
+ *  The default minimal action is to do nothing and there is no any code to increase.
+ *  For debug environments, the debug information can be displayed in HDT or other
+ *  devices.
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+  #if IDSOPT_TRACING_ENABLED == TRUE
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+
+      #ifdef __GNUC__
+        #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL
+		/* print all*/
+		//#define IDS_HDT_CONSOLE(f, s, args...) do {do_printk(BIOS_DEBUG, s, ##args);} while (0)
+		#define IDS_HDT_CONSOLE(f, s, args...) do {\
+			if (f == MAIN_FLOW) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == MEM_FLOW) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == CPU_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == HT_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == GNB_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			} else if (f == FCH_TRACE) {\
+				do_printk(BIOS_DEBUG, s, ##args);\
+			}\
+		} while(0)
+        #else
+        #define IDS_HDT_CONSOLE(s, args...) do {} while(0)
+        #endif
+        #else
+     #define IDS_HDT_CONSOLE(s, args...)
+    #endif
+
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR        NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    //#define CONSOLE(s, ...)
+  #else
+    #define IDS_HDT_CONSOLE_INIT(x)
+    #define IDS_HDT_CONSOLE_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_EXIT(x)
+    #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+    #define IDS_HDT_CONSOLE(f, s, ...)
+    #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+    #define IDS_HDT_CONSOLE_ASSERT(x)
+    #define IDS_FUNCLIST_ADDR                 NULL
+    #define IDS_FUNCLIST_EXTERN()
+    #define IDS_TIMEOUT_CTL(t)
+    #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+    //#define CONSOLE(s, ...)        CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+  #endif
+#else
+  #define IDS_HDT_CONSOLE_INIT(x)
+  #define IDS_HDT_CONSOLE_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_EXIT(x)
+  #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+  #define IDS_HDT_CONSOLE(f, s, ...)
+  #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+  #define IDS_HDT_CONSOLE_ASSERT(x)
+  #define IDS_FUNCLIST_ADDR                   NULL
+  #define IDS_FUNCLIST_EXTERN()
+  #define IDS_TIMEOUT_CTL(t)
+  #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+//  #define CONSOLE(s, ...)        CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG  IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#else
+  #define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
+  #define IDS_PERF_ANALYSE(StdHeader)
+  #define IDS_PERF_TIME_MEASURE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL  0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY    TRUE
+#define IDS_ALL_CORES   FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID     PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT      0x01                             ///< The function data of IDS callout function of initialization.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+  UINT32  FuncAddr;       ///< Function address in ROM
+  CHAR8   FuncName[40];   ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+  IN BOOLEAN CfgEccRedirection;                   ///< ECC Redirection
+  IN UINT16  CfgScrubDramRate;                    ///< Scrub Dram Rate
+  IN UINT16  CfgScrubL2Rate;                      ///< Scrub L2Rate
+  IN UINT16  CfgScrubL3Rate;                      ///< Scrub L3Rate
+  IN UINT16  CfgScrubIcRate;                      ///< Scrub Ic Rate
+  IN UINT16  CfgScrubDcRate;                      ///< Scrub Dc Rate
+  IN BOOLEAN CfgEccSyncFlood;                     ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ *  AGESA Test Points
+ *
+ *  These are the values displayed to the user to indicate progress through boot.
+ *  These can be used in a debug environment to stop the debugger at a specific
+ *  test point:
+ *  For SimNow!, this command
+ *      bi 81 w vb 49
+ *  will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+  StartProcessorTestPoints,           ///< 00 Entry used for range testing for @b Processor related TPs
+
+  // Memory test points
+  TpProcMemBeforeMemDataInit,         ///< 01 .. Memory structure initialization (Public interface)
+  TpProcMemBeforeSpdProcessing,       ///< 02 .. SPD Data processing  (Public interface)
+  TpProcMemAmdMemAuto,                ///< 03 .. Memory configuration  (Public interface)
+  TpProcMemDramInit,                  ///< 04 .. DRAM initialization
+  TpProcMemSPDChecking,               ///< 05 ..
+  TpProcMemModeChecking,              ///< 06 ..
+  TpProcMemSpeedTclConfig,            ///< 07 .. Speed and TCL configuration
+  TpProcMemSpdTiming,                 ///< 08 ..
+  TpProcMemDramMapping,               ///< 09 ..
+  TpProcMemPlatformSpecificConfig,    ///< 0A ..
+  TPProcMemPhyCompensation,           ///< 0B ..
+  TpProcMemStartDcts,                 ///< 0C ..
+  TpProcMemBeforeDramInit,            ///< 0D .. (Public interface)
+  TpProcMemPhyFenceTraining,          ///< 0E ..
+  TpProcMemSynchronizeDcts,           ///< 0F ..
+  TpProcMemSystemMemoryMapping,       ///< 10 ..
+  TpProcMemMtrrConfiguration,         ///< 11 ..
+  TpProcMemDramTraining,              ///< 12 ..
+  TpProcMemBeforeAnyTraining,         ///< 13 .. (Public interface)
+  TpProcMemWriteLevelizationTraining, ///< 14 ..
+  TpProcMemWlFirstPass,               ///< 15 .. Below 800Mhz first pass start
+  TpProcMemWlSecondPass,              ///< 16 .. Above 800Mhz second pass start
+  TpProcMemWlTrainTargetDimm,         ///< 17 .. Target DIMM configured
+  TpProcMemWlPrepDimms,               ///< 18 ..  Prepare DIMMS for WL
+  TpProcMemWlConfigDimms,             ///< 19 ..  Configure DIMMS for WL
+  TpProcMemReceiverEnableTraining,    ///< 1A ..
+  TpProcMemRcvrStartSweep,            ///< 1B .. Start sweep loop
+  TpProcMemRcvrSetDelay,              ///< 1C .. Set receiver Delay
+  TpProcMemRcvrWritePattern,          ///< 1D .. Write test pattern
+  TpProcMemRcvrReadPattern,           ///< 1E .. Read test pattern
+  TpProcMemRcvrTestPattern,           ///< 1F .. Compare test pattern
+  TpProcMemRcvrCalcLatency,           ///< 20 .. Calculate MaxRdLatency per channel
+  TpProcMemReceiveDqsTraining,        ///< 21 ..
+  TpProcMemRcvDqsSetDelay,            ///< 22 .. Set Write Data delay
+  TpProcMemRcvDqsWritePattern,        ///< 23 .. Write test pattern
+  TpProcMemRcvDqsStartSweep,          ///< 24 .. Start read sweep
+  TpProcMemRcvDqsSetRcvDelay,         ///< 25 .. Set Receive DQS delay
+  TpProcMemRcvDqsReadPattern,         ///< 26 .. Read Test pattern
+  TpProcMemRcvDqsTstPattern,          ///< 27 .. Compare Test pattern
+  TpProcMemRcvDqsResults,             ///< 28 .. Update results
+  TpProcMemRcvDqsFindWindow,          ///< 29 .. Start Find passing window
+  TpProcMemTransmitDqsTraining,       ///< 2A ..
+  TpProcMemTxDqStartSweep,            ///< 2B .. Start write sweep
+  TpProcMemTxDqSetDelay,              ///< 2C .. Set Transmit DQ delay
+  TpProcMemTxDqWritePattern,          ///< 2D .. Write test pattern
+  TpProcMemTxDqReadPattern,           ///< 2E .. Read Test pattern
+  TpProcMemTxDqTestPattern,           ///< 2F .. Compare Test pattern
+  TpProcMemTxDqResults,               ///< 30 .. Update results
+  TpProcMemTxDqFindWindow,            ///< 31 .. Start Find passing window
+  TpProcMemMaxRdLatencyTraining,      ///< 32 ..
+  TpProcMemMaxRdLatStartSweep,        ///< 33 .. Start sweep
+  TpProcMemMaxRdLatSetDelay,          ///< 34 .. Set delay
+  TpProcMemMaxRdLatWritePattern,      ///< 35 .. Write test pattern
+  TpProcMemMaxRdLatReadPattern,       ///< 36 .. Read Test pattern
+  TpProcMemMaxRdLatTestPattern,       ///< 37 .. Compare Test pattern
+  TpProcMemOnlineSpareInit,           ///< 38 .. Online Spare init
+  TpProcMemBankInterleaveInit,        ///< 39 .. Bank Interleave Init
+  TpProcMemNodeInterleaveInit,        ///< 3A .. Node Interleave Init
+  TpProcMemChannelInterleaveInit,     ///< 3B .. Channel Interleave Init
+  TpProcMemEccInitialization,         ///< 3C .. ECC initialization
+  TpProcMemPlatformSpecificInit,      ///< 3D .. Platform Specific Init
+  TpProcMemBeforeAgesaReadSpd,        ///< 3E .. Before callout for "AgesaReadSpd"
+  TpProcMemAfterAgesaReadSpd,         ///< 3F .. After callout for "AgesaReadSpd"
+  TpProcMemBeforeAgesaHookBeforeDramInit,    ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeDramInit,     ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemAfterAgesaHookBeforeDQSTraining,  ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+  TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterAgesaHookBeforeExitSelfRef,  ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+  TpProcMemAfterMemDataInit,          ///< 46 .. After MemDataInit
+  TpProcMemInitializeMCT,             ///< 47 .. Before InitializeMCT
+  TpProcMemLvDdr3,                    ///< 48 .. Before LV DDR3
+  TpProcMemInitMCT,                   ///< 49 .. Before InitMCT
+  TpProcMemOtherTiming,               ///< 4A.. Before OtherTiming
+  TpProcMemUMAMemTyping,              ///< 4B .. Before UMAMemTyping
+  TpProcMemSetDqsEccTmgs,             ///< 4C .. Before SetDqsEccTmgs
+  TpProcMemMemClr,                    ///< 4D .. Before MemClr
+  TpProcMemOnDimmThermal,             ///< 4E .. Before On DIMM Thermal
+  TpProcMemDmi,                       ///< 4F .. Before DMI
+  TpProcMemEnd,                       ///< 50 .. End of memory code
+
+  // CPU test points
+  TpProcCpuEntryDmi,                  ///< 51 .. Entry point CreateDmiRecords
+  TpProcCpuEntryPstate,               ///< 52 .. Entry point GenerateSsdt
+  TpProcCpuEntryPstateLeveling,       ///< 53 .. Entry point PStateLeveling
+  TpProcCpuEntryPstateGather,         ///< 54 .. Entry point PStateGatherData
+  TpProcCpuEntryWhea,                 ///< 55 .. Entry point CreateAcpiWhea
+  TpProcCpuEntrySrat,                 ///< 56 .. Entry point CreateAcpiSrat
+  TpProcCpuEntrySlit,                 ///< 57 .. Entry point CreateAcpiSlit
+  TpProcCpuProcessRegisterTables,     ///< 58 .. Register table processing
+  TpProcCpuSetBrandID,                ///< 59 .. Set brand ID
+  TpProcCpuLocalApicInit,             ///< 5A .. Initialize local APIC
+  TpProcCpuLoadUcode,                 ///< 5B .. Load microcode patch
+  TpProcCpuBeforePMFeatureInit,       ///< 5C .. BeforePM feature dispatch point
+  TpProcCpuPowerMgmtInit,             ///< 5D .. Power Management table processing
+  TpProcCpuEarlyFeatureInit,          ///< 5E .. Early feature dispatch point
+  TpProcCpuCoreLeveling,              ///< 5F .. Core Leveling
+  TpProcCpuApMtrrSync,                ///< 60 .. AP MTRR sync up
+  TpProcCpuPostFeatureInit,           ///< 61 .. POST feature dispatch point
+  TpProcCpuFeatureLeveling,           ///< 62 .. CPU Feature Leveling
+  TpProcCpuBeforeRelinquishAPsFeatureInit,   ///< 63 .. Before Relinquishing control of APs feature dispatch point
+  TpProcCpuBeforeAllocateWheaBuffer,  ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateWheaBuffer,   ///< 65 .. After the WHEA init code calls out to allocate a buffer
+  TpProcCpuBeforeAllocateSratBuffer,  ///< 66 .. Before the SRAT init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSratBuffer,   ///< 67 .. After the SRAT init code calls out to allocate a buffer
+  TpProcCpuBeforeLocateSsdtBuffer,    ///< 68 .. Before the P-state init code calls out to locate a buffer
+  TpProcCpuAfterLocateSsdtBuffer,     ///< 69 .. After the P-state init code calls out to locate a buffer
+  TpProcCpuBeforeAllocateSsdtBuffer,  ///< 6A .. Before the P-state init code calls out to allocate a buffer
+  TpProcCpuAfterAllocateSsdtBuffer,   ///< 6B .. After the P-state init code calls out to allocate a buffer
+
+  // HT test points
+  TpProcHtEntry = 0x71,               ///< 71 .. Coherent Discovery begin (Public interface)
+  TpProcHtTopology,                   ///< 72 .. Topology match, routing, begin
+  TpProcHtManualNc,                   ///< 73 .. Manual Non-coherent Init begin
+  TpProcHtAutoNc,                     ///< 74 .. Automatic Non-coherent init begin
+  TpProcHtOptGather,                  ///< 75 .. Optimization: Gather begin
+  TpProcHtOptRegang,                  ///< 76 .. Optimization: Regang begin
+  TpProcHtOptLinks,                   ///< 77 .. Optimization: Link Begin
+  TpProcHtOptSubLinks,                ///< 78 .. Optimization: Sublinks begin
+  TpProcHtOptFinish,                  ///< 79 .. Optimization: Set begin
+  TpProcHtTrafficDist,                ///< 7A .. Traffic Distribution begin
+  TpProcHtTuning,                     ///< 7B .. Misc Tuning Begin
+  TpProcHtDone,                       ///< 7C .. HT Init complete
+  TpProcHtApMapEntry,                 ///< 7D .. AP HT: Init Maps begin
+  TpProcHtApMapDone,                  ///< 7E .. AP HT: Complete
+
+  // Extended memory test point
+  TpProcMemSendMRS2 = 0x80,           ///< 80 .. Sending MRS2
+  TpProcMemSendMRS3,                  ///< 81 .. Sedding MRS3
+  TpProcMemSendMRS1,                  ///< 82 .. Sending MRS1
+  TpProcMemSendMRS0,                  ///< 83 .. Sending MRS0
+  TpProcMemContinPatternGenRead,      ///< 84 .. Continuous Pattern Read
+  TpProcMemContinPatternGenWrite,     ///< 85 .. Continuous Pattern Write
+  TpProcMem__RdDqsTraining,           ///< 86 .. Mem: RdDqs Training begin
+  TpProcMemBefore__TrainExtVrefChange,///< 87 .. Mem: Before optional callout to platfrom BIOS to change External Vref during training
+  TpProcMemAfter__TrainExtVrefChange, ///< 88 .. Mem: After optional callout to platfrom BIOS to change External Vref during training
+
+  StartNbTestPoints = 0x90,           ///< 90 Entry used for range testing for @b NorthBridge related TPs
+  TpNbxxx,                            ///< 91 .
+  EndNbTestPoints,                    ///< 92 End of TP range for NB
+
+  StartFchTestPoints = 0xB0,          ///< B0 Entry used for range testing for @b FCH related TPs
+  TpFchInitResetDispatching,          ///< B1 .. FCH InitReset dispatch point
+  TpFchGppBeforePortTraining,         ///< B2 .. Before FCH GPP port training
+  TpFchGppGen1PortPolling,            ///< B3 .. FCH GPP port polling with GEN1 speed
+  TpFchGppGen2PortPolling,            ///< B4 .. FCH GPP port polling with GEN2 speed
+  TpFchGppAfterPortTraining,          ///< B5 .. After FCH GPP port training
+  TpFchInitEnvDispatching,            ///< B6 .. FCH InitEnv dispatch point
+  TpFchInitMidDispatching,            ///< B7 .. FCH InitMid dispatch point
+  TpFchInitLateDispatching,           ///< B8 .. FCH InitLate dispatch point
+  TpFchGppHotPlugging,                ///< B9 .. FCH GPP hot plug event
+  TpFchGppHotUnplugging,              ///< BA .. AFCH GPP hot unplug event
+  TpFchInitS3EarlyDispatching,        ///< BB .. FCH InitS3Early dispatch point
+  TpFchInitS3LateDispatching,         ///< BC .. FCH InitS3Late dispatch point
+  EndFchTestPoints,                   ///< BF End of TP range for FCH
+
+  // Interface test points
+  TpIfAmdInitResetEntry = 0xC0,       ///< C0 .. Entry to AmdInitReset
+  TpIfAmdInitResetExit,               ///< C1 .. Exiting from AmdInitReset
+  TpIfAmdInitRecoveryEntry,           ///< C2 .. Entry to AmdInitRecovery
+  TpIfAmdInitRecoveryExit,            ///< C3 .. Exiting from AmdInitRecovery
+  TpIfAmdInitEarlyEntry,              ///< C4 .. Entry to AmdInitEarly
+  TpIfAmdInitEarlyExit,               ///< C5 .. Exiting from AmdInitEarly
+  TpIfAmdInitPostEntry,               ///< C6 .. Entry to AmdInitPost
+  TpIfAmdInitPostExit,                ///< C7 .. Exiting from AmdInitPost
+  TpIfAmdInitEnvEntry,                ///< C8 .. Entry to AmdInitEnv
+  TpIfAmdInitEnvExit,                 ///< C9 .. Exiting from AmdInitEnv
+  TpIfAmdInitMidEntry,                ///< CA .. Entry to AmdInitMid
+  TpIfAmdInitMidExit,                 ///< CB .. Exiting from AmdInitMid
+  TpIfAmdInitLateEntry,               ///< CC .. Entry to AmdInitLate
+  TpIfAmdInitLateExit,                ///< CD .. Exiting from AmdInitLate
+  TpIfAmdS3SaveEntry,                 ///< CE .. Entry to AmdS3Save
+  TpIfAmdS3SaveExit,                  ///< CF .. Exiting from AmdS3Save
+  TpIfAmdInitResumeEntry,             ///< D0 .. Entry to AmdInitResume
+  TpIfAmdInitResumeExit,              ///< D1 .. Exiting from AmdInitResume
+  TpIfAmdS3LateRestoreEntry,          ///< D2 .. Entry to AmdS3LateRestore
+  TpIfAmdS3LateRestoreExit,           ///< D3 .. Exiting from AmdS3LateRestore
+  TpIfAmdLateRunApTaskEntry,          ///< D4 .. Entry to AmdS3LateRestore
+  TpIfAmdLateRunApTaskExit,           ///< D5 .. Exiting from AmdS3LateRestore
+  TpIfAmdReadEventLogEntry,           ///< D6 .. Entry to AmdReadEventLog
+  TpIfAmdReadEventLogExit,            ///< D7 .. Exiting from AmdReadEventLog
+  TpIfAmdGetApicIdEntry,              ///< D8 .. Entry to AmdGetApicId
+  TpIfAmdGetApicIdExit,               ///< D9 .. Exiting from AmdGetApicId
+  TpIfAmdGetPciAddressEntry,          ///< DA .. Entry to AmdGetPciAddress
+  TpIfAmdGetPciAddressExit,           ///< DB .. Exiting from AmdGetPciAddress
+  TpIfAmdIdentifyCoreEntry,           ///< DC .. Entry to AmdIdentifyCore
+  TpIfAmdIdentifyCoreExit,            ///< DD .. Exiting from AmdIdentifyCore
+  TpIfBeforeRunApFromIds,             ///< DE .. After IDS calls out to run code on an AP
+  TpIfAfterRunApFromIds,              ///< DF .. After IDS calls out to run code on an AP
+  TpIfBeforeGetIdsData,               ///< E0 .. Before IDS calls out to get IDS data
+  TpIfAfterGetIdsData,                ///< E1 .. After IDS calls out to get IDS data
+  TpIfBeforeAllocateHeapBuffer,       ///< E2 .. Before the heap manager calls out to allocate a buffer
+  TpIfAfterAllocateHeapBuffer,        ///< E3 .. After the heap manager calls out to allocate a buffer
+  TpIfBeforeDeallocateHeapBuffer,     ///< E4 .. Before the heap manager calls out to deallocate a buffer
+  TpIfAfterDeallocateHeapBuffer,      ///< E5 .. After the heap manager calls out to deallocate a buffer
+  TpIfBeforeLocateHeapBuffer,         ///< E6 .. Before the heap manager calls out to locate a buffer
+  TpIfAfterLocateHeapBuffer,          ///< E7 .. After the heap manager calls out to locate a buffer
+  TpIfBeforeRunApFromAllAps,          ///< E8 .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllAps,           ///< E9 .. After the BSP calls out to run code on an AP
+  TpIfBeforeRunApFromAllCore0s,       ///< EA .. Before the BSP calls out to run code on an AP
+  TpIfAfterRunApFromAllCore0s,        ///< EB .. After the BSP calls out to run code on an AP
+  TpIfBeforeAllocateS3SaveBuffer,     ///< EC .. Before the S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateS3SaveBuffer,      ///< ED .. After the S3 save code calls out to allocate a buffer
+  TpIfBeforeAllocateMemoryS3SaveBuffer,  ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+  TpIfAfterAllocateMemoryS3SaveBuffer,   ///< EF .. After the memory S3 save code calls out to allocate a buffer
+  TpIfBeforeLocateS3PciBuffer,        ///< F0 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3PciBuffer,         ///< F1 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CPciBuffer,       ///< F2 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CPciBuffer,        ///< F3 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3MsrBuffer,        ///< F4 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3MsrBuffer,         ///< F5 .. After the memory code calls out to locate a buffer
+  TpIfBeforeLocateS3CMsrBuffer,       ///< F6 .. Before the memory code calls out to locate a buffer
+  TpIfAfterLocateS3CMsrBuffer,        ///< F7 .. After the memory code calls out to locate a buffer
+  TpPerfUnit,                         ///< F8 .. The Unit of performance measure.
+  EndAgesaTps = 0xFF,                 ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+  IDS_FEAT_UCODE_UPDATE = 0x0000,   ///< Feat for Ucode Update
+  IDS_FEAT_TARGET_PSTATE,           ///< Feat for Target Pstate
+  IDS_FEAT_POSTPSTATE,              ///< Feat for Post Pstate
+  IDS_FEAT_ECC_CTRL,                ///< Feat for Ecc Control
+  IDS_FEAT_ECC_SYMBOL_SIZE,         ///< Feat for Ecc symbol size
+  IDS_FEAT_DCT_ALLMEMCLK,           ///< Feat for all memory clock
+  IDS_FEAT_DCT_GANGMODE,            ///< Feat for Dct gang mode
+  IDS_FEAT_DCT_BURSTLENGTH,         ///< Feat for dct burst length
+  IDS_FEAT_DCT_POWERDOWN,           ///< Feat for dct power down
+  IDS_FEAT_DCT_DLLSHUTDOWN,         ///< Feat for dct dll shut down
+  IDS_FEAT_PROBE_FILTER,            ///< Feat for probe filter
+  IDS_FEAT_HDTOUT,                  ///< Feat for hdt out
+  IDS_FEAT_HT_SETTING,              ///< Feat for Ht setting
+  IDS_FEAT_GNB_PLATFORMCFG,         ///< Feat for override GNB platform config
+  IDS_FEAT_CPB_CTRL,                ///< Feat for Config the Core peformance boost feature
+  IDS_FEAT_HTC_CTRL,                ///< Feat for Hardware Thermal Control
+  IDS_FEAT_MEMORY_MAPPING,          ///< Feat for Memory Mapping
+  IDS_FEAT_POWER_POLICY,            ///< Feat for Power Policy
+  IDS_FEAT_NV_TO_CMOS,              ///< Feat for Save BSP Nv to CMOS
+  IDS_FEAT_COMMON,                  ///< Common Feat
+  IDS_FEAT_END = 0xFF               ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+  IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000,   ///< Function ID for saving IDTR for BSC
+  IDS_IDT_RESTORE_IDTR_FOR_BSC,            ///< Function ID for restoring IDTR for BSC
+  IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP,  ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       IDS_NV_ITEM *IdsNvPtr
+  );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef  struct _IDS_FAMILY_FEAT_STRUCT {
+  IDS_FEAT  IdsFeat;      ///< Ids Feat ID
+  BOOLEAN IsBsp;          ///< swith for Bsp check
+  AGESA_IDS_OPTION IdsOption;   ///< IDS option
+  UINT64 CpuFamily;       ///<
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef  struct _IDS_OPTION_STRUCT {
+  AGESA_IDS_OPTION idsoption;       ///< IDS option
+  PIDS_COMMON_FUNC  pf_idsoption;   ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+  UINT8 version;      ///<Version of IDS option table
+  UINT16 size;        ///<Size of IDS option table
+  CONST IDS_OPTION_STRUCT  *pIdsOptionStruct; ///<pointer to array of  structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE   1
+#define IDS_NV_TO_CMOS_LEN_WORD   2
+#define IDS_NV_TO_CMOS_LEN_END   0xFF
+#define IDS_NV_TO_CMOS_ID_END   0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+  UINT8 Length;       ///< Length of NV
+  UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+  IN       AGESA_IDS_OPTION IdsOption,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+AGESA_STATUS
+IdsOptionCallout (
+  IN       UINTN                CallOutId,
+  IN OUT   VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintInit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintS3Exit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrintS3ApExit (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+AmdIdsDebugPrint (
+  IN       UINT64 Flag,
+  IN       CHAR8 *Format,
+  IN       ...
+  );
+
+VOID
+AmdIdsDebugPrintHt (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintCpu (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintMem (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintGnb (
+  IN      CHAR8 *Format,
+  IN      ...
+  );
+
+VOID
+AmdIdsDebugPrintFlush (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsMemTimeOut (
+  IN OUT   VOID *DataPtr
+  );
+
+VOID
+IdsAgesaTestPoint (
+  IN      AGESA_TP TestPoint,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/**
+ *  IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval         TRUE     No error
+**/
+BOOLEAN
+IdsAssert (
+  IN      UINT32 FileCode
+  );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display.  Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display.  The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in]     FileCode    File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+  IN      UINT32 FileCode
+  );
+
+VOID
+IdsDelay (
+  IN	VOID
+);
+
+BOOLEAN
+AmdHeapIntactCheck (
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+VOID
+IdsCarCorruptionCheck (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+IDS_STATUS
+IdsExceptionTrap (
+  IN       IDS_IDT_FUNC_ID IdsIdtFuncId,
+  IN       VOID *DataPtr,
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+#if IDSOPT_IDS_ENABLED == FALSE
+  #undef IEM_SKIP_CODE
+  #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+  #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+  #define IEM_INSERT_CODE(L,Fn,Parm)
+#endif
+
+//Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a)   ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG                                  DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG                                  DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW                                    DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS                                  DEBUG_PRINT_SHIFT (3)
+#define MEMORY_TRACE_RSV1                           DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2                           DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3                           DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4                           DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5                           DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6                           DEBUG_PRINT_SHIFT (9)
+
+
+
+//CPU Masks
+#define CPU_TRACE                                   DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1                              DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2                              DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3                              DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4                              DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5                              DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6                              DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7                              DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8                              DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9                              DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE                                   DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC                                   DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE                          DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE                          DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2                              DEBUG_PRINT_SHIFT (24)
+#define NB_MISC                                     DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3                              DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC                                    DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE                             DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1                              DEBUG_PRINT_SHIFT (29)
+
+//HT Masks
+#define HT_TRACE                                    DEBUG_PRINT_SHIFT (30)
+#define HT_TRACE_RSV1                               DEBUG_PRINT_SHIFT (31)
+#define HT_TRACE_RSV2                               DEBUG_PRINT_SHIFT (32)
+#define HT_TRACE_RSV3                               DEBUG_PRINT_SHIFT (33)
+#define HT_TRACE_RSV4                               DEBUG_PRINT_SHIFT (34)
+#define HT_TRACE_RSV5                               DEBUG_PRINT_SHIFT (35)
+#define HT_TRACE_RSV6                               DEBUG_PRINT_SHIFT (36)
+#define HT_TRACE_RSV7                               DEBUG_PRINT_SHIFT (37)
+#define HT_TRACE_RSV8                               DEBUG_PRINT_SHIFT (38)
+#define HT_TRACE_RSV9                               DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE                                    DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1                               DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2                               DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3                               DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4                               DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5                               DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6                               DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7                               DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8                               DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9                               DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW                                    DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG                                    DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE                          DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE                                    DEBUG_PRINT_SHIFT (53)
+#define IDS_REG                                      DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2                               DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3                               DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE                                     DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD                                   DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR                                   DEBUG_PRINT_SHIFT (59)
+
+//Reserved
+#define TRACE_RSV3                                   DEBUG_PRINT_SHIFT (60)
+#define TRACE_RSV4                                   DEBUG_PRINT_SHIFT (61)
+#define TRACE_RSV5                                   DEBUG_PRINT_SHIFT (62)
+#define TRACE_RSV6                                   DEBUG_PRINT_SHIFT (63)
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/IdsHt.h b/src/vendorcode/amd/agesa/f15/Include/IdsHt.h
new file mode 100644
index 0000000..bdda364
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/IdsHt.h
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS HyperTransport Definitions
+ *
+ * Contains AMD AGESA Integrated Debug HT related items.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  IDS
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HT_H_
+#define _IDS_HT_H_
+
+// Frequency equates for call backs which take an actual frequency setting
+#define HT_FREQUENCY_200M            0
+#define HT_FREQUENCY_400M            2
+#define HT_FREQUENCY_600M            4
+#define HT_FREQUENCY_800M            5
+#define HT_FREQUENCY_1000M           6
+#define HT_FREQUENCY_1200M           7
+#define HT_FREQUENCY_1400M           8
+#define HT_FREQUENCY_1600M           9
+#define HT_FREQUENCY_1800M           10
+#define HT_FREQUENCY_2000M           11
+#define HT_FREQUENCY_2200M           12
+#define HT_FREQUENCY_2400M           13
+#define HT_FREQUENCY_2600M           14
+#define HT_FREQUENCY_2800M           17
+#define HT_FREQUENCY_3000M           18
+#define HT_FREQUENCY_3200M           19
+#define HT_FREQUENCY_3600M           20
+
+/**
+ * HT IDS: HT Link Port Override params.
+ *
+ * Provide an absolute override of HT Link Port settings.  No checking is done that
+ * the settings obey limits or capabilities, this responsibility rests with the user.
+ *
+ * Rules for values of structure items:
+ * - Socket
+ *   - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
+ *   - HT_LIST_MATCH_ANY == Match Any Socket
+ *   - 0 .. 7 == The matching socket
+ * - Link
+ *   - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
+ *   - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
+ *   - 0 .. 7 == The matching package link.  0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
+ * - Frequency
+ *   - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
+ *   - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
+ * - Widthin
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ * - Widthout
+ *   - HT_LIST_TERMINAL == Do not override the width, AUTO setting
+ *   - 2, 4, 8, 16, 32 == The width value to use
+ */
+typedef struct {
+  // Match Fields
+  UINT8       Socket;      ///< The Socket which this port is on.
+  UINT8       Link;        ///< The port for this package link on that socket.
+  // Override fields
+  UINT8       Frequency;   ///< Absolutely override the port's frequency.
+  UINT8       WidthIn;     ///< Absolutely override the port's width.
+  UINT8       WidthOut;    ///< Absolutely override the port's width.
+} HTIDS_PORT_OVERRIDE;
+
+/**
+ * A list of port overrides to search.
+ */
+typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
+VOID
+HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+
+typedef
+VOID
+F_HtIdsGetPortOverride (
+  IN       BOOLEAN                    IsSourcePort,
+  IN OUT   PORT_DESCRIPTOR            *Port0,
+  IN OUT   PORT_DESCRIPTOR            *Port1,
+  IN OUT   HTIDS_PORT_OVERRIDE_LIST   *PortOverrideList,
+  IN       STATE_DATA                 *State
+  );
+typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
+#endif // _IDS_HT_H
diff --git a/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
new file mode 100644
index 0000000..a1dd4fc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/MaranelloInstall.h
@@ -0,0 +1,116 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build options for a Maranello platform solution
+ *
+ * This file generates the defaults tables for the "Maranello" platform solution
+ * set of processors. The documented build options are imported from a user
+ * controlled file for processing.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 59375 $   @e \$Date: 2011-09-21 13:24:35 -0600 (Wed, 21 Sep 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#include "cpuRegisters.h"
+#include "cpuFamRegisters.h"
+#include "cpuFamilyTranslation.h"
+#include "AdvancedApi.h"
+#include "heapManager.h"
+#include "CreateStruct.h"
+#include "cpuFeatures.h"
+#include "Table.h"
+#include "CommonReturns.h"
+#include "cpuEarlyInit.h"
+#include "cpuLateInit.h"
+#include "GnbInterfaceStub.h"
+
+/*****************************************************************************
+ *   Define the RELEASE VERSION string
+ *
+ * The Release Version string should identify the next planned release.
+ * When a branch is made in preparation for a release, the release manager
+ * should change/confirm that the branch version of this file contains the
+ * string matching the desired version for the release. The trunk version of
+ * the file should always contain a trailing 'X'. This will make sure that a
+ * development build from trunk will not be confused for a released version.
+ * The release manager will need to remove the trailing 'X' and update the
+ * version string as appropriate for the release. The trunk copy of this file
+ * should also be updated/incremented for the next expected version, + trailing 'X'
+ ****************************************************************************/
+                    // This is the delivery package title, "MarG34PI"
+                    // This string MUST be exactly 8 characters long
+#define AGESA_PACKAGE_STRING  {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
+
+                    // This is the release version number of the AGESA component
+                    // This string MUST be exactly 12 characters long
+#define AGESA_VERSION_STRING  {'V', '1', '.', '2', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
+
+
+
+// The Maranello solution is defined to be families 0x10 and 0x15 models 0x0 - 0xF in the G34 socket.
+#define INSTALL_G34_SOCKET_SUPPORT           TRUE
+#define INSTALL_FAMILY_10_SUPPORT            TRUE
+#define INSTALL_FAMILY_15_MODEL_0x_SUPPORT   TRUE
+
+#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_10_SUPPORT
+    #define INSTALL_FAMILY_10_SUPPORT     FALSE
+  #endif
+#endif
+
+#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
+  #if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
+    #undef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
+    #define INSTALL_FAMILY_15_MODEL_0x_SUPPORT     FALSE
+  #endif
+#endif
+
+
+// The following definitions specify the default values for various parameters in which there are
+// no clearly defined defaults to be used in the common file.  The values below are based on product
+// and BKDG content, please consult the AGESA Memory team for consultation.
+#define DFLT_SCRUB_DRAM_RATE            (0xFF)
+#define DFLT_SCRUB_L2_RATE              (0x10)
+#define DFLT_SCRUB_L3_RATE              (0x10)
+#define DFLT_SCRUB_IC_RATE              (0)
+#define DFLT_SCRUB_DC_RATE              (0x12)
+#define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_REGISTERED
+#define DFLT_VRM_SLEW_RATE              (2500)
+
+
+// Instantiate all solution relevant data.
+#include "PlatformInstall.h"
+
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
new file mode 100644
index 0000000..4b3b9a8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionApmInstall.h
@@ -0,0 +1,87 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Application Power Management (APM).
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 54493 $   @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_APM_INSTALL_H_
+#define _OPTION_APM_INSTALL_H_
+
+#include "cpuApm.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_APM_FEAT
+#define F15_APM_SUPPORT
+
+#if OPTION_CPU_APM == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureApm;
+          #undef OPTION_CPU_APM_FEAT
+          #define OPTION_CPU_APM_FEAT &CpuFeatureApm,
+          extern CONST APM_FAMILY_SERVICES ROMDATA F15ApmSupport;
+          #undef F15_APM_SUPPORT
+          #define F15_APM_SUPPORT {AMD_FAMILY_15_OR | AMD_FAMILY_15_KM, &F15ApmSupport},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA ApmFamilyServiceArray[] =
+{
+  F15_APM_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA ApmFamilyServiceTable =
+{
+  (sizeof (ApmFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &ApmFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_APM_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
new file mode 100644
index 0000000..2e944bf
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionC6Install.h
@@ -0,0 +1,164 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: C6 C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_C6_STATE_INSTALL_H_
+#define _OPTION_C6_STATE_INSTALL_H_
+
+#include "cpuC6State.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_C6_STATE_FEAT
+#define F12_C6_STATE_SUPPORT
+#define F14_ON_C6_STATE_SUPPORT
+#define F15_OR_C6_STATE_SUPPORT
+
+#if OPTION_C6_STATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
+          #undef F12_C6_STATE_SUPPORT
+          #define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
+
+          #if OPTION_EARLY_SAMPLES == TRUE
+            extern F_F12_ES_C6_INIT F12C6A0Workaround;
+
+            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+            {
+              F12C6A0Workaround
+            };
+          #else
+            CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
+            {
+              (PF_F12_ES_C6_INIT) CommonVoid
+            };
+          #endif
+
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if (OPTION_FAMILY14H_ON == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
+          #undef F14_ON_C6_STATE_SUPPORT
+          #define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
+
+          #if (OPTION_EARLY_SAMPLES == TRUE)
+            extern F_F14_ON_ES_IS_C6_SUPPORTED F14IsC6DisabledEarlySample;
+            extern F_F14_ON_ES_C6_INIT F14C6A0Workaround;
+
+            CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
+            {
+              F14IsC6DisabledEarlySample,
+              F14C6A0Workaround
+            };
+          #else
+            CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
+            {
+              (PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
+              (PF_F14_ON_ES_C6_INIT) CommonVoid
+            };
+          #endif
+        #endif
+
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
+          #undef OPTION_C6_STATE_FEAT
+          #define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
+          extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
+          #undef F15_OR_C6_STATE_SUPPORT
+          #define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
+
+          #if (OPTION_EARLY_SAMPLES == TRUE)
+            extern F_F15_OR_ES_IS_C6_SUPPORTED F15OrIsC6DisabledEarlySample;
+
+            CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
+            {
+              F15OrIsC6DisabledEarlySample
+            };
+          #else
+            CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
+            {
+              (PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
+            };
+          #endif
+        #endif
+
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
+{
+  F12_C6_STATE_SUPPORT
+  F14_ON_C6_STATE_SUPPORT
+  F15_OR_C6_STATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
+{
+  (sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &C6FamilyServiceArray[0]
+};
+
+#endif  // _OPTION_C6_STATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
new file mode 100644
index 0000000..d47619b
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpbInstall.h
@@ -0,0 +1,170 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Core Performance Boost
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 46389 $   @e \$Date: 2011-01-31 20:22:49 -0700 (Mon, 31 Jan 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPB_INSTALL_H_
+#define _OPTION_CPB_INSTALL_H_
+
+#include "cpuCpb.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPB_FEAT
+#define F10_CPB_SUPPORT
+#define F12_CPB_SUPPORT
+#define F14_ON_CPB_SUPPORT
+#define F15_OR_CPB_SUPPORT
+
+#if OPTION_CPB == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    // Family 10h
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_PH == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
+          #undef F10_CPB_SUPPORT
+          #define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 12h
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
+          #undef F12_CPB_SUPPORT
+          #define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
+          #if OPTION_EARLY_SAMPLES == TRUE
+            #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+              extern F_F12_ES_CPB_INIT F12LnA1CpbHook;
+
+              CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+              {
+                F12LnA1CpbHook
+              };
+            #else
+              CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+              {
+                (PF_F12_ES_CPB_INIT) CommonVoid
+              };
+            #endif
+          #else
+            CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
+            {
+              (PF_F12_ES_CPB_INIT) CommonVoid
+            };
+          #endif
+        #endif
+      #endif
+    #endif
+
+    // Family 14h
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if OPTION_FAMILY14H_ON == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
+          #undef F14_ON_CPB_SUPPORT
+          #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
+        #endif
+      #endif
+    #endif
+
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if (OPTION_FAMILY15H_OR == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
+          #undef F15_OR_CPB_SUPPORT
+          #define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
+
+          #if OPTION_EARLY_SAMPLES == TRUE
+            extern F_F15_OR_ES_IS_CPB_SUPPORTED F15OrIsCpbDisabledEarlySample;
+
+            CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
+            {
+              F15OrIsCpbDisabledEarlySample
+            };
+          #else
+            CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
+            {
+              (PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
+            };
+          #endif
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
+{
+  F10_CPB_SUPPORT
+  F12_CPB_SUPPORT
+  F14_ON_CPB_SUPPORT
+  F15_OR_CPB_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
+{
+  (sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpbFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
new file mode 100644
index 0000000..35362ff
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCacheFlushOnHaltInstall.h
@@ -0,0 +1,126 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Cache Flush On Halt
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
+
+#include "cpuPostInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+#define F10_BL_CPU_CFOH_SUPPORT
+#define F10_DA_CPU_CFOH_SUPPORT
+#define F10_CPU_CFOH_SUPPORT
+#define F15_OR_CPU_CFOH_SUPPORT
+#define F15_TN_CPU_CFOH_SUPPORT
+
+#if OPTION_CPU_CFOH == TRUE
+  #if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
+
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY10H_BL == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
+          #undef F10_BL_CPU_CFOH_SUPPORT
+          #define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY10H_DA == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
+          #undef F10_DA_CPU_CFOH_SUPPORT
+          #define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
+        #endif
+
+        #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
+          #undef F10_CPU_CFOH_SUPPORT
+          #define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+        #define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
+
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
+          #undef F15_OR_CPU_CFOH_SUPPORT
+          #define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
+        #endif
+
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15TnCacheFlushOnHalt;
+          #undef F15_TN_CPU_CFOH_SUPPORT
+          #define F15_TN_CPU_CFOH_SUPPORT {AMD_FAMILY_15_TN, &F15TnCacheFlushOnHalt},
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
+{
+  F10_BL_CPU_CFOH_SUPPORT
+  F10_DA_CPU_CFOH_SUPPORT
+  F10_CPU_CFOH_SUPPORT
+  F15_OR_CPU_CFOH_SUPPORT
+  F15_TN_CPU_CFOH_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
+{
+  (sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CacheFlushOnHaltFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
new file mode 100644
index 0000000..d0743ec
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuCoreLevelingInstall.h
@@ -0,0 +1,120 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: CPU Core Leveling
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
+#define _OPTION_CPU_CORELEVELING_INSTALL_H_
+
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_CORE_LEVELING_FEAT
+#define F10_REVE_CPU_CORELEVELING_SUPPORT
+#define F10_REVD_CPU_CORELEVELING_SUPPORT
+#define F10_REVC_CPU_CORELEVELING_SUPPORT
+#define F15_OR_CPU_CORELEVELING_SUPPORT
+#define F15_TN_CPU_CORELEVELING_SUPPORT
+
+#if OPTION_CPU_CORELEVLING == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
+
+    // Family 10h
+    #if OPTION_FAMILY10H == TRUE
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+      #if OPTION_FAMILY10H_HY == TRUE
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
+        #undef F10_REVD_CPU_CORELEVELING_SUPPORT
+        #define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
+      #endif
+
+      #if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
+        #undef F10_REVC_CPU_CORELEVELING_SUPPORT
+        #define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
+      #endif
+
+      #if (OPTION_FAMILY10H_PH == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
+        #undef F10_REVE_CPU_CORELEVELING_SUPPORT
+        #define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
+      #endif
+    #endif
+    // Family 15h
+    #if OPTION_FAMILY15H == TRUE
+      #undef OPTION_CPU_CORE_LEVELING_FEAT
+      #define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
+
+      #if (OPTION_FAMILY15H_OR == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
+        #undef F15_OR_CPU_CORELEVELING_SUPPORT
+        #define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
+      #endif
+      #if (OPTION_FAMILY15H_TN == TRUE)
+        extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15TnCoreLeveling;
+        #undef F15_TN_CPU_CORELEVELING_SUPPORT
+        #define F15_TN_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_TN, &F15TnCoreLeveling},
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
+{
+  F15_TN_CPU_CORELEVELING_SUPPORT
+  F15_OR_CPU_CORELEVELING_SUPPORT
+  F10_REVE_CPU_CORELEVELING_SUPPORT
+  F10_REVD_CPU_CORELEVELING_SUPPORT
+  F10_REVC_CPU_CORELEVELING_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
+{
+  (sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CoreLevelingFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_CPU_CORELEVELING_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
new file mode 100644
index 0000000..5cc4819
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFamiliesInstall.h
@@ -0,0 +1,407 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of all appropriate CPU family specific support.
+ *
+ * This file generates the defaults tables for all family specific
+ * combinations.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 50628 $   @e \$Date: 2011-04-12 15:18:38 -0600 (Tue, 12 Apr 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+/*  Default all CPU Specific Service members to off.  They
+    will be enabled as needed by cross referencing families
+    with entry points in the family / model install files.  */
+#define GET_PSTATE_POWER            FALSE
+#define GET_PSTATE_FREQ             FALSE
+#define DISABLE_PSTATE              FALSE
+#define TRANSITION_PSTATE           FALSE
+#define PROC_IDD_MAX                FALSE
+#define GET_TSC_RATE                FALSE
+#define PSTATE_TRANSITION_LATENCY   FALSE
+#define GET_PSTATE_REGISTER_INFO    FALSE
+#define GET_PSTATE_MAX_STATE        FALSE
+#define SET_PSTATE_LEVELING_REG     FALSE
+#define GET_NB_FREQ                 FALSE
+#define GET_NB_IDD_MAX              FALSE
+#define IS_NBCOF_INIT_NEEDED        FALSE
+#define AP_INITIAL_LAUNCH           FALSE
+#define GET_AP_MAILBOX_FROM_HW      FALSE
+#define SET_AP_CORE_NUMBER          FALSE
+#define GET_AP_CORE_NUMBER          FALSE
+#define TRANSFER_AP_CORE_NUMBER     FALSE
+#define ID_POSITION_INITIAL_APICID  FALSE
+#define SAVE_FEATURES               FALSE
+#define WRITE_FEATURES              FALSE
+#define SET_DOWN_CORE_REG           FALSE
+#define SET_WARM_RESET_FLAG         FALSE
+#define GET_WARM_RESET_FLAG         FALSE
+#define USES_REGISTER_TABLES        FALSE
+#define BASE_FAMILY_PCI             FALSE
+#define MODEL_SPECIFIC_PCI          FALSE
+#define BASE_FAMILY_MSR             FALSE
+#define MODEL_SPECIFIC_MSR          FALSE
+#define BRAND_STRING1               FALSE
+#define BRAND_STRING2               FALSE
+#define BASE_FAMILY_HT_PCI          FALSE
+#define MODEL_SPECIFIC_HT_PCI       FALSE
+#define BASE_FAMILY_WORKAROUNDS     FALSE
+#define GET_PATCHES                 FALSE
+#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
+#define GET_CACHE_INFO              FALSE
+#define GET_SYSTEM_PM_TABLE         FALSE
+#define GET_WHEA_INIT               FALSE
+#define GET_CFOH_REG                FALSE
+#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
+#define IS_NB_PSTATE_ENABLED        FALSE
+
+/*
+ * Pull in family specific services based on entry point
+ */
+#if AGESA_ENTRY_INIT_RESET == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RECOVERY == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef DISABLE_PSTATE
+  #define DISABLE_PSTATE              TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef GET_NB_FREQ
+  #define GET_NB_FREQ                 TRUE
+  #undef GET_NB_IDD_MAX
+  #define GET_NB_IDD_MAX              TRUE
+  #undef IS_NBCOF_INIT_NEEDED
+  #define IS_NBCOF_INIT_NEEDED        TRUE
+  #undef AP_INITIAL_LAUNCH
+  #define AP_INITIAL_LAUNCH           TRUE
+  #undef GET_AP_MAILBOX_FROM_HW
+  #define GET_AP_MAILBOX_FROM_HW      TRUE
+  #undef SET_AP_CORE_NUMBER
+  #define SET_AP_CORE_NUMBER          TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef TRANSFER_AP_CORE_NUMBER
+  #define TRANSFER_AP_CORE_NUMBER     TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef SET_DOWN_CORE_REG
+  #define SET_DOWN_CORE_REG           TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef USES_REGISTER_TABLES
+  #define USES_REGISTER_TABLES        TRUE
+  #undef BASE_FAMILY_PCI
+  #define BASE_FAMILY_PCI             TRUE
+  #undef MODEL_SPECIFIC_PCI
+  #define MODEL_SPECIFIC_PCI          TRUE
+  #undef BASE_FAMILY_MSR
+  #define BASE_FAMILY_MSR             TRUE
+  #undef MODEL_SPECIFIC_MSR
+  #define MODEL_SPECIFIC_MSR          TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+  #undef BASE_FAMILY_HT_PCI
+  #define BASE_FAMILY_HT_PCI          TRUE
+  #undef MODEL_SPECIFIC_HT_PCI
+  #define MODEL_SPECIFIC_HT_PCI       TRUE
+  #undef BASE_FAMILY_WORKAROUNDS
+  #define BASE_FAMILY_WORKAROUNDS     TRUE
+  #undef GET_PATCHES
+  #define GET_PATCHES                 TRUE
+  #undef GET_PATCHES_EQUIVALENCE_TABLE
+  #define GET_PATCHES_EQUIVALENCE_TABLE TRUE
+  #undef GET_SYSTEM_PM_TABLE
+  #define GET_SYSTEM_PM_TABLE         TRUE
+  #undef GET_CACHE_INFO
+  #define GET_CACHE_INFO              TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_POST == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+  #undef GET_PSTATE_POWER
+  #define GET_PSTATE_POWER            TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PROC_IDD_MAX
+  #define PROC_IDD_MAX                TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_REGISTER_INFO
+  #define GET_PSTATE_REGISTER_INFO    TRUE
+  #undef GET_PSTATE_MAX_STATE
+  #define GET_PSTATE_MAX_STATE        TRUE
+  #undef SET_PSTATE_LEVELING_REG
+  #define SET_PSTATE_LEVELING_REG     TRUE
+  #undef SET_WARM_RESET_FLAG
+  #define SET_WARM_RESET_FLAG         TRUE
+  #undef GET_WARM_RESET_FLAG
+  #define GET_WARM_RESET_FLAG         TRUE
+  #undef SAVE_FEATURES
+  #define SAVE_FEATURES               TRUE
+  #undef WRITE_FEATURES
+  #define WRITE_FEATURES              TRUE
+  #undef GET_CFOH_REG
+  #define GET_CFOH_REG                TRUE
+  #undef IS_NB_PSTATE_ENABLED
+  #define IS_NB_PSTATE_ENABLED        TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_ENV == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_MID == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #undef GET_AP_CORE_NUMBER
+  #define GET_AP_CORE_NUMBER          TRUE
+  #undef GET_PSTATE_FREQ
+  #define GET_PSTATE_FREQ             TRUE
+  #undef TRANSITION_PSTATE
+  #define TRANSITION_PSTATE           TRUE
+  #undef PSTATE_TRANSITION_LATENCY
+  #define PSTATE_TRANSITION_LATENCY   TRUE
+  #undef GET_WHEA_INIT
+  #define GET_WHEA_INIT               TRUE
+  #undef GET_PLATFORM_TYPE_SPECIFIC_INFO
+  #define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
+  #undef GET_TSC_RATE
+  #define GET_TSC_RATE                TRUE
+  #undef BRAND_STRING1
+  #define BRAND_STRING1               TRUE
+  #undef BRAND_STRING2
+  #define BRAND_STRING2               TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_S3SAVE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_RESUME == TRUE
+  #undef GET_CFOH_REG
+  #define GET_CFOH_REG                TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
+#endif
+
+#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
+  #undef ID_POSITION_INITIAL_APICID
+  #define ID_POSITION_INITIAL_APICID  TRUE
+#endif
+
+/*
+ * Initialize PCI MMIO mask to 0
+ */
+#define FAMILY_MMIO_BASE_MASK (0ull)
+
+
+/*
+ * Initialize all families to disabled
+ */
+#define OPT_F10_TABLE
+#define OPT_F12_TABLE
+#define OPT_F14_TABLE
+#define OPT_F15_TABLE
+
+#define OPT_F10_ID_TABLE
+#define OPT_F12_ID_TABLE
+#define OPT_F14_ID_TABLE
+#define OPT_F15_ID_TABLE
+
+
+/*
+ * Install family specific support
+ */
+#if (OPTION_FAMILY10H == TRUE)
+  #include  "OptionFamily10hInstall.h"
+#endif
+
+#if (OPTION_FAMILY12H == TRUE)
+  #include  "OptionFamily12hInstall.h"
+#endif
+
+#if (OPTION_FAMILY14H == TRUE)
+  #include  "OptionFamily14hInstall.h"
+#endif
+
+#if (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_TN == TRUE) || (OPTION_FAMILY15H_KM == TRUE)
+  #include  "OptionFamily15hInstall.h"
+#endif
+
+
+/*
+ * Process PCI MMIO mask
+ */
+
+// If size is 0, but base is not, break the build.
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
+  #error    BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+#endif
+
+// If base is 0, but size is not, break the build.
+#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
+  #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+#endif
+
+#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
+  // Both are non-zero, begin further processing.
+
+  // Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
+  #if (CFG_PCI_MMIO_BASE < 0x800000)
+    #error    BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
+  #endif
+
+  // Break the build if the address is too high for the enabled families.
+  #if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
+    #error       BLDCFG: Invalid PCI MMIO base address for the installed CPU families
+  #endif
+
+  // If the size parameter is not valid, break the build.
+  #if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
+    #if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
+      #error      BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
+    #endif
+  #endif
+
+  #define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
+  // If the base is not aligned according to size, break the build.
+  #if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
+    #error      BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
+  #endif
+  #undef PCI_MMIO_ALIGNMENT
+#endif
+
+/*
+ * Process sockets / modules
+ */
+#ifndef ADVCFG_PLATFORM_SOCKETS
+  #error BLDOPT Set Family supported sockets.
+#endif
+#ifndef ADVCFG_PLATFORM_MODULES
+  #error BLDOPT Set Family supported modules.
+#endif
+
+CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
+{
+  ADVCFG_PLATFORM_SOCKETS,
+  ADVCFG_PLATFORM_MODULES
+};
+
+/*
+ * Instantiate global data needed for processor identification
+ */
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
+{
+  OPT_F10_TABLE
+  OPT_F12_TABLE
+  OPT_F14_TABLE
+  OPT_F15_TABLE
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
+{
+  (sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &CpuSupportedFamiliesArray[0]
+};
+
+
+CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
+{
+  OPT_F10_ID_TABLE
+  OPT_F12_ID_TABLE
+  OPT_F14_ID_TABLE
+  OPT_F15_ID_TABLE
+};
+
+CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
+{
+  (sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
+  CpuSupportedFamilyIdArray
+};
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
new file mode 100644
index 0000000..44df5ba
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionCpuFeaturesInstall.h
@@ -0,0 +1,80 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of multiple CPU features.
+ *
+ * Aggregates enabled CPU features into a list for the dispatcher to process.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 54493 $   @e \$Date: 2011-06-08 15:21:06 -0600 (Wed, 08 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
+#define _OPTION_CPU_FEATURES_INSTALL_H_
+
+#include "OptionHwC1eInstall.h"
+#include "OptionMsgBasedC1eInstall.h"
+#include "OptionSwC1eInstall.h"
+#include "OptionL3FeaturesInstall.h"
+#include "OptionCpuCoreLevelingInstall.h"
+#include "OptionIoCstateInstall.h"
+#include "OptionC6Install.h"
+#include "OptionCpbInstall.h"
+#include "OptionCpuCacheFlushOnHaltInstall.h"
+#include "OptionPstateHpcModeInstall.h"
+#include "OptionLowPwrPstateInstall.h"
+#include "OptionApmInstall.h"
+#include "OptionPreserveMailboxInstall.h"
+
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+{
+  OPTION_HW_C1E_FEAT
+  OPTION_MSG_BASED_C1E_FEAT
+  OPTION_SW_C1E_FEAT
+  OPTION_L3_FEAT
+  OPTION_CPU_CORE_LEVELING_FEAT
+  OPTION_IO_CSTATE_FEAT
+  OPTION_C6_STATE_FEAT
+  OPTION_CPB_FEAT
+  OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
+  OPTION_CPU_PSTATE_HPC_MODE_FEAT             // this function should be run before low power pstate for prochot
+  OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT  // this function should be run before creating ACPI objects and after Pstate initialization
+  OPTION_CPU_APM_FEAT
+  OPTION_PRESERVE_MAILBOX_FEAT
+  NULL
+};
+
+
+#endif  // _OPTION_CPU_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h
new file mode 100644
index 0000000..83fb7e9
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmi.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD DMI option API.
+ *
+ * Contains structures and values used to control the DMI option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_DMI_H_
+#define _OPTION_DMI_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_DMI_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader,
+  IN OUT   DMI_INFO             **DmiPtr
+  );
+
+typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
+  IN OUT   AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+#define DMI_STRUCT_VERSION  0x01
+
+/// DMI option configuration. Determine the item of structure when compiling.
+typedef struct  {
+  UINT16              OptDmiVersion;      ///< Dmi version.
+  OPTION_DMI_FEATURE  *DmiFeature;        ///< Feature main routine, otherwise dummy.
+  OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
+  UINT16              NumEntries;         ///< Number of entry.
+  VOID                *((*FamilyList)[]); ///< Family service.
+} OPTION_DMI_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_DMI_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
new file mode 100644
index 0000000..a6d48b3
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h
@@ -0,0 +1,215 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: DMI
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_DMI_INSTALL_H_
+#define _OPTION_DMI_INSTALL_H_
+
+#include "cpuLateInit.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#if AGESA_ENTRY_INIT_LATE == TRUE
+  #ifndef OPTION_DMI
+    #error  BLDOPT: Option not defined: "OPTION_DMI"
+  #endif
+  #if OPTION_DMI == TRUE
+    OPTION_DMI_FEATURE          GetDmiInfoMain;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBuffer;
+    #define USER_DMI_OPTION     &GetDmiInfoMain
+    #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
+
+    // This additional check keeps AP launch routines from being unnecessarily included
+    // in single socket systems.
+    #if OPTION_MULTISOCKET == TRUE
+      #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+      #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+      #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
+    #else
+      #define CPU_DMI_AP_GET_TYPE4_TYPE7
+    #endif
+
+    // Family 10
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
+        #define FAM10_DMI_SUPPORT FAM10_ENABLED,
+        #define FAM10_DMI_TABLE &ProcFamily10DmiTable,
+      #else
+        #define FAM10_DMI_SUPPORT
+        #define FAM10_DMI_TABLE
+      #endif
+    #else
+      #define FAM10_DMI_SUPPORT
+      #define FAM10_DMI_TABLE
+    #endif
+
+    // Family 12
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
+        #define FAM12_DMI_SUPPORT FAM12_ENABLED,
+        #define FAM12_DMI_TABLE &ProcFamily12DmiTable,
+      #else
+        #define FAM12_DMI_SUPPORT
+        #define FAM12_DMI_TABLE
+      #endif
+    #else
+      #define FAM12_DMI_SUPPORT
+      #define FAM12_DMI_TABLE
+    #endif
+
+    // Family 14
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
+        #define FAM14_DMI_SUPPORT FAM14_ENABLED,
+        #define FAM14_DMI_TABLE &ProcFamily14DmiTable,
+      #else
+        #define FAM14_DMI_SUPPORT
+        #define FAM14_DMI_TABLE
+      #endif
+    #else
+      #define FAM14_DMI_SUPPORT
+      #define FAM14_DMI_TABLE
+    #endif
+
+    // Family 15
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
+          #define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
+          #define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
+        #else
+          #define FAM15_OR_DMI_SUPPORT
+          #define FAM15_OR_DMI_TABLE
+        #endif
+        #if OPTION_FAMILY15H_TN == TRUE
+          extern PROC_FAMILY_TABLE ProcFamily15TnDmiTable;
+          #define FAM15_TN_DMI_SUPPORT FAM15_TN_ENABLED,
+          #define FAM15_TN_DMI_TABLE &ProcFamily15TnDmiTable,
+        #else
+          #define FAM15_TN_DMI_SUPPORT
+          #define FAM15_TN_DMI_TABLE
+        #endif
+      #else
+        #define FAM15_OR_DMI_SUPPORT
+        #define FAM15_OR_DMI_TABLE
+        #define FAM15_TN_DMI_SUPPORT
+        #define FAM15_TN_DMI_TABLE
+      #endif
+    #else
+      #define FAM15_OR_DMI_SUPPORT
+      #define FAM15_OR_DMI_TABLE
+      #define FAM15_TN_DMI_SUPPORT
+      #define FAM15_TN_DMI_TABLE
+    #endif
+
+  #else
+    OPTION_DMI_FEATURE          GetDmiInfoStub;
+    OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+    #define USER_DMI_OPTION     GetDmiInfoStub
+    #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+    #define FAM10_DMI_SUPPORT
+    #define FAM10_DMI_TABLE
+    #define FAM12_DMI_SUPPORT
+    #define FAM12_DMI_TABLE
+    #define FAM14_DMI_SUPPORT
+    #define FAM14_DMI_TABLE
+    #define FAM15_OR_DMI_SUPPORT
+    #define FAM15_OR_DMI_TABLE
+    #define FAM15_TN_DMI_SUPPORT
+    #define FAM15_TN_DMI_TABLE
+    #define CPU_DMI_AP_GET_TYPE4_TYPE7
+  #endif
+#else
+  OPTION_DMI_FEATURE          GetDmiInfoStub;
+  OPTION_DMI_RELEASE_BUFFER   ReleaseDmiBufferStub;
+  #define USER_DMI_OPTION     GetDmiInfoStub
+  #define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
+  #define FAM10_DMI_SUPPORT
+  #define FAM10_DMI_TABLE
+  #define FAM12_DMI_SUPPORT
+  #define FAM12_DMI_TABLE
+  #define FAM14_DMI_SUPPORT
+  #define FAM14_DMI_TABLE
+  #define FAM15_OR_DMI_SUPPORT
+  #define FAM15_OR_DMI_TABLE
+  #define FAM15_TN_DMI_SUPPORT
+  #define FAM15_TN_DMI_TABLE
+  #define CPU_DMI_AP_GET_TYPE4_TYPE7
+#endif
+
+/// DMI supported families enum
+typedef enum {
+  FAM10_DMI_SUPPORT                   ///< Conditionally define F10 support
+  FAM12_DMI_SUPPORT                   ///< Conditionally define F12 support
+  FAM14_DMI_SUPPORT                   ///< Conditionally define F14 support
+  FAM15_OR_DMI_SUPPORT                ///< Conditionally define F15 OR support
+  FAM15_TN_DMI_SUPPORT                ///< Conditionally define F15 TN support
+  NUM_DMI_FAMILIES                    ///< Number of installed families
+} AGESA_DMI_SUPPORTED_FAM;
+
+/*  Declare the Family List. An array of pointers to tables that each describe a family  */
+CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
+  FAM10_DMI_TABLE
+  FAM12_DMI_TABLE
+  FAM14_DMI_TABLE
+  FAM15_OR_DMI_TABLE
+  FAM15_TN_DMI_TABLE
+  NULL
+};
+
+/*  Declare the instance of the DMI option configuration structure  */
+CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
+  DMI_STRUCT_VERSION,
+  USER_DMI_OPTION,
+  USER_DMI_RELEASE_BUFFER,
+  NUM_DMI_FAMILIES,
+  (VOID *((*)[])) &ProcTables           // Compiler says array size must match struct decl
+};
+
+#endif  // _OPTION_DMI_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h
new file mode 100644
index 0000000..7eeea69
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily10hInstall.h
@@ -0,0 +1,2058 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 10h support
+ *
+ * This file generates the defaults tables for family 10h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 60726 $   @e \$Date: 2011-10-20 17:08:02 -0600 (Thu, 20 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_10H_INSTALL_H_
+#define _OPTION_FAMILY_10H_INSTALL_H_
+
+/*
+ * Common Family 10h routines
+ */
+extern F_CPU_DISABLE_PSTATE F10DisablePstate;
+extern F_CPU_TRANSITION_PSTATE F10TransitionPstate;
+extern F_CPU_GET_TSC_RATE F10GetTscRate;
+extern F_CPU_GET_NB_FREQ F10GetCurrentNbFrequency;
+extern F_CPU_AP_INITIAL_LAUNCH F10LaunchApCore;
+extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F10GetApMailboxFromHardware;
+extern F_CPU_SET_AP_CORE_NUMBER F10SetApCoreNumber;
+extern F_CPU_GET_AP_CORE_NUMBER F10GetApCoreNumber;
+extern F_CPU_TRANSFER_AP_CORE_NUMBER F10TransferApCoreNumber;
+extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F10CpuAmdCoreIdPositionInInitialApicId;
+extern F_CPU_SAVE_FEATURES F10SaveFeatures;
+extern F_CPU_WRITE_FEATURES F10WriteFeatures;
+extern F_CPU_SET_WARM_RESET_FLAG F10SetAgesaWarmResetFlag;
+extern F_CPU_GET_WARM_RESET_FLAG F10GetAgesaWarmResetFlag;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString1;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BrandIdString2;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10CacheInfo;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10SysPmTable;
+extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10WheaInitData;
+extern F_CPU_SET_CFOH_REG SetF10CacheFlushOnHaltRegister;
+extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F10GetPlatformTypeSpecificInfo;
+extern F_NEXT_LINK_HAS_HTFPY_FEATS F10NextLinkHasHtPhyFeats;
+extern F_SET_HT_PHY_REGISTER F10SetHtPhyRegister;
+extern F_GET_NEXT_HT_LINK_FEATURES F10GetNextHtLinkFeatures;
+extern CONST REGISTER_TABLE ROMDATA F10PciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MsrRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10HtPhyRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10MultiLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10SingleLinkPciRegisterTable;
+extern CONST REGISTER_TABLE ROMDATA F10WorkaroundsTable;
+extern F_GET_EARLY_INIT_TABLE GetF10EarlyInitOnCoreTable;
+
+
+/*
+ * Install family 10h model 5 support
+ */
+#ifdef OPTION_FAMILY10H_BL
+  #if OPTION_FAMILY10H_BL == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10BlHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10BlMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10BlRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10BlPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10BlMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10BlHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10BlTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10BlServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10BlMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10BlMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10BlRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10BlTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define BL_SOCKETS 1
+    #define BL_MODULES 1
+    #define BL_RECOVERY_SOCKETS 1
+    #define BL_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10BlLogicalIdAndRev;
+    #define OPT_F10_BL_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10BlLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < BL_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS BL_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES BL_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < BL_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES BL_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_BL_UCODE_C6
+      #define F10_BL_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+          #undef F10_BL_UCODE_C6
+          #define F10_BL_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+        #endif
+        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_BL_UCODE_C8
+          #define F10_BL_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10BlMicroCodePatchArray[] =
+      {
+        F10_BL_UCODE_C6
+        F10_BL_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10BlNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10BlMicroCodePatchArray) / sizeof (CpuF10BlMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_BL_CPU {AMD_FAMILY_10_BL, &cpuF10BlServices},
+  #else
+    #define OPT_F10_BL_CPU
+    #define OPT_F10_BL_ID
+  #endif
+#else
+  #define OPT_F10_BL_CPU
+  #define OPT_F10_BL_ID
+#endif
+
+/*
+ * Install family 10h model 6 support
+ */
+#ifdef OPTION_FAMILY10H_DA
+  #if OPTION_FAMILY10H_DA == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10DaHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10DaMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_CPU_SET_CFOH_REG SetF10DaCacheFlushOnHaltRegister;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10DaRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10DaPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10DaMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10DaHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10DaTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10DaServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10DaMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10DaMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10DaRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10DaTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define DA_SOCKETS 1
+    #define DA_MODULES 1
+    #define DA_RECOVERY_SOCKETS 1
+    #define DA_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10DaLogicalIdAndRev;
+    #define OPT_F10_DA_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10DaLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < DA_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS DA_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES DA_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < DA_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES DA_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_DA_UCODE_C7
+      #define F10_DA_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c7;
+          #undef F10_DA_UCODE_C7
+          #define F10_DA_UCODE_C7 &CpuF10MicrocodePatch010000c7,
+        #endif
+        #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE) || (OPTION_AM3_SOCKET_SUPPORT == TRUE) || (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_DA_UCODE_C8
+          #define F10_DA_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10DaMicroCodePatchArray[] =
+      {
+        F10_DA_UCODE_C7
+        F10_DA_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10DaNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10DaMicroCodePatchArray) / sizeof (CpuF10DaMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_DA_CPU {AMD_FAMILY_10_DA, &cpuF10DaServices},
+  #else
+    #define OPT_F10_DA_CPU
+    #define OPT_F10_DA_ID
+  #endif
+#else
+  #define OPT_F10_DA_CPU
+  #define OPT_F10_DA_ID
+#endif
+
+/*
+ * Install family 10h models 8 & 9 support
+ */
+#ifdef OPTION_FAMILY10H_HY
+  #if OPTION_FAMILY10H_HY == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10HyPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10HyHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10HyMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevDGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevDGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevDGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevDGetNbCofVidUpdate;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[];
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevDGetNumberOfPhysicalCores;
+    extern F_GET_EARLY_INIT_TABLE GetF10HyEarlyInitOnCoreTable;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10HyRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10MultiLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10HyPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10HyMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HyHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10HyTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10HyServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevDGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevDGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevDGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevDGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevDGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10HyMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10HyMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10HyRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10HyTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
+      #else
+        NULL,
+      #endif
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_C32_SOCKET_SUPPORT == TRUE
+          GetF10HyEarlyInitOnCoreTable
+        #else
+          GetF10EarlyInitOnCoreTable
+        #endif
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define HY_SOCKETS 8
+    #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
+      #define HY_MODULES 2
+    #else
+      #define HY_MODULES 1
+    #endif
+    #define HY_RECOVERY_SOCKETS 1
+    #define HY_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10HyLogicalIdAndRev;
+    #define OPT_F10_HY_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10HyLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < HY_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS HY_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES HY_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < HY_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES HY_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_HY_UCODE_D9
+      #define F10_HY_UCODE_C5
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_C32_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c5;
+          #undef F10_HY_UCODE_C5
+          #define F10_HY_UCODE_C5 &CpuF10MicrocodePatch010000c5,
+        #endif
+        #if (OPTION_C32_SOCKET_SUPPORT == TRUE) || (OPTION_G34_SOCKET_SUPPORT == TRUE)
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000d9;
+          #undef F10_HY_UCODE_D9
+          #define F10_HY_UCODE_D9 &CpuF10MicrocodePatch010000d9,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10HyMicroCodePatchArray[] =
+      {
+        F10_HY_UCODE_D9
+        F10_HY_UCODE_C5
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10HyNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10HyMicroCodePatchArray) / sizeof (CpuF10HyMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_HY_CPU {AMD_FAMILY_10_HY, &cpuF10HyServices},
+  #else
+    #define OPT_F10_HY_CPU
+    #define OPT_F10_HY_ID
+  #endif
+#else
+  #define OPT_F10_HY_CPU
+  #define OPT_F10_HY_ID
+#endif
+
+/*
+ * Install family 10h model 10 support
+ */
+#ifdef OPTION_FAMILY10H_PH
+  #if OPTION_FAMILY10H_PH == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10PhHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10PhMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevEGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevEGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevEGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevEGetNbCofVidUpdate;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevEGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10PhRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevEPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevEMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevEHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10PhHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10PhTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10PhServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevEGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevEGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevEGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevEGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevEGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10PhMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10PhMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10PhRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10PhTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define PH_SOCKETS 1
+    #define PH_MODULES 1
+    #define PH_RECOVERY_SOCKETS 1
+    #define PH_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10PhLogicalIdAndRev;
+    #define OPT_F10_PH_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10PhLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < PH_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS PH_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES PH_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < PH_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES PH_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_PH_UCODE_BF
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000bf;
+          #undef F10_PH_UCODE_BF
+          #define F10_PH_UCODE_BF &CpuF10MicrocodePatch010000bf,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10PhMicroCodePatchArray[] =
+      {
+        F10_PH_UCODE_BF
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10PhNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10PhMicroCodePatchArray) / sizeof (CpuF10PhMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_PH_CPU {AMD_FAMILY_10_PH, &cpuF10PhServices},
+  #else
+    #define OPT_F10_PH_CPU
+    #define OPT_F10_PH_ID
+  #endif
+#else
+  #define OPT_F10_PH_CPU
+  #define OPT_F10_PH_ID
+#endif
+
+
+/*
+ * Install family 10h model 4 support
+ */
+#ifdef OPTION_FAMILY10H_RB
+  #if OPTION_FAMILY10H_RB == TRUE
+    extern CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F10RbHtPhyRegisterTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF10RbMicrocodeEquivalenceTable;
+    extern F_CPU_GET_IDD_MAX F10CommonRevCGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F10CommonRevCGetNbPstateInfo;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F10RevCGetMinMaxNbFrequency;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F10CommonRevCGetNbCofVidUpdate;
+    extern F_IS_NB_PSTATE_ENABLED F10CommonRevCIsNbPstateEnabled;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F10CommonRevCGetNumberOfPhysicalCores;
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F10RbRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F10PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10MultiLinkPciRegisterTable,
+          &F10SingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RevCPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F10RbPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F10MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RevCMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F10RbMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10HtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RevCHtPhyRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F10RbHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F10WorkaroundsTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10RbTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtPhyProfileRegister, SetRegisterForHtPhyProfileEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10RbServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F10DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F10TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F10CommonRevCGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F10GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10GetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10RevCGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F10CommonRevCGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F10CommonRevCGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F10LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F10CommonRevCGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F10GetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F10SetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F10GetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F10TransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F10CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        F10SaveFeatures,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        F10WriteFeatures,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F10SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F10GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        GetF10BrandIdString1,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        GetF10BrandIdString2,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF10RbMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF10RbMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF10CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF10SysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF10WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        F10GetPlatformTypeSpecificInfo,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F10CommonRevCIsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F10SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F10GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F10RbRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10RbTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      NULL,
+      NULL,
+      InitCacheDisabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF10EarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define RB_SOCKETS 8
+    #define RB_MODULES 1
+    #define RB_RECOVERY_SOCKETS 1
+    #define RB_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF10RbLogicalIdAndRev;
+    #define OPT_F10_RB_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF10RbLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < RB_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS RB_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES RB_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < RB_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES RB_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F10_RB_UCODE_85
+      #define F10_RB_UCODE_C6
+      #define F10_RB_UCODE_C8
+
+      // If a patch is required for recovery mode to function properly, add a
+      // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_AM3_SOCKET_SUPPORT == TRUE
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch01000085;
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c6;
+          extern  CONST MICROCODE_PATCHES ROMDATA CpuF10MicrocodePatch010000c8;
+          #undef F10_RB_UCODE_85
+          #define F10_RB_UCODE_85 &CpuF10MicrocodePatch01000085,
+          #undef F10_RB_UCODE_C6
+          #define F10_RB_UCODE_C6 &CpuF10MicrocodePatch010000c6,
+          #undef F10_RB_UCODE_C8
+          #define F10_RB_UCODE_C8 &CpuF10MicrocodePatch010000c8,
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES ROMDATA *CpuF10RbMicroCodePatchArray[] =
+      {
+        F10_RB_UCODE_85
+        F10_RB_UCODE_C6
+        F10_RB_UCODE_C8
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF10RbNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF10RbMicroCodePatchArray) / sizeof (CpuF10RbMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F10_RB_CPU {AMD_FAMILY_10_RB, &cpuF10RbServices},
+  #else
+    #define OPT_F10_RB_CPU
+    #define OPT_F10_RB_ID
+  #endif
+#else
+  #define OPT_F10_RB_CPU
+  #define OPT_F10_RB_ID
+#endif
+
+
+/*
+ * Install unknown family 10h support
+ */
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST REGISTER_TABLE ROMDATA *F10UnknownRegisterTables[] =
+  {
+    #if BASE_FAMILY_PCI == TRUE
+      &F10PciRegisterTable,
+    #endif
+    #if BASE_FAMILY_MSR == TRUE
+      &F10MsrRegisterTable,
+    #endif
+    #if BASE_FAMILY_HT_PCI == TRUE
+      &F10HtPhyRegisterTable,
+    #endif
+    #if OPTION_MULTISOCKET == TRUE
+      #if MODEL_SPECIFIC_PCI == TRUE
+        &F10MultiLinkPciRegisterTable,
+      #endif
+    #endif
+    #if OPTION_MULTISOCKET == FALSE
+      #if MODEL_SPECIFIC_PCI == TRUE
+        &F10SingleLinkPciRegisterTable,
+      #endif
+    #endif
+    #if BASE_FAMILY_WORKAROUNDS == TRUE
+      &F10WorkaroundsTable,
+    #endif
+    // the end.
+    NULL
+  };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F10UnknownTableEntryTypeDescriptors[] =
+  {
+    {MsrRegister, SetRegisterForMsrEntry},
+    {PciRegister, SetRegisterForPciEntry},
+    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+    {HtPhyRegister, SetRegisterForHtPhyEntry},
+    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+    {HtHostPciRegister, SetRegisterForHtHostEntry},
+    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+    // End
+    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+  };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF10UnknownServices =
+{
+  0,
+  #if DISABLE_PSTATE == TRUE
+    F10DisablePstate,
+  #else
+    (PF_CPU_DISABLE_PSTATE) CommonAssert,
+  #endif
+  #if TRANSITION_PSTATE == TRUE
+    F10TransitionPstate,
+  #else
+    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+  #endif
+  #if PROC_IDD_MAX == TRUE
+    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_IDD_MAX) CommonAssert,
+  #endif
+  #if GET_TSC_RATE == TRUE
+    F10GetTscRate,
+  #else
+    (PF_CPU_GET_TSC_RATE) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    F10GetCurrentNbFrequency,
+  #else
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #endif
+  #if IS_NBCOF_INIT_NEEDED == TRUE
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+  #else
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+  #endif
+  #if GET_NB_IDD_MAX == TRUE
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #endif
+  #if AP_INITIAL_LAUNCH == TRUE
+    F10LaunchApCore,
+  #else
+    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+  #endif
+  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonReturnZero8,
+  #else
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+  #endif
+  #if GET_AP_MAILBOX_FROM_HW == TRUE
+    F10GetApMailboxFromHardware,
+  #else
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #endif
+  #if SET_AP_CORE_NUMBER == TRUE
+    F10SetApCoreNumber,
+  #else
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if GET_AP_CORE_NUMBER == TRUE
+    F10GetApCoreNumber,
+  #else
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if TRANSFER_AP_CORE_NUMBER == TRUE
+    F10TransferApCoreNumber,
+  #else
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if ID_POSITION_INITIAL_APICID == TRUE
+    F10CpuAmdCoreIdPositionInInitialApicId,
+  #else
+    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+  #endif
+  #if SAVE_FEATURES == TRUE
+    F10SaveFeatures,
+  #else
+    (PF_CPU_SAVE_FEATURES) CommonAssert,
+  #endif
+  #if WRITE_FEATURES == TRUE
+    F10WriteFeatures,
+  #else
+    (PF_CPU_WRITE_FEATURES) CommonAssert,
+  #endif
+  #if SET_WARM_RESET_FLAG == TRUE
+    F10SetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if GET_WARM_RESET_FLAG == TRUE
+    F10GetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if BRAND_STRING1 == TRUE
+    GetF10BrandIdString1,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if BRAND_STRING2 == TRUE
+    GetF10BrandIdString2,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_CACHE_INFO == TRUE
+    GetF10CacheInfo,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_SYSTEM_PM_TABLE == TRUE
+    GetF10SysPmTable,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_WHEA_INIT == TRUE
+    GetF10WheaInitData,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+    F10GetPlatformTypeSpecificInfo,
+  #else
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+  #endif
+  #if IS_NB_PSTATE_ENABLED == TRUE
+    (PF_IS_NB_PSTATE_ENABLED) CommonReturnFalse,
+  #else
+    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F10NextLinkHasHtPhyFeats,
+  #else
+    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F10SetHtPhyRegister,
+  #else
+    (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  #endif
+  #if BASE_FAMILY_PCI == TRUE
+    F10GetNextHtLinkFeatures,
+  #else
+    (PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (REGISTER_TABLE **) F10UnknownRegisterTables,
+  #else
+    NULL,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F10UnknownTableEntryTypeDescriptors,
+  #else
+    NULL,
+  #endif
+  NULL,
+  NULL,
+  InitCacheDisabled,
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    GetF10EarlyInitOnCoreTable
+  #else
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #endif
+};
+
+// Family 10h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+  #undef  FAMILY_MMIO_BASE_MASK
+  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+#undef OPT_F10_ID_TABLE
+#define OPT_F10_ID_TABLE {0x10, {AMD_FAMILY_10, AMD_F10_UNKNOWN}, F10LogicalIdTable, (sizeof (F10LogicalIdTable) / sizeof (F10LogicalIdTable[0]))},
+#define OPT_F10_UNKNOWN_CPU {AMD_FAMILY_10, &cpuF10UnknownServices},
+
+#undef OPT_F10_TABLE
+#define OPT_F10_TABLE   OPT_F10_BL_CPU  OPT_F10_DA_CPU  OPT_F10_HY_CPU  OPT_F10_PH_CPU  OPT_F10_RB_CPU  OPT_F10_UNKNOWN_CPU
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayG34;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayG34;
+  #define F10_G34_BRANDSTRING1 &F10BrandIdString1ArrayG34,
+  #define F10_G34_BRANDSTRING2 &F10BrandIdString2ArrayG34,
+#else
+  #define F10_G34_BRANDSTRING1
+  #define F10_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayC32;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayC32;
+  #define F10_C32_BRANDSTRING1 &F10BrandIdString1ArrayC32,
+  #define F10_C32_BRANDSTRING2 &F10BrandIdString2ArrayC32,
+#else
+  #define F10_C32_BRANDSTRING1
+  #define F10_C32_BRANDSTRING2
+#endif
+#if OPTION_S1G3_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g3;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g3;
+  #define F10_S1G3_BRANDSTRING1 &F10BrandIdString1ArrayS1g3,
+  #define F10_S1G3_BRANDSTRING2 &F10BrandIdString2ArrayS1g3,
+#else
+  #define F10_S1G3_BRANDSTRING1
+  #define F10_S1G3_BRANDSTRING2
+#endif
+#if OPTION_S1G4_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayS1g4;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayS1g4;
+  #define F10_S1G4_BRANDSTRING1 &F10BrandIdString1ArrayS1g4,
+  #define F10_S1G4_BRANDSTRING2 &F10BrandIdString2ArrayS1g4,
+#else
+  #define F10_S1G4_BRANDSTRING1
+  #define F10_S1G4_BRANDSTRING2
+#endif
+#if OPTION_ASB2_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAsb2;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAsb2;
+  #define F10_ASB2_BRANDSTRING1 &F10BrandIdString1ArrayAsb2,
+  #define F10_ASB2_BRANDSTRING2 &F10BrandIdString2ArrayAsb2,
+#else
+  #define F10_ASB2_BRANDSTRING1
+  #define F10_ASB2_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString1ArrayAm3;
+  extern CONST CPU_BRAND_TABLE ROMDATA F10BrandIdString2ArrayAm3;
+  #define F10_AM3_BRANDSTRING1 &F10BrandIdString1ArrayAm3,
+  #define F10_AM3_BRANDSTRING2 &F10BrandIdString2ArrayAm3,
+#else
+  #define F10_AM3_BRANDSTRING1
+  #define F10_AM3_BRANDSTRING2
+#endif
+
+#if BRAND_STRING1 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString1Tables[] =
+  {
+    F10_G34_BRANDSTRING1
+    F10_C32_BRANDSTRING1
+    F10_S1G3_BRANDSTRING1
+    F10_S1G4_BRANDSTRING1
+    F10_ASB2_BRANDSTRING1
+    F10_AM3_BRANDSTRING1
+  };
+
+  CONST UINT8 F10BrandIdString1TableCount = (sizeof (F10BrandIdString1Tables) / sizeof (F10BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F10BrandIdString2Tables[] =
+  {
+    F10_G34_BRANDSTRING2
+    F10_C32_BRANDSTRING2
+    F10_S1G3_BRANDSTRING2
+    F10_S1G4_BRANDSTRING2
+    F10_ASB2_BRANDSTRING2
+    F10_AM3_BRANDSTRING2
+  };
+
+  CONST UINT8 F10BrandIdString2TableCount = (sizeof (F10BrandIdString2Tables) / sizeof (F10BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F10LogicalIdTable[] =
+{
+  OPT_F10_BL_ID
+  OPT_F10_DA_ID
+  OPT_F10_HY_ID
+  OPT_F10_PH_ID
+  OPT_F10_RB_ID
+};
+
+#endif  // _OPTION_FAMILY_10H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h
new file mode 100644
index 0000000..9d77332
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hEarlySample.h
@@ -0,0 +1,231 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Family 15h 'early sample' support
+ *
+ * This file defines the required structures for family 15h pre-production processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 53356 $   @e \$Date: 2011-05-18 14:14:18 -0600 (Wed, 18 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
+#define _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
+
+
+/*---------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+
+/*
+ * Install family 15h model 0x00 - 0x0F Early Sample support
+ */
+
+/**
+ *  Early sample hook point during HTC initialization
+ *
+ *  @param[in,out] HtcRegister             Value of F3x64 to be written.
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_HTC_INIT_HOOK (
+  IN OUT   UINT32  *HtcRegister,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_HTC_INIT_HOOK *PF_F15_OR_ES_HTC_INIT_HOOK;
+
+/// Hook points in the core functionality necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_HTC_INIT_HOOK     F15OrHtcInitHook;    ///< Allows for override of a certain processor register value during HTC init
+} F15_OR_ES_CORE_SUPPORT;
+
+/**
+ *  Returns whether or not the processor should enable the CPB feature.
+ *
+ *  @param[in,out] IsEnabled               Whether or not to enable CPB
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_IS_CPB_SUPPORTED (
+  IN OUT   BOOLEAN *IsEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_IS_CPB_SUPPORTED *PF_F15_OR_ES_IS_CPB_SUPPORTED;
+
+
+
+/// Hook points in the CPB feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_IS_CPB_SUPPORTED    F15OrIsCpbSupportedHook;   ///< CPB enablement override
+} F15_OR_ES_CPB_SUPPORT;
+
+/**
+ *  Returns whether or not the processor should enable the C6 feature.
+ *
+ *  @param[in,out] IsEnabled               Whether or not to enable C6
+ *  @param[in]     StdHeader               Handle of Header for calling lib functions and services.
+ *
+ */
+typedef VOID F_F15_OR_ES_IS_C6_SUPPORTED (
+  IN OUT   BOOLEAN *IsEnabled,
+  IN       AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_IS_C6_SUPPORTED *PF_F15_OR_ES_IS_C6_SUPPORTED;
+
+
+
+/// Hook points in the C6 feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_IS_C6_SUPPORTED    F15OrIsC6SupportedHook;   ///< C6 enablement override
+} F15_OR_ES_C6_SUPPORT;
+
+
+/**
+ *  Workaround to avoid patch loading from causing NB cycles
+ *
+ *  @param[in,out] StdHeader     - Config handle for library and services.
+ *  @param[in,out] SavedMsrValue - Saved a MSR value
+ *
+ */
+typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_START (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT64            *SavedMsrValue
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AVOID_NB_CYCLES_START *PF_F15_OR_ES_AVOID_NB_CYCLES_START;
+
+/**
+ *  Workaround to avoid patch loading from causing NB cycles
+ *
+ *  @param[in,out] StdHeader - Config handle for library and services.
+ *  @param[in] SavedMsrValue - Saved a MSR value
+ *
+ *
+ */
+typedef VOID F_F15_OR_ES_AVOID_NB_CYCLES_END (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       UINT64            *SavedMsrValue
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AVOID_NB_CYCLES_END *PF_F15_OR_ES_AVOID_NB_CYCLES_END;
+
+/**
+ *  Workaround for Ax processors after patch is loaded.
+ *
+ *  @param[in] StdHeader     - Config handle for library and services.
+ *  @param[in] IsPatchLoaded - Is patch loaded
+ *
+ *
+ */
+typedef VOID F_F15_OR_ES_AFTER_PATCH_LOADED (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader,
+  IN       BOOLEAN IsPatchLoaded
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_AFTER_PATCH_LOADED *PF_F15_OR_ES_AFTER_PATCH_LOADED;
+
+/**
+ *  Update the CPU microcode.
+ *
+ *  @param[in] StdHeader   - Config handle for library and services.
+ *
+ *  @retval    TRUE   - Patch Loaded Successfully.
+ *  @retval    FALSE  - Patch Did Not Get Loaded.
+ *
+ */
+typedef BOOLEAN F_F15_OR_ES_LOAD_MCU_PATCH (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_OR_ES_LOAD_MCU_PATCH *PF_F15_OR_ES_LOAD_MCU_PATCH;
+
+
+/// Hook points in the Microcode Update feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_OR_ES_AVOID_NB_CYCLES_START  F15OrESAvoidNbCyclesStart; ///< Workaround to avoid patch loading from causing NB cycles
+  PF_F15_OR_ES_AVOID_NB_CYCLES_END    F15OrESAvoidNbCyclesEnd;   ///< Workaround to avoid patch loading from causing NB cycles
+  PF_F15_OR_ES_LOAD_MCU_PATCH         F15OrUpdateMcuPatchHook;   ///< Processor MCU Update override
+  PF_F15_OR_ES_AFTER_PATCH_LOADED     F15OrESAfterPatchLoaded;   ///< Workaround for Ax processors after patch is loaded
+} F15_OR_ES_MCU_PATCH;
+
+
+
+typedef BOOLEAN F_F15_TN_ES_LOAD_MCU_PATCH (
+  IN OUT   AMD_CONFIG_PARAMS *StdHeader
+  );
+
+/// Reference to a Method.
+typedef F_F15_TN_ES_LOAD_MCU_PATCH *PF_F15_TN_ES_LOAD_MCU_PATCH;
+
+/// Hook points in the Microcode Update feature necessary for
+/// providing support for pre-production CPUs.
+typedef struct {
+  PF_F15_TN_ES_LOAD_MCU_PATCH    F15TnUpdateMcuPatchHook;   ///< Processor MCU Update override
+} F15_TN_ES_MCU_PATCH;
+
+/*---------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_FAMILY_15H_EARLY_SAMPLE_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
new file mode 100644
index 0000000..73eeb6f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFamily15hInstall.h
@@ -0,0 +1,1570 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of family 15h support
+ *
+ * This file generates the defaults tables for family 15h processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 60770 $   @e \$Date: 2011-10-21 15:51:10 -0600 (Fri, 21 Oct 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_FAMILY_15H_INSTALL_H_
+#define _OPTION_FAMILY_15H_INSTALL_H_
+
+#include "OptionFamily15hEarlySample.h"
+
+/*
+ * Pull in family specific services based on entry point
+ */
+
+/*
+ * Common Family 15h routines
+ */
+extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
+
+/*
+ * Install family 15h model 0 support
+ */
+#ifdef OPTION_FAMILY15H_OR
+  #if OPTION_FAMILY15H_OR == TRUE
+    extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
+    extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
+    extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
+    extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrAM3MsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleWorkaroundsTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrWorkaroundTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleSharedMsrRegisterTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySamplePciRegisterTable;
+      extern CONST REGISTER_TABLE ROMDATA F15OrEarlySampleMsrRegisterTable;
+    #endif
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
+      {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
+      {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15OrMultiLinkPciRegisterTable,
+          &F15OrSingleLinkPciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15OrPciRegisterTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySamplePciRegisterTable,
+          #endif
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15OrMsrRegisterTable,
+          #if (OPTION_AM3_SOCKET_SUPPORT == TRUE) && (CFG_FORCE_MICROSERVER == FALSE)
+            &F15OrAM3MsrWorkaroundTable,
+          #endif
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleMsrRegisterTable,
+          #endif
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15OrSharedMsrRegisterTable,
+          &F15OrSharedMsrCuRegisterTable,
+          &F15OrSharedMsrWorkaroundTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleSharedMsrRegisterTable,
+            &F15OrEarlySampleSharedMsrWorkaroundTable,
+          #endif
+        #endif
+        #if MODEL_SPECIFIC_HT_PCI == TRUE
+          &F15OrHtPhyRegisterTable,
+        #endif
+        #if BASE_FAMILY_WORKAROUNDS == TRUE
+          &F15OrWorkaroundsTable,
+          #if OPTION_EARLY_SAMPLES == TRUE
+            &F15OrEarlySampleWorkaroundsTable,
+          #endif
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15OrGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15OrGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15OrGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15OrGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F15OrSetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15OrGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F15OrTransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        // F15OrSaveFeatures,
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        // F15OrWriteFeatures,
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15OrMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15OrMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15OrSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15OrRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15CorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15OrEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define OR_SOCKETS 8
+    #define OR_MODULES 2
+    #define OR_RECOVERY_SOCKETS 1
+    #define OR_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
+    #define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES OR_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < OR_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES OR_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F15_OR_UCODE_17_UNENC
+      #define F15_OR_UCODE_11F_UNENC
+      #define F15_OR_UCODE_425
+      #define F15_OR_UCODE_50D
+      #define F15_OR_UCODE_624
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+          extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000425 [];
+          #undef F15_OR_UCODE_425
+          #define F15_OR_UCODE_425 CpuF15OrMicrocodePatch06000425,
+
+          extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch0600050D_Enc [];
+          #undef F15_OR_UCODE_50D
+          #define F15_OR_UCODE_50D CpuF15OrMicrocodePatch0600050D_Enc,
+        #endif
+        extern  CONST UINT8 ROMDATA CpuF15OrMicrocodePatch06000624_Enc [];
+        #undef F15_OR_UCODE_624
+        #define F15_OR_UCODE_624 CpuF15OrMicrocodePatch06000624_Enc,
+      #endif
+
+      CONST UINT8 ROMDATA *CpuF15OrMicroCodePatchArray[] =
+      {
+        F15_OR_UCODE_624
+        F15_OR_UCODE_50D
+        F15_OR_UCODE_425
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_OR_ES_AVOID_NB_CYCLES_START F15OrEarlySamplesAvoidNbCyclesStart;
+      extern F_F15_OR_ES_AVOID_NB_CYCLES_END F15OrEarlySamplesAvoidNbCyclesEnd;
+      extern F_F15_OR_ES_LOAD_MCU_PATCH F15OrEarlySamplesLoadMicrocodePatch;
+      extern F_F15_OR_ES_AFTER_PATCH_LOADED F15OrEarlySamplesAfterPatchLoaded;
+
+      CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
+      {
+        F15OrEarlySamplesAvoidNbCyclesStart,
+        F15OrEarlySamplesAvoidNbCyclesEnd,
+        F15OrEarlySamplesLoadMicrocodePatch,
+        F15OrEarlySamplesAfterPatchLoaded
+      };
+    #else
+      CONST F15_OR_ES_MCU_PATCH ROMDATA F15OrEarlySampleLoadMcuPatch =
+      {
+        (PF_F15_OR_ES_AVOID_NB_CYCLES_START)  CommonVoid,
+        (PF_F15_OR_ES_AVOID_NB_CYCLES_END)    CommonVoid,
+        (PF_F15_OR_ES_LOAD_MCU_PATCH)         LoadMicrocodePatch,
+        (PF_F15_OR_ES_AFTER_PATCH_LOADED)     CommonVoid
+      };
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
+
+      CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
+      {
+        #if AGESA_ENTRY_INIT_EARLY == TRUE
+          F15OrHtcInitEarlySampleHook,
+        #else
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
+        #endif
+      };
+    #else
+      CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
+      {
+        #if AGESA_ENTRY_INIT_EARLY == TRUE
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
+        #else
+          (PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
+        #endif
+      };
+    #endif
+
+    #define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
+
+  #else  //  OPTION_FAMILY15H_OR == TRUE
+    #define OPT_F15_OR_CPU
+    #define OPT_F15_OR_ID
+  #endif  //  OPTION_FAMILY15H_OR == TRUE
+#else  //  defined (OPTION_FAMILY15H_OR)
+  #define OPT_F15_OR_CPU
+  #define OPT_F15_OR_ID
+#endif  //  defined (OPTION_FAMILY15H_OR)
+
+
+/*
+ * Install family 15h model 10h - 1Fh support
+ */
+#ifdef OPTION_FAMILY15H_TN
+  #if OPTION_FAMILY15H_TN == TRUE
+    extern F_CPU_GET_IDD_MAX F15TnGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15TnGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_GET_NB_IDD_MAX F15TnGetNbIddMax;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15TnGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15TnGetMinMaxNbFrequency;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15TnGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15TnGetApMailboxFromHardware;
+    extern F_CPU_GET_AP_CORE_NUMBER F15TnGetApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15TnCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15TnMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15TnEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15TnSharedMsrWorkaroundTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15TnCorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15TnPciRegisterTable,
+          &F15TnPciWorkaroundTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15TnMsrRegisterTable,
+          &F15TnSharedMsrRegisterTable,
+          &F15TnSharedMsrCuRegisterTable,
+          &F15TnSharedMsrWorkaroundTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15TnTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15TnServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15TnGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15TnGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) F15TnGetNbIddMax,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15TnGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15TnGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15TnGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15TnMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15TnMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15TnSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15TnRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15TnTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        NULL,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15TnCorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15TnEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define TN_SOCKETS 1
+    #define TN_MODULES 1
+    #define TN_RECOVERY_SOCKETS 1
+    #define TN_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15TnLogicalIdAndRev;
+    #define OPT_F15_TN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15TnLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < TN_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS TN_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES TN_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < TN_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES TN_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+      #define F15_TN_UCODE_04
+      #define F15_TN_UCODE_04_UNENC
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+          extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004_Unenc [];
+          #undef F15_TN_UCODE_04_UNENC
+          #define F15_TN_UCODE_04_UNENC CpuF15TnMicrocodePatch06001004_Unenc,
+
+          extern  CONST UINT8 ROMDATA CpuF15TnMicrocodePatch06001004 [];
+          #undef F15_TN_UCODE_04
+          #define F15_TN_UCODE_04 CpuF15TnMicrocodePatch06001004,
+        #endif
+      #endif
+
+      CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] =
+      {
+        F15_TN_UCODE_04
+        F15_TN_UCODE_04_UNENC
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15TnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15TnMicroCodePatchArray) / sizeof (CpuF15TnMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #if OPTION_EARLY_SAMPLES == TRUE
+      extern F_F15_TN_ES_LOAD_MCU_PATCH F15TnEarlySamplesLoadMicrocodePatch;
+
+      CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
+      {
+        F15TnEarlySamplesLoadMicrocodePatch
+      };
+    #else
+      CONST F15_TN_ES_MCU_PATCH ROMDATA F15TnEarlySampleLoadMcuPatch =
+      {
+        (PF_F15_TN_ES_LOAD_MCU_PATCH) LoadMicrocodePatch
+      };
+    #endif
+
+    #define OPT_F15_TN_CPU {AMD_FAMILY_15_TN, &cpuF15TnServices},
+
+  #else  //  OPTION_FAMILY15H_TN == TRUE
+    #define OPT_F15_TN_CPU
+    #define OPT_F15_TN_ID
+  #endif  //  OPTION_FAMILY15H_TN == TRUE
+#else  //  defined (OPTION_FAMILY15H_TN)
+  #define OPT_F15_TN_CPU
+  #define OPT_F15_TN_ID
+#endif  //  defined (OPTION_FAMILY15H_TN)
+
+/*
+ * Install family 15h model 20h - 2Fh support
+ */
+#ifdef OPTION_FAMILY15H_KM
+  #if OPTION_FAMILY15H_KM == TRUE
+    extern F_CPU_GET_IDD_MAX F15KmGetProcIddMax;
+    extern F_CPU_GET_NB_PSTATE_INFO F15KmGetNbPstateInfo;
+    extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
+    extern F_CPU_DISABLE_PSTATE F15DisablePstate;
+    extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
+    extern F_CPU_GET_TSC_RATE F15GetTscRate;
+    extern F_CPU_GET_NB_FREQ F15KmGetCurrentNbFrequency;
+    extern F_CPU_GET_MIN_MAX_NB_FREQ F15KmGetMinMaxNbFrequency;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
+    extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
+    extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15KmGetNumberOfPhysicalCores;
+    extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15KmGetApMailboxFromHardware;
+    extern F_CPU_SET_AP_CORE_NUMBER F15KmSetApCoreNumber;
+    extern F_CPU_GET_AP_CORE_NUMBER F15KmGetApCoreNumber;
+    extern F_CPU_TRANSFER_AP_CORE_NUMBER F15KmTransferApCoreNumber;
+    extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
+    extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
+    extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmSysPmTable;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
+    extern F_CPU_SET_CFOH_REG SetF15KmCacheFlushOnHaltRegister;
+    extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
+    extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
+    extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicroCodePatchesStruct;
+    extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15KmMicrocodeEquivalenceTable;
+    extern F_GET_EARLY_INIT_TABLE GetF15KmEarlyInitOnCoreTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmPciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15KmSharedMsrCuRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
+    extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
+    extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15Mod2xPackageLinkMap[];
+    /**
+     * Core Pair and core pair primary determination table.
+     *
+     * The two fields from the core pair hardware register can be used to determine whether
+     * even number cores are primary or all cores are primary.  It can be extended if it is
+     * decided to have other configs as well.  The other logically possible value sets are BitMapMapping,
+     * but they are currently not supported by the processor.
+     */
+    CONST CORE_PAIR_MAP ROMDATA HtFam15KmCorePairMapping[] =
+    {
+      {1, 1, EvenCoresMapping},                                     ///< 1 Compute Unit with 2 cores
+      {3, 3, EvenCoresMapping},                                     ///< 2 Compute Units both with 2 Cores
+      {7, 7, EvenCoresMapping},                                     ///< 3 Compute Units all with 2 Cores
+      {0xF, 0xF, EvenCoresMapping},                                 ///< 4 Compute Units all with 2 Cores
+      {0x1F, 0x1F, EvenCoresMapping},                               ///< 5 Compute Units all with 2 Cores
+      {1, 0, AllCoresMapping},                                      ///< 1 Compute Unit with 1 core
+      {3, 0, AllCoresMapping},                                      ///< 2 Compute Units both with 1 Core
+      {7, 0, AllCoresMapping},                                      ///< 3 Compute Units all with 1 Core
+      {0xF, 0, AllCoresMapping},                                    ///< 4 Compute Units all with 1 Core
+      {0x1F, 0, AllCoresMapping},                                   ///< 5 Compute Units all with 1 Core
+      {HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping}   ///< End
+    };
+
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST REGISTER_TABLE ROMDATA *F15KmRegisterTables[] =
+      {
+        #if BASE_FAMILY_PCI == TRUE
+          &F15PciRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F15KmPciRegisterTable,
+        #endif
+        #if BASE_FAMILY_MSR == TRUE
+          &F15MsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15KmMsrRegisterTable,
+        #endif
+        #if MODEL_SPECIFIC_MSR == TRUE
+          &F15KmSharedMsrRegisterTable,
+          &F15KmSharedMsrCuRegisterTable,
+        #endif
+        // the end.
+        NULL
+      };
+    #endif
+
+    #if USES_REGISTER_TABLES == TRUE
+      CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15KmTableEntryTypeDescriptors[] =
+      {
+        {MsrRegister, SetRegisterForMsrEntry},
+        {PciRegister, SetRegisterForPciEntry},
+        {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+        {HtPhyRegister, SetRegisterForHtPhyEntry},
+        {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+        {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+        {HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
+        {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+        {HtHostPciRegister, SetRegisterForHtHostEntry},
+        {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+        {HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
+        {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+        {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+        {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+        {TokenPciRegister, SetRegisterForTokenPciEntry},
+        {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+        {HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
+        {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+        // End
+        {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+      };
+    #endif
+
+    CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15KmServices =
+    {
+      0,
+      #if DISABLE_PSTATE == TRUE
+        F15DisablePstate,
+      #else
+        (PF_CPU_DISABLE_PSTATE) CommonAssert,
+      #endif
+      #if TRANSITION_PSTATE == TRUE
+        F15TransitionPstate,
+      #else
+        (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+      #endif
+      #if PROC_IDD_MAX == TRUE
+        F15KmGetProcIddMax,
+      #else
+        (PF_CPU_GET_IDD_MAX) CommonAssert,
+      #endif
+      #if GET_TSC_RATE == TRUE
+        F15GetTscRate,
+      #else
+        (PF_CPU_GET_TSC_RATE) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetCurrentNbFrequency,
+      #else
+        (PF_CPU_GET_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetMinMaxNbFrequency,
+      #else
+        (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+      #endif
+      #if GET_NB_FREQ == TRUE
+        F15KmGetNbPstateInfo,
+      #else
+        (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+      #endif
+      #if IS_NBCOF_INIT_NEEDED == TRUE
+        F15CommonGetNbCofVidUpdate,
+      #else
+        (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+      #endif
+      #if GET_NB_IDD_MAX == TRUE
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #else
+        (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+      #endif
+      #if AP_INITIAL_LAUNCH == TRUE
+        F15LaunchApCore,
+      #else
+        (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+      #endif
+      #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+        F15KmGetNumberOfPhysicalCores,
+      #else
+        (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+      #endif
+      #if GET_AP_MAILBOX_FROM_HW == TRUE
+        F15KmGetApMailboxFromHardware,
+      #else
+        (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+      #endif
+      #if SET_AP_CORE_NUMBER == TRUE
+        F15KmSetApCoreNumber,
+      #else
+        (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if GET_AP_CORE_NUMBER == TRUE
+        F15KmGetApCoreNumber,
+      #else
+        (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if TRANSFER_AP_CORE_NUMBER == TRUE
+        F15KmTransferApCoreNumber,
+      #else
+        (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+      #endif
+      #if ID_POSITION_INITIAL_APICID == TRUE
+        F15CpuAmdCoreIdPositionInInitialApicId,
+      #else
+        (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+      #endif
+      #if SAVE_FEATURES == TRUE
+        (PF_CPU_SAVE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_SAVE_FEATURES) CommonAssert,
+      #endif
+      #if WRITE_FEATURES == TRUE
+        (PF_CPU_WRITE_FEATURES) CommonVoid,
+      #else
+        (PF_CPU_WRITE_FEATURES) CommonAssert,
+      #endif
+      #if SET_WARM_RESET_FLAG == TRUE
+        F15SetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if GET_WARM_RESET_FLAG == TRUE
+        F15GetAgesaWarmResetFlag,
+      #else
+        (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+      #endif
+      #if BRAND_STRING1 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if BRAND_STRING2 == TRUE
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES == TRUE
+        GetF15KmMicroCodePatchesStruct,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+        GetF15KmMicrocodeEquivalenceTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_CACHE_INFO == TRUE
+        GetF15CacheInfo,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_SYSTEM_PM_TABLE == TRUE
+        GetF15KmSysPmTable,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_WHEA_INIT == TRUE
+        GetF15WheaInitData,
+      #else
+        (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+      #endif
+      #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+      #else
+        (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+      #endif
+      #if IS_NB_PSTATE_ENABLED == TRUE
+        F15IsNbPstateEnabled,
+      #else
+        (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15NextLinkHasHtPhyFeats,
+      #else
+        (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+      #endif
+      #if (BASE_FAMILY_HT_PCI == TRUE)
+        F15SetHtPhyRegister,
+      #else
+        (PF_SET_HT_PHY_REGISTER) CommonAssert,
+      #endif
+      #if BASE_FAMILY_PCI == TRUE
+        F15GetNextHtLinkFeatures,
+      #else
+        (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (REGISTER_TABLE **) F15KmRegisterTables,
+      #else
+        NULL,
+      #endif
+      #if USES_REGISTER_TABLES == TRUE
+        (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15KmTableEntryTypeDescriptors,
+      #else
+        NULL,
+      #endif
+      #if MODEL_SPECIFIC_HT_PCI == TRUE
+        (PACKAGE_HTLINK_MAP) &HtFam15Mod2xPackageLinkMap,
+      #else
+        NULL,
+      #endif
+      (CORE_PAIR_MAP *) &HtFam15KmCorePairMapping,
+      InitCacheEnabled,
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        GetF15KmEarlyInitOnCoreTable
+      #else
+        (PF_GET_EARLY_INIT_TABLE) CommonVoid
+      #endif
+    };
+
+    #define KM_SOCKETS 8
+    #define KM_MODULES 2
+    #define KM_RECOVERY_SOCKETS 1
+    #define KM_RECOVERY_MODULES 1
+    extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15KmLogicalIdAndRev;
+    #define OPT_F15_KM_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15KmLogicalIdAndRev,
+    #ifndef ADVCFG_PLATFORM_SOCKETS
+      #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
+    #else
+      #if ADVCFG_PLATFORM_SOCKETS < KM_SOCKETS
+        #undef ADVCFG_PLATFORM_SOCKETS
+        #define ADVCFG_PLATFORM_SOCKETS KM_SOCKETS
+      #endif
+    #endif
+    #ifndef ADVCFG_PLATFORM_MODULES
+      #define ADVCFG_PLATFORM_MODULES KM_MODULES
+    #else
+      #if ADVCFG_PLATFORM_MODULES < KM_MODULES
+        #undef ADVCFG_PLATFORM_MODULES
+        #define ADVCFG_PLATFORM_MODULES KM_MODULES
+      #endif
+    #endif
+
+    #if GET_PATCHES == TRUE
+
+      #if AGESA_ENTRY_INIT_EARLY == TRUE
+        #if OPTION_EARLY_SAMPLES == TRUE
+        #endif
+      #endif
+
+      CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15KmMicroCodePatchArray[] =
+      {
+        NULL
+      };
+
+      CONST UINT8 ROMDATA CpuF15KmNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15KmMicroCodePatchArray) / sizeof (CpuF15KmMicroCodePatchArray[0])) - 1);
+    #endif
+
+    #define OPT_F15_KM_CPU {AMD_FAMILY_15_KM, &cpuF15KmServices},
+
+  #else  //  OPTION_FAMILY15H_KM == TRUE
+    #define OPT_F15_KM_CPU
+    #define OPT_F15_KM_ID
+  #endif  //  OPTION_FAMILY15H_KM == TRUE
+#else  //  defined (OPTION_FAMILY15H_KM)
+  #define OPT_F15_KM_CPU
+  #define OPT_F15_KM_ID
+#endif  //  defined (OPTION_FAMILY15H_KM)
+
+/*
+ * Install unknown family 15h support
+ */
+
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
+  {
+    #if BASE_FAMILY_PCI == TRUE
+      &F15PciRegisterTable,
+    #endif
+    #if BASE_FAMILY_MSR == TRUE
+      &F15MsrRegisterTable,
+    #endif
+    // the end.
+    NULL
+  };
+#endif
+
+#if USES_REGISTER_TABLES == TRUE
+  CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
+  {
+    {MsrRegister, SetRegisterForMsrEntry},
+    {PciRegister, SetRegisterForPciEntry},
+    {FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
+    {HtPhyRegister, SetRegisterForHtPhyEntry},
+    {HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
+    {DeemphasisRegister, SetRegisterForDeemphasisEntry},
+    {ProfileFixup, SetRegisterForPerformanceProfileEntry},
+    {HtHostPciRegister, SetRegisterForHtHostEntry},
+    {HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
+    {HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
+    {CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
+    {ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
+    {CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
+    {HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
+    {CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
+    // End
+    {TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
+  };
+#endif
+
+
+CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
+{
+  0,
+  #if DISABLE_PSTATE == TRUE
+    F15DisablePstate,
+  #else
+    (PF_CPU_DISABLE_PSTATE) CommonAssert,
+  #endif
+  #if TRANSITION_PSTATE == TRUE
+    F15TransitionPstate,
+  #else
+    (PF_CPU_TRANSITION_PSTATE) CommonAssert,
+  #endif
+  #if PROC_IDD_MAX == TRUE
+    (PF_CPU_GET_IDD_MAX) CommonReturnFalse,
+  #else
+    (PF_CPU_GET_IDD_MAX) CommonAssert,
+  #endif
+  #if GET_TSC_RATE == TRUE
+    F15GetTscRate,
+  #else
+    (PF_CPU_GET_TSC_RATE) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #else
+    (PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
+  #endif
+  #if GET_NB_FREQ == TRUE
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
+  #endif
+  #if IS_NBCOF_INIT_NEEDED == TRUE
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
+  #else
+    (PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
+  #endif
+  #if GET_NB_IDD_MAX == TRUE
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #else
+    (PF_CPU_GET_NB_IDD_MAX) CommonAssert,
+  #endif
+  #if AP_INITIAL_LAUNCH == TRUE
+    F15LaunchApCore,
+  #else
+    (PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
+  #endif
+  #if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
+  #else
+    (PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
+  #endif
+  #if GET_AP_MAILBOX_FROM_HW == TRUE
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #else
+    (PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
+  #endif
+  #if SET_AP_CORE_NUMBER == TRUE
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if GET_AP_CORE_NUMBER == TRUE
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if TRANSFER_AP_CORE_NUMBER == TRUE
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #else
+    (PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
+  #endif
+  #if ID_POSITION_INITIAL_APICID == TRUE
+    F15CpuAmdCoreIdPositionInInitialApicId,
+  #else
+    (PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
+  #endif
+  #if SAVE_FEATURES == TRUE
+    // F15SaveFeatures,
+    (PF_CPU_SAVE_FEATURES) CommonVoid,
+  #else
+    (PF_CPU_SAVE_FEATURES) CommonAssert,
+  #endif
+  #if WRITE_FEATURES == TRUE
+    // F15WriteFeatures,
+    (PF_CPU_WRITE_FEATURES) CommonVoid,
+  #else
+    (PF_CPU_WRITE_FEATURES) CommonAssert,
+  #endif
+  #if SET_WARM_RESET_FLAG == TRUE
+    F15SetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if GET_WARM_RESET_FLAG == TRUE
+    F15GetAgesaWarmResetFlag,
+  #else
+    (PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
+  #endif
+  #if BRAND_STRING1 == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if BRAND_STRING2 == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_CACHE_INFO == TRUE
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_SYSTEM_PM_TABLE == TRUE
+    GetEmptyArray,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_WHEA_INIT == TRUE
+    GetF15WheaInitData,
+  #else
+    (PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
+  #endif
+  #if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
+  #else
+    (PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
+  #endif
+  #if IS_NB_PSTATE_ENABLED == TRUE
+    F15IsNbPstateEnabled,
+  #else
+    (PF_IS_NB_PSTATE_ENABLED) CommonAssert,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F15NextLinkHasHtPhyFeats,
+  #else
+    (PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
+  #endif
+  #if (BASE_FAMILY_HT_PCI == TRUE)
+    F15SetHtPhyRegister,
+  #else
+    (PF_SET_HT_PHY_REGISTER) CommonVoid,
+  #endif
+  #if BASE_FAMILY_PCI == TRUE
+    F15GetNextHtLinkFeatures,
+  #else
+    (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (REGISTER_TABLE **) F15UnknownRegisterTables,
+  #else
+    NULL,
+  #endif
+  #if USES_REGISTER_TABLES == TRUE
+    (TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
+  #else
+    NULL,
+  #endif
+  NULL,
+  NULL,
+  InitCacheEnabled,
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #else
+    (PF_GET_EARLY_INIT_TABLE) CommonVoid
+  #endif
+};
+
+// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
+#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
+  #undef  FAMILY_MMIO_BASE_MASK
+  #define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
+#endif
+
+
+#undef OPT_F15_ID_TABLE
+#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
+#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
+
+#undef OPT_F15_TABLE
+#define OPT_F15_TABLE   OPT_F15_OR_CPU OPT_F15_TN_CPU OPT_F15_KM_CPU OPT_F15_UNKNOWN_CPU
+
+
+#if OPTION_G34_SOCKET_SUPPORT == TRUE
+  #define F15_G34_BRANDSTRING1 NULL,
+  #define F15_G34_BRANDSTRING2 NULL,
+#else
+  #define F15_G34_BRANDSTRING1
+  #define F15_G34_BRANDSTRING2
+#endif
+#if OPTION_C32_SOCKET_SUPPORT == TRUE
+  #define F15_C32_BRANDSTRING1 NULL,
+  #define F15_C32_BRANDSTRING2 NULL,
+#else
+  #define F15_C32_BRANDSTRING1
+  #define F15_C32_BRANDSTRING2
+#endif
+#if OPTION_AM3_SOCKET_SUPPORT == TRUE
+  #define F15_AM3_BRANDSTRING1 NULL,
+  #define F15_AM3_BRANDSTRING2 NULL,
+#else
+  #define F15_AM3_BRANDSTRING1
+  #define F15_AM3_BRANDSTRING2
+#endif
+#if OPTION_FS1_SOCKET_SUPPORT == TRUE
+  #define F15_FS1_BRANDSTRING1 NULL,
+  #define F15_FS1_BRANDSTRING2 NULL,
+#else
+  #define F15_FS1_BRANDSTRING1
+  #define F15_FS1_BRANDSTRING2
+#endif
+#if OPTION_FM2_SOCKET_SUPPORT == TRUE
+  #define F15_FM2_BRANDSTRING1 NULL,
+  #define F15_FM2_BRANDSTRING2 NULL,
+#else
+  #define F15_FM2_BRANDSTRING1
+  #define F15_FM2_BRANDSTRING2
+#endif
+#if OPTION_FP2_SOCKET_SUPPORT == TRUE
+  #define F15_FP2_BRANDSTRING1 NULL,
+  #define F15_FP2_BRANDSTRING2 NULL,
+#else
+  #define F15_FP2_BRANDSTRING1
+  #define F15_FP2_BRANDSTRING2
+#endif
+#if OPTION_G2012_SOCKET_SUPPORT == TRUE
+  #define F15_G2012_BRANDSTRING1 NULL,
+  #define F15_G2012_BRANDSTRING2 NULL,
+#else
+  #define F15_G2012_BRANDSTRING1
+  #define F15_G2012_BRANDSTRING2
+#endif
+#if OPTION_C2012_SOCKET_SUPPORT == TRUE
+  #define F15_C2012_BRANDSTRING1 NULL,
+  #define F15_C2012_BRANDSTRING2 NULL,
+#else
+  #define F15_C2012_BRANDSTRING1
+  #define F15_C2012_BRANDSTRING2
+#endif
+
+
+#if BRAND_STRING1 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
+  {
+    F15_G34_BRANDSTRING1
+    F15_C32_BRANDSTRING1
+    F15_AM3_BRANDSTRING1
+    F15_FS1_BRANDSTRING1
+    F15_FM2_BRANDSTRING1
+    F15_FP2_BRANDSTRING1
+    F15_G2012_BRANDSTRING1
+    F15_C2012_BRANDSTRING1
+  };
+
+  CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
+#endif
+
+#if BRAND_STRING2 == TRUE
+  CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
+  {
+    F15_G34_BRANDSTRING2
+    F15_C32_BRANDSTRING2
+    F15_AM3_BRANDSTRING2
+    F15_FS1_BRANDSTRING2
+    F15_FM2_BRANDSTRING2
+    F15_FP2_BRANDSTRING2
+    F15_G2012_BRANDSTRING2
+    F15_C2012_BRANDSTRING2
+  };
+
+  CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
+#endif
+
+CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
+{
+  OPT_F15_OR_ID
+  OPT_F15_TN_ID
+  OPT_F15_KM_ID
+};
+
+#endif  // _OPTION_FAMILY_15H_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h
new file mode 100644
index 0000000..715e162
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionFchInstall.h
@@ -0,0 +1,988 @@
+/*********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;     * Redistributions of source code must retain the above copyright
+;       notice, this list of conditions and the following disclaimer.
+;     * Redistributions in binary form must reproduce the above copyright
+;       notice, this list of conditions and the following disclaimer in the
+;       documentation and/or other materials provided with the distribution.
+;     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+;       its contributors may be used to endorse or promote products derived
+;       from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _OPTION_FCH_INSTALL_H_
+#define _OPTION_FCH_INSTALL_H_
+
+#include "AmdFch.h"
+
+#define  FCH_SUPPORT   FALSE
+
+
+/* ACPI block register offset definitions */
+#define PM1_STATUS_OFFSET              0x00
+#define PM1_ENABLE_OFFSET              0x02
+#define PM_CONTROL_OFFSET              0x04
+#define PM_TIMER_OFFSET                0x08
+#define CPU_CONTROL_OFFSET             0x10
+#define EVENT_STATUS_OFFSET            0x20
+#define EVENT_ENABLE_OFFSET            0x24
+
+
+#if  FCH_SUPPORT == TRUE
+  /*
+   * FCH subfunctions
+   */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitResetHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitResetAb;
+      extern FCH_TASK_ENTRY    FchInitResetSpi;
+      extern FCH_TASK_ENTRY    FchInitResetGec;
+      extern FCH_TASK_ENTRY    FchInitResetSata;
+      extern FCH_TASK_ENTRY    FchInitResetLpc;
+      extern FCH_TASK_ENTRY    FchInitResetPcib;
+      extern FCH_TASK_ENTRY    FchInitResetPcie;
+      extern FCH_TASK_ENTRY    FchInitResetGpp;
+      extern FCH_TASK_ENTRY    FchInitResetUsb;
+      extern FCH_TASK_ENTRY    FchInitResetEhci;
+      extern FCH_TASK_ENTRY    FchInitResetOhci;
+      extern FCH_TASK_ENTRY    FchInitResetXhci;
+      extern FCH_TASK_ENTRY    FchInitResetImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern FCH_TASK_ENTRY    FchInitEnvUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitEnvUsb;
+      extern FCH_TASK_ENTRY    FchInitEnvAb;
+      extern FCH_TASK_ENTRY    FchInitEnvGpp;
+      extern FCH_TASK_ENTRY    FchInitEnvPcie;
+      extern FCH_TASK_ENTRY    FchInitEnvPcib;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpiP;
+      extern FCH_TASK_ENTRY    FchInitEnvHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitEnvAbSpecial;
+      extern FCH_TASK_ENTRY    FchInitEnvSpi;
+      extern FCH_TASK_ENTRY    FchInitEnvGec;
+      extern FCH_TASK_ENTRY    FchInitEnvSata;
+      extern FCH_TASK_ENTRY    FchInitEnvIde;
+      extern FCH_TASK_ENTRY    FchInitEnvSd;
+      extern FCH_TASK_ENTRY    FchInitEnvIr;
+      extern FCH_TASK_ENTRY    FchInitEnvAzalia;
+      extern FCH_TASK_ENTRY    FchInitEnvHwm;
+      extern FCH_TASK_ENTRY    FchInitEnvImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern FCH_TASK_ENTRY    FchInitMidHwm;
+      extern FCH_TASK_ENTRY    FchInitMidAzalia;
+      extern FCH_TASK_ENTRY    FchInitMidGec;
+      extern FCH_TASK_ENTRY    FchInitMidSata;
+      extern FCH_TASK_ENTRY    FchInitMidIde;
+      extern FCH_TASK_ENTRY    FchInitMidAb;
+      extern FCH_TASK_ENTRY    FchInitMidUsb;
+      extern FCH_TASK_ENTRY    FchInitMidUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitMidUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitMidImc;
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern FCH_TASK_ENTRY    FchInitLateHwAcpi;
+      extern FCH_TASK_ENTRY    FchInitLateSpi;
+      extern FCH_TASK_ENTRY    FchInitLateGec;
+      extern FCH_TASK_ENTRY    FchInitLateSata;
+      extern FCH_TASK_ENTRY    FchInitLateIde;
+      extern FCH_TASK_ENTRY    FchInitLatePcib;
+      extern FCH_TASK_ENTRY    FchInitLateAb;
+      extern FCH_TASK_ENTRY    FchInitLatePcie;
+      extern FCH_TASK_ENTRY    FchInitLateGpp;
+      extern FCH_TASK_ENTRY    FchInitLateUsb;
+      extern FCH_TASK_ENTRY    FchInitLateUsbEhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbOhci;
+      extern FCH_TASK_ENTRY    FchInitLateUsbXhci;
+      extern FCH_TASK_ENTRY    FchInitLateImc;
+      extern FCH_TASK_ENTRY    FchInitLateAzalia;
+      extern FCH_TASK_ENTRY    FchInitLateHwm;
+    #endif
+  #endif
+
+  extern FCH_TASK_ENTRY    FchTaskDummy;
+  extern FCH_TASK_ENTRY    FchGppHotplugSmiCallback;
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  /* FCH Interface entries */
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      extern  FCH_INIT      FchInitReset;
+      extern  FCH_INIT      FchResetConstructor;
+
+      #define FP_FCH_INIT_RESET              &FchInitReset
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &FchResetConstructor
+    #else
+      #define FP_FCH_INIT_RESET              &CommonFchInitStub
+      #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      extern  FCH_INIT      FchInitEnv;
+      extern  FCH_INIT      FchEnvConstructor;
+
+      #define FP_FCH_INIT_ENV                &FchInitEnv
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &FchEnvConstructor
+    #else
+      #define FP_FCH_INIT_ENV                &CommonFchInitStub
+      #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      extern  FCH_INIT      FchInitMid;
+      extern  FCH_INIT      FchMidConstructor;
+
+      #define FP_FCH_INIT_MID                &FchInitMid
+      #define FP_FCH_INIT_MID_CONSTRUCT      &FchMidConstructor
+    #else
+      #define FP_FCH_INIT_MID                &CommonFchInitStub
+      #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      extern  FCH_INIT      FchInitLate;
+      extern  FCH_INIT      FchLateConstructor;
+
+      #define FP_FCH_INIT_LATE               &FchInitLate
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &FchLateConstructor
+    #else
+      #define FP_FCH_INIT_LATE               &CommonFchInitStub
+      #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+    #endif
+  #endif
+
+  /* FCH subcomponent build options */
+  #undef  FCH_NO_HWACPI_SUPPORT
+  #undef  FCH_NO_AB_SUPPORT
+  #undef  FCH_NO_SPI_SUPPORT
+  #undef  FCH_NO_GEC_SUPPORT
+  #undef  FCH_NO_SATA_SUPPORT
+  #undef  FCH_NO_IDE_SUPPORT
+  #undef  FCH_NO_LPC_SUPPORT
+  #undef  FCH_NO_PCIB_SUPPORT
+  #undef  FCH_NO_PCIE_SUPPORT
+  #undef  FCH_NO_GPP_SUPPORT
+  #undef  FCH_NO_USB_SUPPORT
+  #undef  FCH_NO_EHCI_SUPPORT
+  #undef  FCH_NO_OHCI_SUPPORT
+  #undef  FCH_NO_XHCI_SUPPORT
+  #undef  FCH_NO_IMC_SUPPORT
+  #undef  FCH_NO_SD_SUPPORT
+  #undef  FCH_NO_IR_SUPPORT
+  #undef  FCH_NO_AZALIA_SUPPORT
+  #undef  FCH_NO_HWM_SUPPORT
+
+  //
+  // Installable blocks depending on build switches
+  //
+  #ifndef FCH_NO_HWACPI_SUPPORT
+    #define BLOCK_HWACPI_SIZE           sizeof (FCH_ACPI)
+    #define InstallFchInitResetHwAcpiP  &FchInitResetHwAcpiP
+    #define InstallFchInitResetHwAcpi   &FchInitResetHwAcpi
+    #define InstallFchInitEnvHwAcpiP    &FchInitEnvHwAcpiP
+    #define InstallFchInitEnvHwAcpi     &FchInitEnvHwAcpi
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchInitLateHwAcpi
+  #else
+    #define BLOCK_HWACPI_SIZE           0
+    #define InstallFchInitResetHwAcpiP  &FchTaskDummy
+    #define InstallFchInitResetHwAcpi   &FchTaskDummy
+    #define InstallFchInitEnvHwAcpi     &FchTaskDummy
+    #define InstallFchInitMidHwAcpi     &FchTaskDummy
+    #define InstallFchInitLateHwAcpi    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_AB_SUPPORT
+    #define BLOCK_AB_SIZE               sizeof (FCH_AB)
+    #define InstallFchInitResetAb       &FchInitResetAb
+    #define InstallFchInitEnvAb         &FchInitEnvAb
+    #define InstallFchInitEnvAbS        &FchInitEnvAbSpecial
+    #define InstallFchInitMidAb         &FchInitMidAb
+    #define InstallFchInitLateAb        &FchInitLateAb
+  #else
+    #define BLOCK_AB_SIZE               0
+    #define InstallFchInitResetAb       &FchTaskDummy
+    #define InstallFchInitEnvAb         &FchTaskDummy
+    #define InstallFchInitEnvAbS        &FchTaskDummy
+    #define InstallFchInitMidAb         &FchTaskDummy
+    #define InstallFchInitLateAb        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SPI_SUPPORT
+    #define BLOCK_SPI_SIZE              sizeof (FCH_SPI)
+    #define InstallFchInitResetSpi      &FchInitResetSpi
+    #define InstallFchInitEnvSpi        &FchInitEnvSpi
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchInitLateSpi
+  #else
+    #define BLOCK_SPI_SIZE              0
+    #define InstallFchInitResetSpi      &FchTaskDummy
+    #define InstallFchInitEnvSpi        &FchTaskDummy
+    #define InstallFchInitMidSpi        &FchTaskDummy
+    #define InstallFchInitLateSpi       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GEC_SUPPORT
+    #define BLOCK_GEC_SIZE              sizeof (FCH_GEC)
+    #define InstallFchInitResetGec      &FchInitResetGec
+    #define InstallFchInitEnvGec        &FchInitEnvGec
+    #define InstallFchInitMidGec        &FchInitMidGec
+    #define InstallFchInitLateGec       &FchInitLateGec
+  #else
+    #define BLOCK_GEC_SIZE              0
+    #define InstallFchInitResetGec      &FchTaskDummy
+    #define InstallFchInitEnvGec        &FchTaskDummy
+    #define InstallFchInitMidGec        &FchTaskDummy
+    #define InstallFchInitLateGec       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_SATA_SUPPORT
+    #define BLOCK_SATA_SIZE             sizeof (FCH_SATA)
+    #define InstallFchInitResetSata     &FchInitResetSata
+    #define InstallFchInitEnvSata       &FchInitEnvSata
+    #define InstallFchInitMidSata       &FchInitMidSata
+    #define InstallFchInitLateSata      &FchInitLateSata
+  #else
+    #define BLOCK_SATA_SIZE             0
+    #define InstallFchInitResetSata     &FchTaskDummy
+    #define InstallFchInitEnvSata       &FchTaskDummy
+    #define InstallFchInitMidSata       &FchTaskDummy
+    #define InstallFchInitLateSata      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IDE_SUPPORT
+    #define BLOCK_IDE_SIZE              sizeof (FCH_IDE)
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchInitEnvIde
+    #define InstallFchInitMidIde        &FchInitMidIde
+    #define InstallFchInitLateIde       &FchInitLateIde
+  #else
+    #define BLOCK_IDE_SIZE              0
+    #define InstallFchInitResetIde      &FchTaskDummy
+    #define InstallFchInitEnvIde        &FchTaskDummy
+    #define InstallFchInitMidIde        &FchTaskDummy
+    #define InstallFchInitLateIde       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_LPC_SUPPORT
+    #define BLOCK_LPC_SIZE              sizeof (FCH_LPC)
+    #define InstallFchInitResetLpc      &FchInitResetLpc
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #else
+    #define BLOCK_LPC_SIZE              0
+    #define InstallFchInitResetLpc      &FchTaskDummy
+    #define InstallFchInitEnvLpc        &FchTaskDummy
+    #define InstallFchInitMidLpc        &FchTaskDummy
+    #define InstallFchInitLateLpc       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIB_SUPPORT
+    #define BLOCK_PCIB_SIZE             sizeof (FCH_PCIB)
+    #define InstallFchInitResetPcib     &FchInitResetPcib
+    #define InstallFchInitEnvPcib       &FchInitEnvPcib
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchInitLatePcib
+  #else
+    #define BLOCK_PCIB_SIZE             0
+    #define InstallFchInitResetPcib     &FchTaskDummy
+    #define InstallFchInitEnvPcib       &FchTaskDummy
+    #define InstallFchInitMidPcib       &FchTaskDummy
+    #define InstallFchInitLatePcib      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_PCIE_SUPPORT
+    #define InstallFchInitResetPcie     &FchInitResetPcie
+    #define InstallFchInitEnvPcie       &FchInitEnvPcie
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchInitLatePcie
+  #else
+    #define InstallFchInitResetPcie     &FchTaskDummy
+    #define InstallFchInitEnvPcie       &FchTaskDummy
+    #define InstallFchInitMidPcie       &FchTaskDummy
+    #define InstallFchInitLatePcie      &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_GPP_SUPPORT
+    #define BLOCK_GPP_SIZE              sizeof (FCH_GPP)
+    #define InstallFchInitResetGpp      &FchInitResetGpp
+    #define InstallFchInitEnvGpp        &FchInitEnvGpp
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchInitLateGpp
+    #define InstallHpSmiCallback        &FchGppHotplugSmiCallback
+  #else
+    #define BLOCK_GPP_SIZE              0
+    #define InstallFchInitResetGpp      &FchTaskDummy
+    #define InstallFchInitEnvGpp        &FchTaskDummy
+    #define InstallFchInitMidGpp        &FchTaskDummy
+    #define InstallFchInitLateGpp       &FchTaskDummy
+    #define InstallHpSmiCallback        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_USB_SUPPORT
+    #define BLOCK_USB_SIZE              sizeof (FCH_USB)
+    #define InstallFchInitResetUsb      &FchInitResetUsb
+    #define InstallFchInitEnvUsb        &FchInitEnvUsb
+    #define InstallFchInitMidUsb        &FchInitMidUsb
+    #define InstallFchInitLateUsb       &FchInitLateUsb
+  #else
+    #define BLOCK_USB_SIZE              0
+    #define InstallFchInitResetUsb      &FchTaskDummy
+    #define InstallFchInitEnvUsb        &FchTaskDummy
+    #define InstallFchInitMidUsb        &FchTaskDummy
+    #define InstallFchInitLateUsb       &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_EHCI_SUPPORT
+    #define InstallFchInitResetUsbEhci  &FchInitResetEhci
+    #define InstallFchInitEnvUsbEhci    &FchInitEnvUsbEhci
+    #define InstallFchInitMidUsbEhci    &FchInitMidUsbEhci
+    #define InstallFchInitLateUsbEhci   &FchInitLateUsbEhci
+  #else
+    #define InstallFchInitResetUsbEhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbEhci    &FchTaskDummy
+    #define InstallFchInitMidUsbEhci    &FchTaskDummy
+    #define InstallFchInitLateUsbEhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_OHCI_SUPPORT
+    #define InstallFchInitResetUsbOhci  &FchInitResetOhci
+    #define InstallFchInitEnvUsbOhci    &FchInitEnvUsbOhci
+    #define InstallFchInitMidUsbOhci    &FchInitMidUsbOhci
+    #define InstallFchInitLateUsbOhci   &FchInitLateUsbOhci
+  #else
+    #define InstallFchInitResetUsbOhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbOhci    &FchTaskDummy
+    #define InstallFchInitMidUsbOhci    &FchTaskDummy
+    #define InstallFchInitLateUsbOhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_XHCI_SUPPORT
+    #define InstallFchInitResetUsbXhci  &FchInitResetXhci
+    #define InstallFchInitEnvUsbXhci    &FchInitEnvUsbXhci
+    #define InstallFchInitMidUsbXhci    &FchInitMidUsbXhci
+    #define InstallFchInitLateUsbXhci   &FchInitLateUsbXhci
+  #else
+    #define InstallFchInitResetUsbXhci  &FchTaskDummy
+    #define InstallFchInitEnvUsbXhci    &FchTaskDummy
+    #define InstallFchInitMidUsbXhci    &FchTaskDummy
+    #define InstallFchInitLateUsbXhci   &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IMC_SUPPORT
+    #define BLOCK_IMC_SIZE              sizeof (FCH_IMC)
+    #define InstallFchInitResetImc      &FchInitResetImc
+    #define InstallFchInitEnvImc        &FchInitEnvImc
+    #define InstallFchInitMidImc        &FchInitMidImc
+    #define InstallFchInitLateImc       &FchInitLateImc
+  #else
+    #define BLOCK_IMC_SIZE              0
+    #define InstallFchInitResetImc      &FchTaskDummy
+    #define InstallFchInitEnvImc        &FchTaskDummy
+    #define InstallFchInitMidImc        &FchTaskDummy
+    #define InstallFchInitLateImc       &FchTaskDummy
+  #endif
+
+
+  #ifndef FCH_NO_SD_SUPPORT
+    #define BLOCK_SD_SIZE               sizeof (FCH_SD)
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchInitEnvSd
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #else
+    #define BLOCK_SD_SIZE               0
+    #define InstallFchInitResetSd       &FchTaskDummy
+    #define InstallFchInitEnvSd         &FchTaskDummy
+    #define InstallFchInitMidSd         &FchTaskDummy
+    #define InstallFchInitLateSd        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_IR_SUPPORT
+    #define BLOCK_IR_SIZE               sizeof (FCH_IR)
+    #define InstallFchInitResetIr       &FchTaskDummy
+    #define InstallFchInitEnvIr         &FchInitEnvIr
+    #define InstallFchInitMidIr         &FchTaskDummy
+    #define InstallFchInitLateIr        &FchTaskDummy
+  #else
+    #define BLOCK_IR_SIZE               0
+    #define InstallFchInitResetIr       &FchTaskDummy
+    #define InstallFchInitEnvIr         &FchTaskDummy
+    #define InstallFchInitMidIr         &FchTaskDummy
+    #define InstallFchInitLateIr        &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_AZALIA_SUPPORT
+    #define BLOCK_AZALIA_SIZE           sizeof (FCH_AZALIA)
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchInitEnvAzalia
+    #define InstallFchInitMidAzalia     &FchInitMidAzalia
+    #define InstallFchInitLateAzalia    &FchInitLateAzalia
+  #else
+    #define BLOCK_AZALIA_SIZE           0
+    #define InstallFchInitResetAzalia   &FchTaskDummy
+    #define InstallFchInitEnvAzalia     &FchTaskDummy
+    #define InstallFchInitMidAzalia     &FchTaskDummy
+    #define InstallFchInitLateAzalia    &FchTaskDummy
+  #endif
+
+  #ifndef FCH_NO_HWM_SUPPORT
+    #define BLOCK_HWM_SIZE              sizeof (FCH_HWM)
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchInitEnvHwm
+    #define InstallFchInitMidHwm        &FchInitMidHwm
+    #define InstallFchInitLateHwm       &FchInitLateHwm
+  #else
+    #define InstallFchInitResetHwm      &FchTaskDummy
+    #define InstallFchInitEnvHwm        &FchTaskDummy
+    #define InstallFchInitMidHwm        &FchTaskDummy
+    #define InstallFchInitLateHwm       &FchTaskDummy
+  #endif
+
+
+  #define BLOCK_SMBUS_SIZE      sizeof (FCH_SMBUS)
+  #define BLOCK_HPET_SIZE       sizeof (FCH_HPET)
+  #define BLOCK_GCPU_SIZE       sizeof (FCH_GCPU)
+  #define BLOCK_SDB_SIZE        sizeof (FCH_SERIALDB)
+  #define BLOCK_MISC_SIZE       sizeof (FCH_MISC)
+
+
+  // Optionally declare OEM hooks after each phase
+  #ifndef FCH_INIT_RESET_HOOK
+    #define InstallFchInitResetHook     FchTaskDummy
+  #else
+    #define InstallFchInitResetHook     OemFchInitResetHook
+  #endif
+
+
+  //
+  // Define FCH build time options and configurations
+  //
+  #ifdef BLDCFG_SMBUS0_BASE_ADDRESS
+    #define CFG_SMBUS0_BASE_ADDRESS           BLDCFG_SMBUS0_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS0_BASE_ADDRESS           DFLT_SMBUS0_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMBUS1_BASE_ADDRESS
+    #define CFG_SMBUS1_BASE_ADDRESS           BLDCFG_SMBUS1_BASE_ADDRESS
+  #else
+    #define CFG_SMBUS1_BASE_ADDRESS           DFLT_SMBUS1_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SIO_PME_BASE_ADDRESS
+    #define CFG_SIO_PME_BASE_ADDRESS          BLDCFG_SIO_PME_BASE_ADDRESS
+  #else
+    #define CFG_SIO_PME_BASE_ADDRESS          DFLT_SIO_PME_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS    DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS    DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS     DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS    DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
+  #endif
+  #ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
+  #else
+    #define CFG_ACPI_GPE0_BLOCK_ADDRESS       DFLT_ACPI_GPE0_BLOCK_ADDRESS
+  #endif
+
+
+  #ifdef BLDCFG_WATCHDOG_TIMER_BASE
+    #define CFG_WATCHDOG_TIMER_BASE           BLDCFG_WATCHDOG_TIMER_BASE
+  #else
+    #define CFG_WATCHDOG_TIMER_BASE           DFLT_WATCHDOG_TIMER_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       BLDCFG_ACPI_PMA_BLK_ADDRESS
+  #else
+    #define CFG_ACPI_PMA_CNTBLK_ADDRESS       DFLT_ACPI_PMA_CNT_BLK_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
+    #define CFG_SMI_CMD_PORT_ADDRESS          BLDCFG_SMI_CMD_PORT_ADDRESS
+  #else
+    #define CFG_SMI_CMD_PORT_ADDRESS          DFLT_SMI_CMD_PORT
+  #endif
+
+  #ifdef BLDCFG_ROM_BASE_ADDRESS
+    #define CFG_SPI_ROM_BASE_ADDRESS          BLDCFG_ROM_BASE_ADDRESS
+  #else
+    #define CFG_SPI_ROM_BASE_ADDRESS          DFLT_SPI_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_GEC_SHADOW_ROM_BASE
+    #define CFG_GEC_SHADOW_ROM_BASE           BLDCFG_GEC_SHADOW_ROM_BASE
+  #else
+    #define CFG_GEC_SHADOW_ROM_BASE           DFLT_GEC_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_HPET_BASE_ADDRESS
+    #define CFG_HPET_BASE_ADDRESS           BLDCFG_HPET_BASE_ADDRESS
+  #else
+    #define CFG_HPET_BASE_ADDRESS           DFLT_HPET_BASE_ADDRESS
+  #endif
+
+  #ifdef BLDCFG_AZALIA_SSID
+    #define CFG_AZALIA_SSID                 BLDCFG_AZALIA_SSID
+  #else
+    #define CFG_AZALIA_SSID                 DFLT_AZALIA_SSID
+  #endif
+
+  #ifdef BLDCFG_SMBUS_SSID
+    #define CFG_SMBUS_SSID                  BLDCFG_SMBUS_SSID
+  #else
+    #define CFG_SMBUS_SSID                  DFLT_SMBUS_SSID
+  #endif
+
+  #ifdef BLDCFG_IDE_SSID
+    #define CFG_IDE_SSID                    BLDCFG_IDE_SSID
+  #else
+    #define CFG_IDE_SSID                    DFLT_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_AHCI_SSID
+    #define CFG_SATA_AHCI_SSID              BLDCFG_SATA_AHCI_SSID
+  #else
+    #define CFG_SATA_AHCI_SSID              DFLT_SATA_AHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_IDE_SSID
+    #define CFG_SATA_IDE_SSID               BLDCFG_SATA_IDE_SSID
+  #else
+    #define CFG_SATA_IDE_SSID               DFLT_SATA_IDE_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID5_SSID
+    #define CFG_SATA_RAID5_SSID             BLDCFG_SATA_RAID5_SSID
+  #else
+    #define CFG_SATA_RAID5_SSID             DFLT_SATA_RAID5_SSID
+  #endif
+
+  #ifdef BLDCFG_SATA_RAID_SSID
+    #define CFG_SATA_RAID_SSID              BLDCFG_SATA_RAID_SSID
+  #else
+    #define CFG_SATA_RAID_SSID              DFLT_SATA_RAID_SSID
+  #endif
+
+  #ifdef BLDCFG_EHCI_SSID
+    #define CFG_EHCI_SSID                   BLDCFG_EHCI_SSID
+  #else
+    #define CFG_EHCI_SSID                   DFLT_EHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_OHCI_SSID
+    #define CFG_OHCI_SSID                   BLDCFG_OHCI_SSID
+  #else
+    #define CFG_OHCI_SSID                   DFLT_OHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_LPC_SSID
+    #define CFG_LPC_SSID                    BLDCFG_LPC_SSID
+  #else
+    #define CFG_LPC_SSID                    DFLT_LPC_SSID
+  #endif
+
+  #ifdef BLDCFG_SD_SSID
+    #define CFG_SD_SSID                     BLDCFG_SD_SSID
+  #else
+    #define CFG_SD_SSID                     DFLT_SD_SSID
+  #endif
+
+  #ifdef BLDCFG_XHCI_SSID
+    #define CFG_XHCI_SSID                   BLDCFG_XHCI_SSID
+  #else
+    #define CFG_XHCI_SSID                   DFLT_XHCI_SSID
+  #endif
+
+  #ifdef BLDCFG_FCH_PORT80_BEHIND_PCIB
+    #define CFG_FCH_PORT80_BEHIND_PCIB      BLDCFG_FCH_PORT80_BEHIND_PCIB
+  #else
+    #define CFG_FCH_PORT80_BEHIND_PCIB      DFLT_FCH_PORT80_BEHIND_PCIB
+  #endif
+
+  #ifdef BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #else
+    #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP  DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_LINK_CONFIG
+    #define CFG_FCH_GPP_LINK_CONFIG         BLDCFG_FCH_GPP_LINK_CONFIG
+  #else
+    #define CFG_FCH_GPP_LINK_CONFIG         DFLT_FCH_GPP_LINK_CONFIG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
+    #define CFG_FCH_GPP_PORT0_PRESENT       BLDCFG_FCH_GPP_PORT0_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT0_PRESENT       DFLT_FCH_GPP_PORT0_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
+    #define CFG_FCH_GPP_PORT1_PRESENT       BLDCFG_FCH_GPP_PORT1_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT1_PRESENT       DFLT_FCH_GPP_PORT1_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
+    #define CFG_FCH_GPP_PORT2_PRESENT       BLDCFG_FCH_GPP_PORT2_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT2_PRESENT       DFLT_FCH_GPP_PORT2_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
+    #define CFG_FCH_GPP_PORT3_PRESENT       BLDCFG_FCH_GPP_PORT3_PRESENT
+  #else
+    #define CFG_FCH_GPP_PORT3_PRESENT       DFLT_FCH_GPP_PORT3_PRESENT
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       BLDCFG_FCH_GPP_PORT0_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT0_HOTPLUG       DFLT_FCH_GPP_PORT0_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       BLDCFG_FCH_GPP_PORT1_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT1_HOTPLUG       DFLT_FCH_GPP_PORT1_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       BLDCFG_FCH_GPP_PORT2_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT2_HOTPLUG       DFLT_FCH_GPP_PORT2_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       BLDCFG_FCH_GPP_PORT3_HOTPLUG
+  #else
+    #define CFG_FCH_GPP_PORT3_HOTPLUG       DFLT_FCH_GPP_PORT3_HOTPLUG
+  #endif
+
+  #ifdef BLDCFG_FCH_ESATA_PORT_BITMAP
+    #define CFG_FCH_ESATA_PORT_BITMAP       BLDCFG_FCH_ESATA_PORT_BITMAP
+  #else
+    #define CFG_FCH_ESATA_PORT_BITMAP       0
+  #endif
+
+  #ifdef BLDCFG_FCH_IR_PIN_CONTROL
+    #define CFG_FCH_IR_PIN_CONTROL          BLDCFG_FCH_IR_PIN_CONTROL
+  #else
+    #define CFG_FCH_IR_PIN_CONTROL          (BIT5 | BIT1 | BIT0)
+  #endif
+
+  #ifdef BLDCFG_FCH_SD_CLOCK_CONTROL
+    #define CFG_FCH_SD_CLOCK_CONTROL        BLDCFG_FCH_SD_CLOCK_CONTROL
+  #else
+    #define CFG_FCH_SD_CLOCK_CONTROL        Sd50MhzTraceCableLengthWithinSixInches
+  #endif
+
+  #ifdef BLDCFG_FCH_SCI_MAP_LIST
+    #define CFG_FCH_SCI_MAP_LIST            BLDCFG_FCH_SCI_MAP_LIST
+  #else
+    #define CFG_FCH_SCI_MAP_LIST            NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_SATA_PHY_LIST
+    #define CFG_FCH_SATA_PHY_LIST           BLDCFG_FCH_SATA_PHY_LIST
+  #else
+    #define CFG_FCH_SATA_PHY_LIST           NULL
+  #endif
+
+  #ifdef BLDCFG_FCH_GPIO_CONTROL_LIST
+    #define CFG_FCH_GPIO_CONTROL_LIST       BLDCFG_FCH_GPIO_CONTROL_LIST
+  #else
+    #define CFG_FCH_GPIO_CONTROL_LIST       NULL
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_RESET
+    #if AGESA_ENTRY_INIT_RESET == TRUE
+      //
+      // Define task list for InitReset phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
+        InstallFchInitResetHwAcpiP,
+        InstallFchInitResetAb,
+        InstallFchInitResetSpi,
+        InstallFchInitResetGec,
+        InstallFchInitResetHwAcpi,
+        InstallFchInitResetSata,
+        InstallFchInitResetLpc,
+        InstallFchInitResetPcib,
+        InstallFchInitResetPcie,
+        InstallFchInitResetGpp,
+        InstallFchInitResetUsb,
+        InstallFchInitResetUsbEhci,
+        InstallFchInitResetUsbOhci,
+        InstallFchInitResetUsbXhci,
+        InstallFchInitResetImc,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for InitEnv phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
+        InstallFchInitEnvHwAcpiP,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvImc,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvUsbEhci,
+        InstallFchInitEnvUsbOhci,
+        InstallFchInitEnvUsbXhci,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvAbS,
+        InstallFchInitEnvHwm,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_MID
+    #if AGESA_ENTRY_INIT_MID == TRUE
+      //
+      // Define task list for InitMid phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
+        InstallFchInitMidImc,
+        InstallFchInitMidUsb,
+        InstallFchInitMidUsbEhci,
+        InstallFchInitMidUsbOhci,
+        InstallFchInitMidUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitMidHwm,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for InitLate phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateGec,
+        InstallFchInitLateAzalia,
+        InstallFchInitLateImc,
+        InstallFchInitLateHwm,
+        InstallFchInitLateGpp,
+        InstallFchInitLateHwAcpi,
+        NULL
+      };
+    #endif
+  #endif
+
+
+  #ifdef AGESA_ENTRY_INIT_ENV
+    #if AGESA_ENTRY_INIT_ENV == TRUE
+      //
+      // Define task list for S3 resume before PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
+        InstallFchInitEnvPcie,
+        InstallFchInitEnvPcib,
+        InstallFchInitEnvIr,
+        InstallFchInitEnvHwAcpi,
+        InstallFchInitEnvSpi,
+        InstallFchInitEnvSd,
+        InstallFchInitEnvUsb,
+        InstallFchInitEnvSata,
+        InstallFchInitEnvIde,
+        InstallFchInitEnvGec,
+        InstallFchInitEnvAzalia,
+        InstallFchInitEnvAb,
+        InstallFchInitEnvGpp,
+        InstallFchInitEnvAbS,
+        NULL
+      };
+    #endif
+  #endif
+
+  #ifdef AGESA_ENTRY_INIT_LATE
+    #if AGESA_ENTRY_INIT_LATE == TRUE
+      //
+      // Define task list for S3 resume after PCI phase
+      //
+      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
+        InstallFchInitLatePcie,
+        InstallFchInitLatePcib,
+        InstallFchInitLateSpi,
+        InstallFchInitLateUsb,
+        InstallFchInitLateUsbEhci,
+        InstallFchInitLateUsbOhci,
+        InstallFchInitLateUsbXhci,
+        InstallFchInitMidSata,
+        InstallFchInitMidIde,
+        InstallFchInitMidGec,
+        InstallFchInitMidAzalia,
+        InstallFchInitLateSata,
+        InstallFchInitLateIde,
+        InstallFchInitLateHwAcpi,
+        InstallFchInitEnvHwm,
+        InstallFchInitLateHwm,
+        NULL
+      };
+    #endif
+  #endif
+  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
+
+
+#else   // FCH_SUPPORT == FALSE
+  /* FCH Interface entries */
+  extern  FCH_INIT     CommonFchInitStub;
+
+  #define FP_FCH_INIT_RESET              &CommonFchInitStub
+  #define FP_FCH_INIT_RESET_CONSTRUCT    &CommonFchInitStub
+  #define FP_FCH_INIT_ENV                &CommonFchInitStub
+  #define FP_FCH_INIT_ENV_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_MID                &CommonFchInitStub
+  #define FP_FCH_INIT_MID_CONSTRUCT      &CommonFchInitStub
+  #define FP_FCH_INIT_LATE               &CommonFchInitStub
+  #define FP_FCH_INIT_LATE_CONSTRUCT     &CommonFchInitStub
+
+  #define CFG_SMBUS0_BASE_ADDRESS            0
+  #define CFG_SMBUS1_BASE_ADDRESS            0
+  #define CFG_SIO_PME_BASE_ADDRESS           0
+  #define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_PM_TMR_BLOCK_ADDRESS      0
+  #define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS     0
+  #define CFG_ACPI_GPE0_BLOCK_ADDRESS        0
+  #define CFG_SPI_ROM_BASE_ADDRESS           0
+  #define CFG_WATCHDOG_TIMER_BASE            0
+  #define CFG_HPET_BASE_ADDRESS              0
+  #define CFG_SMI_CMD_PORT_ADDRESS           0
+  #define CFG_ACPI_PMA_CNTBLK_ADDRESS        0
+  #define CFG_GEC_SHADOW_ROM_BASE            0
+  #define CFG_AZALIA_SSID                    0
+  #define CFG_SMBUS_SSID                     0
+  #define CFG_IDE_SSID                       0
+  #define CFG_SATA_AHCI_SSID                 0
+  #define CFG_SATA_IDE_SSID                  0
+  #define CFG_SATA_RAID5_SSID                0
+  #define CFG_SATA_RAID_SSID                 0
+  #define CFG_EHCI_SSID                      0
+  #define CFG_OHCI_SSID                      0
+  #define CFG_LPC_SSID                       0
+  #define CFG_SD_SSID                        0
+  #define CFG_XHCI_SSID                      0
+  #define CFG_FCH_PORT80_BEHIND_PCIB         0
+  #define CFG_FCH_ENABLE_ACPI_SLEEP_TRAP     0
+  #define CFG_FCH_GPP_LINK_CONFIG            0
+  #define CFG_FCH_GPP_PORT0_PRESENT          0
+  #define CFG_FCH_GPP_PORT1_PRESENT          0
+  #define CFG_FCH_GPP_PORT2_PRESENT          0
+  #define CFG_FCH_GPP_PORT3_PRESENT          0
+  #define CFG_FCH_GPP_PORT0_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT1_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT2_HOTPLUG          0
+  #define CFG_FCH_GPP_PORT3_HOTPLUG          0
+
+  #define CFG_FCH_ESATA_PORT_BITMAP          0
+  #define CFG_FCH_IR_PIN_CONTROL             0
+  #define CFG_FCH_SD_CLOCK_CONTROL           0
+  #define CFG_FCH_SCI_MAP_LIST               0
+  #define CFG_FCH_SATA_PHY_LIST              0
+  #define CFG_FCH_GPIO_CONTROL_LIST          0
+
+#endif
+
+
+CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
+  FP_FCH_INIT_RESET,
+  FP_FCH_INIT_RESET_CONSTRUCT,
+  FP_FCH_INIT_ENV,
+  FP_FCH_INIT_ENV_CONSTRUCT,
+  FP_FCH_INIT_MID,
+  FP_FCH_INIT_MID_CONSTRUCT,
+  FP_FCH_INIT_LATE,
+  FP_FCH_INIT_LATE_CONSTRUCT,
+};
+
+#endif  // _OPTION_FCH_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h
new file mode 100644
index 0000000..a7b1173
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecovery.h
@@ -0,0 +1,82 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD GFX Recovery option API.
+ *
+ * Contains structures and values used to control the GfxRecovery option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GFX_RECOVERY_H_
+#define _OPTION_GFX_RECOVERY_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
+  IN OUT   AMD_CONFIG_PARAMS     *StdHeader
+  );
+
+#define GFX_RECOVERY_STRUCT_VERSION  0x01
+
+/// The Option Configuration of GFX Recovery
+typedef struct  {
+  UINT16              OptGfxRecoveryVersion;       ///< The version number of GFX Recovery
+  OPTION_GFX_RECOVERY_FEATURE  *GfxRecoveryFeature;        ///< The Option Feature of GFX Recovery
+} OPTION_GFX_RECOVERY_CONFIGURATION;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h
new file mode 100644
index 0000000..1f29c8f
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGfxRecoveryInstall.h
@@ -0,0 +1,54 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GfxRecovery
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
+#define _OPTION_GFX_RECOVERY_INSTALL_H_
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+
+#endif  // _OPTION_GFX_RECOVERY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h
new file mode 100644
index 0000000..4b58645
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGnb.h
@@ -0,0 +1,109 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD ALIB option API.
+ *
+ * Contains structures and values used to control the ALIB option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 53099 $   @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_GNB_H_
+#define _OPTION_GNB_H_
+
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+typedef AGESA_STATUS OPTION_GNB_FEATURE (
+  IN       AMD_CONFIG_PARAMS    *StdHeader
+  );
+
+/// The Option Configuration
+typedef struct {
+  UINT64                Type;                   ///< Type
+  OPTION_GNB_FEATURE    *GnbFeature;            ///< The GNB Feature
+} OPTION_GNB_CONFIGURATION;
+
+/// The Build time options configuration
+typedef struct {
+  BOOLEAN               IgfxModeAsPcieEp;                   ///< Itegrated Gfx mode Pcie EP or Legacy
+  BOOLEAN               LclkDeepSleepEn;                    ///< Default for LCLK deep sleep
+  BOOLEAN               LclkDpmEn;                          ///< Default for LCLK DPM
+  BOOLEAN               GmcPowerGateStutterOnly;            ///< Force GMC power gate to stutter only
+  BOOLEAN               SmuSclkClockGatingEnable;           ///< Control SMU SCLK gating
+  BOOLEAN               PcieAspmBlackListEnable;            ///< Control Pcie Aspm Black List
+  BOOLEAN               IvrsRelativeAddrNamesSupport;       ///< Support for relative address names
+  BOOLEAN               GnbLoadRealFuseTable;               ///< Support for fuse table loading
+  UINT32                CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32                CfgGnbLinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32                CfgGnbLinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32                CfgGnbLinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us
+  UINT8                 CfgGnbTrainingAlgorithm;            ///< distribution of training across interface calls
+  BOOLEAN               CfgForceCableSafeOff;               ///< Force cable safe off
+  BOOLEAN               CfgOrbClockGatingEnable;            ///< Control ORB clock gating
+  UINT8                 CfgPciePowerGatingFlags;            ///< Pcie Power gating flags
+  BOOLEAN               CfgIocLclkClockGatingEnable;        ///< Control IOC LCLK clock gating
+  BOOLEAN               CfgIocSclkClockGatingEnable;        ///< Control IOC SCLK clock gating
+  BOOLEAN               CfgIommuL1ClockGatingEnable;        ///< Control IOMMU L1 clock gating
+  BOOLEAN               CfgIommuL2ClockGatingEnable;        ///< Control IOMMU L2 clock gating
+  BOOLEAN               CfgAltVddNb;                        ///< AltVDDNB support
+  BOOLEAN               CfgBapmSupport;                     ///< BAPM support
+  BOOLEAN               CfgUnusedSimdPowerGatingEnable;     ///< Control unused SIMD power gate
+  BOOLEAN               CfgUnusedRbPowerGatingEnable;       ///< Control unused SIMD power gate
+} GNB_BUILD_OPTIONS;
+
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif  // _OPTION_GNB_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
new file mode 100644
index 0000000..7733859
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionGnbInstall.h
@@ -0,0 +1,591 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: GNB
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 53099 $   @e \$Date: 2011-05-16 01:08:27 -0600 (Mon, 16 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_GNB_INSTALL_H_
+#define _OPTION_GNB_INSTALL_H_
+
+#include "S3SaveState.h"
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+//---------------------------------------------------------------------------------------------------
+// Family installation
+//---------------------------------------------------------------------------------------------------
+
+
+#define GNB_TYPE_LN   FALSE
+#define GNB_TYPE_ON   FALSE
+
+#if (OPTION_FAMILY14H_ON == TRUE)
+  #undef  GNB_TYPE_ON
+  #define GNB_TYPE_ON  TRUE
+#endif
+
+#if (OPTION_FAMILY12H_LN == TRUE)
+  #undef  GNB_TYPE_LN
+  #define GNB_TYPE_LN  TRUE
+#endif
+
+
+#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+//---------------------------------------------------------------------------------------------------
+// Service installation
+//---------------------------------------------------------------------------------------------------
+
+  #include "Gnb.h"
+  #include "GnbPcie.h"
+
+  #define SERVICES_POINTER  NULL
+  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
+
+//---------------------------------------------------------------------------------------------------
+// BUILD options
+//---------------------------------------------------------------------------------------------------
+
+  #ifndef CFG_IGFX_AS_PCIE_EP
+    #define CFG_IGFX_AS_PCIE_EP                           TRUE
+  #endif
+
+  #ifndef CFG_LCLK_DEEP_SLEEP_EN
+    #define  CFG_LCLK_DEEP_SLEEP_EN                       TRUE
+  #endif
+
+  #ifndef CFG_LCLK_DPM_EN
+    #define CFG_LCLK_DPM_EN                               TRUE
+  #endif
+
+  #ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
+    #define CFG_GMC_POWER_GATE_STUTTER_ONLY               FALSE
+  #endif
+
+  #ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
+    #if (GNB_TYPE_ON == TRUE)
+      #define  CFG_SMU_SCLK_CLOCK_GATING_ENABLE           TRUE
+    #else
+      #define CFG_SMU_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+  #endif
+
+  #ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+    #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE               TRUE
+  #endif
+
+  #ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
+    #define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT      FALSE
+  #endif
+
+  #ifndef CFG_GNB_LOAD_REAL_FUSE
+    #define  CFG_GNB_LOAD_REAL_FUSE                       TRUE
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
+    #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_L0_POOLING
+    #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
+    #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
+  #endif
+
+  #ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
+    #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
+  #endif
+
+  #ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
+  #else
+    #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
+  #endif
+
+  #ifndef CFG_GNB_FORCE_CABLESAFE_OFF
+    #define CFG_GNB_FORCE_CABLESAFE_OFF                   FALSE
+  #endif
+
+  #ifndef CFG_ORB_CLOCK_GATING_ENABLE
+      #define CFG_ORB_CLOCK_GATING_ENABLE                 TRUE
+    #endif
+
+  #ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
+    #define CFG_GNB_PCIE_POWERGATING_FLAGS                0x0
+  #endif
+
+  #ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
+      #define CFG_IOC_LCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
+      #define CFG_IOC_SCLK_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
+      #define CFG_IOMMU_L1_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
+      #define CFG_IOMMU_L2_CLOCK_GATING_ENABLE            FALSE
+    #endif
+
+  #ifndef CFG_GNB_ALTVDDNB_SUPPORT
+    #define CFG_GNB_ALTVDDNB_SUPPORT                      TRUE
+  #endif
+
+  #ifndef CFG_GNB_BAPM_SUPPORT
+    #define CFG_GNB_BAPM_SUPPORT                          TRUE
+  #endif
+
+  #ifndef CFG_UNUSED_SIMD_POWERGATING_ENABLE
+    #define CFG_UNUSED_SIMD_POWERGATING_ENABLE            TRUE
+  #endif
+
+  #ifndef CFG_UNUSED_RB_POWERGATING_ENABLE
+    #define CFG_UNUSED_RB_POWERGATING_ENABLE              FALSE
+  #endif
+
+  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
+    CFG_IGFX_AS_PCIE_EP,
+    CFG_LCLK_DEEP_SLEEP_EN,
+    CFG_LCLK_DPM_EN,
+    CFG_GMC_POWER_GATE_STUTTER_ONLY,
+    CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
+    CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
+    CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
+    CFG_GNB_LOAD_REAL_FUSE,
+    CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
+    CFG_GNB_PCIE_LINK_L0_POOLING,
+    CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
+    CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
+    CFG_GNB_PCIE_TRAINING_ALGORITHM,
+    CFG_GNB_FORCE_CABLESAFE_OFF,
+    CFG_ORB_CLOCK_GATING_ENABLE,
+    CFG_GNB_PCIE_POWERGATING_FLAGS,
+    CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
+    CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
+    CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
+    CFG_GNB_ALTVDDNB_SUPPORT,
+    CFG_GNB_BAPM_SUPPORT,
+    CFG_UNUSED_SIMD_POWERGATING_ENABLE,
+    CFG_UNUSED_RB_POWERGATING_ENABLE
+  };
+
+  //---------------------------------------------------------------------------------------------------
+  // Module entries
+  //---------------------------------------------------------------------------------------------------
+
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLY_INIT
+      #define OPTION_NB_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtEarly;
+      #define OPTION_NBINITATEARLY_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
+    #else
+      #define OPTION_NBINITATEARLY_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+  // SMU init
+    #ifndef OPTION_SMU
+      #define OPTION_SMU  TRUE
+    #endif
+    #if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  F12NbSmuInitFeature;
+      #define OPTION_F12NBSMUINITFEATURE_ENTRY            {AMD_FAMILY_LN, F12NbSmuInitFeature},
+    #else
+      #define OPTION_F12NBSMUINITFEATURE_ENTRY
+    #endif
+    #if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbSmuInitFeature;
+      #define OPTION_F14NBSMUINITFEATURE_ENTRY            {AMD_FAMILY_ON, F14NbSmuInitFeature},
+    #else
+      #define OPTION_F14NBSMUINITFEATURE_ENTRY
+    #endif
+      #define OPTION_KRNBSMUINITFEATURE_ENTRY
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_MAP
+      #define OPTION_PCIE_CONFIG_MAP TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_MAP == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                 PcieConfigurationMap;
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationMap},
+    #else
+      #define OPTION_PCIECONFIGURATIONMAP_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_EARLY_INIT
+      #define OPTION_PCIE_EARLY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtEarly;
+      #define OPTION_PCIEINITATEARLY_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
+    #else
+      #define  OPTION_PCIEINITATEARLY_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
+      OPTION_NBINITATEARLY_ENTRY
+      OPTION_F12NBSMUINITFEATURE_ENTRY
+      OPTION_F14NBSMUINITFEATURE_ENTRY
+      OPTION_PCIECONFIGURATIONMAP_ENTRY
+      OPTION_PCIEINITATEARLY_ENTRY
+      {0, NULL}
+    };
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_CONFIG_INIT
+      #define OPTION_PCIE_CONFIG_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieConfigurationInit;
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY          {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
+    #else
+      #define OPTION_PCIECONFIGURATIONINIT_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_EARLIER_INIT
+      #define OPTION_NB_EARLIER_INIT TRUE
+    #endif
+
+    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
+      OPTION_PCIECONFIGURATIONINIT_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_POST_INIT
+      #define OPTION_GFX_CONFIG_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxConfigPostInterface;
+      #define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY         {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
+    #else
+      #define  OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_POST_INIT
+      #define OPTION_GFX_POST_INIT TRUE
+    #endif
+    #if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtPost;
+      #define OPTION_GFXINITATPOST_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
+    #else
+      #define  OPTION_GFXINITATPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_POST_INIT
+      #define OPTION_NB_POST_INIT TRUE
+    #endif
+    #if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtPost;
+      #define OPTION_NBINITATPOST_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
+    #else
+      #define OPTION_NBINITATPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_EALRY_INIT
+      #define OPTION_PCIE_POST_EALRY_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtPostEarly;
+    #define OPTION_PCIEINITATPOSTEARLY_ENTRY              {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
+    #else
+      #define OPTION_PCIEINITATPOSTEARLY_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POST_INIT
+      #define OPTION_PCIE_POST_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtPost;
+      #define OPTION_PCIEINITATPOST_ENTRY                 {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
+    #else
+      #define OPTION_PCIEINITATPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+      OPTION_PCIEINITATPOSTEARLY_ENTRY
+      OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
+      OPTION_GFXINITATPOST_ENTRY
+      OPTION_GFXPOSTINTERFACETN_ENTRY
+      {0, NULL}
+    };
+
+    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
+      OPTION_NBINITATPOST_ENTRY
+      OPTION_PCIEINITATPOST_ENTRY
+      OPTION_PCIEPOSTINTERFACETN_ENTRY
+      OPTION_PCIEPOSTINTERFACEKM_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_ENV == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_FUSE_TABLE_INIT
+      #define OPTION_FUSE_TABLE_INIT TRUE
+    #endif
+    #if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbFuseTableFeature;
+      #define OPTION_NBFUSETABLEFEATURE_ENTRY             {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
+    #else
+      #define OPTION_NBFUSETABLEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_ENV_INIT
+      #define OPTION_NB_ENV_INIT TRUE
+    #endif
+    #if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtEnv;
+      #define OPTION_NBINITATENVT_ENTRY                   {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
+    #else
+      #define OPTION_NBINITATENVT_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_CONFIG_ENV_INIT
+      #define OPTION_GFX_CONFIG_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                   GfxConfigEnvInterface;
+      #define OPTION_GFXCONFIGENVINTERFACE_ENTRY           {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
+    #else
+      #define  OPTION_GFXCONFIGENVINTERFACE_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_ENV_INIT
+      #define OPTION_GFX_ENV_INIT TRUE
+    #endif
+    #if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtEnvPost;
+      #define OPTION_GFXINITATENVPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
+    #else
+      #define OPTION_GFXINITATENVPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_POWER_GATE
+      #define OPTION_POWER_GATE TRUE
+    #endif
+    #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  F12NbPowerGateFeature;
+      #define OPTION_F12NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_LN, F12NbPowerGateFeature},
+    #else
+      #define OPTION_F12NBPOWERGATEFEATURE_ENTRY
+    #endif
+    #if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbPowerGateFeature;
+      #define OPTION_F14NBPOWERGATEFEATURE_ENTRY          {AMD_FAMILY_ON, F14NbPowerGateFeature},
+    #else
+      #define OPTION_F14NBPOWERGATEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_ENV_INIT
+      #define OPTION_PCIE_ENV_INIT TRUE
+    #endif
+    #if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtEnv;
+      #define OPTION_PCIEINITATENV_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
+    #else
+      #define OPTION_PCIEINITATENV_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+
+    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
+      OPTION_NBFUSETABLEFEATURE_ENTRY
+      OPTION_NBINITATENVT_ENTRY
+      OPTION_PCIEINITATENV_ENTRY
+      OPTION_GFXCONFIGENVINTERFACE_ENTRY
+      OPTION_GFXINITATENVPOST_ENTRY
+      OPTION_F12NBPOWERGATEFEATURE_ENTRY
+      OPTION_F14NBPOWERGATEFEATURE_ENTRY
+      OPTION_KRNBPOWERGATEFEATURE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_MID == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GNB_CABLESAFE
+      #define OPTION_GNB_CABLESAFE TRUE
+    #endif
+    #if (OPTION_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  GnbCableSafeEntry;
+      #define OPTION_GNBCABLESAFEENTRY_ENTRY              {AMD_FAMILY_LN, GnbCableSafeEntry},
+    #else
+      #define OPTION_GNBCABLESAFEENTRY_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_LCLK_NCLK_RATIO
+      #define OPTION_NB_LCLK_NCLK_RATIO TRUE
+    #endif
+    #if (OPTION_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  F14NbLclkNclkRatioFeature;
+      #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY      {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
+    #else
+      #define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_LCLK_DPM_INIT
+      #define OPTION_NB_LCLK_DPM_INIT TRUE
+    #endif
+    #if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbLclkDpmFeature;
+      #define OPTION_NBLCLKDPMFEATURE_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
+    #else
+      #define OPTION_NBLCLKDPMFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIE_POWER_GATE
+      #define OPTION_PCIE_POWER_GATE TRUE
+    #endif
+    #if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
+      OPTION_GNB_FEATURE                                  PciePowerGateFeature;
+      #define OPTION_PCIEPOWERGATEFEATURE_ENTRY           {AMD_FAMILY_LN, PciePowerGateFeature},
+    #else
+      #define OPTION_PCIEPOWERGATEFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_MID_INIT
+      #define OPTION_GFX_MID_INIT TRUE
+    #endif
+    #if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  GfxInitAtMidPost;
+      #define OPTION_GFXINITATMIDPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
+    #else
+      #define OPTION_GFXINITATMIDPOST_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
+      #define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
+    #endif
+    #if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                 GfxIntegratedInfoTableEntry;
+      #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY        {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
+    #else
+      #define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_PCIe_MID_INIT
+      #define OPTION_PCIe_MID_INIT TRUE
+    #endif
+    #if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieInitAtMid;
+      #define OPTION_PCIEINITATMID_ENTRY                  {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
+    #else
+      #define OPTION_PCIEINITATMID_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_NB_MID_INIT
+      #define OPTION_NB_MID_INIT TRUE
+    #endif
+    #if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  NbInitAtLatePost;
+      #define OPTION_NBINITATLATEPOST_ENTRY               {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
+    #else
+      #define OPTION_NBINITATLATEPOST_ENTRY
+    #endif
+
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
+      OPTION_GFXINITATMIDPOST_ENTRY
+      OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
+      OPTION_GNBCABLESAFEENTRY_ENTRY
+      OPTION_PCIEINITATMID_ENTRY
+      OPTION_NBINITATLATEPOST_ENTRY
+      OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
+      OPTION_NBLCLKDPMFEATURE_ENTRY
+      OPTION_PCIEPOWERGATEFEATURE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_ALIB
+      #define OPTION_ALIB FALSE
+    #endif
+    #if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+      OPTION_GNB_FEATURE                                  PcieAlibFeature;
+      #define OPTION_PCIEALIBFEATURE_ENTRY                {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
+    #else
+      #define OPTION_PCIEALIBFEATURE_ENTRY
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    #ifndef OPTION_IOMMU_ACPI_IVRS
+      #define OPTION_IOMMU_ACPI_IVRS TRUE
+    #endif
+  //---------------------------------------------------------------------------------------------------
+    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
+      OPTION_PCIEALIBFEATURE_ENTRY
+      OPTIONIOMMUACPIIVRSLATE_ENTRY
+      {0, NULL}
+    };
+  #endif
+
+  #if  (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+    S3_DISPATCH_FUNCTION  NbSmuServiceRequestS3Script;
+    S3_DISPATCH_FUNCTION  PcieLateRestoreS3Script;
+    S3_DISPATCH_FUNCTION  NbSmuIndirectWriteS3Script;
+    #define GNB_S3_DISPATCH_FUNCTION_TABLE \
+    {NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
+    {NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
+    {PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
+  #endif
+
+
+#endif
+#endif  // _OPTION_GNB_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
new file mode 100644
index 0000000..056777d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionHtInstall.h
@@ -0,0 +1,319 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Ht
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 51975 $   @e \$Date: 2011-04-29 01:33:06 -0600 (Fri, 29 Apr 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HT_INSTALL_H_
+#define _OPTION_HT_INSTALL_H_
+
+#include "Topology.h"
+#include "htFeat.h"
+#include "htInterface.h"
+#include "htNb.h"
+#include "htTopologies.h"
+/*
+ * Advanced Option only, hardware socket naming is the preferred method.
+ */
+#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
+#else
+  #define CFG_SYSTEM_PHYSICAL_SOCKET_MAP         (NULL)
+#endif
+
+/*
+ * OPTION_IS_RECOVERY_HT is true if Basic API is being used.
+ */
+#ifndef OPTION_IS_RECOVERY_HT
+  #define OPTION_IS_RECOVERY_HT TRUE
+#endif
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition.
+ */
+
+#ifndef OPTION_MULTISOCKET
+  #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
+#endif
+
+/*
+ * Based on user level options, set Ht internal options.
+ * For now, Family 10h support will assume single module.  For multi module,
+ * this will have to be changed to not set non-coherent only.
+ */
+#define OPTION_HT_NON_COHERENT_ONLY FALSE
+
+#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+/* Families with only PCIe do not need a non-coherent only option. */
+#else
+  // Process Family 10h and 15h Models 00h-0Fh by socket, applying the MultiSocket option where it is allowable.
+  #if OPTION_G34_SOCKET_SUPPORT == FALSE
+  // Hydra has coherent support, other Family 10h should follow MultiSocket support.
+    #if OPTION_MULTISOCKET == FALSE
+      #undef OPTION_HT_NON_COHERENT_ONLY
+      #define OPTION_HT_NON_COHERENT_ONLY TRUE
+    #endif
+  #endif
+#endif
+
+/*
+ * Macros will generate the correct item reference based on options
+ */
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  // Select the interface and features
+  #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+    #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+    #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNone
+    #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceMapsOnly
+  #else
+      // Family 10h and 15h Models 00h-0Fh
+      #if OPTION_HT_NON_COHERENT_ONLY == FALSE
+        #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesDefault
+        #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceDefault
+      #else
+        #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+        #define INTERNAL_HT_OPTION_FEATURES     &HtFeaturesNonCoherentOnly
+        #define INTERNAL_HT_OPTION_INTERFACE    &HtInterfaceNonCoherentOnly
+      #endif
+    #endif
+  // Select Northbridge components
+  #if OPTION_FAMILY10H == TRUE
+    #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly, &HtFam10RevENbNonCoherentOnly,
+    #else
+      #define INTERNAL_HT_OPTION_FAM10_NB     &HtFam10NbDefault, &HtFam10RevDNbDefault, &HtFam10RevENbDefault,
+    #endif
+  #else
+    #define INTERNAL_HT_OPTION_FAM10_NB
+  #endif
+
+  #if OPTION_FAMILY12H == TRUE
+    #define INTERNAL_HT_OPTION_FAM12_NB     &HtFam12Nb,
+  #else
+    #define INTERNAL_HT_OPTION_FAM12_NB
+  #endif
+
+  #if OPTION_FAMILY14H == TRUE
+      #define INTERNAL_HT_OPTION_FAM14_NB     &HtFam14Nb,
+  #else
+    #define INTERNAL_HT_OPTION_FAM14_NB
+  #endif
+
+  #if OPTION_FAMILY15H == TRUE
+    #if OPTION_FAMILY15H_OR == TRUE
+      #if OPTION_HT_NON_COHERENT_ONLY == TRUE
+        #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbNonCoherentOnly,
+      #else
+        #define INTERNAL_HT_OPTION_FAM15_NB     &HtFam15NbDefault,
+      #endif
+    #else
+      #define INTERNAL_HT_OPTION_FAM15_NB
+    #endif
+      #define INTERNAL_HT_OPTION_FAM15TN_NB
+      #define INTERNAL_HT_OPTION_FAM15KM_NB
+  #else
+    #define INTERNAL_HT_OPTION_FAM15_NB
+    #define INTERNAL_HT_OPTION_FAM15TN_NB
+    #define INTERNAL_HT_OPTION_FAM15KM_NB
+  #endif
+
+  #define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
+  #ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
+    #undef INTERNAL_ONLY_NB_LIST_ITEM
+    #define INTERNAL_ONLY_NB_LIST_ITEM
+  #endif
+
+  /* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
+   * is ok to have a comma because the final item (NULL) is added below.
+   */
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS \
+                                             INTERNAL_ONLY_NB_LIST_ITEM \
+                                             INTERNAL_HT_OPTION_FAM10_NB \
+                                             INTERNAL_HT_OPTION_FAM15_NB \
+                                             INTERNAL_HT_OPTION_FAM12_NB \
+                                             INTERNAL_HT_OPTION_FAM14_NB
+#else
+  // Not Init Early
+  #define INTERNAL_HT_OPTION_FEATURES     NULL
+  #define INTERNAL_HT_OPTION_INTERFACE    NULL
+  #define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
+  #define HT_OPTIONS_PLATFORM             NULL
+  #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
+#endif
+
+#ifdef AGESA_ENTRY_INIT_EARLY
+  #if AGESA_ENTRY_INIT_EARLY == TRUE
+
+    extern HT_FEATURES HtFeaturesDefault;
+    extern HT_FEATURES HtFeaturesNonCoherentOnly;
+    extern HT_FEATURES HtFeaturesCoherentOnly;
+    extern HT_FEATURES HtFeaturesNone;
+    extern HT_INTERFACE HtInterfaceDefault;
+    extern HT_INTERFACE HtInterfaceNonCoherentOnly;
+    extern HT_INTERFACE HtInterfaceCoherentOnly;
+    extern HT_INTERFACE HtInterfaceMapsOnly;
+    extern HT_INTERFACE HtInterfaceNone;
+    extern NORTHBRIDGE HtFam10NbDefault;
+    extern NORTHBRIDGE HtFam10RevDNbDefault;
+    extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam10RevENbDefault;
+    extern NORTHBRIDGE HtFam10RevENbNonCoherentOnly;
+    extern NORTHBRIDGE HtFam12Nb;
+    extern NORTHBRIDGE HtFam14Nb;
+    extern NORTHBRIDGE HtFam10NbNone;
+    extern NORTHBRIDGE HtFam15NbDefault;
+    extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
+
+    CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
+      INTERNAL_HT_OPTION_SUPPORTED_NBS
+      NULL
+    };
+
+    STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
+    {
+      CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      (DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
+      (CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
+      (IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
+      (OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
+      (IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
+      (SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
+      (UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
+      (SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
+    };
+    #ifndef HT_OPTIONS_PLATFORM
+      #define HT_OPTIONS_PLATFORM &HtOptionsPlatform
+    #endif
+
+    /**
+     * A list of all the supported topologies.
+     *
+     */
+    #ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+      CONST UINT8 *CONST ROMDATA AmdTopolist[] =
+      {
+        amdHtTopologySingleNode,
+        amdHtTopologyDualNode,
+        amdHtTopologyThreeLine,
+        amdHtTopologyTriangle,
+        amdHtTopologyFourLine,
+        amdHtTopologyFourStar,
+        amdHtTopologyFourDegenerate,
+        amdHtTopologyFourSquare,
+        amdHtTopologyFourKite,
+        amdHtTopologyFourFully,
+        amdHtTopologyFiveFully,
+        amdHtTopologyFiveTwistedLadder,
+        amdHtTopologySixFully,
+        amdHtTopologySixDoubloonLower,
+        amdHtTopologySixDoubloonUpper,
+        amdHtTopologySixTwistedLadder,
+        amdHtTopologySevenFully,
+        amdHtTopologySevenTwistedLadder,
+        amdHtTopologyEightFully,
+        amdHtTopologyEightDoubloon,
+        amdHtTopologyEightTwistedLadder,
+        amdHtTopologyEightStraightLadder,
+        amdHtTopologySixTwinTriangles,
+        amdHtTopologyEightTwinFullyFourWays,
+        NULL
+      };
+      #define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
+    #endif
+
+    /**
+     * Declare the instance of the Ht option configuration structure
+     */
+    CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
+      OPTION_IS_RECOVERY_HT,
+      CFG_SET_HTCRC_SYNC_FLOOD,
+      CFG_USE_UNIT_ID_CLUMPING,
+      HT_OPTIONS_PLATFORM,
+      INTERNAL_HT_OPTION_INTERFACE,
+      INTERNAL_HT_OPTION_FEATURES,
+      &HtInstalledFamilyNorthbridgeList,
+      INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
+    };
+
+  #endif
+#endif
+
+#ifndef OPTION_HT_INIIT_RESET_ENTRY
+
+  #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+  #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
+
+  #if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE))
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY NULL
+    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
+  #endif
+
+  #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
+    #undef OPTION_HT_INIIT_RESET_ENTRY
+    #undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    #define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
+    #define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
+  #endif
+
+#endif
+
+#ifdef AGESA_ENTRY_INIT_RESET
+  #if AGESA_ENTRY_INIT_RESET == TRUE
+
+    CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
+      (MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
+      0                                            // Unused by options
+    };
+
+    CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
+      OPTION_HT_INIIT_RESET_ENTRY,
+      OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
+    };
+  #endif
+
+#endif
+
+#endif  // _OPTION_HT_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h
new file mode 100644
index 0000000..4580809
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionHwC1eInstall.h
@@ -0,0 +1,81 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: HW C1e
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_HW_C1E_INSTALL_H_
+#define _OPTION_HW_C1E_INSTALL_H_
+
+#include "cpuHwC1e.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_HW_C1E_FEAT
+#define F10_HW_C1E_SUPPORT
+#if AGESA_ENTRY_INIT_EARLY == TRUE
+  #ifdef OPTION_FAMILY10H
+    #if OPTION_FAMILY10H == TRUE
+      #if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
+        extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
+        #undef OPTION_HW_C1E_FEAT
+        #define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
+        extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
+        #undef F10_HW_C1E_SUPPORT
+        #define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
+      #endif
+    #endif
+  #endif
+  CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
+  {
+    F10_HW_C1E_SUPPORT
+    {0, NULL}
+  };
+  CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
+  {
+    (sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+    &HwC1eFamilyServiceArray[0]
+  };
+#endif
+
+#endif  // _OPTION_HW_C1E_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
new file mode 100644
index 0000000..16cd68c
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIdsInstall.h
@@ -0,0 +1,588 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option Install File
+ *
+ * This file generates the defaults tables for family 10h model 5 processors.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Core
+ * @e \$Revision: 55277 $   @e \$Date: 2011-06-19 23:03:21 -0600 (Sun, 19 Jun 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_INSTALL_H_
+#define _OPTION_IDS_INSTALL_H_
+#include "Ids.h"
+#include "IdsHt.h"
+#include "IdsLib.h"
+#ifdef __IDS_EXTENDED__
+  #include OPTION_IDS_EXT_INSTALL_FILE
+#endif
+
+#define IDS_LATE_RUN_AP_TASK
+
+#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    // Check for all families which include HT Features.
+    #if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE) || (OPTION_FAMILY15H_KM == TRUE)) && (AGESA_ENTRY_INIT_POST == TRUE)
+      #undef M_HTIDS_PORT_OVERRIDE_HOOK
+      #define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
+    #endif
+  #endif
+#endif // OPTION_IDS_LEVEL
+CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
+
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_LATE == TRUE)
+    #undef IDS_LATE_RUN_AP_TASK
+    #define IDS_LATE_RUN_AP_TASK
+  #endif
+#endif // OPTION_IDS_LEVEL
+
+#if (IDSOPT_TRACING_ENABLED == TRUE)
+  #if (AGESA_ENTRY_INIT_POST == TRUE)
+    #include <mu.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
+      { (UINT32) (UINT64) MemUReadCachelines,  "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
+      { (UINT32) (UINT64) MemUFlushPattern,    "FlushCl(PhyAddrLo,ClCnt)"}
+    };
+  #elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
+    #include <mru.h>
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
+      { (UINT32) (UINT64) MemRecURead1CL,  "Read1Cl(BufferAddr,PhyAddrLo)"},
+      { (UINT32) (UINT64) MemRecUFlushPattern,    "Flush1Cl(PhyAddrLo)"}
+    };
+  #else
+    CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+      { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
+      { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+    };
+  #endif
+#else
+  CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
+    { (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
+    { (UINT32) (UINT64) CommonReturnFalse,  "DefRet()"},
+    { (UINT32) (UINT64) CommonReturnFalse,    "DefRet()"}
+  };
+#endif
+
+
+#define NV_TO_CMOS(Len, NV_ID) {Len, NV_ID},
+#define OPTION_IDS_NV_TO_CMOS_END NV_TO_CMOS (IDS_NV_TO_CMOS_LEN_END, IDS_NV_TO_CMOS_ID_END)
+#if (IDSOPT_IDS_ENABLED == TRUE)
+  #if ((IDSOPT_CONTROL_ENABLED == TRUE) && \
+       ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+        (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+        (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+    #if (IDSOPT_CONTROL_NV_TO_CMOS == TRUE)
+      #define OPTION_IDS_NV_TO_CMOS_COMMON
+
+      #ifdef OPTION_FAMILY10H
+        #if OPTION_FAMILY10H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F10
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY12H
+        #if OPTION_FAMILY12H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F12
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY14H
+        #if OPTION_FAMILY14H == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F14
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY15H_OR
+        #if OPTION_FAMILY15H_OR == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F15_OR
+        #endif
+      #endif
+
+      #ifdef OPTION_FAMILY15H_TN
+        #if OPTION_FAMILY15H_TN == TRUE
+          #define OPTION_IDS_NV_TO_CMOS_F15_TN\
+            {IDS_NV_TO_CMOS_LEN_BYTE, AGESA_IDS_NV_UCODE},
+        #endif
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F10
+        #define OPTION_IDS_NV_TO_CMOS_F10
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F12
+        #define OPTION_IDS_NV_TO_CMOS_F12
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F14
+        #define OPTION_IDS_NV_TO_CMOS_F14
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F15_OR
+        #define OPTION_IDS_NV_TO_CMOS_F15_OR
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_F15_TN
+        #define OPTION_IDS_NV_TO_CMOS_F15_TN
+      #endif
+
+      #ifndef OPTION_IDS_NV_TO_CMOS_EXTEND
+        #define OPTION_IDS_NV_TO_CMOS_EXTEND
+      #endif
+
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_COMMON
+        OPTION_IDS_NV_TO_CMOS_F10
+        OPTION_IDS_NV_TO_CMOS_F12
+        OPTION_IDS_NV_TO_CMOS_F14
+        OPTION_IDS_NV_TO_CMOS_F15_OR
+        OPTION_IDS_NV_TO_CMOS_F15_TN
+        OPTION_IDS_NV_TO_CMOS_EXTEND
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #else
+      IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+        OPTION_IDS_NV_TO_CMOS_END
+      };
+    #endif
+  #else
+    IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+      OPTION_IDS_NV_TO_CMOS_END
+    };
+  #endif
+#else
+  IDS_NV_TO_CMOS gIdsNVToCmos[] = {
+    OPTION_IDS_NV_TO_CMOS_END
+  };
+#endif
+
+///Ids Feat Options
+#if ((IDSOPT_IDS_ENABLED == TRUE) && \
+     ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || \
+      (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || \
+      (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)))
+  #if (IDSOPT_CONTROL_ENABLED == TRUE)
+    #ifndef OPTION_IDS_EXTEND_FEATS
+      #define OPTION_IDS_EXTEND_FEATS
+    #endif
+
+    #define OPTION_IDS_FEAT_ECCCTRL\
+                OPTION_IDS_FEAT_ECCCTRL_F10 \
+                OPTION_IDS_FEAT_ECCCTRL_F12 \
+                OPTION_IDS_FEAT_ECCCTRL_F15_OR
+
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 \
+                OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+
+    #define OPTION_IDS_FEAT_CPB_CTRL\
+                OPTION_IDS_FEAT_CPB_CTRL_F12
+
+    #define OPTION_IDS_FEAT_HTC_CTRL\
+                OPTION_IDS_FEAT_HTC_CTRL_F15_OR \
+                OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING\
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR \
+                OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+
+    #define OPTION_IDS_FEAT_HT_ASSIST\
+                OPTION_IDS_FEAT_HT_ASSIST_F10HY \
+                OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
+                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
+                OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+
+/*----------------------------------------------------------------------------
+ *                        Family 10 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
+    #define OPTION_IDS_FEAT_ECCCTRL_F10
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+//Ecc symbol size
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
+        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
+        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
+
+//ECC scrub control
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F10
+        #define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
+      #endif
+    #endif
+
+    //Misc Features
+    #define OPTION_IDS_FEAT_HT_ASSIST_F10HY
+    #ifdef OPTION_FAMILY10H_HY
+      #if OPTION_FAMILY10H_HY == TRUE
+        #undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
+
+        #define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
+                    &IdsFeatHtAssistBlockPlatformCfgF10Hy,
+      #endif
+    #endif
+/*----------------------------------------------------------------------------
+ *                        Family 12 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
+    #define OPTION_IDS_FEAT_ECCCTRL_F12
+    #define OPTION_IDS_FEAT_CPB_CTRL_F12
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
+
+        //ECC scrub control
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F12
+        #define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
+
+        #undef OPTION_IDS_FEAT_CPB_CTRL_F12
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
+        #define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryChIntlvPostBeforeBlockF12;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF12;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F12
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
+                    &IdsFeatMemoryChIntlvPostBeforeBlockF12, \
+                    &IdsFeatMemoryMappingChIntlvBlockF12,
+
+      #endif
+    #endif
+
+/*----------------------------------------------------------------------------
+ *                        Family 14 feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
+      #endif
+    #endif
+
+/*----------------------------------------------------------------------------
+ *                        Family 15 OR feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
+    #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+    #define OPTION_IDS_FEAT_ECCCTRL_F15_OR
+    #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+    #ifdef OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
+        #define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
+                    &IdsFeatHtcControlBlockF15Or,\
+                    &IdsFeatHtcControlLateBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
+        &IdsFeatMemoryMappingPostBeforeBlockF15Or,\
+        &IdsFeatMemoryMappingChIntlvBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
+        #undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
+        #define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
+        &IdsFeatHtAssistBlockPlatformCfgF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
+        #undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
+        #define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
+        #undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
+        #define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
+
+      #endif
+    #endif
+/*----------------------------------------------------------------------------
+ *                        Family 15 TN feat blocks
+ *
+ *----------------------------------------------------------------------------
+ */
+    #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+    #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+    #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+    #ifdef OPTION_FAMILY15H_TN
+      #if OPTION_FAMILY15H_TN == TRUE
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Tn;
+        #undef OPTION_IDS_FEAT_HTC_CTRL_F15_TN
+        #define OPTION_IDS_FEAT_HTC_CTRL_F15_TN\
+                    &IdsFeatHtcControlBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Tn;
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Tn;
+        #undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN
+        #define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_TN\
+        &IdsFeatMemoryMappingPostBeforeBlockF15Tn,\
+        &IdsFeatMemoryMappingChIntlvBlockF15Tn,
+
+        extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF15Tn;
+        #undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN
+        #define OPTION_IDS_FEAT_GNB_PLATFORMCFGF15TN &IdsFeatGnbPlatformCfgBlockF15Tn,
+      #endif
+    #endif
+
+    #define OPTION_IDS_FEAT_NV_TO_CMOS
+    #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+      #undef OPTION_IDS_FEAT_NV_TO_CMOS
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosSaveBlock;
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatNvToCmosRestoreBlock;
+      #define OPTION_IDS_FEAT_NV_TO_CMOS\
+        &IdsFeatNvToCmosSaveBlock, \
+        &IdsFeatNvToCmosRestoreBlock,
+
+    #endif
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
+    {
+      IDS_FEAT_UCODE_UPDATE,
+      IDS_ALL_CORES,
+      IDS_UCODE,
+      IDS_FAMILY_ALL,
+      IdsSubUCode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
+    {
+      IDS_FEAT_POWER_POLICY,
+      IDS_ALL_CORES,
+      IDS_PLATFORMCFG_OVERRIDE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerPolicyOverride
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
+    {
+      IDS_FEAT_TARGET_PSTATE,
+      IDS_BSP_ONLY,
+      IDS_INIT_LATE_AFTER,
+      IDS_FAMILY_ALL,
+      IdsSubTargetPstate
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
+    {
+      IDS_FEAT_POSTPSTATE,
+      IDS_ALL_CORES,
+      IDS_CPU_Early_Override,
+      IDS_FAMILY_ALL,
+      IdsSubPostPState
+    };
+
+    //Dram controller Features
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
+    {
+      IDS_FEAT_DCT_ALLMEMCLK,
+      IDS_BSP_ONLY,
+      IDS_ALL_MEMORY_CLOCK,
+      IDS_FAMILY_ALL,
+      IdsSubAllMemClkEn
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
+    {
+      IDS_FEAT_DCT_GANGMODE,
+      IDS_BSP_ONLY,
+      IDS_GANGING_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubGangingMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
+    {
+      IDS_FEAT_DCT_BURSTLENGTH,
+      IDS_BSP_ONLY,
+      IDS_BURST_LENGTH32,
+      AMD_FAMILY_10,
+      IdsSubBurstLength32
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_INIT_POST_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownCtrl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
+    {
+      IDS_FEAT_DCT_DLLSHUTDOWN,
+      IDS_BSP_ONLY,
+      IDS_DLL_SHUT_DOWN,
+      IDS_FAMILY_ALL,
+      IdsSubDllShutDownSR
+    };
+
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
+    {
+      IDS_FEAT_DCT_POWERDOWN,
+      IDS_BSP_ONLY,
+      IDS_POWERDOWN_MODE,
+      IDS_FAMILY_ALL,
+      IdsSubPowerDownMode
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
+    {
+      IDS_FEAT_HDTOUT,
+      IDS_BSP_ONLY,
+      IDS_INIT_EARLY_BEFORE,
+      IDS_FAMILY_ALL,
+      IdsSubHdtOut
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
+    {
+      IDS_FEAT_HT_SETTING,
+      IDS_BSP_ONLY,
+      IDS_HT_CONTROL,
+      IDS_FAMILY_ALL,
+      IdsSubHtLinkControl
+    };
+
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+    {
+      &IdsFeatUcodeBlock,
+      &IdsFeatPowerPolicyBlock,
+
+      &IdsFeatTargetPstateBlock,
+
+      &IdsFeatPostPstateBlock,
+
+      OPTION_IDS_FEAT_NV_TO_CMOS
+
+      OPTION_IDS_FEAT_ECCSYMBOLSIZE
+
+      OPTION_IDS_FEAT_ECCCTRL
+
+      &IdsFeatDctAllMemClkBlock,
+
+      &IdsFeatDctGangModeBlock,
+
+      &IdsFeatDctBurstLengthBlock,
+
+      &IdsFeatDctPowerDownCtrlBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      &IdsFeatDctPowerDownModeBlock,
+
+      OPTION_IDS_FEAT_HT_ASSIST
+
+      &IdsFeatHdtOutBlock,
+
+      &IdsFeatHtSettingBlock,
+
+      OPTION_IDS_FEAT_GNB_PLATFORMCFG
+
+      OPTION_IDS_FEAT_CPB_CTRL
+
+      OPTION_IDS_FEAT_HTC_CTRL
+
+      OPTION_IDS_FEAT_MEMORY_MAPPING
+
+      OPTION_IDS_EXTEND_FEATS
+
+      NULL
+    };
+  #else
+    CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+    {
+      NULL
+    };
+  #endif//IDSOPT_CONTROL_ENABLED
+
+  #define OPTION_IDS_FAM_REGACC\
+            OPTION_IDS_FAM_REGACC_F15TN
+
+  #define OPTION_IDS_FAM_REGACC_F15TN
+  #ifdef OPTION_FAMILY15H_TN
+    #if OPTION_FAMILY15H_TN == TRUE
+      extern CONST IDS_FAMILY_FEAT_STRUCT ROMDATA IdsFeatRegGmmxF15Tn;
+      #undef OPTION_IDS_FAM_REGACC_F15TN
+      #define OPTION_IDS_FAM_REGACC_F15TN \
+                &IdsFeatRegGmmxF15Tn,
+    #endif
+  #endif
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    OPTION_IDS_FAM_REGACC
+    NULL
+  };
+
+#else
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsContorlFeats[] =
+  {
+    NULL
+  };
+
+  CONST IDS_FAMILY_FEAT_STRUCT* ROMDATA IdsRegAccessTbl[] =
+  {
+    NULL
+  };
+#endif// IDSOPT_IDS_ENABLED
+
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
new file mode 100644
index 0000000..f83ad70
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionIoCstateInstall.h
@@ -0,0 +1,133 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: IO C-state
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 44324 $   @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_IO_CSTATE_INSTALL_H_
+#define _OPTION_IO_CSTATE_INSTALL_H_
+
+#include "cpuIoCstate.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+#define OPTION_IO_CSTATE_FEAT
+#define F10_IO_CSTATE_SUPPORT
+#define F12_IO_CSTATE_SUPPORT
+#define F14_IO_CSTATE_SUPPORT
+#define F15_OR_IO_CSTATE_SUPPORT
+
+#if OPTION_IO_CSTATE == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    #ifdef OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_PH == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
+          #undef F10_IO_CSTATE_SUPPORT
+          #define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY12H
+      #if OPTION_FAMILY12H == TRUE
+        #if OPTION_FAMILY12H_LN == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
+          #undef F12_IO_CSTATE_SUPPORT
+          #define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if (OPTION_FAMILY14H_ON == TRUE)
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
+          #undef F14_IO_CSTATE_SUPPORT
+          #define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
+          #undef OPTION_IO_CSTATE_FEAT
+          #define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
+          extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
+          #undef F15_OR_IO_CSTATE_SUPPORT
+          #define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
+        #endif
+      #endif
+    #endif
+
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
+{
+  F10_IO_CSTATE_SUPPORT
+  F12_IO_CSTATE_SUPPORT
+  F14_IO_CSTATE_SUPPORT
+  F15_OR_IO_CSTATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
+{
+  (sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &IoCstateFamilyServiceArray[0]
+};
+
+#endif // _OPTION_IO_CSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
new file mode 100644
index 0000000..5804f1d
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: L3 Dependent Features
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56186 $   @e \$Date: 2011-07-08 15:35:23 -0600 (Fri, 08 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_L3_FEATURES_INSTALL_H_
+#define _OPTION_L3_FEATURES_INSTALL_H_
+
+#include "cpuL3Features.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_L3_FEAT
+#define F10_L3_FEAT_SUPPORT
+#define F15_OR_L3_FEAT_SUPPORT
+#define F15_KM_L3_FEAT_SUPPORT
+#define L3_FEAT_AP_DISABLE_CACHE
+#define L3_FEAT_AP_ENABLE_CACHE
+
+#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
+    extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
+
+    #ifdef  OPTION_FAMILY10H
+      #if OPTION_FAMILY10H == TRUE
+        #if OPTION_FAMILY10H_HY == TRUE
+          #undef OPTION_L3_FEAT
+          #define OPTION_L3_FEAT &CpuL3Features,
+          extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
+          #undef F10_L3_FEAT_SUPPORT
+          #define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
+        #endif
+      #endif
+    #endif
+
+    #ifdef  OPTION_FAMILY15H_OR
+      #if OPTION_FAMILY15H_OR == TRUE
+        #undef OPTION_L3_FEAT
+        #define OPTION_L3_FEAT &CpuL3Features,
+        extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
+        #undef F15_OR_L3_FEAT_SUPPORT
+        #define F15_OR_L3_FEAT_SUPPORT {AMD_FAMILY_15_OR, &F15OrL3Features},
+      #endif
+    #endif
+
+    #ifdef OPTION_FAMILY15H_KM
+      #if OPTION_FAMILY15H_KM == TRUE
+        #undef OPTION_L3_FEAT
+        #define OPTION_L3_FEAT &CpuL3Features,
+        extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15KmL3Features;
+        #undef F15_KM_L3_FEAT_SUPPORT
+        #define F15_KM_L3_FEAT_SUPPORT {AMD_FAMILY_15_KM, &F15KmL3Features},
+      #endif
+    #endif
+
+    #undef AGESA_ENTRY_LATE_RUN_AP_TASK
+    #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
+    #undef L3_FEAT_AP_DISABLE_CACHE
+    #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
+    #undef L3_FEAT_AP_ENABLE_CACHE
+    #define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
+{
+  F10_L3_FEAT_SUPPORT
+  F15_OR_L3_FEAT_SUPPORT
+  F15_KM_L3_FEAT_SUPPORT
+  {0, NULL}
+};
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
+{
+  (sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &L3FeatureFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_L3_FEATURES_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h
new file mode 100644
index 0000000..9950d94
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionLowPwrPstateInstall.h
@@ -0,0 +1,89 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Low Power Pstate for PROCHOT_L Throttling.
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 53056 $   @e \$Date: 2011-05-13 23:48:24 -0600 (Fri, 13 May 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
+
+#include "cpuLowPwrPstate.h"
+
+/*  This option is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
+#define F15_OR_LOW_PWR_PSTATE_SUPPORT
+
+#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+    // Family 15h
+    #ifdef OPTION_FAMILY15H
+      #if OPTION_FAMILY15H == TRUE
+        #if OPTION_FAMILY15H_OR == TRUE
+          #if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
+            extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
+            #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
+            #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
+            extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
+            #undef F15_OR_LOW_PWR_PSTATE_SUPPORT
+            #define F15_OR_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
+          #endif
+        #endif
+      #endif
+    #endif
+  #endif
+#endif
+
+CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
+{
+  F15_OR_LOW_PWR_PSTATE_SUPPORT
+  {0, NULL}
+};
+
+CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
+{
+  (sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
+  &LowPwrPstateFamilyServiceArray[0]
+};
+
+#endif  // _OPTION_LOW_PWR_PSTATE_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h
new file mode 100644
index 0000000..2635dbc
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemory.h
@@ -0,0 +1,358 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Memory option API.
+ *
+ * Contains structures and values used to control the Memory option code.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  OPTION
+ * @e \$Revision: 55039 $   @e \$Date: 2011-06-15 23:31:36 -0600 (Wed, 15 Jun 2011) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#ifndef _OPTION_MEMORY_H_
+#define _OPTION_MEMORY_H_
+
+/* Memory Includes */
+#include "mm.h"
+#include "mn.h"
+#include "mt.h"
+#include "ma.h"
+#include "mp.h"
+/*----------------------------------------------------------------------------------------
+ *          M I X E D   (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ *                 D E F I N I T I O N S     A N D     M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+#define MAX_FF_TYPES      6   ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
+
+/*----------------------------------------------------------------------------------------
+ *               T Y P E D E F S,   S T R U C T U R E S,    E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/*
+* STANDARD MEMORY FEATURE FUNCTION POINTER
+*/
+
+typedef BOOLEAN OPTION_MEM_FEATURE_NB (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+typedef BOOLEAN MEM_TECH_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr
+  );
+
+typedef UINT8 MEM_TABLE_FEAT (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+
+#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION  0x01
+
+/**
+ *  MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Northbridge devices supported by
+ *  AGESA.
+ */
+typedef struct _MEM_FEAT_BLOCK_NB {
+  UINT16              OptMemFeatVersion; ///< Version of memory feature block.
+  OPTION_MEM_FEATURE_NB  *OnlineSpare; ///< Online spare support.
+  OPTION_MEM_FEATURE_NB  *InterleaveBanks; ///< Bank (Chip select) interleaving support.
+  OPTION_MEM_FEATURE_NB  *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
+  OPTION_MEM_FEATURE_NB  *CheckInterleaveNodes; ///< Check for Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveNodes; ///< Node interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveChannels; ///< Channel interleaving support.
+  OPTION_MEM_FEATURE_NB  *InterleaveRegion;  ///< Interleave Region support.
+  OPTION_MEM_FEATURE_NB  *CheckEcc; ///< Check for ECC support.
+  OPTION_MEM_FEATURE_NB  *InitEcc; ///< ECC support.
+  OPTION_MEM_FEATURE_NB  *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
+  OPTION_MEM_FEATURE_NB  *LvDdr3; ///< Low voltage DDR3 dimm support
+  OPTION_MEM_FEATURE_NB  *OnDimmThermal; ///< On-Dimm thermal management
+  MEM_TECH_FEAT  *DramInit; ///< Choose the type of Dram init (hardware based or software based).
+  OPTION_MEM_FEATURE_NB  *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_NB  *InitEarlySampleSupport; ///< Initialize early sample support.
+  OPTION_MEM_FEATURE_NB  *InitCPG; ///< Continuous pattern generation.
+  OPTION_MEM_FEATURE_NB  *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
+} MEM_FEAT_BLOCK_NB;
+
+typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemMainPtr
+  );
+
+typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+typedef BOOLEAN MEM_NB_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       MEM_FEAT_BLOCK_NB *FeatPtr,
+  IN       MEM_SHARED_DATA *mmSharedPtr,     ///< Pointer to Memory scratchpad
+  IN       UINT8 NodeID
+  );
+
+typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN OUT   MEM_NB_BLOCK   *NBPtr
+  );
+
+typedef VOID MEM_INITIALIZER (
+  IN OUT   MEM_DATA_STRUCT *MemPtr
+ );
+
+typedef AGESA_STATUS MEM_PLATFORM_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN UINT8 SocketID,
+  IN CH_DEF_STRUCT *CurrentChannel
+  );
+
+typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef VOID MEM_TECH_TRAINING_FEAT (
+  IN OUT   MEM_TECH_BLOCK *TechPtr,
+  IN       UINT8 Pass
+  );
+
+typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
+  IN struct _MEM_DATA_STRUCT *MemData,
+  IN OUT   CH_DEF_STRUCT *CurrentChannel,
+  IN OUT   MEM_PS_BLOCK *PsPtr
+  );
+
+typedef AGESA_STATUS MEM_FLOW_CFG (
+  IN OUT   MEM_MAIN_DATA_BLOCK *MemData
+  );
+
+#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION  0x01
+
+/**
+ * MAIN FEATURE BLOCK - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_BLOCK_MAIN {
+  UINT16              OptMemFeatVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
+  OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
+  OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
+  OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
+  OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
+  OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
+  OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
+  OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
+  OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
+  OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
+  OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
+} MEM_FEAT_BLOCK_MAIN;
+
+#define MEM_NB_SUPPORT_STRUCT_VERSION  0x01
+#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION  0x01
+#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION  0x01
+#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
+/**
+ *  MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_FEAT_BLOCK {
+  UINT16  OptMemTechFeatVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
+  MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
+  MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
+  MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
+  MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
+  MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
+  MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
+  MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
+  MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
+  MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
+  MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
+  MEM_TECH_FEAT *RdDqs__Training; ///< Read DQS Training
+} MEM_TECH_FEAT_BLOCK;
+
+/**
+ *  MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
+ *  memory feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various LRDIMM features supported by
+ *  AGESA.
+ */
+typedef struct _MEM_TECH_LRDIMM {
+  UINT16  OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
+  MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
+} MEM_TECH_LRDIMM;
+/**
+ * MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
+ * options together in a list to provide a single access point for all code to use
+ * and to ensure that everything corresponding to the same NB type is grouped together.
+ *
+ * The Technology Block pointers are not included in this structure because DRAM technology
+ * needs to be decoupled from the northbridge type.
+ *
+ */
+typedef struct _MEM_NB_SUPPORT {
+  UINT16              MemNBSupportVersion; ///< Version of northbridge support.
+  MEM_NB_CONSTRUCTOR  *MemConstructNBBlock; ///< NorthBridge block constructor.
+  MEM_INITIALIZER     *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
+  MEM_FEAT_BLOCK_NB      *MemFeatBlock; ///< Memory feature block.
+  MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
+  MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
+} MEM_NB_SUPPORT;
+
+/*
+ *  MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
+ *  memory non-training feature implementation functions.  It contains vectors for all of the
+ *  features that are supported by the various Technology devices supported by
+ *  AGESA.
+ */
+
+/**
+ * MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
+ * that shared between all northbridge devices.
+ */
+typedef struct _MEM_FEAT_TRAIN_SEQ {
+  UINT16              OptMemTrainingSequenceListVersion; ///< Version of main feature block.
+  OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
+  OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
+  MEM_TECH_FEAT_BLOCK      *MemTechFeatBlock; ///< Memory feature block.
+} MEM_FEAT_TRAIN_SEQ;
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
+ * entries which are used by PSC engine
+ */
+typedef struct _MEM_PSC_TABLE_BLOCK {
+  PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
+  PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
+  PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
+  PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
+  PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
+  PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
+  PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
+  PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
+  PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
+  PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
+  PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
+  PSC_TBL_ENTRY **TblEntryOfS__; ///< Table entry of training configs
+  PSC_TBL_ENTRY **TblEntryOfWLSeed; ///< Table entry of WL seed
+  PSC_TBL_ENTRY **TblEntryOfHWRxENSeed; ///< Table entry of HW RxEN seed
+} MEM_PSC_TABLE_BLOCK;
+
+typedef BOOLEAN MEM_PSC_FLOW (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       MEM_PSC_TABLE_BLOCK *EntryOfTables
+  );
+
+/**
+ * PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
+ * specific configuration.
+ */
+typedef struct _MEM_PSC_FLOW_BLOCK {
+  MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
+  MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
+  MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
+  MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
+  MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
+  MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
+  MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
+  MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
+  MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
+  MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
+  MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
+  MEM_PSC_FLOW *S__; ///< Sub-engine which performs training configuration  checking
+  MEM_PSC_FLOW *TrainingSeedVal; ///< Sub-engine for WL and HW RxEn pass1 seed value extraction
+} MEM_PSC_FLOW_BLOCK;
+
+/*----------------------------------------------------------------------------------------
+ *                        F U N C T I O N    P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+/* Feature Default Return */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  );
+
+BOOLEAN MemMDefRet (
+  IN MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
+/* Table Feature Default Return */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  );
+/* S3 Feature Default Return */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
+BOOLEAN
+MemProcessConditionalOverrides (
+  IN       PSO_TABLE *PlatformMemoryConfiguration,
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN       UINT8 PsoAction,
+  IN       UINT8 Dimm
+   );
+
+#endif  // _OPTION_MEMORY_H_
diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
new file mode 100644
index 0000000..24c1ae8
--- /dev/null
+++ b/src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h
@@ -0,0 +1,3778 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Install of build option: Memory
+ *
+ * Contains AMD AGESA install macros and test conditions. Output is the
+ * defaults tables reflecting the User's build options selection.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      AGESA
+ * @e sub-project:  Options
+ * @e \$Revision: 56315 $   @e \$Date: 2011-07-11 15:59:14 -0600 (Mon, 11 Jul 2011) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ *       its contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+#ifndef _OPTION_MEMORY_INSTALL_H_
+#define _OPTION_MEMORY_INSTALL_H_
+
+/* Memory Includes */
+#include "OptionMemory.h"
+
+/*-------------------------------------------------------------------------------
+ *  This option file is designed to be included into the platform solution install
+ *  file. The platform solution install file will define the options status.
+ *  Check to validate the definition
+ */
+
+/*----------------------------------------------------------------------------------
+ * FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFDefRet (
+  IN OUT   MEM_NB_BLOCK *NBPtr
+  )
+{
+  return FALSE;
+}
+
+BOOLEAN MemMDefRet (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return TRUE;
+}
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  )
+{
+  return FALSE;
+}
+
+/* -----------------------------------------------------------------------------*/
+/**
+ *
+ *
+ *   This function initializes the northbridge block for dimm identification translator
+ *
+ *     @param[in,out]   *NBPtr   - Pointer to the MEM_NB_BLOCK
+ *     @param[in,out]   *MemPtr  - Pointer to the MEM_DATA_STRUCT
+ *     @param[in,out]   NodeID   - ID of current node to construct
+ *     @return          TRUE     - This is the correct constructor for the targeted node.
+ *     @return          FALSE    - This isn't the correct constructor for the targeted node.
+ */
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return FALSE;
+}
+/*----------------------------------------------------------------------------------
+ * TABLE FEATURE BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+UINT8 MemFTableDefRet (
+  IN OUT   MEM_TABLE_ALIAS **MTPtr
+  )
+{
+  return 0;
+}
+/*----------------------------------------------------------------------------------
+ * FEATURE S3 BLOCK FUNCTIONS
+ *
+ *  This section defines function names that depend upon options that are selected
+ *  in the platform solution install file.
+ */
+BOOLEAN MemFS3DefConstructorRet (
+  IN OUT   VOID *S3NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  )
+{
+  return TRUE;
+}
+
+#if (OPTION_MEMCTLR_DR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemS3ResumeConstructNBBlockDr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDr;
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorDr
+  #else
+    #define MEM_IDENDIMM_DR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_DA == TRUE  || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      #if (OPTION_MEMCTLR_Ni == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockNi;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemS3ResumeConstructNBBlockNi
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_DA == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockDA;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemS3ResumeConstructNBBlockDA
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_PH == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockPh;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemS3ResumeConstructNBBlockPh
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
+      #endif
+      #if (OPTION_MEMCTLR_RB == TRUE)
+        extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockRb;
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemS3ResumeConstructNBBlockRb
+      #else
+        #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
+      #endif
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB MemFS3DefConstructorRet
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorDA;
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorDA
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorRb;
+    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRb
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorPh;
+    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorPh
+  #else
+    #define MEM_IDENDIMM_DA MemNIdentifyDimmConstructorRetDef
+    #define MEM_IDENDIMM_RB MemNIdentifyDimmConstructorRetDef
+    #define MEM_IDENDIMM_PH MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_OR == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockOr;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemS3ResumeConstructNBBlockOr
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorOr;
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorOr
+  #else
+    #define MEM_IDENDIMM_OR MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_HY == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockHy;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemS3ResumeConstructNBBlockHy
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorHy;
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorHy
+  #else
+    #define MEM_IDENDIMM_HY MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+#if (OPTION_MEMCTLR_C32 == TRUE)
+  #if ((AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_S3SAVE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE))
+    #if (OPTION_S3_MEM_SUPPORT == TRUE)
+      extern MEM_RESUME_CONSTRUCTOR MemS3ResumeConstructNBBlockC32;
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemS3ResumeConstructNBBlockC32
+    #else
+      #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+    #endif
+  #else
+    #define MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32 MemFS3DefConstructorRet
+  #endif
+  #if (AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE)
+    extern MEM_IDENDIMM_CONSTRUCTOR MemNIdentifyDimmConstructorC32;
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorC32
+  #else
+    #define MEM_IDENDIMM_C32 MemNIdentifyDimmConstructorRetDef
+  #endif
+#endif
+
+/*----------------------------------------------------------------------------------
+ * NORTHBRIDGE BLOCK CONSTRUCTOR AND INITIALIZER FUNCTION DEFAULT ASSIGNMENTS
+ *
+ *----------------------------------------------------------------------------------
+*/
+#define MEM_NB_SUPPORT_DR
+#define MEM_NB_SUPPORT_RB
+#define MEM_NB_SUPPORT_DA
+#define MEM_NB_SUPPORT_Ni
+#define MEM_NB_SUPPORT_PH
+#define MEM_NB_SUPPORT_HY
+#define MEM_NB_SUPPORT_OR
+#define MEM_NB_SUPPORT_C32
+#define MEM_NB_SUPPORT_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0, 0, 0 }
+
+#if (AGESA_ENTRY_INIT_POST == TRUE)
+  /*----------------------------------------------------------------------------------
+   * FLOW CONTROL FUNCTION
+   *
+   *  This section selects the function that controls the memory initialization sequence
+   *  based upon the number of processor families that the BIOS will support.
+   */
+  extern MEM_FLOW_CFG MemMFlowDef;
+  extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
+
+
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDr;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_DA == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDA;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    extern MEM_FLOW_CFG MemMFlowHy;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    extern MEM_FLOW_CFG MemMFlowOr;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    extern MEM_FLOW_CFG MemMFlowC32;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_Ni == TRUE)
+    extern MEM_FLOW_CFG MemMFlowDA;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_RB == TRUE)
+    extern MEM_FLOW_CFG MemMFlowRb;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
+  #endif
+  #if (OPTION_MEMCTLR_PH == TRUE)
+    extern MEM_FLOW_CFG MemMFlowPh;
+    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
+  #else
+    #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
+  #endif
+
+  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+    MEM_MAIN_FLOW_CONTROL_PTR_Dr
+    MEM_MAIN_FLOW_CONTROL_PTR_DA
+    MEM_MAIN_FLOW_CONTROL_PTR_RB
+    MEM_MAIN_FLOW_CONTROL_PTR_PH
+    MEM_MAIN_FLOW_CONTROL_PTR_Hy
+    MEM_MAIN_FLOW_CONTROL_PTR_OR
+    MEM_MAIN_FLOW_CONTROL_PTR_C32
+    MEM_MAIN_FLOW_CONTROL_PTR_Ni
+    NULL
+  };
+
+  #if (OPTION_ONLINE_SPARE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMOnlineSpare;
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMOnlineSpare
+    extern OPTION_MEM_FEATURE_NB MemFOnlineSpare;
+    #define MEM_FEATURE_ONLINE_SPARE  MemFOnlineSpare
+  #else
+    #define MEM_MAIN_FEATURE_ONLINE_SPARE  MemMDefRet
+    #define MEM_FEATURE_ONLINE_SPARE  MemFDefRet
+  #endif
+
+  #if (OPTION_MEM_RESTORE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMContextSave;
+    extern OPTION_MEM_FEATURE_MAIN MemMContextRestore;
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMContextSave
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMContextRestore
+  #else
+    #define MEM_MAIN_FEATURE_MEM_SAVE     MemMDefRet
+    #define MEM_MAIN_FEATURE_MEM_RESTORE  MemMDefRetFalse
+  #endif
+
+  #if (OPTION_BANK_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveBanks;
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFInterleaveBanks
+    extern OPTION_MEM_FEATURE_NB MemFUndoInterleaveBanks;
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFUndoInterleaveBanks
+  #else
+    #define MEM_FEATURE_BANK_INTERLEAVE  MemFDefRet
+    #define MEM_FEATURE_UNDO_BANK_INTERLEAVE MemFDefRet
+  #endif
+
+  #if (OPTION_NODE_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMInterleaveNodes;
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMInterleaveNodes
+    extern OPTION_MEM_FEATURE_NB MemFCheckInterleaveNodes;
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveNodes;
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFCheckInterleaveNodes
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFInterleaveNodes
+  #else
+    #define MEM_FEATURE_NODE_INTERLEAVE_CHECK  MemFDefRet
+    #define MEM_FEATURE_NODE_INTERLEAVE  MemFDefRet
+    #define MEM_MAIN_FEATURE_NODE_INTERLEAVE  MemMDefRet
+  #endif
+
+  #if (OPTION_DCT_INTERLEAVE == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFInterleaveChannels;
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFInterleaveChannels
+  #else
+    #define MEM_FEATURE_CHANNEL_INTERLEAVE  MemFDefRet
+  #endif
+
+  #if (OPTION_ECC == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMEcc;
+    #define MEM_MAIN_FEATURE_ECC  MemMEcc
+    extern OPTION_MEM_FEATURE_NB MemFCheckECC;
+    extern OPTION_MEM_FEATURE_NB MemFInitECC;
+    #define MEM_FEATURE_CK_ECC   MemFCheckECC
+    #define MEM_FEATURE_ECC   MemFInitECC
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #else
+    #define MEM_MAIN_FEATURE_ECC  MemMDefRet
+    #define MEM_FEATURE_CK_ECC   MemFDefRet
+    #define MEM_FEATURE_ECC   MemFDefRet
+    #define MEM_FEATURE_ECCX8  MemMDefRet
+  #endif
+
+    #define MEM_FEATURE_EMP   MemFDefRet
+
+  extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
+  #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
+
+  #if (OPTION_DMI == TRUE)
+    #if (OPTION_DDR3 == TRUE)
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport3;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport3
+    #else
+      extern OPTION_MEM_FEATURE_MAIN MemFDMISupport2;
+      #define MEM_MAIN_FEATURE_MEM_DMI MemFDMISupport2
+    #endif
+  #else
+    #define MEM_MAIN_FEATURE_MEM_DMI MemMDefRet
+  #endif
+
+  #if (OPTION_DDR3 == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemFOnDimmThermal;
+    extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3;
+    extern OPTION_MEM_FEATURE_NB MemFLvDdr3;
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFOnDimmThermal
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3
+    #define MEM_FEATURE_LVDDR3 MemFLvDdr3
+  #else
+    #define MEM_FEATURE_ONDIMMTHERMAL MemFDefRet
+    #define MEM_MAIN_FEATURE_LVDDR3 MemMDefRet
+    #define MEM_FEATURE_LVDDR3 MemFDefRet
+  #endif
+
+  extern OPTION_MEM_FEATURE_NB MemFInterleaveRegion;
+  #define MEM_FEATURE_REGION_INTERLEAVE    MemFInterleaveRegion
+
+  extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
+  #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
+
+  #if (OPTION_PARALLEL_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
+    #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
+  #else
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+  #endif
+
+  #if (OPTION_DIMM_EXCLUDE == TRUE)
+    extern OPTION_MEM_FEATURE_MAIN MemMRASExcludeDIMM;
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMRASExcludeDIMM
+    extern OPTION_MEM_FEATURE_NB MemFRASExcludeDIMM;
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFRASExcludeDIMM
+  #else
+    #define MEM_FEATURE_DIMM_EXCLUDE  MemFDefRet
+    #define MEM_MAIN_FEATURE_DIMM_EXCLUDE  MemMDefRet
+  #endif
+
+  /*----------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK CONSTRUCTOR FUNCTION ASSIGNMENTS
+   *
+   *----------------------------------------------------------------------------------
+  */
+  #if OPTION_DDR2 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock2;
+    #define MEM_TECH_CONSTRUCTOR_DDR2 MemConstructTechBlock2,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR2
+  #endif
+  #if OPTION_DDR3 == TRUE
+    extern MEM_TECH_CONSTRUCTOR MemConstructTechBlock3;
+    #define MEM_TECH_CONSTRUCTOR_DDR3 MemConstructTechBlock3,
+    #if (OPTION_HW_DRAM_INIT == TRUE)
+      extern MEM_TECH_FEAT MemTDramInitHw;
+      #define MEM_TECH_FEATURE_HW_DRAMINIT  MemTDramInitHw
+    #else
+      #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
+    #endif
+    #if (OPTION_SW_DRAM_INIT == TRUE)
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
+    #else
+      #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
+    #endif
+  #else
+    #define MEM_TECH_CONSTRUCTOR_DDR3
+  #endif
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * FEATURE BLOCKS
+   *
+   *  This section instantiates a feature block structure for each memory controller installed
+   *  by the platform solution install file.
+   *---------------------------------------------------------------------------------------------------
+   */
+
+  #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+    extern OPTION_MEM_FEATURE_NB MemNInitDqsTrainRcvrEnHwNb;
+  #endif
+  extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
+
+  /*---------------------------------------------------------------------------------------------------
+   * DEERHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockDr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MemFDefRet,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_DR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDR;
+    extern MEM_INITIALIZER MemNInitDefaultsDR;
+
+
+    #define MEM_NB_SUPPORT_DR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDR, MemNInitDefaultsDR, &MemFeatBlockDr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DR, MEM_IDENDIMM_DR },
+  #endif // OPTION_MEMCTRL_DR
+
+  /*---------------------------------------------------------------------------------------------------
+   * DASHOUND FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_DA == TRUE || OPTION_MEMCTLR_Ni == TRUE || OPTION_MEMCTLR_RB == TRUE || OPTION_MEMCTLR_PH == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    #if (OPTION_MEMCTLR_Ni == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockNi = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_Ni
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockNi;
+      extern MEM_INITIALIZER MemNInitDefaultsNi;
+
+      #define MEM_NB_SUPPORT_Ni { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockNi, MemNInitDefaultsNi, &MemFeatBlockNi, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_Ni, MEM_IDENDIMM_DA },
+    #endif
+
+    #if (OPTION_MEMCTLR_PH == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockPh = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_PH
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockPh;
+      extern MEM_INITIALIZER MemNInitDefaultsPh;
+
+      #define MEM_NB_SUPPORT_PH { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockPh, MemNInitDefaultsPh, &MemFeatBlockPh, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_PH, MEM_IDENDIMM_PH },
+    #endif
+
+    #if (OPTION_MEMCTLR_RB == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockRb = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_RB
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockRb;
+      extern MEM_INITIALIZER MemNInitDefaultsRb;
+
+      #define MEM_NB_SUPPORT_RB { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockRb, MemNInitDefaultsRb, &MemFeatBlockRb, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_RB, MEM_IDENDIMM_RB },
+    #endif
+
+    #if (OPTION_MEMCTLR_DA == TRUE)
+      MEM_FEAT_BLOCK_NB  MemFeatBlockDA = {
+        MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+        MemFDefRet,
+        MEM_FEATURE_BANK_INTERLEAVE,
+        MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+        MemFDefRet,
+        MemFDefRet,
+        MEM_FEATURE_CHANNEL_INTERLEAVE,
+        MEM_FEATURE_REGION_INTERLEAVE,
+        MEM_FEATURE_CK_ECC,
+        MEM_FEATURE_ECC,
+        MEM_FEATURE_TRAINING,
+        MEM_FEATURE_LVDDR3,
+        MemFDefRet,
+        MEM_TECH_FEATURE_DRAMINIT,
+        MEM_FEATURE_DIMM_EXCLUDE,
+        MemFDefRet,
+        MEM_TECH_FEATURE_CPG,
+        MEM_TECH_FEATURE_HWRXEN
+      };
+
+      #undef MEM_NB_SUPPORT_DA
+      extern MEM_NB_CONSTRUCTOR MemConstructNBBlockDA;
+      extern MEM_INITIALIZER MemNInitDefaultsDA;
+
+      #define MEM_NB_SUPPORT_DA { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockDA, MemNInitDefaultsDA, &MemFeatBlockDA, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_DA, MEM_IDENDIMM_DA },
+    #endif
+  #endif // OPTION_MEMCTRL_DA
+
+  /*---------------------------------------------------------------------------------------------------
+   * HYDRA FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_HY == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #undef MEM_TECH_FEATURE_CPG
+    #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockHy = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_HY
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockHY;
+    extern MEM_INITIALIZER MemNInitDefaultsHY;
+    #define MEM_NB_SUPPORT_HY { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockHY, MemNInitDefaultsHY, &MemFeatBlockHy, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_HY, MEM_IDENDIMM_HY },
+  #endif // OPTION_MEMCTRL_HY
+  /*---------------------------------------------------------------------------------------------------
+   * OROCHI FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_OR == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_MAIN_FEATURE_LVDDR3
+      extern OPTION_MEM_FEATURE_MAIN MemMLvDdr3PerformanceEnhPre;
+      #define MEM_MAIN_FEATURE_LVDDR3 MemMLvDdr3PerformanceEnhPre
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+    #if (OPTION_G34_SOCKET_SUPPORT || OPTION_C32_SOCKET_SUPPORT)
+      #undef MEM_FEATURE_REGION_INTERLEAVE
+      #define MEM_FEATURE_REGION_INTERLEAVE MemFDefRet
+    #endif
+
+    #if (OPTION_EARLY_SAMPLES == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitEarlySampleSupportOr;
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemNInitEarlySampleSupportOr
+    #else
+      #define MEM_EARLY_SAMPLE_SUPPORT    MemFDefRet
+    #endif
+
+    #if (OPTION_CONTINOUS_PATTERN_GENERATION == TRUE)
+      extern OPTION_MEM_FEATURE_NB MemNInitCPGUnb;
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemNInitCPGUnb
+    #else
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+    #endif
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockOr = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MEM_FEATURE_REGION_INTERLEAVE,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MEM_EARLY_SAMPLE_SUPPORT,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_OR
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockOR;
+    extern MEM_INITIALIZER MemNInitDefaultsOR;
+    #define MEM_NB_SUPPORT_OR { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockOR, MemNInitDefaultsOR, &MemFeatBlockOr, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_OR, MEM_IDENDIMM_OR },
+  #endif // OPTION_MEMCTRL_OR
+
+  /*---------------------------------------------------------------------------------------------------
+   * C32 FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  #if (OPTION_MEMCTLR_C32 == TRUE)
+    #if OPTION_DDR2
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_HW_DRAMINIT
+    #endif
+    #if OPTION_DDR3
+      #undef MEM_TECH_FEATURE_DRAMINIT
+      #define MEM_TECH_FEATURE_DRAMINIT MEM_TECH_FEATURE_SW_DRAMINIT
+    #endif
+
+      #undef MEM_TECH_FEATURE_CPG
+      #define MEM_TECH_FEATURE_CPG    MemFDefRet
+
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+      #undef MEM_TECH_FEATURE_HWRXEN
+      #define MEM_TECH_FEATURE_HWRXEN    MemNInitDqsTrainRcvrEnHwNb
+    #else
+      extern OPTION_MEM_FEATURE_NB MemNDisableDqsTrainRcvrEnHwNb;
+      #define MEM_TECH_FEATURE_HWRXEN    MemNDisableDqsTrainRcvrEnHwNb
+    #endif
+
+    #undef MEM_MAIN_FEATURE_TRAINING
+    #undef MEM_FEATURE_TRAINING
+    #if (OPTION_MEMCTLR_OR == TRUE)
+    #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #else
+      #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
+    #endif
+    #define MEM_FEATURE_TRAINING  MemFStandardTraining
+
+    MEM_FEAT_BLOCK_NB  MemFeatBlockC32 = {
+      MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
+      MEM_FEATURE_ONLINE_SPARE,
+      MEM_FEATURE_BANK_INTERLEAVE,
+      MEM_FEATURE_UNDO_BANK_INTERLEAVE,
+      MEM_FEATURE_NODE_INTERLEAVE_CHECK,
+      MEM_FEATURE_NODE_INTERLEAVE,
+      MEM_FEATURE_CHANNEL_INTERLEAVE,
+      MemFDefRet,
+      MEM_FEATURE_CK_ECC,
+      MEM_FEATURE_ECC,
+      MEM_FEATURE_TRAINING,
+      MEM_FEATURE_LVDDR3,
+      MEM_FEATURE_ONDIMMTHERMAL,
+      MEM_TECH_FEATURE_DRAMINIT,
+      MEM_FEATURE_DIMM_EXCLUDE,
+      MemFDefRet,
+      MEM_TECH_FEATURE_CPG,
+      MEM_TECH_FEATURE_HWRXEN
+    };
+
+    #undef MEM_NB_SUPPORT_C32
+    extern MEM_NB_CONSTRUCTOR MemConstructNBBlockC32;
+    extern MEM_INITIALIZER MemNInitDefaultsC32;
+    #define MEM_NB_SUPPORT_C32 { MEM_NB_SUPPORT_STRUCT_VERSION, MemConstructNBBlockC32, MemNInitDefaultsC32, &MemFeatBlockC32, MEM_FEATURE_S3_RESUME_CONSTRUCTOR_C32, MEM_IDENDIMM_C32 },
+  #endif // OPTION_MEMCTRL_C32
+
+  /*---------------------------------------------------------------------------------------------------
+   * MAIN FEATURE BLOCK
+   *---------------------------------------------------------------------------------------------------
+   */
+  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+    MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
+    MEM_MAIN_FEATURE_TRAINING,
+    MEM_MAIN_FEATURE_DIMM_EXCLUDE,
+    MEM_MAIN_FEATURE_ONLINE_SPARE,
+    MEM_MAIN_FEATURE_NODE_INTERLEAVE,
+    MEM_MAIN_FEATURE_ECC,
+    MEM_MAIN_FEATURE_MEM_CLEAR,
+    MEM_MAIN_FEATURE_MEM_DMI,
+    MEM_MAIN_FEATURE_LVDDR3,
+    MEM_MAIN_FEATURE_UMAALLOC,
+    MEM_MAIN_FEATURE_MEM_SAVE,
+    MEM_MAIN_FEATURE_MEM_RESTORE
+  };
+
+
+  /*---------------------------------------------------------------------------------------------------
+   * Technology Training SPECIFIC CONFIGURATION
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  #define MEM_TECH_TRAINING_FEAT_NULL_TERNMIATOR 0
+  #if OPTION_MEMCTLR_DR
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
+    #endif
+    #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+    #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Dr = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR2Dr },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+    #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+    #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+    #endif
+    #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
+    #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+    #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+    #endif
+    #endif
+    #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+      #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+      #endif
+    #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+    #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+    #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+    #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+    #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDr;
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Dr = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+    };
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDr, &memTechTrainingFeatSequenceDDR3Dr },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+
+  #if (OPTION_MEMCTLR_DA || OPTION_MEMCTLR_Ni || OPTION_MEMCTLR_PH || OPTION_MEMCTLR_RB)
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2  MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2DA = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2PH = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Rb = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Ni = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #if (OPTION_MEMCTLR_DA)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR2DA },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_PH)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR2PH },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_RB)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR2ServerNb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR2Rb },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+
+      #if (OPTION_MEMCTLR_Ni)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR2Ni },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3DA = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ph = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Rb = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Ni = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #if (OPTION_MEMCTLR_DA)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceDA;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceDA, &memTechTrainingFeatSequenceDDR3DA },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_PH)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequencePh;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequencePh, &memTechTrainingFeatSequenceDDR3Ph },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_RB)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceRb;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, memNSequenceDDR3Nb, memNEnableTrainSequenceRb, &memTechTrainingFeatSequenceDDR3Rb },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+      #if (OPTION_MEMCTLR_Ni)
+        extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceNi;
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceNi, &memTechTrainingFeatSequenceDDR3Ni },
+      #else
+        #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #endif
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #if OPTION_MEMCTLR_HY
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceHy;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2Hy = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR2Hy },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3Hy = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceHy, &memTechTrainingFeatSequenceDDR3Hy },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #if OPTION_MEMCTLR_C32
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceC32;
+    #if OPTION_DDR2
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2    MemTDqsTrainRcvrEnHwPass1
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2    MemTDqsTrainRcvrEnHwPass2
+        #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2    MemTTrainDQSEdgeDetect
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+        #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR2    MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR2C32 = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR2,
+        TECH_TRAIN_SW_WL_DDR2,
+        TECH_TRAIN_HW_WL_P1_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_HW_WL_P2_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2,
+        TECH_TRAIN_EXIT_HW_TRN_DDR2,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2,
+        TECH_TRAIN_MAX_RD_LAT_DDR2,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR2,
+        TECH_TRAIN_DQS____DDR2
+      };
+      extern OPTION_MEM_FEATURE_NB MemNDQSTiming2Nb;
+      #define NB_TRAIN_FLOW_DDR2    MemNDQSTiming2Nb
+      extern OPTION_MEM_FEATURE_NB memNSequenceDDR2ServerNb;
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR2ServerNb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR2C32 },
+    #else
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+      #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTFeatDef
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTTrainOptRcvrEnSwPass1
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3C32 = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceC32, &memTechTrainingFeatSequenceDDR3C32 },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32 { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+
+  #if OPTION_MEMCTLR_OR
+    extern OPTION_MEM_FEATURE_NB memNEnableTrainSequenceOr;
+    #define TECH_TRAIN_ENTER_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_EXIT_HW_TRN_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_WL_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_SW_WL_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR2 MemTFeatDef
+    #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR2 MemTFeatDef
+    #define TECH_TRAIN_MAX_RD_LAT_DDR2 MemTFeatDef
+    #define TECH_TRAIN_DQS____DDR2 MemTFeatDef
+    #define NB_TRAIN_FLOW_DDR2    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #if OPTION_DDR3
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3   MemTPreparePhyAssistedTraining
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3    MemTExitPhyAssistedTraining
+      #if (OPTION_HW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_HW_WL_P1_DDR3   MemTWriteLevelizationHw3Pass1
+        #define TECH_TRAIN_HW_WL_P2_DDR3   MemTWriteLevelizationHw3Pass2
+      #else
+        #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_SW_WRITE_LEV_TRAINING == TRUE)
+        #define TECH_TRAIN_SW_WL_DDR3    MemTFeatDef
+      #else
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_HW_DQS_REC_EN_TRAINING == TRUE)
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3    MemTDqsTrainRcvrEnHwPass1
+        #ifdef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+          #undef TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3
+        #endif
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3    MemTDqsTrainRcvrEnHwPass2
+        #if (OPTION_HW_DQS_REC_EN_SEED_TRAINING == TRUE)
+          #undef TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTRdPosWithRxEnDlySeeds3
+        #else
+          #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+          #else
+            #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+          #endif
+        #endif
+      #else
+        #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+        #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+        #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE  || OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3    MemTTrainDQSEdgeDetect
+        #else
+          #define TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3 MemTFeatDef
+        #endif
+      #endif
+      #if (OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3
+      #if (OPTION_OPT_SW_DQS_REC_EN_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3    MemTFeatDef
+      #else
+        #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #undef TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3
+      #if (OPTION_OPT_SW_RD_WR_POS_TRAINING == TRUE)
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3    MemTTrainDQSEdgeDetectSw
+      #else
+        #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #endif
+      #if (OPTION_MAX_RD_LAT_TRAINING == TRUE)
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3    MemTTrainMaxLatency
+      #else
+        #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #endif
+      #define TECH_TRAIN_DQS____DDR3 MemTFeatDef
+      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3OR = {
+        MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
+        TECH_TRAIN_ENTER_HW_TRN_DDR3,
+        TECH_TRAIN_SW_WL_DDR3,
+        TECH_TRAIN_HW_WL_P1_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_HW_WL_P2_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3,
+        TECH_TRAIN_EXIT_HW_TRN_DDR3,
+        TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3,
+        TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
+        TECH_TRAIN_MAX_RD_LAT_DDR3,
+        TECH_TRAIN_HW_DQS_REC_EN_SEED_DDR3,
+        TECH_TRAIN_DQS____DDR3
+      };
+      #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceOr, &memTechTrainingFeatSequenceDDR3OR },
+    #else
+      #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
+      #define TECH_TRAIN_ENTER_HW_TRN_DDR3 MemTFeatDef
+      #undef TECH_TRAIN_EXIT_HW_TRN_DDR3
+      #define TECH_TRAIN_EXIT_HW_TRN_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_WL_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_SW_WL_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_HW_DQS_REC_EN_P2_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_DQS_REC_EN_P1_DDR3 MemTFeatDef
+      #define TECH_TRAIN_NON_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3 MemTFeatDef
+      #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef
+      #define NB_TRAIN_FLOW_DDR3    (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue
+      #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #endif
+  #else
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+    #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR  { MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefTrue, (BOOLEAN (*) (MEM_NB_BLOCK*)) memDefFalse, 0 },
+  #endif
+
+  #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_DA
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_HY
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_C32
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_Ni
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_OR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_PH
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_RB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+
+  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_C32
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_Ni
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_OR
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_PH
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_RB
+    MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * NB TRAINING FLOW CONTROL
+   *
+   *
+   *---------------------------------------------------------------------------------------------------
+   */
+  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+    NB_TRAIN_FLOW_DDR2,
+    NB_TRAIN_FLOW_DDR3,
+  };
+  /*---------------------------------------------------------------------------------------------------
+   * TECHNOLOGY BLOCK
+