[coreboot] Patch set updated for coreboot: 0303640 SIO: Winbond w83627dhg update

Kerry Sheh (shekairui@gmail.com) gerrit at coreboot.org
Tue Jan 31 12:47:19 CET 2012


Kerry Sheh (shekairui at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565

-gerrit

commit 03036400344cb59079c47ed0d9949e5b89e6e904
Author: Kerry Sheh <shekairui at gmail.com>
Date:   Tue Jan 31 20:42:27 2012 +0800

    SIO: Winbond w83627dhg update
    
    1. Stop include c file.
    2. W83627dhg Pin 89, Pin 90 are multi function pins,
       add support to select them to I2C function.
    
    Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
    Signed-off-by: Kerry Sheh <kerry.she at amd.com>
    Signed-off-by: Kerry Sheh <shekairui at gmail.com>
---
 src/mainboard/asrock/939a785gmh/romstage.c   |    2 +-
 src/mainboard/kontron/kt690/romstage.c       |    2 +-
 src/superio/winbond/w83627dhg/Makefile.inc   |    2 +
 src/superio/winbond/w83627dhg/early_serial.c |   29 +++++++++++++++++++++++--
 src/superio/winbond/w83627dhg/superio.c      |    4 +-
 src/superio/winbond/w83627dhg/w83627dhg.h    |    6 +++++
 6 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 3183c1c..4a1b1c3 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -39,7 +39,7 @@
 #include <spd.h>
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627dhg/early_serial.c"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index f2525e3..621c27f 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -40,7 +40,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "superio/winbond/w83627dhg/early_serial.c"
+#include "superio/winbond/w83627dhg/w83627dhg.h"
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc
index 0b0bb8b..09df47e 100644
--- a/src/superio/winbond/w83627dhg/Makefile.inc
+++ b/src/superio/winbond/w83627dhg/Makefile.inc
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+## Copyright (C) 2012 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -18,5 +19,6 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c
 ramstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += superio.c
 
diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c
index f530dc6..e0be8de 100644
--- a/src/superio/winbond/w83627dhg/early_serial.c
+++ b/src/superio/winbond/w83627dhg/early_serial.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,24 +19,26 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <device/pnp_def.h>
 #include <stdint.h>
 #include "w83627dhg.h"
 
-static void pnp_enter_ext_func_mode(device_t dev)
+void pnp_enter_ext_func_mode(device_t dev)
 {
 	u16 port = dev >> 8;
 	outb(0x87, port);
 	outb(0x87, port);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
+void pnp_exit_ext_func_mode(device_t dev)
 {
 	u16 port = dev >> 8;
 	outb(0xaa, port);
 }
 
-static void w83627dhg_enable_serial(device_t dev, u16 iobase)
+void w83627dhg_enable_serial(device_t dev, u16 iobase)
 {
 	pnp_enter_ext_func_mode(dev);
 	pnp_set_logical_device(dev);
@@ -44,3 +47,23 @@ static void w83627dhg_enable_serial(device_t dev, u16 iobase)
 	pnp_set_enable(dev, 1);
 	pnp_exit_ext_func_mode(dev);
 }
+
+/**
+ * Select Pin 89, Pin 90 function as I2C interface SDA, SCL.
+ *  {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or
+ *  {RSTOUT3#, RSTOUT2#} or {SDA, SCL}
+ */
+void w83627dhg_enable_i2c(device_t dev)
+{
+	u8 val;
+
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+
+	val = pnp_read_config(dev, 0x2A);
+	val |= 1 << 1;
+	pnp_write_config(dev, 0x2A, val);
+
+	pnp_exit_ext_func_mode(dev);
+}
+
diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c
index 1771c26..a936ce1 100644
--- a/src/superio/winbond/w83627dhg/superio.c
+++ b/src/superio/winbond/w83627dhg/superio.c
@@ -26,13 +26,13 @@
 #include "chip.h"
 #include "w83627dhg.h"
 
-static void pnp_enter_ext_func_mode(device_t dev)
+void pnp_enter_ext_func_mode(device_t dev)
 {
 	outb(0x87, dev->path.pnp.port);
 	outb(0x87, dev->path.pnp.port);
 }
 
-static void pnp_exit_ext_func_mode(device_t dev)
+void pnp_exit_ext_func_mode(device_t dev)
 {
 	outb(0xaa, dev->path.pnp.port);
 }
diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h
index 74761e9..158e60b 100644
--- a/src/superio/winbond/w83627dhg/w83627dhg.h
+++ b/src/superio/winbond/w83627dhg/w83627dhg.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -51,4 +52,9 @@
 
 /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */
 
+void pnp_enter_ext_func_mode(device_t dev);
+void pnp_exit_ext_func_mode(device_t dev);
+void w83627dhg_enable_serial(device_t dev, u16 iobase);
+void w83627dhg_enable_i2c(device_t dev);
+
 #endif




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