[coreboot] Patch set updated for coreboot: 9113e9e AMD northbridges: drop unused sysconf fields

Kyösti Mälkki (kyosti.malkki@gmail.com) gerrit at coreboot.org
Tue Jul 17 00:31:28 CEST 2012


Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1201

-gerrit

commit 9113e9ef0ea65ec267405e86f5b92e59fa7d64b9
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Jul 10 08:58:00 2012 +0300

    AMD northbridges: drop unused sysconf fields
    
    Fields were not referenced after being set.
    
    Change-Id: I1edd563fa46c1a1fea6e971d9858bdc1206f74d8
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/include/cpu/amd/amdfam10_sysconf.h     |    2 --
 src/include/cpu/amd/amdk8_sysconf.h        |    5 -----
 src/northbridge/amd/amdfam10/northbridge.c |   16 +---------------
 src/northbridge/amd/amdk8/northbridge.c    |   18 ------------------
 4 files changed, 1 insertions(+), 40 deletions(-)

diff --git a/src/include/cpu/amd/amdfam10_sysconf.h b/src/include/cpu/amd/amdfam10_sysconf.h
index fb973a25..1b2ea2b 100644
--- a/src/include/cpu/amd/amdfam10_sysconf.h
+++ b/src/include/cpu/amd/amdfam10_sysconf.h
@@ -61,8 +61,6 @@ struct amdfam10_sysconf_t {
 
 	unsigned bsp_apicid;
 	int enabled_apic_ext_id;
-	unsigned lift_bsp_apicid;
-	int apicid_offset;
 
 	void *mb; // pointer for mb releated struct
 
diff --git a/src/include/cpu/amd/amdk8_sysconf.h b/src/include/cpu/amd/amdk8_sysconf.h
index a10ae89..594a87c 100644
--- a/src/include/cpu/amd/amdk8_sysconf.h
+++ b/src/include/cpu/amd/amdk8_sysconf.h
@@ -15,12 +15,7 @@ struct amdk8_sysconf_t {
 
 	unsigned hcdn_reg[4]; // it will be used by get_sblk_pci1234
 
-	int enabled_apic_ext_id;
-	unsigned lift_bsp_apicid;
-	int apicid_offset;
-
 	void *mb; // pointer for mb releated struct
-
 };
 
 extern struct amdk8_sysconf_t sysconf;
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 320e1dc..2372eed 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -1203,28 +1203,14 @@ static void sysconf_init(device_t dev) // first node
 	sysconf.nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3);
 #endif
 
-	sysconf.enabled_apic_ext_id = 0;
-	sysconf.lift_bsp_apicid = 0;
 
 	/* Find the bootstrap processors apicid */
 	sysconf.bsp_apicid = lapicid();
-	sysconf.apicid_offset = sysconf.bsp_apicid;
 
+	sysconf.enabled_apic_ext_id = 0;
 #if CONFIG_ENABLE_APIC_EXT_ID
 	if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
-	{
 		sysconf.enabled_apic_ext_id = 1;
-	}
-	#if (CONFIG_APIC_ID_OFFSET>0)
-	if(sysconf.enabled_apic_ext_id) {
-		if(sysconf.bsp_apicid == 0) {
-			/* bsp apic id is not changed */
-			sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
-		} else {
-			sysconf.lift_bsp_apicid = 1;
-		}
-	}
-	#endif
 #endif
 }
 
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index aa87927..0559690 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -1209,12 +1209,8 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 	int e0_later_single_core;
 	int disable_siblings;
 
-	sysconf.enabled_apic_ext_id = 0;
-	sysconf.lift_bsp_apicid = 0;
-
 	/* Find the bootstrap processors apicid */
 	bsp_apicid = lapicid();
-	sysconf.apicid_offset = bsp_apicid;
 
 	disable_siblings = !CONFIG_LOGICAL_CPUS;
 #if CONFIG_LOGICAL_CPUS
@@ -1233,20 +1229,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
 
 	sysconf.nodes = ((pci_read_config32(dev_mc, 0x60)>>4) & 7) + 1;
 
-
-	if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
-	{
-		sysconf.enabled_apic_ext_id = 1;
-		if(bsp_apicid == 0) {
-			/* bsp apic id is not changed */
-			sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET;
-		} else
-		{
-			sysconf.lift_bsp_apicid = 1;
-		}
-
-	}
-
 	/* Find which cpus are present */
 	cpu_bus = dev->link_list;
 	for(i = 0; i < sysconf.nodes; i++) {




More information about the coreboot mailing list