> > First problem: spd eprom say that memory ddr1600 capable, but it is not
> > so, is there are right way to limit memory frequency at ddr1333?
> Overwrite the MEM_MAX_LOAD_FREQ macro.
This works thanks, but looks like this are not a main problem, Memtest86
+ still find a many errors.
-------------- next part --------------
coreboot-4.0-2568-g8bacc40-dirty Sun Jul 22 13:38:15 MSK 2012 starting...
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1041, current patch id = 0x00000000
microcode: rev id (1043) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
POST: 0x33
cpuSetAMDMSR done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600e681
F3x84: 80e641e6
F3xD4: c8810f24
F3xD8: 03001816
F3xDC: 00006322
POST: 0x36
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
POST: 0x37
started ap apicid: PPPOOOSSSTTT::: 000xxx333000
cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000123 NNNOOODDDEEEIIIDDD === 000000 CCCOOOR-
* AmmmiiPicc cr0rro1oocccooodddeee::: eeeqqquuuiiivvvaaallleeennnttt rrreeevvv iiiddd === 000xxx111000444111,,,0
ddmimtiiaccrrrctoorccoeocdodo
. ee::e: rrreevev v ii ddid ((1(1010404334))3) dddooeoeses snn nooott t m maamttatccchh h t ththihissi spp paaattctch
mmm*i iicAccPrrrooo cc0co2oodddeee::: NNNooottt uuupppdddaaattteeeddd!!! FFFiiixxx mmmiiicccrrrooocccooodddeee___uuu
MMcccpppauuruStSSeeeedtttAAA
e MDDDMMMSSSRRR * AP d0 do3doonnnee
iffdiiiinnriitttte__df_
3 vddivvdii_dda__apapp(((ssstattgaagege1e11))) apaaippicicicididd::: 0 1002
FFFI
IIDDDVVVIIIDDD ooonnn AAAPPP::: 000321
POST: 0x38
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb800_early_setup()
sb800_devices_por_init()
sb800_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A13
sb800_devices_por_init(): IDE Device, BDF:0-20-1
sb800_devices_por_init(): LPC Device, BDF:0-20-3
sb800_devices_por_init(): P2P Bridge, BDF:0-20-4
sb800_devices_por_init(): SATA Device, BDF:0-18-0
Begin FIDVID MSR 0xc0010071 0x30b800a3 0x40035840
POST: 0x39
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 2
readback = 2010601
common_fid(packed) = 10600
Wait for AP stage 1: ap_apicid = 3
readback = 3010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b800a3 0x38005840
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
...WARM RESET...
coreboot-4.0-2568-g8bacc40-dirty Sun Jul 22 13:38:15 MSK 2012 starting...
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cf360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1041, current patch id = 0x00000000
microcode: rev id (1043) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
POST: 0x33
cpuSetAMDMSR done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600e681
F3x84: 80e641e6
F3xD4: c8810f26
F3xD8: 03001816
F3xDC: 00006322
POST: 0x36
core0 started:
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
POST: 0x37
started ap apicid: PPPOOOSSSTTT::: 000xxx333000
cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === 000123 NNNOOODDDEEEIIIDDD === 000000 CCCOOOR-
* AmmmiiPic cc0rrroo1occcooodddeee::: eeeqqquuuiiivvvaaallleeennnttt rrreeevvv iiiddd === 000xxx111000444111,,,0
ddmtiimcciarcrrrtooccoeocdoo
eed::e: rr ereevv vi iidd d( ((11001404433))3 ) ddoodeoeess sn nnootto t mmmaatattcchhc h tthhthiiiss s pppaatattc.
mmm*ii icAccPrrrooo cc0c2ooodddeee::: NNNooottt uuupppdddaaattteeeddd!!! FFFiiixxx mmmiiicccrrrooocccooodddeee___uuu
AAcccapppuuruStSSeeeetttdA
MMMDDDMMMSSSRRR * AP d0dd3ooonnneee
iiiiiannniiirtttte___fffdi
dddvvviiiddd___ssstttaaagggeee222 aaapppiiiccciiiddd::: 000132
POST: 0x38
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb800_early_setup()
sb800_devices_por_init()
sb800_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A13
sb800_devices_por_init(): IDE Device, BDF:0-20-1
sb800_devices_por_init(): LPC Device, BDF:0-20-3
sb800_devices_por_init(): P2P Bridge, BDF:0-20-4
sb800_devices_por_init(): SATA Device, BDF:0-18-0
Begin FIDVID MSR 0xc0010071 0x30b800a3 0x38005840
POST: 0x39
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b800a3 0x3800280c
rs780_htinit cpu_ht_freq=0.
rs780_htinit: HT1 mode
POST: 0x3b
fill_mem_ctrl()
POST: 0x40
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=3
DIMMPresence: DIMMPresent=3
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=3
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=0
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=1
DIMMPresence: MAload[0]=8
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=1
DIMMPresence: MAload[1]=8
DIMMPresence: MAdimms[1]=1
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: a0092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 80
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 80
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 1
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 80
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = fffffe
StitchMemory: Status 1000
StitchMemory: ErrStatus 80
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 80
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: a0092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 10000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 80
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: ffffff BottomIO: c00000
Node: 00 base: 03 limit: 13fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:c00000
CPUMemTyping: Bottom32bIO:c00000
CPUMemTyping: Bottom40bIO:1400000
mctAutoInitMCT_D: DQSTiming_D
TrainRcvrEn: Status 1100
TrainRcvrEn: ErrStatus 80
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1100
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 80
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1100
InterleaveNodes_D: ErrStatus 80
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1100
InterleaveChannels_D: ErrStatus 80
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
ECCInit: Node 00
ECCInit: Status 1100
ECCInit: ErrStatus 80
ECCInit: ErrCode 0
ECCInit: Done
mctAutoInitMCT_D Done: Global Status: 10
raminit_amdmct end:
POST: 0x41
POST: 0x42
v_esp=000cbef8
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1245184 bytes), entry @ 0x200000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-4.0-2568-g8bacc40-dirty Sun Jul 22 13:38:15 MSK 2012 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Mainboard enable. dev=0x00226c50
setup_uma_memory, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000
setup_uma_memory, TOP MEM2: msr.lo = 0x40000000, msr.hi = 0x00000001
setup_uma_memory: uma size 0x10000000, memory start 0xb0000000
Dev3 is present. GFX Configuration is Two x8 slots
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=3
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
CPU: APIC: 02 enabled
CPU: APIC: 03 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
POST: 0x25
rs780_enable: dev=00227384, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
addr=e0000000,bus=0,devfn=40
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
Capability: type 0x08 @ 0xc4
flags: 0x0181
PCI: pci_scan_bus for bus 00
PCI: pci_scan_bus limits devfn 0 - devfn ffffffff
PCI: pci_scan_bus upper limit too big. Using 0xff.
POST: 0x24
rs780_enable: dev=00227384, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
NB_PCI_REG04 = 6.
NB_PCI_REG84 = 3000095.
NB_PCI_REG4C = 52042.
PCI: 00:00.0 [1022/9601] enabled
rs780_enable: dev=00227804, VID_DID=0x96021022
Bus-0, Dev-1, Fun-0.
GC is accessible from now on.
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0x44
Capability: type 0x0d @ 0xb0
PCI: 00:01.0 [1022/9602] enabled
rs780_enable: dev=00227b64, VID_DID=0x96031022
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00227384, dev=0x00227b64, port=0x2.
misc 28 = 1
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
rs780_gfx_init step2.
device = 2
PcieLinkTraining port=2:lc current state=4000102
PCI: Static device PCI: 00:02.0 not found, disabling it.
rs780_enable: dev=00227e34, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=1
rs780_gfx_init, nb_dev=0x00227384, dev=0x00227e34, port=0x3.
misc 28 = 1
rs780_gfx_init step5.9.12.1.
rs780_gfx_init step5.9.12.3.
rs780_gfx_init step5.9.12.9.
rs780_gfx_init step1.
rs780_gfx_init step2.
device = 3
PcieLinkTraining port=3:lc current state=ffffffff
PCI: Static device PCI: 00:03.0 not found, disabling it.
rs780_enable: dev=00227fe4, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x20, port=0x4
PcieLinkTraining port=4:lc current state=10203
PcieTrainPort port=0x4 result=0
PCI: Static device PCI: 00:04.0 not found, disabling it.
rs780_enable: dev=00228194, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228344, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228464, VID_DID=0xffffffff
Bus-0, Dev-4,5,6,7, Fun-0. enable=0
rs780_enable: dev=00228584, VID_DID=0x960a1022
Bus-0, Dev-8, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x40, port=0x8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:08.0 subordinate bus PCI Express
PCI: 00:08.0 [1022/960a] enabled
rs780_enable: dev=002286a4, VID_DID=0x96081022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x48, port=0x9
PcieLinkTraining port=9:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=48
PcieTrainPort reg=0x10000
PcieTrainPort port=0x9 result=1
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:09.0 subordinate bus PCI Express
PCI: 00:09.0 [1022/9608] enabled
rs780_enable: dev=002287c4, VID_DID=0x96091022
Bus-0, Dev-9, 10, Fun-0. enable=1
gpp_sb_init nb_dev=0x0, dev=0x50, port=0xa
PcieLinkTraining port=a:lc current state=a0b0f10
addr=e0000000,bus=0,devfn=50
PcieTrainPort reg=0x10000
PcieTrainPort port=0xa result=1
disable_pcie_bar3()
rs780 unused GPP ports bitmap=0x0fc, force disabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:0a.0 subordinate bus PCI Express
PCI: 00:0a.0 [1022/9609] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:11.0 [1002/4390] ops
PCI: 00:11.0 [1002/4390] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
unknown dev: PCI: 00:12.1 deviceid=ffff
PCI: Static device PCI: 00:12.1 not found, disabling it.
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
unknown dev: PCI: 00:13.1 deviceid=ffff
PCI: Static device PCI: 00:13.1 not found, disabling it.
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.0 [1002/4385] bus ops
PCI: 00:14.0 [1002/4385] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.1 [1002/439c] ops
PCI: 00:14.1 [1002/439c] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
set_sb800_gpp() 1
set_sb800_gpp() 2,
set_sb800_gpp() 3
imp_rb 1=6600380
imp_rb 5=6600380
lc_status=a0b0f10
PCI: 00:15.0 [1002/43a0] bus ops
PCI: 00:15.0 [1002/43a0] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:16.0 [1002/4397] ops
PCI: 00:16.0 [1002/4397] enabled
sb800_enable()
sb800_enable() 1
sb800_enable() 2
unknown dev: PCI: 00:16.1 deviceid=ffff
sb800_enable()
sb800_enable() 1
sb800_enable() 2
PCI: 00:16.2 [1002/4396] ops
PCI: 00:16.2 [1002/4396] enabled
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
POST: 0x25
do_pci_scan_bridge for PCI: 00:01.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:05.0 [1002/9715] enabled
PCI: 01:05.1 [1002/970f] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:08.0
PCI: pci_scan_bus for bus 02
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:09.0
PCI: pci_scan_bus for bus 03
POST: 0x24
PCI: 03:00.0 [1b6f/7023] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=003
POST: 0x55
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x70
Capability: type 0x10 @ 0xa0
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 3
do_pci_scan_bridge for PCI: 00:0a.0
PCI: pci_scan_bus for bus 04
POST: 0x24
PCI: 04:00.0 [1969/1083] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=004
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x58
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 4
scan_static_bus for PCI: 00:14.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
scan_static_bus for PCI: 00:14.0 done
scan_static_bus for PCI: 00:14.3
PNP: 002e.0 disabled
PNP: 002e.1 disabled
PNP: 002e.2 enabled
PNP: 002e.3 enabled
PNP: 002e.5 enabled
PNP: 002e.307 disabled
PNP: 002e.8 enabled
PNP: 002e.9 enabled
PNP: 002e.109 enabled
PNP: 002e.209 enabled
PNP: 002e.309 disabled
PNP: 002e.a disabled
PNP: 002e.b enabled
PNP: 002e.c disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 05
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=005
POST: 0x55
do_pci_scan_bridge returns max 5
do_pci_scan_bridge for PCI: 00:15.0
PCI: pci_scan_bus for bus 06
POST: 0x24
PCI: 06:00.0 [1106/3403] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=006
POST: 0x55
do_pci_scan_bridge returns max 6
PCI: pci_scan_bus returning with max=006
POST: 0x55
PCI: pci_scan_bus returning with max=006
POST: 0x55
PCI_DOMAIN: 0000 passpw: enabled
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC: 02 missing read_resources
APIC: 03 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:18.0 read_resources bus 0 link: 0
PCI: 00:00.0 register 1c(00000004), read-only ignoring it
PCI: 00:01.0 read_resources bus 1 link: 0
PCI: 00:01.0 read_resources bus 1 link: 0 done
PCI: 00:08.0 read_resources bus 2 link: 0
PCI: 00:08.0 read_resources bus 2 link: 0 done
PCI: 00:09.0 read_resources bus 3 link: 0
PCI: 00:09.0 read_resources bus 3 link: 0 done
PCI: 00:0a.0 read_resources bus 4 link: 0
PCI: 00:0a.0 read_resources bus 4 link: 0 done
PCI: 00:14.0 read_resources bus 1 link: 0
I2C: 01:50 missing read_resources
I2C: 01:51 missing read_resources
I2C: 01:52 missing read_resources
I2C: 01:53 missing read_resources
PCI: 00:14.0 read_resources bus 1 link: 0 done
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 5 link: 0
PCI: 00:14.4 read_resources bus 5 link: 0 done
PCI: 00:15.0 read_resources bus 6 link: 0
PCI: 00:15.0 read_resources bus 6 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 0 done
PCI: 00:18.0 read_resources bus 0 link: 1
PCI: 00:18.0 read_resources bus 0 link: 1 done
PCI: 00:18.0 read_resources bus 0 link: 2
PCI: 00:18.0 read_resources bus 0 link: 2 done
PCI: 00:18.0 read_resources bus 0 link: 3
PCI: 00:18.0 read_resources bus 0 link: 3 done
PCI: 00:18.0 read_resources bus 0 link: 4
PCI: 00:18.0 read_resources bus 0 link: 4 done
PCI: 00:18.0 read_resources bus 0 link: 5
PCI: 00:18.0 read_resources bus 0 link: 5 done
PCI: 00:18.0 read_resources bus 0 link: 6
PCI: 00:18.0 read_resources bus 0 link: 6 done
PCI: 00:18.0 read_resources bus 0 link: 7
PCI: 00:18.0 read_resources bus 0 link: 7 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 10d8
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 10b8
PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 10b0
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit 1ffffff flags 80102 index 1c
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81202 index 24
PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
PCI: 01:05.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
PCI: 01:05.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 18
PCI: 01:05.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 24
PCI: 01:05.1
PCI: 01:05.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:08.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:08.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:08.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:0a.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base 0 size 40000 align 18 gran 18 limit ffffffffffffffff flags 201 index 10
PCI: 04:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18
PCI: 00:11.0
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:12.1
PCI: 00:12.2
PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:13.1
PCI: 00:13.2
PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit fefffff flags 80000200 index 74
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
PCI: 00:14.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
PCI: 00:14.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
PCI: 00:14.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags c0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PCI: 00:14.4
PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:15.0 child on link 0 PCI: 06:00.0
PCI: 00:15.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
PCI: 06:00.0
PCI: 06:00.0 resource base 0 size 800 align 11 gran 11 limit ffffffffffffffff flags 201 index 10
PCI: 06:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 18
PCI: 00:16.0
PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
PCI: 00:18.4
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94
PCI: 00:18.4
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: 1ffffff
PCI: 01:05.0 14 * [0x0 - 0xff] io
PCI: 00:01.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:08.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:08.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 00:09.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 00:0a.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 04:00.0 18 * [0x0 - 0x7f] io
PCI: 00:0a.0 compute_resources_io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:15.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 06:00.0 18 * [0x0 - 0xff] io
PCI: 00:15.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:01.0 1c * [0x0 - 0xfff] io
PCI: 00:0a.0 1c * [0x1000 - 0x1fff] io
PCI: 00:15.0 1c * [0x2000 - 0x2fff] io
PCI: 00:11.0 20 * [0x3000 - 0x300f] io
PCI: 00:14.1 20 * [0x3010 - 0x301f] io
PCI: 00:11.0 10 * [0x3020 - 0x3027] io
PCI: 00:11.0 18 * [0x3028 - 0x302f] io
PCI: 00:14.1 10 * [0x3030 - 0x3037] io
PCI: 00:14.1 18 * [0x3038 - 0x303f] io
PCI: 00:11.0 14 * [0x3040 - 0x3043] io
PCI: 00:11.0 1c * [0x3044 - 0x3047] io
PCI: 00:14.1 14 * [0x3048 - 0x304b] io
PCI: 00:14.1 1c * [0x304c - 0x304f] io
PCI: 00:18.0 compute_resources_io: base: 3050 size: 4000 align: 12 gran: 12 limit: ffff done
PCI: 00:18.0 10d8 * [0x0 - 0x3fff] io
PCI_DOMAIN: 0000 compute_resources_io: base: 4000 size: 4000 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 01:05.0 10 * [0x0 - 0xfffffff] prefmem
PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:08.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:08.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:09.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:0a.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 00:15.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:01.0 24 * [0x0 - 0xfffffff] prefmem
PCI: 00:18.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff
PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:05.0 24 * [0x0 - 0xfffff] mem
PCI: 01:05.0 18 * [0x100000 - 0x10ffff] mem
PCI: 01:05.1 10 * [0x110000 - 0x113fff] mem
PCI: 00:01.0 compute_resources_mem: base: 114000 size: 200000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:08.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:08.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:09.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:00.0 10 * [0x0 - 0x7fff] mem
PCI: 00:09.0 compute_resources_mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:0a.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 04:00.0 10 * [0x0 - 0x3ffff] mem
PCI: 00:0a.0 compute_resources_mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:15.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 06:00.0 10 * [0x0 - 0x7ff] mem
PCI: 00:15.0 compute_resources_mem: base: 800 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem
PCI: 00:01.0 20 * [0x4000000 - 0x41fffff] mem
PCI: 00:09.0 20 * [0x4200000 - 0x42fffff] mem
PCI: 00:0a.0 20 * [0x4300000 - 0x43fffff] mem
PCI: 00:15.0 20 * [0x4400000 - 0x44fffff] mem
PCI: 00:14.2 10 * [0x4500000 - 0x4503fff] mem
PCI: 00:12.0 10 * [0x4504000 - 0x4504fff] mem
PCI: 00:13.0 10 * [0x4505000 - 0x4505fff] mem
PCI: 00:14.5 10 * [0x4506000 - 0x4506fff] mem
PCI: 00:16.0 10 * [0x4507000 - 0x4507fff] mem
PCI: 00:11.0 24 * [0x4508000 - 0x45083ff] mem
PCI: 00:12.2 10 * [0x4508400 - 0x45084ff] mem
PCI: 00:13.2 10 * [0x4508500 - 0x45085ff] mem
PCI: 00:16.2 10 * [0x4508600 - 0x45086ff] mem
PCI: 00:14.3 a0 * [0x4508700 - 0x4508700] mem
PCI: 00:18.0 compute_resources_mem: base: 4508701 size: 4600000 align: 26 gran: 20 limit: ffffffff done
PCI: 00:18.0 10b8 * [0x0 - 0xfffffff] prefmem
PCI: 00:18.0 10b0 * [0x10000000 - 0x145fffff] mem
PCI: 00:18.3 94 * [0x18000000 - 0x1bffffff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 1c000000 size: 1c000000 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 01:05.0
constrain_resources: PCI: 01:05.1
constrain_resources: PCI: 00:08.0
constrain_resources: PCI: 00:09.0
constrain_resources: PCI: 03:00.0
constrain_resources: PCI: 00:0a.0
constrain_resources: PCI: 04:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 01:50
constrain_resources: I2C: 01:51
constrain_resources: I2C: 01:52
constrain_resources: I2C: 01:53
constrain_resources: PCI: 00:14.1
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 002e.2
constrain_resources: PNP: 002e.3
constrain_resources: PNP: 002e.5
constrain_resources: PNP: 002e.8
constrain_resources: PNP: 002e.9
constrain_resources: PNP: 002e.109
constrain_resources: PNP: 002e.209
constrain_resources: PNP: 002e.b
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:15.0
constrain_resources: PCI: 06:00.0
constrain_resources: PCI: 00:16.0
constrain_resources: PCI: 00:16.2
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit dfffffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:4000 align:12 gran:0 limit:ffff
Assigned: PCI: 00:18.0 10d8 * [0x1000 - 0x4fff] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 5000 size: 4000 align: 12 gran: 0 done
PCI: 00:18.0 allocate_resources_io: base:1000 size:4000 align:12 gran:12 limit:ffff
Assigned: PCI: 00:01.0 1c * [0x1000 - 0x1fff] io
Assigned: PCI: 00:0a.0 1c * [0x2000 - 0x2fff] io
Assigned: PCI: 00:15.0 1c * [0x3000 - 0x3fff] io
Assigned: PCI: 00:11.0 20 * [0x4000 - 0x400f] io
Assigned: PCI: 00:14.1 20 * [0x4010 - 0x401f] io
Assigned: PCI: 00:11.0 10 * [0x4020 - 0x4027] io
Assigned: PCI: 00:11.0 18 * [0x4028 - 0x402f] io
Assigned: PCI: 00:14.1 10 * [0x4030 - 0x4037] io
Assigned: PCI: 00:14.1 18 * [0x4038 - 0x403f] io
Assigned: PCI: 00:11.0 14 * [0x4040 - 0x4043] io
Assigned: PCI: 00:11.0 1c * [0x4044 - 0x4047] io
Assigned: PCI: 00:14.1 14 * [0x4048 - 0x404b] io
Assigned: PCI: 00:14.1 1c * [0x404c - 0x404f] io
PCI: 00:18.0 allocate_resources_io: next_base: 4050 size: 4000 align: 12 gran: 12 done
PCI: 00:01.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:05.0 14 * [0x1000 - 0x10ff] io
PCI: 00:01.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:08.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:08.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:09.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:09.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:0a.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 04:00.0 18 * [0x2000 - 0x207f] io
PCI: 00:0a.0 allocate_resources_io: next_base: 2080 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:15.0 allocate_resources_io: base:3000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 06:00.0 18 * [0x3000 - 0x30ff] io
PCI: 00:15.0 allocate_resources_io: next_base: 3100 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:1c000000 align:28 gran:0 limit:dfffffff
Assigned: PCI: 00:18.0 10b8 * [0xc0000000 - 0xcfffffff] prefmem
Assigned: PCI: 00:18.0 10b0 * [0xd0000000 - 0xd45fffff] mem
Assigned: PCI: 00:18.3 94 * [0xd8000000 - 0xdbffffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: dc000000 size: 1c000000 align: 28 gran: 0 done
PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
Assigned: PCI: 00:01.0 24 * [0xc0000000 - 0xcfffffff] prefmem
PCI: 00:18.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
PCI: 00:01.0 allocate_resources_prefmem: base:c0000000 size:10000000 align:28 gran:20 limit:dfffffff
Assigned: PCI: 01:05.0 10 * [0xc0000000 - 0xcfffffff] prefmem
PCI: 00:01.0 allocate_resources_prefmem: next_base: d0000000 size: 10000000 align: 28 gran: 20 done
PCI: 00:08.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:08.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:09.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:0a.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.0 allocate_resources_prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:15.0 allocate_resources_prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:18.0 allocate_resources_mem: base:d0000000 size:4600000 align:26 gran:20 limit:dfffffff
Assigned: PCI: 00:18.3 94 * [0xd0000000 - 0xd3ffffff] mem
Assigned: PCI: 00:01.0 20 * [0xd4000000 - 0xd41fffff] mem
Assigned: PCI: 00:09.0 20 * [0xd4200000 - 0xd42fffff] mem
Assigned: PCI: 00:0a.0 20 * [0xd4300000 - 0xd43fffff] mem
Assigned: PCI: 00:15.0 20 * [0xd4400000 - 0xd44fffff] mem
Assigned: PCI: 00:14.2 10 * [0xd4500000 - 0xd4503fff] mem
Assigned: PCI: 00:12.0 10 * [0xd4504000 - 0xd4504fff] mem
Assigned: PCI: 00:13.0 10 * [0xd4505000 - 0xd4505fff] mem
Assigned: PCI: 00:14.5 10 * [0xd4506000 - 0xd4506fff] mem
Assigned: PCI: 00:16.0 10 * [0xd4507000 - 0xd4507fff] mem
Assigned: PCI: 00:11.0 24 * [0xd4508000 - 0xd45083ff] mem
Assigned: PCI: 00:12.2 10 * [0xd4508400 - 0xd45084ff] mem
Assigned: PCI: 00:13.2 10 * [0xd4508500 - 0xd45085ff] mem
Assigned: PCI: 00:16.2 10 * [0xd4508600 - 0xd45086ff] mem
Assigned: PCI: 00:14.3 a0 * [0xd4508700 - 0xd4508700] mem
PCI: 00:18.0 allocate_resources_mem: next_base: d4508701 size: 4600000 align: 26 gran: 20 done
PCI: 00:01.0 allocate_resources_mem: base:d4000000 size:200000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 01:05.0 24 * [0xd4000000 - 0xd40fffff] mem
Assigned: PCI: 01:05.0 18 * [0xd4100000 - 0xd410ffff] mem
Assigned: PCI: 01:05.1 10 * [0xd4110000 - 0xd4113fff] mem
PCI: 00:01.0 allocate_resources_mem: next_base: d4114000 size: 200000 align: 20 gran: 20 done
PCI: 00:08.0 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:08.0 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:09.0 allocate_resources_mem: base:d4200000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 03:00.0 10 * [0xd4200000 - 0xd4207fff] mem
PCI: 00:09.0 allocate_resources_mem: next_base: d4208000 size: 100000 align: 20 gran: 20 done
PCI: 00:0a.0 allocate_resources_mem: base:d4300000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 04:00.0 10 * [0xd4300000 - 0xd433ffff] mem
PCI: 00:0a.0 allocate_resources_mem: next_base: d4340000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
PCI: 00:14.4 allocate_resources_mem: next_base: dfffffff size: 0 align: 20 gran: 20 done
PCI: 00:15.0 allocate_resources_mem: base:d4400000 size:100000 align:20 gran:20 limit:dfffffff
Assigned: PCI: 06:00.0 10 * [0xd4400000 - 0xd44007ff] mem
PCI: 00:15.0 allocate_resources_mem: next_base: d4400800 size: 100000 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0
split: 128K table at =affe0000
0: mmio_basek=00300000, basek=00400000, limitk=00500000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 10d8 <- [0x0000001000 - 0x0000004fff] size 0x00004000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 10b8 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 10b0 <- [0x00d0000000 - 0x00d45fffff] size 0x04600000 gran 0x14 mem <node 0 link 0>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00d4000000 - 0x00d41fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 01:05.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem
PCI: 01:05.0 14 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 18 <- [0x00d4100000 - 0x00d410ffff] size 0x00010000 gran 0x10 mem
PCI: 01:05.0 24 <- [0x00d4000000 - 0x00d40fffff] size 0x00100000 gran 0x14 mem
PCI: 01:05.1 10 <- [0x00d4110000 - 0x00d4113fff] size 0x00004000 gran 0x0e mem
PCI: 00:01.0 assign_resources, bus 1 link: 0
PCI: 00:08.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:08.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:08.0 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:09.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:09.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:09.0 20 <- [0x00d4200000 - 0x00d42fffff] size 0x00100000 gran 0x14 bus 03 mem
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 03:00.0 10 <- [0x00d4200000 - 0x00d4207fff] size 0x00008000 gran 0x0f mem64
PCI: 00:09.0 assign_resources, bus 3 link: 0
PCI: 00:0a.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io
PCI: 00:0a.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:0a.0 20 <- [0x00d4300000 - 0x00d43fffff] size 0x00100000 gran 0x14 bus 04 mem
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 04:00.0 10 <- [0x00d4300000 - 0x00d433ffff] size 0x00040000 gran 0x12 mem64
PCI: 04:00.0 18 <- [0x0000002000 - 0x000000207f] size 0x00000080 gran 0x07 io
PCI: 00:0a.0 assign_resources, bus 4 link: 0
PCI: 00:11.0 10 <- [0x0000004020 - 0x0000004027] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000004040 - 0x0000004043] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000004028 - 0x000000402f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000004044 - 0x0000004047] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00d4508000 - 0x00d45083ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00d4504000 - 0x00d4504fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00d4508400 - 0x00d45084ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00d4505000 - 0x00d4505fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00d4508500 - 0x00d45085ff] size 0x00000100 gran 0x08 mem
ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned
PCI: 00:14.0 assign_resources, bus 1 link: 0
PCI: 00:14.0 assign_resources, bus 1 link: 0
sb800_sm_set_resources, res->base=0xfec00000
PCI: 00:14.1 10 <- [0x0000004030 - 0x0000004037] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000004048 - 0x000000404b] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000004038 - 0x000000403f] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x000000404c - 0x000000404f] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000004010 - 0x000000401f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00d4500000 - 0x00d4503fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00d4508700 - 0x00d4508700] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
ERROR: PNP: 002e.5 72 irq size: 0x0000000001 not assigned
PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io
ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned
PCI: 00:14.3 assign_resources, bus 0 link: 0
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:14.4 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:14.4 20 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 00:14.5 10 <- [0x00d4506000 - 0x00d4506fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.0 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 06 io
PCI: 00:15.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 00:15.0 20 <- [0x00d4400000 - 0x00d44fffff] size 0x00100000 gran 0x14 bus 06 mem
PCI: 00:15.0 assign_resources, bus 6 link: 0
PCI: 06:00.0 10 <- [0x00d4400000 - 0x00d44007ff] size 0x00000800 gran 0x0b mem64
PCI: 06:00.0 18 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io
PCI: 00:15.0 assign_resources, bus 6 link: 0
PCI: 00:16.0 10 <- [0x00d4507000 - 0x00d4507fff] size 0x00001000 gran 0x0c mem
PCI: 00:16.2 10 <- [0x00d4508600 - 0x00d45086ff] size 0x00000100 gran 0x08 mem
PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00d0000000 - 0x00d3ffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.0 assign_resources, bus 0 link: 0
PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI: 00:18.3 94 <- [0x00d8000000 - 0x00dbffffff] size 0x04000000 gran 0x1a mem <gart>
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
Root Device child on link 0 APIC_CLUSTER: 0
APIC_CLUSTER: 0 child on link 0 APIC: 00
APIC: 00
APIC: 01
APIC: 02
APIC: 03
PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0
PCI_DOMAIN: 0000 resource base 1000 size 4000 align 12 gran 0 limit ffff flags 40040100 index 10000000
PCI_DOMAIN: 0000 resource base c0000000 size 1c000000 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
PCI_DOMAIN: 0000 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20
PCI_DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30
PCI_DOMAIN: 0000 resource base b0000000 size 10000000 align 0 gran 0 limit 0 flags f0100200 index 7
PCI: 00:18.0 child on link 0 PCI: 00:00.0
PCI: 00:18.0 resource base 1000 size 4000 align 12 gran 12 limit ffff flags 60080100 index 10d8
PCI: 00:18.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60081200 index 10b8
PCI: 00:18.0 resource base d0000000 size 4600000 align 26 gran 20 limit dfffffff flags 60080200 index 10b0
PCI: 00:00.0
PCI: 00:01.0 child on link 0 PCI: 01:05.0
PCI: 00:01.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:01.0 resource base c0000000 size 10000000 align 28 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:01.0 resource base d4000000 size 200000 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 01:05.0
PCI: 01:05.0 resource base c0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001200 index 10
PCI: 01:05.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
PCI: 01:05.0 resource base d4100000 size 10000 align 16 gran 16 limit dfffffff flags 60000200 index 18
PCI: 01:05.0 resource base d4000000 size 100000 align 20 gran 20 limit dfffffff flags 60000200 index 24
PCI: 01:05.1
PCI: 01:05.1 resource base d4110000 size 4000 align 14 gran 14 limit dfffffff flags 60000200 index 10
PCI: 00:02.0
PCI: 00:03.0
PCI: 00:04.0
PCI: 00:05.0
PCI: 00:06.0
PCI: 00:07.0
PCI: 00:08.0
PCI: 00:08.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:08.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:08.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 00:09.0 child on link 0 PCI: 03:00.0
PCI: 00:09.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:09.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:09.0 resource base d4200000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 03:00.0
PCI: 03:00.0 resource base d4200000 size 8000 align 15 gran 15 limit dfffffff flags 60000201 index 10
PCI: 00:0a.0 child on link 0 PCI: 04:00.0
PCI: 00:0a.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:0a.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:0a.0 resource base d4300000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 04:00.0
PCI: 04:00.0 resource base d4300000 size 40000 align 18 gran 18 limit dfffffff flags 60000201 index 10
PCI: 04:00.0 resource base 2000 size 80 align 7 gran 7 limit ffff flags 60000100 index 18
PCI: 00:11.0
PCI: 00:11.0 resource base 4020 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
PCI: 00:11.0 resource base 4040 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
PCI: 00:11.0 resource base 4028 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
PCI: 00:11.0 resource base 4044 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
PCI: 00:11.0 resource base 4000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 00:11.0 resource base d4508000 size 400 align 10 gran 10 limit dfffffff flags 60000200 index 24
PCI: 00:12.0
PCI: 00:12.0 resource base d4504000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
PCI: 00:12.1
PCI: 00:12.2
PCI: 00:12.2 resource base d4508400 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:13.0
PCI: 00:13.0 resource base d4505000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
PCI: 00:13.1
PCI: 00:13.2
PCI: 00:13.2 resource base d4508500 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:14.0 child on link 0 I2C: 01:50
PCI: 00:14.0 resource base fec00000 size 1000 align 8 gran 8 limit fefffff flags 80000200 index 74
I2C: 01:50
I2C: 01:51
I2C: 01:52
I2C: 01:53
PCI: 00:14.1
PCI: 00:14.1 resource base 4030 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
PCI: 00:14.1 resource base 4048 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
PCI: 00:14.1 resource base 4038 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
PCI: 00:14.1 resource base 404c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
PCI: 00:14.1 resource base 4010 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
PCI: 00:14.2
PCI: 00:14.2 resource base d4500000 size 4000 align 14 gran 14 limit dfffffff flags 60000201 index 10
PCI: 00:14.3 child on link 0 PNP: 002e.0
PCI: 00:14.3 resource base d4508700 size 1 align 0 gran 0 limit dfffffff flags 60000200 index a0
PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
PNP: 002e.0
PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
PNP: 002e.1
PNP: 002e.1 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
PNP: 002e.2
PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.3
PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5
PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
PNP: 002e.307
PNP: 002e.8
PNP: 002e.9
PNP: 002e.109
PNP: 002e.209
PNP: 002e.309
PNP: 002e.a
PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.b
PNP: 002e.b resource base 290 size 2 align 1 gran 1 limit 7ff flags e0000100 index 60
PNP: 002e.b resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
PNP: 002e.c
PCI: 00:14.4
PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:14.4 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 00:14.5
PCI: 00:14.5 resource base d4506000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
PCI: 00:15.0 child on link 0 PCI: 06:00.0
PCI: 00:15.0 resource base 3000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
PCI: 00:15.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
PCI: 00:15.0 resource base d4400000 size 100000 align 20 gran 20 limit dfffffff flags 60080202 index 20
PCI: 06:00.0
PCI: 06:00.0 resource base d4400000 size 800 align 11 gran 11 limit dfffffff flags 60000201 index 10
PCI: 06:00.0 resource base 3000 size 100 align 8 gran 8 limit ffff flags 60000100 index 18
PCI: 00:16.0
PCI: 00:16.0 resource base d4507000 size 1000 align 12 gran 12 limit dfffffff flags 60000200 index 10
PCI: 00:16.1
PCI: 00:16.2
PCI: 00:16.2 resource base d4508600 size 100 align 8 gran 8 limit dfffffff flags 60000200 index 10
PCI: 00:18.0
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base d0000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
PCI: 00:18.4
PCI: 00:18.1
PCI: 00:18.2
PCI: 00:18.3
PCI: 00:18.3 resource base d8000000 size 4000000 align 26 gran 26 limit dfffffff flags 60000200 index 94
PCI: 00:18.4
Done allocating resources.
POST: 0x88
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 0000/0000
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 0000/0000
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 0000/0000
PCI: 00:18.4 cmd <- 00
PCI: 00:00.0 subsystem <- 0000/0000
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 00:08.0 bridge ctrl <- 0003
PCI: 00:08.0 cmd <- 00
PCI: 00:09.0 bridge ctrl <- 0003
PCI: 00:09.0 cmd <- 06
PCI: 00:0a.0 bridge ctrl <- 0003
PCI: 00:0a.0 cmd <- 07
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 0000/0000
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 0000/0000
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 0000/0000
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 0000/0000
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 0000/0000
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 0000/0000
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 0000/0000
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 0000/0000
PCI: 00:14.3 cmd <- 0f
sb800 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff
sb800 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff
sb800 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb800 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
sb800 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000291
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 00
PCI: 00:14.5 subsystem <- 0000/0000
PCI: 00:14.5 cmd <- 02
PCI: 00:15.0 bridge ctrl <- 0003
PCI: 00:15.0 cmd <- 07
PCI: 00:16.0 subsystem <- 0000/0000
PCI: 00:16.0 cmd <- 02
PCI: 00:16.2 subsystem <- 0000/0000
PCI: 00:16.2 cmd <- 02
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 cmd <- 00
PCI: 01:05.0 cmd <- 03
PCI: 01:05.1 cmd <- 02
PCI: 03:00.0 cmd <- 02
PCI: 04:00.0 cmd <- 03
PCI: 06:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00001000, code_size=0x00000031
Initializing CPU #0
CPU: vendor AMD device 100f42
CPU: family 10, model 04, stepping 02
nodeid = 00, coreid = 00
POST: 0x60
Enabling cache
CPU ID 0x80000001: 100f42
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 0, base: 2816MB, range: 256MB, type UC
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 1, base: 0MB, range: 4096MB, type WB
ADDRESS_MASK_HIGH=0xffff
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs
POST: 0x6a
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
CPU model: AMD Phenom(tm) II X4 925 Processor
siblings = 03, CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Sending STARTUP.
After apic_write.
Initializing CPU #3
Startup point 1.
Waiting for send to finish...
+CPU: vendor AMD device 100f42
After Startup.
Waiting for 3 CPUS to stop
Initializing CPU #1
Initializing CPU #2
CPU: vendor AMD device 100f42
CPU: family 10, model 04, stepping 02
CPU: vendor AMD device 100f42
nodeid = 00, coreid = 03
CPU: family 10, model 04, stepping 02
CPU: family 10, model 04, stepping 02
nodeid = 00, coreid = 01
nodeid = 00, coreid = 02
POST: 0xPOST: 0xPOST: 0x6060
60
Enabling cache
Enabling cache
CPU ID 0x80000001: 100f42
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
CPU ID 0x80000001: 100f42
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-88) type: UC
Enabling cache
CPU ID 0x80000001: 100f42
CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
ADDRESS_MASK_HIGH=0xffff
Betting fixedS MeTttRiRsn(g 2v4-a8r8ia)b Tlyep MeT: RWR B0, ,R dbaMsEMe,: 2Wr8M16EMM
, range: 256MB, type UC
DOANED DRfEiSxeSd_M AMTSRKR_HsI
GH=0xffff
ADDRESS_MASK_HIGH=0xffff
5etting variabSeltet MiTngR R v1ar,i ababslee :M T RR 00MB,, b arasneg: e2: 84160M96BM,B r,a tnygep:e W2B
6MB, type UC
IGNADED fRiESxSe_d MMATSKR_RsH
H=0xffff
ADDRESS_MASK_HIGH=0xffff
ADDRESS_MASK_HIGH=0xffff
5etting variaSbleett iMTnRg Rv 2a,ri abbaslee :M 3T0R7R 20MB,, b arsaneg: e2: 81160M24BM, Br,a tnygep:e U2C
6MB, type UC
SeAttDiDRnEgS vSa_MrAiSabKl_HeI GMTHR=0Rx 1f,ff fba
se: 0MB, range: 4096MB, type WB
DONE variable MTRRs
Clear out the extra MTRR's
Setting variable MTRR 1, base: 0MB, range: 4096MB, type WB
call enable_var_mtrr()
ADDRESS_MASK_HIGH=0xffff
Leave x86_setup_var_mtrrs
POST: 0x6a
Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
ADDRESS_MASK_HIGH=0xffff
DONE variable MTRRs
Clear out the extra MTRR's
Setting up local apic...Setting variable MTRR 2, base: 3072MB, range: 1024MB, type UC
call enable_var_mtrr()
DONE variable MTRRs
Clear out the extra MTRR's
Leave x86_setup_var_mtrrs
POST: 0x6a
apic_id: 0x03 done.
POST: 0x9b
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
call enable_var_mtrr()
Setting up local apic...Leave x86_setup_var_mtrrs
POST: 0x6a
apic_id: 0x01 done.
POST: 0x9b
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
POST: 0x93
CPU model: AMD Phenom(tm) II X4 925 Processor
Setting up local apic...CPU model: AMD Phenom(tm) II X4 925 Processor
apic_id: 0x02 done.
POST: 0x9b
siblings = 03, siblings = 03, CPU model: AMD Phenom(tm) II X4 925 Processor
CPU #3 initialized
CPU #1 initialized
siblings = 03, Waiting for 2 CPUS to stop
CPU #2 initialized
Waiting for 1 CPUS to stop
Waiting for send to finish...
+All AP CPUs stopped (25655 loops)
PCI: 00:18.0 init
PCI: 00:18.1 init
CBFS: Looking for 'pci1022,1201.rom'
CBFS: Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
CBFS: Looking for 'pci1022,1202.rom'
CBFS: Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
CBFS: Looking for 'pci1022,1204.rom'
CBFS: Could not find file 'pci1022,1204.rom'.
PCI: 00:00.0 init
CBFS: Looking for 'pci1022,9601.rom'
CBFS: Could not find file 'pci1022,9601.rom'.
PCI: 00:11.0 init
sata_bar0=4020
sata_bar1=4040
sata_bar2=4028
sata_bar3=4044
sata_bar4=4000
sata_bar5=d4508000
rev_id=13
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 0
No Primary Slave SATA drive on Slot1
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
PCI: 00:12.0 init
PCI: 00:12.2 init
usb2_bar0=0xd4508400
PCI: 00:13.0 init
PCI: 00:13.2 init
usb2_bar0=0xd4508500
PCI: 00:14.0 init
sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
RTC Init
PCI: 00:14.1 init
CBFS: Looking for 'pci1002,439c.rom'
CBFS: Could not find file 'pci1002,439c.rom'.
PCI: 00:14.2 init
base = 0xd4500000
codec_mask = 0f
3(th) codec viddid: 00000000
2(th) codec viddid: 00000000
1(th) codec viddid: 00000000
0(th) codec viddid: 10ec0892
PCI: 00:14.3 init
PCI: 00:14.4 init
PCI: 00:14.5 init
PCI: 00:15.0 init
pcie_init in rs780_ht.c
PCI: 00:16.0 init
PCI: 00:16.2 init
usb2_bar0=0xd4508600
PCI: 00:18.0 init
PCI: 00:18.1 init
CBFS: Looking for 'pci1022,1201.rom'
CBFS: Could not find file 'pci1022,1201.rom'.
PCI: 00:18.2 init
CBFS: Looking for 'pci1022,1202.rom'
CBFS: Could not find file 'pci1022,1202.rom'.
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 00:18.4 init
CBFS: Looking for 'pci1022,1204.rom'
CBFS: Could not find file 'pci1022,1204.rom'.
PCI: 01:05.0 init
CBFS: Looking for 'pci1002,9715.rom'
CBFS: Could not find file 'pci1002,9715.rom'.
PCI: 01:05.1 init
CBFS: Looking for 'pci1002,970f.rom'
CBFS: Could not find file 'pci1002,970f.rom'.
PCI: 03:00.0 init
CBFS: Looking for 'pci1b6f,7023.rom'
CBFS: Could not find file 'pci1b6f,7023.rom'.
PCI: 04:00.0 init
CBFS: Looking for 'pci1969,1083.rom'
CBFS: Could not find file 'pci1969,1083.rom'.
PNP: 002e.2 init
PNP: 002e.3 init
PNP: 002e.5 init
PNP: 002e.8 init
PNP: 002e.9 init
PNP: 002e.109 init
PNP: 002e.209 init
PNP: 002e.b init
PCI: 06:00.0 init
CBFS: Looking for 'pci1106,3403.rom'
CBFS: Could not find file 'pci1106,3403.rom'.
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:02.0: enabled 0
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 1
PCI: 00:09.0: enabled 1
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 0
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 0
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 01:50: enabled 1
I2C: 01:51: enabled 1
I2C: 01:52: enabled 1
I2C: 01:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 0
PNP: 002e.2: enabled 1
PNP: 002e.3: enabled 1
PNP: 002e.5: enabled 1
PNP: 002e.307: enabled 0
PNP: 002e.8: enabled 1
PNP: 002e.9: enabled 1
PNP: 002e.109: enabled 1
PNP: 002e.209: enabled 1
PNP: 002e.309: enabled 0
PNP: 002e.a: enabled 0
PNP: 002e.b: enabled 1
PNP: 002e.c: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 1
PCI: 00:16.0: enabled 1
PCI: 00:16.1: enabled 0
PCI: 00:16.2: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
APIC: 01: enabled 1
APIC: 02: enabled 1
APIC: 03: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 01:05.0: enabled 1
PCI: 01:05.1: enabled 1
PCI: 03:00.0: enabled 1
PCI: 04:00.0: enabled 1
PCI: 06:00.0: enabled 1
POST: 0x89
Re-Initializing CBMEM area to 0xaffe0000
Initializing CBMEM area to 0xaffe0000 (131072 bytes)
Adding CBMEM entry as no. 1
Moving GDT to affe0200...ok
High Tables Base is affe0000.
POST: 0x9a
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0xaffe0400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
POST: 0x9b
Wrote the mp table end at: 000f0410 - 000f0554
Adding CBMEM entry as no. 3
Wrote the mp table end at: affe1410 - affe1554
MP table: 340 bytes.
POST: 0x9c
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at affe2400...
ACPI: * HPET at affe24c8
ACPI: added table 1/32, length now 40
ACPI: * MADT at affe2500
ACPI: added table 2/32, length now 44
ACPI: * SRAT at affe2570
SRAT: lapic cpu_index=00, node_id=00, apic_id=00
SRAT: lapic cpu_index=01, node_id=00, apic_id=01
SRAT: lapic cpu_index=02, node_id=00, apic_id=02
SRAT: lapic cpu_index=03, node_id=00, apic_id=03
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00
set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000
ACPI: added table 3/32, length now 48
ACPI: * SLIT at affe2658
ACPI: added table 4/32, length now 52
ACPI: * coreboot PSTATE/TOM SSDT at affe2690
ACPI: added table 5/32, length now 56
ACPI: * DSDT at affe26d8
ACPI: * DSDT @ affe26d8 Length 298c
ACPI: * FACS at affe5068
ACPI: * FADT at affe50a8
pm_base: 0x0800
ACPI: added table 6/32, length now 60
ACPI: done.
ACPI tables: 11676 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: affed800
Root Device (ASROCK 880G Pro3 Mainboard)
APIC_CLUSTER: 0 (AMD FAM10 Root Complex)
APIC: 00 (socket AM3)
PCI_DOMAIN: 0000 (AMD FAM10 Root Complex)
PCI: 00:18.0 (AMD FAM10 Northbridge)
PCI: 00:00.0 (ATI RS780)
PCI: 00:01.0 (ATI RS780)
PCI: 00:02.0 (ATI RS780)
PCI: 00:03.0 (ATI RS780)
PCI: 00:04.0 (ATI RS780)
PCI: 00:05.0 (ATI RS780)
PCI: 00:06.0 (ATI RS780)
PCI: 00:07.0 (ATI RS780)
PCI: 00:08.0 (ATI RS780)
PCI: 00:09.0 (ATI RS780)
PCI: 00:0a.0 (ATI RS780)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.1 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.1 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 01:50 ()
I2C: 01:51 ()
I2C: 01:52 ()
I2C: 01:53 ()
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 002e.0 (Winbond W83627DHG Super I/O)
PNP: 002e.1 (Winbond W83627DHG Super I/O)
PNP: 002e.2 (Winbond W83627DHG Super I/O)
PNP: 002e.3 (Winbond W83627DHG Super I/O)
PNP: 002e.5 (Winbond W83627DHG Super I/O)
PNP: 002e.307 (Winbond W83627DHG Super I/O)
PNP: 002e.8 (Winbond W83627DHG Super I/O)
PNP: 002e.9 (Winbond W83627DHG Super I/O)
PNP: 002e.109 (Winbond W83627DHG Super I/O)
PNP: 002e.209 (Winbond W83627DHG Super I/O)
PNP: 002e.309 (Winbond W83627DHG Super I/O)
PNP: 002e.a (Winbond W83627DHG Super I/O)
PNP: 002e.b (Winbond W83627DHG Super I/O)
PNP: 002e.c (Winbond W83627DHG Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.1 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.1 (AMD FAM10 Northbridge)
PCI: 00:18.2 (AMD FAM10 Northbridge)
PCI: 00:18.3 (AMD FAM10 Northbridge)
PCI: 00:18.4 (AMD FAM10 Northbridge)
APIC: 01 ()
APIC: 02 ()
APIC: 03 ()
PCI: 00:18.0 ()
PCI: 00:18.1 ()
PCI: 00:18.2 ()
PCI: 00:18.3 ()
PCI: 00:18.4 ()
PCI: 01:05.0 ()
PCI: 01:05.1 ()
PCI: 03:00.0 ()
PCI: 04:00.0 ()
PCI: 06:00.0 ()
SMBIOS tables: 299 bytes.
POST: 0x9d
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6fdf
New low_table_end: 0x00000528
Now going to write high coreboot table at 0xaffee000
rom_table_end = 0xaffee000
Adjust low_table_end from 0x00000528 to 0x00001000
Adjust rom_table_end from 0xaffee000 to 0xafff0000
Adding high table area
uma_memory_start=0xb0000000, uma_memory_size=0x10000000
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-00000000affdffff: RAM
3. 00000000affe0000-00000000afffffff: CONFIGURATION TABLES
4. 00000000b0000000-00000000bfffffff: RESERVED
5. 00000000e0000000-00000000efffffff: RESERVED
6. 0000000100000000-000000013fffffff: RAM
Wrote coreboot table at: affee000, 0x208 bytes, checksum 40ed
coreboot table: 544 bytes.
POST: 0x9e
POST: 0x9d
Multiboot Information structure has been written.
0. FREE SPACE afff6000 0000a000
1. GDT affe0200 00000200
2. IRQ TABLE affe0400 00001000
3. SMP TABLE affe1400 00001000
4. ACPI affe2400 0000b400
5. SMBIOS affed800 00000800
6. COREBOOT affee000 00008000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
Loading segment from rom address 0xffc25f78
code (compression=1)
New segment dstaddr 0xe760c memsize 0x189f4 srcaddr 0xffc25fb0 filesize 0xc713
(cleaned up) New segment addr 0xe760c size 0x189f4 offset 0xffc25fb0 filesize 0xc713
Loading segment from rom address 0xffc25f94
Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e760c memsz: 0x00000000000189f4 filesz: 0x000000000000c713
lb: [0x0000000000200000, 0x0000000000330000)
Post relocation: addr: 0x00000000000e760c memsz: 0x00000000000189f4 filesz: 0x000000000000c713
using LZMA
[ 0x000e760c, 00100000, 0x00100000) <- ffc25fb0
dest 000e760c, end 00100000, bouncebuffer afd80000
Loaded segments
Jumping to boot code at fc7db
POST: 0xf8
entry = 0x000fc7db
lb_start = 0x00200000
lb_size = 0x00130000
adjust = 0xafcb0000
buffer = 0xafd80000
elf_boot_notes = 0x00228e28
adjusted_boot_notes = 0xafed8e28
Start bios (version rel-1.7.0-82-g9d6bac1-20120722_133824-DarkstarU)
Found mainboard ASROCK 880G Pro3
Ram Size=0xaffe0000 (0x0000000040000000 high)
Relocating low data from 0x000e7d50 to 0x000ef790 (size 2153)
Relocating init from 0x000e85b9 to 0xaffc6820 (size 38579)
Found CBFS header at 0xfffffc90
CPU Mhz=2801
Found 29 PCI devices (max PCI bus is 06)
Found 4 cpu(s) max supported 4 cpu(s)
Copying PIR from 0xaffe0400 to 0x000fdbc0
Copying MPTABLE from 0xaffe1400/affe1410 to 0x000fda60
Copying ACPI RSDP from 0xaffe2400 to 0x000fda40
Copying SMBIOS entry point from 0xaffed800 to 0x000fda20
Scan for VGA option rom
EHCI init on dev 00:12.2 (regs=0xd4508420)
EHCI init on dev 00:13.2 (regs=0xd4508520)
OHCI init on dev 00:14.5 (regs=0xd4506000)
EHCI init on dev 00:16.2 (regs=0xd4508620)
Found 0 lpt ports
Found 2 serial ports
ATA controller 1 at 4020/4040/0 (irq 0 dev 88)
ATA controller 2 at 4028/4044/0 (irq 0 dev 88)
ATA controller 3 at 1f0/3f4/0 (irq 14 dev a1)
ATA controller 4 at 170/374/0 (irq 15 dev a1)
Got ps2 nak (status=51)
Searching bootorder for: /pci at i0cf8/usb at 12,2/storage at 3/*@0/*@0,0
Searching bootorder for: /pci at i0cf8/usb at 12,2/usb-*@3
USB MSC vendor='WDC' product='INIC-1610P' rev='1.01' type=0 removable=0
USB keyboard initialized
ehci_wait_td error - status=80000d42
Initialized USB HUB (1 ports used)
USB MSC blksize=512 sectors=625142448
All threads complete.
Scan for option roms
Press F12 for boot menu.
drive 0x000fd9b0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=625142448
Space available for UMB: 000c0000-000ef000
Returned 49152 bytes of ZoneHigh
e820 map has 7 items:
INE_SCROLL;24r
0: 0000000000000000 - 000000000009fc00 on1 RAM
1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
3: 0000000000100000 - 00000000affdc000 = 1 RAM
4: 00000000affdc000 - 00000000c0000000 = 2 RESERVED
5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED
6: 0000000100000000 - 0000000140000000 = 1 RAM
enter handle_19:
NULL
Booting from Hard Disk...
Booting from 0000:7c00
Memtest86+ v4.20 | Pass 0%
AMD K10 (45nm) @ 2800 MHz | Test 41% ###############
L1 Cache: 64K 45905 MB/s | Test #1 [Address test, own address]
L2 Cache: 512K 14816 MB/s | Testing: 2048M - 2816M 3840M
L3 Cache: 6144K 8750 MB/s | Pattern:
Memory : 3840M 3599 MB/s |-------------------------------------------------
IMC : AMD Phenom(tm) II X4 925 Processor (ECC : Disabled)
Settings: RAM : 400 MHz (DDR800) / CAS : 6-6-6-15 / DDR3 (64 bits)
WallTime Cached RsvdMem MemMap Cache ECC Test Pass Errors ECC Errs
--------- ------ ------- -------- ----- --- ---- ---- ------ --------
0:00:03 3840M 0K LxBIOS on off Std 0 6 0
-----------------------------------------------------------------------------
Tst Pass Failing Address Good Bad Err-Bits Count Chan
--- ---- ----------------------- -------- -------- -------- ----- ----
1 0 000000ef688 - 0.9MB 000ef688 000ef618 00000090 1
1 0 000000ef698 - 0.9MB 000ef698 000ef618 00000080 2
1 0 000000ef6a0 - 0.9MB 000ef6a0 000ef0a0 00000600 3
1 0 000000ef688 - 0.9MB 000ef688 000ef618 00000090 4
1 0 000000ef698 - 0.9MB 000ef698 000ef618 00000080 5
1 0 000000ef6a0 - 0.9MB 000ef6a0 000ef0a0 00000600 6
1 0 000affdc130 - 2815.8MB affdc130 0ffdc130 a0000000 8
1 0 000affdc134 - 2815.8MB affdc134 0ffdc134 a0000000 9