[coreboot] New patch to review for coreboot: 055e26e Drop (empty) sandybridge_late_initialization()

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Mon Jul 23 23:21:12 CEST 2012


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1290

-gerrit

commit 055e26eaeff8c4f2558d7dbadbbc7e4953eee260
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Jun 18 15:43:50 2012 -0700

    Drop (empty) sandybridge_late_initialization()
    
    The function is empty (a left-over from i945) and should be removed.
    
    Change-Id: I91e573b5e37cb9133ea1037aef7e6daf3c292864
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/mainboard/intel/emeraldlake2/romstage.c    |    5 +----
 src/mainboard/samsung/lumpy/romstage.c         |    5 +----
 src/mainboard/samsung/stumpy/romstage.c        |    5 +----
 src/northbridge/intel/sandybridge/early_init.c |    5 -----
 4 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index aba89d4..f8ef17d 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -312,11 +312,8 @@ void main(unsigned long bist)
 	rcba_config();
 	post_code(0x3d);
 
-	/* Initialize the internal PCIe links before we go into stage2 */
-	sandybridge_late_initialization();
-
-	post_code(0x3e);
 	quick_ram_check();
+	post_code(0x3e);
 
 	MCHBAR16(SSKPD) = 0xCAFE;
 #if CONFIG_EARLY_CBMEM_INIT
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 82856f6..09cbd2a 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -330,11 +330,8 @@ void main(unsigned long bist)
 	rcba_config();
 	post_code(0x3c);
 
-	/* Initialize the internal PCIe links before we go into stage2 */
-	sandybridge_late_initialization();
-
-	post_code(0x3e);
 	quick_ram_check();
+	post_code(0x3e);
 
 	MCHBAR16(SSKPD) = 0xCAFE;
 
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 10a9d7b..68f6260 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -335,11 +335,8 @@ void main(unsigned long bist)
 	rcba_config();
 	post_code(0x3c);
 
-	/* Initialize the internal PCIe links before we go into stage2 */
-	sandybridge_late_initialization();
-
-	post_code(0x3e);
 	quick_ram_check();
+	post_code(0x3e);
 
 	MCHBAR16(SSKPD) = 0xCAFE;
 #if CONFIG_EARLY_CBMEM_INIT
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f052fbc..48faf5f 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -158,8 +158,3 @@ void sandybridge_early_initialization(int chipset_type)
 
 	sandybridge_setup_graphics();
 }
-
-void sandybridge_late_initialization(void)
-{
-}
-




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