[coreboot] New patch to review for coreboot: 81a02a1 SMM: Skip locking SPI registers in finalize step

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1318

-gerrit

commit 81a02a12b1f4a1fb9be6217f3249debb34ed7043
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Jun 23 17:02:29 2012 -0700

    SMM: Skip locking SPI registers in finalize step
    
    This is a temporary workaround so the SPI bus can be accessed
    at runtime in SMM code until the SPI opcode menu is used
    properly.
    
    Change-Id: I93d188c55b66d8dce49fa91a1de53ee195944b30
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/bd82x6x/finalize.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7..d62600f 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -31,8 +31,11 @@ void intel_pch_finalize_smm(void)
 	RCBA32(0x3898) = SPI_OPMENU_LOWER;
 	RCBA32(0x389c) = SPI_OPMENU_UPPER;
 
+/* Need to fix SMI driver use of opcode menu */
+#if !CONFIG_ELOG_GSMI
 	/* Lock SPIBAR */
 	RCBA32_OR(0x3804, (1 << 15));
+#endif
 
 	/* TCLOCKDN: TC Lockdown */
 	RCBA32_OR(0x0050, (1 << 31));