[coreboot] New patch to review for coreboot: 1eb5629 ACPI: Add function to write _PPC using NVS
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Jul 24 01:43:00 CEST 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1341
-gerrit
commit 1eb5629e24af2b52941848d57ae251565b5dc207
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Mon Jul 16 12:11:53 2012 -0700
ACPI: Add function to write _PPC using NVS
The existing NVS variable for PPCM will be used to
select a dynamic max P-state.
By itself this does not change existing behavior because
the NVS PPCM variable is initialized to zero.
PPCM can be tested by building and booting a modified BIOS
that sets gnvs->ppcm to a value greater than 1 and checking
from the OS that the P-state is limited to that value.
Change-Id: Ia7b3bbc6b84c1aa42349bb236abee5cc92486561
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/arch/x86/boot/acpigen.c | 26 ++++++++++++++++++++++++++
src/arch/x86/include/arch/acpigen.h | 1 +
src/cpu/intel/model_206ax/acpi.c | 2 +-
3 files changed, 28 insertions(+), 1 deletions(-)
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index 71aa10c..47845a0 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -396,6 +396,32 @@ int acpigen_write_PPC(u8 nr)
return len;
}
+/* generates a func with max supported P states */
+int acpigen_write_PPC_NVS(void)
+{
+/*
+ Method (_PPC, 0, NotSerialized)
+ {
+ Return (PPCM)
+ }
+*/
+ int len;
+ /* method op */
+ acpigen_emit_byte(0x14);
+ len = acpigen_write_len_f();
+ len += acpigen_emit_namestring("_PPC");
+ /* no fnarg */
+ acpigen_emit_byte(0x00);
+ /* return */
+ acpigen_emit_byte(0xa4);
+ /* arg */
+ len += acpigen_emit_namestring("PPCM");
+ /* add all single bytes */
+ len += 3;
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
int acpigen_write_TPC(const char *gnvs_tpc_limit)
{
/*
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index aebf508..5297aff 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -42,6 +42,7 @@ int acpigen_write_name_qword(const char *name, uint64_t val);
int acpigen_write_name_byte(const char *name, uint8_t val);
int acpigen_write_scope(const char *name);
int acpigen_write_PPC(u8 nr);
+int acpigen_write_PPC_NVS(void);
int acpigen_write_empty_PCT(void);
int acpigen_write_empty_PTC(void);
int acpigen_write_TPC(const char *gnvs_tpc_limit);
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index 9784c47..f66df51 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -251,7 +251,7 @@ static int generate_P_state_entries(int core, int cores_per_package)
len = acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
- len += acpigen_write_PPC(0);
+ len += acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
More information about the coreboot
mailing list