[coreboot] Patch merged into coreboot/master: fe5a554 SMM: Fix state save map for sandybridge and TSEG

gerrit at coreboot.org gerrit at coreboot.org
Tue Jul 24 23:49:29 CEST 2012

the following patch was just integrated into master:
commit fe5a5548bd833818ec15d2fa6ad121794dd29d62
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Sat Jun 23 15:22:43 2012 -0700

    SMM: Fix state save map for sandybridge and TSEG
    There are enough differences that it is worth defining the
    proper map for the sandybridge/ivybridge CPUs.  The state
    save map was not being addressed properly for TSEG and
    needs to use the right offset instead of pointing in ASEG.
    To do this properly add a required southbridge export to
    return the TSEG base and use that where appropriate.
    Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>

Build-Tested: build bot (Jenkins) at Tue Jul 24 14:31:46 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Tue Jul 24 23:49:28 2012, giving +2
See http://review.coreboot.org/1309 for details.


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