[coreboot] New patch to review for coreboot: fad6d0b SMM: Fix state table for Intel Core2 CPUs

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1353

-gerrit

commit fad6d0bbfd2152af48bc4648e72afe839f306d3d
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Jul 24 14:53:15 2012 -0700

    SMM: Fix state table for Intel Core2 CPUs
    
    When fixing the SMM state table for SandyBridge/IvyBridge CPUs
    the wrong table was used for older 64bit capable CPUs.
    
    Change-Id: Ia7dff21aa3f0e5aa61575634fc839777de6bef10
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/smm/smihandler.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index 83ebaf9..10f38f9 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -158,6 +158,7 @@ void smi_handler(u32 smm_revision)
 		state_save.type = EM64T;
 		state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
 			(smm_base + 0x7d00 - (node * 0x400));
+		break;
 	case 0x00030101: /* SandyBridge/IvyBridge */
 		state_save.type = EM64T101;
 		state_save.em64t101_state_save =