From gerrit at coreboot.org  Fri Jun  1 12:21:16 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:21:16 +0200
Subject: [coreboot] Patch merged into coreboot/master: aad56a1 libpayload:
	Add clear_feature() function to USB framework
References: <I4d1d2e94f4442cbb636ae989e8ffd543181c4357+0@gerrit.coreboot.org>
Message-ID: <E1SaOyq-0005JY-IP@ra.coresystems.de>

the following patch was just integrated into master:
commit aad56a1666c97ec6c78e4e191b134c0ac4216361
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 16:19:05 2012 +0200

    libpayload: Add clear_feature() function to USB framework
    
    This function will be used by the USB hub driver.
    
    Change-Id: I4d1d2e94f4442cbb636ae989e8ffd543181c4357
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:21:13 2012, giving +2
See http://review.coreboot.org/1079 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:22:10 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:22:10 +0200
Subject: [coreboot] Patch merged into coreboot/master: 8141a15 libpayload:
	Correct port power settings for EHCI root hub
References: <I8897756ed2bfcb88408fe5e9f9e3f8af5dd900ac+0@gerrit.coreboot.org>
Message-ID: <E1SaOzi-0005Uy-AL@ra.coresystems.de>

the following patch was just integrated into master:
commit 8141a15f6aa96be6c388421fa190950cfbaf9f55
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:56:21 2012 +0200

    libpayload: Correct port power settings for EHCI root hub
    
    Enable power on EHCI root hub ports only if the controller supports it.
    Wait 20ms for the power to become stable.
    
    Change-Id: I8897756ed2bfcb88408fe5e9f9e3f8af5dd900ac
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:22:08 2012, giving +2
See http://review.coreboot.org/1078 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:22:40 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:22:40 +0200
Subject: [coreboot] Patch merged into coreboot/master: fe83010 libpayload:
	fix UHCI timeout
References: <Iebcf338317164eb1e683e1de850ffab5022ca3a1+0@gerrit.coreboot.org>
Message-ID: <E1SaP0D-0005cU-0M@ra.coresystems.de>

the following patch was just integrated into master:
commit fe83010951dbf184cb5665ed375851360073d02b
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue May 29 16:19:19 2012 +0200

    libpayload: fix UHCI timeout
    
    UHCI commands should have a timeout of 30ms, not 30s!
    
    Change-Id: Iebcf338317164eb1e683e1de850ffab5022ca3a1
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:22:38 2012, giving +2
See http://review.coreboot.org/1085 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:23:06 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:23:06 +0200
Subject: [coreboot] Patch merged into coreboot/master: f1f1cbb libpayload:
	fix OHCI IN commands
References: <I87ef51590c9db7a6cbc7304e1ccac29895f8a51e+0@gerrit.coreboot.org>
Message-ID: <E1SaP0c-0005fx-OC@ra.coresystems.de>

the following patch was just integrated into master:
commit f1f1cbb111ff7a5b70d6a9baf1c75d28f70bffc1
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue May 29 14:28:26 2012 +0200

    libpayload: fix OHCI IN commands
    
    Due to operator precedence incomming USB commands were missing some
    flags.
    
    Change-Id: I87ef51590c9db7a6cbc7304e1ccac29895f8a51e
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:22:59 2012, giving +2
See http://review.coreboot.org/1084 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:24:19 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:24:19 +0200
Subject: [coreboot] Patch merged into coreboot/master: 6ce9398 libpayload:
	Disable some buggy debugging code
References: <Ic274c162846137ee00638ffbc59ccf1d8130586f+0@gerrit.coreboot.org>
Message-ID: <E1SaP1n-0005si-Pj@ra.coresystems.de>

the following patch was just integrated into master:
commit 6ce9398ed02e1fd55b1f329de89e4eff5e1c8c2a
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:38:08 2012 +0200

    libpayload: Disable some buggy debugging code
    
    This disables some debugging code in the OHCI USB driver which causes
    reboots under rare circumstances.
    
    Change-Id: Ic274c162846137ee00638ffbc59ccf1d8130586f
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:24:16 2012, giving +2
See http://review.coreboot.org/1074 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:25:21 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:25:21 +0200
Subject: [coreboot] Patch merged into coreboot/master: b2718de Enable
	CONFIG_GFXUMA for roda/rk886ex
References: <I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c+0@gerrit.coreboot.org>
Message-ID: <E1SaP2n-0006J2-SB@ra.coresystems.de>

the following patch was just integrated into master:
commit b2718de7d2812aa391e6c845ef344ed8a35b8f3a
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed May 30 14:50:53 2012 +0200

    Enable CONFIG_GFXUMA for roda/rk886ex
    
    Without GFXUMA beeing set, MTRR initialization runs out of variable MTRRs.
    
    Change-Id: I5d1aa0d5fa2d72f17a0d88cae3fad880b489828c
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:25:13 2012, giving +2
See http://review.coreboot.org/1086 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 12:26:34 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 1 Jun 2012 12:26:34 +0200
Subject: [coreboot] Patch merged into coreboot/master: 3e0c664 libpayload:
	Remove orphaned delay from USB mass storage
References: <Ida7423229373ec521d4326c5467a3f518b76149c+0@gerrit.coreboot.org>
Message-ID: <E1SaP3y-0006z3-AE@ra.coresystems.de>

the following patch was just integrated into master:
commit 3e0c6641a94dbcb652f9283b4b769c56c0d9829a
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:01:52 2012 +0200

    libpayload: Remove orphaned delay from USB mass storage
    
    This removes a synthetic delay of 10ms from every mass storage command.
    A delay here seems to be of no use and first tests have only shown a
    huge speed increase.
    
    Change-Id: Ida7423229373ec521d4326c5467a3f518b76149c
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Jun  1 12:26:30 2012, giving +2
See http://review.coreboot.org/1071 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  1 13:59:41 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Fri, 1 Jun 2012 13:59:41 +0200
Subject: [coreboot] New patch to review for filo: 4193fd9 Make booting from
	ATAPI drives more resilient.
References: <Iabf20120c841bbc277af4efa48c6594804f60205+0@gerrit.coreboot.org>
Message-ID: <Iabf20120c841bbc277af4efa48c6594804f60205+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1087

-gerrit

commit 4193fd9b4921a78831f9346b02cbb004b69b16e3
Author: Nico Huber <nico.huber at secunet.com>
Date:   Fri May 25 11:34:08 2012 +0200

    Make booting from ATAPI drives more resilient.
    
    This fixes a semantic error, where the ATAPI driver requested sense from the
    drive instead of retrying a failed command (i.e. the actual command had been
    overwritten). The count of retries and delays are also adapted to behave
    more like the Linux kernel driver.
    
    Change-Id: Iabf20120c841bbc277af4efa48c6594804f60205
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>
---
 drivers/ide_new.c |   90 +++++++++++++++++++++++------------------------------
 drivers/ide_new.h |    6 ++--
 2 files changed, 42 insertions(+), 54 deletions(-)

diff --git a/drivers/ide_new.c b/drivers/ide_new.c
index 658f177..cc1fb83 100644
--- a/drivers/ide_new.c
+++ b/drivers/ide_new.c
@@ -192,8 +192,10 @@ ob_ide_error(struct ide_drive *drive, unsigned char stat, char *msg)
 			for (i = 0; i < sizeof(cmd->cdb); i++)
 				debug("%02x ", cmd->cdb[i]);
 		}
-		if (cmd->sense_valid)
-			debug(", sense: %02x/%02x/%02x", cmd->sense.sense_key, cmd->sense.asc, cmd->sense.ascq);
+		if (cmd->sense)
+			debug(", sense: %02x/%02x/%02x",
+					cmd->sense->sense_key,
+					cmd->sense->asc, cmd->sense->ascq);
 		else
 			debug(", no sense");
 		debug("\n");
@@ -535,7 +537,7 @@ ob_ide_pio_packet(struct ide_drive *drive, struct atapi_command *cmd)
 static int
 ob_ide_atapi_packet(struct ide_drive *drive, struct atapi_command *cmd)
 {
-	int retries = 5, ret;
+	int retries = 10, ret;
 
 	if (drive->type != ide_type_atapi)
 		return 1;
@@ -550,33 +552,35 @@ ob_ide_atapi_packet(struct ide_drive *drive, struct atapi_command *cmd)
 		if (!ret)
 			break;
 
-		/*
-		 * request sense failed, bummer
-		 */
-		if (cmd->cdb[0] == ATAPI_REQ_SENSE)
-			break;
-
 		if (ob_ide_atapi_request_sense(drive))
 			break;
 
 		/*
-		 * we know sense is valid. retry if the drive isn't ready,
-		 * otherwise don't bother.
-		 */
-		if (cmd->sense.sense_key != ATAPI_SENSE_NOT_READY)
-			break;
-		/*
-		 * ... except 'medium not present'
+		 * We know sense is valid. Retry if the unit attention
+		 * condition has been set (media change / reset) or the
+		 * drive isn't ready, otherwise don't bother.
 		 */
-		if (cmd->sense.asc == 0x3a) {
-			/* 'medium not present' is not an error */
-			ret = 0;
-			/* force reevaluation */
-			drive->channel->present = 0;
+		if (cmd->sense->sense_key == ATAPI_SENSE_UNIT_ATTENTION) {
+			/* Just retry. */
+		} else if (cmd->sense->sense_key == ATAPI_SENSE_NOT_READY) {
+			if (cmd->sense->asc == 0x04) {
+				/* The drive is becoming ready, give it some
+				 * more time. */
+				mdelay(3000);
+			} else if (cmd->sense->asc == 0x3a) {
+				/*
+				 * 'medium not present' is not an error,
+				 * but we have to report nevertheless
+				 */
+				ret = RETURN_NO_MEDIUM;
+				/* force reevaluation */
+				drive->channel->present = 0;
+				/* Don't retry in this case. */
+				break;
+			}
+		} else {
 			break;
 		}
-
-		mdelay(1000);
 	} while (retries--);
 
 	if (ret)
@@ -588,26 +592,25 @@ ob_ide_atapi_packet(struct ide_drive *drive, struct atapi_command *cmd)
 static int
 ob_ide_atapi_request_sense(struct ide_drive *drive)
 {
-	struct atapi_command *cmd = &drive->channel->atapi_cmd;
-	unsigned char old_cdb;
+	struct atapi_command *orig_cmd = &drive->channel->atapi_cmd;
+	struct atapi_command cmd;
 
+	memset(&cmd, 0, sizeof(cmd));
+
+	cmd.cdb[0] = ATAPI_REQ_SENSE;
+	cmd.cdb[4] = 18;
+	cmd.buffer = (unsigned char *)&drive->channel->atapi_sense;
+	cmd.buflen = 18;
+	cmd.data_direction = atapi_ddir_read;
 	/*
 	 * save old cdb for debug error
 	 */
-	old_cdb = cmd->cdb[0];
-
-	memset(cmd, 0, sizeof(*cmd));
-	cmd->cdb[0] = ATAPI_REQ_SENSE;
-	cmd->cdb[4] = 18;
-	cmd->buffer = (unsigned char *) &cmd->sense;
-	cmd->buflen = 18;
-	cmd->data_direction = atapi_ddir_read;
-	cmd->old_cdb = old_cdb;
+	cmd.old_cdb = orig_cmd->cdb[0];
 
-	if (ob_ide_atapi_packet(drive, cmd))
+	if (ob_ide_pio_packet(drive, &cmd))
 		return 1;
 
-	cmd->sense_valid = 1;
+	orig_cmd->sense = &drive->channel->atapi_sense;
 	return 0;
 }
 
@@ -621,21 +624,6 @@ ob_ide_atapi_drive_ready(struct ide_drive *drive)
 	struct atapi_capacity cap;
 	int i;
 
-	/*
-	 * Test Unit Ready is like a ping
-	 * But wait a bit, as the drive might take a while
-	 */
-	i = 30;
-	while (i-- != 0) {
-		memset(cmd, 0, sizeof(*cmd));
-		cmd->cdb[0] = ATAPI_TUR;
-
-		if (!ob_ide_atapi_packet(drive,cmd)) break;
-
-		/* Give the drive some time to breathe */
-		mdelay(500);
-	}
-
 	memset(cmd, 0, sizeof(*cmd));
 	cmd->cdb[0] = ATAPI_TUR;
 
diff --git a/drivers/ide_new.h b/drivers/ide_new.h
index f667e41..742cc42 100644
--- a/drivers/ide_new.h
+++ b/drivers/ide_new.h
@@ -77,6 +77,7 @@
  * atapi sense keys
  */
 #define ATAPI_SENSE_NOT_READY	0x02
+#define ATAPI_SENSE_UNIT_ATTENTION	0x06
 
 /*
  * supported device types
@@ -142,8 +143,7 @@ struct atapi_command {
 	unsigned char data_direction;
 
 	unsigned char stat;
-	unsigned char sense_valid;
-	struct request_sense sense;
+	struct request_sense *sense;
 	unsigned char old_cdb;
 };
 
@@ -199,7 +199,7 @@ struct ide_channel {
 	 */
 	struct ata_command ata_cmd;
 	struct atapi_command atapi_cmd;
-	
+	struct request_sense atapi_sense;
 };
 
 enum {



From rhyotte at gmail.com  Sun Jun  3 18:38:17 2012
From: rhyotte at gmail.com (gary sheppard)
Date: Sun, 3 Jun 2012 09:38:17 -0700
Subject: [coreboot] New Motherboards?
Message-ID: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>

Hello everyone,

Are there any new motherboards that are fully supported? About mid-year
2013 I will be looking to build a new desktop / workstation. I would like
to avoid UEFI like the plague. I am serious. If a donation would help I
would like to propose a "What board" type discussion. I am guessing Intel?
I am open minded on what board folks. I simply will not buy into UEFI. I
have read quite a bit of the specifications material, and I simply do not
believe that it cures any of the problems it seems to be saying it will. I
can foresee a security / user nightmare coming. Corporate Root kits were
bad enough before UEFI, I can only imagine how bad it will get after we are
all Secured using UEFI.

Thank you for your time and consideration,
Gary Sheppard
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From rminnich at gmail.com  Sun Jun  3 21:27:02 2012
From: rminnich at gmail.com (ron minnich)
Date: Sun, 3 Jun 2012 12:27:02 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
Message-ID: <CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>

Get a chromebox. It's quite well supported and it's a very fine machine.

ron



From manasa671989 at gmail.com  Mon Jun  4 14:54:13 2012
From: manasa671989 at gmail.com (manasa gv)
Date: Mon, 4 Jun 2012 18:24:13 +0530
Subject: [coreboot] Regarding contribution for coreboot
Message-ID: <CALYtimrh2oMCddpDkja=kxEmPF0ntaa-wUsAcHpc-11RC-z63g@mail.gmail.com>

Hi,


I am new and interested to work on coreboot.I have gone through the
coreboot website.
I am trying to do ?patch review.. But I am taking more time to come up
with the solution compared to others..
So,Please let me know any other ways to contribute for coreboot apart
from patch review??



Thanks,
Manasa



From mailinglists at fnoss.com  Mon Jun  4 14:42:51 2012
From: mailinglists at fnoss.com (mailinglists)
Date: Mon, 04 Jun 2012 13:42:51 +0100
Subject: [coreboot] Potential development funding.
Message-ID: <1797962.oed9JXq5lN@sosillyme>

Hi everyone,

My name is Nick Bowes and I'm looking to create a small (got to start 
somewhere) Foss-only computer build and supply business.  To make that viable, 
I need a free bios implementation for one or two new mobos, and coreboot seems 
to hold the most promise.  I'm interested in doing this in the hope that I can 
help the foss community get away from the emerging and likely pervasive UEFI 
stupidness thats coming. As you probably know better then I do, creating 
alternatives to the things that cause us all problems is the only way to 
truely solve them.

Having heard recently that Google released coreboot updates for both Sandy 
Bridge and Ivy Bridge chipsets, I thought now would be a good time to ask this 
mailing list a few questions about the viability of funding some development.

As a future small distributor of foss-only computers and likely a one man band 
to start with, I would need to keep things very simple.  That means creating a 
product line (if you can call it that) of perhaps only 3-5 different 
desktops/laptops in total.  Idealy I'd like to offer a range of 3 itx desktops, 
Ivy Bridge i3 i5 i7, or, Trinity A6 A8 A10, and one or two laptops, one 
budget, one highend.  

So, if you don't mind, and this is the right place(if it isn't, please point 
me in the right direction) I'd like to ask you all...

1.      What do you all think the requirements will be for replacing UEFI on 
future mobos.  Will it likely be a case of switching out the bios chip or just 
flashing it?

2.      What % of flashes resulted in bricked mobos? Do most new boards come 
with a backup chip which can restore life after a failure?  

3.      Can anyone reccomend a possible target ivy bridge or Trinity itx mobo 
for coreboot development?  Perhaps one that's already being worked on?

4.      If we can identify a good itx mobo for the desktop line-up,  would 
someone here be able to asses how much time a fairly full featured and 
reliable implementation of coreboot would take to develop?

        note: to me "fairly full featured would be to have all the 
fundamentals  up and avaliable for the OS to pick up, such as pci-e usb 3.0, 
hdmi, sata 3, wifi, and working reliably.

5.      Is there any special requirement for getting amd/nvidia gfx cards 
working with coreboot?

6.      Which hardware have you found to be the simplist to fully implement 
coreboot on, and which hardware (if any) should be considered a no go?  

7.      What type of computer would most on this list be interested to develop 
coreboot for.  As in, if you were going to buy a desktop or laptop today, or 
in the near future, what combination of hardware would you go for?

8.	What do you think about the viability of a kickstarter campaign to raise 
development funds.  Has anyone tried this yet?


I would truely love to distribute computers which run entirely on free 
software. Unfortunately, I'm no developer so If funding some development is 
the only way I can achieve this, I will find a way to do it.

I look forward to any insights you provide.

Thanks
Nick




From svn at coreboot.org  Mon Jun  4 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 04 Jun 2012 16:00:01 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1SbXpB-0001bt-Jm@ra.coresystems.de>

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From patrick at georgi-clan.de  Mon Jun  4 16:12:50 2012
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Mon, 04 Jun 2012 16:12:50 +0200
Subject: [coreboot] Potential development funding.
In-Reply-To: <1797962.oed9JXq5lN@sosillyme>
References: <1797962.oed9JXq5lN@sosillyme>
Message-ID: <4FCCC262.8040702@georgi-clan.de>

Am 04.06.2012 14:42, schrieb mailinglists:
> 1.      What do you all think the requirements will be for replacing UEFI on 
> future mobos.  Will it likely be a case of switching out the bios chip or just 
> flashing it?
We generally reuse the chips. If you're doing business, you should be
able to afford an external flasher, so getting rid of the original BIOS
is no problem, even if vendor BIOS locks down the chip on boot.

Some chip types are easier to flash externally than others, but that's
from a hobbyist perspective. As a business, investing some money in the
right adapter for a large number of boards isn't too bad, it's just hard
to justify spending $50 (to pick some upper bound) on a single-use item
when it's just a hobby.

> 2.      What % of flashes resulted in bricked mobos? Do most new boards come 
> with a backup chip which can restore life after a failure? 
With external flashing you can recover by just writing again. "bricked"
means wrong content and thus unable to boot, not destroyed chip (usually
- I've seen the latter case, but it's very rare).

> 3.      Can anyone reccomend a possible target ivy bridge or Trinity itx mobo 
> for coreboot development?  Perhaps one that's already being worked on?
As yet, Trinity is only released for notebooks, at least that's what I
gathered from the tech media. Desktop and server Trinity are scheduled
for summer and fall releases (AFAIK).

As for Ivybridge, please note that it requires a couple of binary-only
components (beyond those we usually need, see below): RAM init is done
with the Intel reference code, and to turn on the system in the first
place, the Management Engine (some embedded controller in the chipset)
requires a binary-only component as well.

It's remotely feasible to replace the RAM init with source (multimonth
effort, after obtaining access to the documentation), but the ME code
will remain a requirement (if only because it's said to be signed by
Intel, so replacing it requires cracking their signature scheme - good
luck).

> 4.      If we can identify a good itx mobo for the desktop line-up,  would 
> someone here be able to asses how much time a fairly full featured and 
> reliable implementation of coreboot would take to develop?
> 
>         note: to me "fairly full featured would be to have all the 
> fundamentals  up and avaliable for the OS to pick up, such as pci-e usb 3.0, 
> hdmi, sata 3, wifi, and working reliably.
This depends (among other things) on the kind of OS support you desire.
OSS systems are generally more forgiving for incomplete configuration
than Windows - but with "FOSS-only computers" Windows might not be a
priority.

> 5.      Is there any special requirement for getting amd/nvidia gfx cards 
> working with coreboot?
Minor hacks might be necessary to get the IGD/GFX switch to work right.
On systems with integrated graphics we generally expect IGD to manage
the primary display.
Details on that vary by chipset and/or vendor.

> 6.      Which hardware have you found to be the simplist to fully implement 
> coreboot on, and which hardware (if any) should be considered a no go? 
nVidia chipsets are no-go (there was a lucky strike once that gave us
the nVidia support we have - I don't expect that to happen again). Intel
chipsets are complicated. AMD is the best choice for coreboot support
these days.

We don't have to care about many other things (eg. the Wifi card - we
don't handle Wifi, we just have to make sure the card is found on the bus)

> 8.	What do you think about the viability of a kickstarter campaign to raise 
> development funds.  Has anyone tried this yet?
Last I heard Kickstarter has a backlog of several thousand projects.

Kickstarter seems to be first and foremost a social media popularity
contest at the moment, for which coreboot is probably not a fancy enough
topic. I'd assume the same for "FOSS Hardware", but feel free to try, if
you feel like it.

Make clear that you're not collecting funds for the coreboot project -
our situation is that we can't accept donations of any kind (nor take
money with any other designation).

> I would truely love to distribute computers which run entirely on free 
> software. Unfortunately, I'm no developer so If funding some development is 
> the only way I can achieve this, I will find a way to do it.
"run entirely on free software":
We usually reuse the VGABIOS image delivered by the hardware vendor,
which comes in binary-only form. There are a couple of ways around it,
but they're only appropriate for systems where you control the OS that's
used (eg. not doing VGA init at all and defer things to Linux KMS), or
they're still experimental (see i915tool - it's an attempt to create a
coreboot-level driver from KMS sources).

This means that for a "generic" box you're still bound to the VGABIOS to
some degree (you can't rely on KMS being available in the OS when using
a bootloader menu).


The other aspect is that you generally have an embedded controller on
notebooks (in addition to the management engine on newer Intel
chipsets). It usually runs its own firmware, which is also not availabe
in source form. If you're lucky, it's part of the EC chip as read-only
memory - in this case, you can safely consider it part of the hardware
(even under FSF's strict definition, as far as I understand it).


Regards,
Patrick

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From gerrit at coreboot.org  Mon Jun  4 16:19:47 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Mon, 4 Jun 2012 16:19:47 +0200
Subject: [coreboot] Patch merged into coreboot/master: a786a68 Improve
	parsing of --cpu parameter in abuild script.
References: <I96236ef719a1a9f942b8e15bfcf015d60068e58a+0@gerrit.coreboot.org>
Message-ID: <E1SbY8J-0004X8-JY@ra.coresystems.de>

the following patch was just integrated into master:
commit a786a680476fd605f78b11ff60cd074d03f2b57f
Author: Raymond Danks <ray.danks at se-eng.com>
Date:   Wed May 30 16:03:48 2012 -0600

    Improve parsing of --cpu parameter in abuild script.
    
    * -c "" need never be tested if getopt params are handled; fail abuild script when getopt parsing fails
    * use expr to resolve numeric test fails with -c max
    * cpus variable may be being passed in the environment.  Don't overwrite MAKEFLAGS if it is not.
    
    Change-Id: I96236ef719a1a9f942b8e15bfcf015d60068e58a
    Signed-off-by: Raymond Danks <ray.danks at se-eng.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Mon Jun  4 16:19:34 2012, giving +2
See http://review.coreboot.org/1068 for details.

-gerrit



From rminnich at gmail.com  Mon Jun  4 17:45:28 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Jun 2012 08:45:28 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338824583.6720.66.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
Message-ID: <CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>

On Mon, Jun 4, 2012 at 8:43 AM, Bob Ham <rah at settrans.net> wrote:

> This doesn't really answer Gary's question. ?I would like to build a
> silent PC for music production. ?The chromebox is not an option as
> firstly, it has a fan inside and secondly, it has no PCI slots for my
> sound cards.


I did not see those requirements in Gary's note, just in your note; on
rereading his note, they did not appear :-)

For you, no, it won't work. For his case, I guess Gary can tell us.

what kind of pci slots do your sound cards need?

ron



From rah at settrans.net  Mon Jun  4 18:10:43 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 17:10:43 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
Message-ID: <1338826243.6720.81.camel@myrtle.6gnip.net>

On Mon, 2012-06-04 at 08:45 -0700, ron minnich wrote:

> what kind of pci slots do your sound cards need?

Not PCI-E or PCI-X, just normal PCI.

-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }
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From rminnich at gmail.com  Mon Jun  4 18:15:29 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Jun 2012 09:15:29 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338826243.6720.81.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
Message-ID: <CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>

On Mon, Jun 4, 2012 at 9:10 AM, Bob Ham <rah at settrans.net> wrote:

> Not PCI-E or PCI-X, just normal PCI.

Wow. More than one? How many?

ron



From rah at settrans.net  Mon Jun  4 17:43:03 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 16:43:03 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
Message-ID: <1338824583.6720.66.camel@myrtle.6gnip.net>

On Sun, 2012-06-03 at 12:27 -0700, ron minnich wrote:
> Get a chromebox. It's quite well supported and it's a very fine machine.

This doesn't really answer Gary's question.  I would like to build a
silent PC for music production.  The chromebox is not an option as
firstly, it has a fan inside and secondly, it has no PCI slots for my
sound cards.

-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }
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From rah at settrans.net  Mon Jun  4 18:29:23 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 17:29:23 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
Message-ID: <1338827363.6720.86.camel@myrtle.6gnip.net>

On Mon, 2012-06-04 at 09:15 -0700, ron minnich wrote:
> On Mon, Jun 4, 2012 at 9:10 AM, Bob Ham <rah at settrans.net> wrote:
> 
> > Not PCI-E or PCI-X, just normal PCI.
> 
> Wow. More than one? How many?

Two; I have two identical M-Audio Delta 1010s.

-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }

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From rah at settrans.net  Mon Jun  4 19:15:18 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 18:15:18 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <20120604170104.GA24923@countzero.vandewege.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
	<20120604170104.GA24923@countzero.vandewege.net>
Message-ID: <1338830118.6720.97.camel@myrtle.6gnip.net>

On Mon, 2012-06-04 at 13:01 -0400, Ward Vandewege wrote:
> On Mon, Jun 04, 2012 at 05:29:23PM +0100, Bob Ham wrote:
> > On Mon, 2012-06-04 at 09:15 -0700, ron minnich wrote:
> > > On Mon, Jun 4, 2012 at 9:10 AM, Bob Ham <rah at settrans.net> wrote:
> > > 
> > > > Not PCI-E or PCI-X, just normal PCI.
> > > 
> > > Wow. More than one? How many?
> > 
> > Two; I have two identical M-Audio Delta 1010s.
> 
> Finding a modern board with two 'old' PCI slots may be difficult, regardless
> of coreboot... Have you seen any at all?

There are loads of new boards with at least two PCI slots; I've seen
many.

-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }
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From rminnich at gmail.com  Mon Jun  4 19:22:12 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Jun 2012 10:22:12 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338830118.6720.97.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
	<20120604170104.GA24923@countzero.vandewege.net>
	<1338830118.6720.97.camel@myrtle.6gnip.net>
Message-ID: <CAP6exYJ+PzSnK1hHwVnYh7b1ZUYK8JEqHaxEXojbuvKRSQrc5g@mail.gmail.com>

On Mon, Jun 4, 2012 at 10:15 AM, Bob Ham <rah at settrans.net> wrote:

> There are loads of new boards with at least two PCI slots; I've seen
> many.

got some pointers? In my world PCI has been an endangered species for years.

ron



From rah at settrans.net  Mon Jun  4 19:32:01 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 18:32:01 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAP6exYJ+PzSnK1hHwVnYh7b1ZUYK8JEqHaxEXojbuvKRSQrc5g@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
	<20120604170104.GA24923@countzero.vandewege.net>
	<1338830118.6720.97.camel@myrtle.6gnip.net>
	<CAP6exYJ+PzSnK1hHwVnYh7b1ZUYK8JEqHaxEXojbuvKRSQrc5g@mail.gmail.com>
Message-ID: <1338831121.6720.100.camel@myrtle.6gnip.net>

On Mon, 2012-06-04 at 10:22 -0700, ron minnich wrote:
> On Mon, Jun 4, 2012 at 10:15 AM, Bob Ham <rah at settrans.net> wrote:
> 
> > There are loads of new boards with at least two PCI slots; I've seen
> > many.
> 
> got some pointers? In my world PCI has been an endangered species for years.

http://www.scan.co.uk/products/gigabyte-ga-990xa-ud3-amd-990x-s-am3plus-ddr3-sata-iii-6gb-s-raid-sata-pcie-20-%28x16%29-atx
http://www.scan.co.uk/products/asus-m5a97-pro-amd-970-s-am3plus-ddr3-sata-iii-6gb-s-raid-sata-pcie-20-%28x16%29-atx
http://www.scan.co.uk/products/gigabyte-ga-970a-ds3-amd-970-s-am3plus-ddr3-sata-iii-6gb-s-sata-raid-pcie-20-%28x16%29-atx
http://www.scan.co.uk/products/msi-760gm-e51-%28fx%29-am3plus-cpu-amd-760g-plus-sb710-16gb-max-1xpcix16-1xpcix1-2-pci-dviplusvgaplushdm
http://www.scan.co.uk/products/asus-m5a78l-amd-760g-s-am3plus-ddr3-sata-ii-3gb-s-raid-sata-pcie-20-%28x16%29-atx
http://www.scan.co.uk/products/asus-e35m1-m-amd-hudson-m1-amd-e-350-dual-core-cpu-pci-e-20-%28x16%29-ddr3-1066-sata-6gb-s-matx


-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }
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From rminnich at gmail.com  Mon Jun  4 19:35:18 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Jun 2012 10:35:18 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338831121.6720.100.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
	<20120604170104.GA24923@countzero.vandewege.net>
	<1338830118.6720.97.camel@myrtle.6gnip.net>
	<CAP6exYJ+PzSnK1hHwVnYh7b1ZUYK8JEqHaxEXojbuvKRSQrc5g@mail.gmail.com>
	<1338831121.6720.100.camel@myrtle.6gnip.net>
Message-ID: <CAP6exYKmkPYfa=6f_Eki13dpkYxxEi9QctMJVvCYezOhRA9OWw@mail.gmail.com>

so that answers your question, I guess: match the chipsets on those
boards up, see what kind of flash, etc. and you maybe one will work?

ron



From rah at settrans.net  Mon Jun  4 20:26:19 2012
From: rah at settrans.net (Bob Ham)
Date: Mon, 04 Jun 2012 19:26:19 +0100
Subject: [coreboot] New Motherboards?
In-Reply-To: <CAP6exYKmkPYfa=6f_Eki13dpkYxxEi9QctMJVvCYezOhRA9OWw@mail.gmail.com>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
	<20120604170104.GA24923@countzero.vandewege.net>
	<1338830118.6720.97.camel@myrtle.6gnip.net>
	<CAP6exYJ+PzSnK1hHwVnYh7b1ZUYK8JEqHaxEXojbuvKRSQrc5g@mail.gmail.com>
	<1338831121.6720.100.camel@myrtle.6gnip.net>
	<CAP6exYKmkPYfa=6f_Eki13dpkYxxEi9QctMJVvCYezOhRA9OWw@mail.gmail.com>
Message-ID: <1338834379.6720.145.camel@myrtle.6gnip.net>

On Mon, 2012-06-04 at 10:35 -0700, ron minnich wrote:
> so that answers your question, I guess: match the chipsets on those
> boards up, see what kind of flash, etc. and you maybe one will work?

You've used the phrase "match the chipsets" but haven't said what to
match them up to.  Presumably you're referring to the "Supported
Chipsets and Devices" page on the wiki.  Unfortunately this page isn't
much use because information on what kind of flash, etc. a motherboard
has, isn't usually published.

The answer to Gary's question, "are there any new motherboards that are
fully supported?", has value beyond just mine and Gary's use cases.
Though it sounds like the answer is: you don't know.

-- 
Bob Ham <rah at settrans.net>

for (;;) { ++pancakes; }
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From rminnich at gmail.com  Mon Jun  4 22:04:05 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 4 Jun 2012 13:04:05 -0700
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338834379.6720.145.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
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	<1338831121.6720.100.camel@myrtle.6gnip.net>
	<CAP6exYKmkPYfa=6f_Eki13dpkYxxEi9QctMJVvCYezOhRA9OWw@mail.gmail.com>
	<1338834379.6720.145.camel@myrtle.6gnip.net>
Message-ID: <CAP6exYL3ps4YaNZ8s0xz-QQfSYYxurYfemaDb6aWhNxuq2G_ZQ@mail.gmail.com>

On Mon, Jun 4, 2012 at 11:26 AM, Bob Ham <rah at settrans.net> wrote:

> Though it sounds like the answer is: you don't know.

I know about some. It is not possible to know about all. In general,
it's not possible to know *even if you have a part number* because
vendors change things on these boards all the time without changing
the board number. I've bought boards in the past that were supported
and a the board arrives and it has enough changes to qualify as a new
board -- and the original part number.

In general, the best bet is to buy a board which has vendor-supported
coreboot -- such as the chromebox.

ron



From gerrit at coreboot.org  Tue Jun  5 01:02:24 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:24 +0200
Subject: [coreboot] New patch to review for coreboot: 0672250 userspace
	coreboot support
References: <Iaeef5c159a1e8871ea24f57b4fd161f979a4ed77+0@gerrit.coreboot.org>
Message-ID: <Iaeef5c159a1e8871ea24f57b4fd161f979a4ed77+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1089

-gerrit

commit 0672250797641683cab727784362d1d4be9ffb28
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:15:56 2012 +0200

    userspace coreboot support
    
    Add the basic linux userspace support. Avoid the priviledge ops
    and map low mem area to 64KB (which is normally mappable)
    Provide the linux sycall & console.
    
    Change-Id: Iaeef5c159a1e8871ea24f57b4fd161f979a4ed77
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/Kconfig                    |   20 ++++
 src/arch/x86/boot/gdt.c        |    5 +-
 src/arch/x86/boot/tables.c     |    6 +
 src/arch/x86/include/arch/io.h |   76 ++++++++++++++
 src/arch/x86/lib/c_start.S     |   36 ++++++-
 src/arch/x86/lib/ebda.c        |    3 +
 src/boot/hardwaremain.c        |   11 ++
 src/console/Makefile.inc       |    1 +
 src/console/ulinux_console.c   |   18 ++++
 src/include/cpu/x86/lapic.h    |   12 ++
 src/include/termios.h          |  219 ++++++++++++++++++++++++++++++++++++++++
 src/include/ulinux.h           |   36 +++++++
 src/lib/Makefile.inc           |    3 +
 src/lib/ulinux.c               |  160 +++++++++++++++++++++++++++++
 14 files changed, 602 insertions(+), 4 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index a5a0f00..21efe56 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -193,6 +193,26 @@ config REQUIRES_BLOB
 	  coreboot build for such a board can override this manually, but
 	  this option serves as warning that it might fail.
 
+config ULINUX
+	bool "Compile and run coreboot as Linux userspace process"
+	default n
+	help
+	  This option enables to run coreboot as Linux process which
+	  communicates with hardware using SerialICE.
+
+config ULINUX_VALGRIND
+	bool "Add valgrind instrumentation"
+	default n
+	depends on ULINUX
+	help
+	  This option enables to track heap using valgrind.
+
+config SERIALICE_HOST_DEV
+	string "SerialICE host device"
+	default "/dev/ttyUSB0"
+	depends on ULINUX
+	help
+	  Selects the serial port to which is connected your remote target.
 endmenu
 
 source src/mainboard/Kconfig
diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c
index b425ade..407cfe2 100644
--- a/src/arch/x86/boot/gdt.c
+++ b/src/arch/x86/boot/gdt.c
@@ -38,7 +38,9 @@ void move_gdt(void)
 {
 	void *newgdt;
 	u16 num_gdt_bytes = &gdt_end - &gdt;
+#if CONFIG_ULINUX == 0
 	struct gdtarg gdtarg;
+#endif
 
 	newgdt = cbmem_find(CBMEM_ID_GDT);
 	if (!newgdt) {
@@ -50,11 +52,12 @@ void move_gdt(void)
 		printk(BIOS_DEBUG, "Moving GDT to %p...", newgdt);
 		memcpy((void*)newgdt, &gdt, num_gdt_bytes);
 	}
-
+#if CONFIG_ULINUX == 0
 	gdtarg.base = (u32)newgdt;
 	gdtarg.limit = num_gdt_bytes - 1;
 
 	__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
+#endif
 	printk(BIOS_DEBUG, "ok\n");
 }
 
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 72aa979..456f161 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -32,6 +32,7 @@
 #include <cbmem.h>
 #include <lib.h>
 #include <smbios.h>
+#include <ulinux.h>
 
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
@@ -69,7 +70,12 @@ struct lb_memory *write_tables(void)
 	 * and the coreboot table use low_tables.
 	 */
 	low_table_start = 0;
+#if CONFIG_ULINUX
+	low_table_end = 0x10000;
+	ulinux_mmap(low_table_end, 0x1000);
+#else
 	low_table_end = 0x500;
+#endif
 
 #if CONFIG_GENERATE_PIRQ_TABLE
 #define MAX_PIRQ_TABLE_SIZE (4 * 1024)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index f4c6967..88338e1 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -9,6 +9,7 @@
  * (insb/insw/insl/outsb/outsw/outsl).
  */
 #if defined(__ROMCC__)
+
 static inline void outb(uint8_t value, uint16_t port)
 {
 	__builtin_outb(value, port);
@@ -41,6 +42,9 @@ static inline uint32_t inl(uint16_t port)
 	return __builtin_inl(port);
 }
 #else
+
+#if defined(__PRE_RAM__) || defined(__SMM__) || CONFIG_ULINUX == 0
+
 static inline void outb(uint8_t value, uint16_t port)
 {
 	__asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
@@ -76,6 +80,43 @@ static inline uint32_t inl(uint16_t port)
 	__asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
 	return value;
 }
+
+#else /* CONFIG_ULINUX == 1 */
+
+#include <console/console.h>
+#include <serialice_host.h>
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+	serialice_outb(value, port);
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+	serialice_outw(value, port);
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+	serialice_outl(value, port);
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+	return serialice_inb(port);
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+	return serialice_inw(port);
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+	return serialice_inl(port);
+}
+
+#endif /* CONFIG_ULINUX */
 #endif /* __ROMCC__ */
 
 static inline void outsb(uint16_t port, const void *addr, unsigned long count)
@@ -133,6 +174,9 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
 		);
 }
 
+
+#if defined(__PRE_RAM__) || defined(__SMM__) || CONFIG_ULINUX == 0
+
 static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
 {
 	return *((volatile uint8_t *)(addr));
@@ -163,5 +207,37 @@ static inline __attribute__((always_inline)) void write32(unsigned long addr, ui
 	*((volatile uint32_t *)(addr)) = value;
 }
 
+#else /* CONFIG_ULINUX */
+
+static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+{
+	return serialice_readb(addr);
+}
+
+static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
+{
+	return serialice_readw(addr);
+}
+
+static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
+{
+	return serialice_readl(addr);
+}
+
+static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
+{
+	serialice_writeb(value, addr);
+}
+
+static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
+{
+	serialice_writew(value, addr);
+}
+
+static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
+{
+	serialice_writel(value, addr);
+}
+#endif
 #endif
 
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 005ac33..e5ea273 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -4,6 +4,8 @@
 	.code32
 	.globl _start
 _start:
+
+#if CONFIG_ULINUX == 0
 	cli
 	lgdt	%cs:gdtaddr
 	ljmp	$0x10, $1f
@@ -13,8 +15,8 @@ _start:
 	movl	%eax, %ss
 	movl	%eax, %fs
 	movl	%eax, %gs
-
 	post_code(POST_ENTRY_C_START)		/* post 13 */
+#endif
 
 	/** clear stack */
 	cld
@@ -49,7 +51,7 @@ _start:
 
 	/* Save the stack location */
 	movl	%esp, %ebp
-
+#if CONFIG_ULINUX == 0
 	/* Initialize the Interrupt Descriptor table */
 	leal	_idt, %edi
 	leal	vec0, %ebx
@@ -67,13 +69,13 @@ _start:
 
 	/* Load the Interrupt descriptor table */
 	lidt	idtarg
-
 	/*
 	 *	Now we are finished. Memory is up, data is copied and
 	 *	bss is cleared.   Now we call the main routine and
 	 *	let it do the rest.
 	 */
 	post_code(POST_PRE_HARDWAREMAIN)	/* post fe */
+#endif
 
 	/* Restore the stack location */
 	movl	%ebp, %esp
@@ -315,3 +317,31 @@ _idt_end:
 
 	.previous
 .code32
+
+#if CONFIG_ULINUX
+	.globl _call_linux
+	/* be paranoid of what registers to preserve for GCC */
+_call_linux:
+	pushl	%ebp
+	movl	%esp, %ebp
+	push	%ebx
+	push	%ecx
+	push	%edx
+	push	%esi
+	push	%edi
+	movl	0x8(%ebp), %eax
+	movl	0xc(%ebp), %ebx
+	movl	0x10(%ebp), %ecx
+	movl	0x14(%ebp), %edx
+	movl	0x18(%ebp), %esi
+	movl	0x1c(%ebp), %edi
+	movl	0x20(%ebp), %ebp
+	int	$0x80
+	popl	%edi
+	popl	%esi
+	popl	%edx
+	popl	%ecx
+	popl	%ebx
+	popl	%ebp
+	ret
+#endif
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index fb407b6..1a1d16d 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -35,6 +35,9 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 		return;
 #endif
 
+#if CONFIG_ULINUX
+	return;
+#endif
 	if (!low_memory_size || !ebda_segment || !ebda_size)
 		return;
 
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index d78b859..d244d8d 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -35,6 +35,9 @@ it with the version available from LANL.
 #include <boot/tables.h>
 #include <boot/elf.h>
 #include <cbfs.h>
+#if CONFIG_ULINUX
+#include <ulinux.h>
+#endif
 #if CONFIG_HAVE_ACPI_RESUME
 #include <arch/acpi.h>
 #endif
@@ -63,6 +66,10 @@ void hardwaremain(int boot_complete)
 #endif
 	post_code(POST_ENTRY_RAMSTAGE);
 
+#if CONFIG_ULINUX
+	ulinux_init();
+#endif
+
 	/* console_init() MUST PRECEDE ALL printk()! */
 	console_init();
 
@@ -143,6 +150,10 @@ void hardwaremain(int boot_complete)
 	lb_mem = write_tables();
 
 	timestamp_add_now(TS_LOAD_PAYLOAD);
+#if CONFIG_ULINUX
+	printk(BIOS_INFO, "All done, exiting\n");
+	ulinux_exit(0);
+#endif
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index f3b8758..afde535 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -19,6 +19,7 @@ driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
 driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+driver-$(CONFIG_ULINUX) += ulinux_console.c
 
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
diff --git a/src/console/ulinux_console.c b/src/console/ulinux_console.c
new file mode 100644
index 0000000..4a5dd47
--- /dev/null
+++ b/src/console/ulinux_console.c
@@ -0,0 +1,18 @@
+#include <console/console.h>
+#include <ulinux.h>
+
+static void linux_tx_byte(unsigned char byte)
+{
+	unsigned char c;
+	c = byte;
+
+	ulinux_write(1, &c, 1);
+}
+
+
+static const struct console_driver linux_console __console = {
+	.init    = 0,
+	.tx_byte = linux_tx_byte,
+	.rx_byte = 0,
+	.tst_byte = 0,
+};
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 078f2a7..7efeb45 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -5,6 +5,10 @@
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
 
+#if !defined(__PRE_RAM__)
+#include <serialice_host.h>
+#endif
+
 /* See if I need to initialize the local apic */
 #if CONFIG_SMP || CONFIG_IOAPIC
 #  define NEED_LAPIC 1
@@ -14,12 +18,20 @@
 
 static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
 {
+#if defined(__PRE_RAM__)
 	return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
+#else
+	return serialice_readl((LAPIC_DEFAULT_BASE+reg));
+#endif
 }
 
 static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
 {
+#if defined(__PRE_RAM__)
 	*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
+#else
+	serialice_writel(v, LAPIC_DEFAULT_BASE+reg);
+#endif
 }
 
 static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
diff --git a/src/include/termios.h b/src/include/termios.h
new file mode 100644
index 0000000..5133e6b
--- /dev/null
+++ b/src/include/termios.h
@@ -0,0 +1,219 @@
+/* termios type and macro definitions.  Linux version.
+   Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2003, 2005
+	Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Lesser General Public
+   License as published by the Free Software Foundation; either
+   version 2.1 of the License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Lesser General Public License for more details.
+
+   You should have received a copy of the GNU Lesser General Public
+   License along with the GNU C Library; if not, write to the Free
+   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+   02111-1307 USA.  */
+
+#ifndef _TERMIOS_H
+///# error "Never include <bits/termios.h> directly; use <termios.h> instead."
+#define _TERMIOS_H
+
+typedef unsigned char	cc_t;
+typedef unsigned int	speed_t;
+typedef unsigned int	tcflag_t;
+
+#define NCCS 32
+struct termios
+  {
+    tcflag_t c_iflag;		/* input mode flags */
+    tcflag_t c_oflag;		/* output mode flags */
+    tcflag_t c_cflag;		/* control mode flags */
+    tcflag_t c_lflag;		/* local mode flags */
+    cc_t c_line;			/* line discipline */
+    cc_t c_cc[NCCS];		/* control characters */
+    speed_t c_ispeed;		/* input speed */
+    speed_t c_ospeed;		/* output speed */
+#define _HAVE_STRUCT_TERMIOS_C_ISPEED 1
+#define _HAVE_STRUCT_TERMIOS_C_OSPEED 1
+  };
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK	0000001
+#define BRKINT	0000002
+#define IGNPAR	0000004
+#define PARMRK	0000010
+#define INPCK	0000020
+#define ISTRIP	0000040
+#define INLCR	0000100
+#define IGNCR	0000200
+#define ICRNL	0000400
+#define IUCLC	0001000
+#define IXON	0002000
+#define IXANY	0004000
+#define IXOFF	0010000
+#define IMAXBEL	0020000
+#define IUTF8	0040000
+
+/* c_oflag bits */
+#define OPOST	0000001
+#define OLCUC	0000002
+#define ONLCR	0000004
+#define OCRNL	0000010
+#define ONOCR	0000020
+#define ONLRET	0000040
+#define OFILL	0000100
+#define OFDEL	0000200
+#if defined __USE_MISC || defined __USE_XOPEN
+# define NLDLY	0000400
+# define   NL0	0000000
+# define   NL1	0000400
+# define CRDLY	0003000
+# define   CR0	0000000
+# define   CR1	0001000
+# define   CR2	0002000
+# define   CR3	0003000
+# define TABDLY	0014000
+# define   TAB0	0000000
+# define   TAB1	0004000
+# define   TAB2	0010000
+# define   TAB3	0014000
+# define BSDLY	0020000
+# define   BS0	0000000
+# define   BS1	0020000
+# define FFDLY	0100000
+# define   FF0	0000000
+# define   FF1	0100000
+#endif
+
+#define VTDLY	0040000
+#define   VT0	0000000
+#define   VT1	0040000
+
+#ifdef __USE_MISC
+# define XTABS	0014000
+#endif
+
+/* c_cflag bit meaning */
+#ifdef __USE_MISC
+# define CBAUD	0010017
+#endif
+#define  B0	0000000		/* hang up */
+#define  B50	0000001
+#define  B75	0000002
+#define  B110	0000003
+#define  B134	0000004
+#define  B150	0000005
+#define  B200	0000006
+#define  B300	0000007
+#define  B600	0000010
+#define  B1200	0000011
+#define  B1800	0000012
+#define  B2400	0000013
+#define  B4800	0000014
+#define  B9600	0000015
+#define  B19200	0000016
+#define  B38400	0000017
+#ifdef __USE_MISC
+# define EXTA B19200
+# define EXTB B38400
+#endif
+#define CSIZE	0000060
+#define   CS5	0000000
+#define   CS6	0000020
+#define   CS7	0000040
+#define   CS8	0000060
+#define CSTOPB	0000100
+#define CREAD	0000200
+#define PARENB	0000400
+#define PARODD	0001000
+#define HUPCL	0002000
+#define CLOCAL	0004000
+#ifdef __USE_MISC
+# define CBAUDEX 0010000
+#endif
+#define  B57600   0010001
+#define  B115200  0010002
+#define  B230400  0010003
+#define  B460800  0010004
+#define  B500000  0010005
+#define  B576000  0010006
+#define  B921600  0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define __MAX_BAUD B4000000
+#ifdef __USE_MISC
+# define CIBAUD	  002003600000		/* input baud rate (not used) */
+# define CMSPAR   010000000000		/* mark or space (stick) parity */
+# define CRTSCTS  020000000000		/* flow control */
+#endif
+
+/* c_lflag bits */
+#define ISIG	0000001
+#define ICANON	0000002
+#if defined __USE_MISC || defined __USE_XOPEN
+# define XCASE	0000004
+#endif
+#define ECHO	0000010
+#define ECHOE	0000020
+#define ECHOK	0000040
+#define ECHONL	0000100
+#define NOFLSH	0000200
+#define TOSTOP	0000400
+#ifdef __USE_MISC
+# define ECHOCTL 0001000
+# define ECHOPRT 0002000
+# define ECHOKE	 0004000
+# define FLUSHO	 0010000
+# define PENDIN	 0040000
+#endif
+#define IEXTEN	0100000
+
+/* tcflow() and TCXONC use these */
+#define	TCOOFF		0
+#define	TCOON		1
+#define	TCIOFF		2
+#define	TCION		3
+
+/* tcflush() and TCFLSH use these */
+#define	TCIFLUSH	0
+#define	TCOFLUSH	1
+#define	TCIOFLUSH	2
+
+/* tcsetattr uses these */
+#define	TCSANOW		0
+#define	TCSADRAIN	1
+#define	TCSAFLUSH	2
+
+
+#define _IOT_termios /* Hurd ioctl type field.  */ \
+  _IOT (_IOTS (cflag_t), 4, _IOTS (cc_t), NCCS, _IOTS (speed_t), 2)
+#endif
diff --git a/src/include/ulinux.h b/src/include/ulinux.h
new file mode 100644
index 0000000..e0408ad
--- /dev/null
+++ b/src/include/ulinux.h
@@ -0,0 +1,36 @@
+#include <stdint.h>
+#include <termios.h>
+extern  int _call_linux(uint32_t a0, uint32_t a1, uint32_t a2, uint32_t a3, uint32_t a4, uint32_t a5, uint32_t a6);
+
+void __stack_chk_init(void);
+void *ulinux_mmap(unsigned long addr, unsigned int length);
+int ulinux_write(int fd, const void *buf, unsigned int count);
+int ulinux_close(int fd);
+int ulinux_read(int fd, void *buf, unsigned int count);
+int ulinux_open(const char *pathname, int flags);
+
+#define EINTR 4
+extern int ulinux_errno;
+
+#define O_RDWR		00000002
+#define O_NOCTTY	   0400	/* not fcntl */
+#define O_NONBLOCK	  04000
+#define O_NDELAY	O_NONBLOCK
+#define F_SETFL		4	/* Set file status flags.  */
+#define EOF -1
+
+#define perror(x) printk(BIOS_ERR, x)
+
+int ulinux_ioctl(int d, int request);
+
+int ulinux_tcgetattr(int fd, struct termios *termios_p);
+int ulinux_cfsetispeed(struct termios *termios_p, speed_t speed);
+int ulinux_cfsetospeed(struct termios *termios_p, speed_t speed);
+int ulinux_tcsetattr(int fd, int optional_actions,
+                     const struct termios *termios_p);
+void ulinux_exit(int status);
+int ulinux_fcntl(int fd, int cmd, int a);
+int ulinux_tcflush(int fd, int queue_selector);
+void ulinux_init(void);
+
+#define TIOCEXCL        0x540C
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 7c081ac..3bd7f99 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -42,6 +42,9 @@ ramstage-y += lzma.c
 ramstage-y += gcc.c
 ramstage-y += clog2.c
 ramstage-y += cbmem.c
+ramstage-$(CONFIG_ULINUX) += ulinux.c
+ramstage-$(CONFIG_ULINUX) += serialice_host.c
+
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
diff --git a/src/lib/ulinux.c b/src/lib/ulinux.c
new file mode 100644
index 0000000..a9c0431
--- /dev/null
+++ b/src/lib/ulinux.c
@@ -0,0 +1,160 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <console/console.h>
+#include <serialice_host.h>
+#include <ulinux.h>
+
+#if CONFIG_ULINUX_VALGRIND
+#include "valgrind.h"
+#include "memcheck.h"
+extern unsigned char _heap, _eheap;
+#endif
+
+#define NR_EXIT 1
+#define NR_MMAP 192
+#define NR_READ 3
+#define NR_WRITE 4
+#define NR_OPEN 5
+#define NR_CLOSE 6
+#define NR_IOCTL 54
+#define NR_FCNTL 55
+
+#define TCGETS 0x5401
+#define TCSETS 0x5402
+#define TCFLSH 0x540b
+
+int ulinux_errno;
+
+
+unsigned long __stack_chk_guard = 0xdeadbeef;
+
+void __stack_chk_init(void)
+{
+}
+
+void __stack_chk_fail(void);
+
+void __attribute__ ((noreturn)) __stack_chk_fail(void)
+{
+	die("Stack SMASHED\n");
+}
+
+void ulinux_init(void)
+{
+	/* Map last 64KB of 1MB */
+	ulinux_mmap((960 * 1024), 64 * 1024);
+
+#if CONFIG_ULINUX_VALGRIND
+	VALGRIND_CREATE_MEMPOOL(&_heap, 8, 0);
+	VALGRIND_MAKE_MEM_NOACCESS(&_heap,  &_eheap - &_heap);
+#endif
+
+//	serialice_init();
+
+}
+
+void *ulinux_mmap(unsigned long addr, unsigned int size)
+{
+	return (void *) _call_linux(NR_MMAP, (uint32_t) addr, size,
+				    (uint32_t) 3, 0x32, -1, 0);
+}
+
+int ulinux_write(int fd, const void *buf, unsigned int count)
+{
+	return _call_linux(NR_WRITE, (uint32_t) fd, (uint32_t) buf,
+			   (uint32_t) count, 0, 0, 0);
+}
+
+int ulinux_close(int fd)
+{
+	return _call_linux(NR_CLOSE, (uint32_t) fd, 0, 0, 0, 0, 0);
+}
+
+int ulinux_read(int fd, void *buf, unsigned int count)
+{
+	int ret =
+	    _call_linux(NR_READ, (uint32_t) fd, (uint32_t) buf,
+			(uint32_t) count,
+			0, 0, 0);
+	ulinux_errno = (ret < 0) ? -ret : 0;
+	return ret;
+}
+
+
+int ulinux_open(const char *pathname, int flags)
+{
+	return _call_linux(NR_OPEN, (uint32_t) pathname, (uint32_t) flags,
+			   (uint32_t) 0, 0, 0, 0);
+
+}
+
+
+int ulinux_ioctl(int fd, int request)
+{
+	return _call_linux(NR_IOCTL, (uint32_t) fd, (uint32_t) request,
+			   (uint32_t) 0, 0, 0, 0);
+}
+
+int ulinux_tcgetattr(int fd, struct termios *termios_p)
+{
+	return _call_linux(NR_IOCTL, (uint32_t) fd, TCGETS,
+			   (uint32_t) termios_p, 0, 0, 0);
+}
+
+
+int ulinux_cfsetispeed(struct termios *termios_p, speed_t speed)
+{
+	termios_p->c_ispeed = speed;
+	return 0;
+}
+
+int ulinux_cfsetospeed(struct termios *termios_p, speed_t speed)
+{
+	termios_p->c_ospeed = speed;
+	return 0;
+}
+
+int ulinux_tcsetattr(int fd, int optional_actions,
+		     const struct termios *termios_p)
+{
+	return _call_linux(NR_IOCTL, (uint32_t) fd, TCSETS,
+			   (uint32_t) termios_p,
+			   (uint32_t) optional_actions, 0, 0);
+
+}
+
+void ulinux_exit(int status)
+{
+	_call_linux(NR_EXIT, status, 0, 0, 0, 0, 0);
+}
+
+int ulinux_fcntl(int fd, int cmd, int a)
+{
+	return _call_linux(NR_FCNTL, (uint32_t) fd, (uint32_t) cmd,
+			   (uint32_t) a, 0, 0, 0);
+}
+
+int ulinux_tcflush(int fd, int queue_selector)
+{
+	return _call_linux(NR_IOCTL, (uint32_t) fd, TCFLSH,
+			   (uint32_t) queue_selector, 0, 0, 0);
+
+}



From gerrit at coreboot.org  Tue Jun  5 01:02:25 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:25 +0200
Subject: [coreboot] New patch to review for coreboot: c804366 Do not use
	CBFS while in userspace coreboot, fake 64KB chip.
References: <I3cf7e8504e216eef7f88e14a3a2906f91fe3abb4+0@gerrit.coreboot.org>
Message-ID: <I3cf7e8504e216eef7f88e14a3a2906f91fe3abb4+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1090

-gerrit

commit c804366903fb035c75a7d07fa72874a6e1c27a29
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:18:37 2012 +0200

    Do not use CBFS while in userspace coreboot, fake 64KB chip.
    
    Avoid CBFS, it could be mmaped as file in the future.
    
    Change-Id: I3cf7e8504e216eef7f88e14a3a2906f91fe3abb4
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/arch/x86/boot/smbios.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index f39bf04..78e4e04 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -142,8 +142,14 @@ static int smbios_write_type0(unsigned long *current, int handle)
 	vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
 #endif
 
+#if CONFIG_ULINUX
+	/* No CBFS mapped yet */
+	t->bios_rom_size = 64;
+	hdr = NULL;
+#else
 	if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff)
 		t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1;
+#endif
 	t->system_bios_major_release = 4;
 	t->bios_characteristics =
 		BIOS_CHARACTERISTICS_PCI_SUPPORTED |



From gerrit at coreboot.org  Tue Jun  5 01:02:26 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:26 +0200
Subject: [coreboot] New patch to review for coreboot: f6bf6c4 valgrind
	support for malloc()
References: <I4999b70e6617b5328792ddef5041800668dd2ae4+0@gerrit.coreboot.org>
Message-ID: <I4999b70e6617b5328792ddef5041800668dd2ae4+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1091

-gerrit

commit f6bf6c4303d62ae75098433a395b65c34d31aba3
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:21:10 2012 +0200

    valgrind support for malloc()
    
    Demo valgrind support, need some more work as the red zone regions overlap a bit
    but it is capable of reporting errors even now. This needs to be fixed...
    
    Change-Id: I4999b70e6617b5328792ddef5041800668dd2ae4
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/include/memcheck.h |  287 ++++
 src/include/valgrind.h | 4037 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/lib/malloc.c       |   10 +-
 3 files changed, 4331 insertions(+), 3 deletions(-)

diff --git a/src/include/memcheck.h b/src/include/memcheck.h
new file mode 100644
index 0000000..68474b4
--- /dev/null
+++ b/src/include/memcheck.h
@@ -0,0 +1,287 @@
+
+/*
+   ----------------------------------------------------------------
+
+   Notice that the following BSD-style license applies to this one
+   file (memcheck.h) only.  The rest of Valgrind is licensed under the
+   terms of the GNU General Public License, version 2, unless
+   otherwise indicated.  See the COPYING file in the source
+   distribution for details.
+
+   ----------------------------------------------------------------
+
+   This file is part of MemCheck, a heavyweight Valgrind tool for
+   detecting memory errors.
+
+   Copyright (C) 2000-2011 Julian Seward.  All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. The origin of this software must not be misrepresented; you must 
+      not claim that you wrote the original software.  If you use this 
+      software in a product, an acknowledgment in the product 
+      documentation would be appreciated but is not required.
+
+   3. Altered source versions must be plainly marked as such, and must
+      not be misrepresented as being the original software.
+
+   4. The name of the author may not be used to endorse or promote 
+      products derived from this software without specific prior written 
+      permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+   OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+   GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+   WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+   ----------------------------------------------------------------
+
+   Notice that the above BSD-style license applies to this one file
+   (memcheck.h) only.  The entire rest of Valgrind is licensed under
+   the terms of the GNU General Public License, version 2.  See the
+   COPYING file in the source distribution for details.
+
+   ---------------------------------------------------------------- 
+*/
+
+
+#ifndef __MEMCHECK_H
+#define __MEMCHECK_H
+
+
+/* This file is for inclusion into client (your!) code.
+
+   You can use these macros to manipulate and query memory permissions
+   inside your own programs.
+
+   See comment near the top of valgrind.h on how to use them.
+*/
+
+#include "valgrind.h"
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !! 
+   This enum comprises an ABI exported by Valgrind to programs
+   which use client requests.  DO NOT CHANGE THE ORDER OF THESE
+   ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+typedef
+   enum { 
+      VG_USERREQ__MAKE_MEM_NOACCESS = VG_USERREQ_TOOL_BASE('M','C'),
+      VG_USERREQ__MAKE_MEM_UNDEFINED,
+      VG_USERREQ__MAKE_MEM_DEFINED,
+      VG_USERREQ__DISCARD,
+      VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE,
+      VG_USERREQ__CHECK_MEM_IS_DEFINED,
+      VG_USERREQ__DO_LEAK_CHECK,
+      VG_USERREQ__COUNT_LEAKS,
+
+      VG_USERREQ__GET_VBITS,
+      VG_USERREQ__SET_VBITS,
+
+      VG_USERREQ__CREATE_BLOCK,
+
+      VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE,
+
+      /* Not next to VG_USERREQ__COUNT_LEAKS because it was added later. */
+      VG_USERREQ__COUNT_LEAK_BLOCKS,
+
+      /* This is just for memcheck's internal use - don't use it */
+      _VG_USERREQ__MEMCHECK_RECORD_OVERLAP_ERROR 
+         = VG_USERREQ_TOOL_BASE('M','C') + 256
+   } Vg_MemCheckClientRequest;
+
+
+
+/* Client-code macros to manipulate the state of memory. */
+
+/* Mark memory at _qzz_addr as unaddressable for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_NOACCESS(_qzz_addr,_qzz_len)           \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,      \
+                            VG_USERREQ__MAKE_MEM_NOACCESS,       \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+      
+/* Similarly, mark memory at _qzz_addr as addressable but undefined
+   for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_UNDEFINED(_qzz_addr,_qzz_len)          \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,      \
+                            VG_USERREQ__MAKE_MEM_UNDEFINED,      \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similarly, mark memory at _qzz_addr as addressable and defined
+   for _qzz_len bytes. */
+#define VALGRIND_MAKE_MEM_DEFINED(_qzz_addr,_qzz_len)            \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,      \
+                            VG_USERREQ__MAKE_MEM_DEFINED,        \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Similar to VALGRIND_MAKE_MEM_DEFINED except that addressability is
+   not altered: bytes which are addressable are marked as defined,
+   but those which are not addressable are left unchanged. */
+#define VALGRIND_MAKE_MEM_DEFINED_IF_ADDRESSABLE(_qzz_addr,_qzz_len)     \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,              \
+                            VG_USERREQ__MAKE_MEM_DEFINED_IF_ADDRESSABLE, \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Create a block-description handle.  The description is an ascii
+   string which is included in any messages pertaining to addresses
+   within the specified memory range.  Has no other effect on the
+   properties of the memory range. */
+#define VALGRIND_CREATE_BLOCK(_qzz_addr,_qzz_len, _qzz_desc)	   \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,        \
+                            VG_USERREQ__CREATE_BLOCK,              \
+                            (_qzz_addr), (_qzz_len), (_qzz_desc),  \
+                            0, 0)
+
+/* Discard a block-description-handle. Returns 1 for an
+   invalid handle, 0 for a valid handle. */
+#define VALGRIND_DISCARD(_qzz_blkindex)                          \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,      \
+                            VG_USERREQ__DISCARD,                 \
+                            0, (_qzz_blkindex), 0, 0, 0)
+
+
+/* Client-code macros to check the state of memory. */
+
+/* Check that memory at _qzz_addr is addressable for _qzz_len bytes.
+   If suitable addressibility is not established, Valgrind prints an
+   error message and returns the address of the first offending byte.
+   Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_ADDRESSABLE(_qzz_addr,_qzz_len)      \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                             \
+                            VG_USERREQ__CHECK_MEM_IS_ADDRESSABLE,  \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Check that memory at _qzz_addr is addressable and defined for
+   _qzz_len bytes.  If suitable addressibility and definedness are not
+   established, Valgrind prints an error message and returns the
+   address of the first offending byte.  Otherwise it returns zero. */
+#define VALGRIND_CHECK_MEM_IS_DEFINED(_qzz_addr,_qzz_len)        \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                           \
+                            VG_USERREQ__CHECK_MEM_IS_DEFINED,    \
+                            (_qzz_addr), (_qzz_len), 0, 0, 0)
+
+/* Use this macro to force the definedness and addressibility of an
+   lvalue to be checked.  If suitable addressibility and definedness
+   are not established, Valgrind prints an error message and returns
+   the address of the first offending byte.  Otherwise it returns
+   zero. */
+#define VALGRIND_CHECK_VALUE_IS_DEFINED(__lvalue)                \
+   VALGRIND_CHECK_MEM_IS_DEFINED(                                \
+      (volatile unsigned char *)&(__lvalue),                     \
+                      (unsigned long)(sizeof (__lvalue)))
+
+
+/* Do a full memory leak check (like --leak-check=full) mid-execution. */
+#define VALGRIND_DO_LEAK_CHECK                                   \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK,   \
+                                    0, 0, 0, 0, 0)
+
+/* Same as VALGRIND_DO_LEAK_CHECK but only showing the entries for
+   which there was an increase in leaked bytes or leaked nr of blocks
+   since the previous leak search. */
+#define VALGRIND_DO_ADDED_LEAK_CHECK                            \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK,  \
+                                    0, 1, 0, 0, 0)
+
+/* Same as VALGRIND_DO_ADDED_LEAK_CHECK but showing entries with
+   increased or decreased leaked bytes/blocks since previous leak
+   search. */
+#define VALGRIND_DO_CHANGED_LEAK_CHECK                          \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK,  \
+                                    0, 2, 0, 0, 0)
+
+/* Do a summary memory leak check (like --leak-check=summary) mid-execution. */
+#define VALGRIND_DO_QUICK_LEAK_CHECK                             \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DO_LEAK_CHECK,   \
+                                    1, 0, 0, 0, 0)
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+   all previous leak checks.  They must be lvalues.  */
+#define VALGRIND_COUNT_LEAKS(leaked, dubious, reachable, suppressed)     \
+   /* For safety on 64-bit platforms we assign the results to private
+      unsigned long variables, then assign these to the lvalues the user
+      specified, which works no matter what type 'leaked', 'dubious', etc
+      are.  We also initialise '_qzz_leaked', etc because
+      VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+      defined. */                                                        \
+   {                                                                     \
+    unsigned long _qzz_leaked    = 0, _qzz_dubious    = 0;               \
+    unsigned long _qzz_reachable = 0, _qzz_suppressed = 0;               \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(                                     \
+                               VG_USERREQ__COUNT_LEAKS,                  \
+                               &_qzz_leaked, &_qzz_dubious,              \
+                               &_qzz_reachable, &_qzz_suppressed, 0);    \
+    leaked     = _qzz_leaked;                                            \
+    dubious    = _qzz_dubious;                                           \
+    reachable  = _qzz_reachable;                                         \
+    suppressed = _qzz_suppressed;                                        \
+   }
+
+/* Return number of leaked, dubious, reachable and suppressed bytes found by
+   all previous leak checks.  They must be lvalues.  */
+#define VALGRIND_COUNT_LEAK_BLOCKS(leaked, dubious, reachable, suppressed) \
+   /* For safety on 64-bit platforms we assign the results to private
+      unsigned long variables, then assign these to the lvalues the user
+      specified, which works no matter what type 'leaked', 'dubious', etc
+      are.  We also initialise '_qzz_leaked', etc because
+      VG_USERREQ__COUNT_LEAKS doesn't mark the values returned as
+      defined. */                                                        \
+   {                                                                     \
+    unsigned long _qzz_leaked    = 0, _qzz_dubious    = 0;               \
+    unsigned long _qzz_reachable = 0, _qzz_suppressed = 0;               \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(                                     \
+                               VG_USERREQ__COUNT_LEAK_BLOCKS,            \
+                               &_qzz_leaked, &_qzz_dubious,              \
+                               &_qzz_reachable, &_qzz_suppressed, 0);    \
+    leaked     = _qzz_leaked;                                            \
+    dubious    = _qzz_dubious;                                           \
+    reachable  = _qzz_reachable;                                         \
+    suppressed = _qzz_suppressed;                                        \
+   }
+
+
+/* Get the validity data for addresses [zza..zza+zznbytes-1] and copy it
+   into the provided zzvbits array.  Return values:
+      0   if not running on valgrind
+      1   success
+      2   [previously indicated unaligned arrays;  these are now allowed]
+      3   if any parts of zzsrc/zzvbits are not addressable.
+   The metadata is not copied in cases 0, 2 or 3 so it should be
+   impossible to segfault your system by using this call.
+*/
+#define VALGRIND_GET_VBITS(zza,zzvbits,zznbytes)                \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                \
+                                    VG_USERREQ__GET_VBITS,      \
+                                    (const char*)(zza),         \
+                                    (char*)(zzvbits),           \
+                                    (zznbytes), 0, 0)
+
+/* Set the validity data for addresses [zza..zza+zznbytes-1], copying it
+   from the provided zzvbits array.  Return values:
+      0   if not running on valgrind
+      1   success
+      2   [previously indicated unaligned arrays;  these are now allowed]
+      3   if any parts of zza/zzvbits are not addressable.
+   The metadata is not copied in cases 0, 2 or 3 so it should be
+   impossible to segfault your system by using this call.
+*/
+#define VALGRIND_SET_VBITS(zza,zzvbits,zznbytes)                \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                \
+                                    VG_USERREQ__SET_VBITS,      \
+                                    (const char*)(zza),         \
+                                    (const char*)(zzvbits),     \
+                                    (zznbytes), 0, 0 )
+
+#endif
+
diff --git a/src/include/valgrind.h b/src/include/valgrind.h
new file mode 100644
index 0000000..ed53273
--- /dev/null
+++ b/src/include/valgrind.h
@@ -0,0 +1,4037 @@
+/* -*- c -*-
+   ----------------------------------------------------------------
+
+   Notice that the following BSD-style license applies to this one
+   file (valgrind.h) only.  The rest of Valgrind is licensed under the
+   terms of the GNU General Public License, version 2, unless
+   otherwise indicated.  See the COPYING file in the source
+   distribution for details.
+
+   ----------------------------------------------------------------
+
+   This file is part of Valgrind, a dynamic binary instrumentation
+   framework.
+
+   Copyright (C) 2000-2011 Julian Seward.  All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+
+   2. The origin of this software must not be misrepresented; you must 
+      not claim that you wrote the original software.  If you use this 
+      software in a product, an acknowledgment in the product 
+      documentation would be appreciated but is not required.
+
+   3. Altered source versions must be plainly marked as such, and must
+      not be misrepresented as being the original software.
+
+   4. The name of the author may not be used to endorse or promote 
+      products derived from this software without specific prior written 
+      permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
+   OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+   WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+   DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+   DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+   GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+   WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+   ----------------------------------------------------------------
+
+   Notice that the above BSD-style license applies to this one file
+   (valgrind.h) only.  The entire rest of Valgrind is licensed under
+   the terms of the GNU General Public License, version 2.  See the
+   COPYING file in the source distribution for details.
+
+   ---------------------------------------------------------------- 
+*/
+
+
+/* This file is for inclusion into client (your!) code.
+
+   You can use these macros to manipulate and query Valgrind's 
+   execution inside your own programs.
+
+   The resulting executables will still run without Valgrind, just a
+   little bit more slowly than they otherwise would, but otherwise
+   unchanged.  When not running on valgrind, each client request
+   consumes very few (eg. 7) instructions, so the resulting performance
+   loss is negligible unless you plan to execute client requests
+   millions of times per second.  Nevertheless, if that is still a
+   problem, you can compile with the NVALGRIND symbol defined (gcc
+   -DNVALGRIND) so that client requests are not even compiled in.  */
+
+#ifndef __VALGRIND_H
+#define __VALGRIND_H
+
+
+/* ------------------------------------------------------------------ */
+/* VERSION NUMBER OF VALGRIND                                         */
+/* ------------------------------------------------------------------ */
+
+/* Specify Valgrind's version number, so that user code can
+   conditionally compile based on our version number.  Note that these
+   were introduced at version 3.6 and so do not exist in version 3.5
+   or earlier.  The recommended way to use them to check for "version
+   X.Y or later" is (eg)
+
+#if defined(__VALGRIND_MAJOR__) && defined(__VALGRIND_MINOR__)   \
+    && (__VALGRIND_MAJOR__ > 3                                   \
+        || (__VALGRIND_MAJOR__ == 3 && __VALGRIND_MINOR__ >= 6))
+*/
+#define __VALGRIND_MAJOR__    3
+#define __VALGRIND_MINOR__    6
+
+
+///#include <stdarg.h>
+
+/* Nb: this file might be included in a file compiled with -ansi.  So
+   we can't use C++ style "//" comments nor the "asm" keyword (instead
+   use "__asm__"). */
+
+/* Derive some tags indicating what the target platform is.  Note
+   that in this file we're using the compiler's CPP symbols for
+   identifying architectures, which are different to the ones we use
+   within the rest of Valgrind.  Note, __powerpc__ is active for both
+   32 and 64-bit PPC, whereas __powerpc64__ is only active for the
+   latter (on Linux, that is).
+
+   Misc note: how to find out what's predefined in gcc by default:
+   gcc -Wp,-dM somefile.c
+*/
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#define PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_arm_linux
+#undef PLAT_s390x_linux
+
+#define va_start(v,l)		__builtin_va_start(v,l)
+#define va_end(v)		__builtin_va_end(v)
+#define va_arg(v,l)		__builtin_va_arg(v,l)
+typedef __builtin_va_list	va_list;
+
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE SPECIFICS for SPECIAL INSTRUCTIONS.  There is nothing */
+/* in here of use to end-users -- skip to the next section.           */
+/* ------------------------------------------------------------------ */
+
+/*
+ * VALGRIND_DO_CLIENT_REQUEST(): a statement that invokes a Valgrind client
+ * request. Accepts both pointers and integers as arguments.
+ *
+ * VALGRIND_DO_CLIENT_REQUEST_STMT(): a statement that invokes a Valgrind
+ * client request that does not return a value.
+
+ * VALGRIND_DO_CLIENT_REQUEST_EXPR(): a C expression that invokes a Valgrind
+ * client request and whose value equals the client request result.  Accepts
+ * both pointers and integers as arguments.  Note that such calls are not
+ * necessarily pure functions -- they may have side effects.
+ */
+
+#define VALGRIND_DO_CLIENT_REQUEST(_zzq_rlval, _zzq_default,            \
+                                   _zzq_request, _zzq_arg1, _zzq_arg2,  \
+                                   _zzq_arg3, _zzq_arg4, _zzq_arg5)     \
+  do { (_zzq_rlval) = VALGRIND_DO_CLIENT_REQUEST_EXPR((_zzq_default),   \
+                        (_zzq_request), (_zzq_arg1), (_zzq_arg2),       \
+                        (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#define VALGRIND_DO_CLIENT_REQUEST_STMT(_zzq_request, _zzq_arg1,        \
+                           _zzq_arg2,  _zzq_arg3, _zzq_arg4, _zzq_arg5) \
+  do { (void) VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                        \
+                    (_zzq_request), (_zzq_arg1), (_zzq_arg2),           \
+                    (_zzq_arg3), (_zzq_arg4), (_zzq_arg5)); } while (0)
+
+#if defined(NVALGRIND)
+
+/* Define NVALGRIND to completely remove the Valgrind magic sequence
+   from the compiled code (analogous to NDEBUG's effects on
+   assert()) */
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+      (_zzq_default)
+
+#else  /* ! NVALGRIND */
+
+/* The following defines the magic code sequences which the JITter
+   spots and handles magically.  Don't look too closely at them as
+   they will rot your brain.
+
+   The assembly code sequences for all architectures is in this one
+   file.  This is because this file must be stand-alone, and we don't
+   want to have multiple files.
+
+   For VALGRIND_DO_CLIENT_REQUEST, we must ensure that the default
+   value gets put in the return slot, so that everything works when
+   this is executed not under Valgrind.  Args are passed in a memory
+   block, and so there's no intrinsic limit to the number that could
+   be passed, but it's currently five.
+   
+   The macro args are: 
+      _zzq_rlval    result lvalue
+      _zzq_default  default value (result returned when running on real CPU)
+      _zzq_request  request code
+      _zzq_arg1..5  request params
+
+   The other two macros are used to support function wrapping, and are
+   a lot simpler.  VALGRIND_GET_NR_CONTEXT returns the value of the
+   guest's NRADDR pseudo-register and whatever other information is
+   needed to safely run the call original from the wrapper: on
+   ppc64-linux, the R2 value at the divert point is also needed.  This
+   information is abstracted into a user-visible type, OrigFn.
+
+   VALGRIND_CALL_NOREDIR_* behaves the same as the following on the
+   guest, but guarantees that the branch instruction will not be
+   redirected: x86: call *%eax, amd64: call *%rax, ppc32/ppc64:
+   branch-and-link-to-r11.  VALGRIND_CALL_NOREDIR is just text, not a
+   complete inline asm, since it needs to be combined with more magic
+   inline asm stuff to be useful.
+*/
+
+/* ------------------------- x86-{linux,darwin} ---------------- */
+
+#if defined(PLAT_x86_linux)  ||  defined(PLAT_x86_darwin)  \
+    ||  (defined(PLAT_x86_win32) && defined(__GNUC__))
+
+typedef
+   struct { 
+      unsigned int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     "roll $3,  %%edi ; roll $13, %%edi\n\t"      \
+                     "roll $29, %%edi ; roll $19, %%edi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+  __extension__                                                   \
+  ({volatile unsigned int _zzq_args[6];                           \
+    volatile unsigned int _zzq_result;                            \
+    _zzq_args[0] = (unsigned int)(_zzq_request);                  \
+    _zzq_args[1] = (unsigned int)(_zzq_arg1);                     \
+    _zzq_args[2] = (unsigned int)(_zzq_arg2);                     \
+    _zzq_args[3] = (unsigned int)(_zzq_arg3);                     \
+    _zzq_args[4] = (unsigned int)(_zzq_arg4);                     \
+    _zzq_args[5] = (unsigned int)(_zzq_arg5);                     \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %EDX = client_request ( %EAX ) */         \
+                     "xchgl %%ebx,%%ebx"                          \
+                     : "=d" (_zzq_result)                         \
+                     : "a" (&_zzq_args[0]), "0" (_zzq_default)    \
+                     : "cc", "memory"                             \
+                    );                                            \
+    _zzq_result;                                                  \
+  })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    volatile unsigned int __addr;                                 \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %EAX = guest_NRADDR */                    \
+                     "xchgl %%ecx,%%ecx"                          \
+                     : "=a" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory"                             \
+                    );                                            \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_CALL_NOREDIR_EAX                                 \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* call-noredir *%EAX */                     \
+                     "xchgl %%edx,%%edx\n\t"
+#endif /* PLAT_x86_linux || PLAT_x86_darwin || (PLAT_x86_win32 && __GNUC__) */
+
+/* ------------------------- x86-Win32 ------------------------- */
+
+#if defined(PLAT_x86_win32) && !defined(__GNUC__)
+
+typedef
+   struct { 
+      unsigned int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#if defined(_MSC_VER)
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     __asm rol edi, 3  __asm rol edi, 13          \
+                     __asm rol edi, 29 __asm rol edi, 19
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+    valgrind_do_client_request_expr((uintptr_t)(_zzq_default),    \
+        (uintptr_t)(_zzq_request), (uintptr_t)(_zzq_arg1),        \
+        (uintptr_t)(_zzq_arg2), (uintptr_t)(_zzq_arg3),           \
+        (uintptr_t)(_zzq_arg4), (uintptr_t)(_zzq_arg5))
+
+static __inline uintptr_t
+valgrind_do_client_request_expr(uintptr_t _zzq_default, uintptr_t _zzq_request,
+                                uintptr_t _zzq_arg1, uintptr_t _zzq_arg2,
+                                uintptr_t _zzq_arg3, uintptr_t _zzq_arg4,
+                                uintptr_t _zzq_arg5)
+{
+    volatile uintptr_t _zzq_args[6];
+    volatile unsigned int _zzq_result;
+    _zzq_args[0] = (uintptr_t)(_zzq_request);
+    _zzq_args[1] = (uintptr_t)(_zzq_arg1);
+    _zzq_args[2] = (uintptr_t)(_zzq_arg2);
+    _zzq_args[3] = (uintptr_t)(_zzq_arg3);
+    _zzq_args[4] = (uintptr_t)(_zzq_arg4);
+    _zzq_args[5] = (uintptr_t)(_zzq_arg5);
+    __asm { __asm lea eax, _zzq_args __asm mov edx, _zzq_default
+            __SPECIAL_INSTRUCTION_PREAMBLE
+            /* %EDX = client_request ( %EAX ) */
+            __asm xchg ebx,ebx
+            __asm mov _zzq_result, edx
+    }
+    return _zzq_result;
+}
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    volatile unsigned int __addr;                                 \
+    __asm { __SPECIAL_INSTRUCTION_PREAMBLE                        \
+            /* %EAX = guest_NRADDR */                             \
+            __asm xchg ecx,ecx                                    \
+            __asm mov __addr, eax                                 \
+    }                                                             \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_CALL_NOREDIR_EAX ERROR
+
+#else
+#error Unsupported compiler.
+#endif
+
+#endif /* PLAT_x86_win32 */
+
+/* ------------------------ amd64-{linux,darwin} --------------- */
+
+#if defined(PLAT_amd64_linux)  ||  defined(PLAT_amd64_darwin)
+
+typedef
+   struct { 
+      unsigned long long int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     "rolq $3,  %%rdi ; rolq $13, %%rdi\n\t"      \
+                     "rolq $61, %%rdi ; rolq $51, %%rdi\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+    __extension__                                                 \
+    ({ volatile unsigned long long int _zzq_args[6];              \
+    volatile unsigned long long int _zzq_result;                  \
+    _zzq_args[0] = (unsigned long long int)(_zzq_request);        \
+    _zzq_args[1] = (unsigned long long int)(_zzq_arg1);           \
+    _zzq_args[2] = (unsigned long long int)(_zzq_arg2);           \
+    _zzq_args[3] = (unsigned long long int)(_zzq_arg3);           \
+    _zzq_args[4] = (unsigned long long int)(_zzq_arg4);           \
+    _zzq_args[5] = (unsigned long long int)(_zzq_arg5);           \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %RDX = client_request ( %RAX ) */         \
+                     "xchgq %%rbx,%%rbx"                          \
+                     : "=d" (_zzq_result)                         \
+                     : "a" (&_zzq_args[0]), "0" (_zzq_default)    \
+                     : "cc", "memory"                             \
+                    );                                            \
+    _zzq_result;                                                  \
+    })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    volatile unsigned long long int __addr;                       \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %RAX = guest_NRADDR */                    \
+                     "xchgq %%rcx,%%rcx"                          \
+                     : "=a" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory"                             \
+                    );                                            \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_CALL_NOREDIR_RAX                                 \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* call-noredir *%RAX */                     \
+                     "xchgq %%rdx,%%rdx\n\t"
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+typedef
+   struct { 
+      unsigned int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     "rlwinm 0,0,3,0,0  ; rlwinm 0,0,13,0,0\n\t"  \
+                     "rlwinm 0,0,29,0,0 ; rlwinm 0,0,19,0,0\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+                                                                  \
+    __extension__                                                 \
+  ({         unsigned int  _zzq_args[6];                          \
+             unsigned int  _zzq_result;                           \
+             unsigned int* _zzq_ptr;                              \
+    _zzq_args[0] = (unsigned int)(_zzq_request);                  \
+    _zzq_args[1] = (unsigned int)(_zzq_arg1);                     \
+    _zzq_args[2] = (unsigned int)(_zzq_arg2);                     \
+    _zzq_args[3] = (unsigned int)(_zzq_arg3);                     \
+    _zzq_args[4] = (unsigned int)(_zzq_arg4);                     \
+    _zzq_args[5] = (unsigned int)(_zzq_arg5);                     \
+    _zzq_ptr = _zzq_args;                                         \
+    __asm__ volatile("mr 3,%1\n\t" /*default*/                    \
+                     "mr 4,%2\n\t" /*ptr*/                        \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %R3 = client_request ( %R4 ) */           \
+                     "or 1,1,1\n\t"                               \
+                     "mr %0,3"     /*result*/                     \
+                     : "=b" (_zzq_result)                         \
+                     : "b" (_zzq_default), "b" (_zzq_ptr)         \
+                     : "cc", "memory", "r3", "r4");               \
+    _zzq_result;                                                  \
+    })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    unsigned int __addr;                                          \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %R3 = guest_NRADDR */                     \
+                     "or 2,2,2\n\t"                               \
+                     "mr %0,3"                                    \
+                     : "=b" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory", "r3"                       \
+                    );                                            \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                   \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* branch-and-link-to-noredir *%R11 */       \
+                     "or 3,3,3\n\t"
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64_linux)
+
+typedef
+   struct { 
+      unsigned long long int nraddr; /* where's the code? */
+      unsigned long long int r2;  /* what tocptr do we need? */
+   }
+   OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+                     "rotldi 0,0,3  ; rotldi 0,0,13\n\t"          \
+                     "rotldi 0,0,61 ; rotldi 0,0,51\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+                                                                  \
+  __extension__                                                   \
+  ({         unsigned long long int  _zzq_args[6];                \
+             unsigned long long int  _zzq_result;                 \
+             unsigned long long int* _zzq_ptr;                    \
+    _zzq_args[0] = (unsigned long long int)(_zzq_request);        \
+    _zzq_args[1] = (unsigned long long int)(_zzq_arg1);           \
+    _zzq_args[2] = (unsigned long long int)(_zzq_arg2);           \
+    _zzq_args[3] = (unsigned long long int)(_zzq_arg3);           \
+    _zzq_args[4] = (unsigned long long int)(_zzq_arg4);           \
+    _zzq_args[5] = (unsigned long long int)(_zzq_arg5);           \
+    _zzq_ptr = _zzq_args;                                         \
+    __asm__ volatile("mr 3,%1\n\t" /*default*/                    \
+                     "mr 4,%2\n\t" /*ptr*/                        \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %R3 = client_request ( %R4 ) */           \
+                     "or 1,1,1\n\t"                               \
+                     "mr %0,3"     /*result*/                     \
+                     : "=b" (_zzq_result)                         \
+                     : "b" (_zzq_default), "b" (_zzq_ptr)         \
+                     : "cc", "memory", "r3", "r4");               \
+    _zzq_result;                                                  \
+  })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    unsigned long long int __addr;                                \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %R3 = guest_NRADDR */                     \
+                     "or 2,2,2\n\t"                               \
+                     "mr %0,3"                                    \
+                     : "=b" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory", "r3"                       \
+                    );                                            \
+    _zzq_orig->nraddr = __addr;                                   \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* %R3 = guest_NRADDR_GPR2 */                \
+                     "or 4,4,4\n\t"                               \
+                     "mr %0,3"                                    \
+                     : "=b" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory", "r3"                       \
+                    );                                            \
+    _zzq_orig->r2 = __addr;                                       \
+  }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                   \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* branch-and-link-to-noredir *%R11 */       \
+                     "or 3,3,3\n\t"
+
+#endif /* PLAT_ppc64_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+typedef
+   struct { 
+      unsigned int nraddr; /* where's the code? */
+   }
+   OrigFn;
+
+#define __SPECIAL_INSTRUCTION_PREAMBLE                            \
+            "mov r12, r12, ror #3  ; mov r12, r12, ror #13 \n\t"  \
+            "mov r12, r12, ror #29 ; mov r12, r12, ror #19 \n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                          \
+        _zzq_default, _zzq_request,                               \
+        _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+                                                                  \
+  __extension__                                                   \
+  ({volatile unsigned int  _zzq_args[6];                          \
+    volatile unsigned int  _zzq_result;                           \
+    _zzq_args[0] = (unsigned int)(_zzq_request);                  \
+    _zzq_args[1] = (unsigned int)(_zzq_arg1);                     \
+    _zzq_args[2] = (unsigned int)(_zzq_arg2);                     \
+    _zzq_args[3] = (unsigned int)(_zzq_arg3);                     \
+    _zzq_args[4] = (unsigned int)(_zzq_arg4);                     \
+    _zzq_args[5] = (unsigned int)(_zzq_arg5);                     \
+    __asm__ volatile("mov r3, %1\n\t" /*default*/                 \
+                     "mov r4, %2\n\t" /*ptr*/                     \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* R3 = client_request ( R4 ) */             \
+                     "orr r10, r10, r10\n\t"                      \
+                     "mov %0, r3"     /*result*/                  \
+                     : "=r" (_zzq_result)                         \
+                     : "r" (_zzq_default), "r" (&_zzq_args[0])    \
+                     : "cc","memory", "r3", "r4");                \
+    _zzq_result;                                                  \
+  })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                       \
+  { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+    unsigned int __addr;                                          \
+    __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* R3 = guest_NRADDR */                      \
+                     "orr r11, r11, r11\n\t"                      \
+                     "mov %0, r3"                                 \
+                     : "=r" (__addr)                              \
+                     :                                            \
+                     : "cc", "memory", "r3"                       \
+                    );                                            \
+    _zzq_orig->nraddr = __addr;                                   \
+  }
+
+#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                    \
+                     __SPECIAL_INSTRUCTION_PREAMBLE               \
+                     /* branch-and-link-to-noredir *%R4 */        \
+                     "orr r12, r12, r12\n\t"
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------ s390x-linux ------------------------ */
+
+#if defined(PLAT_s390x_linux)
+
+typedef
+  struct {
+     unsigned long long int nraddr; /* where's the code? */
+  }
+  OrigFn;
+
+/* __SPECIAL_INSTRUCTION_PREAMBLE will be used to identify Valgrind specific
+ * code. This detection is implemented in platform specific toIR.c
+ * (e.g. VEX/priv/guest_s390_decoder.c).
+ */
+#define __SPECIAL_INSTRUCTION_PREAMBLE                           \
+                     "lr 15,15\n\t"                              \
+                     "lr 1,1\n\t"                                \
+                     "lr 2,2\n\t"                                \
+                     "lr 3,3\n\t"
+
+#define __CLIENT_REQUEST_CODE "lr 2,2\n\t"
+#define __GET_NR_CONTEXT_CODE "lr 3,3\n\t"
+#define __CALL_NO_REDIR_CODE  "lr 4,4\n\t"
+
+#define VALGRIND_DO_CLIENT_REQUEST_EXPR(                         \
+       _zzq_default, _zzq_request,                               \
+       _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5)    \
+  __extension__                                                  \
+ ({volatile unsigned long long int _zzq_args[6];                 \
+   volatile unsigned long long int _zzq_result;                  \
+   _zzq_args[0] = (unsigned long long int)(_zzq_request);        \
+   _zzq_args[1] = (unsigned long long int)(_zzq_arg1);           \
+   _zzq_args[2] = (unsigned long long int)(_zzq_arg2);           \
+   _zzq_args[3] = (unsigned long long int)(_zzq_arg3);           \
+   _zzq_args[4] = (unsigned long long int)(_zzq_arg4);           \
+   _zzq_args[5] = (unsigned long long int)(_zzq_arg5);           \
+   __asm__ volatile(/* r2 = args */                              \
+                    "lgr 2,%1\n\t"                               \
+                    /* r3 = default */                           \
+                    "lgr 3,%2\n\t"                               \
+                    __SPECIAL_INSTRUCTION_PREAMBLE               \
+                    __CLIENT_REQUEST_CODE                        \
+                    /* results = r3 */                           \
+                    "lgr %0, 3\n\t"                              \
+                    : "=d" (_zzq_result)                         \
+                    : "a" (&_zzq_args[0]), "0" (_zzq_default)    \
+                    : "cc", "2", "3", "memory"                   \
+                   );                                            \
+   _zzq_result;                                                  \
+ })
+
+#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval)                      \
+ { volatile OrigFn* _zzq_orig = &(_zzq_rlval);                   \
+   volatile unsigned long long int __addr;                       \
+   __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE               \
+                    __GET_NR_CONTEXT_CODE                        \
+                    "lgr %0, 3\n\t"                              \
+                    : "=a" (__addr)                              \
+                    :                                            \
+                    : "cc", "3", "memory"                        \
+                   );                                            \
+   _zzq_orig->nraddr = __addr;                                   \
+ }
+
+#define VALGRIND_CALL_NOREDIR_R1                                 \
+                    __SPECIAL_INSTRUCTION_PREAMBLE               \
+                    __CALL_NO_REDIR_CODE
+
+#endif /* PLAT_s390x_linux */
+
+/* Insert assembly code for other platforms here... */
+
+#endif /* NVALGRIND */
+
+
+/* ------------------------------------------------------------------ */
+/* PLATFORM SPECIFICS for FUNCTION WRAPPING.  This is all very        */
+/* ugly.  It's the least-worst tradeoff I can think of.               */
+/* ------------------------------------------------------------------ */
+
+/* This section defines magic (a.k.a appalling-hack) macros for doing
+   guaranteed-no-redirection macros, so as to get from function
+   wrappers to the functions they are wrapping.  The whole point is to
+   construct standard call sequences, but to do the call itself with a
+   special no-redirect call pseudo-instruction that the JIT
+   understands and handles specially.  This section is long and
+   repetitious, and I can't see a way to make it shorter.
+
+   The naming scheme is as follows:
+
+      CALL_FN_{W,v}_{v,W,WW,WWW,WWWW,5W,6W,7W,etc}
+
+   'W' stands for "word" and 'v' for "void".  Hence there are
+   different macros for calling arity 0, 1, 2, 3, 4, etc, functions,
+   and for each, the possibility of returning a word-typed result, or
+   no result.
+*/
+
+/* Use these to write the name of your wrapper.  NOTE: duplicates
+   VG_WRAP_FUNCTION_Z{U,Z} in pub_tool_redir.h.  NOTE also: inserts
+   the default behaviour equivalance class tag "0000" into the name.
+   See pub_tool_redir.h for details -- normally you don't need to
+   think about this, though. */
+
+/* Use an extra level of macroisation so as to ensure the soname/fnname
+   args are fully macro-expanded before pasting them together. */
+#define VG_CONCAT4(_aa,_bb,_cc,_dd) _aa##_bb##_cc##_dd
+
+#define I_WRAP_SONAME_FNNAME_ZU(soname,fnname)                    \
+   VG_CONCAT4(_vgw00000ZU_,soname,_,fnname)
+
+#define I_WRAP_SONAME_FNNAME_ZZ(soname,fnname)                    \
+   VG_CONCAT4(_vgw00000ZZ_,soname,_,fnname)
+
+/* Use this macro from within a wrapper function to collect the
+   context (address and possibly other info) of the original function.
+   Once you have that you can then use it in one of the CALL_FN_
+   macros.  The type of the argument _lval is OrigFn. */
+#define VALGRIND_GET_ORIG_FN(_lval)  VALGRIND_GET_NR_CONTEXT(_lval)
+
+/* Derivatives of the main macros below, for calling functions
+   returning void. */
+
+#define CALL_FN_v_v(fnptr)                                        \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_v(_junk,fnptr); } while (0)
+
+#define CALL_FN_v_W(fnptr, arg1)                                  \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_W(_junk,fnptr,arg1); } while (0)
+
+#define CALL_FN_v_WW(fnptr, arg1,arg2)                            \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_WW(_junk,fnptr,arg1,arg2); } while (0)
+
+#define CALL_FN_v_WWW(fnptr, arg1,arg2,arg3)                      \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_WWW(_junk,fnptr,arg1,arg2,arg3); } while (0)
+
+#define CALL_FN_v_WWWW(fnptr, arg1,arg2,arg3,arg4)                \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_WWWW(_junk,fnptr,arg1,arg2,arg3,arg4); } while (0)
+
+#define CALL_FN_v_5W(fnptr, arg1,arg2,arg3,arg4,arg5)             \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_5W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5); } while (0)
+
+#define CALL_FN_v_6W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6)        \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_6W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6); } while (0)
+
+#define CALL_FN_v_7W(fnptr, arg1,arg2,arg3,arg4,arg5,arg6,arg7)   \
+   do { volatile unsigned long _junk;                             \
+        CALL_FN_W_7W(_junk,fnptr,arg1,arg2,arg3,arg4,arg5,arg6,arg7); } while (0)
+
+/* ------------------------- x86-{linux,darwin} ---------------- */
+
+#if defined(PLAT_x86_linux)  ||  defined(PLAT_x86_darwin)
+
+/* These regs are trashed by the hidden call.  No need to mention eax
+   as gcc can already see that, plus causes gcc to bomb. */
+#define __CALLER_SAVED_REGS /*"eax"*/ "ecx", "edx"
+
+/* These CALL_FN_ macros assume that on x86-linux, sizeof(unsigned
+   long) == 4. */
+
+#define CALL_FN_W_v(lval, orig)                                   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[1];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      __asm__ volatile(                                           \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1)                             \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[2];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      __asm__ volatile(                                           \
+         "subl $12, %%esp\n\t"                                    \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $16, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      __asm__ volatile(                                           \
+         "subl $8, %%esp\n\t"                                     \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $16, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3)                 \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[4];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      __asm__ volatile(                                           \
+         "subl $4, %%esp\n\t"                                     \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $16, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[5];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      __asm__ volatile(                                           \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $16, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5)        \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[6];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      __asm__ volatile(                                           \
+         "subl $12, %%esp\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $32, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6)   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[7];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      __asm__ volatile(                                           \
+         "subl $8, %%esp\n\t"                                     \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $32, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7)                            \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[8];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      __asm__ volatile(                                           \
+         "subl $4, %%esp\n\t"                                     \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $32, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[9];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      __asm__ volatile(                                           \
+         "pushl 32(%%eax)\n\t"                                    \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $32, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8,arg9)                  \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[10];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      __asm__ volatile(                                           \
+         "subl $12, %%esp\n\t"                                    \
+         "pushl 36(%%eax)\n\t"                                    \
+         "pushl 32(%%eax)\n\t"                                    \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $48, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[11];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      __asm__ volatile(                                           \
+         "subl $8, %%esp\n\t"                                     \
+         "pushl 40(%%eax)\n\t"                                    \
+         "pushl 36(%%eax)\n\t"                                    \
+         "pushl 32(%%eax)\n\t"                                    \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $48, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,       \
+                                  arg6,arg7,arg8,arg9,arg10,      \
+                                  arg11)                          \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[12];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      __asm__ volatile(                                           \
+         "subl $4, %%esp\n\t"                                     \
+         "pushl 44(%%eax)\n\t"                                    \
+         "pushl 40(%%eax)\n\t"                                    \
+         "pushl 36(%%eax)\n\t"                                    \
+         "pushl 32(%%eax)\n\t"                                    \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $48, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,       \
+                                  arg6,arg7,arg8,arg9,arg10,      \
+                                  arg11,arg12)                    \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[13];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      _argvec[12] = (unsigned long)(arg12);                       \
+      __asm__ volatile(                                           \
+         "pushl 48(%%eax)\n\t"                                    \
+         "pushl 44(%%eax)\n\t"                                    \
+         "pushl 40(%%eax)\n\t"                                    \
+         "pushl 36(%%eax)\n\t"                                    \
+         "pushl 32(%%eax)\n\t"                                    \
+         "pushl 28(%%eax)\n\t"                                    \
+         "pushl 24(%%eax)\n\t"                                    \
+         "pushl 20(%%eax)\n\t"                                    \
+         "pushl 16(%%eax)\n\t"                                    \
+         "pushl 12(%%eax)\n\t"                                    \
+         "pushl 8(%%eax)\n\t"                                     \
+         "pushl 4(%%eax)\n\t"                                     \
+         "movl (%%eax), %%eax\n\t"  /* target->%eax */            \
+         VALGRIND_CALL_NOREDIR_EAX                                \
+         "addl $48, %%esp\n"                                      \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#endif /* PLAT_x86_linux || PLAT_x86_darwin */
+
+/* ------------------------ amd64-{linux,darwin} --------------- */
+
+#if defined(PLAT_amd64_linux)  ||  defined(PLAT_amd64_darwin)
+
+/* ARGREGS: rdi rsi rdx rcx r8 r9 (the rest on stack in R-to-L order) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS /*"rax",*/ "rcx", "rdx", "rsi",       \
+                            "rdi", "r8", "r9", "r10", "r11"
+
+/* This is all pretty complex.  It's so as to make stack unwinding
+   work reliably.  See bug 243270.  The basic problem is the sub and
+   add of 128 of %rsp in all of the following macros.  If gcc believes
+   the CFA is in %rsp, then unwinding may fail, because what's at the
+   CFA is not what gcc "expected" when it constructs the CFIs for the
+   places where the macros are instantiated.
+
+   But we can't just add a CFI annotation to increase the CFA offset
+   by 128, to match the sub of 128 from %rsp, because we don't know
+   whether gcc has chosen %rsp as the CFA at that point, or whether it
+   has chosen some other register (eg, %rbp).  In the latter case,
+   adding a CFI annotation to change the CFA offset is simply wrong.
+
+   So the solution is to get hold of the CFA using
+   __builtin_dwarf_cfa(), put it in a known register, and add a
+   CFI annotation to say what the register is.  We choose %rbp for
+   this (perhaps perversely), because:
+
+   (1) %rbp is already subject to unwinding.  If a new register was
+       chosen then the unwinder would have to unwind it in all stack
+       traces, which is expensive, and
+
+   (2) %rbp is already subject to precise exception updates in the
+       JIT.  If a new register was chosen, we'd have to have precise
+       exceptions for it too, which reduces performance of the
+       generated code.
+
+   However .. one extra complication.  We can't just whack the result
+   of __builtin_dwarf_cfa() into %rbp and then add %rbp to the
+   list of trashed registers at the end of the inline assembly
+   fragments; gcc won't allow %rbp to appear in that list.  Hence
+   instead we need to stash %rbp in %r15 for the duration of the asm,
+   and say that %r15 is trashed instead.  gcc seems happy to go with
+   that.
+
+   Oh .. and this all needs to be conditionalised so that it is
+   unchanged from before this commit, when compiled with older gccs
+   that don't support __builtin_dwarf_cfa.  Furthermore, since
+   this header file is freestanding, it has to be independent of
+   config.h, and so the following conditionalisation cannot depend on
+   configure time checks.
+
+   Although it's not clear from
+   'defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)',
+   this expression excludes Darwin.
+   .cfi directives in Darwin assembly appear to be completely
+   different and I haven't investigated how they work.
+
+   For even more entertainment value, note we have to use the
+   completely undocumented __builtin_dwarf_cfa(), which appears to
+   really compute the CFA, whereas __builtin_frame_address(0) claims
+   to but actually doesn't.  See
+   https://bugs.kde.org/show_bug.cgi?id=243270#c47
+*/
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+#  define __FRAME_POINTER                                         \
+      ,"r"(__builtin_dwarf_cfa())
+#  define VALGRIND_CFI_PROLOGUE                                   \
+      "movq %%rbp, %%r15\n\t"                                     \
+      "movq %2, %%rbp\n\t"                                        \
+      ".cfi_remember_state\n\t"                                   \
+      ".cfi_def_cfa rbp, 0\n\t"
+#  define VALGRIND_CFI_EPILOGUE                                   \
+      "movq %%r15, %%rbp\n\t"                                     \
+      ".cfi_restore_state\n\t"
+#else
+#  define __FRAME_POINTER
+#  define VALGRIND_CFI_PROLOGUE
+#  define VALGRIND_CFI_EPILOGUE
+#endif
+
+
+/* These CALL_FN_ macros assume that on amd64-linux, sizeof(unsigned
+   long) == 8. */
+
+/* NB 9 Sept 07.  There is a nasty kludge here in all these CALL_FN_
+   macros.  In order not to trash the stack redzone, we need to drop
+   %rsp by 128 before the hidden call, and restore afterwards.  The
+   nastyness is that it is only by luck that the stack still appears
+   to be unwindable during the hidden call - since then the behaviour
+   of any routine using this macro does not match what the CFI data
+   says.  Sigh.
+
+   Why is this important?  Imagine that a wrapper has a stack
+   allocated local, and passes to the hidden call, a pointer to it.
+   Because gcc does not know about the hidden call, it may allocate
+   that local in the redzone.  Unfortunately the hidden call may then
+   trash it before it comes to use it.  So we must step clear of the
+   redzone, for the duration of the hidden call, to make it safe.
+
+   Probably the same problem afflicts the other redzone-style ABIs too
+   (ppc64-linux); but for those, the stack is
+   self describing (none of this CFI nonsense) so at least messing
+   with the stack pointer doesn't give a danger of non-unwindable
+   stack. */
+
+#define CALL_FN_W_v(lval, orig)                                   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[1];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1)                             \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[2];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3)                 \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[4];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[5];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5)        \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[6];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6)   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[7];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7)                            \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[8];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $136,%%rsp\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $8, %%rsp\n"                                       \
+         "addq $136,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[9];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "pushq 64(%%rax)\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $16, %%rsp\n"                                      \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8,arg9)                  \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[10];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $136,%%rsp\n\t"                                    \
+         "pushq 72(%%rax)\n\t"                                    \
+         "pushq 64(%%rax)\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $24, %%rsp\n"                                      \
+         "addq $136,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[11];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "pushq 80(%%rax)\n\t"                                    \
+         "pushq 72(%%rax)\n\t"                                    \
+         "pushq 64(%%rax)\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $32, %%rsp\n"                                      \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10,arg11)     \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[12];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $136,%%rsp\n\t"                                    \
+         "pushq 88(%%rax)\n\t"                                    \
+         "pushq 80(%%rax)\n\t"                                    \
+         "pushq 72(%%rax)\n\t"                                    \
+         "pushq 64(%%rax)\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $40, %%rsp\n"                                      \
+         "addq $136,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                arg7,arg8,arg9,arg10,arg11,arg12) \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[13];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      _argvec[12] = (unsigned long)(arg12);                       \
+      __asm__ volatile(                                           \
+         VALGRIND_CFI_PROLOGUE                                    \
+         "subq $128,%%rsp\n\t"                                    \
+         "pushq 96(%%rax)\n\t"                                    \
+         "pushq 88(%%rax)\n\t"                                    \
+         "pushq 80(%%rax)\n\t"                                    \
+         "pushq 72(%%rax)\n\t"                                    \
+         "pushq 64(%%rax)\n\t"                                    \
+         "pushq 56(%%rax)\n\t"                                    \
+         "movq 48(%%rax), %%r9\n\t"                               \
+         "movq 40(%%rax), %%r8\n\t"                               \
+         "movq 32(%%rax), %%rcx\n\t"                              \
+         "movq 24(%%rax), %%rdx\n\t"                              \
+         "movq 16(%%rax), %%rsi\n\t"                              \
+         "movq 8(%%rax), %%rdi\n\t"                               \
+         "movq (%%rax), %%rax\n\t"  /* target->%rax */            \
+         VALGRIND_CALL_NOREDIR_RAX                                \
+         "addq $48, %%rsp\n"                                      \
+         "addq $128,%%rsp\n\t"                                    \
+         VALGRIND_CFI_EPILOGUE                                    \
+         : /*out*/   "=a" (_res)                                  \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r15"   \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#endif /* PLAT_amd64_linux || PLAT_amd64_darwin */
+
+/* ------------------------ ppc32-linux ------------------------ */
+
+#if defined(PLAT_ppc32_linux)
+
+/* This is useful for finding out about the on-stack stuff:
+
+   extern int f9  ( int,int,int,int,int,int,int,int,int );
+   extern int f10 ( int,int,int,int,int,int,int,int,int,int );
+   extern int f11 ( int,int,int,int,int,int,int,int,int,int,int );
+   extern int f12 ( int,int,int,int,int,int,int,int,int,int,int,int );
+
+   int g9 ( void ) {
+      return f9(11,22,33,44,55,66,77,88,99);
+   }
+   int g10 ( void ) {
+      return f10(11,22,33,44,55,66,77,88,99,110);
+   }
+   int g11 ( void ) {
+      return f11(11,22,33,44,55,66,77,88,99,110,121);
+   }
+   int g12 ( void ) {
+      return f12(11,22,33,44,55,66,77,88,99,110,121,132);
+   }
+*/
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS                                       \
+   "lr", "ctr", "xer",                                            \
+   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",        \
+   "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",   \
+   "r11", "r12", "r13"
+
+/* These CALL_FN_ macros assume that on ppc32-linux, 
+   sizeof(unsigned long) == 4. */
+
+#define CALL_FN_W_v(lval, orig)                                   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[1];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1)                             \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[2];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3)                 \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[4];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[5];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5)        \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[6];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6)   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[7];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7)                            \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[8];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[9];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      _argvec[8] = (unsigned long)arg8;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 10,32(11)\n\t" /* arg8->r10 */                      \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8,arg9)                  \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[10];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      _argvec[8] = (unsigned long)arg8;                           \
+      _argvec[9] = (unsigned long)arg9;                           \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "addi 1,1,-16\n\t"                                       \
+         /* arg9 */                                               \
+         "lwz 3,36(11)\n\t"                                       \
+         "stw 3,8(1)\n\t"                                         \
+         /* args1-8 */                                            \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 10,32(11)\n\t" /* arg8->r10 */                      \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "addi 1,1,16\n\t"                                        \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[11];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      _argvec[8] = (unsigned long)arg8;                           \
+      _argvec[9] = (unsigned long)arg9;                           \
+      _argvec[10] = (unsigned long)arg10;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "addi 1,1,-16\n\t"                                       \
+         /* arg10 */                                              \
+         "lwz 3,40(11)\n\t"                                       \
+         "stw 3,12(1)\n\t"                                        \
+         /* arg9 */                                               \
+         "lwz 3,36(11)\n\t"                                       \
+         "stw 3,8(1)\n\t"                                         \
+         /* args1-8 */                                            \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 10,32(11)\n\t" /* arg8->r10 */                      \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "addi 1,1,16\n\t"                                        \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10,arg11)     \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[12];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      _argvec[8] = (unsigned long)arg8;                           \
+      _argvec[9] = (unsigned long)arg9;                           \
+      _argvec[10] = (unsigned long)arg10;                         \
+      _argvec[11] = (unsigned long)arg11;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "addi 1,1,-32\n\t"                                       \
+         /* arg11 */                                              \
+         "lwz 3,44(11)\n\t"                                       \
+         "stw 3,16(1)\n\t"                                        \
+         /* arg10 */                                              \
+         "lwz 3,40(11)\n\t"                                       \
+         "stw 3,12(1)\n\t"                                        \
+         /* arg9 */                                               \
+         "lwz 3,36(11)\n\t"                                       \
+         "stw 3,8(1)\n\t"                                         \
+         /* args1-8 */                                            \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 10,32(11)\n\t" /* arg8->r10 */                      \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "addi 1,1,32\n\t"                                        \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                arg7,arg8,arg9,arg10,arg11,arg12) \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[13];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)arg1;                           \
+      _argvec[2] = (unsigned long)arg2;                           \
+      _argvec[3] = (unsigned long)arg3;                           \
+      _argvec[4] = (unsigned long)arg4;                           \
+      _argvec[5] = (unsigned long)arg5;                           \
+      _argvec[6] = (unsigned long)arg6;                           \
+      _argvec[7] = (unsigned long)arg7;                           \
+      _argvec[8] = (unsigned long)arg8;                           \
+      _argvec[9] = (unsigned long)arg9;                           \
+      _argvec[10] = (unsigned long)arg10;                         \
+      _argvec[11] = (unsigned long)arg11;                         \
+      _argvec[12] = (unsigned long)arg12;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "addi 1,1,-32\n\t"                                       \
+         /* arg12 */                                              \
+         "lwz 3,48(11)\n\t"                                       \
+         "stw 3,20(1)\n\t"                                        \
+         /* arg11 */                                              \
+         "lwz 3,44(11)\n\t"                                       \
+         "stw 3,16(1)\n\t"                                        \
+         /* arg10 */                                              \
+         "lwz 3,40(11)\n\t"                                       \
+         "stw 3,12(1)\n\t"                                        \
+         /* arg9 */                                               \
+         "lwz 3,36(11)\n\t"                                       \
+         "stw 3,8(1)\n\t"                                         \
+         /* args1-8 */                                            \
+         "lwz 3,4(11)\n\t"   /* arg1->r3 */                       \
+         "lwz 4,8(11)\n\t"                                        \
+         "lwz 5,12(11)\n\t"                                       \
+         "lwz 6,16(11)\n\t"  /* arg4->r6 */                       \
+         "lwz 7,20(11)\n\t"                                       \
+         "lwz 8,24(11)\n\t"                                       \
+         "lwz 9,28(11)\n\t"                                       \
+         "lwz 10,32(11)\n\t" /* arg8->r10 */                      \
+         "lwz 11,0(11)\n\t"  /* target->r11 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "addi 1,1,32\n\t"                                        \
+         "mr %0,3"                                                \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#endif /* PLAT_ppc32_linux */
+
+/* ------------------------ ppc64-linux ------------------------ */
+
+#if defined(PLAT_ppc64_linux)
+
+/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS                                       \
+   "lr", "ctr", "xer",                                            \
+   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",        \
+   "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",   \
+   "r11", "r12", "r13"
+
+/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
+   long) == 8. */
+
+#define CALL_FN_W_v(lval, orig)                                   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+0];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1] = (unsigned long)_orig.r2;                       \
+      _argvec[2] = (unsigned long)_orig.nraddr;                   \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1)                             \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+1];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+2];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3)                 \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+3];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+4];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5)        \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+5];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6)   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+6];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7)                            \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+7];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+8];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      _argvec[2+8] = (unsigned long)arg8;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  10, 64(11)\n\t" /* arg8->r10 */                     \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)" /* restore tocptr */                      \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8,arg9)                  \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+9];                        \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      _argvec[2+8] = (unsigned long)arg8;                         \
+      _argvec[2+9] = (unsigned long)arg9;                         \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "addi 1,1,-128\n\t"  /* expand stack frame */            \
+         /* arg9 */                                               \
+         "ld  3,72(11)\n\t"                                       \
+         "std 3,112(1)\n\t"                                       \
+         /* args1-8 */                                            \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  10, 64(11)\n\t" /* arg8->r10 */                     \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)\n\t" /* restore tocptr */                  \
+         "addi 1,1,128"     /* restore frame */                   \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+10];                       \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      _argvec[2+8] = (unsigned long)arg8;                         \
+      _argvec[2+9] = (unsigned long)arg9;                         \
+      _argvec[2+10] = (unsigned long)arg10;                       \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "addi 1,1,-128\n\t"  /* expand stack frame */            \
+         /* arg10 */                                              \
+         "ld  3,80(11)\n\t"                                       \
+         "std 3,120(1)\n\t"                                       \
+         /* arg9 */                                               \
+         "ld  3,72(11)\n\t"                                       \
+         "std 3,112(1)\n\t"                                       \
+         /* args1-8 */                                            \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  10, 64(11)\n\t" /* arg8->r10 */                     \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)\n\t" /* restore tocptr */                  \
+         "addi 1,1,128"     /* restore frame */                   \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10,arg11)     \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+11];                       \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      _argvec[2+8] = (unsigned long)arg8;                         \
+      _argvec[2+9] = (unsigned long)arg9;                         \
+      _argvec[2+10] = (unsigned long)arg10;                       \
+      _argvec[2+11] = (unsigned long)arg11;                       \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "addi 1,1,-144\n\t"  /* expand stack frame */            \
+         /* arg11 */                                              \
+         "ld  3,88(11)\n\t"                                       \
+         "std 3,128(1)\n\t"                                       \
+         /* arg10 */                                              \
+         "ld  3,80(11)\n\t"                                       \
+         "std 3,120(1)\n\t"                                       \
+         /* arg9 */                                               \
+         "ld  3,72(11)\n\t"                                       \
+         "std 3,112(1)\n\t"                                       \
+         /* args1-8 */                                            \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  10, 64(11)\n\t" /* arg8->r10 */                     \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)\n\t" /* restore tocptr */                  \
+         "addi 1,1,144"     /* restore frame */                   \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                arg7,arg8,arg9,arg10,arg11,arg12) \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3+12];                       \
+      volatile unsigned long _res;                                \
+      /* _argvec[0] holds current r2 across the call */           \
+      _argvec[1]   = (unsigned long)_orig.r2;                     \
+      _argvec[2]   = (unsigned long)_orig.nraddr;                 \
+      _argvec[2+1] = (unsigned long)arg1;                         \
+      _argvec[2+2] = (unsigned long)arg2;                         \
+      _argvec[2+3] = (unsigned long)arg3;                         \
+      _argvec[2+4] = (unsigned long)arg4;                         \
+      _argvec[2+5] = (unsigned long)arg5;                         \
+      _argvec[2+6] = (unsigned long)arg6;                         \
+      _argvec[2+7] = (unsigned long)arg7;                         \
+      _argvec[2+8] = (unsigned long)arg8;                         \
+      _argvec[2+9] = (unsigned long)arg9;                         \
+      _argvec[2+10] = (unsigned long)arg10;                       \
+      _argvec[2+11] = (unsigned long)arg11;                       \
+      _argvec[2+12] = (unsigned long)arg12;                       \
+      __asm__ volatile(                                           \
+         "mr 11,%1\n\t"                                           \
+         "std 2,-16(11)\n\t"  /* save tocptr */                   \
+         "ld   2,-8(11)\n\t"  /* use nraddr's tocptr */           \
+         "addi 1,1,-144\n\t"  /* expand stack frame */            \
+         /* arg12 */                                              \
+         "ld  3,96(11)\n\t"                                       \
+         "std 3,136(1)\n\t"                                       \
+         /* arg11 */                                              \
+         "ld  3,88(11)\n\t"                                       \
+         "std 3,128(1)\n\t"                                       \
+         /* arg10 */                                              \
+         "ld  3,80(11)\n\t"                                       \
+         "std 3,120(1)\n\t"                                       \
+         /* arg9 */                                               \
+         "ld  3,72(11)\n\t"                                       \
+         "std 3,112(1)\n\t"                                       \
+         /* args1-8 */                                            \
+         "ld   3, 8(11)\n\t"  /* arg1->r3 */                      \
+         "ld   4, 16(11)\n\t" /* arg2->r4 */                      \
+         "ld   5, 24(11)\n\t" /* arg3->r5 */                      \
+         "ld   6, 32(11)\n\t" /* arg4->r6 */                      \
+         "ld   7, 40(11)\n\t" /* arg5->r7 */                      \
+         "ld   8, 48(11)\n\t" /* arg6->r8 */                      \
+         "ld   9, 56(11)\n\t" /* arg7->r9 */                      \
+         "ld  10, 64(11)\n\t" /* arg8->r10 */                     \
+         "ld  11, 0(11)\n\t"  /* target->r11 */                   \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R11                  \
+         "mr 11,%1\n\t"                                           \
+         "mr %0,3\n\t"                                            \
+         "ld 2,-16(11)\n\t" /* restore tocptr */                  \
+         "addi 1,1,144"     /* restore frame */                   \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "r" (&_argvec[2])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#endif /* PLAT_ppc64_linux */
+
+/* ------------------------- arm-linux ------------------------- */
+
+#if defined(PLAT_arm_linux)
+
+/* These regs are trashed by the hidden call. */
+#define __CALLER_SAVED_REGS "r0", "r1", "r2", "r3","r4","r14"
+
+/* These CALL_FN_ macros assume that on arm-linux, sizeof(unsigned
+   long) == 4. */
+
+#define CALL_FN_W_v(lval, orig)                                   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[1];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      __asm__ volatile(                                           \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "mov %0, r0\n"                                           \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_W(lval, orig, arg1)                             \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[2];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "mov %0, r0\n"                                           \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory",  __CALLER_SAVED_REGS         \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1,arg2)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[3];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "mov %0, r0\n"                                           \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3)                 \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[4];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "mov %0, r0\n"                                           \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[5];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5)        \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[6];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "push {r0} \n\t"                                         \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #4 \n\t"                                    \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6)   \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[7];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "push {r0, r1} \n\t"                                     \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #8 \n\t"                                    \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7)                            \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[8];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "push {r0, r1, r2} \n\t"                                 \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #12 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8)                       \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[9];                          \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "ldr r3, [%1, #32] \n\t"                                 \
+         "push {r0, r1, r2, r3} \n\t"                             \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #16 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,   \
+                                 arg7,arg8,arg9)                  \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[10];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "ldr r3, [%1, #32] \n\t"                                 \
+         "ldr r4, [%1, #36] \n\t"                                 \
+         "push {r0, r1, r2, r3, r4} \n\t"                         \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #20 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6,  \
+                                  arg7,arg8,arg9,arg10)           \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[11];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #40] \n\t"                                 \
+         "push {r0} \n\t"                                         \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "ldr r3, [%1, #32] \n\t"                                 \
+         "ldr r4, [%1, #36] \n\t"                                 \
+         "push {r0, r1, r2, r3, r4} \n\t"                         \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #24 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,       \
+                                  arg6,arg7,arg8,arg9,arg10,      \
+                                  arg11)                          \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[12];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #40] \n\t"                                 \
+         "ldr r1, [%1, #44] \n\t"                                 \
+         "push {r0, r1} \n\t"                                     \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "ldr r3, [%1, #32] \n\t"                                 \
+         "ldr r4, [%1, #36] \n\t"                                 \
+         "push {r0, r1, r2, r3, r4} \n\t"                         \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #28 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory",__CALLER_SAVED_REGS           \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,       \
+                                  arg6,arg7,arg8,arg9,arg10,      \
+                                  arg11,arg12)                    \
+   do {                                                           \
+      volatile OrigFn        _orig = (orig);                      \
+      volatile unsigned long _argvec[13];                         \
+      volatile unsigned long _res;                                \
+      _argvec[0] = (unsigned long)_orig.nraddr;                   \
+      _argvec[1] = (unsigned long)(arg1);                         \
+      _argvec[2] = (unsigned long)(arg2);                         \
+      _argvec[3] = (unsigned long)(arg3);                         \
+      _argvec[4] = (unsigned long)(arg4);                         \
+      _argvec[5] = (unsigned long)(arg5);                         \
+      _argvec[6] = (unsigned long)(arg6);                         \
+      _argvec[7] = (unsigned long)(arg7);                         \
+      _argvec[8] = (unsigned long)(arg8);                         \
+      _argvec[9] = (unsigned long)(arg9);                         \
+      _argvec[10] = (unsigned long)(arg10);                       \
+      _argvec[11] = (unsigned long)(arg11);                       \
+      _argvec[12] = (unsigned long)(arg12);                       \
+      __asm__ volatile(                                           \
+         "ldr r0, [%1, #40] \n\t"                                 \
+         "ldr r1, [%1, #44] \n\t"                                 \
+         "ldr r2, [%1, #48] \n\t"                                 \
+         "push {r0, r1, r2} \n\t"                                 \
+         "ldr r0, [%1, #20] \n\t"                                 \
+         "ldr r1, [%1, #24] \n\t"                                 \
+         "ldr r2, [%1, #28] \n\t"                                 \
+         "ldr r3, [%1, #32] \n\t"                                 \
+         "ldr r4, [%1, #36] \n\t"                                 \
+         "push {r0, r1, r2, r3, r4} \n\t"                         \
+         "ldr r0, [%1, #4] \n\t"                                  \
+         "ldr r1, [%1, #8] \n\t"                                  \
+         "ldr r2, [%1, #12] \n\t"                                 \
+         "ldr r3, [%1, #16] \n\t"                                 \
+         "ldr r4, [%1] \n\t"  /* target->r4 */                    \
+         VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R4                   \
+         "add sp, sp, #32 \n\t"                                   \
+         "mov %0, r0"                                             \
+         : /*out*/   "=r" (_res)                                  \
+         : /*in*/    "0" (&_argvec[0])                            \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS          \
+      );                                                          \
+      lval = (__typeof__(lval)) _res;                             \
+   } while (0)
+
+#endif /* PLAT_arm_linux */
+
+/* ------------------------- s390x-linux ------------------------- */
+
+#if defined(PLAT_s390x_linux)
+
+/* Similar workaround as amd64 (see above), but we use r11 as frame
+   pointer and save the old r11 in r7. r11 might be used for
+   argvec, therefore we copy argvec in r1 since r1 is clobbered
+   after the call anyway.  */
+#if defined(__GNUC__) && defined(__GCC_HAVE_DWARF2_CFI_ASM)
+#  define __FRAME_POINTER                                         \
+      ,"d"(__builtin_dwarf_cfa())
+#  define VALGRIND_CFI_PROLOGUE                                   \
+      ".cfi_remember_state\n\t"                                   \
+      "lgr 1,%1\n\t" /* copy the argvec pointer in r1 */          \
+      "lgr 7,11\n\t"                                              \
+      "lgr 11,%2\n\t"                                             \
+      ".cfi_def_cfa r11, 0\n\t"
+#  define VALGRIND_CFI_EPILOGUE                                   \
+      "lgr 11, 7\n\t"                                             \
+      ".cfi_restore_state\n\t"
+#else
+#  define __FRAME_POINTER
+#  define VALGRIND_CFI_PROLOGUE                                   \
+      "lgr 1,%1\n\t"
+#  define VALGRIND_CFI_EPILOGUE
+#endif
+
+
+
+
+/* These regs are trashed by the hidden call. Note that we overwrite
+   r14 in s390_irgen_noredir (VEX/priv/guest_s390_irgen.c) to give the
+   function a proper return address. All others are ABI defined call
+   clobbers. */
+#define __CALLER_SAVED_REGS "0","1","2","3","4","5","14", \
+                           "f0","f1","f2","f3","f4","f5","f6","f7"
+
+
+#define CALL_FN_W_v(lval, orig)                                  \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long  _argvec[1];                        \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 1, 0(1)\n\t"  /* target->r1 */                      \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "d" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7"     \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+/* The call abi has the arguments in r2-r6 and stack */
+#define CALL_FN_W_W(lval, orig, arg1)                            \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[2];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7"     \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_WW(lval, orig, arg1, arg2)                     \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[3];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7"     \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_WWW(lval, orig, arg1, arg2, arg3)              \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[4];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7"     \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_WWWW(lval, orig, arg1, arg2, arg3, arg4)       \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[5];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"7"     \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_5W(lval, orig, arg1, arg2, arg3, arg4, arg5)   \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[6];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-160\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,160\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_6W(lval, orig, arg1, arg2, arg3, arg4, arg5,   \
+                     arg6)                                       \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[7];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-168\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,168\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_7W(lval, orig, arg1, arg2, arg3, arg4, arg5,   \
+                     arg6, arg7)                                 \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[8];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-176\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,176\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_8W(lval, orig, arg1, arg2, arg3, arg4, arg5,   \
+                     arg6, arg7 ,arg8)                           \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[9];                         \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      _argvec[8] = (unsigned long)arg8;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-184\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "mvc 176(8,15), 64(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,184\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_9W(lval, orig, arg1, arg2, arg3, arg4, arg5,   \
+                     arg6, arg7 ,arg8, arg9)                     \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[10];                        \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      _argvec[8] = (unsigned long)arg8;                          \
+      _argvec[9] = (unsigned long)arg9;                          \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-192\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "mvc 176(8,15), 64(1)\n\t"                              \
+         "mvc 184(8,15), 72(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,192\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_10W(lval, orig, arg1, arg2, arg3, arg4, arg5,  \
+                     arg6, arg7 ,arg8, arg9, arg10)              \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[11];                        \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      _argvec[8] = (unsigned long)arg8;                          \
+      _argvec[9] = (unsigned long)arg9;                          \
+      _argvec[10] = (unsigned long)arg10;                        \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-200\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "mvc 176(8,15), 64(1)\n\t"                              \
+         "mvc 184(8,15), 72(1)\n\t"                              \
+         "mvc 192(8,15), 80(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,200\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_11W(lval, orig, arg1, arg2, arg3, arg4, arg5,  \
+                     arg6, arg7 ,arg8, arg9, arg10, arg11)       \
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[12];                        \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      _argvec[8] = (unsigned long)arg8;                          \
+      _argvec[9] = (unsigned long)arg9;                          \
+      _argvec[10] = (unsigned long)arg10;                        \
+      _argvec[11] = (unsigned long)arg11;                        \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-208\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "mvc 176(8,15), 64(1)\n\t"                              \
+         "mvc 184(8,15), 72(1)\n\t"                              \
+         "mvc 192(8,15), 80(1)\n\t"                              \
+         "mvc 200(8,15), 88(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,208\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+#define CALL_FN_W_12W(lval, orig, arg1, arg2, arg3, arg4, arg5,  \
+                     arg6, arg7 ,arg8, arg9, arg10, arg11, arg12)\
+   do {                                                          \
+      volatile OrigFn        _orig = (orig);                     \
+      volatile unsigned long _argvec[13];                        \
+      volatile unsigned long _res;                               \
+      _argvec[0] = (unsigned long)_orig.nraddr;                  \
+      _argvec[1] = (unsigned long)arg1;                          \
+      _argvec[2] = (unsigned long)arg2;                          \
+      _argvec[3] = (unsigned long)arg3;                          \
+      _argvec[4] = (unsigned long)arg4;                          \
+      _argvec[5] = (unsigned long)arg5;                          \
+      _argvec[6] = (unsigned long)arg6;                          \
+      _argvec[7] = (unsigned long)arg7;                          \
+      _argvec[8] = (unsigned long)arg8;                          \
+      _argvec[9] = (unsigned long)arg9;                          \
+      _argvec[10] = (unsigned long)arg10;                        \
+      _argvec[11] = (unsigned long)arg11;                        \
+      _argvec[12] = (unsigned long)arg12;                        \
+      __asm__ volatile(                                          \
+         VALGRIND_CFI_PROLOGUE                                   \
+         "aghi 15,-216\n\t"                                      \
+         "lg 2, 8(1)\n\t"                                        \
+         "lg 3,16(1)\n\t"                                        \
+         "lg 4,24(1)\n\t"                                        \
+         "lg 5,32(1)\n\t"                                        \
+         "lg 6,40(1)\n\t"                                        \
+         "mvc 160(8,15), 48(1)\n\t"                              \
+         "mvc 168(8,15), 56(1)\n\t"                              \
+         "mvc 176(8,15), 64(1)\n\t"                              \
+         "mvc 184(8,15), 72(1)\n\t"                              \
+         "mvc 192(8,15), 80(1)\n\t"                              \
+         "mvc 200(8,15), 88(1)\n\t"                              \
+         "mvc 208(8,15), 96(1)\n\t"                              \
+         "lg 1, 0(1)\n\t"                                        \
+         VALGRIND_CALL_NOREDIR_R1                                \
+         "lgr %0, 2\n\t"                                         \
+         "aghi 15,216\n\t"                                       \
+         VALGRIND_CFI_EPILOGUE                                   \
+         : /*out*/   "=d" (_res)                                 \
+         : /*in*/    "a" (&_argvec[0]) __FRAME_POINTER           \
+         : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS,"6","7" \
+      );                                                         \
+      lval = (__typeof__(lval)) _res;                            \
+   } while (0)
+
+
+#endif /* PLAT_s390x_linux */
+
+
+/* ------------------------------------------------------------------ */
+/* ARCHITECTURE INDEPENDENT MACROS for CLIENT REQUESTS.               */
+/*                                                                    */
+/* ------------------------------------------------------------------ */
+
+/* Some request codes.  There are many more of these, but most are not
+   exposed to end-user view.  These are the public ones, all of the
+   form 0x1000 + small_number.
+
+   Core ones are in the range 0x00000000--0x0000ffff.  The non-public
+   ones start at 0x2000.
+*/
+
+/* These macros are used by tools -- they must be public, but don't
+   embed them into other programs. */
+#define VG_USERREQ_TOOL_BASE(a,b) \
+   ((unsigned int)(((a)&0xff) << 24 | ((b)&0xff) << 16))
+#define VG_IS_TOOL_USERREQ(a, b, v) \
+   (VG_USERREQ_TOOL_BASE(a,b) == ((v) & 0xffff0000))
+
+/* !! ABIWARNING !! ABIWARNING !! ABIWARNING !! ABIWARNING !! 
+   This enum comprises an ABI exported by Valgrind to programs
+   which use client requests.  DO NOT CHANGE THE ORDER OF THESE
+   ENTRIES, NOR DELETE ANY -- add new ones at the end. */
+typedef
+   enum { VG_USERREQ__RUNNING_ON_VALGRIND  = 0x1001,
+          VG_USERREQ__DISCARD_TRANSLATIONS = 0x1002,
+
+          /* These allow any function to be called from the simulated
+             CPU but run on the real CPU.  Nb: the first arg passed to
+             the function is always the ThreadId of the running
+             thread!  So CLIENT_CALL0 actually requires a 1 arg
+             function, etc. */
+          VG_USERREQ__CLIENT_CALL0 = 0x1101,
+          VG_USERREQ__CLIENT_CALL1 = 0x1102,
+          VG_USERREQ__CLIENT_CALL2 = 0x1103,
+          VG_USERREQ__CLIENT_CALL3 = 0x1104,
+
+          /* Can be useful in regression testing suites -- eg. can
+             send Valgrind's output to /dev/null and still count
+             errors. */
+          VG_USERREQ__COUNT_ERRORS = 0x1201,
+
+          /* Allows a string (gdb monitor command) to be passed to the tool
+             Used for interaction with vgdb/gdb */
+          VG_USERREQ__GDB_MONITOR_COMMAND = 0x1202,
+
+          /* These are useful and can be interpreted by any tool that
+             tracks malloc() et al, by using vg_replace_malloc.c. */
+          VG_USERREQ__MALLOCLIKE_BLOCK = 0x1301,
+          VG_USERREQ__RESIZEINPLACE_BLOCK = 0x130b,
+          VG_USERREQ__FREELIKE_BLOCK   = 0x1302,
+          /* Memory pool support. */
+          VG_USERREQ__CREATE_MEMPOOL   = 0x1303,
+          VG_USERREQ__DESTROY_MEMPOOL  = 0x1304,
+          VG_USERREQ__MEMPOOL_ALLOC    = 0x1305,
+          VG_USERREQ__MEMPOOL_FREE     = 0x1306,
+          VG_USERREQ__MEMPOOL_TRIM     = 0x1307,
+          VG_USERREQ__MOVE_MEMPOOL     = 0x1308,
+          VG_USERREQ__MEMPOOL_CHANGE   = 0x1309,
+          VG_USERREQ__MEMPOOL_EXISTS   = 0x130a,
+
+          /* Allow printfs to valgrind log. */
+          /* The first two pass the va_list argument by value, which
+             assumes it is the same size as or smaller than a UWord,
+             which generally isn't the case.  Hence are deprecated.
+             The second two pass the vargs by reference and so are
+             immune to this problem. */
+          /* both :: char* fmt, va_list vargs (DEPRECATED) */
+          VG_USERREQ__PRINTF           = 0x1401,
+          VG_USERREQ__PRINTF_BACKTRACE = 0x1402,
+          /* both :: char* fmt, va_list* vargs */
+          VG_USERREQ__PRINTF_VALIST_BY_REF = 0x1403,
+          VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF = 0x1404,
+
+          /* Stack support. */
+          VG_USERREQ__STACK_REGISTER   = 0x1501,
+          VG_USERREQ__STACK_DEREGISTER = 0x1502,
+          VG_USERREQ__STACK_CHANGE     = 0x1503,
+
+          /* Wine support */
+          VG_USERREQ__LOAD_PDB_DEBUGINFO = 0x1601,
+
+          /* Querying of debug info. */
+          VG_USERREQ__MAP_IP_TO_SRCLOC = 0x1701,
+
+          /* Disable/enable error reporting level.  Takes a single
+             Word arg which is the delta to this thread's error
+             disablement indicator.  Hence 1 disables or further
+             disables errors, and -1 moves back towards enablement.
+             Other values are not allowed. */
+          VG_USERREQ__CHANGE_ERR_DISABLEMENT = 0x1801
+   } Vg_ClientRequest;
+
+#if !defined(__GNUC__)
+#  define __extension__ /* */
+#endif
+
+
+/* Returns the number of Valgrinds this code is running under.  That
+   is, 0 if running natively, 1 if running under Valgrind, 2 if
+   running under Valgrind which is running under another Valgrind,
+   etc. */
+#define RUNNING_ON_VALGRIND                                           \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* if not */,         \
+                                    VG_USERREQ__RUNNING_ON_VALGRIND,  \
+                                    0, 0, 0, 0, 0)                    \
+
+
+/* Discard translation of code in the range [_qzz_addr .. _qzz_addr +
+   _qzz_len - 1].  Useful if you are debugging a JITter or some such,
+   since it provides a way to make sure valgrind will retranslate the
+   invalidated area.  Returns no value. */
+#define VALGRIND_DISCARD_TRANSLATIONS(_qzz_addr,_qzz_len)              \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DISCARD_TRANSLATIONS,  \
+                                    _qzz_addr, _qzz_len, 0, 0, 0)
+
+
+/* These requests are for getting Valgrind itself to print something.
+   Possibly with a backtrace.  This is a really ugly hack.  The return value
+   is the number of characters printed, excluding the "**<pid>** " part at the
+   start and the backtrace (if present). */
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+/* Modern GCC will optimize the static routine out if unused,
+   and unused attribute will shut down warnings about it.  */
+static int VALGRIND_PRINTF(const char *format, ...)
+   __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF(const char *format, ...)
+{
+#if defined(NVALGRIND)
+   return 0;
+#else /* NVALGRIND */
+#if defined(_MSC_VER)
+   uintptr_t _qzz_res;
+#else
+   unsigned long _qzz_res;
+#endif
+   va_list vargs;
+   va_start(vargs, format);
+#if defined(_MSC_VER)
+   _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+                              VG_USERREQ__PRINTF_VALIST_BY_REF,
+                              (uintptr_t)format,
+                              (uintptr_t)&vargs,
+                              0, 0, 0);
+#else
+   _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+                              VG_USERREQ__PRINTF_VALIST_BY_REF,
+                              (unsigned long)format,
+                              (unsigned long)&vargs, 
+                              0, 0, 0);
+#endif
+   va_end(vargs);
+   return (int)_qzz_res;
+#endif /* NVALGRIND */
+}
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+static int VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+   __attribute__((format(__printf__, 1, 2), __unused__));
+#endif
+static int
+#if defined(_MSC_VER)
+__inline
+#endif
+VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+{
+#if defined(NVALGRIND)
+   return 0;
+#else /* NVALGRIND */
+#if defined(_MSC_VER)
+   uintptr_t _qzz_res;
+#else
+   unsigned long _qzz_res;
+#endif
+   va_list vargs;
+   va_start(vargs, format);
+#if defined(_MSC_VER)
+   _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+                              VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+                              (uintptr_t)format,
+                              (uintptr_t)&vargs,
+                              0, 0, 0);
+#else
+   _qzz_res = VALGRIND_DO_CLIENT_REQUEST_EXPR(0,
+                              VG_USERREQ__PRINTF_BACKTRACE_VALIST_BY_REF,
+                              (unsigned long)format,
+                              (unsigned long)&vargs, 
+                              0, 0, 0);
+#endif
+   va_end(vargs);
+   return (int)_qzz_res;
+#endif /* NVALGRIND */
+}
+
+
+/* These requests allow control to move from the simulated CPU to the
+   real CPU, calling an arbitary function.
+   
+   Note that the current ThreadId is inserted as the first argument.
+   So this call:
+
+     VALGRIND_NON_SIMD_CALL2(f, arg1, arg2)
+
+   requires f to have this signature:
+
+     Word f(Word tid, Word arg1, Word arg2)
+
+   where "Word" is a word-sized type.
+
+   Note that these client requests are not entirely reliable.  For example,
+   if you call a function with them that subsequently calls printf(),
+   there's a high chance Valgrind will crash.  Generally, your prospects of
+   these working are made higher if the called function does not refer to
+   any global variables, and does not refer to any libc or other functions
+   (printf et al).  Any kind of entanglement with libc or dynamic linking is
+   likely to have a bad outcome, for tricky reasons which we've grappled
+   with a lot in the past.
+*/
+#define VALGRIND_NON_SIMD_CALL0(_qyy_fn)                          \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,       \
+                                    VG_USERREQ__CLIENT_CALL0,     \
+                                    _qyy_fn,                      \
+                                    0, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL1(_qyy_fn, _qyy_arg1)                    \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,            \
+                                    VG_USERREQ__CLIENT_CALL1,          \
+                                    _qyy_fn,                           \
+                                    _qyy_arg1, 0, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL2(_qyy_fn, _qyy_arg1, _qyy_arg2)         \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,            \
+                                    VG_USERREQ__CLIENT_CALL2,          \
+                                    _qyy_fn,                           \
+                                    _qyy_arg1, _qyy_arg2, 0, 0)
+
+#define VALGRIND_NON_SIMD_CALL3(_qyy_fn, _qyy_arg1, _qyy_arg2, _qyy_arg3) \
+    VALGRIND_DO_CLIENT_REQUEST_EXPR(0 /* default return */,             \
+                                    VG_USERREQ__CLIENT_CALL3,           \
+                                    _qyy_fn,                            \
+                                    _qyy_arg1, _qyy_arg2,               \
+                                    _qyy_arg3, 0)
+
+
+/* Counts the number of errors that have been recorded by a tool.  Nb:
+   the tool must record the errors with VG_(maybe_record_error)() or
+   VG_(unique_error)() for them to be counted. */
+#define VALGRIND_COUNT_ERRORS                                     \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(                    \
+                               0 /* default return */,            \
+                               VG_USERREQ__COUNT_ERRORS,          \
+                               0, 0, 0, 0, 0)
+
+/* Several Valgrind tools (Memcheck, Massif, Helgrind, DRD) rely on knowing
+   when heap blocks are allocated in order to give accurate results.  This
+   happens automatically for the standard allocator functions such as
+   malloc(), calloc(), realloc(), memalign(), new, new[], free(), delete,
+   delete[], etc.
+
+   But if your program uses a custom allocator, this doesn't automatically
+   happen, and Valgrind will not do as well.  For example, if you allocate
+   superblocks with mmap() and then allocates chunks of the superblocks, all
+   Valgrind's observations will be at the mmap() level and it won't know that
+   the chunks should be considered separate entities.  In Memcheck's case,
+   that means you probably won't get heap block overrun detection (because
+   there won't be redzones marked as unaddressable) and you definitely won't
+   get any leak detection.
+
+   The following client requests allow a custom allocator to be annotated so
+   that it can be handled accurately by Valgrind.
+
+   VALGRIND_MALLOCLIKE_BLOCK marks a region of memory as having been allocated
+   by a malloc()-like function.  For Memcheck (an illustrative case), this
+   does two things:
+
+   - It records that the block has been allocated.  This means any addresses
+     within the block mentioned in error messages will be
+     identified as belonging to the block.  It also means that if the block
+     isn't freed it will be detected by the leak checker.
+
+   - It marks the block as being addressable and undefined (if 'is_zeroed' is
+     not set), or addressable and defined (if 'is_zeroed' is set).  This
+     controls how accesses to the block by the program are handled.
+   
+   'addr' is the start of the usable block (ie. after any
+   redzone), 'sizeB' is its size.  'rzB' is the redzone size if the allocator
+   can apply redzones -- these are blocks of padding at the start and end of
+   each block.  Adding redzones is recommended as it makes it much more likely
+   Valgrind will spot block overruns.  `is_zeroed' indicates if the memory is
+   zeroed (or filled with another predictable value), as is the case for
+   calloc().
+   
+   VALGRIND_MALLOCLIKE_BLOCK should be put immediately after the point where a
+   heap block -- that will be used by the client program -- is allocated.
+   It's best to put it at the outermost level of the allocator if possible;
+   for example, if you have a function my_alloc() which calls
+   internal_alloc(), and the client request is put inside internal_alloc(),
+   stack traces relating to the heap block will contain entries for both
+   my_alloc() and internal_alloc(), which is probably not what you want.
+
+   For Memcheck users: if you use VALGRIND_MALLOCLIKE_BLOCK to carve out
+   custom blocks from within a heap block, B, that has been allocated with
+   malloc/calloc/new/etc, then block B will be *ignored* during leak-checking
+   -- the custom blocks will take precedence.
+
+   VALGRIND_FREELIKE_BLOCK is the partner to VALGRIND_MALLOCLIKE_BLOCK.  For
+   Memcheck, it does two things:
+
+   - It records that the block has been deallocated.  This assumes that the
+     block was annotated as having been allocated via
+     VALGRIND_MALLOCLIKE_BLOCK.  Otherwise, an error will be issued.
+
+   - It marks the block as being unaddressable.
+
+   VALGRIND_FREELIKE_BLOCK should be put immediately after the point where a
+   heap block is deallocated.
+
+   VALGRIND_RESIZEINPLACE_BLOCK informs a tool about reallocation. For
+   Memcheck, it does four things:
+
+   - It records that the size of a block has been changed.  This assumes that
+     the block was annotated as having been allocated via
+     VALGRIND_MALLOCLIKE_BLOCK.  Otherwise, an error will be issued.
+
+   - If the block shrunk, it marks the freed memory as being unaddressable.
+
+   - If the block grew, it marks the new area as undefined and defines a red
+     zone past the end of the new block.
+
+   - The V-bits of the overlap between the old and the new block are preserved.
+
+   VALGRIND_RESIZEINPLACE_BLOCK should be put after allocation of the new block
+   and before deallocation of the old block.
+
+   In many cases, these three client requests will not be enough to get your
+   allocator working well with Memcheck.  More specifically, if your allocator
+   writes to freed blocks in any way then a VALGRIND_MAKE_MEM_UNDEFINED call
+   will be necessary to mark the memory as addressable just before the zeroing
+   occurs, otherwise you'll get a lot of invalid write errors.  For example,
+   you'll need to do this if your allocator recycles freed blocks, but it
+   zeroes them before handing them back out (via VALGRIND_MALLOCLIKE_BLOCK).
+   Alternatively, if your allocator reuses freed blocks for allocator-internal
+   data structures, VALGRIND_MAKE_MEM_UNDEFINED calls will also be necessary.
+
+   Really, what's happening is a blurring of the lines between the client
+   program and the allocator... after VALGRIND_FREELIKE_BLOCK is called, the
+   memory should be considered unaddressable to the client program, but the
+   allocator knows more than the rest of the client program and so may be able
+   to safely access it.  Extra client requests are necessary for Valgrind to
+   understand the distinction between the allocator and the rest of the
+   program.
+
+   Ignored if addr == 0.
+*/
+#define VALGRIND_MALLOCLIKE_BLOCK(addr, sizeB, rzB, is_zeroed)          \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MALLOCLIKE_BLOCK,       \
+                                    addr, sizeB, rzB, is_zeroed, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+   Ignored if addr == 0.
+*/
+#define VALGRIND_RESIZEINPLACE_BLOCK(addr, oldSizeB, newSizeB, rzB)     \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__RESIZEINPLACE_BLOCK,    \
+                                    addr, oldSizeB, newSizeB, rzB, 0)
+
+/* See the comment for VALGRIND_MALLOCLIKE_BLOCK for details.
+   Ignored if addr == 0.
+*/
+#define VALGRIND_FREELIKE_BLOCK(addr, rzB)                              \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__FREELIKE_BLOCK,         \
+                                    addr, rzB, 0, 0, 0)
+
+/* Create a memory pool. */
+#define VALGRIND_CREATE_MEMPOOL(pool, rzB, is_zeroed)             \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CREATE_MEMPOOL,   \
+                                    pool, rzB, is_zeroed, 0, 0)
+
+/* Destroy a memory pool. */
+#define VALGRIND_DESTROY_MEMPOOL(pool)                            \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__DESTROY_MEMPOOL,  \
+                                    pool, 0, 0, 0, 0)
+
+/* Associate a piece of memory with a memory pool. */
+#define VALGRIND_MEMPOOL_ALLOC(pool, addr, size)                  \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_ALLOC,    \
+                                    pool, addr, size, 0, 0)
+
+/* Disassociate a piece of memory from a memory pool. */
+#define VALGRIND_MEMPOOL_FREE(pool, addr)                         \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_FREE,     \
+                                    pool, addr, 0, 0, 0)
+
+/* Disassociate any pieces outside a particular range. */
+#define VALGRIND_MEMPOOL_TRIM(pool, addr, size)                   \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_TRIM,     \
+                                    pool, addr, size, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MOVE_MEMPOOL(poolA, poolB)                       \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MOVE_MEMPOOL,     \
+                                    poolA, poolB, 0, 0, 0)
+
+/* Resize and/or move a piece associated with a memory pool. */
+#define VALGRIND_MEMPOOL_CHANGE(pool, addrA, addrB, size)         \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__MEMPOOL_CHANGE,   \
+                                    pool, addrA, addrB, size, 0)
+
+/* Return 1 if a mempool exists, else 0. */
+#define VALGRIND_MEMPOOL_EXISTS(pool)                             \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                  \
+                               VG_USERREQ__MEMPOOL_EXISTS,        \
+                               pool, 0, 0, 0, 0)
+
+/* Mark a piece of memory as being a stack. Returns a stack id. */
+#define VALGRIND_STACK_REGISTER(start, end)                       \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                  \
+                               VG_USERREQ__STACK_REGISTER,        \
+                               start, end, 0, 0, 0)
+
+/* Unmark the piece of memory associated with a stack id as being a
+   stack. */
+#define VALGRIND_STACK_DEREGISTER(id)                             \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_DEREGISTER, \
+                                    id, 0, 0, 0, 0)
+
+/* Change the start and end address of the stack id. */
+#define VALGRIND_STACK_CHANGE(id, start, end)                     \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__STACK_CHANGE,     \
+                                    id, start, end, 0, 0)
+
+/* Load PDB debug info for Wine PE image_map. */
+#define VALGRIND_LOAD_PDB_DEBUGINFO(fd, ptr, total_size, delta)     \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__LOAD_PDB_DEBUGINFO, \
+                                    fd, ptr, total_size, delta, 0)
+
+/* Map a code address to a source file name and line number.  buf64
+   must point to a 64-byte buffer in the caller's address space.  The
+   result will be dumped in there and is guaranteed to be zero
+   terminated.  If no info is found, the first byte is set to zero. */
+#define VALGRIND_MAP_IP_TO_SRCLOC(addr, buf64)                    \
+    (unsigned)VALGRIND_DO_CLIENT_REQUEST_EXPR(0,                  \
+                               VG_USERREQ__MAP_IP_TO_SRCLOC,      \
+                               addr, buf64, 0, 0, 0)
+
+/* Disable error reporting for this thread.  Behaves in a stack like
+   way, so you can safely call this multiple times provided that
+   VALGRIND_ENABLE_ERROR_REPORTING is called the same number of times
+   to re-enable reporting.  The first call of this macro disables
+   reporting.  Subsequent calls have no effect except to increase the
+   number of VALGRIND_ENABLE_ERROR_REPORTING calls needed to re-enable
+   reporting.  Child threads do not inherit this setting from their
+   parents -- they are always created with reporting enabled. */
+#define VALGRIND_DISABLE_ERROR_REPORTING                                \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+                                    1, 0, 0, 0, 0)
+
+/* Re-enable error reporting, as per comments on
+   VALGRIND_DISABLE_ERROR_REPORTING. */
+#define VALGRIND_ENABLE_ERROR_REPORTING                                 \
+    VALGRIND_DO_CLIENT_REQUEST_STMT(VG_USERREQ__CHANGE_ERR_DISABLEMENT, \
+                                    -1, 0, 0, 0, 0)
+
+#undef PLAT_x86_darwin
+#undef PLAT_amd64_darwin
+#undef PLAT_x86_win32
+#undef PLAT_x86_linux
+#undef PLAT_amd64_linux
+#undef PLAT_ppc32_linux
+#undef PLAT_ppc64_linux
+#undef PLAT_arm_linux
+#undef PLAT_s390x_linux
+
+#endif   /* __VALGRIND_H */
diff --git a/src/lib/malloc.c b/src/lib/malloc.c
index 2e700f7..19862eb 100644
--- a/src/lib/malloc.c
+++ b/src/lib/malloc.c
@@ -1,6 +1,10 @@
 #include <stdlib.h>
 #include <console/console.h>
 
+#if CONFIG_ULINUX_VALGRIND
+#include <valgrind.h>
+#endif
+
 #if CONFIG_DEBUG_MALLOC
 #define MALLOCDBG(x...) printk(BIOS_SPEW, x)
 #else
@@ -8,7 +12,7 @@
 #endif
 
 extern unsigned char _heap, _eheap;
-static void *free_mem_ptr = &_heap;		/* Start of heap */
+static void *free_mem_ptr = &_heap + 64;		/* Start of heap */
 static void *free_mem_end_ptr = &_eheap;	/* End of heap */
 
 /* We don't restrict the boundary. This is firmware,
@@ -26,9 +30,9 @@ void *memalign(size_t boundary, size_t size)
 		die("Error! memalign: Free_mem_ptr <= 0");
 
 	free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary);
-
+	VALGRIND_MEMPOOL_ALLOC(&_heap, free_mem_ptr, size);
 	p = free_mem_ptr;
-	free_mem_ptr += size;
+	free_mem_ptr += (size + 8);
 
 	if (free_mem_ptr >= free_mem_end_ptr)
 		die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)");



From gerrit at coreboot.org  Tue Jun  5 01:02:26 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:26 +0200
Subject: [coreboot] New patch to review for coreboot: 922b3c6 leave frame
	pointers
References: <I4f96ca321a175c941c55846fd2471ef5cc4897af+0@gerrit.coreboot.org>
Message-ID: <I4f96ca321a175c941c55846fd2471ef5cc4897af+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1092

-gerrit

commit 922b3c627bd573513b26fcb47197b01e77bfee0b
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:22:39 2012 +0200

    leave frame pointers
    
    Do not strip out frame pointer, handy for debugging (this needs to be somehow more polished
    but one gets the idea).
    
    Change-Id: I4f96ca321a175c941c55846fd2471ef5cc4897af
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 Makefile.inc              |   16 +++++++++++++++-
 src/arch/x86/Makefile.inc |    5 +++++
 2 files changed, 20 insertions(+), 1 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 176ff67..f3e87cc 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -61,8 +61,15 @@ subdirs-y += site-local
 # Add source classes and their build options
 classes-y := ramstage romstage driver smm
 
-romstage-c-ccopts:=-D__PRE_RAM__
+
+ifeq ($(CONFIG_ULINUX),y)
+stack_opt := -fomit-frame-pointer
+ramstage-c-ccopts:= -fstack-protector-all
+endif
+
+romstage-c-ccopts:=-D__PRE_RAM__ $(stack_opt)
 romstage-S-ccopts:=-D__PRE_RAM__
+
 ifeq ($(CONFIG_TRACE),y)
 ramstage-c-ccopts:= -finstrument-functions
 endif
@@ -163,7 +170,14 @@ CFLAGS += -Wstrict-aliasing -Wshadow
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS += -Werror
 endif
+
+ifeq ($(CONFIG_ULINUX),n)
 CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
+endif
+
+ifeq ($(CONFIG_ULINUX),y)
+CFLAGS += -fno-common -ffreestanding -fno-builtin
+endif
 
 additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/options
 
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9739555..dc7a7a0 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -208,7 +208,12 @@ else
 
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
 	@printf "    CC         romstage.inc\n"
+ifeq ($(CONFIG_ULINUX),y)
+	$(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -fomit-frame-pointer -I$(src) -I. -I$(obj) -c -S $< -o $@
+endif
+ifeq ($(CONFIG_ULINUX),n)
 	$(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@
+endif
 
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
 	@printf "    POST       romstage.inc\n"



From gerrit at coreboot.org  Tue Jun  5 01:02:27 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:27 +0200
Subject: [coreboot] New patch to review for coreboot: a4e7fb1 random hack in
	qemu target
References: <I0c8f8619fa054af72cca76a0825fd00a4d301c3d+0@gerrit.coreboot.org>
Message-ID: <I0c8f8619fa054af72cca76a0825fd00a4d301c3d+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1093

-gerrit

commit a4e7fb13b611d5d3f14b3a21f34d19939e5e62ed
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:24:14 2012 +0200

    random hack in qemu target
    
    Not for merge, just simple hack to use userspace coreboot even without serialice (comment out serialice_init).
    if serialice_init is commented all IO will fail but one can test the memory access/workflow more faster.
    
    Change-Id: I0c8f8619fa054af72cca76a0825fd00a4d301c3d
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/mainboard/emulation/qemu-x86/northbridge.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index f1669bb..d701b8c 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -11,6 +11,7 @@
 #include "chip.h"
 #include <delay.h>
 #include <smbios.h>
+#include <ulinux.h>
 
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
@@ -38,7 +39,8 @@ static void cpu_pci_domain_set_resources(device_t dev)
 	unsigned long tomk = 0, tolmk;
 	int idx;
 
-	tomk = qemu_get_memory_size();
+//	tomk = qemu_get_memory_size();
+	tomk = 16*1024;
 	printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
 	       tomk, tomk / 1024);
 
@@ -58,8 +60,10 @@ static void cpu_pci_domain_set_resources(device_t dev)
 	/* Leave some space for ACPI, PIRQ and MP tables */
 	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
 	high_tables_size = HIGH_MEMORY_SIZE;
+#if CONFIG_ULINUX
+	ulinux_mmap(high_tables_base, high_tables_size);
+#endif
 #endif
-
 	assign_resources(dev->link_list);
 }
 



From gerrit at coreboot.org  Tue Jun  5 01:02:28 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:28 +0200
Subject: [coreboot] New patch to review for coreboot: d602fc7 Add host side
	of serialICE which uses ulinux.
References: <If71737e6866c5c4dd62b9c26c676686ebfd20bcc+0@gerrit.coreboot.org>
Message-ID: <If71737e6866c5c4dd62b9c26c676686ebfd20bcc+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1094

-gerrit

commit d602fc79e963057e4db00a4e2dca38d48ad6b484
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:26:06 2012 +0200

    Add host side of serialICE which uses ulinux.
    
    This is copied from serialICE qemu and strtoul is from libpayload. this must be fixed
    maybe into string.h?
    
    Change-Id: If71737e6866c5c4dd62b9c26c676686ebfd20bcc
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/include/serialice_host.h |   66 ++++
 src/lib/serialice_host.c     |  676 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 742 insertions(+), 0 deletions(-)

diff --git a/src/include/serialice_host.h b/src/include/serialice_host.h
new file mode 100644
index 0000000..f099325
--- /dev/null
+++ b/src/include/serialice_host.h
@@ -0,0 +1,66 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2009 coresystems GmbH
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef SERIALICE_HH
+#define SERIALICE_HH
+#include <stdint.h>
+extern const char *serialice_device;
+extern int serialice_active;
+
+void serialice_init(void);
+void serialice_exit(void);
+const char *serialice_lua_execute(const char *cmd);
+
+uint8_t serialice_inb(uint16_t port);
+uint16_t serialice_inw(uint16_t port);
+uint32_t serialice_inl(uint16_t port);
+
+void serialice_outb(uint8_t data, uint16_t port);
+void serialice_outw(uint16_t data, uint16_t port);
+void serialice_outl(uint32_t data, uint16_t port);
+
+uint8_t serialice_readb(uint32_t addr);
+uint16_t serialice_readw(uint32_t addr);
+uint32_t serialice_readl(uint32_t addr);
+
+void serialice_writeb(uint8_t data, uint32_t addr);
+void serialice_writew(uint16_t data, uint32_t addr);
+void serialice_writel(uint32_t data, uint32_t addr);
+
+uint64_t serialice_rdmsr(uint32_t addr, uint32_t key);
+void serialice_wrmsr(uint64_t data, uint32_t addr, uint32_t key);
+
+typedef struct {
+    uint32_t eax, ebx, ecx, edx;
+} cpuid_regs_t;
+
+cpuid_regs_t serialice_cpuid(uint32_t eax, uint32_t ecx);
+
+int serialice_handle_load(uint32_t addr, uint32_t * result,
+                          unsigned int data_size);
+void serialice_log_load(int caught, uint32_t addr, uint32_t result,
+                        unsigned int data_size);
+int serialice_handle_store(uint32_t addr, uint32_t val, unsigned int data_size);
+
+#endif
diff --git a/src/lib/serialice_host.c b/src/lib/serialice_host.c
new file mode 100644
index 0000000..4d318b2
--- /dev/null
+++ b/src/lib/serialice_host.c
@@ -0,0 +1,676 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2009 coresystems GmbH
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/* Indented with:
+ * gnuindent -npro -kr -i4 -nut -bap -sob -l80 -ss -ncs serialice.*
+ */
+
+/* System includes */
+#include <stdlib.h>
+#include <stdint.h>
+
+#include <string.h>
+#ifdef WIN32
+#include <windows.h>
+#include <conio.h>
+#else
+#include <termios.h>
+#endif
+
+#include <console/console.h>
+#include <serialice_host.h>
+#include <ulinux.h>
+
+const char *serialice_device = CONFIG_SERIALICE_HOST_DEV;
+
+/* Check that a character is in the valid range for the
+   given base
+*/
+
+//#warning "move this to string.h? got it from libpayload"
+
+#define UINT32_MAX 0xffffffffU
+static int _valid(char ch, int base)
+{
+        char end = (base > 9) ? '9' : '0' + (base - 1);
+
+        /* all bases will be some subset of the 0-9 range */
+
+        if (ch >= '0' && ch <= end)
+                return 1;
+
+        /* Bases > 11 will also have to match in the a-z range */
+
+        if (base > 11) {
+                if (tolower(ch) >= 'a' &&
+                    tolower(ch) <= 'a' + (base - 11))
+                        return 1;
+        }
+
+        return 0;
+}
+
+/* Return the "value" of the character in the given base */
+
+static int _offset(char ch, int base)
+{
+        if (ch >= '0' && ch <= '9')
+                return ch - '0';
+        else
+                return 10 + tolower(ch) - 'a';
+}
+
+/**
+ * Convert the initial portion of a string into an unsigned int
+ * @param ptr A pointer to the string to convert
+ * @param endptr A pointer to the unconverted part of the string
+ * @param base The base of the number to convert, or 0 for auto
+ * @return An unsigned integer representation of the string
+ */
+
+static unsigned long long strtoull(const char *ptr, char **endptr, unsigned int base)
+{
+        unsigned long long  ret = 0;
+
+	if (endptr != NULL)
+		*endptr = (char *) ptr;
+
+        /* Purge whitespace */
+
+        for( ; *ptr && isspace(*ptr); ptr++);
+
+        if (!*ptr)
+                return 0;
+
+        /* Determine the base */
+
+        if (base == 0) {
+		if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
+			base = 16;
+		else if (ptr[0] == '0') {
+			base = 8;
+			ptr++;
+		}
+		else
+			base = 10;
+        }
+
+	/* Base 16 allows the 0x on front - so skip over it */
+
+	if (base == 16) {
+		if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
+			ptr += 2;
+	}
+
+	/* If the first character isn't valid, then don't
+         * bother */
+
+        if (!*ptr || !_valid(*ptr, base))
+                return 0;
+
+        for( ; *ptr && _valid(*ptr, base); ptr++)
+                ret = (ret * base) + _offset(*ptr, base);
+
+	if (endptr != NULL)
+		*endptr = (char *) ptr;
+
+        return ret;
+}
+
+static unsigned long  strtoul(const char *ptr, char **endptr, unsigned int base)
+{
+	unsigned long long val = strtoull(ptr, endptr, base);
+	if (val > UINT32_MAX) return UINT32_MAX;
+	return val;
+}
+
+#define SERIALICE_DEBUG 3
+#define BUFFER_SIZE 1024
+typedef struct {
+#ifdef WIN32
+    HANDLE fd;
+#else
+    int fd;
+#endif
+    char *buffer;
+    char *command;
+} SerialICEState;
+
+/* Make it static, so it works from start */
+static char bb[BUFFER_SIZE];
+static  char cc[BUFFER_SIZE];
+
+static SerialICEState ss = {
+	.buffer  = bb,
+	.command = cc,
+    };
+
+static SerialICEState *s = &ss;
+int serialice_active = 0;
+
+#ifndef WIN32
+static struct termios options;
+#endif
+
+/* SerialICE output loggers */
+
+#define LOG_IO		0
+#define LOG_MEMORY	1
+#define LOG_READ	0
+#define LOG_WRITE	2
+// these two are separate
+#define LOG_QEMU	4
+#define LOG_TARGET	8
+
+static void serialice_log(int flags, uint32_t data, uint32_t addr, int size)
+{
+    if ((flags & LOG_WRITE) && (flags & LOG_MEMORY)) {
+	printk(BIOS_INFO, "MEM WRITE: [%08x] %08x size %d\n", addr, data, size);
+    } else if (!(flags & LOG_WRITE) && (flags & LOG_MEMORY)) {
+	printk(BIOS_INFO, "MEM READ: [%08x] %08x size %d\n", addr, data, size);
+    } else if ((flags & LOG_WRITE) && !(flags & LOG_MEMORY)) {
+	printk(BIOS_INFO, "IO WRITE: [%08x] %08x size %d\n", addr, data, size);
+    } else {                    // if (!(flags & LOG_WRITE) && !(flags & LOG_MEMORY))
+	printk(BIOS_INFO, "IO READ: [%08x] %08x size %d\n", addr, data, size);
+    }
+
+}
+
+static void serialice_msr_log(int flags, uint32_t addr, uint32_t hi,
+                              uint32_t lo, int filtered)
+{
+
+    if (flags & LOG_WRITE) {
+	printk(BIOS_INFO, "MSR READ: [%08x] %08x%08x\n", addr,hi,lo);
+    } else {                    // if (!(flags & LOG_WRITE))
+	printk(BIOS_INFO, "MSR WRITE: [%08x] %08x%08x\n", addr,hi,lo);
+    }
+
+}
+
+static void serialice_cpuid_log(uint32_t eax, uint32_t ecx, cpuid_regs_t res,
+                                int filtered)
+{
+
+	printk(BIOS_INFO, "CPUID todo\n");
+}
+
+// **************************************************************************
+// low level communication with the SerialICE shell (serial communication)
+
+static int serialice_read(SerialICEState * state, void *buf, size_t nbyte)
+{
+    int bytes_read = 0;
+
+    while (1) {
+#ifdef WIN32
+        int ret = 0;
+        ReadFile(state->fd, buf, nbyte - bytes_read, &ret, NULL);
+        if (!ret) {
+            break;
+        }
+#else
+        int ret = ulinux_read(state->fd, buf, nbyte - bytes_read);
+
+        if (ret == -1 && ulinux_errno == EINTR) {
+            continue;
+        }
+
+        if (ret == -1) {
+            break;
+        }
+#endif
+
+        bytes_read += ret;
+        buf += ret;
+
+        if (bytes_read >= (int)nbyte) {
+            break;
+        }
+    }
+
+    return bytes_read;
+}
+
+static int handshake_mode = 0;
+
+static int serialice_write(SerialICEState * state, const void *buf,
+                           size_t nbyte)
+{
+    char *buffer = (char *)buf;
+    char c;
+    int i;
+    for (i = 0; i < (int)nbyte; i++) {
+#ifdef WIN32
+        int ret = 0;
+        while (ret == 0) {
+            WriteFile(state->fd, buffer + i, 1, &ret, NULL);
+        }
+        ret = 0;
+        while (ret == 0) {
+            ReadFile(state->fd, &c, 1, &ret, NULL);
+        }
+#else
+        while (ulinux_write(state->fd, buffer + i, 1) != 1) ;
+        while (ulinux_read(state->fd, &c, 1) != 1) ;
+#endif
+        if (c != buffer[i] && !handshake_mode) {
+            printk(BIOS_ERR, "Readback error! %x/%x\n", c, buffer[i]);
+        }
+    }
+
+    return nbyte;
+}
+
+static int serialice_wait_prompt(void)
+{
+    char buf[3];
+    int l;
+
+    l = serialice_read(s, buf, 3);
+
+    if (l == -1) {
+        perror("SerialICE: Could not read from target");
+        ulinux_exit(1);
+    }
+
+    while (buf[0] != '\n' || buf[1] != '>' || buf[2] != ' ') {
+        buf[0] = buf[1];
+        buf[1] = buf[2];
+        l = serialice_read(s, buf + 2, 1);
+        if (l == -1) {
+            perror("SerialICE: Could not read from target");
+            ulinux_exit(1);
+        }
+    }
+
+    return 0;
+}
+
+static void serialice_command(const char *command, int reply_len)
+{
+#if SERIALICE_DEBUG > 5
+    int i;
+#endif
+    int l;
+    
+    if (!serialice_active) {
+        printk(BIOS_ERR, "SerialICE not ready yet (ignoring)\n");
+	return;
+    }
+
+    serialice_wait_prompt();
+
+    serialice_write(s, command, strlen(command));
+
+    memset(s->buffer, 0, reply_len + 1);        // clear enough of the buffer
+
+    l = serialice_read(s, s->buffer, reply_len);
+
+    if (l == -1) {
+        perror("SerialICE: Could not read from target");
+        ulinux_exit(1);
+    }
+    // compensate for CR on the wire. Needed on Win32
+    if (s->buffer[0] == '\r') {
+        memmove(s->buffer, s->buffer + 1, reply_len);
+        serialice_read(s, s->buffer + reply_len - 1, 1);
+    }
+
+    if (l != reply_len) {
+        printk(BIOS_ERR, "SerialICE: command was not answered sufficiently: "
+               "(%d/%d bytes)\n'%s'\n", l, reply_len, s->buffer);
+        ulinux_exit(1);
+    }
+#if SERIALICE_DEBUG > 5
+    for (i = 0; i < reply_len; i++) {
+        printk(BIOS_ERR, "%02x ", s->buffer[i]);
+    }
+    printk(BIOS_ERR, "\n");
+#endif
+}
+
+// **************************************************************************
+// high level communication with the SerialICE shell
+
+static void serialice_get_version(void)
+{
+    int len = 0;
+    printk(BIOS_INFO, "SerialICE: Version.....: ");
+    serialice_command("*vi", 0);
+
+    memset(s->buffer, 0, BUFFER_SIZE);
+    serialice_read(s, s->buffer, 1);
+    serialice_read(s, s->buffer, 1);
+    while (s->buffer[len++] != '\n') {
+        serialice_read(s, s->buffer + len, 1);
+    }
+    s->buffer[len - 1] = '\0';
+
+    printk(BIOS_INFO, "%s\n", s->buffer);
+}
+
+static void serialice_get_mainboard(void)
+{
+}
+
+uint8_t serialice_inb(uint16_t port)
+{
+    uint8_t ret;
+
+    sprintf(s->command, "*ri%04x.b", port);
+    // command read back: "\n00" (3 characters)
+    serialice_command(s->command, 3);
+    ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+    serialice_log(LOG_READ | LOG_IO, ret, port, 1);
+
+    return ret;
+}
+
+uint16_t serialice_inw(uint16_t port)
+{
+    uint16_t ret;
+
+    sprintf(s->command, "*ri%04x.w", port);
+    // command read back: "\n0000" (5 characters)
+    serialice_command(s->command, 5);
+    ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+    serialice_log(LOG_READ | LOG_IO, ret, port, 2);
+
+    return ret;
+}
+
+uint32_t serialice_inl(uint16_t port)
+{
+    uint32_t ret;
+
+    sprintf(s->command, "*ri%04x.l", port);
+    // command read back: "\n00000000" (9 characters)
+    serialice_command(s->command, 9);
+    ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+
+    serialice_log(LOG_READ | LOG_IO, ret, port, 4);
+
+    return ret;
+}
+
+void serialice_outb(uint8_t data, uint16_t port)
+{
+    serialice_log(LOG_WRITE | LOG_IO, data, port, 1);
+
+    sprintf(s->command, "*wi%04x.b=%02x", port, data);
+    serialice_command(s->command, 0);
+}
+
+void serialice_outw(uint16_t data, uint16_t port)
+{
+    serialice_log(LOG_WRITE | LOG_IO, data, port, 2);
+
+    sprintf(s->command, "*wi%04x.w=%04x", port, data);
+    serialice_command(s->command, 0);
+}
+
+void serialice_outl(uint32_t data, uint16_t port)
+{
+    serialice_log(LOG_WRITE | LOG_IO, data, port, 4);
+
+    sprintf(s->command, "*wi%04x.l=%08x", port, data);
+    serialice_command(s->command, 0);
+}
+
+uint8_t serialice_readb(uint32_t addr)
+{
+    uint8_t ret;
+    sprintf(s->command, "*rm%08x.b", addr);
+    // command read back: "\n00" (3 characters)
+    serialice_command(s->command, 3);
+    ret = (uint8_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+    serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 1);
+
+    return ret;
+}
+
+uint16_t serialice_readw(uint32_t addr)
+{
+    uint16_t ret;
+    sprintf(s->command, "*rm%08x.w", addr);
+    // command read back: "\n0000" (5 characters)
+    serialice_command(s->command, 5);
+    ret = (uint16_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+    serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 2);
+
+    return ret;
+}
+
+uint32_t serialice_readl(uint32_t addr)
+{
+    uint32_t ret;
+    sprintf(s->command, "*rm%08x.l", addr);
+    // command read back: "\n00000000" (9 characters)
+    serialice_command(s->command, 9);
+    ret = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+    serialice_log(LOG_READ | LOG_MEMORY, ret, addr, 4);
+
+    return ret;
+}
+
+void serialice_writeb(uint8_t data, uint32_t addr)
+{
+    serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 1);
+    sprintf(s->command, "*wm%08x.b=%02x", addr, data);
+    serialice_command(s->command, 0);
+}
+
+void serialice_writew(uint16_t data, uint32_t addr)
+{
+    serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 2);
+    sprintf(s->command, "*wm%08x.w=%04x", addr, data);
+    serialice_command(s->command, 0);
+}
+
+void serialice_writel(uint32_t data, uint32_t addr)
+{
+    serialice_log(LOG_WRITE | LOG_MEMORY, data, addr, 4);
+    sprintf(s->command, "*wm%08x.l=%08x", addr, data);
+    serialice_command(s->command, 0);
+}
+
+uint64_t serialice_rdmsr(uint32_t addr, uint32_t key)
+{
+    uint32_t hi, lo;
+    uint64_t ret;
+    int filtered = 0;
+
+        sprintf(s->command, "*rc%08x.%08x", addr, key);
+
+        // command read back: "\n00000000.00000000" (18 characters)
+        serialice_command(s->command, 18);
+
+        s->buffer[9] = 0;       // . -> \0
+        hi = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+        lo = (uint32_t) strtoul(s->buffer + 10, (char **)NULL, 16);
+
+    ret = hi;
+    ret <<= 32;
+    ret |= lo;
+
+    serialice_msr_log(LOG_READ, addr, hi, lo, filtered);
+
+    return ret;
+}
+
+void serialice_wrmsr(uint64_t data, uint32_t addr, uint32_t key)
+{
+    uint32_t hi, lo;
+    int filtered = 0;
+
+    hi = (data >> 32);
+    lo = (data & 0xffffffff);
+
+    if (!filtered) {
+        sprintf(s->command, "*wc%08x.%08x=%08x.%08x", addr, key, hi, lo);
+        serialice_command(s->command, 0);
+    }
+
+    serialice_msr_log(LOG_WRITE, addr, hi, lo, filtered);
+}
+
+cpuid_regs_t serialice_cpuid(uint32_t eax, uint32_t ecx)
+{
+    cpuid_regs_t ret;
+
+    ret.eax = eax;
+    ret.ebx = 0;                // either set by filter or by target
+    ret.ecx = ecx;
+    ret.edx = 0;                // either set by filter or by target
+
+    sprintf(s->command, "*ci%08x.%08x", eax, ecx);
+
+    // command read back: "\n000006f2.00000000.00001234.12340324"
+    // (36 characters)
+    serialice_command(s->command, 36);
+
+    s->buffer[9] = 0;           // . -> \0
+    s->buffer[18] = 0;          // . -> \0
+    s->buffer[27] = 0;          // . -> \0
+    ret.eax = (uint32_t) strtoul(s->buffer + 1, (char **)NULL, 16);
+    ret.ebx = (uint32_t) strtoul(s->buffer + 10, (char **)NULL, 16);
+    ret.ecx = (uint32_t) strtoul(s->buffer + 19, (char **)NULL, 16);
+    ret.edx = (uint32_t) strtoul(s->buffer + 28, (char **)NULL, 16);
+
+    serialice_cpuid_log(eax, ecx, ret, 0);
+
+    return ret;
+}
+
+// **************************************************************************
+// initialization and exit
+
+void serialice_init(void)
+{
+    printk(BIOS_INFO, "SerialICE: Open connection to target hardware...\n");
+
+    if (serialice_device == NULL) {
+        printk(BIOS_INFO, "You need to specify a serial device to use SerialICE.\n");
+        ulinux_exit(1);
+    }
+#ifdef WIN32
+    s->fd = CreateFile(serialice_device, GENERIC_READ | GENERIC_WRITE,
+                       0, NULL, OPEN_EXISTING, 0, NULL);
+
+    if (s->fd == INVALID_HANDLE_VALUE) {
+        perror("SerialICE: Could not connect to target TTY");
+        ulinux_exit(1);
+    }
+
+    DCB dcb;
+    if (!GetCommState(s->fd, &dcb)) {
+        perror("SerialICE: Could not load config for target TTY");
+        ulinux_exit(1);
+    }
+
+    dcb.BaudRate = CBR_115200;
+    dcb.ByteSize = 8;
+    dcb.Parity = NOPARITY;
+    dcb.StopBits = ONESTOPBIT;
+
+    if (!SetCommState(s->fd, &dcb)) {
+        perror("SerialICE: Could not store config for target TTY");
+        ulinux_exit(1);
+    }
+#else
+    s->fd = ulinux_open(serialice_device, O_RDWR | O_NOCTTY | O_NONBLOCK);
+
+    if (s->fd == -1) {
+        perror("SerialICE: Could not connect to target TTY");
+        ulinux_exit(1);
+    }
+
+    if (ulinux_ioctl(s->fd, TIOCEXCL) == -1) {
+        perror("SerialICE: TTY not exclusively available");
+        ulinux_exit(1);
+    }
+
+    if (ulinux_fcntl(s->fd, F_SETFL, 0) == -1) {
+        perror("SerialICE: Could not switch to blocking I/O");
+        ulinux_exit(1);
+    }
+
+    if (ulinux_tcgetattr(s->fd, &options) == -1) {
+        perror("SerialICE: Could not get TTY attributes");
+        ulinux_exit(1);
+    }
+
+    ulinux_cfsetispeed(&options, B115200);
+    ulinux_cfsetospeed(&options, B115200);
+
+    /* set raw input, 1 second timeout */
+    options.c_cflag |= (CLOCAL | CREAD);
+    options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG);
+    options.c_oflag &= ~OPOST;
+    options.c_iflag |= IGNCR;
+    options.c_cc[VMIN] = 0;
+    options.c_cc[VTIME] = 100;
+
+    ulinux_tcsetattr(s->fd, TCSANOW, &options);
+
+    ulinux_tcflush(s->fd, TCIOFLUSH);
+#endif
+
+    s->buffer = bb;
+    s->command = cc;
+
+    printk(BIOS_INFO, "SerialICE: Waiting for handshake with target... ");
+
+    handshake_mode = 1;         // Readback errors are to be expected in this phase.
+
+    /* Trigger a prompt */
+    serialice_write(s, "\n\n\n\n", 4);
+    serialice_write(s, "\n\n\n\n", 4);
+
+    /* ... and wait for it to appear */
+    if (serialice_wait_prompt() == 0) {
+        printk(BIOS_INFO, "target alive!\n");
+        serialice_active = 1;
+    } else {
+        printk(BIOS_INFO, "target not ok!\n");
+        ulinux_exit(1);
+    }
+
+    /* Each serialice_command() waits for a prompt, so trigger one for the
+     * first command, as we consumed the last one for the handshake
+     */
+    serialice_write(s, "@", 1);
+
+    handshake_mode = 0;         // from now on, warn about readback errors.
+
+    serialice_get_version();
+
+    serialice_get_mainboard();
+
+    /* Let the rest of Qemu know we're alive */
+}
+



From gerrit at coreboot.org  Tue Jun  5 01:02:29 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:29 +0200
Subject: [coreboot] New patch to review for coreboot: dd11f54 Add MSR
	support for serialICE.
References: <Ib33f91839d2a1b07314dc4b0f6aead00c47f1b08+0@gerrit.coreboot.org>
Message-ID: <Ib33f91839d2a1b07314dc4b0f6aead00c47f1b08+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1095

-gerrit

commit dd11f547bb130790fbe1d0f8b17591be50faf6ec
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:27:54 2012 +0200

    Add MSR support for serialICE.
    
    Adds MSR support forwarding, no password key yet, cpuid is missing.
    
    Change-Id: Ib33f91839d2a1b07314dc4b0f6aead00c47f1b08
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/include/cpu/x86/msr.h |   15 ++++++++++++++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 40926df..0ba3910 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -16,7 +16,7 @@ static void wrmsr(unsigned long index, msr_t msr)
 }
 
 #else
-
+#include <serialice_host.h>
 typedef struct msr_struct
 {
 	unsigned lo;
@@ -42,21 +42,34 @@ typedef struct msrinit_struct
 static inline __attribute__((always_inline)) msr_t rdmsr(unsigned index)
 {
 	msr_t result;
+#if defined(__PRE_RAM__)
 	__asm__ __volatile__ (
 		"rdmsr"
 		: "=a" (result.lo), "=d" (result.hi)
 		: "c" (index)
 		);
 	return result;
+
+#else
+	int64_t ret =  serialice_rdmsr(index, 0);
+	result.lo = ret & 0xffffffff;
+	result.hi = (ret >> 32) & 0xffffffff;
+	return result;
+#endif
 }
 
 static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t msr)
 {
+
+#if defined(__PRE_RAM__) || CONFIG_ULINUX == 0
 	__asm__ __volatile__ (
 		"wrmsr"
 		: /* No outputs */
 		: "c" (index), "a" (msr.lo), "d" (msr.hi)
 		);
+#else
+     serialice_wrmsr ((((uint64_t) msr.hi) << 32) | msr.lo, index, 0);
+#endif
 }
 
 #endif /* __ROMCC__ */



From gerrit at coreboot.org  Tue Jun  5 01:02:29 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:29 +0200
Subject: [coreboot] New patch to review for coreboot: 2eea342 Hack in the
	target part of serialICE this needs to be done in more sane way.
References: <I4b39eba9526bdd21e99044bc5f67106176d26e2b+0@gerrit.coreboot.org>
Message-ID: <I4b39eba9526bdd21e99044bc5f67106176d26e2b+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1096

-gerrit

commit 2eea3421b95a5b1127805ac623ea5a16cfae2e83
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:29:45 2012 +0200

    Hack in the target part of serialICE this needs to be done in more sane way.
    
    Just some quick and dirty way of using real serialICE.
    
    Change-Id: I4b39eba9526bdd21e99044bc5f67106176d26e2b
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/arch/x86/lib/cbfs_and_run.c |    5 +-
 src/lib/Makefile.inc            |    1 +
 src/lib/serialice/serial.c      |  196 ++++++++++++++++++++++++++++++
 src/lib/serialice/serialice.c   |  256 +++++++++++++++++++++++++++++++++++++++
 src/lib/serialice/serialice.h   |   31 +++++
 5 files changed, 487 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 62b2789..a63e50d 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -25,7 +25,6 @@
 static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
-
 	timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
@@ -40,13 +39,15 @@ static void cbfs_and_run_core(const char *filename, unsigned ebp)
 		:: "a"(ebp), "D"(dst)
 	);
 }
-
+void serialice_main(void);
 void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
 {
 	// FIXME fix input parameters instead normalizing them here.
 	if (cpu_reset == 1) cpu_reset = -1;
 	else cpu_reset = 0;
 
+	serialice_main();
+
 	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
 }
 
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 3bd7f99..e6ae8b6 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -21,6 +21,7 @@ romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 romstage-y += compute_ip_checksum.c
 romstage-y += memmove.c
+romstage-y += serialice/serialice.c
 
 ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
diff --git a/src/lib/serialice/serial.c b/src/lib/serialice/serial.c
new file mode 100644
index 0000000..529009c
--- /dev/null
+++ b/src/lib/serialice/serial.c
@@ -0,0 +1,196 @@
+/*
+ * SerialICE 
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+/* SIO functions */
+
+static void sio_init(void)
+{
+#if SIO_SPEED > 115200
+	/* "high speed" serial requires special chip setup
+	 * (to be done in superio_init), and special divisor
+	 * values (implement superio_serial_divisor() for that).
+	 * Maybe it requires even more, but so far that seems
+	 * to be enough.
+	 */
+	int divisor = superio_serial_divisor(SIO_SPEED);
+#else
+	int divisor = 115200 / SIO_SPEED;
+#endif
+	int lcs = 3;
+	outb(0x00, SIO_PORT + UART_IER);
+	outb(0x01, SIO_PORT + UART_FCR);
+	outb(0x03, SIO_PORT + UART_MCR);
+	outb(0x80 | lcs, SIO_PORT + UART_LCR);
+	outb(divisor & 0xff, SIO_PORT + UART_DLL);
+	outb((divisor >> 8) & 0xff, SIO_PORT + UART_DLM);
+	outb(lcs, SIO_PORT + UART_LCR);
+}
+
+static void sio_putc(u8 data)
+{
+	while (!(inb(SIO_PORT + UART_LSR) & 0x20)) ;
+	outb(data, SIO_PORT + UART_TBR);
+	while (!(inb(SIO_PORT + UART_LSR) & 0x40)) ;
+}
+
+static u8 sio_getc(void)
+{
+	u8 val;
+	while (!(inb(SIO_PORT + UART_LSR) & 0x01)) ;
+
+	val = inb(SIO_PORT + UART_RBR);
+
+#if ECHO_MODE
+	sio_putc(val);
+#endif
+	return val;
+}
+
+/* SIO helpers */
+
+static void sio_putstring(const char *string)
+{
+	/* Very simple, no %d, %x etc. */
+	while (*string) {
+		if (*string == '\n')
+			sio_putc('\r');
+		sio_putc(*string);
+		string++;
+	}
+}
+
+#define sio_put_nibble(nibble)	\
+	if (nibble > 9)		\
+		nibble += ('a' - 10);	\
+	else			\
+		nibble += '0';	\
+	sio_putc(nibble)
+
+static void sio_put8(u8 data)
+{
+	u8 c;
+		
+	c = (data >> 4) & 0xf;
+	sio_put_nibble(c);
+
+	c = data & 0xf;
+	sio_put_nibble(c);
+}
+
+static void sio_put16(u16 data)
+{
+	int i;
+	for (i=12; i >= 0; i -= 4) {
+		u8 c = (data >> i) & 0xf;
+		sio_put_nibble(c);
+	}
+}
+
+static void sio_put32(u32 data)
+{
+	int i;
+	for (i=28; i >= 0; i -= 4) {
+		u8 c = (data >> i) & 0xf;
+		sio_put_nibble(c);
+	}
+}
+
+static u8 sio_get_nibble(void)
+{
+	u8 ret = 0;
+	u8 nibble = sio_getc();
+
+	if (nibble >= '0' && nibble <= '9') {
+		ret = (nibble - '0');
+	} else if (nibble >= 'a' && nibble <= 'f') {
+		ret = (nibble - 'a') + 0xa;
+	} else if (nibble >= 'A' && nibble <= 'F') {
+		ret = (nibble - 'A') + 0xa;
+	} else {
+		sio_putstring("ERROR: parsing number\n");
+	}
+	return ret;
+}
+
+static u8 sio_get8(void)
+{
+	u8 data;
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	return data;
+}
+
+static u16 sio_get16(void)
+{
+	u16 data;
+
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+
+	return data;
+}
+
+static u32 sio_get32(void)
+{
+	u32 data;
+
+	data = sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+	data = data << 4;
+	data |= sio_get_nibble();
+
+	return data;
+}
+
+
diff --git a/src/lib/serialice/serialice.c b/src/lib/serialice/serialice.c
new file mode 100644
index 0000000..0a5a8e0
--- /dev/null
+++ b/src/lib/serialice/serialice.c
@@ -0,0 +1,256 @@
+/*
+ * SerialICE 
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "serialice.h"
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <arch/cpu.h>
+
+const char boardname[33]="infinite improbability board    ";
+
+
+/* Hardware specific functions */
+
+/* SIO functions */
+#include "serial.c"
+
+/* Accessor functions */
+
+static void serialice_read_memory(void)
+{
+	u8 width;
+	u32 addr;
+
+	// Format:
+	// *rm00000000.w
+	addr = sio_get32();
+	sio_getc();	// skip .
+	width = sio_getc();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	switch (width) {
+	case 'b': sio_put8(read8(addr)); break;
+	case 'w': sio_put16(read16(addr)); break;
+	case 'l': sio_put32(read32(addr)); break;
+	}
+}
+
+static void serialice_write_memory(void)
+{
+	u8 width;
+	u32 addr;
+	u32 data;
+
+	// Format:
+	// *wm00000000.w=0000
+	addr = sio_get32();
+	sio_getc();	// skip .
+	width = sio_getc();
+	sio_getc();	// skip =
+
+	switch (width) {
+	case 'b': data = sio_get8(); write8(addr, (u8)data); break;
+	case 'w': data = sio_get16(); write16(addr, (u16)data); break;
+	case 'l': data = sio_get32(); write32(addr, (u32)data); break;
+	}
+}
+
+static void serialice_read_io(void)
+{
+	u8 width;
+	u16 port;
+
+	// Format:
+	// *ri0000.w
+	port = sio_get16();
+	sio_getc();	// skip .
+	width = sio_getc();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	switch (width) {
+	case 'b': sio_put8(inb(port)); break;
+	case 'w': sio_put16(inw(port)); break;
+	case 'l': sio_put32(inl(port)); break;
+	}
+}
+
+static void serialice_write_io(void)
+{
+	u8 width;
+	u16 port;
+	u32 data;
+
+	// Format:
+	// *wi0000.w=0000
+	port = sio_get16();
+	sio_getc();	// skip .
+	width = sio_getc();
+	sio_getc();	// skip =
+
+	switch (width) {
+	case 'b': data = sio_get8(); outb((u8)data, port); break;
+	case 'w': data = sio_get16(); outw((u16)data, port); break;
+	case 'l': data = sio_get32(); outl((u32)data, port); break;
+	}
+}
+
+static void serialice_read_msr(void)
+{
+	u32 addr, key;
+	msr_t msr;
+
+	// Format:
+	// *rc00000000.9c5a203a
+	addr = sio_get32();
+	sio_getc();	   // skip .
+	key = sio_get32(); // key in %edi
+
+	sio_putc('\r'); sio_putc('\n');
+
+	msr = rdmsr(addr);
+	sio_put32(msr.hi);
+	sio_putc('.');
+	sio_put32(msr.lo);
+}
+
+static void serialice_write_msr(void)
+{
+	u32 addr, key;
+	msr_t msr;
+
+	// Format:
+	// *wc00000000.9c5a203a=00000000.00000000
+	addr = sio_get32();
+	sio_getc();	// skip .
+	key = sio_get32(); // read key in %edi
+	sio_getc();	// skip =
+	msr.hi = sio_get32();
+	sio_getc();	// skip .
+	msr.lo = sio_get32();
+
+#ifdef __ROMCC__
+	/* Cheat to avoid register outage */
+	wrmsr(addr, msr, 0x9c5a203a);
+#else
+	wrmsr(addr, msr);
+#endif
+}
+
+static void serialice_cpuinfo(void)
+{
+	u32 eax, ecx;
+	u32 reg32 = 0xdeadbeef;
+
+	// Format:
+	//    --EAX--- --ECX---
+	// *ci00000000.00000000
+	eax = sio_get32();
+	sio_getc(); // skip .
+	ecx = sio_get32();
+
+	sio_putc('\r'); sio_putc('\n');
+
+	/* This code looks quite crappy but this way we don't
+ 	 * have to worry about running out of registers if we
+ 	 * occupy eax, ebx, ecx, edx at the same time 
+ 	 */
+//	reg32 = cpuid_eax(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+//	reg32 = cpuid_ebx(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+//	reg32 = cpuid_ecx(eax, ecx);
+	sio_put32(reg32);
+	sio_putc('.');
+
+//	reg32 = cpuid_edx(eax, ecx);
+	sio_put32(reg32);
+}
+
+static void serialice_mainboard(void)
+{
+	sio_putc('\r'); sio_putc('\n');
+
+	/* must be defined in mainboard/<boardname>.c */
+	sio_putstring(boardname);
+}
+
+static void serialice_version(void)
+{
+	sio_putstring("\nSerialICE v" VERSION " (" __DATE__ ")\n");
+}
+void serialice_main(void);
+
+void serialice_main(void)
+{
+	sio_init();
+	serialice_version();
+
+	while(1) {
+		u16 c;
+		sio_putstring("\n> ");
+
+		c = sio_getc();
+		if (c != '*')
+			continue;
+
+		c = sio_getc() << 8;
+		c |= sio_getc();
+
+		switch(c) {
+		case (('r' << 8)|'m'): // Read Memory *rm
+			serialice_read_memory();
+			break;
+		case (('w' << 8)|'m'): // Write Memory *wm
+			serialice_write_memory();
+			break;
+		case (('r' << 8)|'i'): // Read IO *ri
+			serialice_read_io();
+			break;
+		case (('w' << 8)|'i'): // Write IO *wi
+			serialice_write_io();
+			break;
+		case (('r' << 8)|'c'): // Read CPU MSR *rc
+			serialice_read_msr();
+			break;
+		case (('w' << 8)|'c'): // Write CPU MSR *wc
+			serialice_write_msr();
+			break;
+		case (('c' << 8)|'i'): // Read CPUID *ci
+			serialice_cpuinfo();
+			break;
+		case (('m' << 8)|'b'): // Read mainboard type *mb
+			serialice_mainboard();
+			break;
+		case (('v' << 8)|'i'): // Read version info *vi
+			serialice_version();
+			break;
+		default:
+			sio_putstring("ERROR\n");
+			break;
+		}
+	}
+
+	// Never get here:
+}
diff --git a/src/lib/serialice/serialice.h b/src/lib/serialice/serialice.h
new file mode 100644
index 0000000..1d01849
--- /dev/null
+++ b/src/lib/serialice/serialice.h
@@ -0,0 +1,31 @@
+/*
+ * SerialICE 
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SERIALICE_H
+#define SERIALICE_H
+
+#include "config.h"
+
+#define ECHO_MODE	1
+
+#define VERSION "42"
+#define SIO_SPEED	115200
+#define SIO_PORT	0x3f8
+
+#endif



From gerrit at coreboot.org  Tue Jun  5 01:02:30 2012
From: gerrit at coreboot.org (Rudolf Marek (r.marek@assembler.cz))
Date: Tue, 5 Jun 2012 01:02:30 +0200
Subject: [coreboot] New patch to review for coreboot: 2551459 Random VIA
	fixups to make it faster or non-crashing
References: <I029091973cee3dafc39a8d4b18aae4d8c6d10127+0@gerrit.coreboot.org>
Message-ID: <I029091973cee3dafc39a8d4b18aae4d8c6d10127+1@gerrit.coreboot.org>

Rudolf Marek (r.marek at assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1097

-gerrit

commit 255145949fe31a194c8e47b0af0d73b6775907c3
Author: Rudolf Marek <r.marek at assembler.cz>
Date:   Tue Jun 5 00:31:09 2012 +0200

    Random VIA fixups to make it faster or non-crashing
    
    IOAPIC uses now read32/write32 which is redirected, possibly even better is to use common IOAPIC setup
    ditch out the dump of PCI space, it takes way a lot time with serialICE.
    
    Change-Id: I029091973cee3dafc39a8d4b18aae4d8c6d10127
    Signed-off-by: Rudolf Marek <r.marek at assembler.cz>
---
 src/southbridge/via/k8t890/pcie.c      |    7 ++++++-
 src/southbridge/via/k8t890/traf_ctrl.c |   14 +++++++-------
 src/southbridge/via/vt8237r/vt8237r.c  |    2 ++
 3 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/southbridge/via/k8t890/pcie.c b/src/southbridge/via/k8t890/pcie.c
index 2840bf3..6ec1c41 100644
--- a/src/southbridge/via/k8t890/pcie.c
+++ b/src/southbridge/via/k8t890/pcie.c
@@ -35,6 +35,11 @@ static void pcie_common_init(struct device *dev)
 {
 	u8 reg;
 	int i, up;
+#if CONFIG_ULINUX
+	int loops = 2;
+#else
+	int loops = 1000;
+#endif
 
 	/* Disable downstream read cycle retry,
 	 * otherwise the bus scan will hang if no device is plugged in. */
@@ -64,7 +69,7 @@ static void pcie_common_init(struct device *dev)
 
 	/* Wait up to 100ms for link to come up */
 	up = 0;
-	for (i=0; i<1000; i++) {
+	for (i=0; i<loops; i++) {
 		if (pci_read_config16(dev, 0x52) & (1<<13)) {
 			up = 1;
 			break;
diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c
index d3ed1e7..c55052c 100644
--- a/src/southbridge/via/k8t890/traf_ctrl.c
+++ b/src/southbridge/via/k8t890/traf_ctrl.c
@@ -21,6 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <console/console.h>
+#include <arch/io.h>
 #include "k8t890.h"
 
 extern unsigned long log2(unsigned long x);
@@ -96,14 +97,13 @@ static void traf_ctrl_enable_generic(struct device *dev)
 	apic = (u32 *)K8T890_APIC_BASE;
 
 	/* Set APIC to FSB transported messages. */
-	apic[0] = 3;
-	data = apic[4];
-	apic[4] = (data & 0xFFFFFE) | 1;
-
+	write32(K8T890_APIC_BASE, 3);
+	data = read32(K8T890_APIC_BASE + 0x10);
+	write32(K8T890_APIC_BASE + 0x10, (data & 0xFFFFFE) | 1);
 	/* Set APIC ID. */
-	apic[0] = 0;
-	data = apic[4];
-	apic[4] = (data & 0xF0FFFF) | (K8T890_APIC_ID << 24);
+	write32(K8T890_APIC_BASE, 0);
+	data = read32(K8T890_APIC_BASE + 0x10);
+	write32(K8T890_APIC_BASE + 0x10, (data & 0xF0FFFF) | (K8T890_APIC_ID << 24));
 }
 
 static void traf_ctrl_enable_k8m890(struct device *dev)
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 586df66..c8eaca1 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -54,6 +54,7 @@ void writeback(struct device *dev, u16 where, u8 what)
 
 void dump_south(device_t dev)
 {
+#if CONFIG_ULINUX == 0
 	int i, j;
 
 	for (i = 0; i < 256; i += 16) {
@@ -62,6 +63,7 @@ void dump_south(device_t dev)
 			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i + j));
 		printk(BIOS_DEBUG, "\n");
 	}
+#endif
 }
 
 static void vt8237r_enable(struct device *dev)



From r.marek at assembler.cz  Tue Jun  5 01:03:17 2012
From: r.marek at assembler.cz (Rudolf Marek)
Date: Tue, 05 Jun 2012 01:03:17 +0200
Subject: [coreboot] coreboot runs in linux userspace
Message-ID: <4FCD3EB5.90003@assembler.cz>

Hi all,

I had this long in mind, now it works, coreboot can be run as Linux process and 
IO is done through a serialICE. This is handy for debugging and valgrinding, or 
maybe handy for zillions of other reasons.

How it works:

ruik at ruik:~/coreboot$ gdb ./build/cbfs/fallback/coreboot_ram.elf
(gdb) run
Starting program: /home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf
POST: 0x80
IO WRITE: [00000080] 00000080 size 1
SerialICE not ready yet (ignoring)
POST: 0x39
IO WRITE: [00000080] 00000039 size 1
SerialICE not ready yet (ignoring)
coreboot-4.0-2408-gad422c0-dirty Tue Jun  5 00:04:52 CEST 2012 booting...
POST: 0x40
IO WRITE: [00000080] 00000040 size 1
SerialICE not ready yet (ignoring)
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
PCI_DOMAIN: 0000: enabled 1

....

Or when it crashes:

Root Device init
APIC_CLUSTER: 0 init
MSR WRITE: [0000001b] 00000000fee00900
MSR READ: [0000001b] 00000000fee00900
MEM READ: [fee00020] 00000000 size 4
==13541== Invalid read of size 1
==13541==    at 0x106C0E: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x10991B: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x10AD0B: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x10BA3F: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x10C232: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x106F99: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x10003D: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==    by 0x127347: ??? (in 
/home/ruik/coreboot/build/cbfs/fallback/coreboot_ram.elf)
==13541==  Address 0xa000 is not stack'd, malloc'd or (recently) free'd
==13541==
==13541==
==13541== Process terminating with default action of signal 11 (SIGSEGV)
==13541==  Access not within mapped region at address 0xA000


Please note that valgrind is confused with our debug symbols, but gdb works fine.

In general, the real coreboot jumps to hacked version of serial ICE and waits.
The userspace program is run as any process and hacked version serialICE host 
from qemu talks normally to linux kernel (this is done via custom 0x80 calls)

no libc is used, even the memory layout is same. The only memory mapped is what 
ELF has and also highmem/lowmem bits (check ulinux_mmap calls).

It is still very experimental but works fine. I put together quickly some 
patches which may be found here:

emote: New Changes:
remote:   http://review.coreboot.org/1089
remote:   http://review.coreboot.org/1090
remote:   http://review.coreboot.org/1091
remote:   http://review.coreboot.org/1092
remote:   http://review.coreboot.org/1093
remote:   http://review.coreboot.org/1094
remote:   http://review.coreboot.org/1095
remote:   http://review.coreboot.org/1096
remote:   http://review.coreboot.org/1097

Thanks
Rudolf




From ward at fsf.org  Mon Jun  4 19:01:04 2012
From: ward at fsf.org (Ward Vandewege)
Date: Mon, 4 Jun 2012 13:01:04 -0400
Subject: [coreboot] New Motherboards?
In-Reply-To: <1338827363.6720.86.camel@myrtle.6gnip.net>
References: <CAMBnPoAnS5pf-uXGViB5GRcQZsEV2cLK=291GF2_ROx_WKqypg@mail.gmail.com>
	<CAP6exYK_fUs494AJaZzFN9fhgpfSPBZ90BfAC64B0SgEwtrOVg@mail.gmail.com>
	<1338824583.6720.66.camel@myrtle.6gnip.net>
	<CAP6exYKm3tcocJbtMknzCyeEkbf-v9TabSbbvP_WNTtBnw1wKQ@mail.gmail.com>
	<1338826243.6720.81.camel@myrtle.6gnip.net>
	<CAP6exYK4Twy03wjaD9vxBc-pRdod3S5fwcqODPET0LqC9+q4qA@mail.gmail.com>
	<1338827363.6720.86.camel@myrtle.6gnip.net>
Message-ID: <20120604170104.GA24923@countzero.vandewege.net>

On Mon, Jun 04, 2012 at 05:29:23PM +0100, Bob Ham wrote:
> On Mon, 2012-06-04 at 09:15 -0700, ron minnich wrote:
> > On Mon, Jun 4, 2012 at 9:10 AM, Bob Ham <rah at settrans.net> wrote:
> > 
> > > Not PCI-E or PCI-X, just normal PCI.
> > 
> > Wow. More than one? How many?
> 
> Two; I have two identical M-Audio Delta 1010s.

Finding a modern board with two 'old' PCI slots may be difficult, regardless
of coreboot... Have you seen any at all?

Thanks,
Ward.

-- 
Ward Vandewege | CTO, Free Software Foundation
GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS

Do you use free software? Donate to join the FSF and support freedom at
         http://www.fsf.org/register_form?referrer=859



From andywyse6 at gmail.com  Mon Jun  4 21:42:39 2012
From: andywyse6 at gmail.com (Andy Sharp)
Date: Mon, 4 Jun 2012 12:42:39 -0700
Subject: [coreboot] amd/persimmon does not scan behind bridge on sb800
	southbridge
Message-ID: <CAHgS8JXeEXtmuXAc-Fvfc2gEK9MzT2fbT+YYfEwOR+cRbq+ZGg@mail.gmail.com>

Howdy,

I've got an amd/persimmon board, and when I build the coreboot for it from
the tree, it only finds the PCIe devices directly attached to the CPU, but
not any of the ones hanging off the sb800 southbridge.  Anyone have any
clues for me?

Thanks!

coreboot console log:



coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
starting...
POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000000
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000001
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly passed.
SLP_TYP type was 0
POST: 0x40
agesawrapper_amdinitpost
EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.
SLP_TYP type was 0
error level: 4
POST: 0x42
agesawrapper_amdinitenv SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
POST: 0x43
POST: 0x44
POST: 0x50
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry
@ 0x200000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:05.0: enabled 0
  PCI: 00:06.0: enabled 0
  PCI: 00:07.0: enabled 0
  PCI: 00:08.0: enabled 0
  PCI: 00:11.0: enabled 1
  PCI: 00:12.0: enabled 1
  PCI: 00:12.1: enabled 1
  PCI: 00:12.2: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:13.1: enabled 1
  PCI: 00:13.2: enabled 1
  PCI: 00:14.0: enabled 1
   I2C: 00:50: enabled 1
   I2C: 00:51: enabled 1
  PCI: 00:14.1: enabled 1
  PCI: 00:14.2: enabled 1
  PCI: 00:14.3: enabled 1
   PNP: 004e.0: enabled 0
   PNP: 004e.3: enabled 0
   PNP: 004e.4: enabled 0
   PNP: 004e.5: enabled 1
   PNP: 004e.6: enabled 0
   PNP: 004e.a: enabled 0
   PNP: 004e.10: enabled 1
   PNP: 004e.11: enabled 0
  PCI: 00:14.4: enabled 1
  PCI: 00:14.5: enabled 1
  PCI: 00:15.0: enabled 0
  PCI: 00:15.1: enabled 0
  PCI: 00:15.2: enabled 0
  PCI: 00:15.3: enabled 0
  PCI: 00:16.0: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:18.0: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
  PCI: 00:18.5: enabled 1
  PCI: 00:18.6: enabled 1
  PCI: 00:18.7: enabled 1
Mainboard Persimmon Enable.
SLP_TYP type was 0
persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
persimmon_enable: uma size 0x18000000, memory start 0x67000000
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9804] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/1512] enabled
sb800_enable() SLP_TYP type was 0
PCI: 00:11.0 [1002/4393] ops
PCI: 00:11.0 [1002/4393] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable()
sb800_enable() PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
POST: 0x25
PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:14.3
PNP: 004e.0 disabled
PNP: 004e.3 disabled
PNP: 004e.4 disabled
PNP: 004e.5 enabled
PNP: 004e.6 disabled
PNP: 004e.a disabled
PNP: 004e.10 enabled
PNP: 004e.11 disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 02
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
do_pci_scan_bridge returns max 2
PCI: pci_scan_bus returning with max=002
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0

Fam14h - cpu_bus_read_resources.
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

Fam14h - domain_read_resources.
PCI_DOMAIN: 0000 read_resources bus 0 link: 0

Fam14h - read_resources.
PCI: 00:04.0 read_resources bus 1 link: 0
PCI: 00:04.0 read_resources bus 1 link: 0 done
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
SB800 - Lpc.c - lpc_read_resources - Start.
SB800 - Lpc.c - lpc_read_resources - End.
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 2 link: 0
PCI: 00:14.4 read_resources bus 2 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit
0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10
   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 14
   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff
flags 200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
flags 80102 index 1c
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 10
    PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffffffffffff flags 1201 index 18
    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 1201 index 20
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff
flags 2200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 10
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 14
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 18
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 1c
   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20
   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff
flags 200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
c0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags
80102 index 1c
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 81202 index 24
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0xff] io
PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12
limit: ffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff done
PCI: 00:04.0 1c *  [0x0 - 0xfff] io
PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:11.0 20 *  [0x1400 - 0x140f] io
PCI: 00:11.0 10 *  [0x1410 - 0x1417] io
PCI: 00:11.0 18 *  [0x1418 - 0x141f] io
PCI: 00:11.0 14 *  [0x1420 - 0x1423] io
PCI: 00:11.0 1c *  [0x1424 - 0x1427] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12
gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffffffffffff
PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20
gran: 20 limit: ffffffffffffffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20
gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem
PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem
PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem
PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem
PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem
PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem
PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem
PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem
PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601
align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 00:50
constrain_resources: I2C: 00:51
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 004e.5
skipping PNP: 004e.5 at 62 fixed resource, size=0!
constrain_resources: PNP: 004e.10
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.5
constrain_resources: PCI: 00:18.6
constrain_resources: PCI: 00:18.7
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0
limit:ffff
Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io
Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io
Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io
Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io
Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io
Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align:
12 gran: 0 done
PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff
Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io
PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran:
12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
align:28 gran:0 limit:febfffff
Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem
Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem
Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem
Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem
Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem
Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem
Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem
Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem
Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size: 10247601
align: 28 gran: 0 done
PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem
Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000
align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem
PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000
align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align:
20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20
limit:febfffff
PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20
gran: 20 done
Root Device assign_resources, bus 0 link: 0

Fam14h - cpu_bus_set_resources.
APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000
gran 0x00 mem <mmconfig>
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

Fam14h - domain_set_resources.
  amsr - incoming dev = 00272248
adsr: (before) basek = 0, limitk = 7effffff.
adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.
adsr - 0xa0000 to 0xbffff resource.
adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff
0: mmio_basek=00380000, basek=00000300, limitk=001fbfff
  adsr - uma_memory_base = 67000000.
  adsr - mmio_basek = 380000.
  adsr - high_tables_size = e91000.
adsr - adding uma resource.

Fam14h - Adding UMA memory.
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
prefmem
PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08
io
PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12
mem
PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c
bus 01 io
PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14
bus 01 prefmem
PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14
bus 01 mem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
io
PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c
prefmem64
PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e
prefmem64
PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran 0x11
romem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03
io
PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02
io
PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03
io
PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02
io
PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04
io
PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran 0x0a
mem
PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran 0x0c
mem
PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran 0x08
mem
PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran 0x0c
mem
PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran 0x08
mem
PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e
mem64
SB800 - Lpc.c - lpc_set_resources - Start.
PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran 0x00
mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io
PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00
irq
ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned
PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03
io
PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00
irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
SB800 - Lpc.c - lpc_set_resources - End.
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c
bus 02 io
PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 prefmem
PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 mem
PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran 0x0c
mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
  adsr - leaving this lovely routine.
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit
0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff
flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0 limit 0
flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0
limit 0 flags f0000200 index 7
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit
febfffff flags 60001200 index 10
   PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags
60000100 index 14
   PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit
febfffff flags 60000200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff
flags 60080102 index 1c
   PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit
febfffff flags 60081202 index 24
   PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit
febfffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff
flags 60000100 index 10
    PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit
febfffff flags 60001201 index 18
    PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit
febfffff flags 60001201 index 20
    PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17 limit
febfffff flags 60002200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags
60000100 index 10
   PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags
60000100 index 14
   PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags
60000100 index 18
   PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags
60000100 index 1c
   PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags
60000100 index 20
   PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
febfffff flags 60000200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
febfffff flags 60000201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit febfffff
flags 60000200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
e0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags
60080102 index 1c
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
Done allocating resources.
POST: 0x88
Enabling resources...

Fam14h - domain_enable_resources: AmdInitMid.
agesawrapper_amdinitmid SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
  ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1510
PCI: 00:01.0 cmd <- 07
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 07
PCI: 00:11.0 subsystem <- 1022/1510
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/1510
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/1510
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1510
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/1510
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1510
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1510
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/1510
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 subsystem <- 1022/1510
PCI: 00:14.4 cmd <- 21
PCI: 00:14.5 subsystem <- 1022/1510
PCI: 00:14.5 cmd <- 02
PCI: 00:18.0 subsystem <- 1022/1510
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1510
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1510
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1510
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1510
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1510
PCI: 00:18.5 cmd <- 00
PCI: 00:18.6 subsystem <- 1022/1510
PCI: 00:18.6 cmd <- 00
PCI: 00:18.7 subsystem <- 1022/1510
PCI: 00:18.7 cmd <- 00
PCI: 01:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
model_14_init done.
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x01 done.
POST: 0x9b
model_14_init done.
CPU #1 initialized
All AP CPUs stopped (5043 loops)
PCI: 00:00.0 init
Northbridge init
PCI: 00:01.0 init
CBFS: Looking for 'pci1002,9804.rom'
CBFS: found.
In CBFS, ROM address for PCI: 00:01.0 = ffe00778
PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0
PCI ROM image, vendor ID 1002, device ID 9804,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
Getting information about VESA mode 4117
framebuffer: e0000000
Setting VESA mode 4117
PCI: 00:11.0 init
AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0
Number of Ports: 0x6, Port implemented(bit map): 0x3f
AHCI/RAID controller initialized
PCI: 00:14.0 init
CBFS: Looking for 'pci1002,4385.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1002,4385.rom'.
PCI: 00:14.4 init
PCI: 00:18.0 init
CBFS: Looking for 'pci1022,1700.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1700.rom'.
PCI: 00:18.1 init
CBFS: Looking for 'pci1022,1701.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1701.rom'.
PCI: 00:18.2 init
CBFS: Looking for 'pci1022,1702.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1702.rom'.
PCI: 00:18.3 init
CBFS: Looking for 'pci1022,1703.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1703.rom'.
PCI: 00:18.4 init
CBFS: Looking for 'pci1022,1704.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1704.rom'.
PCI: 00:18.5 init
CBFS: Looking for 'pci1022,1718.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1718.rom'.
PCI: 00:18.6 init
CBFS: Looking for 'pci1022,1716.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1716.rom'.
PCI: 00:18.7 init
CBFS: Looking for 'pci1022,1719.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1719.rom'.
PCI: 01:00.0 init
CBFS: Looking for 'pci10ec,8168.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci10ec,8168.rom'.
Option ROM address for PCI: 01:00.0 = f0100000
PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect expansion ROM header signature 0000
PNP: 004e.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 004e.10 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 0
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 0
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
APIC: 01: enabled 1
PCI: 01:00.0: enabled 1
POST: 0x89
Re-Initializing CBMEM area to 0x6616f000
Initializing CBMEM area to 0x6616f000 (15273984 bytes)
dword=6616f000
nvram_pos=f8, dword>>(8*i)=0
nvram_pos=f9, dword>>(8*i)=f0
nvram_pos=fa, dword>>(8*i)=16
nvram_pos=fb, dword>>(8*i)=66
Adding CBMEM entry as no. 1
Moving GDT to 6616f200...ok
POST: 0x8a
High Tables Base is 6616f000.
POST: 0x9a
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
In agesawrapper_amdinitlate, AGESA generated ACPI tables:
   DmiTable:00000000
   AcpiPstate: 00022165
   AcpiSrat:00000000
   AcpiSlit:00000000
   Mce:00022621
   Cmc:000226c7
   Alib:00022765
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
POST: 0x9b
Wrote the mp table end at: 000f0410 - 000f0514
Adding CBMEM entry as no. 3
Wrote the mp table end at: 66170410 - 66170514
MP table: 276 bytes.
POST: 0x9c
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 66171400...
ACPI:  * DSDT at 661714c8
ACPI:  * DSDT @ 661714c8 Length 28cd
ACPI:  * FACS at 66173d98
ACPI:  * FADT at 66173dd8
ACPI_BLK_BASE: 0x0800
ACPI: added table 1/32, length now 40
ACPI:  * HPET at 66173ed0
ACPI: added table 2/32, length now 44
ACPI:  * MADT at 66173f08
ACPI: added table 3/32, length now 48
ACPI: added table 4/32, length now 52
ACPI:  * SRAT at 66174100
  AGESA SRAT table NULL. Skipping.
ACPI:  * SLIT at 66174100
  AGESA SLIT table NULL. Skipping.
ACPI:  * AGESA ALIB SSDT at 66174100
ACPI: added table 5/32, length now 56
ACPI:  * AGESA SSDT Pstate at 66175790
ACPI: added table 6/32, length now 60
ACPI:  * coreboot TOM SSDT2 at 66175aa0
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 18149 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 6617c800
Root Device (AMD Persimmon Mainboard)
APIC_CLUSTER: 0 (AMD Family 14h Root Complex)
APIC: 00 (AMD CPU Family 14h)
PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)
PCI: 00:00.0 (AMD Family 14h Northbridge)
PCI: 00:01.0 (AMD Family 14h Northbridge)
PCI: 00:01.1 (AMD Family 14h Northbridge)
PCI: 00:04.0 (AMD Family 14h Northbridge)
PCI: 00:05.0 (AMD Family 14h Northbridge)
PCI: 00:06.0 (AMD Family 14h Northbridge)
PCI: 00:07.0 (AMD Family 14h Northbridge)
PCI: 00:08.0 (AMD Family 14h Northbridge)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.1 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.1 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 ()
I2C: 00:51 ()
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 004e.0 (Fintek F81865F Super I/O)
PNP: 004e.3 (Fintek F81865F Super I/O)
PNP: 004e.4 (Fintek F81865F Super I/O)
PNP: 004e.5 (Fintek F81865F Super I/O)
PNP: 004e.6 (Fintek F81865F Super I/O)
PNP: 004e.a (Fintek F81865F Super I/O)
PNP: 004e.10 (Fintek F81865F Super I/O)
PNP: 004e.11 (Fintek F81865F Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.0 (AMD Family 14h Northbridge)
PCI: 00:18.1 (AMD Family 14h Northbridge)
PCI: 00:18.2 (AMD Family 14h Northbridge)
PCI: 00:18.3 (AMD Family 14h Northbridge)
PCI: 00:18.4 (AMD Family 14h Northbridge)
PCI: 00:18.5 (AMD Family 14h Northbridge)
PCI: 00:18.6 (AMD Family 14h Northbridge)
PCI: 00:18.7 (AMD Family 14h Northbridge)
APIC: 01 ()
PCI: 01:00.0 ()
SMBIOS tables: 287 bytes.
POST: 0x9d
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x6617d000
rom_table_end = 0x6617d000
Adjust low_table_end from 0x00000528 to 0x00001000
Adjust rom_table_end from 0x6617d000 to 0x66180000
Adding high table area
uma_memory_start=0x67000000, uma_memory_size=0x18000000
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000006616efff: RAM
 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES
 4. 0000000067000000-000000007effffff: RESERVED
 5. 00000000f8000000-00000000f8ffffff: RESERVED
Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f
coreboot table: 532 bytes.
POST: 0x9e
Adding CBMEM entry as no. 7
Adding CBMEM entry as no. 8
POST: 0x9d
Multiboot Information structure has been written.
 0. FREE SPACE 66ff6000 0000a000
 1. GDT        6616f200 00000200
 2. IRQ TABLE  6616f400 00001000
 3. SMP TABLE  66170400 00001000
 4. ACPI       66171400 0000b400
 5. SMBIOS     6617c800 00000800
 6. COREBOOT   6617d000 00008000
 7. ACPI RESUME66185000 00e00000
 8. ACPISCRATCH66f85000 00071000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
Loading segment from rom address 0xffee35f8
  code (compression=0)
  New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630 filesize
0x18b60
  (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
filesize 0x18b60
Loading segment from rom address 0xffee3614
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60
lb: [0x0000000000200000, 0x0000000000360000)
Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60
it's not compressed!
[ 0x000e74a0, 00100000, 0x00100000) <- ffee3630
dest 000e74a0, end 00100000, bouncebuffer 65eaf000
Loaded segments
Jumping to boot code at fc855
POST: 0xf8
entry    = 0x000fc855
lb_start = 0x00200000
lb_size  = 0x00160000
adjust   = 0x65e0f000
buffer   = 0x65eaf000
     elf_boot_notes = 0x00272e18
adjusted_boot_notes = 0x66081e18
Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)
Found mainboard AMD Persimmon
Found CBFS header at 0xfffffbf0
Ram Size=0x6616f000 (0x0000000000000000 high)
Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)
CPU Mhz=1001
Found 22 PCI devices (max PCI bus is 02)
Found 2 cpu(s) max supported 2 cpu(s)
Copying PIR from 0x6616f400 to 0x000fdbc0
Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0
Copying ACPI RSDP from 0x66171400 to 0x000fda80
Copying SMBIOS entry point from 0x6617c800 to 0x000fda60
Scan for VGA option rom
Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b
EHCI init on dev 00:12.2 (regs=0xf0247420)
EHCI init on dev 00:13.2 (regs=0xf0247520)
OHCI init on dev 00:14.5 (regs=0xf0246000)
Found 0 lpt ports
Found 3 serial ports
ebda moved from 9fc00 to 9f400
AHCI controller at 11.0, iobase f0247000, irq 0
OHCI init on dev 00:12.0 (regs=0xf0244000)
Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0
ebda moved from 9f400 to 9f000
ebda moved from 9f000 to 9ec00
AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
MiBytes)"
Got ps2 nak (status=51)
USB keyboard initialized
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=125045424
Returned 57344 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009ec00 = 1 RAM
  1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000006616d000 = 1 RAM
  4: 000000006616d000 - 000000007f000000 = 2 RESERVED
  5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
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From shekairui at gmail.com  Tue Jun  5 04:49:38 2012
From: shekairui at gmail.com (shekairui)
Date: Tue, 05 Jun 2012 10:49:38 +0800
Subject: [coreboot] amd/persimmon does not scan behind bridge on sb800
 southbridge
In-Reply-To: <CAHgS8JXeEXtmuXAc-Fvfc2gEK9MzT2fbT+YYfEwOR+cRbq+ZGg@mail.gmail.com>
References: <CAHgS8JXeEXtmuXAc-Fvfc2gEK9MzT2fbT+YYfEwOR+cRbq+ZGg@mail.gmail.com>
Message-ID: <4FCD73C2.8060409@gmail.com>

On 06/05/2012 03:42 AM, Andy Sharp wrote:
> Howdy,
>
> I've got an amd/persimmon board, and when I build the coreboot for it
> from the tree, it only finds the PCIe devices directly attached to the
> CPU, but not any of the ones hanging off the sb800 southbridge.  Anyone
> have any clues for me?
I suggest to check the devicetree.cb first.
The sb800 PCIe ports were set off by default.
--snip--
                                 device pci 15.0 off end # PCIe PortA
                                 device pci 15.1 off end # PCIe PortB
                                 device pci 15.2 off end # PCIe PortC
                                 device pci 15.3 off end # PCIe PortD
--snip--

Kerry
Thanks

> Thanks!
>
> coreboot console log:
>
>
>
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> starting...
> POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000000
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000001
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly passed.
> SLP_TYP type was 0
> POST: 0x40
> agesawrapper_amdinitpost
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
>
> EventLog: EventClass = 2, EventInfo = 8040100.
> Param1 = a00a, Param2 = 0.
> Param3 = 0, Param4 = 0.
> SLP_TYP type was 0
> error level: 4
> POST: 0x42
> agesawrapper_amdinitenv SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> passed.
> POST: 0x43
> POST: 0x44
> POST: 0x50
> Loading image.
> CBFS: Looking for 'fallback/coreboot_ram'
> CBFS: found.
> CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> entry @ 0x200000
> Jumping to image.
> POST: 0x80
> POST: 0x39
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> booting...
> POST: 0x40
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 1
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 1
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 1
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> Compare with tree...
> Root Device: enabled 1
>   APIC_CLUSTER: 0: enabled 1
>    APIC: 00: enabled 1
>   PCI_DOMAIN: 0000: enabled 1
>    PCI: 00:00.0: enabled 1
>    PCI: 00:01.0: enabled 1
>    PCI: 00:01.1: enabled 1
>    PCI: 00:04.0: enabled 1
>    PCI: 00:05.0: enabled 0
>    PCI: 00:06.0: enabled 0
>    PCI: 00:07.0: enabled 0
>    PCI: 00:08.0: enabled 0
>    PCI: 00:11.0: enabled 1
>    PCI: 00:12.0: enabled 1
>    PCI: 00:12.1: enabled 1
>    PCI: 00:12.2: enabled 1
>    PCI: 00:13.0: enabled 1
>    PCI: 00:13.1: enabled 1
>    PCI: 00:13.2: enabled 1
>    PCI: 00:14.0: enabled 1
>     I2C: 00:50: enabled 1
>     I2C: 00:51: enabled 1
>    PCI: 00:14.1: enabled 1
>    PCI: 00:14.2: enabled 1
>    PCI: 00:14.3: enabled 1
>     PNP: 004e.0: enabled 0
>     PNP: 004e.3: enabled 0
>     PNP: 004e.4: enabled 0
>     PNP: 004e.5: enabled 1
>     PNP: 004e.6: enabled 0
>     PNP: 004e.a: enabled 0
>     PNP: 004e.10: enabled 1
>     PNP: 004e.11: enabled 0
>    PCI: 00:14.4: enabled 1
>    PCI: 00:14.5: enabled 1
>    PCI: 00:15.0: enabled 0
>    PCI: 00:15.1: enabled 0
>    PCI: 00:15.2: enabled 0
>    PCI: 00:15.3: enabled 0
>    PCI: 00:16.0: enabled 0
>    PCI: 00:16.2: enabled 0
>    PCI: 00:18.0: enabled 1
>    PCI: 00:18.1: enabled 1
>    PCI: 00:18.2: enabled 1
>    PCI: 00:18.3: enabled 1
>    PCI: 00:18.4: enabled 1
>    PCI: 00:18.5: enabled 1
>    PCI: 00:18.6: enabled 1
>    PCI: 00:18.7: enabled 1
> Mainboard Persimmon Enable.
> SLP_TYP type was 0
> persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
> persimmon_enable: uma size 0x18000000, memory start 0x67000000
> scan_static_bus for Root Device
> APIC_CLUSTER: 0 enabled
> PCI_DOMAIN: 0000 enabled
> APIC_CLUSTER: 0 scanning...
>    AP siblings=1
> CPU: APIC: 00 enabled
> CPU: APIC: 01 enabled
> PCI_DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> POST: 0x24
> PCI: 00:00.0 [1022/1510] ops
> PCI: 00:00.0 [1022/1510] enabled
> PCI: 00:01.0 [1002/9804] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:04.0 subordinate bus PCI Express
> PCI: 00:04.0 [1022/1512] enabled
> sb800_enable() SLP_TYP type was 0
> PCI: 00:11.0 [1002/4393] ops
> PCI: 00:11.0 [1002/4393] enabled
> sb800_enable() PCI: 00:12.0 [1002/4397] ops
> PCI: 00:12.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
> sb800_enable() PCI: 00:12.2 [1002/4396] ops
> PCI: 00:12.2 [1002/4396] enabled
> sb800_enable() PCI: 00:13.0 [1002/4397] ops
> PCI: 00:13.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
> sb800_enable() PCI: 00:13.2 [1002/4396] ops
> PCI: 00:13.2 [1002/4396] enabled
> sb800_enable() sm_init().
> IOAPIC: Clearing IOAPIC at 0xfec00000
> IOAPIC: 23 interrupts
> IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> IOAPIC: Initializing IOAPIC at 0xfec00000
> IOAPIC: Bootstrap Processor Local APIC = 0x00
> IOAPIC: ID = 0x02
> IOAPIC: 23 interrupts
> IOAPIC: Enabling interrupts on FSB
> IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> PCI: 00:14.0 [1002/4385] enabled
> sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
> sb800_enable() hda enabled
> PCI: 00:14.2 [1002/4383] ops
> PCI: 00:14.2 [1002/4383] enabled
> sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> PCI: 00:14.3 [1002/439d] enabled
> sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> PCI: 00:14.4 [1002/4384] enabled
> sb800_enable() PCI: 00:14.5 [1002/4399] ops
> PCI: 00:14.5 [1002/4399] enabled
> sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> PCI: 00:18.1 [1022/1701] enabled
> PCI: 00:18.2 [1022/1702] enabled
> PCI: 00:18.3 [1022/1703] enabled
> PCI: 00:18.4 [1022/1704] enabled
> PCI: 00:18.5 [1022/1718] enabled
> PCI: 00:18.6 [1022/1716] enabled
> PCI: 00:18.7 [1022/1719] enabled
> POST: 0x25
> PCI: Left over static devices:
> PCI: 00:01.1
> PCI: Check your devicetree.cb.
> do_pci_scan_bridge for PCI: 00:04.0
> PCI: pci_scan_bus for bus 01
> POST: 0x24
> PCI: 01:00.0 [10ec/8168] enabled
> POST: 0x25
> PCI: pci_scan_bus returning with max=001
> POST: 0x55
> Capability: type 0x01 @ 0x40
> Capability: type 0x05 @ 0x50
> Capability: type 0x10 @ 0x70
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> do_pci_scan_bridge returns max 1
> scan_static_bus for PCI: 00:14.3
> PNP: 004e.0 disabled
> PNP: 004e.3 disabled
> PNP: 004e.4 disabled
> PNP: 004e.5 enabled
> PNP: 004e.6 disabled
> PNP: 004e.a disabled
> PNP: 004e.10 enabled
> PNP: 004e.11 disabled
> scan_static_bus for PCI: 00:14.3 done
> do_pci_scan_bridge for PCI: 00:14.4
> PCI: pci_scan_bus for bus 02
> POST: 0x24
> POST: 0x25
> PCI: pci_scan_bus returning with max=002
> POST: 0x55
> do_pci_scan_bridge returns max 2
> PCI: pci_scan_bus returning with max=002
> POST: 0x55
> scan_static_bus for Root Device done
> done
> POST: 0x66
> Setting up VGA for PCI: 00:01.0
> Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
> Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
> Allocating resources...
> Reading resources...
> Root Device read_resources bus 0 link: 0
>
> Fam14h - cpu_bus_read_resources.
> APIC_CLUSTER: 0 read_resources bus 0 link: 0
> APIC: 00 missing read_resources
> APIC: 01 missing read_resources
> APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
>
> Fam14h - domain_read_resources.
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0
>
> Fam14h - read_resources.
> PCI: 00:04.0 read_resources bus 1 link: 0
> PCI: 00:04.0 read_resources bus 1 link: 0 done
> PCI: 00:14.0 read_resources bus 0 link: 0
> I2C: 00:50 missing read_resources
> I2C: 00:51 missing read_resources
> PCI: 00:14.0 read_resources bus 0 link: 0 done
> SB800 - Lpc.c - lpc_read_resources - Start.
> SB800 - Lpc.c - lpc_read_resources - End.
> PCI: 00:14.3 read_resources bus 0 link: 0
> PCI: 00:14.3 read_resources bus 0 link: 0 done
> PCI: 00:14.4 read_resources bus 2 link: 0
> PCI: 00:14.4 read_resources bus 2 link: 0 done
> PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
> Root Device read_resources bus 0 link: 0 done
> Done reading resources.
> Show resources in subtree (Root Device)...After reading.
>   Root Device child on link 0 APIC_CLUSTER: 0
>    APIC_CLUSTER: 0 child on link 0 APIC: 00
>    APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0
> limit 0 flags f0000200 index c0010058
>     APIC: 00
>     APIC: 01
>    PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
>    PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff
> flags 40040100 index 10000000
>    PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
> flags 40040200 index 10000100
>     PCI: 00:00.0
>     PCI: 00:01.0
>     PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
> ffffffff flags 1200 index 10
>     PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff
> flags 100 index 14
>     PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit
> ffffffff flags 200 index 18
>     PCI: 00:04.0 child on link 0 PCI: 01:00.0
>     PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
> flags 80102 index 1c
>     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
> ffffffffffffffff flags 81202 index 24
>     PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 80202 index 20
>      PCI: 01:00.0
>      PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff
> flags 100 index 10
>      PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffffffffffff flags 1201 index 18
>      PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
> ffffffffffffffff flags 1201 index 20
>      PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit
> ffffffff flags 2200 index 30
>     PCI: 00:05.0
>     PCI: 00:06.0
>     PCI: 00:07.0
>     PCI: 00:08.0
>     PCI: 00:11.0
>     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
> 100 index 10
>     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
> 100 index 14
>     PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags
> 100 index 18
>     PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags
> 100 index 1c
>     PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags
> 100 index 20
>     PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit
> ffffffff flags 200 index 24
>     PCI: 00:12.0
>     PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
>     PCI: 00:12.1
>     PCI: 00:12.2
>     PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
> flags 200 index 10
>     PCI: 00:13.0
>     PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
>     PCI: 00:13.1
>     PCI: 00:13.2
>     PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
> flags 200 index 10
>     PCI: 00:14.0 child on link 0 I2C: 00:50
>      I2C: 00:50
>      I2C: 00:51
>     PCI: 00:14.1
>     PCI: 00:14.2
>     PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
> ffffffffffffffff flags 201 index 10
>     PCI: 00:14.3 child on link 0 PNP: 004e.0
>     PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff
> flags 200 index a0
>     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
> c0040100 index 10000000
>     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
> 0 flags c0040200 index 10000100
>     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
> flags c0000200 index 3
>      PNP: 004e.0
>      PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
> c0000100 index 60
>      PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>      PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
> c0000800 index 74
>      PNP: 004e.3
>      PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags
> 100 index 60
>      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
> index 74
>      PNP: 004e.4
>      PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags
> 100 index 60
>      PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.5
>      PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff
> flags c0000100 index 60
>      PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
> c0000100 index 62
>      PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>      PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 72
>      PNP: 004e.6
>      PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.a
>      PNP: 004e.10
>      PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
>      PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>      PNP: 004e.11
>      PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
>      PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>     PCI: 00:14.4
>     PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff
> flags 80102 index 1c
>     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 81202 index 24
>     PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
> flags 80202 index 20
>     PCI: 00:14.5
>     PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit
> ffffffff flags 200 index 10
>     PCI: 00:15.0
>     PCI: 00:15.1
>     PCI: 00:15.2
>     PCI: 00:15.3
>     PCI: 00:16.0
>     PCI: 00:16.2
>     PCI: 00:18.0
>     PCI: 00:18.1
>     PCI: 00:18.2
>     PCI: 00:18.3
>     PCI: 00:18.4
>     PCI: 00:18.5
>     PCI: 00:18.6
>     PCI: 00:18.7
> PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
> limit: ffff
> PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffffffff
> PCI: 01:00.0 10 *  [0x0 - 0xff] io
> PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran:
> 12 limit: ffff done
> PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffff
> PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
> limit: ffff done
> PCI: 00:04.0 1c *  [0x0 - 0xfff] io
> PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io
> PCI: 00:11.0 20 *  [0x1400 - 0x140f] io
> PCI: 00:11.0 10 *  [0x1410 - 0x1417] io
> PCI: 00:11.0 18 *  [0x1418 - 0x141f] io
> PCI: 00:11.0 14 *  [0x1420 - 0x1423] io
> PCI: 00:11.0 1c *  [0x1424 - 0x1427] io
> PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12
> gran: 0 limit: ffff done
> PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
> limit: ffffffff
> PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffffffffffff
> PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem
> PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem
> PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align:
> 20 gran: 20 limit: ffffffffffffffff done
> PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff
> PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
> PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20
> gran: 20 limit: ffffffff done
> PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffff
> PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran:
> 20 limit: ffffffff done
> PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff
> PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
> limit: ffffffff done
> PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem
> PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem
> PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem
> PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem
> PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem
> PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem
> PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem
> PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem
> PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem
> PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem
> PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem
> PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem
> PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601
> align: 28 gran: 0 limit: ffffffff done
> avoid_fixed_resources: PCI_DOMAIN: 0000
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
> avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
> constrain_resources: PCI_DOMAIN: 0000
> constrain_resources: PCI: 00:00.0
> constrain_resources: PCI: 00:01.0
> constrain_resources: PCI: 00:04.0
> constrain_resources: PCI: 01:00.0
> constrain_resources: PCI: 00:11.0
> constrain_resources: PCI: 00:12.0
> constrain_resources: PCI: 00:12.2
> constrain_resources: PCI: 00:13.0
> constrain_resources: PCI: 00:13.2
> constrain_resources: PCI: 00:14.0
> constrain_resources: I2C: 00:50
> constrain_resources: I2C: 00:51
> constrain_resources: PCI: 00:14.2
> constrain_resources: PCI: 00:14.3
> constrain_resources: PNP: 004e.5
> skipping PNP: 004e.5 at 62 fixed resource, size=0!
> constrain_resources: PNP: 004e.10
> constrain_resources: PCI: 00:14.4
> constrain_resources: PCI: 00:14.5
> constrain_resources: PCI: 00:18.0
> constrain_resources: PCI: 00:18.1
> constrain_resources: PCI: 00:18.2
> constrain_resources: PCI: 00:18.3
> constrain_resources: PCI: 00:18.4
> constrain_resources: PCI: 00:18.5
> constrain_resources: PCI: 00:18.6
> constrain_resources: PCI: 00:18.7
> avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
> lim->base 00001000 lim->limit 0000ffff
> avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
> lim->base 00000000 lim->limit febfffff
> Setting resources...
> PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12
> gran:0 limit:ffff
> Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
> Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io
> Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io
> Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io
> Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io
> Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io
> Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io
> PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428
> align: 12 gran: 0 done
> PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
> limit:ffff
> Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io
> PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
> gran: 12 done
> PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
> limit:ffff
> PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12
> gran: 12 done
> PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
> align:28 gran:0 limit:febfffff
> Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem
> Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
> Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem
> Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem
> Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem
> Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem
> Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem
> Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem
> Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem
> Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem
> Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem
> Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem
> PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size:
> 10247601 align: 28 gran: 0 done
> PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000
> align:20 gran:20 limit:febfffff
> Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem
> Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem
> PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size:
> 100000 align: 20 gran: 20 done
> PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
> gran:20 limit:febfffff
> Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem
> PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000
> align: 20 gran: 20 done
> PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
> gran:20 limit:febfffff
> PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0
> align: 20 gran: 20 done
> PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20
> gran:20 limit:febfffff
> PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align:
> 20 gran: 20 done
> Root Device assign_resources, bus 0 link: 0
>
> Fam14h - cpu_bus_set_resources.
> APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size
> 0x01000000 gran 0x00 mem <mmconfig>
> APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
> APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
>
> Fam14h - domain_set_resources.
>    amsr - incoming dev = 00272248
> adsr: (before) basek = 0, limitk = 7effffff.
> adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.
> adsr - 0xa0000 to 0xbffff resource.
> adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff
> 0: mmio_basek=00380000, basek=00000300, limitk=001fbfff
>    adsr - uma_memory_base = 67000000.
>    adsr - mmio_basek = 380000.
>    adsr - high_tables_size = e91000.
> adsr - adding uma resource.
>
> Fam14h - Adding UMA memory.
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
> PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran
> 0x1c prefmem
> PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran
> 0x08 io
> PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran
> 0x12 mem
> PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran
> 0x0c bus 01 io
> PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran
> 0x14 bus 01 prefmem
> PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran
> 0x14 bus 01 mem
> PCI: 00:04.0 assign_resources, bus 1 link: 0
> PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran
> 0x08 io
> PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran
> 0x0c prefmem64
> PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran
> 0x0e prefmem64
> PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran
> 0x11 romem
> PCI: 00:04.0 assign_resources, bus 1 link: 0
> PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran
> 0x03 io
> PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran
> 0x02 io
> PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran
> 0x03 io
> PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran
> 0x02 io
> PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran
> 0x04 io
> PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran
> 0x0a mem
> PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran
> 0x0c mem
> PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran
> 0x08 mem
> PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran
> 0x0c mem
> PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran
> 0x08 mem
> PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran
> 0x0e mem64
> SB800 - Lpc.c - lpc_set_resources - Start.
> PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran
> 0x00 mem
> PCI: 00:14.3 assign_resources, bus 0 link: 0
> PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
> PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io
> PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran
> 0x00 irq
> ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned
> PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran
> 0x03 io
> PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran
> 0x00 irq
> PCI: 00:14.3 assign_resources, bus 0 link: 0
> SB800 - Lpc.c - lpc_set_resources - End.
> PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran
> 0x0c bus 02 io
> PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
> 0x14 bus 02 prefmem
> PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran
> 0x14 bus 02 mem
> PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran
> 0x0c mem
> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
>    adsr - leaving this lovely routine.
> Root Device assign_resources, bus 0 link: 0
> Done setting resources.
> Show resources in subtree (Root Device)...After assigning values.
>   Root Device child on link 0 APIC_CLUSTER: 0
>    APIC_CLUSTER: 0 child on link 0 APIC: 00
>    APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0
> limit 0 flags f0000200 index c0010058
>     APIC: 00
>     APIC: 01
>    PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
>    PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit
> ffff flags 40040100 index 10000000
>    PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
> limit febfffff flags 40040200 index 10000100
>    PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0
> flags e0004200 index 10
>    PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0
> limit 0 flags e0004200 index 20
>    PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0
> limit 0 flags f0000200 index 7
>     PCI: 00:00.0
>     PCI: 00:01.0
>     PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28
> limit febfffff flags 60001200 index 10
>     PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff
> flags 60000100 index 14
>     PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18
> limit febfffff flags 60000200 index 18
>     PCI: 00:04.0 child on link 0 PCI: 01:00.0
>     PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit
> ffff flags 60080102 index 1c
>     PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20
> limit febfffff flags 60081202 index 24
>     PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20
> limit febfffff flags 60080202 index 20
>      PCI: 01:00.0
>      PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff
> flags 60000100 index 10
>      PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12
> limit febfffff flags 60001201 index 18
>      PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14
> limit febfffff flags 60001201 index 20
>      PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17
> limit febfffff flags 60002200 index 30
>     PCI: 00:05.0
>     PCI: 00:06.0
>     PCI: 00:07.0
>     PCI: 00:08.0
>     PCI: 00:11.0
>     PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff
> flags 60000100 index 10
>     PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff
> flags 60000100 index 14
>     PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff
> flags 60000100 index 18
>     PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff
> flags 60000100 index 1c
>     PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff
> flags 60000100 index 20
>     PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
> febfffff flags 60000200 index 24
>     PCI: 00:12.0
>     PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
>     PCI: 00:12.1
>     PCI: 00:12.2
>     PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 10
>     PCI: 00:13.0
>     PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
>     PCI: 00:13.1
>     PCI: 00:13.2
>     PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
> febfffff flags 60000200 index 10
>     PCI: 00:14.0 child on link 0 I2C: 00:50
>      I2C: 00:50
>      I2C: 00:51
>     PCI: 00:14.1
>     PCI: 00:14.2
>     PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
> febfffff flags 60000201 index 10
>     PCI: 00:14.3 child on link 0 PNP: 004e.0
>     PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit
> febfffff flags 60000200 index a0
>     PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
> c0040100 index 10000000
>     PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit
> 0 flags c0040200 index 10000100
>     PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
> flags c0000200 index 3
>      PNP: 004e.0
>      PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
> c0000100 index 60
>      PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>      PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
> c0000800 index 74
>      PNP: 004e.3
>      PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags
> 100 index 60
>      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
> index 74
>      PNP: 004e.4
>      PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags
> 100 index 60
>      PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.5
>      PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff
> flags e0000100 index 60
>      PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
> e0000100 index 62
>      PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
> e0000400 index 70
>      PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 72
>      PNP: 004e.6
>      PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
> index 70
>      PNP: 004e.a
>      PNP: 004e.10
>      PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff
> flags e0000100 index 60
>      PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
> e0000400 index 70
>      PNP: 004e.11
>      PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff
> flags c0000100 index 60
>      PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
> c0000400 index 70
>     PCI: 00:14.4
>     PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff
> flags 60080102 index 1c
>     PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
> febfffff flags 60081202 index 24
>     PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
> febfffff flags 60080202 index 20
>     PCI: 00:14.5
>     PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
> febfffff flags 60000200 index 10
>     PCI: 00:15.0
>     PCI: 00:15.1
>     PCI: 00:15.2
>     PCI: 00:15.3
>     PCI: 00:16.0
>     PCI: 00:16.2
>     PCI: 00:18.0
>     PCI: 00:18.1
>     PCI: 00:18.2
>     PCI: 00:18.3
>     PCI: 00:18.4
>     PCI: 00:18.5
>     PCI: 00:18.6
>     PCI: 00:18.7
> Done allocating resources.
> POST: 0x88
> Enabling resources...
>
> Fam14h - domain_enable_resources: AmdInitMid.
> agesawrapper_amdinitmid SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> passed.
>    ader - leaving domain_enable_resources.
> PCI: 00:00.0 cmd <- 06
> PCI: 00:01.0 subsystem <- 1022/1510
> PCI: 00:01.0 cmd <- 07
> PCI: 00:04.0 bridge ctrl <- 0003
> PCI: 00:04.0 cmd <- 07
> PCI: 00:11.0 subsystem <- 1022/1510
> PCI: 00:11.0 cmd <- 03
> PCI: 00:12.0 subsystem <- 1022/1510
> PCI: 00:12.0 cmd <- 02
> PCI: 00:12.2 subsystem <- 1022/1510
> PCI: 00:12.2 cmd <- 02
> PCI: 00:13.0 subsystem <- 1022/1510
> PCI: 00:13.0 cmd <- 02
> PCI: 00:13.2 subsystem <- 1022/1510
> PCI: 00:13.2 cmd <- 02
> PCI: 00:14.0 subsystem <- 1022/1510
> PCI: 00:14.0 cmd <- 403
> PCI: 00:14.2 subsystem <- 1022/1510
> PCI: 00:14.2 cmd <- 02
> PCI: 00:14.3 subsystem <- 1022/1510
> PCI: 00:14.3 cmd <- 0f
> PCI: 00:14.4 bridge ctrl <- 0003
> PCI: 00:14.4 subsystem <- 1022/1510
> PCI: 00:14.4 cmd <- 21
> PCI: 00:14.5 subsystem <- 1022/1510
> PCI: 00:14.5 cmd <- 02
> PCI: 00:18.0 subsystem <- 1022/1510
> PCI: 00:18.0 cmd <- 00
> PCI: 00:18.1 subsystem <- 1022/1510
> PCI: 00:18.1 cmd <- 00
> PCI: 00:18.2 subsystem <- 1022/1510
> PCI: 00:18.2 cmd <- 00
> PCI: 00:18.3 subsystem <- 1022/1510
> PCI: 00:18.3 cmd <- 00
> PCI: 00:18.4 subsystem <- 1022/1510
> PCI: 00:18.4 cmd <- 00
> PCI: 00:18.5 subsystem <- 1022/1510
> PCI: 00:18.5 cmd <- 00
> PCI: 00:18.6 subsystem <- 1022/1510
> PCI: 00:18.6 cmd <- 00
> PCI: 00:18.7 subsystem <- 1022/1510
> PCI: 00:18.7 cmd <- 00
> PCI: 01:00.0 cmd <- 03
> done.
> Initializing devices...
> Root Device init
> APIC_CLUSTER: 0 init
> start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b
> Initializing CPU #0
> CPU: vendor AMD device 500f20
> CPU: family 14, model 02, stepping 00
> Model 14 Init.
>
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
>
> POST: 0x93
> POST: 0x60
> Enabling cache
> Setting up local apic... apic_id: 0x00 done.
> POST: 0x9b
> model_14_init done.
> CPU #0 initialized
> Asserting INIT.
> Waiting for send to finish...
> +Deasserting INIT.
> Waiting for send to finish...
> +#startup loops: 2.
> Sending STARTUP #1 to 1.
> After apic_write.
> Startup point 1.
> Waiting for send to finish...
> +Sending STARTUP #2 to 1.
> After apic_write.
> Startup point 1.
> Waiting for send to finish...
> +After Startup.
> Initializing CPU #1
> Waiting for 1 CPUS to stop
> CPU: vendor AMD device 500f20
> CPU: family 14, model 02, stepping 00
> Model 14 Init.
>
> MTRR check
> Fixed MTRRs   : Enabled
> Variable MTRRs: Enabled
>
> POST: 0x93
> POST: 0x60
> Enabling cache
> Setting up local apic... apic_id: 0x01 done.
> POST: 0x9b
> model_14_init done.
> CPU #1 initialized
> All AP CPUs stopped (5043 loops)
> PCI: 00:00.0 init
> Northbridge init
> PCI: 00:01.0 init
> CBFS: Looking for 'pci1002,9804.rom'
> CBFS: found.
> In CBFS, ROM address for PCI: 00:01.0 = ffe00778
> PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0
> PCI ROM image, vendor ID 1002, device ID 9804,
> PCI ROM image, Class Code 030000, Code Type 00
> Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes
> Real mode stub @00000600: 867 bytes
> Calling Option ROM...
> ... Option ROM returned.
> Getting information about VESA mode 4117
> framebuffer: e0000000
> Setting VESA mode 4117
> PCI: 00:11.0 init
> AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0
> Number of Ports: 0x6, Port implemented(bit map): 0x3f
> AHCI/RAID controller initialized
> PCI: 00:14.0 init
> CBFS: Looking for 'pci1002,4385.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1002,4385.rom'.
> PCI: 00:14.4 init
> PCI: 00:18.0 init
> CBFS: Looking for 'pci1022,1700.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1700.rom'.
> PCI: 00:18.1 init
> CBFS: Looking for 'pci1022,1701.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1701.rom'.
> PCI: 00:18.2 init
> CBFS: Looking for 'pci1022,1702.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1702.rom'.
> PCI: 00:18.3 init
> CBFS: Looking for 'pci1022,1703.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1703.rom'.
> PCI: 00:18.4 init
> CBFS: Looking for 'pci1022,1704.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1704.rom'.
> PCI: 00:18.5 init
> CBFS: Looking for 'pci1022,1718.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1718.rom'.
> PCI: 00:18.6 init
> CBFS: Looking for 'pci1022,1716.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1716.rom'.
> PCI: 00:18.7 init
> CBFS: Looking for 'pci1022,1719.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci1022,1719.rom'.
> PCI: 01:00.0 init
> CBFS: Looking for 'pci10ec,8168.rom'
> CBFS: ERROR: No file header found at fffffc00, attempting to recover by
> searching for header
> CBFS: Could not find file 'pci10ec,8168.rom'.
> Option ROM address for PCI: 01:00.0 = f0100000
> PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
> Incorrect expansion ROM header signature 0000
> PNP: 004e.5 init
> Keyboard init...
> No PS/2 keyboard detected.
> PNP: 004e.10 init
> Devices initialized
> Show all devs...After init.
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 0
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 0
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 0
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> APIC: 01: enabled 1
> PCI: 01:00.0: enabled 1
> POST: 0x89
> Re-Initializing CBMEM area to 0x6616f000
> Initializing CBMEM area to 0x6616f000 (15273984 bytes)
> dword=6616f000
> nvram_pos=f8, dword>>(8*i)=0
> nvram_pos=f9, dword>>(8*i)=f0
> nvram_pos=fa, dword>>(8*i)=16
> nvram_pos=fb, dword>>(8*i)=66
> Adding CBMEM entry as no. 1
> Moving GDT to 6616f200...ok
> POST: 0x8a
> High Tables Base is 6616f000.
> POST: 0x9a
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> In agesawrapper_amdinitlate, AGESA generated ACPI tables:
>     DmiTable:00000000
>     AcpiPstate: 00022165
>     AcpiSrat:00000000
>     AcpiSlit:00000000
>     Mce:00022621
>     Cmc:000226c7
>     Alib:00022765
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> mid=0, did=0
> mid=0, did=0
> mid=0, did=0
> mid=c2, did=14
> mid=0, did=0
> mid=0, did=0
> mid=0, did=0
> mid=c2, did=14
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
> Adding CBMEM entry as no. 2
> Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.
> PIRQ table: 48 bytes.
> POST: 0x9b
> Wrote the mp table end at: 000f0410 - 000f0514
> Adding CBMEM entry as no. 3
> Wrote the mp table end at: 66170410 - 66170514
> MP table: 276 bytes.
> POST: 0x9c
> Adding CBMEM entry as no. 4
> ACPI: Writing ACPI tables at 66171400...
> ACPI:  * DSDT at 661714c8
> ACPI:  * DSDT @ 661714c8 Length 28cd
> ACPI:  * FACS at 66173d98
> ACPI:  * FADT at 66173dd8
> ACPI_BLK_BASE: 0x0800
> ACPI: added table 1/32, length now 40
> ACPI:  * HPET at 66173ed0
> ACPI: added table 2/32, length now 44
> ACPI:  * MADT at 66173f08
> ACPI: added table 3/32, length now 48
> ACPI: added table 4/32, length now 52
> ACPI:  * SRAT at 66174100
>    AGESA SRAT table NULL. Skipping.
> ACPI:  * SLIT at 66174100
>    AGESA SLIT table NULL. Skipping.
> ACPI:  * AGESA ALIB SSDT at 66174100
> ACPI: added table 5/32, length now 56
> ACPI:  * AGESA SSDT Pstate at 66175790
> ACPI: added table 6/32, length now 60
> ACPI:  * coreboot TOM SSDT2 at 66175aa0
> ACPI: added table 7/32, length now 64
> ACPI: done.
> ACPI tables: 18149 bytes.
> Adding CBMEM entry as no. 5
> smbios_write_tables: 6617c800
> Root Device (AMD Persimmon Mainboard)
> APIC_CLUSTER: 0 (AMD Family 14h Root Complex)
> APIC: 00 (AMD CPU Family 14h)
> PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)
> PCI: 00:00.0 (AMD Family 14h Northbridge)
> PCI: 00:01.0 (AMD Family 14h Northbridge)
> PCI: 00:01.1 (AMD Family 14h Northbridge)
> PCI: 00:04.0 (AMD Family 14h Northbridge)
> PCI: 00:05.0 (AMD Family 14h Northbridge)
> PCI: 00:06.0 (AMD Family 14h Northbridge)
> PCI: 00:07.0 (AMD Family 14h Northbridge)
> PCI: 00:08.0 (AMD Family 14h Northbridge)
> PCI: 00:11.0 (ATI SB800)
> PCI: 00:12.0 (ATI SB800)
> PCI: 00:12.1 (ATI SB800)
> PCI: 00:12.2 (ATI SB800)
> PCI: 00:13.0 (ATI SB800)
> PCI: 00:13.1 (ATI SB800)
> PCI: 00:13.2 (ATI SB800)
> PCI: 00:14.0 (ATI SB800)
> I2C: 00:50 ()
> I2C: 00:51 ()
> PCI: 00:14.1 (ATI SB800)
> PCI: 00:14.2 (ATI SB800)
> PCI: 00:14.3 (ATI SB800)
> PNP: 004e.0 (Fintek F81865F Super I/O)
> PNP: 004e.3 (Fintek F81865F Super I/O)
> PNP: 004e.4 (Fintek F81865F Super I/O)
> PNP: 004e.5 (Fintek F81865F Super I/O)
> PNP: 004e.6 (Fintek F81865F Super I/O)
> PNP: 004e.a (Fintek F81865F Super I/O)
> PNP: 004e.10 (Fintek F81865F Super I/O)
> PNP: 004e.11 (Fintek F81865F Super I/O)
> PCI: 00:14.4 (ATI SB800)
> PCI: 00:14.5 (ATI SB800)
> PCI: 00:15.0 (ATI SB800)
> PCI: 00:15.1 (ATI SB800)
> PCI: 00:15.2 (ATI SB800)
> PCI: 00:15.3 (ATI SB800)
> PCI: 00:16.0 (ATI SB800)
> PCI: 00:16.2 (ATI SB800)
> PCI: 00:18.0 (AMD Family 14h Northbridge)
> PCI: 00:18.1 (AMD Family 14h Northbridge)
> PCI: 00:18.2 (AMD Family 14h Northbridge)
> PCI: 00:18.3 (AMD Family 14h Northbridge)
> PCI: 00:18.4 (AMD Family 14h Northbridge)
> PCI: 00:18.5 (AMD Family 14h Northbridge)
> PCI: 00:18.6 (AMD Family 14h Northbridge)
> PCI: 00:18.7 (AMD Family 14h Northbridge)
> APIC: 01 ()
> PCI: 01:00.0 ()
> SMBIOS tables: 287 bytes.
> POST: 0x9d
> Adding CBMEM entry as no. 6
> Writing high table forward entry at 0x00000500
> Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6
> New low_table_end: 0x00000528
> Now going to write high coreboot table at 0x6617d000
> rom_table_end = 0x6617d000
> Adjust low_table_end from 0x00000528 to 0x00001000
> Adjust rom_table_end from 0x6617d000 to 0x66180000
> Adding high table area
> uma_memory_start=0x67000000, uma_memory_size=0x18000000
> coreboot memory table:
>   0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
>   1. 0000000000001000-000000000009ffff: RAM
>   2. 00000000000c0000-000000006616efff: RAM
>   3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES
>   4. 0000000067000000-000000007effffff: RESERVED
>   5. 00000000f8000000-00000000f8ffffff: RESERVED
> Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f
> coreboot table: 532 bytes.
> POST: 0x9e
> Adding CBMEM entry as no. 7
> Adding CBMEM entry as no. 8
> POST: 0x9d
> Multiboot Information structure has been written.
>   0. FREE SPACE 66ff6000 0000a000
>   1. GDT        6616f200 00000200
>   2. IRQ TABLE  6616f400 00001000
>   3. SMP TABLE  66170400 00001000
>   4. ACPI       66171400 0000b400
>   5. SMBIOS     6617c800 00000800
>   6. COREBOOT   6617d000 00008000
>   7. ACPI RESUME66185000 00e00000
>   8. ACPISCRATCH66f85000 00071000
> CBFS: Looking for 'fallback/payload'
> CBFS: found.
> Got a payload
> Loading segment from rom address 0xffee35f8
>    code (compression=0)
>    New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630
> filesize 0x18b60
>    (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
> filesize 0x18b60
> Loading segment from rom address 0xffee3614
>    Entry Point 0x00000000
> Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60
> filesz: 0x0000000000018b60
> lb: [0x0000000000200000, 0x0000000000360000)
> Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60
> filesz: 0x0000000000018b60
> it's not compressed!
> [ 0x000e74a0, 00100000, 0x00100000) <- ffee3630
> dest 000e74a0, end 00100000, bouncebuffer 65eaf000
> Loaded segments
> Jumping to boot code at fc855
> POST: 0xf8
> entry    = 0x000fc855
> lb_start = 0x00200000
> lb_size  = 0x00160000
> adjust   = 0x65e0f000
> buffer   = 0x65eaf000
>       elf_boot_notes = 0x00272e18
> adjusted_boot_notes = 0x66081e18
> Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)
> Found mainboard AMD Persimmon
> Found CBFS header at 0xfffffbf0
> Ram Size=0x6616f000 (0x0000000000000000 high)
> Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)
> CPU Mhz=1001
> Found 22 PCI devices (max PCI bus is 02)
> Found 2 cpu(s) max supported 2 cpu(s)
> Copying PIR from 0x6616f400 to 0x000fdbc0
> Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0
> Copying ACPI RSDP from 0x66171400 to 0x000fda80
> Copying SMBIOS entry point from 0x6617c800 to 0x000fda60
> Scan for VGA option rom
> Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b
> EHCI init on dev 00:12.2 (regs=0xf0247420)
> EHCI init on dev 00:13.2 (regs=0xf0247520)
> OHCI init on dev 00:14.5 (regs=0xf0246000)
> Found 0 lpt ports
> Found 3 serial ports
> ebda moved from 9fc00 to 9f400
> AHCI controller at 11.0, iobase f0247000, irq 0
> OHCI init on dev 00:12.0 (regs=0xf0244000)
> Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0
> ebda moved from 9f400 to 9f000
> ebda moved from 9f000 to 9ec00
> AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
> MiBytes)"
> Got ps2 nak (status=51)
> USB keyboard initialized
> All threads complete.
> Scan for option roms
> Press F12 for boot menu.
>
> drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
> s=125045424
> Returned 57344 bytes of ZoneHigh
> e820 map has 6 items:
>    0: 0000000000000000 - 000000000009ec00 = 1 RAM
>    1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED
>    2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
>    3: 0000000000100000 - 000000006616d000 = 1 RAM
>    4: 000000006616d000 - 000000007f000000 = 2 RESERVED
>    5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED
> enter handle_19:
>    NULL
> Booting from Hard Disk...
> Booting from 0000:7c00
>




From mailinglists at fnoss.com  Tue Jun  5 11:50:43 2012
From: mailinglists at fnoss.com (mailinglists)
Date: Tue, 05 Jun 2012 10:50:43 +0100
Subject: [coreboot] Potential development funding.
In-Reply-To: <4FCCC262.8040702@georgi-clan.de>
References: <1797962.oed9JXq5lN@sosillyme> <4FCCC262.8040702@georgi-clan.de>
Message-ID: <2548083.LO1ZdAULiN@sosillyme>

Hi Patrick,

Sorry, I was hopping to have the time to reply sooner.

On Monday 04 Jun 2012 16:12:50 Patrick Georgi wrote:
> Am 04.06.2012 14:42, schrieb mailinglists:
> > 1.      What do you all think the requirements will be for replacing UEFI
> > on future mobos.  Will it likely be a case of switching out the bios chip
> > or just flashing it?
> 
> We generally reuse the chips. If you're doing business, you should be
> able to afford an external flasher, so getting rid of the original BIOS
> is no problem, even if vendor BIOS locks down the chip on boot.
> 
> Some chip types are easier to flash externally than others, but that's
> from a hobbyist perspective. As a business, investing some money in the
> right adapter for a large number of boards isn't too bad, it's just hard
> to justify spending $50 (to pick some upper bound) on a single-use item
> when it's just a hobby.
> 

Unfortunately, as you might have guessed, I?m fairly technical but my 
experience is at the OS level.  I found this

http://www.ebay.com/itm/SP8-A-Universal-EEPROM-Flash-SPI-BIOS-24-25-BR90-93-
USB-Programmer-4000-
CHIPS-/180852019132?pt=LH_DefaultDomain_0&hash=item2a1b9ecfbc#ht_31613wt_1163

I'm guessing that's the type of equipment you're referring to?  no problem to 
invest in one or a few of those.


> > 2.      What % of flashes resulted in bricked mobos? Do most new boards
> > come with a backup chip which can restore life after a failure?
> 
> With external flashing you can recover by just writing again. "bricked"
> means wrong content and thus unable to boot, not destroyed chip (usually
> - I've seen the latter case, but it's very rare).
> 

Excellent.

> > 3.      Can anyone recommend a possible target ivy bridge or Trinity itx
> > mobo for coreboot development?  Perhaps one that's already being worked
> > on?
> As yet, Trinity is only released for notebooks, at least that's what I
> gathered from the tech media. Desktop and server Trinity are scheduled
> for summer and fall releases (AFAIK).
> 

Unfortunately it seems you're right, I must not have paid close enough 
attention.  Though, I did find the link below. The name of the site doesn't 
inspire confidence however;)

At the bottom of the article 
"Updated: June 4th, 2012 9am.  AMD has responded with the following.  So we?re 
confirming that we?ll have OEM Trinity desktops on shelves this week."

http://semiaccurate.com/2012/06/01/amd-delays-desktop-trinity-one-quarter/


> As for Ivybridge, please note that it requires a couple of binary-only
> components (beyond those we usually need, see below): RAM init is done
> with the Intel reference code, and to turn on the system in the first
> place, the Management Engine (some embedded controller in the chipset)
> requires a binary-only component as well.
> 
> It's remotely feasible to replace the RAM init with source (multimonth
> effort, after obtaining access to the documentation), but the ME code
> will remain a requirement (if only because it's said to be signed by
> Intel, so replacing it requires cracking their signature scheme - good
> luck).

If there is no hope of replacing these bits then a FOSS-almost computer will 
suffice.  Thankfully, the only real concern at the moment is to sidestep 
Microsoft's influence on OEMs.  You guys have already done a fantastic job of 
that, we just need to get that work onto some hardware that people will be 
buying in future.  If we can do that, it will inspire others to follow suit.  

> 
> > 4.      If we can identify a good itx mobo for the desktop line-up,  would
> > someone here be able to asses how much time a fairly full featured and
> > reliable implementation of coreboot would take to develop?
> > 
> >         note: to me "fairly full featured would be to have all the
> > 
> > fundamentals  up and avaliable for the OS to pick up, such as pci-e usb
> > 3.0, hdmi, sata 3, wifi, and working reliably.
> 
> This depends (among other things) on the kind of OS support you desire.
> OSS systems are generally more forgiving for incomplete configuration
> than Windows - but with "FOSS-only computers" Windows might not be a
> priority.

Windows is definitely not a priority.  In an ideal world, I?d be looking to 
offer Linux distributions without binary blobs, but that is probably out of the 
question for now.  Never mind though, getting close is a very good first step.   

> 
> > 5.      Is there any special requirement for getting AMD/nvidia gfx cards
> > working with coreboot?
> 
> Minor hacks might be necessary to get the IGD/GFX switch to work right.
> On systems with integrated graphics we generally expect IGD to manage
> the primary display.
> Details on that vary by chipset and/or vendor.
> 

Sounds promising.

> > 6.      Which hardware have you found to be the simplist to fully
> > implement
> > coreboot on, and which hardware (if any) should be considered a no go?
> 
> nVidia chipsets are no-go (there was a lucky strike once that gave us
> the nVidia support we have - I don't expect that to happen again). Intel
> chipsets are complicated. AMD is the best choice for coreboot support
> these days.
> 

Ok, AMD it is then.  I only hope the semiaccurate.com article above has some 
merit.  FM1 chips don't really compete with the new intel offerings.  I'll 
contact someone at AMD to get a status on the trinity chips. 

Are Intel chipsets complicated due to lack of documentation?  If so, can I 
contact/badger the right people on your behalf?

> We don't have to care about many other things (eg. the Wifi card - we
> don't handle Wifi, we just have to make sure the card is found on the bus)
> 

Good to know, thank you.


> > 8.	What do you think about the viability of a kickstarter campaign to
> > raise
> > development funds.  Has anyone tried this yet?
> 
> Last I heard Kickstarter has a backlog of several thousand projects.
> 
> Kickstarter seems to be first and foremost a social media popularity
> contest at the moment, for which coreboot is probably not a fancy enough
> topic. I'd assume the same for "FOSS Hardware", but feel free to try, if
> you feel like it.
> 

Yes it does seem to be like that.  Though If I can make the case for UEFI-less 
computers compelling enough, and market it through foss type news and review 
sites,  a crowd sourced project, what ever site it is posted on, might just 
capture enough of the right audience to fund the initial requirements. I can 
but try... 

> Make clear that you're not collecting funds for the coreboot project -
> our situation is that we can't accept donations of any kind (nor take
> money with any other designation).
> 

No problem, it would of course be deceptive of me to use a name I'm not 
affiliated with.  

I would imagine the best way to fund development (initially) would be 
to put the chosen mobo into interested developers hands (Acting on their own 
behalf of course). 

> > I would truely love to distribute computers which run entirely on free
> > software. Unfortunately, I'm no developer so If funding some development
> > is
> > the only way I can achieve this, I will find a way to do it.
> 
> "run entirely on free software":
> We usually reuse the VGABIOS image delivered by the hardware vendor,
> which comes in binary-only form. There are a couple of ways around it,
> but they're only appropriate for systems where you control the OS that's
> used (eg. not doing VGA init at all and defer things to Linux KMS), or
> they're still experimental (see i915tool - it's an attempt to create a
> coreboot-level driver from KMS sources).
> 
> This means that for a "generic" box you're still bound to the VGABIOS to
> some degree (you can't rely on KMS being available in the OS when using
> a bootloader menu).
>  
> The other aspect is that you generally have an embedded controller on
> notebooks (in addition to the management engine on newer Intel
> chipsets). It usually runs its own firmware, which is also not availabe
> in source form. If you're lucky, it's part of the EC chip as read-only
> memory - in this case, you can safely consider it part of the hardware
> (even under FSF's strict definition, as far as I understand it).
>
As long as implementing coreboot removes anything to do with secure boot, I 
and most others concerned about it will remain fairly satisfied. 

My ultimate aim will remain a FOSS-only computer business, but the timeframe  
requires some sacrifice for now.
 
> 
> Regards,
> Patrick

Thank you very much for your thoughtful reply.  You have given me many things 
to research.



From paulepanter at users.sourceforge.net  Tue Jun  5 16:42:18 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 05 Jun 2012 16:42:18 +0200
Subject: [coreboot] http://review.coreboot.org/#/c/493/: Add mainboard
 supermicro x7db8
In-Reply-To: <CALYtimqM4tRaOqOoZnetDp_srUfFcbr3G4RJgA3+x2OOZpF4YA@mail.gmail.com>
References: <CALYtimqM4tRaOqOoZnetDp_srUfFcbr3G4RJgA3+x2OOZpF4YA@mail.gmail.com>
Message-ID: <1338907338.4597.32.camel@mattotaupa>

Dear Manasa,


I am sorry for the late reply and thank you for your contributions.

Before going further please make sure you disable digest mode in your
Mailman preferences [1], so that threading is kept when you reply to
messages.

Unfortunately you took a patch for review, which was not meant to be
committed. Sven commented the following [2].

    Unfinished, only pushed for backup purposes


Am Mittwoch, den 23.05.2012, 17:55 +0530 schrieb manasa gv:
> From: Manasa GV <manasa671989 at gmail.com>
> 
> This patch is to file x7db8.Build(Jenkins) results failed for patch
> set1 in patch493.Test results showing error. So i added cmos.layout
> file.Later i done abuild,then also it is showing errors. Errors are-
> need to add smbus.c, smbus.h ,early_setup.c file for Southbridge
> i63xx.
> So please suggest me to add these files.

I think there are two options.

1. Either contact Sven Schnelle and ask him, if he can use your
contributions and how you can help.

2. Or, register with Gerrit and push an updated patch with the change ID
in the commit message of the patch you are updating.

> Signed-off-by: manasa gv<manasa671989 at gmail.com>

Please add a space before the email address. You can add Signed-off-by
lines with Git by appending `-s` to most commands. Two examples:

    $ git commit -s
    $ git format-patch -s -1

But currently Gerrit is used for patch review in coreboot.

> ---
> src/mainboard/supermicro/x7db8/cmos.layout |   72 ++++++++++++++++++++++++++++
> 1 files changed, 72 insertions(+), 0 deletions(-)
> create mode 100644 src/mainboard/supermicro/x7db8/cmos.layout

[?]


Thanks,

Paul


[1] http://www.coreboot.org/mailman/options/coreboot
[2] http://review.coreboot.org/#/c/493/
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From paulepanter at users.sourceforge.net  Tue Jun  5 16:55:48 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Tue, 05 Jun 2012 16:55:48 +0200
Subject: [coreboot] Regarding contribution for coreboot
In-Reply-To: <CALYtimrh2oMCddpDkja=kxEmPF0ntaa-wUsAcHpc-11RC-z63g@mail.gmail.com>
References: <CALYtimrh2oMCddpDkja=kxEmPF0ntaa-wUsAcHpc-11RC-z63g@mail.gmail.com>
Message-ID: <1338908148.4597.43.camel@mattotaupa>

Dear Manasa,


please excuse the late replay and thank you for your patience.


Am Montag, den 04.06.2012, 18:24 +0530 schrieb manasa gv:

> I am new and interested to work on coreboot.I have gone through the
> coreboot website.
> I am trying to do  patch review.. But I am taking more time to come up
> with the solution compared to others..

that is to be expected when getting into coreboot. Do not let this
demotivate you.

Sorry for the lack of replies. I am not up to date, but I think you
tried to do patch review over the list only which is not how it is done
in coreboot currently. A Gerrit instance [1] is used for that. You need
to log in with an OpenID (from Google Mail(?)) and leave comments there
for example. [2]

> So,Please let me know any other ways to contribute for coreboot apart
> from patch review??

I guess the best thing to get going is probably to get it running on
some hardware. The Toshiba laptop you asked about is currently not
supported [3]. Getting the chipset support done is probably to much
work, so you should get a different system. The ASRock E350M1 is pretty
good supported. Otherwise get some other AMD based system.

If that is not possible you could try QEMU although this is better to
play with payloads. You could try to get Tint running with QEMU and
probably port some more programs to libpayload.

It is pretty difficult to suggest something not knowing what your
background and interests are. Can you also share where you are located?
Maybe some coreboot user lives near by you could get in touch with.

Please also feel free to join the IRC channel [4] to get more
information.


Thanks,

Paul


[1] http://review.coreboot.org/
[2] http://www.coreboot.org/Git
[3] http://www.coreboot.org/pipermail/coreboot/2012-May/069976.html
[4] http://www.coreboot.org/IRC
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From c-d.hailfinger.devel.2006 at gmx.net  Tue Jun  5 21:08:23 2012
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Tue, 05 Jun 2012 21:08:23 +0200
Subject: [coreboot] [flashrom] Creating a nonprofit
Message-ID: <4FCE5927.8050203@gmx.net>

Hi,

the flashrom project gets donation offers roughly twice a month, and
quite a few times people wanted to donate more than 50 EUR / 60 USD. We
can't accept those donations right now because there is no legal entity
behind the flashrom project.
At the same time, we could use some money to improve flasher support by
buying some flash chips and programmers so all developers can easily
test changes. Besides that, posters/handouts for LinuxTag/FOSDEM/...
booths are currently paid for by those flashrom guys who go to those
exhibitions.

My proposal is to create a nonprofit club in Germany (eingetragener
Verein) in the same way as KDE and OpenEmbedded did it.
Given that the majority of the flashrom team lives somewhere in the EU,
starting or joining a nonprofit in the USA wouldn't make sense. An
informal request for comments among those who are involved in flashrom
did yield some noticeable interest, and I guess now is the time to make
this plan public.

coreboot is not an immediate target of this nonprofit club because I
don't want to interfere with any plans which may be ongoing on the
coreboot side. Nonwithstanding the above, if the coreboot project
leaders decide that participating in a nonprofit in Germany would make
sense, there's no reason not to do this together. Then again, the
majority of coreboot developers live in the USA and a nonprofit outside
the USA might not make sense for them.

Side note: We (coreboot/flashrom) won a substantial amount of money (to
be redeemed in hardware) in a "project beauty contest" held by
Thomas-Krenn.com, a nice server manufacturer. We need a legal entity to
accept that hardware.

Comments?

Regards,
Carl-Daniel



From ross0mcdonald at gmail.com  Wed Jun  6 18:51:06 2012
From: ross0mcdonald at gmail.com (Ross McDonald)
Date: Wed, 6 Jun 2012 18:51:06 +0200
Subject: [coreboot] Support for HP Compaq NC6320
Message-ID: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>

Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq
NC6320. The board vendor is HP. It is a
HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M southbridge and
i945 northbridge). The CPU is an Intel Core 2 Duo T5600. It has a SMSC
LPC47N217 SuperIO chip (that is the output of SuperIOTool).

# lspci -tvnn
-[0000:00]-+-00.0  Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and
945GT Express Memory Controller Hub [8086:27a0]
           +-02.0  Intel Corporation Mobile 945GM/GMS, 943/940GML Express
Integrated Graphics Controller [8086:27a2]
           +-02.1  Intel Corporation Mobile 945GM/GMS/GME, 943/940GML
Express Integrated Graphics Controller [8086:27a6]
           +-1b.0  Intel Corporation N10/ICH 7 Family High Definition Audio
Controller [8086:27d8]
           +-1c.0-[08]----00.0  Intel Corporation PRO/Wireless 3945ABG
[Golan] Network Connection [8086:4222]
           +-1c.2-[18]--
           +-1c.3-[20]--
           +-1d.0  Intel Corporation N10/ICH 7 Family USB UHCI Controller
#1 [8086:27c8]
           +-1d.1  Intel Corporation N10/ICH 7 Family USB UHCI Controller
#2 [8086:27c9]
           +-1d.2  Intel Corporation N10/ICH 7 Family USB UHCI Controller
#3 [8086:27ca]
           +-1d.3  Intel Corporation N10/ICH 7 Family USB UHCI Controller
#4 [8086:27cb]
           +-1d.7  Intel Corporation N10/ICH 7 Family USB2 EHCI Controller
[8086:27cc]
           +-1e.0-[02-06]--+-06.0  Texas Instruments PCIxx12 Cardbus
Controller [104c:8039]
           |               +-06.1  Texas Instruments PCIxx12 OHCI Compliant
IEEE 1394 Host Controller [104c:803a]
           |               +-06.2  Texas Instruments 5-in-1 Multimedia Card
Reader (SD/MMC/MS/MS PRO/xD) [104c:803b]
           |               +-06.3  Texas Instruments PCIxx12 SDA Standard
Compliant SD Host Controller [104c:803c]
           |               +-06.4  Texas Instruments PCIxx12 GemCore based
SmartCard controller [104c:803d]
           |               \-0e.0  Broadcom Corporation NetXtreme BCM5788
Gigabit Ethernet [14e4:169c]
           +-1f.0  Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge
[8086:27b9]
           +-1f.1  Intel Corporation 82801G (ICH7 Family) IDE Controller
[8086:27df]
           \-1f.2  Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA
Controller [AHCI mode] [8086:27c5]

# superiotool -dV
superiotool r6637
Probing for ALi Super I/O at 0x3f0...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
  Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0x8400, id=0x0026
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
  Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=it8502e) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id=0x2600, rev=0x0
Probing for ITE Super I/O (init=standard) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
  Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
  Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
  Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
  Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
  Failed. Returned data: id=0x26, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
  Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
Found SMSC LPC47N217 (id=0x7a, rev=0x03) at 0x4e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
  Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
  Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
  PCI device 1106:0686 not found.
Probing for Server Engines Super I/O at 0x2e...
  Failed. Returned data: id=0xffff, rev=0xff

# flashrom -V
flashrom v0.9.5.2-r1515 on Linux 3.4.0-1-ARCH (x86_64), built with libpci
3.1.9, GCC 4.6.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org

Calibrating delay loop... OS timer resolution is 1 usecs, 1803M loops per
second, 10 myus = 11 us, 100 myus = 99 us, 1000 myus = 1002 us, 10000 myus
= 9991 us, 4 myus = 5 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "HP Compaq nc6320 (RN442AWR#ABA)"
DMI string system-version: "F.0E"
DMI string baseboard-manufacturer: "Hewlett-Packard"
DMI string baseboard-product-name: "30AA"
DMI string baseboard-version: "KBC Version 58.13"
DMI string chassis-type: "Notebook"
Laptop detected via DMI.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Aborting.

I can open up the case to find out what BIOS chip I have.
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From namedylan at gmail.com  Wed Jun  6 20:28:41 2012
From: namedylan at gmail.com (Fengwei Zhang)
Date: Wed, 6 Jun 2012 14:28:41 -0400
Subject: [coreboot] Supported Motherboards with SMM
Message-ID: <C11600F1-ADF1-4732-B442-A738F0958CFD@gmail.com>

Hi All,

My name is Fengwei. For one of my research project, I need a relative new Coreboot supported board with SMM working. I am wondering if there is a list of Coreboot supported boards with SMM working. 
I have been working with board ASUS M2V-MX_SE, which supports SMM by applying Ruldof's patch. However, this board is very old, and I am unable to find it on the market now. 
I would appreciate if anyone could give me some suggestions. 

Regards,
Fengwei


From paulepanter at users.sourceforge.net  Wed Jun  6 21:29:18 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 06 Jun 2012 21:29:18 +0200
Subject: [coreboot] Support for laptop HP Compaq NC6320
In-Reply-To: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
References: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
Message-ID: <1339010958.4163.11.camel@mattotaupa>

Dear Ross,


thank you for your message. First three off-topic things.

1. Please send just plain text messages and no HTML. This is covered in
the netiquette [1].
2. When pasting stuff please turn off line wrapping. This is not
possible with the Google Mail Web interface as far as I know. So either
attach this stuff as text files or use a good mail user agent like
Thunderbird/Iceweasel, Mutt, ?.
3. The project name is spelled all lower case: coreboot.

Am Mittwoch, den 06.06.2012, 18:51 +0200 schrieb Ross McDonald:
> Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq
> NC6320. The board vendor is HP.

Ok, this a laptop for everyone.

> It is a HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M
> southbridge and i945 northbridge). The CPU is an Intel Core 2 Duo
> T5600. It has a SMSC LPC47N217 SuperIO chip (that is the output of
> SuperIOTool).

[?]

If I am not mistaken, this is the same chipset as for example used in
the Lenovo X60 or T60 and 986LCD-M/mITX [2].

So make sure you have a way to recover. Easiest way is when the flash
chip is socketed to get some spare flash chips. Since this is a laptop
you probably need to solder a socket or an adapter to the board like was
done with the X60 or T60 [3][4].

You also need to find out if an embedded controller is used and how it
works. Lastly you also need the laptop board schematics I think to set
everything up. Then you should be able to do the port pretty easily I
think. Look at the commits for the X60 and T60.


Thanks,

Paul


[1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette
[2] http://www.coreboot.org/Supported_Motherboards
[3] http://thread.gmane.org/gmane.linux.bios/69354
[4] http://thread.gmane.org/gmane.linux.bios.flashrom/575
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From paulepanter at users.sourceforge.net  Wed Jun  6 21:42:51 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 06 Jun 2012 21:42:51 +0200
Subject: [coreboot] Support for laptop HP Compaq NC6320
In-Reply-To: <1339010958.4163.11.camel@mattotaupa>
References: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
	<1339010958.4163.11.camel@mattotaupa>
Message-ID: <1339011771.4163.14.camel@mattotaupa>

Dear Ross,


Am Mittwoch, den 06.06.2012, 21:29 +0200 schrieb Paul Menzel:

> thank you for your message. First three off-topic things.
> 
> 1. Please send just plain text messages and no HTML. This is covered in
> the netiquette [1].
> 2. When pasting stuff please turn off line wrapping. This is not
> possible with the Google Mail Web interface as far as I know. So either
> attach this stuff as text files or use a good mail user agent like
> Thunderbird/Iceweasel, Mutt, ?.
> 3. The project name is spelled all lower case: coreboot.
> 
> Am Mittwoch, den 06.06.2012, 18:51 +0200 schrieb Ross McDonald:
> > Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq
> > NC6320. The board vendor is HP.
> 
> Ok, this a laptop for everyone.
> 
> > It is a HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M
> > southbridge and i945 northbridge). The CPU is an Intel Core 2 Duo
> > T5600. It has a SMSC LPC47N217 SuperIO chip (that is the output of
> > SuperIOTool).
> 
> [?]
> 
> If I am not mistaken, this is the same chipset as for example used in
> the Lenovo X60 or T60 and 986LCD-M/mITX [2].
> 
> So make sure you have a way to recover. Easiest way is when the flash
> chip is socketed to get some spare flash chips. Since this is a laptop
> you probably need to solder a socket or an adapter to the board like was
> done with the X60 or T60 [3][4].

On the IRC channel #coreboot, idwer gave an URL to a picture of the
board [5].

So you need to do some soldering. Probably you have the same options as
for the Lenovo T60/X60.

> You also need to find out if an embedded controller is used and how it
> works. Lastly you also need the laptop board schematics I think to set
> everything up. Then you should be able to do the port pretty easily I
> think. Look at the commits for the X60 and T60.


Thanks,

Paul


> [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette
> [2] http://www.coreboot.org/Supported_Motherboards
> [3] http://thread.gmane.org/gmane.linux.bios/69354
> [4] http://thread.gmane.org/gmane.linux.bios.flashrom/575
[5] http://bios-repair.co.uk/Images/Laptops/HP/Notebook/NC6320-Mainboard.jpg
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From vidwer at gmail.com  Wed Jun  6 21:55:30 2012
From: vidwer at gmail.com (Idwer Vollering)
Date: Wed, 6 Jun 2012 21:55:30 +0200
Subject: [coreboot] Support for HP Compaq NC6320
In-Reply-To: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
References: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
Message-ID: <CAPp9Or=gpi_z0xcQpc4jwnQbyZ4_0E2pR57oZyFZQq=QwqfbEw@mail.gmail.com>

2012/6/6 Ross McDonald <ross0mcdonald at gmail.com>:
> Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq NC6320.
> The board vendor is HP. It is a
> HP 30AA motherboard with an Intel 945GM Chipset (ICH7-M southbridge and i945
> northbridge). The CPU is an Intel Core 2 Duo T5600. It has a SMSC LPC47N217
> SuperIO chip (that is the output of SuperIOTool).
>
> # flashrom -V
> flashrom v0.9.5.2-r1515 on Linux 3.4.0-1-ARCH (x86_64), built with libpci
> 3.1.9, GCC 4.6.3, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
>
> Calibrating delay loop... OS timer resolution is 1 usecs, 1803M loops per
> second, 10 myus = 11 us, 100 myus = 99 us, 1000 myus = 1002 us, 10000 myus =
> 9991 us, 4 myus = 5 us, OK.
> Initializing internal programmer
> No coreboot table found.
> DMI string system-manufacturer: "Hewlett-Packard"
> DMI string system-product-name: "HP Compaq nc6320 (RN442AWR#ABA)"
> DMI string system-version: "F.0E"
> DMI string baseboard-manufacturer: "Hewlett-Packard"
> DMI string baseboard-product-name: "30AA"
> DMI string baseboard-version: "KBC Version 58.13"
> DMI string chassis-type: "Notebook"
> Laptop detected via DMI.
> ========================================================================
> WARNING! You seem to be running flashrom on an unsupported laptop.
> Laptops, notebooks and netbooks are difficult to support and we
> recommend to use the vendor flashing utility. The embedded controller
> (EC) in these machines often interacts badly with flashing.
> See http://www.flashrom.org/Laptops for details.
>
> If flash is shared with the EC, erase is guaranteed to brick your laptop
> and write may brick your laptop.
> Read and probe may irritate your EC and cause fan failure, backlight
> failure and sudden poweroff.
> You have been warned.
> ========================================================================
> Aborting.
>
> I can open up the case to find out what BIOS chip I have.

Or you can run flashrom like this (as root): flashrom -V -p
internal:laptop=force_I_want_a_brick
Passing additional parameters, such as reading or writing/erasing, is
not necessary (is potentionally invasive/destructive).

Idwer



From yulong.coreboot at gmail.com  Wed Jun  6 21:31:26 2012
From: yulong.coreboot at gmail.com (Yulong Zhang)
Date: Wed, 6 Jun 2012 15:31:26 -0400
Subject: [coreboot] Supported Motherboards with SMM
In-Reply-To: <C11600F1-ADF1-4732-B442-A738F0958CFD@gmail.com>
References: <C11600F1-ADF1-4732-B442-A738F0958CFD@gmail.com>
Message-ID: <001E61B7-9327-4168-A3B6-5C5BD2DE84EA@gmail.com>

Hi Fengwei,

To my knowledge, the following boards/platforms have already had SMM supported:

ASUS:		m2v-mx_se
GETAC:		p470
IBASE:		mb899
INTEL:		d945gclf, emeraldlake2
IWAVE:		iWRainbowG6
KONTRON:	986lcd-m
LENOVO:	T60, X60
RCA:		rm4100
RODA:		rk886ex
SAMSUNG:	lumpy, stumpy
THOMSON:	ip1000

If you don't want to spend effort to enable SMM by yourself, the above boards/platforms might be considered.
However, you can definitely enable SMM by yourself. Basically it requires the following steps (I assume that you wanna send sw smi):
0)	Of course the processor should have SMM and the SB should be able to generate sw smi#
1)	Initialize the SMRAM, by copying smi handlers into this region (SMRAM relocation is needed if you want the entry point to be 0xa8000 instead of 0x30000)
2)	Configure the southbridge, by setting the SMBUS/PM related registers (plz refer to the SB RRG/RPR/BDG). Don't forget to set the EOS bit, otherwise SMI# won't reach the processor
3)	If you also need ACPI modifications, you should adjust FADT

I am just a newbie to Coreboot. Plz correct me if I made a mistake.

BTW, it seems that Coreboot likes the SMM-free fashion, according to my observation. I am not sure if this is the design philosophy of Coreboot. If not, I'd like to contribute by adding SMM support.

Best,
Yulong


On Jun 6, 2012, at 2:28 PM, Fengwei Zhang wrote:

> Hi All,
> 
> My name is Fengwei. For one of my research project, I need a relative new Coreboot supported board with SMM working. I am wondering if there is a list of Coreboot supported boards with SMM working. 
> I have been working with board ASUS M2V-MX_SE, which supports SMM by applying Ruldof's patch. However, this board is very old, and I am unable to find it on the market now. 
> I would appreciate if anyone could give me some suggestions. 
> 
> Regards,
> Fengwei
> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot




From gerrit at coreboot.org  Wed Jun  6 22:00:44 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 6 Jun 2012 22:00:44 +0200
Subject: [coreboot] Patch merged into filo/master: 4193fd9 Make booting from
	ATAPI drives more resilient.
References: <Iabf20120c841bbc277af4efa48c6594804f60205+0@gerrit.coreboot.org>
Message-ID: <E1ScMPM-00079F-NT@ra.coresystems.de>

the following patch was just integrated into master:
commit 4193fd9b4921a78831f9346b02cbb004b69b16e3
Author: Nico Huber <nico.huber at secunet.com>
Date:   Fri May 25 11:34:08 2012 +0200

    Make booting from ATAPI drives more resilient.
    
    This fixes a semantic error, where the ATAPI driver requested sense from the
    drive instead of retrying a failed command (i.e. the actual command had been
    overwritten). The count of retries and delays are also adapted to behave
    more like the Linux kernel driver.
    
    Change-Id: Iabf20120c841bbc277af4efa48c6594804f60205
    Signed-off-by: Patrick Georgi <patrick.georgi at secunet.com>

Build-Tested: build bot (Jenkins) at Fri Jun  1 14:02:21 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Jun  6 22:00:43 2012, giving +2
See http://review.coreboot.org/1087 for details.

-gerrit



From GNUtoo at no-log.org  Wed Jun  6 21:53:05 2012
From: GNUtoo at no-log.org (Denis 'GNUtoo' Carikli)
Date: Wed, 06 Jun 2012 21:53:05 +0200
Subject: [coreboot] Support for HP Compaq NC6320
In-Reply-To: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
References: <CADQMMsUEQaxmtQvmON19_rvPMHTWiPcYjnXUCQgjjbFQ9Ya1ww@mail.gmail.com>
Message-ID: <1339012385.6051.2.camel@gnutoo-desktop>

On Wed, 2012-06-06 at 18:51 +0200, Ross McDonald wrote:
> Hello! I would like to use CoreBoot on my laptop. It is an HP Compaq
> NC6320. The board vendor is HP. 
I've the same laptop.

I've made an internal picture of it:
http://www.flashrom.org/File:Serduino_laptop.jpeg

> # flashrom -V
> flashrom v0.9.5.2-r1515 on Linux 3.4.0-1-ARCH (x86_64), built with libpci
> 3.1.9, GCC 4.6.3, little endian
> flashrom is free software, get the source code at http://www.flashrom.org
> 
> Calibrating delay loop... OS timer resolution is 1 usecs, 1803M loops per
> second, 10 myus = 11 us, 100 myus = 99 us, 1000 myus = 1002 us, 10000 myus
> = 9991 us, 4 myus = 5 us, OK.
> Initializing internal programmer
> No coreboot table found.
> DMI string system-manufacturer: "Hewlett-Packard"
> DMI string system-product-name: "HP Compaq nc6320 (RN442AWR#ABA)"
> DMI string system-version: "F.0E"
> DMI string baseboard-manufacturer: "Hewlett-Packard"
> DMI string baseboard-product-name: "30AA"
> DMI string baseboard-version: "KBC Version 58.13"
> DMI string chassis-type: "Notebook"
> Laptop detected via DMI.
> ========================================================================
> WARNING! You seem to be running flashrom on an unsupported laptop.
> Laptops, notebooks and netbooks are difficult to support and we
> recommend to use the vendor flashing utility. The embedded controller
> (EC) in these machines often interacts badly with flashing.
> See http://www.flashrom.org/Laptops for details.
> 
> If flash is shared with the EC, erase is guaranteed to brick your laptop
> and write may brick your laptop.
> Read and probe may irritate your EC and cause fan failure, backlight
> failure and sudden poweroff.
> You have been warned.
> ========================================================================
> Aborting.
> 
> I can open up the case to find out what BIOS chip I have.
# ./flashrom -V -p internal:laptop=force_I_want_a_brick 
flashrom v0.9.5.2-r1539 on Linux 3.0.0-20-generic (x86_64), built with
libpci 3.1.7, GCC 4.6.1, little endian
flashrom is free software, get the source code at
http://www.flashrom.org

Command line (3 args): ./flashrom -V -p
internal:laptop=force_I_want_a_brick
Calibrating delay loop... OS timer resolution is 1 usecs, 1991M loops
per second, 10 myus = 11 us, 100 myus = 101 us, 1000 myus = 1015 us,
10000 myus = 9996 us, 4 myus = 6 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "Hewlett-Packard"
DMI string system-product-name: "                                "
DMI string system-version: "F.0E"
DMI string baseboard-manufacturer: "Hewlett-Packard"
DMI string baseboard-product-name: "30AA"
DMI string baseboard-version: "KBC Version 58.13"
DMI string chassis-type: "Notebook"
Laptop detected via DMI.
========================================================================
WARNING! You seem to be running flashrom on an unsupported laptop.
Laptops, notebooks and netbooks are difficult to support and we
recommend to use the vendor flashing utility. The embedded controller
(EC) in these machines often interacts badly with flashing.
See http://www.flashrom.org/Laptops for details.

If flash is shared with the EC, erase is guaranteed to brick your laptop
and write may brick your laptop.
Read and probe may irritate your EC and cause fan failure, backlight
failure and sudden poweroff.
You have been warned.
========================================================================
Proceeding anyway because user forced us to.
Found chipset "Intel ICH7M" with PCI ID 8086:27b9. Enabling flash
write... 
0xfff80000/0xffb80000 FWH IDSEL: 0x0
0xfff00000/0xffb00000 FWH IDSEL: 0x0
0xffe80000/0xffa80000 FWH IDSEL: 0x1
0xffe00000/0xffa00000 FWH IDSEL: 0x1
0xffd80000/0xff980000 FWH IDSEL: 0x2
0xffd00000/0xff900000 FWH IDSEL: 0x2
0xffc80000/0xff880000 FWH IDSEL: 0x3
0xffc00000/0xff800000 FWH IDSEL: 0x3
0xff700000/0xff300000 FWH IDSEL: 0x4
0xff600000/0xff200000 FWH IDSEL: 0x5
0xff500000/0xff100000 FWH IDSEL: 0x6
0xff400000/0xff000000 FWH IDSEL: 0x7
0xfff80000/0xffb80000 FWH decode enabled
0xfff00000/0xffb00000 FWH decode enabled
0xffe80000/0xffa80000 FWH decode disabled
0xffe00000/0xffa00000 FWH decode disabled
0xffd80000/0xff980000 FWH decode disabled
0xffd00000/0xff900000 FWH decode disabled
0xffc80000/0xff880000 FWH decode disabled
0xffc00000/0xff800000 FWH decode disabled
0xff700000/0xff300000 FWH decode disabled
0xff600000/0xff200000 FWH decode disabled
0xff500000/0xff100000 FWH decode disabled
0xff400000/0xff000000 FWH decode disabled
Maximum FWH chip size: 0x100000 bytes
BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is
0x0
Root Complex Register Block address = 0xfed90000
GCS = 0x30460: BIOS Interface Lock-Down: disabled, Boot BIOS Straps: 0x1
(SPI)
Top Swap : not enabled
SPIBAR = 0xfed90000 + 0x3020
0x00: 0x8004     (SPIS)
0x02: 0x4200     (SPIC)
0x04: 0x00000000 (SPIA)
0x08: 0x00148020 (SPID0)
0x0c: 0x00000000 (SPID0+4)
0x10: 0x00000000 (SPID1)
0x14: 0x00000000 (SPID1+4)
0x18: 0x00000000 (SPID2)
0x1c: 0x00000000 (SPID2+4)
0x20: 0x00000000 (SPID3)
0x24: 0x00000000 (SPID3+4)
0x28: 0x00000000 (SPID4)
0x2c: 0x00000000 (SPID4+4)
0x30: 0x00000000 (SPID5)
0x34: 0x00000000 (SPID5+4)
0x38: 0x00000000 (SPID6)
0x3c: 0x00000000 (SPID6+4)
0x40: 0x00000000 (SPID7)
0x44: 0x00000000 (SPID7+4)
0x50: 0x00000000 (BBAR)
0x54: 0x5006     (PREOP)
0x56: 0x7f48     (OPTYPE)
0x58: 0x0405039f (OPMENU)
0x5c: 0x0102d852 (OPMENU+4)
0x60: 0x00000000 (PBR0)
0x64: 0x00000000 (PBR1)
0x68: 0x00000000 (PBR2)
WARNING: SPI Configuration Lockdown activated.
Reading OPCODES... done
SPI Read Configuration: prefetching disabled, caching enabled, OK.
The following protocols are supported: SPI.
Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Chip status register is 00
Found Numonyx flash chip "M25PE80" (1024 kB, SPI) at physical address
0xfff00000.
Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not
execute.
Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not
execute.
Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not
execute.
Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not
execute.
Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not
execute.
Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID.
Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID.
Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID.
Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0x20, id2
0x8014
Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0x20,
id2 0x8014
Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will
not execute.
Receiving SFDP signature failed.
Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic:
id1 0x20, id2 0x8014
Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic:
id1 0x20, id2 0x8014
Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Macronix unknown Macronix SPI chip, 0 kB:
probe_spi_rdid_generic: id1 0x20, id2 0x8014
Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1
0x20, id2 0x8014
Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic:
id1 0x20, id2 0x8014
Probing for Generic unknown SPI chip (RDID), 0 kB:
probe_spi_rdid_generic: id1 0x20, id2 0x8014
Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90,
will not execute.
Found Numonyx flash chip "M25PE80" (1024 kB, SPI).
No operations were specified.
Restoring MMIO space at 0x7f991c460070
Restoring PCI config space for 00:1f:0 reg 0xdc

Don't try such things if you don't have a way to recover(such as the way
in the picture).

Denis.




From stefan.reinauer at coreboot.org  Thu Jun  7 07:15:24 2012
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Wed, 06 Jun 2012 22:15:24 -0700
Subject: [coreboot] Supported Motherboards with SMM
In-Reply-To: <C11600F1-ADF1-4732-B442-A738F0958CFD@gmail.com>
References: <C11600F1-ADF1-4732-B442-A738F0958CFD@gmail.com>
Message-ID: <4FD038EC.9000509@coreboot.org>

On 6/6/12 11:28 AM, Fengwei Zhang wrote:
> Hi All,
>
> My name is Fengwei. For one of my research project, I need a relative new Coreboot supported board with SMM working. I am wondering if there is a list of Coreboot supported boards with SMM working.
> I have been working with board ASUS M2V-MX_SE, which supports SMM by applying Ruldof's patch. However, this board is very old, and I am unable to find it on the market now.
> I would appreciate if anyone could give me some suggestions.
>
> Regards,
> Fengwei
Here's the list of mainboards that have SMM enabled by default:

$ find src/mainboard -name Kconfig|xargs grep HAVE_SMI_HANDLER
src/mainboard/asus/m2v-mx_se/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/asus/m2v-mx_se/Kconfig:    #select HAVE_SMI_HANDLER
src/mainboard/getac/p470/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/ibase/mb899/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/intel/d945gclf/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/intel/emeraldlake2/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/iwave/iWRainbowG6/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/kontron/986lcd-m/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/lenovo/t60/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/lenovo/x60/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/rca/rm4100/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/roda/rk886ex/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/samsung/lumpy/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/samsung/stumpy/Kconfig:    select HAVE_SMI_HANDLER
src/mainboard/thomson/ip1000/Kconfig:    select HAVE_SMI_HANDLER




From wmkamp at datakamp.de  Thu Jun  7 13:29:20 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Thu, 7 Jun 2012 13:29:20 +0200
Subject: [coreboot] VGA Option ROM
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F235@DATAKAMPONE.datakamp2008.local>



Hello,

I'm using Coreboot with Seabios on the AMD Persimmon platform.
In the current versions I found a problem with the VGA Option ROM initialization.
Normally Seabios should be configured to initialize the VGA Option ROM and  Coreboot should not.
But in this scenario Coreboot does not copy the VGA ROM in the right place at C000:0, so Seabios could not find it.
If I configure Coreboot  to initialize the VGA ROM it will copy the VGA ROM to C000:0 and calls it.
Now Seabios which is configured to call Option ROMs will find the VGA ROM and also calls it. But the double initialization leads to a VGA failure.
In the older versions coreboot puts the VGA ROM always in the right place and Seabios finds it.

Could anyone help me?

Thank you

Regards

Wolfgang
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From wangqingpei at gmail.com  Thu Jun  7 17:25:34 2012
From: wangqingpei at gmail.com (QingPei Wang)
Date: Thu, 7 Jun 2012 23:25:34 +0800
Subject: [coreboot] VGA Option ROM
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DD118F235@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F235@DATAKAMPONE.datakamp2008.local>
Message-ID: <CADuV8k6D2sbJZdg0jGQH7T_fo3C3ZKTOrWuOPgK5WSGqG1rXFw@mail.gmail.com>

hi,
  seabios can search the vbios not only from C000 but also cbfs. So it
would not be a coreboot related problem. Could you please attach any log,
so more things can be found. And also that vbios got double initialization
failed would be interesting, any details?



Best wishes
QingPei Wang
Phone: 86+018930528086


On Thu, Jun 7, 2012 at 7:29 PM, Wolfgang Kamp - datakamp <wmkamp at datakamp.de
> wrote:

> ** **
>
> ** **
>
> Hello,****
>
> ** **
>
> I?m using Coreboot with Seabios on the AMD Persimmon platform. ****
>
> In the current versions I found a problem with the VGA Option ROM
> initialization.****
>
> Normally Seabios should be configured to initialize the VGA Option ROM and
>  Coreboot should not.****
>
> But in this scenario Coreboot does not copy the VGA ROM in the right place
> at C000:0, so Seabios could not find it.****
>
> If I configure Coreboot  to initialize the VGA ROM it will copy the VGA
> ROM to C000:0 and calls it.****
>
> Now Seabios which is configured to call Option ROMs will find the VGA ROM
> and also calls it. But the double initialization leads to a VGA failure.**
> **
>
> In the older versions coreboot puts the VGA ROM always in the right place
> and Seabios finds it.****
>
> ** **
>
> Could anyone help me?****
>
> ** **
>
> Thank you****
>
> ** **
>
> Regards****
>
> ** **
>
> Wolfgang****
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From andywyse6 at gmail.com  Thu Jun  7 22:31:23 2012
From: andywyse6 at gmail.com (Andy Sharp)
Date: Thu, 7 Jun 2012 13:31:23 -0700
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
Message-ID: <CAHgS8JVR8HQVKn4kTsvirK2d8oERUDXoff-MAmJctx-Q+tBOWw@mail.gmail.com>

Howdy,

I've got an AMD/persimmon board, with the agesa family 14 northbridge on
the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on them, but
coreboot isn't enabling or enumerating any of the PCIe devices on the
SB800.  Does anyone have any ideas for me?  The two devices on that
southbridge are an NEC USB3 and a Mini-PCIe slot.


Pasting the console output below for those interested:


coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
starting...
POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000000
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000001
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly passed.
SLP_TYP type was 0
POST: 0x40
agesawrapper_amdinitpost
EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.

EventLog: EventClass = 2, EventInfo = 8040100.
Param1 = a00a, Param2 = 0.
Param3 = 0, Param4 = 0.
SLP_TYP type was 0
error level: 4
POST: 0x42
agesawrapper_amdinitenv SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
POST: 0x43
POST: 0x44
POST: 0x50
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry
@ 0x200000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:05.0: enabled 0
  PCI: 00:06.0: enabled 0
  PCI: 00:07.0: enabled 0
  PCI: 00:08.0: enabled 0
  PCI: 00:11.0: enabled 1
  PCI: 00:12.0: enabled 1
  PCI: 00:12.1: enabled 1
  PCI: 00:12.2: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:13.1: enabled 1
  PCI: 00:13.2: enabled 1
  PCI: 00:14.0: enabled 1
   I2C: 00:50: enabled 1
   I2C: 00:51: enabled 1
  PCI: 00:14.1: enabled 1
  PCI: 00:14.2: enabled 1
  PCI: 00:14.3: enabled 1
   PNP: 004e.0: enabled 0
   PNP: 004e.3: enabled 0
   PNP: 004e.4: enabled 0
   PNP: 004e.5: enabled 1
   PNP: 004e.6: enabled 0
   PNP: 004e.a: enabled 0
   PNP: 004e.10: enabled 1
   PNP: 004e.11: enabled 0
  PCI: 00:14.4: enabled 1
  PCI: 00:14.5: enabled 1
  PCI: 00:15.0: enabled 0
  PCI: 00:15.1: enabled 0
  PCI: 00:15.2: enabled 0
  PCI: 00:15.3: enabled 0
  PCI: 00:16.0: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:18.0: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
  PCI: 00:18.5: enabled 1
  PCI: 00:18.6: enabled 1
  PCI: 00:18.7: enabled 1
Mainboard Persimmon Enable.
SLP_TYP type was 0
persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
persimmon_enable: uma size 0x18000000, memory start 0x67000000
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9804] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/1512] enabled
sb800_enable() SLP_TYP type was 0
PCI: 00:11.0 [1002/4393] ops
PCI: 00:11.0 [1002/4393] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable()
sb800_enable() PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
POST: 0x25
PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:14.3
PNP: 004e.0 disabled
PNP: 004e.3 disabled
PNP: 004e.4 disabled
PNP: 004e.5 enabled
PNP: 004e.6 disabled
PNP: 004e.a disabled
PNP: 004e.10 enabled
PNP: 004e.11 disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 02
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
do_pci_scan_bridge returns max 2
PCI: pci_scan_bus returning with max=002
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0

Fam14h - cpu_bus_read_resources.
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

Fam14h - domain_read_resources.
PCI_DOMAIN: 0000 read_resources bus 0 link: 0

Fam14h - read_resources.
PCI: 00:04.0 read_resources bus 1 link: 0
PCI: 00:04.0 read_resources bus 1 link: 0 done
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
SB800 - Lpc.c - lpc_read_resources - Start.
SB800 - Lpc.c - lpc_read_resources - End.
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 2 link: 0
PCI: 00:14.4 read_resources bus 2 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit
0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10
   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 14
   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff
flags 200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff
flags 80102 index 1c
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 10
    PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffffffffffff flags 1201 index 18
    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 1201 index 20
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff
flags 2200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 10
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 14
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 18
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 1c
   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20
   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff
flags 200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff
flags 200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
c0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags
80102 index 1c
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 81202 index 24
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0xff] io
PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12
limit: ffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12
limit: ffff done
PCI: 00:04.0 1c *  [0x0 - 0xfff] io
PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:11.0 20 *  [0x1400 - 0x140f] io
PCI: 00:11.0 10 *  [0x1410 - 0x1417] io
PCI: 00:11.0 18 *  [0x1418 - 0x141f] io
PCI: 00:11.0 14 *  [0x1420 - 0x1423] io
PCI: 00:11.0 1c *  [0x1424 - 0x1427] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12
gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffffffffffff
PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20
gran: 20 limit: ffffffffffffffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20
gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done
PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem
PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem
PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem
PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem
PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem
PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem
PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem
PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem
PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601
align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:12.2
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 00:50
constrain_resources: I2C: 00:51
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 004e.5
skipping PNP: 004e.5 at 62 fixed resource, size=0!
constrain_resources: PNP: 004e.10
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:18.3
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.5
constrain_resources: PCI: 00:18.6
constrain_resources: PCI: 00:18.7
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0
limit:ffff
Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io
Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io
Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io
Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io
Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io
Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align:
12 gran: 0 done
PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff
Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io
PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran:
12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
align:28 gran:0 limit:febfffff
Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem
Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem
Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem
Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem
Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem
Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem
Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem
Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem
Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size: 10247601
align: 28 gran: 0 done
PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem
Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000
align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
gran:20 limit:febfffff
Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem
PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000
align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align:
20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20
limit:febfffff
PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20
gran: 20 done
Root Device assign_resources, bus 0 link: 0

Fam14h - cpu_bus_set_resources.
APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000
gran 0x00 mem <mmconfig>
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

Fam14h - domain_set_resources.
  amsr - incoming dev = 00272248
adsr: (before) basek = 0, limitk = 7effffff.
adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.
adsr - 0xa0000 to 0xbffff resource.
adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff
0: mmio_basek=00380000, basek=00000300, limitk=001fbfff
  adsr - uma_memory_base = 67000000.
  adsr - mmio_basek = 380000.
  adsr - high_tables_size = e91000.
adsr - adding uma resource.

Fam14h - Adding UMA memory.
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
prefmem
PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08
io
PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12
mem
PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c
bus 01 io
PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14
bus 01 prefmem
PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14
bus 01 mem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
io
PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c
prefmem64
PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e
prefmem64
PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran 0x11
romem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03
io
PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02
io
PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03
io
PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02
io
PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04
io
PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran 0x0a
mem
PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran 0x0c
mem
PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran 0x08
mem
PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran 0x0c
mem
PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran 0x08
mem
PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e
mem64
SB800 - Lpc.c - lpc_set_resources - Start.
PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran 0x00
mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io
PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00
irq
ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned
PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03
io
PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00
irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
SB800 - Lpc.c - lpc_set_resources - End.
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c
bus 02 io
PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 prefmem
PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 mem
PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran 0x0c
mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
  adsr - leaving this lovely routine.
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit
0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff
flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0 limit 0
flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0
limit 0 flags f0000200 index 7
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit
febfffff flags 60001200 index 10
   PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags
60000100 index 14
   PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit
febfffff flags 60000200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff
flags 60080102 index 1c
   PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit
febfffff flags 60081202 index 24
   PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit
febfffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff
flags 60000100 index 10
    PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit
febfffff flags 60001201 index 18
    PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit
febfffff flags 60001201 index 20
    PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17 limit
febfffff flags 60002200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags
60000100 index 10
   PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags
60000100 index 14
   PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags
60000100 index 18
   PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags
60000100 index 1c
   PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags
60000100 index 20
   PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
febfffff flags 60000200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
febfffff flags 60000201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit febfffff
flags 60000200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags
c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
e0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags
60080102 index 1c
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
Done allocating resources.
POST: 0x88
Enabling resources...

Fam14h - domain_enable_resources: AmdInitMid.
agesawrapper_amdinitmid SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
  ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1510
PCI: 00:01.0 cmd <- 07
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 07
PCI: 00:11.0 subsystem <- 1022/1510
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/1510
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/1510
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1510
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/1510
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1510
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1510
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/1510
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 subsystem <- 1022/1510
PCI: 00:14.4 cmd <- 21
PCI: 00:14.5 subsystem <- 1022/1510
PCI: 00:14.5 cmd <- 02
PCI: 00:18.0 subsystem <- 1022/1510
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1510
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1510
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1510
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1510
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1510
PCI: 00:18.5 cmd <- 00
PCI: 00:18.6 subsystem <- 1022/1510
PCI: 00:18.6 cmd <- 00
PCI: 00:18.7 subsystem <- 1022/1510
PCI: 00:18.7 cmd <- 00
PCI: 01:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
model_14_init done.
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x01 done.
POST: 0x9b
model_14_init done.
CPU #1 initialized
All AP CPUs stopped (5043 loops)
PCI: 00:00.0 init
Northbridge init
PCI: 00:01.0 init
CBFS: Looking for 'pci1002,9804.rom'
CBFS: found.
In CBFS, ROM address for PCI: 00:01.0 = ffe00778
PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0
PCI ROM image, vendor ID 1002, device ID 9804,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
Getting information about VESA mode 4117
framebuffer: e0000000
Setting VESA mode 4117
PCI: 00:11.0 init
AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0
Number of Ports: 0x6, Port implemented(bit map): 0x3f
AHCI/RAID controller initialized
PCI: 00:14.0 init
CBFS: Looking for 'pci1002,4385.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1002,4385.rom'.
PCI: 00:14.4 init
PCI: 00:18.0 init
CBFS: Looking for 'pci1022,1700.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1700.rom'.
PCI: 00:18.1 init
CBFS: Looking for 'pci1022,1701.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1701.rom'.
PCI: 00:18.2 init
CBFS: Looking for 'pci1022,1702.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1702.rom'.
PCI: 00:18.3 init
CBFS: Looking for 'pci1022,1703.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1703.rom'.
PCI: 00:18.4 init
CBFS: Looking for 'pci1022,1704.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1704.rom'.
PCI: 00:18.5 init
CBFS: Looking for 'pci1022,1718.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1718.rom'.
PCI: 00:18.6 init
CBFS: Looking for 'pci1022,1716.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1716.rom'.
PCI: 00:18.7 init
CBFS: Looking for 'pci1022,1719.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci1022,1719.rom'.
PCI: 01:00.0 init
CBFS: Looking for 'pci10ec,8168.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header
CBFS: Could not find file 'pci10ec,8168.rom'.
Option ROM address for PCI: 01:00.0 = f0100000
PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect expansion ROM header signature 0000
PNP: 004e.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 004e.10 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 0
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 0
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
APIC: 01: enabled 1
PCI: 01:00.0: enabled 1
POST: 0x89
Re-Initializing CBMEM area to 0x6616f000
Initializing CBMEM area to 0x6616f000 (15273984 bytes)
dword=6616f000
nvram_pos=f8, dword>>(8*i)=0
nvram_pos=f9, dword>>(8*i)=f0
nvram_pos=fa, dword>>(8*i)=16
nvram_pos=fb, dword>>(8*i)=66
Adding CBMEM entry as no. 1
Moving GDT to 6616f200...ok
POST: 0x8a
High Tables Base is 6616f000.
POST: 0x9a
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
In agesawrapper_amdinitlate, AGESA generated ACPI tables:
   DmiTable:00000000
   AcpiPstate: 00022165
   AcpiSrat:00000000
   AcpiSlit:00000000
   Mce:00022621
   Cmc:000226c7
   Alib:00022765
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
POST: 0x9b
Wrote the mp table end at: 000f0410 - 000f0514
Adding CBMEM entry as no. 3
Wrote the mp table end at: 66170410 - 66170514
MP table: 276 bytes.
POST: 0x9c
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 66171400...
ACPI:  * DSDT at 661714c8
ACPI:  * DSDT @ 661714c8 Length 28cd
ACPI:  * FACS at 66173d98
ACPI:  * FADT at 66173dd8
ACPI_BLK_BASE: 0x0800
ACPI: added table 1/32, length now 40
ACPI:  * HPET at 66173ed0
ACPI: added table 2/32, length now 44
ACPI:  * MADT at 66173f08
ACPI: added table 3/32, length now 48
ACPI: added table 4/32, length now 52
ACPI:  * SRAT at 66174100
  AGESA SRAT table NULL. Skipping.
ACPI:  * SLIT at 66174100
  AGESA SLIT table NULL. Skipping.
ACPI:  * AGESA ALIB SSDT at 66174100
ACPI: added table 5/32, length now 56
ACPI:  * AGESA SSDT Pstate at 66175790
ACPI: added table 6/32, length now 60
ACPI:  * coreboot TOM SSDT2 at 66175aa0
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 18149 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 6617c800
Root Device (AMD Persimmon Mainboard)
APIC_CLUSTER: 0 (AMD Family 14h Root Complex)
APIC: 00 (AMD CPU Family 14h)
PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)
PCI: 00:00.0 (AMD Family 14h Northbridge)
PCI: 00:01.0 (AMD Family 14h Northbridge)
PCI: 00:01.1 (AMD Family 14h Northbridge)
PCI: 00:04.0 (AMD Family 14h Northbridge)
PCI: 00:05.0 (AMD Family 14h Northbridge)
PCI: 00:06.0 (AMD Family 14h Northbridge)
PCI: 00:07.0 (AMD Family 14h Northbridge)
PCI: 00:08.0 (AMD Family 14h Northbridge)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.1 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.1 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 ()
I2C: 00:51 ()
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 004e.0 (Fintek F81865F Super I/O)
PNP: 004e.3 (Fintek F81865F Super I/O)
PNP: 004e.4 (Fintek F81865F Super I/O)
PNP: 004e.5 (Fintek F81865F Super I/O)
PNP: 004e.6 (Fintek F81865F Super I/O)
PNP: 004e.a (Fintek F81865F Super I/O)
PNP: 004e.10 (Fintek F81865F Super I/O)
PNP: 004e.11 (Fintek F81865F Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:16.2 (ATI SB800)
PCI: 00:18.0 (AMD Family 14h Northbridge)
PCI: 00:18.1 (AMD Family 14h Northbridge)
PCI: 00:18.2 (AMD Family 14h Northbridge)
PCI: 00:18.3 (AMD Family 14h Northbridge)
PCI: 00:18.4 (AMD Family 14h Northbridge)
PCI: 00:18.5 (AMD Family 14h Northbridge)
PCI: 00:18.6 (AMD Family 14h Northbridge)
PCI: 00:18.7 (AMD Family 14h Northbridge)
APIC: 01 ()
PCI: 01:00.0 ()
SMBIOS tables: 287 bytes.
POST: 0x9d
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x6617d000
rom_table_end = 0x6617d000
Adjust low_table_end from 0x00000528 to 0x00001000
Adjust rom_table_end from 0x6617d000 to 0x66180000
Adding high table area
uma_memory_start=0x67000000, uma_memory_size=0x18000000
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000006616efff: RAM
 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES
 4. 0000000067000000-000000007effffff: RESERVED
 5. 00000000f8000000-00000000f8ffffff: RESERVED
Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f
coreboot table: 532 bytes.
POST: 0x9e
Adding CBMEM entry as no. 7
Adding CBMEM entry as no. 8
POST: 0x9d
Multiboot Information structure has been written.
 0. FREE SPACE 66ff6000 0000a000
 1. GDT        6616f200 00000200
 2. IRQ TABLE  6616f400 00001000
 3. SMP TABLE  66170400 00001000
 4. ACPI       66171400 0000b400
 5. SMBIOS     6617c800 00000800
 6. COREBOOT   6617d000 00008000
 7. ACPI RESUME66185000 00e00000
 8. ACPISCRATCH66f85000 00071000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
Loading segment from rom address 0xffee35f8
  code (compression=0)
  New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630 filesize
0x18b60
  (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
filesize 0x18b60
Loading segment from rom address 0xffee3614
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60
lb: [0x0000000000200000, 0x0000000000360000)
Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60
it's not compressed!
[ 0x000e74a0, 00100000, 0x00100000) <- ffee3630
dest 000e74a0, end 00100000, bouncebuffer 65eaf000
Loaded segments
Jumping to boot code at fc855
POST: 0xf8
entry    = 0x000fc855
lb_start = 0x00200000
lb_size  = 0x00160000
adjust   = 0x65e0f000
buffer   = 0x65eaf000
     elf_boot_notes = 0x00272e18
adjusted_boot_notes = 0x66081e18
Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)
Found mainboard AMD Persimmon
Found CBFS header at 0xfffffbf0
Ram Size=0x6616f000 (0x0000000000000000 high)
Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)
CPU Mhz=1001
Found 22 PCI devices (max PCI bus is 02)
Found 2 cpu(s) max supported 2 cpu(s)
Copying PIR from 0x6616f400 to 0x000fdbc0
Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0
Copying ACPI RSDP from 0x66171400 to 0x000fda80
Copying SMBIOS entry point from 0x6617c800 to 0x000fda60
Scan for VGA option rom
Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b
EHCI init on dev 00:12.2 (regs=0xf0247420)
EHCI init on dev 00:13.2 (regs=0xf0247520)
OHCI init on dev 00:14.5 (regs=0xf0246000)
Found 0 lpt ports
Found 3 serial ports
ebda moved from 9fc00 to 9f400
AHCI controller at 11.0, iobase f0247000, irq 0
OHCI init on dev 00:12.0 (regs=0xf0244000)
Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0
ebda moved from 9f400 to 9f000
ebda moved from 9f000 to 9ec00
AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
MiBytes)"
Got ps2 nak (status=51)
USB keyboard initialized
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=125045424
Returned 57344 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009ec00 = 1 RAM
  1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000006616d000 = 1 RAM
  4: 000000006616d000 - 000000007f000000 = 2 RESERVED
  5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00
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From gerrit at coreboot.org  Thu Jun  7 23:12:46 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:12:46 +0200
Subject: [coreboot] Patch merged into coreboot/master: 677206d libpayload:
	Bring USB hub driver to a working state
References: <I80bf03f3117116a60382b87a4f84366370649915+0@gerrit.coreboot.org>
Message-ID: <E1Sck0c-00029D-Qb@ra.coresystems.de>

the following patch was just integrated into master:
commit 677206d4a32112759afe93c36b9d4ed9931b0f2b
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 16:20:59 2012 +0200

    libpayload: Bring USB hub driver to a working state
    
    This adds proper device attachment and detachment detection and port enable-
    ment to the USB hub driver. Support for split transactions is still missing,
    so this works only with USB2.0 devices on hubs in USB2.0 mode and USB1.1
    devices on hubs in USB1.1 mode.
    
    Change-Id: I80bf03f3117116a60382b87a4f84366370649915
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 18:52:01 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:12:44 2012, giving +2
See http://review.coreboot.org/1080 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  7 23:14:20 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:14:20 +0200
Subject: [coreboot] Patch merged into coreboot/master: 405fa26 libpayload:
	Add support for split transactions in EHCI
References: <I30fa1ce25757f33b1e6ed34207949c9255f05d49+0@gerrit.coreboot.org>
Message-ID: <E1Sck28-0002O9-GC@ra.coresystems.de>

the following patch was just integrated into master:
commit 405fa269240133fc6fdbc8ee6976e923fc68642b
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed May 23 09:21:54 2012 +0200

    libpayload: Add support for split transactions in EHCI
    
    With split transactions, the EHCI host controller can handle full- and
    low-speed devices on hubs in high-speed mode. This adds support for split
    transactions for control and bulk transfers.
    
    Change-Id: I30fa1ce25757f33b1e6ed34207949c9255f05d49
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 19:24:05 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:14:17 2012, giving +2
See http://review.coreboot.org/1081 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  7 23:15:30 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:15:30 +0200
Subject: [coreboot] Patch merged into coreboot/master: bab3243 libpayload:
	Free intr queue structure in usb_hid_destroy
References: <I51ccc6a79bc005819317263be24a56c51acd5f55+0@gerrit.coreboot.org>
Message-ID: <E1Sck3G-00031M-2D@ra.coresystems.de>

the following patch was just integrated into master:
commit bab32430f9e8c9588912ff41ce48ede6edd129b4
Author: Nico Huber <nico.huber at secunet.com>
Date:   Fri May 25 09:59:19 2012 +0200

    libpayload: Free intr queue structure in usb_hid_destroy
    
    The call to destroy_intr_queue was missing in usb_hid_destroy.
    
    Change-Id: I51ccc6a79bc005819317263be24a56c51acd5f55
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 19:40:58 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:15:27 2012, giving +2
See http://review.coreboot.org/1082 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  7 23:16:40 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:16:40 +0200
Subject: [coreboot] Patch merged into coreboot/master: 291be8f libpayload:
	Add support for interrupt transfers in EHCI
References: <I9eb08f12b12c67ece10814952cb8651278b02f9d+0@gerrit.coreboot.org>
Message-ID: <E1Sck4O-0003ck-CP@ra.coresystems.de>

the following patch was just integrated into master:
commit 291be8f0a7480943e53c60b44d139e21fc9147d1
Author: Nico Huber <nico.huber at secunet.com>
Date:   Fri May 25 10:09:13 2012 +0200

    libpayload: Add support for interrupt transfers in EHCI
    
    This adds support for usb interrupt transfers in the EHCI driver. Split
    transactions are supported, so this enables support for HID keyboards
    devices over hubs in high-speed mode.
    
    Change-Id: I9eb08f12b12c67ece10814952cb8651278b02f9d
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 19:57:36 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:16:23 2012, giving +2
See http://review.coreboot.org/1083 for details.

-gerrit



From gerrit at coreboot.org  Thu Jun  7 23:49:04 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:49:04 +0200
Subject: [coreboot] Patch merged into coreboot/master: 309aa8c libpayload:
	Add timeouts in the OHCI USB driver
References: <I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e+0@gerrit.coreboot.org>
Message-ID: <E1SckZk-00019T-Ex@ra.coresystems.de>

the following patch was just integrated into master:
commit 309aa8cc0731941ea7b219c8a374bbe182c44891
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:46:26 2012 +0200

    libpayload: Add timeouts in the OHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts and a more standard compliant port reset to the OHCI driver.
    
    Change-Id: I2cfcb1039fd12f291e88dcb8b74d41cb5bb2315e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 17:52:05 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:48:29 2012, giving +2
See http://review.coreboot.org/1076 for details.

-gerrit



From gerrit at coreboot.org  Fri Jun  8 00:01:28 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 8 Jun 2012 00:01:28 +0200
Subject: [coreboot] Patch merged into coreboot/master: 2f51d92 libpayload:
	Add timeouts in the EHCI USB driver
References: <I13ba532a6daf47510b16b8fdbe572a21f1d8b09c+0@gerrit.coreboot.org>
Message-ID: <E1Scklk-0004PN-Nv@ra.coresystems.de>

the following patch was just integrated into master:
commit 2f51d9239824baaac28029b5cabb69f1cad06236
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:53:43 2012 +0200

    libpayload: Add timeouts in the EHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts to the EHCI driver.
    
    Change-Id: I13ba532a6daf47510b16b8fdbe572a21f1d8b09c
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 18:07:02 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Jun  8 00:00:56 2012, giving +2
See http://review.coreboot.org/1077 for details.

-gerrit



From steve.goodrich at se-eng.com  Thu Jun  7 23:54:13 2012
From: steve.goodrich at se-eng.com (Steve Goodrich)
Date: Thu, 7 Jun 2012 15:54:13 -0600
Subject: [coreboot]  PCIe devices not enabled on amd/persimmon
Message-ID: <017d01cd44f8$13ca5de0$3b5f19a0$@goodrich@se-eng.com>

ARG.. Thanks, Outlook.  :P

 

Andy,

 

Check the devicetree.cb file in your ./src/mainboard/amd/persimmon folder.
Mine shows:

 

            device pci 15.0 off end # PCIe PortA

            device pci 15.1 off end # PCIe PortB

            device pci 15.2 off end # PCIe PortC

            device pci 15.3 off end # PCIe PortD

 

I'm not 100% certain, but I suspect that changing these from "off" to "on"
will enable the devices.  Try the change and see if the console output
starts reflecting the devices you're looking for.

 

            -- Steve G.

 

 

 

From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
On Behalf Of Andy Sharp
Sent: Thursday, June 07, 2012 2:31 PM
To: coreboot at coreboot.org
Subject: [coreboot] PCIe devices not enabled on amd/persimmon

 

Howdy,

 

I've got an AMD/persimmon board, with the agesa family 14 northbridge on the
CPU, and the SB800 southbridge.  Both have 4 PCIe ports on them, but
coreboot isn't enabling or enumerating any of the PCIe devices on the SB800.
Does anyone have any ideas for me?  The two devices on that southbridge are
an NEC USB3 and a Mini-PCIe slot.

 

 

Pasting the console output below for those interested:

 

 

coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
starting...

POST: 0x34

BSP Family_Model: 00500f20 

cpu_init_detectedx = 00000000 

POST: 0x35

agesawrapper_amdinitmmio passed.

POST: 0x37

agesawrapper_amdinitreset passed.

POST: 0x39

agesawrapper_amdinitearly POST: 0x34

BSP Family_Model: 00500f20 

cpu_init_detectedx = 00000001 

POST: 0x35

agesawrapper_amdinitmmio passed.

POST: 0x37

agesawrapper_amdinitreset passed.

POST: 0x39

agesawrapper_amdinitearly passed.

SLP_TYP type was 0

POST: 0x40

agesawrapper_amdinitpost 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

SLP_TYP type was 0

error level: 4 

POST: 0x42

agesawrapper_amdinitenv SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

passed.

POST: 0x43

POST: 0x44

POST: 0x50

Loading image.

CBFS: Looking for 'fallback/coreboot_ram'

CBFS: found.

CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry
@ 0x200000

Jumping to image.

POST: 0x80

POST: 0x39

coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
booting...

POST: 0x40

Enumerating buses...

Show all devs...Before device enumeration.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:01.0: enabled 1

PCI: 00:01.1: enabled 1

PCI: 00:04.0: enabled 1

PCI: 00:05.0: enabled 0

PCI: 00:06.0: enabled 0

PCI: 00:07.0: enabled 0

PCI: 00:08.0: enabled 0

PCI: 00:11.0: enabled 1

PCI: 00:12.0: enabled 1

PCI: 00:12.1: enabled 1

PCI: 00:12.2: enabled 1

PCI: 00:13.0: enabled 1

PCI: 00:13.1: enabled 1

PCI: 00:13.2: enabled 1

PCI: 00:14.0: enabled 1

I2C: 00:50: enabled 1

I2C: 00:51: enabled 1

PCI: 00:14.1: enabled 1

PCI: 00:14.2: enabled 1

PCI: 00:14.3: enabled 1

PNP: 004e.0: enabled 0

PNP: 004e.3: enabled 0

PNP: 004e.4: enabled 0

PNP: 004e.5: enabled 1

PNP: 004e.6: enabled 0

PNP: 004e.a: enabled 0

PNP: 004e.10: enabled 1

PNP: 004e.11: enabled 0

PCI: 00:14.4: enabled 1

PCI: 00:14.5: enabled 1

PCI: 00:15.0: enabled 0

PCI: 00:15.1: enabled 0

PCI: 00:15.2: enabled 0

PCI: 00:15.3: enabled 0

PCI: 00:16.0: enabled 0

PCI: 00:16.2: enabled 0

PCI: 00:18.0: enabled 1

PCI: 00:18.1: enabled 1

PCI: 00:18.2: enabled 1

PCI: 00:18.3: enabled 1

PCI: 00:18.4: enabled 1

PCI: 00:18.5: enabled 1

PCI: 00:18.6: enabled 1

PCI: 00:18.7: enabled 1

Compare with tree...

Root Device: enabled 1

 APIC_CLUSTER: 0: enabled 1

  APIC: 00: enabled 1

 PCI_DOMAIN: 0000: enabled 1

  PCI: 00:00.0: enabled 1

  PCI: 00:01.0: enabled 1

  PCI: 00:01.1: enabled 1

  PCI: 00:04.0: enabled 1

  PCI: 00:05.0: enabled 0

  PCI: 00:06.0: enabled 0

  PCI: 00:07.0: enabled 0

  PCI: 00:08.0: enabled 0

  PCI: 00:11.0: enabled 1

  PCI: 00:12.0: enabled 1

  PCI: 00:12.1: enabled 1

  PCI: 00:12.2: enabled 1

  PCI: 00:13.0: enabled 1

  PCI: 00:13.1: enabled 1

  PCI: 00:13.2: enabled 1

  PCI: 00:14.0: enabled 1

   I2C: 00:50: enabled 1

   I2C: 00:51: enabled 1

  PCI: 00:14.1: enabled 1

  PCI: 00:14.2: enabled 1

  PCI: 00:14.3: enabled 1

   PNP: 004e.0: enabled 0

   PNP: 004e.3: enabled 0

   PNP: 004e.4: enabled 0

   PNP: 004e.5: enabled 1

   PNP: 004e.6: enabled 0

   PNP: 004e.a: enabled 0

   PNP: 004e.10: enabled 1

   PNP: 004e.11: enabled 0

  PCI: 00:14.4: enabled 1

  PCI: 00:14.5: enabled 1

  PCI: 00:15.0: enabled 0

  PCI: 00:15.1: enabled 0

  PCI: 00:15.2: enabled 0

  PCI: 00:15.3: enabled 0

  PCI: 00:16.0: enabled 0

  PCI: 00:16.2: enabled 0

  PCI: 00:18.0: enabled 1

  PCI: 00:18.1: enabled 1

  PCI: 00:18.2: enabled 1

  PCI: 00:18.3: enabled 1

  PCI: 00:18.4: enabled 1

  PCI: 00:18.5: enabled 1

  PCI: 00:18.6: enabled 1

  PCI: 00:18.7: enabled 1

Mainboard Persimmon Enable.

SLP_TYP type was 0

persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000

persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000

persimmon_enable: uma size 0x18000000, memory start 0x67000000

scan_static_bus for Root Device

APIC_CLUSTER: 0 enabled

PCI_DOMAIN: 0000 enabled

APIC_CLUSTER: 0 scanning...

  AP siblings=1

CPU: APIC: 00 enabled

CPU: APIC: 01 enabled

PCI_DOMAIN: 0000 scanning...

PCI: pci_scan_bus for bus 00

POST: 0x24

PCI: 00:00.0 [1022/1510] ops

PCI: 00:00.0 [1022/1510] enabled

PCI: 00:01.0 [1002/9804] enabled

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

Capability: type 0x05 @ 0xa0

Capability: type 0x0d @ 0xb0

Capability: type 0x08 @ 0xb8

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

PCI: 00:04.0 subordinate bus PCI Express

PCI: 00:04.0 [1022/1512] enabled

sb800_enable() SLP_TYP type was 0

PCI: 00:11.0 [1002/4393] ops

PCI: 00:11.0 [1002/4393] enabled

sb800_enable() PCI: 00:12.0 [1002/4397] ops

PCI: 00:12.0 [1002/4397] enabled

sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.

sb800_enable() PCI: 00:12.2 [1002/4396] ops

PCI: 00:12.2 [1002/4396] enabled

sb800_enable() PCI: 00:13.0 [1002/4397] ops

PCI: 00:13.0 [1002/4397] enabled

sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.

sb800_enable() PCI: 00:13.2 [1002/4396] ops

PCI: 00:13.2 [1002/4396] enabled

sb800_enable() sm_init().

IOAPIC: Clearing IOAPIC at 0xfec00000

IOAPIC: 23 interrupts

IOAPIC: reg 0x00000000 value 0x00000000 0x00010000

IOAPIC: reg 0x00000001 value 0x00000000 0x00010000

IOAPIC: reg 0x00000002 value 0x00000000 0x00010000

IOAPIC: reg 0x00000003 value 0x00000000 0x00010000

IOAPIC: reg 0x00000004 value 0x00000000 0x00010000

IOAPIC: reg 0x00000005 value 0x00000000 0x00010000

IOAPIC: reg 0x00000006 value 0x00000000 0x00010000

IOAPIC: reg 0x00000007 value 0x00000000 0x00010000

IOAPIC: reg 0x00000008 value 0x00000000 0x00010000

IOAPIC: reg 0x00000009 value 0x00000000 0x00010000

IOAPIC: reg 0x0000000a value 0x00000000 0x00010000

IOAPIC: reg 0x0000000b value 0x00000000 0x00010000

IOAPIC: reg 0x0000000c value 0x00000000 0x00010000

IOAPIC: reg 0x0000000d value 0x00000000 0x00010000

IOAPIC: reg 0x0000000e value 0x00000000 0x00010000

IOAPIC: reg 0x0000000f value 0x00000000 0x00010000

IOAPIC: reg 0x00000010 value 0x00000000 0x00010000

IOAPIC: reg 0x00000011 value 0x00000000 0x00010000

IOAPIC: reg 0x00000012 value 0x00000000 0x00010000

IOAPIC: reg 0x00000013 value 0x00000000 0x00010000

IOAPIC: reg 0x00000014 value 0x00000000 0x00010000

IOAPIC: reg 0x00000015 value 0x00000000 0x00010000

IOAPIC: reg 0x00000016 value 0x00000000 0x00010000

IOAPIC: Initializing IOAPIC at 0xfec00000

IOAPIC: Bootstrap Processor Local APIC = 0x00

IOAPIC: ID = 0x02

IOAPIC: 23 interrupts

IOAPIC: Enabling interrupts on FSB

IOAPIC: reg 0x00000000 value 0x00000000 0x00000700

IOAPIC: reg 0x00000001 value 0x00000000 0x00010000

IOAPIC: reg 0x00000002 value 0x00000000 0x00010000

IOAPIC: reg 0x00000003 value 0x00000000 0x00010000

IOAPIC: reg 0x00000004 value 0x00000000 0x00010000

IOAPIC: reg 0x00000005 value 0x00000000 0x00010000

IOAPIC: reg 0x00000006 value 0x00000000 0x00010000

IOAPIC: reg 0x00000007 value 0x00000000 0x00010000

IOAPIC: reg 0x00000008 value 0x00000000 0x00010000

IOAPIC: reg 0x00000009 value 0x00000000 0x00010000

IOAPIC: reg 0x0000000a value 0x00000000 0x00010000

IOAPIC: reg 0x0000000b value 0x00000000 0x00010000

IOAPIC: reg 0x0000000c value 0x00000000 0x00010000

IOAPIC: reg 0x0000000d value 0x00000000 0x00010000

IOAPIC: reg 0x0000000e value 0x00000000 0x00010000

IOAPIC: reg 0x0000000f value 0x00000000 0x00010000

IOAPIC: reg 0x00000010 value 0x00000000 0x00010000

IOAPIC: reg 0x00000011 value 0x00000000 0x00010000

IOAPIC: reg 0x00000012 value 0x00000000 0x00010000

IOAPIC: reg 0x00000013 value 0x00000000 0x00010000

IOAPIC: reg 0x00000014 value 0x00000000 0x00010000

IOAPIC: reg 0x00000015 value 0x00000000 0x00010000

IOAPIC: reg 0x00000016 value 0x00000000 0x00010000

PCI: 00:14.0 [1002/4385] enabled

sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.

sb800_enable() hda enabled

PCI: 00:14.2 [1002/4383] ops

PCI: 00:14.2 [1002/4383] enabled

sb800_enable() PCI: 00:14.3 [1002/439d] bus ops

PCI: 00:14.3 [1002/439d] enabled

sb800_enable() PCI: 00:14.4 [1002/4384] bus ops

PCI: 00:14.4 [1002/4384] enabled

sb800_enable() PCI: 00:14.5 [1002/4399] ops

PCI: 00:14.5 [1002/4399] enabled

sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable()
sb800_enable() PCI: 00:18.0 [1022/1700] enabled

PCI: 00:18.1 [1022/1701] enabled

PCI: 00:18.2 [1022/1702] enabled

PCI: 00:18.3 [1022/1703] enabled

PCI: 00:18.4 [1022/1704] enabled

PCI: 00:18.5 [1022/1718] enabled

PCI: 00:18.6 [1022/1716] enabled

PCI: 00:18.7 [1022/1719] enabled

POST: 0x25

PCI: Left over static devices:

PCI: 00:01.1

PCI: Check your devicetree.cb.

do_pci_scan_bridge for PCI: 00:04.0

PCI: pci_scan_bus for bus 01

POST: 0x24

PCI: 01:00.0 [10ec/8168] enabled

POST: 0x25

PCI: pci_scan_bus returning with max=001

POST: 0x55

Capability: type 0x01 @ 0x40

Capability: type 0x05 @ 0x50

Capability: type 0x10 @ 0x70

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

do_pci_scan_bridge returns max 1

scan_static_bus for PCI: 00:14.3

PNP: 004e.0 disabled

PNP: 004e.3 disabled

PNP: 004e.4 disabled

PNP: 004e.5 enabled

PNP: 004e.6 disabled

PNP: 004e.a disabled

PNP: 004e.10 enabled

PNP: 004e.11 disabled

scan_static_bus for PCI: 00:14.3 done

do_pci_scan_bridge for PCI: 00:14.4

PCI: pci_scan_bus for bus 02

POST: 0x24

POST: 0x25

PCI: pci_scan_bus returning with max=002

POST: 0x55

do_pci_scan_bridge returns max 2

PCI: pci_scan_bus returning with max=002

POST: 0x55

scan_static_bus for Root Device done

done

POST: 0x66

Setting up VGA for PCI: 00:01.0

Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000

Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

Allocating resources...

Reading resources...

Root Device read_resources bus 0 link: 0

 

Fam14h - cpu_bus_read_resources.

APIC_CLUSTER: 0 read_resources bus 0 link: 0

APIC: 00 missing read_resources

APIC: 01 missing read_resources

APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

 

Fam14h - domain_read_resources.

PCI_DOMAIN: 0000 read_resources bus 0 link: 0

 

Fam14h - read_resources.

PCI: 00:04.0 read_resources bus 1 link: 0

PCI: 00:04.0 read_resources bus 1 link: 0 done

PCI: 00:14.0 read_resources bus 0 link: 0

I2C: 00:50 missing read_resources

I2C: 00:51 missing read_resources

PCI: 00:14.0 read_resources bus 0 link: 0 done

SB800 - Lpc.c - lpc_read_resources - Start.

SB800 - Lpc.c - lpc_read_resources - End.

PCI: 00:14.3 read_resources bus 0 link: 0

PCI: 00:14.3 read_resources bus 0 link: 0 done

PCI: 00:14.4 read_resources bus 2 link: 0

PCI: 00:14.4 read_resources bus 2 link: 0 done

PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done

Root Device read_resources bus 0 link: 0 done

Done reading resources.

Show resources in subtree (Root Device)...After reading.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0
flags f0000200 index c0010058

   APIC: 00

   APIC: 01

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100

   PCI: 00:00.0

   PCI: 00:01.0

   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10

   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100
index 14

   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff
flags 200 index 18

   PCI: 00:04.0 child on link 0 PCI: 01:00.0

   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags
80102 index 1c

   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24

   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20

    PCI: 01:00.0

    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 10

    PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffffffffffff flags 1201 index 18

    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 1201 index 20

    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff
flags 2200 index 30

   PCI: 00:05.0

   PCI: 00:06.0

   PCI: 00:07.0

   PCI: 00:08.0

   PCI: 00:11.0

   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 10

   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 14

   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 18

   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 1c

   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20

   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff
flags 200 index 24

   PCI: 00:12.0

   PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:12.1

   PCI: 00:12.2

   PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
200 index 10

   PCI: 00:13.0

   PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:13.1

   PCI: 00:13.2

   PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
200 index 10

   PCI: 00:14.0 child on link 0 I2C: 00:50

    I2C: 00:50

    I2C: 00:51

   PCI: 00:14.1

   PCI: 00:14.2

   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 201 index 10

   PCI: 00:14.3 child on link 0 PNP: 004e.0

   PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
200 index a0

   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000

   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100

   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3

    PNP: 004e.0

    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74

    PNP: 004e.3

    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74

    PNP: 004e.4

    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60

    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.5

    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60

    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
c0000100 index 62

    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72

    PNP: 004e.6

    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.a

    PNP: 004e.10

    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

    PNP: 004e.11

    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

   PCI: 00:14.4

   PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags
80102 index 1c

   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
81202 index 24

   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20

   PCI: 00:14.5

   PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:15.0

   PCI: 00:15.1

   PCI: 00:15.2

   PCI: 00:15.3

   PCI: 00:16.0

   PCI: 00:16.2

   PCI: 00:18.0

   PCI: 00:18.1

   PCI: 00:18.2

   PCI: 00:18.3

   PCI: 00:18.4

   PCI: 00:18.5

   PCI: 00:18.6

   PCI: 00:18.7

PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff

PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffffffff

PCI: 01:00.0 10 *  [0x0 - 0xff] io

PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12
limit: ffff done

PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff

PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff done

PCI: 00:04.0 1c *  [0x0 - 0xfff] io

PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io

PCI: 00:11.0 20 *  [0x1400 - 0x140f] io

PCI: 00:11.0 10 *  [0x1410 - 0x1417] io

PCI: 00:11.0 18 *  [0x1418 - 0x141f] io

PCI: 00:11.0 14 *  [0x1420 - 0x1423] io

PCI: 00:11.0 1c *  [0x1424 - 0x1427] io

PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran:
0 limit: ffff done

PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff

PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffffffffffff

PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem

PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem

PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20
gran: 20 limit: ffffffffffffffff done

PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem

PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran:
20 limit: ffffffff done

PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done

PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done

PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem

PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem

PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem

PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem

PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem

PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem

PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem

PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem

PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem

PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem

PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem

PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem

PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601 align:
28 gran: 0 limit: ffffffff done

avoid_fixed_resources: PCI_DOMAIN: 0000

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff

constrain_resources: PCI_DOMAIN: 0000

constrain_resources: PCI: 00:00.0

constrain_resources: PCI: 00:01.0

constrain_resources: PCI: 00:04.0

constrain_resources: PCI: 01:00.0

constrain_resources: PCI: 00:11.0

constrain_resources: PCI: 00:12.0

constrain_resources: PCI: 00:12.2

constrain_resources: PCI: 00:13.0

constrain_resources: PCI: 00:13.2

constrain_resources: PCI: 00:14.0

constrain_resources: I2C: 00:50

constrain_resources: I2C: 00:51

constrain_resources: PCI: 00:14.2

constrain_resources: PCI: 00:14.3

constrain_resources: PNP: 004e.5

skipping PNP: 004e.5 at 62 fixed resource, size=0!

constrain_resources: PNP: 004e.10

constrain_resources: PCI: 00:14.4

constrain_resources: PCI: 00:14.5

constrain_resources: PCI: 00:18.0

constrain_resources: PCI: 00:18.1

constrain_resources: PCI: 00:18.2

constrain_resources: PCI: 00:18.3

constrain_resources: PCI: 00:18.4

constrain_resources: PCI: 00:18.5

constrain_resources: PCI: 00:18.6

constrain_resources: PCI: 00:18.7

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff

          lim->base 00001000 lim->limit 0000ffff

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff

          lim->base 00000000 lim->limit febfffff

Setting resources...

PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0
limit:ffff

Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io

Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io

Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io

Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io

Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io

Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io

Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io

PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12
gran: 0 done

PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff

Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io

PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
gran: 12 done

PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff

PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran:
12 done

PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
align:28 gran:0 limit:febfffff

Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem

Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem

Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem

Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem

Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem

Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem

Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem

Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem

Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem

Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem

Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem

Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem

PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size: 10247601
align: 28 gran: 0 done

PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20
gran:20 limit:febfffff

Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem

Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem

PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000
align: 20 gran: 20 done

PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
gran:20 limit:febfffff

Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem

PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000 align:
20 gran: 20 done

PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff

PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align:
20 gran: 20 done

PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20
limit:febfffff

PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20
gran: 20 done

Root Device assign_resources, bus 0 link: 0

 

Fam14h - cpu_bus_set_resources.

APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000
gran 0x00 mem <mmconfig>

APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

 

Fam14h - domain_set_resources.

  amsr - incoming dev = 00272248

adsr: (before) basek = 0, limitk = 7effffff.

adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.

adsr - 0xa0000 to 0xbffff resource.

adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff

0: mmio_basek=00380000, basek=00000300, limitk=001fbfff

  adsr - uma_memory_base = 67000000.

  adsr - mmio_basek = 380000.

  adsr - high_tables_size = e91000.

adsr - adding uma resource.

 

Fam14h - Adding UMA memory.

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
prefmem

PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08
io

PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12
mem

PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c
bus 01 io

PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14
bus 01 prefmem

PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14
bus 01 mem

PCI: 00:04.0 assign_resources, bus 1 link: 0

PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
io

PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c
prefmem64

PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e
prefmem64

PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran 0x11
romem

PCI: 00:04.0 assign_resources, bus 1 link: 0

PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03
io

PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02
io

PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03
io

PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02
io

PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04
io

PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran 0x0a
mem

PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran 0x0c
mem

PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran 0x08
mem

PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran 0x0c
mem

PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran 0x08
mem

PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e
mem64

SB800 - Lpc.c - lpc_set_resources - Start.

PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran 0x00
mem

PCI: 00:14.3 assign_resources, bus 0 link: 0

PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io

PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io

PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00
irq

ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned

PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03
io

PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00
irq

PCI: 00:14.3 assign_resources, bus 0 link: 0

SB800 - Lpc.c - lpc_set_resources - End.

PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c
bus 02 io

PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 prefmem

PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 mem

PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran 0x0c
mem

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

  adsr - leaving this lovely routine.

Root Device assign_resources, bus 0 link: 0

Done setting resources.

Show resources in subtree (Root Device)...After assigning values.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0
flags f0000200 index c0010058

   APIC: 00

   APIC: 01

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff
flags 40040100 index 10000000

  PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
limit febfffff flags 40040200 index 10000100

  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 10

  PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0 limit 0
flags e0004200 index 20

  PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0 limit
0 flags f0000200 index 7

   PCI: 00:00.0

   PCI: 00:01.0

   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit
febfffff flags 60001200 index 10

   PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags
60000100 index 14

   PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit
febfffff flags 60000200 index 18

   PCI: 00:04.0 child on link 0 PCI: 01:00.0

   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff
flags 60080102 index 1c

   PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit
febfffff flags 60081202 index 24

   PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit
febfffff flags 60080202 index 20

    PCI: 01:00.0

    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
60000100 index 10

    PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit
febfffff flags 60001201 index 18

    PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit
febfffff flags 60001201 index 20

    PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17 limit
febfffff flags 60002200 index 30

   PCI: 00:05.0

   PCI: 00:06.0

   PCI: 00:07.0

   PCI: 00:08.0

   PCI: 00:11.0

   PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags
60000100 index 10

   PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags
60000100 index 14

   PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags
60000100 index 18

   PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags
60000100 index 1c

   PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags
60000100 index 20

   PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
febfffff flags 60000200 index 24

   PCI: 00:12.0

   PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:12.1

   PCI: 00:12.2

   PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10

   PCI: 00:13.0

   PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:13.1

   PCI: 00:13.2

   PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10

   PCI: 00:14.0 child on link 0 I2C: 00:50

    I2C: 00:50

    I2C: 00:51

   PCI: 00:14.1

   PCI: 00:14.2

   PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
febfffff flags 60000201 index 10

   PCI: 00:14.3 child on link 0 PNP: 004e.0

   PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit febfffff
flags 60000200 index a0

   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000

   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100

   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3

    PNP: 004e.0

    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74

    PNP: 004e.3

    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74

    PNP: 004e.4

    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60

    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.5

    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60

    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
e0000100 index 62

    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400
index 70

    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72

    PNP: 004e.6

    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.a

    PNP: 004e.10

    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60

    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70

    PNP: 004e.11

    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

   PCI: 00:14.4

   PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags
60080102 index 1c

   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24

   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20

   PCI: 00:14.5

   PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:15.0

   PCI: 00:15.1

   PCI: 00:15.2

   PCI: 00:15.3

   PCI: 00:16.0

   PCI: 00:16.2

   PCI: 00:18.0

   PCI: 00:18.1

   PCI: 00:18.2

   PCI: 00:18.3

   PCI: 00:18.4

   PCI: 00:18.5

   PCI: 00:18.6

   PCI: 00:18.7

Done allocating resources.

POST: 0x88

Enabling resources...

 

Fam14h - domain_enable_resources: AmdInitMid.

agesawrapper_amdinitmid SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

passed.

  ader - leaving domain_enable_resources.

PCI: 00:00.0 cmd <- 06

PCI: 00:01.0 subsystem <- 1022/1510

PCI: 00:01.0 cmd <- 07

PCI: 00:04.0 bridge ctrl <- 0003

PCI: 00:04.0 cmd <- 07

PCI: 00:11.0 subsystem <- 1022/1510

PCI: 00:11.0 cmd <- 03

PCI: 00:12.0 subsystem <- 1022/1510

PCI: 00:12.0 cmd <- 02

PCI: 00:12.2 subsystem <- 1022/1510

PCI: 00:12.2 cmd <- 02

PCI: 00:13.0 subsystem <- 1022/1510

PCI: 00:13.0 cmd <- 02

PCI: 00:13.2 subsystem <- 1022/1510

PCI: 00:13.2 cmd <- 02

PCI: 00:14.0 subsystem <- 1022/1510

PCI: 00:14.0 cmd <- 403

PCI: 00:14.2 subsystem <- 1022/1510

PCI: 00:14.2 cmd <- 02

PCI: 00:14.3 subsystem <- 1022/1510

PCI: 00:14.3 cmd <- 0f

PCI: 00:14.4 bridge ctrl <- 0003

PCI: 00:14.4 subsystem <- 1022/1510

PCI: 00:14.4 cmd <- 21

PCI: 00:14.5 subsystem <- 1022/1510

PCI: 00:14.5 cmd <- 02

PCI: 00:18.0 subsystem <- 1022/1510

PCI: 00:18.0 cmd <- 00

PCI: 00:18.1 subsystem <- 1022/1510

PCI: 00:18.1 cmd <- 00

PCI: 00:18.2 subsystem <- 1022/1510

PCI: 00:18.2 cmd <- 00

PCI: 00:18.3 subsystem <- 1022/1510

PCI: 00:18.3 cmd <- 00

PCI: 00:18.4 subsystem <- 1022/1510

PCI: 00:18.4 cmd <- 00

PCI: 00:18.5 subsystem <- 1022/1510

PCI: 00:18.5 cmd <- 00

PCI: 00:18.6 subsystem <- 1022/1510

PCI: 00:18.6 cmd <- 00

PCI: 00:18.7 subsystem <- 1022/1510

PCI: 00:18.7 cmd <- 00

PCI: 01:00.0 cmd <- 03

done.

Initializing devices...

Root Device init

APIC_CLUSTER: 0 init

start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b

Initializing CPU #0

CPU: vendor AMD device 500f20

CPU: family 14, model 02, stepping 00

Model 14 Init.

 

MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled

 

POST: 0x93

POST: 0x60

Enabling cache

Setting up local apic... apic_id: 0x00 done.

POST: 0x9b

model_14_init done.

CPU #0 initialized

Asserting INIT.

Waiting for send to finish...

+Deasserting INIT.

Waiting for send to finish...

+#startup loops: 2.

Sending STARTUP #1 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+Sending STARTUP #2 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+After Startup.

Initializing CPU #1

Waiting for 1 CPUS to stop

CPU: vendor AMD device 500f20

CPU: family 14, model 02, stepping 00

Model 14 Init.

 

MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled

 

POST: 0x93

POST: 0x60

Enabling cache

Setting up local apic... apic_id: 0x01 done.

POST: 0x9b

model_14_init done.

CPU #1 initialized

All AP CPUs stopped (5043 loops)

PCI: 00:00.0 init

Northbridge init

PCI: 00:01.0 init

CBFS: Looking for 'pci1002,9804.rom'

CBFS: found.

In CBFS, ROM address for PCI: 00:01.0 = ffe00778

PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0

PCI ROM image, vendor ID 1002, device ID 9804,

PCI ROM image, Class Code 030000, Code Type 00

Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes

Real mode stub @00000600: 867 bytes

Calling Option ROM...

... Option ROM returned.

Getting information about VESA mode 4117

framebuffer: e0000000

Setting VESA mode 4117

PCI: 00:11.0 init

AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0

Number of Ports: 0x6, Port implemented(bit map): 0x3f

AHCI/RAID controller initialized

PCI: 00:14.0 init

CBFS: Looking for 'pci1002,4385.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1002,4385.rom'.

PCI: 00:14.4 init

PCI: 00:18.0 init

CBFS: Looking for 'pci1022,1700.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1700.rom'.

PCI: 00:18.1 init

CBFS: Looking for 'pci1022,1701.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1701.rom'.

PCI: 00:18.2 init

CBFS: Looking for 'pci1022,1702.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1702.rom'.

PCI: 00:18.3 init

CBFS: Looking for 'pci1022,1703.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1703.rom'.

PCI: 00:18.4 init

CBFS: Looking for 'pci1022,1704.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1704.rom'.

PCI: 00:18.5 init

CBFS: Looking for 'pci1022,1718.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1718.rom'.

PCI: 00:18.6 init

CBFS: Looking for 'pci1022,1716.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1716.rom'.

PCI: 00:18.7 init

CBFS: Looking for 'pci1022,1719.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1719.rom'.

PCI: 01:00.0 init

CBFS: Looking for 'pci10ec,8168.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci10ec,8168.rom'.

Option ROM address for PCI: 01:00.0 = f0100000

PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000

Incorrect expansion ROM header signature 0000

PNP: 004e.5 init

Keyboard init...

No PS/2 keyboard detected.

PNP: 004e.10 init

Devices initialized

Show all devs...After init.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:01.0: enabled 1

PCI: 00:01.1: enabled 1

PCI: 00:04.0: enabled 1

PCI: 00:05.0: enabled 0

PCI: 00:06.0: enabled 0

PCI: 00:07.0: enabled 0

PCI: 00:08.0: enabled 0

PCI: 00:11.0: enabled 1

PCI: 00:12.0: enabled 1

PCI: 00:12.1: enabled 0

PCI: 00:12.2: enabled 1

PCI: 00:13.0: enabled 1

PCI: 00:13.1: enabled 0

PCI: 00:13.2: enabled 1

PCI: 00:14.0: enabled 1

I2C: 00:50: enabled 1

I2C: 00:51: enabled 1

PCI: 00:14.1: enabled 0

PCI: 00:14.2: enabled 1

PCI: 00:14.3: enabled 1

PNP: 004e.0: enabled 0

PNP: 004e.3: enabled 0

PNP: 004e.4: enabled 0

PNP: 004e.5: enabled 1

PNP: 004e.6: enabled 0

PNP: 004e.a: enabled 0

PNP: 004e.10: enabled 1

PNP: 004e.11: enabled 0

PCI: 00:14.4: enabled 1

PCI: 00:14.5: enabled 1

PCI: 00:15.0: enabled 0

PCI: 00:15.1: enabled 0

PCI: 00:15.2: enabled 0

PCI: 00:15.3: enabled 0

PCI: 00:16.0: enabled 0

PCI: 00:16.2: enabled 0

PCI: 00:18.0: enabled 1

PCI: 00:18.1: enabled 1

PCI: 00:18.2: enabled 1

PCI: 00:18.3: enabled 1

PCI: 00:18.4: enabled 1

PCI: 00:18.5: enabled 1

PCI: 00:18.6: enabled 1

PCI: 00:18.7: enabled 1

APIC: 01: enabled 1

PCI: 01:00.0: enabled 1

POST: 0x89

Re-Initializing CBMEM area to 0x6616f000

Initializing CBMEM area to 0x6616f000 (15273984 bytes)

dword=6616f000

nvram_pos=f8, dword>>(8*i)=0

nvram_pos=f9, dword>>(8*i)=f0

nvram_pos=fa, dword>>(8*i)=16

nvram_pos=fb, dword>>(8*i)=66

Adding CBMEM entry as no. 1

Moving GDT to 6616f200...ok

POST: 0x8a

High Tables Base is 6616f000.

POST: 0x9a

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

In agesawrapper_amdinitlate, AGESA generated ACPI tables:

   DmiTable:00000000

   AcpiPstate: 00022165

   AcpiSrat:00000000

   AcpiSlit:00000000

   Mce:00022621

   Cmc:000226c7

   Alib:00022765

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

mid=0, did=0

mid=0, did=0

mid=0, did=0

mid=c2, did=14

mid=0, did=0

mid=0, did=0

mid=0, did=0

mid=c2, did=14

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.

Adding CBMEM entry as no. 2

Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.

PIRQ table: 48 bytes.

POST: 0x9b

Wrote the mp table end at: 000f0410 - 000f0514

Adding CBMEM entry as no. 3

Wrote the mp table end at: 66170410 - 66170514

MP table: 276 bytes.

POST: 0x9c

Adding CBMEM entry as no. 4

ACPI: Writing ACPI tables at 66171400...

ACPI:  * DSDT at 661714c8

ACPI:  * DSDT @ 661714c8 Length 28cd

ACPI:  * FACS at 66173d98

ACPI:  * FADT at 66173dd8

ACPI_BLK_BASE: 0x0800

ACPI: added table 1/32, length now 40

ACPI:  * HPET at 66173ed0

ACPI: added table 2/32, length now 44

ACPI:  * MADT at 66173f08

ACPI: added table 3/32, length now 48

ACPI: added table 4/32, length now 52

ACPI:  * SRAT at 66174100

  AGESA SRAT table NULL. Skipping.

ACPI:  * SLIT at 66174100

  AGESA SLIT table NULL. Skipping.

ACPI:  * AGESA ALIB SSDT at 66174100

ACPI: added table 5/32, length now 56

ACPI:  * AGESA SSDT Pstate at 66175790

ACPI: added table 6/32, length now 60

ACPI:  * coreboot TOM SSDT2 at 66175aa0

ACPI: added table 7/32, length now 64

ACPI: done.

ACPI tables: 18149 bytes.

Adding CBMEM entry as no. 5

smbios_write_tables: 6617c800

Root Device (AMD Persimmon Mainboard)

APIC_CLUSTER: 0 (AMD Family 14h Root Complex)

APIC: 00 (AMD CPU Family 14h)

PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)

PCI: 00:00.0 (AMD Family 14h Northbridge)

PCI: 00:01.0 (AMD Family 14h Northbridge)

PCI: 00:01.1 (AMD Family 14h Northbridge)

PCI: 00:04.0 (AMD Family 14h Northbridge)

PCI: 00:05.0 (AMD Family 14h Northbridge)

PCI: 00:06.0 (AMD Family 14h Northbridge)

PCI: 00:07.0 (AMD Family 14h Northbridge)

PCI: 00:08.0 (AMD Family 14h Northbridge)

PCI: 00:11.0 (ATI SB800)

PCI: 00:12.0 (ATI SB800)

PCI: 00:12.1 (ATI SB800)

PCI: 00:12.2 (ATI SB800)

PCI: 00:13.0 (ATI SB800)

PCI: 00:13.1 (ATI SB800)

PCI: 00:13.2 (ATI SB800)

PCI: 00:14.0 (ATI SB800)

I2C: 00:50 ()

I2C: 00:51 ()

PCI: 00:14.1 (ATI SB800)

PCI: 00:14.2 (ATI SB800)

PCI: 00:14.3 (ATI SB800)

PNP: 004e.0 (Fintek F81865F Super I/O)

PNP: 004e.3 (Fintek F81865F Super I/O)

PNP: 004e.4 (Fintek F81865F Super I/O)

PNP: 004e.5 (Fintek F81865F Super I/O)

PNP: 004e.6 (Fintek F81865F Super I/O)

PNP: 004e.a (Fintek F81865F Super I/O)

PNP: 004e.10 (Fintek F81865F Super I/O)

PNP: 004e.11 (Fintek F81865F Super I/O)

PCI: 00:14.4 (ATI SB800)

PCI: 00:14.5 (ATI SB800)

PCI: 00:15.0 (ATI SB800)

PCI: 00:15.1 (ATI SB800)

PCI: 00:15.2 (ATI SB800)

PCI: 00:15.3 (ATI SB800)

PCI: 00:16.0 (ATI SB800)

PCI: 00:16.2 (ATI SB800)

PCI: 00:18.0 (AMD Family 14h Northbridge)

PCI: 00:18.1 (AMD Family 14h Northbridge)

PCI: 00:18.2 (AMD Family 14h Northbridge)

PCI: 00:18.3 (AMD Family 14h Northbridge)

PCI: 00:18.4 (AMD Family 14h Northbridge)

PCI: 00:18.5 (AMD Family 14h Northbridge)

PCI: 00:18.6 (AMD Family 14h Northbridge)

PCI: 00:18.7 (AMD Family 14h Northbridge)

APIC: 01 ()

PCI: 01:00.0 ()

SMBIOS tables: 287 bytes.

POST: 0x9d

Adding CBMEM entry as no. 6

Writing high table forward entry at 0x00000500

Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6

New low_table_end: 0x00000528

Now going to write high coreboot table at 0x6617d000

rom_table_end = 0x6617d000

Adjust low_table_end from 0x00000528 to 0x00001000 

Adjust rom_table_end from 0x6617d000 to 0x66180000 

Adding high table area

uma_memory_start=0x67000000, uma_memory_size=0x18000000 

coreboot memory table:

 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES

 1. 0000000000001000-000000000009ffff: RAM

 2. 00000000000c0000-000000006616efff: RAM

 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES

 4. 0000000067000000-000000007effffff: RESERVED

 5. 00000000f8000000-00000000f8ffffff: RESERVED

Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f

coreboot table: 532 bytes.

POST: 0x9e

Adding CBMEM entry as no. 7

Adding CBMEM entry as no. 8

POST: 0x9d

Multiboot Information structure has been written.

 0. FREE SPACE 66ff6000 0000a000

 1. GDT        6616f200 00000200

 2. IRQ TABLE  6616f400 00001000

 3. SMP TABLE  66170400 00001000

 4. ACPI       66171400 0000b400

 5. SMBIOS     6617c800 00000800

 6. COREBOOT   6617d000 00008000

 7. ACPI RESUME66185000 00e00000

 8. ACPISCRATCH66f85000 00071000

CBFS: Looking for 'fallback/payload'

CBFS: found.

Got a payload

Loading segment from rom address 0xffee35f8

  code (compression=0)

  New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630 filesize
0x18b60

  (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
filesize 0x18b60

Loading segment from rom address 0xffee3614

  Entry Point 0x00000000

Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60

lb: [0x0000000000200000, 0x0000000000360000)

Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60

it's not compressed!

[ 0x000e74a0, 00100000, 0x00100000) <- ffee3630

dest 000e74a0, end 00100000, bouncebuffer 65eaf000

Loaded segments

Jumping to boot code at fc855

POST: 0xf8

entry    = 0x000fc855

lb_start = 0x00200000

lb_size  = 0x00160000

adjust   = 0x65e0f000

buffer   = 0x65eaf000

     elf_boot_notes = 0x00272e18

adjusted_boot_notes = 0x66081e18

Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)

Found mainboard AMD Persimmon

Found CBFS header at 0xfffffbf0

Ram Size=0x6616f000 (0x0000000000000000 high)

Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)

CPU Mhz=1001

Found 22 PCI devices (max PCI bus is 02)

Found 2 cpu(s) max supported 2 cpu(s)

Copying PIR from 0x6616f400 to 0x000fdbc0

Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0

Copying ACPI RSDP from 0x66171400 to 0x000fda80

Copying SMBIOS entry point from 0x6617c800 to 0x000fda60

Scan for VGA option rom

Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b

EHCI init on dev 00:12.2 (regs=0xf0247420)

EHCI init on dev 00:13.2 (regs=0xf0247520)

OHCI init on dev 00:14.5 (regs=0xf0246000)

Found 0 lpt ports

Found 3 serial ports

ebda moved from 9fc00 to 9f400

AHCI controller at 11.0, iobase f0247000, irq 0

OHCI init on dev 00:12.0 (regs=0xf0244000)

Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0

ebda moved from 9f400 to 9f000

ebda moved from 9f000 to 9ec00

AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
MiBytes)"

Got ps2 nak (status=51)

USB keyboard initialized

All threads complete.

Scan for option roms

Press F12 for boot menu.

 

drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=125045424

Returned 57344 bytes of ZoneHigh

e820 map has 6 items:

  0: 0000000000000000 - 000000000009ec00 = 1 RAM

  1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED

  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED

  3: 0000000000100000 - 000000006616d000 = 1 RAM

  4: 000000006616d000 - 000000007f000000 = 2 RESERVED

  5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED

enter handle_19:

  NULL

Booting from Hard Disk...

Booting from 0000:7c00

 

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From gerrit at coreboot.org  Thu Jun  7 23:21:11 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 7 Jun 2012 23:21:11 +0200
Subject: [coreboot] Patch merged into coreboot/master: 7772794 libpayload:
	Remove orphaned delay from OHCI USB driver
References: <Ie72b2d49e6734345708f04f3f7b86bacc7926108+0@gerrit.coreboot.org>
Message-ID: <E1Sck8l-000634-Sw@ra.coresystems.de>

the following patch was just integrated into master:
commit 77727940b54e5fe4daafa21e638951f2fb2162f2
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:41:49 2012 +0200

    libpayload: Remove orphaned delay from OHCI USB driver
    
    This removes a synthetic delay of 5ms from every OHCI USB command.  A delay
    here seems to be of no use and first tests have shown no glitches.
    
    Change-Id: Ie72b2d49e6734345708f04f3f7b86bacc7926108
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Build-Tested: build bot (Jenkins) at Thu May 31 17:36:14 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Jun  7 23:17:40 2012, giving +2
See http://review.coreboot.org/1075 for details.

-gerrit



From steve.goodrich at se-eng.com  Thu Jun  7 23:52:02 2012
From: steve.goodrich at se-eng.com (Steve Goodrich)
Date: Thu, 7 Jun 2012 15:52:02 -0600
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JVR8HQVKn4kTsvirK2d8oERUDXoff-MAmJctx-Q+tBOWw@mail.gmail.com>
References: <CAHgS8JVR8HQVKn4kTsvirK2d8oERUDXoff-MAmJctx-Q+tBOWw@mail.gmail.com>
Message-ID: <017801cd44f7$c71d4ed0$5557ec70$@goodrich@se-eng.com>

Andy,

 

Check the devicetree.cb file in your ./src/mainboard/amd/persimmon folder.
Mine shows:

 

 

 

From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
On Behalf Of Andy Sharp
Sent: Thursday, June 07, 2012 2:31 PM
To: coreboot at coreboot.org
Subject: [coreboot] PCIe devices not enabled on amd/persimmon

 

Howdy,

 

I've got an AMD/persimmon board, with the agesa family 14 northbridge on the
CPU, and the SB800 southbridge.  Both have 4 PCIe ports on them, but
coreboot isn't enabling or enumerating any of the PCIe devices on the SB800.
Does anyone have any ideas for me?  The two devices on that southbridge are
an NEC USB3 and a Mini-PCIe slot.

 

 

Pasting the console output below for those interested:

 

 

coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
starting...

POST: 0x34

BSP Family_Model: 00500f20 

cpu_init_detectedx = 00000000 

POST: 0x35

agesawrapper_amdinitmmio passed.

POST: 0x37

agesawrapper_amdinitreset passed.

POST: 0x39

agesawrapper_amdinitearly POST: 0x34

BSP Family_Model: 00500f20 

cpu_init_detectedx = 00000001 

POST: 0x35

agesawrapper_amdinitmmio passed.

POST: 0x37

agesawrapper_amdinitreset passed.

POST: 0x39

agesawrapper_amdinitearly passed.

SLP_TYP type was 0

POST: 0x40

agesawrapper_amdinitpost 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

 

EventLog:     EventClass = 2, EventInfo = 8040100.

          Param1 = a00a, Param2 = 0.

          Param3 = 0, Param4 = 0.

SLP_TYP type was 0

error level: 4 

POST: 0x42

agesawrapper_amdinitenv SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

passed.

POST: 0x43

POST: 0x44

POST: 0x50

Loading image.

CBFS: Looking for 'fallback/coreboot_ram'

CBFS: found.

CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry
@ 0x200000

Jumping to image.

POST: 0x80

POST: 0x39

coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
booting...

POST: 0x40

Enumerating buses...

Show all devs...Before device enumeration.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:01.0: enabled 1

PCI: 00:01.1: enabled 1

PCI: 00:04.0: enabled 1

PCI: 00:05.0: enabled 0

PCI: 00:06.0: enabled 0

PCI: 00:07.0: enabled 0

PCI: 00:08.0: enabled 0

PCI: 00:11.0: enabled 1

PCI: 00:12.0: enabled 1

PCI: 00:12.1: enabled 1

PCI: 00:12.2: enabled 1

PCI: 00:13.0: enabled 1

PCI: 00:13.1: enabled 1

PCI: 00:13.2: enabled 1

PCI: 00:14.0: enabled 1

I2C: 00:50: enabled 1

I2C: 00:51: enabled 1

PCI: 00:14.1: enabled 1

PCI: 00:14.2: enabled 1

PCI: 00:14.3: enabled 1

PNP: 004e.0: enabled 0

PNP: 004e.3: enabled 0

PNP: 004e.4: enabled 0

PNP: 004e.5: enabled 1

PNP: 004e.6: enabled 0

PNP: 004e.a: enabled 0

PNP: 004e.10: enabled 1

PNP: 004e.11: enabled 0

PCI: 00:14.4: enabled 1

PCI: 00:14.5: enabled 1

PCI: 00:15.0: enabled 0

PCI: 00:15.1: enabled 0

PCI: 00:15.2: enabled 0

PCI: 00:15.3: enabled 0

PCI: 00:16.0: enabled 0

PCI: 00:16.2: enabled 0

PCI: 00:18.0: enabled 1

PCI: 00:18.1: enabled 1

PCI: 00:18.2: enabled 1

PCI: 00:18.3: enabled 1

PCI: 00:18.4: enabled 1

PCI: 00:18.5: enabled 1

PCI: 00:18.6: enabled 1

PCI: 00:18.7: enabled 1

Compare with tree...

Root Device: enabled 1

 APIC_CLUSTER: 0: enabled 1

  APIC: 00: enabled 1

 PCI_DOMAIN: 0000: enabled 1

  PCI: 00:00.0: enabled 1

  PCI: 00:01.0: enabled 1

  PCI: 00:01.1: enabled 1

  PCI: 00:04.0: enabled 1

  PCI: 00:05.0: enabled 0

  PCI: 00:06.0: enabled 0

  PCI: 00:07.0: enabled 0

  PCI: 00:08.0: enabled 0

  PCI: 00:11.0: enabled 1

  PCI: 00:12.0: enabled 1

  PCI: 00:12.1: enabled 1

  PCI: 00:12.2: enabled 1

  PCI: 00:13.0: enabled 1

  PCI: 00:13.1: enabled 1

  PCI: 00:13.2: enabled 1

  PCI: 00:14.0: enabled 1

   I2C: 00:50: enabled 1

   I2C: 00:51: enabled 1

  PCI: 00:14.1: enabled 1

  PCI: 00:14.2: enabled 1

  PCI: 00:14.3: enabled 1

   PNP: 004e.0: enabled 0

   PNP: 004e.3: enabled 0

   PNP: 004e.4: enabled 0

   PNP: 004e.5: enabled 1

   PNP: 004e.6: enabled 0

   PNP: 004e.a: enabled 0

   PNP: 004e.10: enabled 1

   PNP: 004e.11: enabled 0

  PCI: 00:14.4: enabled 1

  PCI: 00:14.5: enabled 1

  PCI: 00:15.0: enabled 0

  PCI: 00:15.1: enabled 0

  PCI: 00:15.2: enabled 0

  PCI: 00:15.3: enabled 0

  PCI: 00:16.0: enabled 0

  PCI: 00:16.2: enabled 0

  PCI: 00:18.0: enabled 1

  PCI: 00:18.1: enabled 1

  PCI: 00:18.2: enabled 1

  PCI: 00:18.3: enabled 1

  PCI: 00:18.4: enabled 1

  PCI: 00:18.5: enabled 1

  PCI: 00:18.6: enabled 1

  PCI: 00:18.7: enabled 1

Mainboard Persimmon Enable.

SLP_TYP type was 0

persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000

persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000

persimmon_enable: uma size 0x18000000, memory start 0x67000000

scan_static_bus for Root Device

APIC_CLUSTER: 0 enabled

PCI_DOMAIN: 0000 enabled

APIC_CLUSTER: 0 scanning...

  AP siblings=1

CPU: APIC: 00 enabled

CPU: APIC: 01 enabled

PCI_DOMAIN: 0000 scanning...

PCI: pci_scan_bus for bus 00

POST: 0x24

PCI: 00:00.0 [1022/1510] ops

PCI: 00:00.0 [1022/1510] enabled

PCI: 00:01.0 [1002/9804] enabled

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

Capability: type 0x05 @ 0xa0

Capability: type 0x0d @ 0xb0

Capability: type 0x08 @ 0xb8

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

PCI: 00:04.0 subordinate bus PCI Express

PCI: 00:04.0 [1022/1512] enabled

sb800_enable() SLP_TYP type was 0

PCI: 00:11.0 [1002/4393] ops

PCI: 00:11.0 [1002/4393] enabled

sb800_enable() PCI: 00:12.0 [1002/4397] ops

PCI: 00:12.0 [1002/4397] enabled

sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.

sb800_enable() PCI: 00:12.2 [1002/4396] ops

PCI: 00:12.2 [1002/4396] enabled

sb800_enable() PCI: 00:13.0 [1002/4397] ops

PCI: 00:13.0 [1002/4397] enabled

sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.

sb800_enable() PCI: 00:13.2 [1002/4396] ops

PCI: 00:13.2 [1002/4396] enabled

sb800_enable() sm_init().

IOAPIC: Clearing IOAPIC at 0xfec00000

IOAPIC: 23 interrupts

IOAPIC: reg 0x00000000 value 0x00000000 0x00010000

IOAPIC: reg 0x00000001 value 0x00000000 0x00010000

IOAPIC: reg 0x00000002 value 0x00000000 0x00010000

IOAPIC: reg 0x00000003 value 0x00000000 0x00010000

IOAPIC: reg 0x00000004 value 0x00000000 0x00010000

IOAPIC: reg 0x00000005 value 0x00000000 0x00010000

IOAPIC: reg 0x00000006 value 0x00000000 0x00010000

IOAPIC: reg 0x00000007 value 0x00000000 0x00010000

IOAPIC: reg 0x00000008 value 0x00000000 0x00010000

IOAPIC: reg 0x00000009 value 0x00000000 0x00010000

IOAPIC: reg 0x0000000a value 0x00000000 0x00010000

IOAPIC: reg 0x0000000b value 0x00000000 0x00010000

IOAPIC: reg 0x0000000c value 0x00000000 0x00010000

IOAPIC: reg 0x0000000d value 0x00000000 0x00010000

IOAPIC: reg 0x0000000e value 0x00000000 0x00010000

IOAPIC: reg 0x0000000f value 0x00000000 0x00010000

IOAPIC: reg 0x00000010 value 0x00000000 0x00010000

IOAPIC: reg 0x00000011 value 0x00000000 0x00010000

IOAPIC: reg 0x00000012 value 0x00000000 0x00010000

IOAPIC: reg 0x00000013 value 0x00000000 0x00010000

IOAPIC: reg 0x00000014 value 0x00000000 0x00010000

IOAPIC: reg 0x00000015 value 0x00000000 0x00010000

IOAPIC: reg 0x00000016 value 0x00000000 0x00010000

IOAPIC: Initializing IOAPIC at 0xfec00000

IOAPIC: Bootstrap Processor Local APIC = 0x00

IOAPIC: ID = 0x02

IOAPIC: 23 interrupts

IOAPIC: Enabling interrupts on FSB

IOAPIC: reg 0x00000000 value 0x00000000 0x00000700

IOAPIC: reg 0x00000001 value 0x00000000 0x00010000

IOAPIC: reg 0x00000002 value 0x00000000 0x00010000

IOAPIC: reg 0x00000003 value 0x00000000 0x00010000

IOAPIC: reg 0x00000004 value 0x00000000 0x00010000

IOAPIC: reg 0x00000005 value 0x00000000 0x00010000

IOAPIC: reg 0x00000006 value 0x00000000 0x00010000

IOAPIC: reg 0x00000007 value 0x00000000 0x00010000

IOAPIC: reg 0x00000008 value 0x00000000 0x00010000

IOAPIC: reg 0x00000009 value 0x00000000 0x00010000

IOAPIC: reg 0x0000000a value 0x00000000 0x00010000

IOAPIC: reg 0x0000000b value 0x00000000 0x00010000

IOAPIC: reg 0x0000000c value 0x00000000 0x00010000

IOAPIC: reg 0x0000000d value 0x00000000 0x00010000

IOAPIC: reg 0x0000000e value 0x00000000 0x00010000

IOAPIC: reg 0x0000000f value 0x00000000 0x00010000

IOAPIC: reg 0x00000010 value 0x00000000 0x00010000

IOAPIC: reg 0x00000011 value 0x00000000 0x00010000

IOAPIC: reg 0x00000012 value 0x00000000 0x00010000

IOAPIC: reg 0x00000013 value 0x00000000 0x00010000

IOAPIC: reg 0x00000014 value 0x00000000 0x00010000

IOAPIC: reg 0x00000015 value 0x00000000 0x00010000

IOAPIC: reg 0x00000016 value 0x00000000 0x00010000

PCI: 00:14.0 [1002/4385] enabled

sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.

sb800_enable() hda enabled

PCI: 00:14.2 [1002/4383] ops

PCI: 00:14.2 [1002/4383] enabled

sb800_enable() PCI: 00:14.3 [1002/439d] bus ops

PCI: 00:14.3 [1002/439d] enabled

sb800_enable() PCI: 00:14.4 [1002/4384] bus ops

PCI: 00:14.4 [1002/4384] enabled

sb800_enable() PCI: 00:14.5 [1002/4399] ops

PCI: 00:14.5 [1002/4399] enabled

sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable()
sb800_enable() PCI: 00:18.0 [1022/1700] enabled

PCI: 00:18.1 [1022/1701] enabled

PCI: 00:18.2 [1022/1702] enabled

PCI: 00:18.3 [1022/1703] enabled

PCI: 00:18.4 [1022/1704] enabled

PCI: 00:18.5 [1022/1718] enabled

PCI: 00:18.6 [1022/1716] enabled

PCI: 00:18.7 [1022/1719] enabled

POST: 0x25

PCI: Left over static devices:

PCI: 00:01.1

PCI: Check your devicetree.cb.

do_pci_scan_bridge for PCI: 00:04.0

PCI: pci_scan_bus for bus 01

POST: 0x24

PCI: 01:00.0 [10ec/8168] enabled

POST: 0x25

PCI: pci_scan_bus returning with max=001

POST: 0x55

Capability: type 0x01 @ 0x40

Capability: type 0x05 @ 0x50

Capability: type 0x10 @ 0x70

Capability: type 0x01 @ 0x50

Capability: type 0x10 @ 0x58

do_pci_scan_bridge returns max 1

scan_static_bus for PCI: 00:14.3

PNP: 004e.0 disabled

PNP: 004e.3 disabled

PNP: 004e.4 disabled

PNP: 004e.5 enabled

PNP: 004e.6 disabled

PNP: 004e.a disabled

PNP: 004e.10 enabled

PNP: 004e.11 disabled

scan_static_bus for PCI: 00:14.3 done

do_pci_scan_bridge for PCI: 00:14.4

PCI: pci_scan_bus for bus 02

POST: 0x24

POST: 0x25

PCI: pci_scan_bus returning with max=002

POST: 0x55

do_pci_scan_bridge returns max 2

PCI: pci_scan_bus returning with max=002

POST: 0x55

scan_static_bus for Root Device done

done

POST: 0x66

Setting up VGA for PCI: 00:01.0

Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000

Setting PCI_BRIDGE_CTL_VGA for bridge Root Device

Allocating resources...

Reading resources...

Root Device read_resources bus 0 link: 0

 

Fam14h - cpu_bus_read_resources.

APIC_CLUSTER: 0 read_resources bus 0 link: 0

APIC: 00 missing read_resources

APIC: 01 missing read_resources

APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

 

Fam14h - domain_read_resources.

PCI_DOMAIN: 0000 read_resources bus 0 link: 0

 

Fam14h - read_resources.

PCI: 00:04.0 read_resources bus 1 link: 0

PCI: 00:04.0 read_resources bus 1 link: 0 done

PCI: 00:14.0 read_resources bus 0 link: 0

I2C: 00:50 missing read_resources

I2C: 00:51 missing read_resources

PCI: 00:14.0 read_resources bus 0 link: 0 done

SB800 - Lpc.c - lpc_read_resources - Start.

SB800 - Lpc.c - lpc_read_resources - End.

PCI: 00:14.3 read_resources bus 0 link: 0

PCI: 00:14.3 read_resources bus 0 link: 0 done

PCI: 00:14.4 read_resources bus 2 link: 0

PCI: 00:14.4 read_resources bus 2 link: 0 done

PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done

Root Device read_resources bus 0 link: 0 done

Done reading resources.

Show resources in subtree (Root Device)...After reading.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0
flags f0000200 index c0010058

   APIC: 00

   APIC: 01

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags
40040100 index 10000000

  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff
flags 40040200 index 10000100

   PCI: 00:00.0

   PCI: 00:01.0

   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit
ffffffff flags 1200 index 10

   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100
index 14

   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff
flags 200 index 18

   PCI: 00:04.0 child on link 0 PCI: 01:00.0

   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags
80102 index 1c

   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit
ffffffffffffffff flags 81202 index 24

   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20

    PCI: 01:00.0

    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags
100 index 10

    PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit
ffffffffffffffff flags 1201 index 18

    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 1201 index 20

    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff
flags 2200 index 30

   PCI: 00:05.0

   PCI: 00:06.0

   PCI: 00:07.0

   PCI: 00:08.0

   PCI: 00:11.0

   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 10

   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 14

   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100
index 18

   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100
index 1c

   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100
index 20

   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff
flags 200 index 24

   PCI: 00:12.0

   PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:12.1

   PCI: 00:12.2

   PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
200 index 10

   PCI: 00:13.0

   PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:13.1

   PCI: 00:13.2

   PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags
200 index 10

   PCI: 00:14.0 child on link 0 I2C: 00:50

    I2C: 00:50

    I2C: 00:51

   PCI: 00:14.1

   PCI: 00:14.2

   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit
ffffffffffffffff flags 201 index 10

   PCI: 00:14.3 child on link 0 PNP: 004e.0

   PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags
200 index a0

   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000

   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100

   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3

    PNP: 004e.0

    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74

    PNP: 004e.3

    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74

    PNP: 004e.4

    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60

    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.5

    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
c0000100 index 60

    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
c0000100 index 62

    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72

    PNP: 004e.6

    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.a

    PNP: 004e.10

    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

    PNP: 004e.11

    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

   PCI: 00:14.4

   PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags
80102 index 1c

   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
81202 index 24

   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags
80202 index 20

   PCI: 00:14.5

   PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff
flags 200 index 10

   PCI: 00:15.0

   PCI: 00:15.1

   PCI: 00:15.2

   PCI: 00:15.3

   PCI: 00:16.0

   PCI: 00:16.2

   PCI: 00:18.0

   PCI: 00:18.1

   PCI: 00:18.2

   PCI: 00:18.3

   PCI: 00:18.4

   PCI: 00:18.5

   PCI: 00:18.6

   PCI: 00:18.7

PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0
limit: ffff

PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffffffff

PCI: 01:00.0 10 *  [0x0 - 0xff] io

PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12
limit: ffff done

PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff

PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit:
ffff done

PCI: 00:04.0 1c *  [0x0 - 0xfff] io

PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io

PCI: 00:11.0 20 *  [0x1400 - 0x140f] io

PCI: 00:11.0 10 *  [0x1410 - 0x1417] io

PCI: 00:11.0 18 *  [0x1418 - 0x141f] io

PCI: 00:11.0 14 *  [0x1420 - 0x1423] io

PCI: 00:11.0 1c *  [0x1424 - 0x1427] io

PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran:
0 limit: ffff done

PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0
limit: ffffffff

PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffffffffffff

PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem

PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem

PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20
gran: 20 limit: ffffffffffffffff done

PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem

PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran:
20 limit: ffffffff done

PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done

PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff

PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20
limit: ffffffff done

PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem

PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem

PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem

PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem

PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem

PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem

PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem

PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem

PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem

PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem

PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem

PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem

PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601 align:
28 gran: 0 limit: ffffffff done

avoid_fixed_resources: PCI_DOMAIN: 0000

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff

avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff

constrain_resources: PCI_DOMAIN: 0000

constrain_resources: PCI: 00:00.0

constrain_resources: PCI: 00:01.0

constrain_resources: PCI: 00:04.0

constrain_resources: PCI: 01:00.0

constrain_resources: PCI: 00:11.0

constrain_resources: PCI: 00:12.0

constrain_resources: PCI: 00:12.2

constrain_resources: PCI: 00:13.0

constrain_resources: PCI: 00:13.2

constrain_resources: PCI: 00:14.0

constrain_resources: I2C: 00:50

constrain_resources: I2C: 00:51

constrain_resources: PCI: 00:14.2

constrain_resources: PCI: 00:14.3

constrain_resources: PNP: 004e.5

skipping PNP: 004e.5 at 62 fixed resource, size=0!

constrain_resources: PNP: 004e.10

constrain_resources: PCI: 00:14.4

constrain_resources: PCI: 00:14.5

constrain_resources: PCI: 00:18.0

constrain_resources: PCI: 00:18.1

constrain_resources: PCI: 00:18.2

constrain_resources: PCI: 00:18.3

constrain_resources: PCI: 00:18.4

constrain_resources: PCI: 00:18.5

constrain_resources: PCI: 00:18.6

constrain_resources: PCI: 00:18.7

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff

          lim->base 00001000 lim->limit 0000ffff

avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff

          lim->base 00000000 lim->limit febfffff

Setting resources...

PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0
limit:ffff

Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io

Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io

Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io

Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io

Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io

Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io

Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io

PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12
gran: 0 done

PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12
limit:ffff

Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io

PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12
gran: 12 done

PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12
limit:ffff

PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran:
12 done

PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601
align:28 gran:0 limit:febfffff

Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem

Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem

Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem

Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem

Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem

Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem

Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem

Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem

Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem

Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem

Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem

Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem

PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size: 10247601
align: 28 gran: 0 done

PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20
gran:20 limit:febfffff

Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem

Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem

PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000
align: 20 gran: 20 done

PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20
gran:20 limit:febfffff

Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem

PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000 align:
20 gran: 20 done

PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20
gran:20 limit:febfffff

PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align:
20 gran: 20 done

PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20
limit:febfffff

PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20
gran: 20 done

Root Device assign_resources, bus 0 link: 0

 

Fam14h - cpu_bus_set_resources.

APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000
gran 0x00 mem <mmconfig>

APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

 

Fam14h - domain_set_resources.

  amsr - incoming dev = 00272248

adsr: (before) basek = 0, limitk = 7effffff.

adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.

adsr - 0xa0000 to 0xbffff resource.

adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff

0: mmio_basek=00380000, basek=00000300, limitk=001fbfff

  adsr - uma_memory_base = 67000000.

  adsr - mmio_basek = 380000.

  adsr - high_tables_size = e91000.

adsr - adding uma resource.

 

Fam14h - Adding UMA memory.

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c
prefmem

PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08
io

PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12
mem

PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c
bus 01 io

PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14
bus 01 prefmem

PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14
bus 01 mem

PCI: 00:04.0 assign_resources, bus 1 link: 0

PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08
io

PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c
prefmem64

PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e
prefmem64

PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran 0x11
romem

PCI: 00:04.0 assign_resources, bus 1 link: 0

PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03
io

PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02
io

PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03
io

PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02
io

PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04
io

PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran 0x0a
mem

PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran 0x0c
mem

PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran 0x08
mem

PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran 0x0c
mem

PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran 0x08
mem

PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e
mem64

SB800 - Lpc.c - lpc_set_resources - Start.

PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran 0x00
mem

PCI: 00:14.3 assign_resources, bus 0 link: 0

PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io

PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io

PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00
irq

ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned

PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03
io

PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00
irq

PCI: 00:14.3 assign_resources, bus 0 link: 0

SB800 - Lpc.c - lpc_set_resources - End.

PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c
bus 02 io

PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 prefmem

PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14
bus 02 mem

PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran 0x0c
mem

PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0

  adsr - leaving this lovely routine.

Root Device assign_resources, bus 0 link: 0

Done setting resources.

Show resources in subtree (Root Device)...After assigning values.

 Root Device child on link 0 APIC_CLUSTER: 0

  APIC_CLUSTER: 0 child on link 0 APIC: 00

  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0
flags f0000200 index c0010058

   APIC: 00

   APIC: 01

  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0

  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff
flags 40040100 index 10000000

  PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0
limit febfffff flags 40040200 index 10000100

  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index 10

  PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0 limit 0
flags e0004200 index 20

  PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0 limit
0 flags f0000200 index 7

   PCI: 00:00.0

   PCI: 00:01.0

   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit
febfffff flags 60001200 index 10

   PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags
60000100 index 14

   PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit
febfffff flags 60000200 index 18

   PCI: 00:04.0 child on link 0 PCI: 01:00.0

   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff
flags 60080102 index 1c

   PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit
febfffff flags 60081202 index 24

   PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit
febfffff flags 60080202 index 20

    PCI: 01:00.0

    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
60000100 index 10

    PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit
febfffff flags 60001201 index 18

    PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit
febfffff flags 60001201 index 20

    PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17 limit
febfffff flags 60002200 index 30

   PCI: 00:05.0

   PCI: 00:06.0

   PCI: 00:07.0

   PCI: 00:08.0

   PCI: 00:11.0

   PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags
60000100 index 10

   PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags
60000100 index 14

   PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags
60000100 index 18

   PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags
60000100 index 1c

   PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags
60000100 index 20

   PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit
febfffff flags 60000200 index 24

   PCI: 00:12.0

   PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:12.1

   PCI: 00:12.2

   PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10

   PCI: 00:13.0

   PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:13.1

   PCI: 00:13.2

   PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit
febfffff flags 60000200 index 10

   PCI: 00:14.0 child on link 0 I2C: 00:50

    I2C: 00:50

    I2C: 00:51

   PCI: 00:14.1

   PCI: 00:14.2

   PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit
febfffff flags 60000201 index 10

   PCI: 00:14.3 child on link 0 PNP: 004e.0

   PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit febfffff
flags 60000200 index a0

   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags
c0040100 index 10000000

   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0
flags c0040200 index 10000100

   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0
flags c0000200 index 3

    PNP: 004e.0

    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400
index 70

    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800
index 74

    PNP: 004e.3

    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100
index 60

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800
index 74

    PNP: 004e.4

    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100
index 60

    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.5

    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags
e0000100 index 60

    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags
e0000100 index 62

    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400
index 70

    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 72

    PNP: 004e.6

    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400
index 70

    PNP: 004e.a

    PNP: 004e.10

    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags
e0000100 index 60

    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags
e0000400 index 70

    PNP: 004e.11

    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags
c0000100 index 60

    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags
c0000400 index 70

   PCI: 00:14.4

   PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags
60080102 index 1c

   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60081202 index 24

   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit
febfffff flags 60080202 index 20

   PCI: 00:14.5

   PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit
febfffff flags 60000200 index 10

   PCI: 00:15.0

   PCI: 00:15.1

   PCI: 00:15.2

   PCI: 00:15.3

   PCI: 00:16.0

   PCI: 00:16.2

   PCI: 00:18.0

   PCI: 00:18.1

   PCI: 00:18.2

   PCI: 00:18.3

   PCI: 00:18.4

   PCI: 00:18.5

   PCI: 00:18.6

   PCI: 00:18.7

Done allocating resources.

POST: 0x88

Enabling resources...

 

Fam14h - domain_enable_resources: AmdInitMid.

agesawrapper_amdinitmid SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

passed.

  ader - leaving domain_enable_resources.

PCI: 00:00.0 cmd <- 06

PCI: 00:01.0 subsystem <- 1022/1510

PCI: 00:01.0 cmd <- 07

PCI: 00:04.0 bridge ctrl <- 0003

PCI: 00:04.0 cmd <- 07

PCI: 00:11.0 subsystem <- 1022/1510

PCI: 00:11.0 cmd <- 03

PCI: 00:12.0 subsystem <- 1022/1510

PCI: 00:12.0 cmd <- 02

PCI: 00:12.2 subsystem <- 1022/1510

PCI: 00:12.2 cmd <- 02

PCI: 00:13.0 subsystem <- 1022/1510

PCI: 00:13.0 cmd <- 02

PCI: 00:13.2 subsystem <- 1022/1510

PCI: 00:13.2 cmd <- 02

PCI: 00:14.0 subsystem <- 1022/1510

PCI: 00:14.0 cmd <- 403

PCI: 00:14.2 subsystem <- 1022/1510

PCI: 00:14.2 cmd <- 02

PCI: 00:14.3 subsystem <- 1022/1510

PCI: 00:14.3 cmd <- 0f

PCI: 00:14.4 bridge ctrl <- 0003

PCI: 00:14.4 subsystem <- 1022/1510

PCI: 00:14.4 cmd <- 21

PCI: 00:14.5 subsystem <- 1022/1510

PCI: 00:14.5 cmd <- 02

PCI: 00:18.0 subsystem <- 1022/1510

PCI: 00:18.0 cmd <- 00

PCI: 00:18.1 subsystem <- 1022/1510

PCI: 00:18.1 cmd <- 00

PCI: 00:18.2 subsystem <- 1022/1510

PCI: 00:18.2 cmd <- 00

PCI: 00:18.3 subsystem <- 1022/1510

PCI: 00:18.3 cmd <- 00

PCI: 00:18.4 subsystem <- 1022/1510

PCI: 00:18.4 cmd <- 00

PCI: 00:18.5 subsystem <- 1022/1510

PCI: 00:18.5 cmd <- 00

PCI: 00:18.6 subsystem <- 1022/1510

PCI: 00:18.6 cmd <- 00

PCI: 00:18.7 subsystem <- 1022/1510

PCI: 00:18.7 cmd <- 00

PCI: 01:00.0 cmd <- 03

done.

Initializing devices...

Root Device init

APIC_CLUSTER: 0 init

start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b

Initializing CPU #0

CPU: vendor AMD device 500f20

CPU: family 14, model 02, stepping 00

Model 14 Init.

 

MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled

 

POST: 0x93

POST: 0x60

Enabling cache

Setting up local apic... apic_id: 0x00 done.

POST: 0x9b

model_14_init done.

CPU #0 initialized

Asserting INIT.

Waiting for send to finish...

+Deasserting INIT.

Waiting for send to finish...

+#startup loops: 2.

Sending STARTUP #1 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+Sending STARTUP #2 to 1.

After apic_write.

Startup point 1.

Waiting for send to finish...

+After Startup.

Initializing CPU #1

Waiting for 1 CPUS to stop

CPU: vendor AMD device 500f20

CPU: family 14, model 02, stepping 00

Model 14 Init.

 

MTRR check

Fixed MTRRs   : Enabled

Variable MTRRs: Enabled

 

POST: 0x93

POST: 0x60

Enabling cache

Setting up local apic... apic_id: 0x01 done.

POST: 0x9b

model_14_init done.

CPU #1 initialized

All AP CPUs stopped (5043 loops)

PCI: 00:00.0 init

Northbridge init

PCI: 00:01.0 init

CBFS: Looking for 'pci1002,9804.rom'

CBFS: found.

In CBFS, ROM address for PCI: 00:01.0 = ffe00778

PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0

PCI ROM image, vendor ID 1002, device ID 9804,

PCI ROM image, Class Code 030000, Code Type 00

Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes

Real mode stub @00000600: 867 bytes

Calling Option ROM...

... Option ROM returned.

Getting information about VESA mode 4117

framebuffer: e0000000

Setting VESA mode 4117

PCI: 00:11.0 init

AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0

Number of Ports: 0x6, Port implemented(bit map): 0x3f

AHCI/RAID controller initialized

PCI: 00:14.0 init

CBFS: Looking for 'pci1002,4385.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1002,4385.rom'.

PCI: 00:14.4 init

PCI: 00:18.0 init

CBFS: Looking for 'pci1022,1700.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1700.rom'.

PCI: 00:18.1 init

CBFS: Looking for 'pci1022,1701.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1701.rom'.

PCI: 00:18.2 init

CBFS: Looking for 'pci1022,1702.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1702.rom'.

PCI: 00:18.3 init

CBFS: Looking for 'pci1022,1703.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1703.rom'.

PCI: 00:18.4 init

CBFS: Looking for 'pci1022,1704.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1704.rom'.

PCI: 00:18.5 init

CBFS: Looking for 'pci1022,1718.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1718.rom'.

PCI: 00:18.6 init

CBFS: Looking for 'pci1022,1716.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1716.rom'.

PCI: 00:18.7 init

CBFS: Looking for 'pci1022,1719.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci1022,1719.rom'.

PCI: 01:00.0 init

CBFS: Looking for 'pci10ec,8168.rom'

CBFS: ERROR: No file header found at fffffc00, attempting to recover by
searching for header

CBFS: Could not find file 'pci10ec,8168.rom'.

Option ROM address for PCI: 01:00.0 = f0100000

PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000

Incorrect expansion ROM header signature 0000

PNP: 004e.5 init

Keyboard init...

No PS/2 keyboard detected.

PNP: 004e.10 init

Devices initialized

Show all devs...After init.

Root Device: enabled 1

APIC_CLUSTER: 0: enabled 1

APIC: 00: enabled 1

PCI_DOMAIN: 0000: enabled 1

PCI: 00:00.0: enabled 1

PCI: 00:01.0: enabled 1

PCI: 00:01.1: enabled 1

PCI: 00:04.0: enabled 1

PCI: 00:05.0: enabled 0

PCI: 00:06.0: enabled 0

PCI: 00:07.0: enabled 0

PCI: 00:08.0: enabled 0

PCI: 00:11.0: enabled 1

PCI: 00:12.0: enabled 1

PCI: 00:12.1: enabled 0

PCI: 00:12.2: enabled 1

PCI: 00:13.0: enabled 1

PCI: 00:13.1: enabled 0

PCI: 00:13.2: enabled 1

PCI: 00:14.0: enabled 1

I2C: 00:50: enabled 1

I2C: 00:51: enabled 1

PCI: 00:14.1: enabled 0

PCI: 00:14.2: enabled 1

PCI: 00:14.3: enabled 1

PNP: 004e.0: enabled 0

PNP: 004e.3: enabled 0

PNP: 004e.4: enabled 0

PNP: 004e.5: enabled 1

PNP: 004e.6: enabled 0

PNP: 004e.a: enabled 0

PNP: 004e.10: enabled 1

PNP: 004e.11: enabled 0

PCI: 00:14.4: enabled 1

PCI: 00:14.5: enabled 1

PCI: 00:15.0: enabled 0

PCI: 00:15.1: enabled 0

PCI: 00:15.2: enabled 0

PCI: 00:15.3: enabled 0

PCI: 00:16.0: enabled 0

PCI: 00:16.2: enabled 0

PCI: 00:18.0: enabled 1

PCI: 00:18.1: enabled 1

PCI: 00:18.2: enabled 1

PCI: 00:18.3: enabled 1

PCI: 00:18.4: enabled 1

PCI: 00:18.5: enabled 1

PCI: 00:18.6: enabled 1

PCI: 00:18.7: enabled 1

APIC: 01: enabled 1

PCI: 01:00.0: enabled 1

POST: 0x89

Re-Initializing CBMEM area to 0x6616f000

Initializing CBMEM area to 0x6616f000 (15273984 bytes)

dword=6616f000

nvram_pos=f8, dword>>(8*i)=0

nvram_pos=f9, dword>>(8*i)=f0

nvram_pos=fa, dword>>(8*i)=16

nvram_pos=fb, dword>>(8*i)=66

Adding CBMEM entry as no. 1

Moving GDT to 6616f200...ok

POST: 0x8a

High Tables Base is 6616f000.

POST: 0x9a

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

In agesawrapper_amdinitlate, AGESA generated ACPI tables:

   DmiTable:00000000

   AcpiPstate: 00022165

   AcpiSrat:00000000

   AcpiSlit:00000000

   Mce:00022621

   Cmc:000226c7

   Alib:00022765

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

BiosAllocateBuffer BiosHeapBaseAddr: 10000

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

mid=0, did=0

mid=0, did=0

mid=0, did=0

mid=c2, did=14

mid=0, did=0

mid=0, did=0

mid=0, did=0

mid=c2, did=14

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

SLP_TYP type was 0

Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.

Adding CBMEM entry as no. 2

Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.

PIRQ table: 48 bytes.

POST: 0x9b

Wrote the mp table end at: 000f0410 - 000f0514

Adding CBMEM entry as no. 3

Wrote the mp table end at: 66170410 - 66170514

MP table: 276 bytes.

POST: 0x9c

Adding CBMEM entry as no. 4

ACPI: Writing ACPI tables at 66171400...

ACPI:  * DSDT at 661714c8

ACPI:  * DSDT @ 661714c8 Length 28cd

ACPI:  * FACS at 66173d98

ACPI:  * FADT at 66173dd8

ACPI_BLK_BASE: 0x0800

ACPI: added table 1/32, length now 40

ACPI:  * HPET at 66173ed0

ACPI: added table 2/32, length now 44

ACPI:  * MADT at 66173f08

ACPI: added table 3/32, length now 48

ACPI: added table 4/32, length now 52

ACPI:  * SRAT at 66174100

  AGESA SRAT table NULL. Skipping.

ACPI:  * SLIT at 66174100

  AGESA SLIT table NULL. Skipping.

ACPI:  * AGESA ALIB SSDT at 66174100

ACPI: added table 5/32, length now 56

ACPI:  * AGESA SSDT Pstate at 66175790

ACPI: added table 6/32, length now 60

ACPI:  * coreboot TOM SSDT2 at 66175aa0

ACPI: added table 7/32, length now 64

ACPI: done.

ACPI tables: 18149 bytes.

Adding CBMEM entry as no. 5

smbios_write_tables: 6617c800

Root Device (AMD Persimmon Mainboard)

APIC_CLUSTER: 0 (AMD Family 14h Root Complex)

APIC: 00 (AMD CPU Family 14h)

PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)

PCI: 00:00.0 (AMD Family 14h Northbridge)

PCI: 00:01.0 (AMD Family 14h Northbridge)

PCI: 00:01.1 (AMD Family 14h Northbridge)

PCI: 00:04.0 (AMD Family 14h Northbridge)

PCI: 00:05.0 (AMD Family 14h Northbridge)

PCI: 00:06.0 (AMD Family 14h Northbridge)

PCI: 00:07.0 (AMD Family 14h Northbridge)

PCI: 00:08.0 (AMD Family 14h Northbridge)

PCI: 00:11.0 (ATI SB800)

PCI: 00:12.0 (ATI SB800)

PCI: 00:12.1 (ATI SB800)

PCI: 00:12.2 (ATI SB800)

PCI: 00:13.0 (ATI SB800)

PCI: 00:13.1 (ATI SB800)

PCI: 00:13.2 (ATI SB800)

PCI: 00:14.0 (ATI SB800)

I2C: 00:50 ()

I2C: 00:51 ()

PCI: 00:14.1 (ATI SB800)

PCI: 00:14.2 (ATI SB800)

PCI: 00:14.3 (ATI SB800)

PNP: 004e.0 (Fintek F81865F Super I/O)

PNP: 004e.3 (Fintek F81865F Super I/O)

PNP: 004e.4 (Fintek F81865F Super I/O)

PNP: 004e.5 (Fintek F81865F Super I/O)

PNP: 004e.6 (Fintek F81865F Super I/O)

PNP: 004e.a (Fintek F81865F Super I/O)

PNP: 004e.10 (Fintek F81865F Super I/O)

PNP: 004e.11 (Fintek F81865F Super I/O)

PCI: 00:14.4 (ATI SB800)

PCI: 00:14.5 (ATI SB800)

PCI: 00:15.0 (ATI SB800)

PCI: 00:15.1 (ATI SB800)

PCI: 00:15.2 (ATI SB800)

PCI: 00:15.3 (ATI SB800)

PCI: 00:16.0 (ATI SB800)

PCI: 00:16.2 (ATI SB800)

PCI: 00:18.0 (AMD Family 14h Northbridge)

PCI: 00:18.1 (AMD Family 14h Northbridge)

PCI: 00:18.2 (AMD Family 14h Northbridge)

PCI: 00:18.3 (AMD Family 14h Northbridge)

PCI: 00:18.4 (AMD Family 14h Northbridge)

PCI: 00:18.5 (AMD Family 14h Northbridge)

PCI: 00:18.6 (AMD Family 14h Northbridge)

PCI: 00:18.7 (AMD Family 14h Northbridge)

APIC: 01 ()

PCI: 01:00.0 ()

SMBIOS tables: 287 bytes.

POST: 0x9d

Adding CBMEM entry as no. 6

Writing high table forward entry at 0x00000500

Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6

New low_table_end: 0x00000528

Now going to write high coreboot table at 0x6617d000

rom_table_end = 0x6617d000

Adjust low_table_end from 0x00000528 to 0x00001000 

Adjust rom_table_end from 0x6617d000 to 0x66180000 

Adding high table area

uma_memory_start=0x67000000, uma_memory_size=0x18000000 

coreboot memory table:

 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES

 1. 0000000000001000-000000000009ffff: RAM

 2. 00000000000c0000-000000006616efff: RAM

 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES

 4. 0000000067000000-000000007effffff: RESERVED

 5. 00000000f8000000-00000000f8ffffff: RESERVED

Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f

coreboot table: 532 bytes.

POST: 0x9e

Adding CBMEM entry as no. 7

Adding CBMEM entry as no. 8

POST: 0x9d

Multiboot Information structure has been written.

 0. FREE SPACE 66ff6000 0000a000

 1. GDT        6616f200 00000200

 2. IRQ TABLE  6616f400 00001000

 3. SMP TABLE  66170400 00001000

 4. ACPI       66171400 0000b400

 5. SMBIOS     6617c800 00000800

 6. COREBOOT   6617d000 00008000

 7. ACPI RESUME66185000 00e00000

 8. ACPISCRATCH66f85000 00071000

CBFS: Looking for 'fallback/payload'

CBFS: found.

Got a payload

Loading segment from rom address 0xffee35f8

  code (compression=0)

  New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630 filesize
0x18b60

  (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630
filesize 0x18b60

Loading segment from rom address 0xffee3614

  Entry Point 0x00000000

Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60

lb: [0x0000000000200000, 0x0000000000360000)

Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz:
0x0000000000018b60

it's not compressed!

[ 0x000e74a0, 00100000, 0x00100000) <- ffee3630

dest 000e74a0, end 00100000, bouncebuffer 65eaf000

Loaded segments

Jumping to boot code at fc855

POST: 0xf8

entry    = 0x000fc855

lb_start = 0x00200000

lb_size  = 0x00160000

adjust   = 0x65e0f000

buffer   = 0x65eaf000

     elf_boot_notes = 0x00272e18

adjusted_boot_notes = 0x66081e18

Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)

Found mainboard AMD Persimmon

Found CBFS header at 0xfffffbf0

Ram Size=0x6616f000 (0x0000000000000000 high)

Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)

CPU Mhz=1001

Found 22 PCI devices (max PCI bus is 02)

Found 2 cpu(s) max supported 2 cpu(s)

Copying PIR from 0x6616f400 to 0x000fdbc0

Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0

Copying ACPI RSDP from 0x66171400 to 0x000fda80

Copying SMBIOS entry point from 0x6617c800 to 0x000fda60

Scan for VGA option rom

Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b

EHCI init on dev 00:12.2 (regs=0xf0247420)

EHCI init on dev 00:13.2 (regs=0xf0247520)

OHCI init on dev 00:14.5 (regs=0xf0246000)

Found 0 lpt ports

Found 3 serial ports

ebda moved from 9fc00 to 9f400

AHCI controller at 11.0, iobase f0247000, irq 0

OHCI init on dev 00:12.0 (regs=0xf0244000)

Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0

ebda moved from 9f400 to 9f000

ebda moved from 9f000 to 9ec00

AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057
MiBytes)"

Got ps2 nak (status=51)

USB keyboard initialized

All threads complete.

Scan for option roms

Press F12 for boot menu.

 

drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
s=125045424

Returned 57344 bytes of ZoneHigh

e820 map has 6 items:

  0: 0000000000000000 - 000000000009ec00 = 1 RAM

  1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED

  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED

  3: 0000000000100000 - 000000006616d000 = 1 RAM

  4: 000000006616d000 - 000000007f000000 = 2 RESERVED

  5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED

enter handle_19:

  NULL

Booting from Hard Disk...

Booting from 0000:7c00

 

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From paulepanter at users.sourceforge.net  Fri Jun  8 01:01:18 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 08 Jun 2012 01:01:18 +0200
Subject: [coreboot] crossgcc: make[2]: iasl: command not found
Message-ID: <1339110078.4294.18.camel@mattotaupa>

Dear coreboot folks,


with a current clone of coreboot

        $ git describe
        4.0-2451-g2d1758b

and

        $ make crossgcc
          Working around non-functional -combine
        Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011)
        
        Will skip GDB ... ok
        Downloading tar balls ... 
         * gmp-5.0.5.tar.bz2 (downloading)
         * mpfr-3.1.0.tar.bz2 (downloading)
         * mpc-0.9.tar.gz (downloading)
         * libelf-0.8.13.tar.gz (downloading)
         * gcc-core-4.6.3.tar.bz2 (downloading)
         * binutils-2.22.tar.bz2 (downloading)
         * acpica-unix-20120420.tar.gz (downloading)
        
        Downloaded tar balls ... ok
        Unpacking and patching ... 
         * gmp-5.0.5.tar.bz2
         * mpfr-3.1.0.tar.bz2
         * mpc-0.9.tar.gz
         * libelf-0.8.13.tar.gz
         * gcc-core-4.6.3.tar.bz2
         * binutils-2.22.tar.bz2
         * acpica-unix-20120420.tar.gz
        Unpacked and patched ... ok
        Building GMP 5.0.5 ... ok
        Building MPFR 3.1.0 ... ok
        Building MPC 0.9 ... ok
        Building libelf 0.8.13 ... ok
        Building binutils 2.22 ... ok
        Building GCC 4.6.3 ... ok
        Skipping Expat (Python scripting not enabled)
        Skipping Python (Python scripting not enabled)
        Skipping GDB (GDB support not enabled)
        Building IASL 20120420 ... ok
        Cleaning up... ok
        
        You can now run your i386-elf cross toolchain from /opt/src/coreboot/util/crossgcc/xgcc.
        $ make menuconfig # for ASRock E350M1 with SeaBIOS master and 4 MB image
        $ make

I got the following error.

        [?]
            Checking out SeaBIOS revision origin/master
        Switched to branch 'master'
        Deleted branch coreboot (was e66fb31).
        Branch coreboot set up to track remote branch master from
        origin.
        Switched to a new branch 'coreboot'
            CONFIG     SeaBIOS origin/master
          Working around non-functional -combine
          Build default config
        #
        # configuration written
        to /opt/src/coreboot/build/seabios/.config
        #
            MAKE       SeaBIOS origin/master
          Working around non-functional -combine
          Build Kconfig config file
        /opt/src/coreboot/build/seabios/.config:89:warning: override:
        reassigning to symbol COREBOOT
        /opt/src/coreboot/build/seabios/.config:90:warning: override:
        reassigning to symbol DEBUG_SERIAL
        /opt/src/coreboot/build/seabios/.config:95:warning: override:
        reassigning to symbol VGAHOOKS
        #
        # configuration written
        to /opt/src/coreboot/build/seabios/.config
        #
        Compiling DSDT
        make[2]: iasl: Kommando nicht gefunden
        make[2]: *** [src/acpi-dsdt.hex] Fehler 127
        make[1]: *** [build] Fehler 2
        make: *** [seabios] Fehler 2

The file `.xcompile` also contains the correct definition for `IASL`.

        IASL:=/opt/src/coreboot/util/crossgcc/xgcc/bin/iasl

Running that file works too so no `noexec` flag or something else seems
to be at fault.


Thanks,

Paul
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From andywyse6 at gmail.com  Fri Jun  8 02:57:10 2012
From: andywyse6 at gmail.com (Andy Sharp)
Date: Thu, 7 Jun 2012 17:57:10 -0700
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <4fd1257c.0cbd0e0a.4083.4555SMTPIN_ADDED@mx.google.com>
References: <4fd1257c.0cbd0e0a.4083.4555SMTPIN_ADDED@mx.google.com>
Message-ID: <CAHgS8JUo0N_G4GDdmSt1es0kOegkvE8aje88GswNxz0GGXAqpA@mail.gmail.com>

Hi Steve,

Makes no [substantive] difference.   All that does is cause 4 extra lines
to be added to the console output:

.
.
.
sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling it.
.
.
.



On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich <steve.goodrich at se-eng.com>wrote:

> ARG?. Thanks, Outlook.  :P****
>
> ** **
>
> Andy,****
>
> ** **
>
> Check the devicetree.cb file in your ?/src/mainboard/amd/persimmon
> folder.  Mine shows:****
>
> ** **
>
>             device pci 15.0 off end # PCIe PortA****
>
>             device pci 15.1 off end # PCIe PortB****
>
>             device pci 15.2 off end # PCIe PortC****
>
>             device pci 15.3 off end # PCIe PortD****
>
> ** **
>
> I?m not 100% certain, but I suspect that changing these from ?off? to ?on?
> will enable the devices.  Try the change and see if the console output
> starts reflecting the devices you?re looking for.****
>
> ** **
>
>             -- Steve G.****
>
> ** **
>
> ** **
>
> ** **
>
> *From:* coreboot-bounces at coreboot.org [
> mailto:coreboot-bounces at coreboot.org <coreboot-bounces at coreboot.org>] *On
> Behalf Of *Andy Sharp
> *Sent:* Thursday, June 07, 2012 2:31 PM
> *To:* coreboot at coreboot.org
> *Subject:* [coreboot] PCIe devices not enabled on amd/persimmon****
>
> ** **
>
> Howdy,****
>
> ** **
>
> I've got an AMD/persimmon board, with the agesa family 14 northbridge on
> the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on them, but
> coreboot isn't enabling or enumerating any of the PCIe devices on the
> SB800.  Does anyone have any ideas for me?  The two devices on that
> southbridge are an NEC USB3 and a Mini-PCIe slot.****
>
> ** **
>
> ** **
>
> Pasting the console output below for those interested:****
>
> ** **
>
> ** **
>
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> starting...****
>
> POST: 0x34****
>
> BSP Family_Model: 00500f20 ****
>
> cpu_init_detectedx = 00000000 ****
>
> POST: 0x35****
>
> agesawrapper_amdinitmmio passed.****
>
> POST: 0x37****
>
> agesawrapper_amdinitreset passed.****
>
> POST: 0x39****
>
> agesawrapper_amdinitearly POST: 0x34****
>
> BSP Family_Model: 00500f20 ****
>
> cpu_init_detectedx = 00000001 ****
>
> POST: 0x35****
>
> agesawrapper_amdinitmmio passed.****
>
> POST: 0x37****
>
> agesawrapper_amdinitreset passed.****
>
> POST: 0x39****
>
> agesawrapper_amdinitearly passed.****
>
> SLP_TYP type was 0****
>
> POST: 0x40****
>
> agesawrapper_amdinitpost ****
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> ** **
>
> EventLog:     EventClass = 2, EventInfo = 8040100.****
>
>           Param1 = a00a, Param2 = 0.****
>
>           Param3 = 0, Param4 = 0.****
>
> SLP_TYP type was 0****
>
> error level: 4 ****
>
> POST: 0x42****
>
> agesawrapper_amdinitenv SLP_TYP type was 0****
>
> BiosAllocateBuffer BiosHeapBaseAddr: 10000****
>
> SLP_TYP type was 0****
>
> SLP_TYP type was 0****
>
> BiosAllocateBuffer BiosHeapBaseAddr: 10000****
>
> SLP_TYP type was 0****
>
> BiosAllocateBuffer BiosHeapBaseAddr: 10000****
>
> SLP_TYP type was 0****
>
> SLP_TYP type was 0
>
> SLP_TYP type was 0****
>
> passed.****
>
> POST: 0x43****
>
> POST: 0x44****
>
> POST: 0x50****
>
> Loading image.****
>
> CBFS: Looking for 'fallback/coreboot_ram'****
>
> CBFS: found.****
>
> CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> entry @ 0x200000****
>
> Jumping to image.****
>
> POST: 0x80****
>
> POST: 0x39****
>
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> booting...****
>
> POST: 0x40****
>
> Enumerating buses...****
>
> Show all devs...Before device enumeration.****
>
> Root Device: enabled 1****
>
> APIC_CLUSTER: 0: enabled 1****
>
> APIC: 00: enabled 1****
>
> PCI_DOMAIN: 0000: enabled 1****
>
> PCI: 00:00.0: enabled 1****
>
> PCI: 00:01.0: enabled 1****
>
> PCI: 00:01.1: enabled 1****
>
> PCI: 00:04.0: enabled 1****
>
> PCI: 00:05.0: enabled 0****
>
> PCI: 00:06.0: enabled 0****
>
> PCI: 00:07.0: enabled 0****
>
> PCI: 00:08.0: enabled 0****
>
> PCI: 00:11.0: enabled 1****
>
> PCI: 00:12.0: enabled 1****
>
> PCI: 00:12.1: enabled 1****
>
> PCI: 00:12.2: enabled 1****
>
> PCI: 00:13.0: enabled 1****
>
> PCI: 00:13.1: enabled 1****
>
> PCI: 00:13.2: enabled 1****
>
> PCI: 00:14.0: enabled 1****
>
> I2C: 00:50: enabled 1****
>
> I2C: 00:51: enabled 1****
>
> PCI: 00:14.1: enabled 1****
>
> PCI: 00:14.2: enabled 1****
>
> PCI: 00:14.3: enabled 1****
>
> PNP: 004e.0: enabled 0****
>
> PNP: 004e.3: enabled 0****
>
> PNP: 004e.4: enabled 0****
>
> PNP: 004e.5: enabled 1****
>
> PNP: 004e.6: enabled 0****
>
> PNP: 004e.a: enabled 0****
>
> PNP: 004e.10: enabled 1****
>
> PNP: 004e.11: enabled 0****
>
> PCI: 00:14.4: enabled 1****
>
> PCI: 00:14.5: enabled 1****
>
> PCI: 00:15.0: enabled 0****
>
> PCI: 00:15.1: enabled 0****
>
> PCI: 00:15.2: enabled 0****
>
> PCI: 00:15.3: enabled 0****
>
> PCI: 00:16.0: enabled 0****
>
> PCI: 00:16.2: enabled 0****
>
> PCI: 00:18.0: enabled 1****
>
> PCI: 00:18.1: enabled 1****
>
> PCI: 00:18.2: enabled 1****
>
> PCI: 00:18.3: enabled 1****
>
> PCI: 00:18.4: enabled 1****
>
> PCI: 00:18.5: enabled 1****
>
> PCI: 00:18.6: enabled 1****
>
> PCI: 00:18.7: enabled 1****
>
> Compare with tree...****
>
> Root Device: enabled 1****
>
>  APIC_CLUSTER: 0: enabled 1****
>
>   APIC: 00: enabled 1****
>
>  PCI_DOMAIN: 0000: enabled 1****
>
>   PCI: 00:00.0: enabled 1****
>
>   PCI: 00:01.0: enabled 1****
>
>   PCI: 00:01.1: enabled 1****
>
>   PCI: 00:04.0: enabled 1****
>
>   PCI: 00:05.0: enabled 0****
>
>   PCI: 00:06.0: enabled 0****
>
>   PCI: 00:07.0: enabled 0****
>
>   PCI: 00:08.0: enabled 0****
>
>   PCI: 00:11.0: enabled 1****
>
>   PCI: 00:12.0: enabled 1****
>
>   PCI: 00:12.1: enabled 1****
>
>   PCI: 00:12.2: enabled 1****
>
>   PCI: 00:13.0: enabled 1****
>
>   PCI: 00:13.1: enabled 1****
>
>   PCI: 00:13.2: enabled 1****
>
>   PCI: 00:14.0: enabled 1****
>
>    I2C: 00:50: enabled 1****
>
>    I2C: 00:51: enabled 1****
>
>   PCI: 00:14.1: enabled 1****
>
>   PCI: 00:14.2: enabled 1****
>
>   PCI: 00:14.3: enabled 1****
>
>    PNP: 004e.0: enabled 0****
>
>    PNP: 004e.3: enabled 0****
>
>    PNP: 004e.4: enabled 0****
>
>    PNP: 004e.5: enabled 1****
>
>    PNP: 004e.6: enabled 0****
>
>    PNP: 004e.a: enabled 0****
>
>    PNP: 004e.10: enabled 1****
>
>    PNP: 004e.11: enabled 0****
>
>   PCI: 00:14.4: enabled 1****
>
>   PCI: 00:14.5: enabled 1****
>
>   PCI: 00:15.0: enabled 0****
>
>   PCI: 00:15.1: enabled 0****
>
>   PCI: 00:15.2: enabled 0****
>
>   PCI: 00:15.3: enabled 0****
>
>   PCI: 00:16.0: enabled 0****
>
>   PCI: 00:16.2: enabled 0****
>
>   PCI: 00:18.0: enabled 1****
>
>   PCI: 00:18.1: enabled 1****
>
>   PCI: 00:18.2: enabled 1****
>
>   PCI: 00:18.3: enabled 1****
>
>   PCI: 00:18.4: enabled 1****
>
>   PCI: 00:18.5: enabled 1****
>
>   PCI: 00:18.6: enabled 1****
>
>   PCI: 00:18.7: enabled 1****
>
> Mainboard Persimmon Enable.****
>
> SLP_TYP type was 0****
>
> persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000****
>
> persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000****
>
> persimmon_enable: uma size 0x18000000, memory start 0x67000000****
>
> scan_static_bus for Root Device****
>
> APIC_CLUSTER: 0 enabled****
>
> PCI_DOMAIN: 0000 enabled****
>
> APIC_CLUSTER: 0 scanning...****
>
>   AP siblings=1****
>
> CPU: APIC: 00 enabled****
>
> CPU: APIC: 01 enabled****
>
> PCI_DOMAIN: 0000 scanning...****
>
> PCI: pci_scan_bus for bus 00****
>
> POST: 0x24****
>
> PCI: 00:00.0 [1022/1510] ops****
>
> PCI: 00:00.0 [1022/1510] enabled****
>
> PCI: 00:01.0 [1002/9804] enabled****
>
> Capability: type 0x01 @ 0x50****
>
> Capability: type 0x10 @ 0x58****
>
> Capability: type 0x05 @ 0xa0****
>
> Capability: type 0x0d @ 0xb0****
>
> Capability: type 0x08 @ 0xb8****
>
> Capability: type 0x01 @ 0x50****
>
> Capability: type 0x10 @ 0x58****
>
> PCI: 00:04.0 subordinate bus PCI Express****
>
> PCI: 00:04.0 [1022/1512] enabled****
>
> sb800_enable() SLP_TYP type was 0****
>
> PCI: 00:11.0 [1002/4393] ops****
>
> PCI: 00:11.0 [1002/4393] enabled****
>
> sb800_enable() PCI: 00:12.0 [1002/4397] ops****
>
> PCI: 00:12.0 [1002/4397] enabled****
>
> sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.***
> *
>
> sb800_enable() PCI: 00:12.2 [1002/4396] ops****
>
> PCI: 00:12.2 [1002/4396] enabled****
>
> sb800_enable() PCI: 00:13.0 [1002/4397] ops****
>
> PCI: 00:13.0 [1002/4397] enabled****
>
> sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.***
> *
>
> sb800_enable() PCI: 00:13.2 [1002/4396] ops****
>
> PCI: 00:13.2 [1002/4396] enabled****
>
> sb800_enable() sm_init().****
>
> IOAPIC: Clearing IOAPIC at 0xfec00000****
>
> IOAPIC: 23 interrupts****
>
> IOAPIC: reg 0x00000000 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000****
>
> IOAPIC: Initializing IOAPIC at 0xfec00000****
>
> IOAPIC: Bootstrap Processor Local APIC = 0x00****
>
> IOAPIC: ID = 0x02****
>
> IOAPIC: 23 interrupts****
>
> IOAPIC: Enabling interrupts on FSB****
>
> IOAPIC: reg 0x00000000 value 0x00000000 0x00000700****
>
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000****
>
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000****
>
> PCI: 00:14.0 [1002/4385] enabled****
>
> sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.***
> *
>
> sb800_enable() hda enabled****
>
> PCI: 00:14.2 [1002/4383] ops****
>
> PCI: 00:14.2 [1002/4383] enabled****
>
> sb800_enable() PCI: 00:14.3 [1002/439d] bus ops****
>
> PCI: 00:14.3 [1002/439d] enabled****
>
> sb800_enable() PCI: 00:14.4 [1002/4384] bus ops****
>
> PCI: 00:14.4 [1002/4384] enabled****
>
> sb800_enable() PCI: 00:14.5 [1002/4399] ops****
>
> PCI: 00:14.5 [1002/4399] enabled****
>
> sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> sb800_enable() PCI: 00:18.0 [1022/1700] enabled****
>
> PCI: 00:18.1 [1022/1701] enabled****
>
> PCI: 00:18.2 [1022/1702] enabled****
>
> PCI: 00:18.3 [1022/1703] enabled****
>
> PCI: 00:18.4 [1022/1704] enabled****
>
> PCI: 00:18.5 [1022/1718] enabled****
>
> PCI: 00:18.6 [1022/1716] enabled****
>
> PCI: 00:18.7 [1022/1719] enabled****
>
> POST: 0x25****
>
> PCI: Left over static devices:****
>
> PCI: 00:01.1****
>
> PCI: Check your devicetree.cb.****
>
> do_pci_scan_bridge for PCI: 00:04.0****
>
> PCI: pci_scan_bus for bus 01****
>
> POST: 0x24****
>
> PCI: 01:00.0 [10ec/8168] enabled****
>
> POST: 0x25****
>
> PCI: pci_scan_bus returning with max=001****
>
> POST: 0x55****
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From shekairui at gmail.com  Fri Jun  8 04:01:51 2012
From: shekairui at gmail.com (shekairui)
Date: Fri, 08 Jun 2012 10:01:51 +0800
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JUo0N_G4GDdmSt1es0kOegkvE8aje88GswNxz0GGXAqpA@mail.gmail.com>
References: <4fd1257c.0cbd0e0a.4083.4555SMTPIN_ADDED@mx.google.com>
	<CAHgS8JUo0N_G4GDdmSt1es0kOegkvE8aje88GswNxz0GGXAqpA@mail.gmail.com>
Message-ID: <4FD15D0F.4000403@gmail.com>

On 06/08/2012 08:57 AM, Andy Sharp wrote:
> Hi Steve,
>
> Makes no [substantive] difference.   All that does is cause 4 extra
> lines to be added to the console output:
>
> .
> .
> .
> sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling it.
> sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling it.
> sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling it.
> sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling it.
> .
> .
You also need to tune "gpp_configuration" in devicetree.cb, it depends 
on the PCIe port configuration, pls. reference the gpp_configuration 
definition in /src/southbridge/amd/cimx/sb800/chip.h.

The right place to trace port detecting is the CIMX vender code, 
CheckGppLinkStatus() in Gpp.c.

Thanks

>
>
>
> On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
> <steve.goodrich at se-eng.com <mailto:steve.goodrich at se-eng.com>> wrote:
>
>     ARG?. Thanks, Outlook.  :P____
>
>     __ __
>
>     Andy,____
>
>     __ __
>
>     Check the devicetree.cb file in your ?/src/mainboard/amd/persimmon
>     folder.  Mine shows:____
>
>     __ __
>
>                  device pci 15.0 off end # PCIe PortA____
>
>                  device pci 15.1 off end # PCIe PortB____
>
>                  device pci 15.2 off end # PCIe PortC____
>
>                  device pci 15.3 off end # PCIe PortD____
>
>     __ __
>
>     I?m not 100% certain, but I suspect that changing these from ?off?
>     to ?on? will enable the devices.  Try the change and see if the
>     console output starts reflecting the devices you?re looking for.____
>
>     __ __
>
>                  -- Steve G.____
>
>     __ __
>
>     __ __
>
>     __ __
>
>     *From:* coreboot-bounces at coreboot.org
>     <mailto:coreboot-bounces at coreboot.org>
>     [mailto:coreboot-bounces at coreboot.org] *On Behalf Of *Andy Sharp
>     *Sent:* Thursday, June 07, 2012 2:31 PM
>     *To:* coreboot at coreboot.org <mailto:coreboot at coreboot.org>
>     *Subject:* [coreboot] PCIe devices not enabled on amd/persimmon____
>
>     __ __
>
>     Howdy,____
>
>     __ __
>
>     I've got an AMD/persimmon board, with the agesa family 14
>     northbridge on the CPU, and the SB800 southbridge.  Both have 4 PCIe
>     ports on them, but coreboot isn't enabling or enumerating any of the
>     PCIe devices on the SB800.  Does anyone have any ideas for me?  The
>     two devices on that southbridge are an NEC USB3 and a Mini-PCIe
>     slot.____
>
>     __ __
>
>     __ __
>
>     Pasting the console output below for those interested:____
>
>     __ __
>
>     __ __
>
>     coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>     starting...____
>
>     POST: 0x34____
>
>     BSP Family_Model: 00500f20 ____
>
>     cpu_init_detectedx = 00000000 ____
>
>     POST: 0x35____
>
>     agesawrapper_amdinitmmio passed.____
>
>     POST: 0x37____
>
>     agesawrapper_amdinitreset passed.____
>
>     POST: 0x39____
>
>     agesawrapper_amdinitearly POST: 0x34____
>
>     BSP Family_Model: 00500f20 ____
>
>     cpu_init_detectedx = 00000001 ____
>
>     POST: 0x35____
>
>     agesawrapper_amdinitmmio passed.____
>
>     POST: 0x37____
>
>     agesawrapper_amdinitreset passed.____
>
>     POST: 0x39____
>
>     agesawrapper_amdinitearly passed.____
>
>     SLP_TYP type was 0____
>
>     POST: 0x40____
>
>     agesawrapper_amdinitpost ____
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     __ __
>
>     EventLog: EventClass = 2, EventInfo = 8040100.____
>
>     Param1 = a00a, Param2 = 0.____
>
>     Param3 = 0, Param4 = 0.____
>
>     SLP_TYP type was 0____
>
>     error level: 4 ____
>
>     POST: 0x42____
>
>     agesawrapper_amdinitenv SLP_TYP type was 0____
>
>     BiosAllocateBuffer BiosHeapBaseAddr: 10000____
>
>     SLP_TYP type was 0____
>
>     SLP_TYP type was 0____
>
>     BiosAllocateBuffer BiosHeapBaseAddr: 10000____
>
>     SLP_TYP type was 0____
>
>     BiosAllocateBuffer BiosHeapBaseAddr: 10000____
>
>     SLP_TYP type was 0____
>
>     SLP_TYP type was 0
>
>     SLP_TYP type was 0____
>
>     passed.____
>
>     POST: 0x43____
>
>     POST: 0x44____
>
>     POST: 0x50____
>
>     Loading image.____
>
>     CBFS: Looking for 'fallback/coreboot_ram'____
>
>     CBFS: found.____
>
>     CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792
>     bytes), entry @ 0x200000____
>
>     Jumping to image.____
>
>     POST: 0x80____
>
>     POST: 0x39____
>
>     coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>     booting...____
>
>     POST: 0x40____
>
>     Enumerating buses...____
>
>     Show all devs...Before device enumeration.____
>
>     Root Device: enabled 1____
>
>     APIC_CLUSTER: 0: enabled 1____
>
>     APIC: 00: enabled 1____
>
>     PCI_DOMAIN: 0000: enabled 1____
>
>     PCI: 00:00.0: enabled 1____
>
>     PCI: 00:01.0: enabled 1____
>
>     PCI: 00:01.1: enabled 1____
>
>     PCI: 00:04.0: enabled 1____
>
>     PCI: 00:05.0: enabled 0____
>
>     PCI: 00:06.0: enabled 0____
>
>     PCI: 00:07.0: enabled 0____
>
>     PCI: 00:08.0: enabled 0____
>
>     PCI: 00:11.0: enabled 1____
>
>     PCI: 00:12.0: enabled 1____
>
>     PCI: 00:12.1: enabled 1____
>
>     PCI: 00:12.2: enabled 1____
>
>     PCI: 00:13.0: enabled 1____
>
>     PCI: 00:13.1: enabled 1____
>
>     PCI: 00:13.2: enabled 1____
>
>     PCI: 00:14.0: enabled 1____
>
>     I2C: 00:50: enabled 1____
>
>     I2C: 00:51: enabled 1____
>
>     PCI: 00:14.1: enabled 1____
>
>     PCI: 00:14.2: enabled 1____
>
>     PCI: 00:14.3: enabled 1____
>
>     PNP: 004e.0: enabled 0____
>
>     PNP: 004e.3: enabled 0____
>
>     PNP: 004e.4: enabled 0____
>
>     PNP: 004e.5: enabled 1____
>
>     PNP: 004e.6: enabled 0____
>
>     PNP: 004e.a: enabled 0____
>
>     PNP: 004e.10: enabled 1____
>
>     PNP: 004e.11: enabled 0____
>
>     PCI: 00:14.4: enabled 1____
>
>     PCI: 00:14.5: enabled 1____
>
>     PCI: 00:15.0: enabled 0____
>
>     PCI: 00:15.1: enabled 0____
>
>     PCI: 00:15.2: enabled 0____
>
>     PCI: 00:15.3: enabled 0____
>
>     PCI: 00:16.0: enabled 0____
>
>     PCI: 00:16.2: enabled 0____
>
>     PCI: 00:18.0: enabled 1____
>
>     PCI: 00:18.1: enabled 1____
>
>     PCI: 00:18.2: enabled 1____
>
>     PCI: 00:18.3: enabled 1____
>
>     PCI: 00:18.4: enabled 1____
>
>     PCI: 00:18.5: enabled 1____
>
>     PCI: 00:18.6: enabled 1____
>
>     PCI: 00:18.7: enabled 1____
>
>     Compare with tree...____
>
>     Root Device: enabled 1____
>
>       APIC_CLUSTER: 0: enabled 1____
>
>        APIC: 00: enabled 1____
>
>       PCI_DOMAIN: 0000: enabled 1____
>
>        PCI: 00:00.0: enabled 1____
>
>        PCI: 00:01.0: enabled 1____
>
>        PCI: 00:01.1: enabled 1____
>
>        PCI: 00:04.0: enabled 1____
>
>        PCI: 00:05.0: enabled 0____
>
>        PCI: 00:06.0: enabled 0____
>
>        PCI: 00:07.0: enabled 0____
>
>        PCI: 00:08.0: enabled 0____
>
>        PCI: 00:11.0: enabled 1____
>
>        PCI: 00:12.0: enabled 1____
>
>        PCI: 00:12.1: enabled 1____
>
>        PCI: 00:12.2: enabled 1____
>
>        PCI: 00:13.0: enabled 1____
>
>        PCI: 00:13.1: enabled 1____
>
>        PCI: 00:13.2: enabled 1____
>
>        PCI: 00:14.0: enabled 1____
>
>         I2C: 00:50: enabled 1____
>
>         I2C: 00:51: enabled 1____
>
>        PCI: 00:14.1: enabled 1____
>
>        PCI: 00:14.2: enabled 1____
>
>        PCI: 00:14.3: enabled 1____
>
>         PNP: 004e.0: enabled 0____
>
>         PNP: 004e.3: enabled 0____
>
>         PNP: 004e.4: enabled 0____
>
>         PNP: 004e.5: enabled 1____
>
>         PNP: 004e.6: enabled 0____
>
>         PNP: 004e.a: enabled 0____
>
>         PNP: 004e.10: enabled 1____
>
>         PNP: 004e.11: enabled 0____
>
>        PCI: 00:14.4: enabled 1____
>
>        PCI: 00:14.5: enabled 1____
>
>        PCI: 00:15.0: enabled 0____
>
>        PCI: 00:15.1: enabled 0____
>
>        PCI: 00:15.2: enabled 0____
>
>        PCI: 00:15.3: enabled 0____
>
>        PCI: 00:16.0: enabled 0____
>
>        PCI: 00:16.2: enabled 0____
>
>        PCI: 00:18.0: enabled 1____
>
>        PCI: 00:18.1: enabled 1____
>
>        PCI: 00:18.2: enabled 1____
>
>        PCI: 00:18.3: enabled 1____
>
>        PCI: 00:18.4: enabled 1____
>
>        PCI: 00:18.5: enabled 1____
>
>        PCI: 00:18.6: enabled 1____
>
>        PCI: 00:18.7: enabled 1____
>
>     Mainboard Persimmon Enable.____
>
>     SLP_TYP type was 0____
>
>     persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000____
>
>     persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
>     0x00000000____
>
>     persimmon_enable: uma size 0x18000000, memory start 0x67000000____
>
>     scan_static_bus for Root Device____
>
>     APIC_CLUSTER: 0 enabled____
>
>     PCI_DOMAIN: 0000 enabled____
>
>     APIC_CLUSTER: 0 scanning...____
>
>        AP siblings=1____
>
>     CPU: APIC: 00 enabled____
>
>     CPU: APIC: 01 enabled____
>
>     PCI_DOMAIN: 0000 scanning...____
>
>     PCI: pci_scan_bus for bus 00____
>
>     POST: 0x24____
>
>     PCI: 00:00.0 [1022/1510] ops____
>
>     PCI: 00:00.0 [1022/1510] enabled____
>
>     PCI: 00:01.0 [1002/9804] enabled____
>
>     Capability: type 0x01 @ 0x50____
>
>     Capability: type 0x10 @ 0x58____
>
>     Capability: type 0x05 @ 0xa0____
>
>     Capability: type 0x0d @ 0xb0____
>
>     Capability: type 0x08 @ 0xb8____
>
>     Capability: type 0x01 @ 0x50____
>
>     Capability: type 0x10 @ 0x58____
>
>     PCI: 00:04.0 subordinate bus PCI Express____
>
>     PCI: 00:04.0 [1022/1512] enabled____
>
>     sb800_enable() SLP_TYP type was 0____
>
>     PCI: 00:11.0 [1002/4393] ops____
>
>     PCI: 00:11.0 [1002/4393] enabled____
>
>     sb800_enable() PCI: 00:12.0 [1002/4397] ops____
>
>     PCI: 00:12.0 [1002/4397] enabled____
>
>     sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
>     it.____
>
>     sb800_enable() PCI: 00:12.2 [1002/4396] ops____
>
>     PCI: 00:12.2 [1002/4396] enabled____
>
>     sb800_enable() PCI: 00:13.0 [1002/4397] ops____
>
>     PCI: 00:13.0 [1002/4397] enabled____
>
>     sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
>     it.____
>
>     sb800_enable() PCI: 00:13.2 [1002/4396] ops____
>
>     PCI: 00:13.2 [1002/4396] enabled____
>
>     sb800_enable() sm_init().____
>
>     IOAPIC: Clearing IOAPIC at 0xfec00000____
>
>     IOAPIC: 23 interrupts____
>
>     IOAPIC: reg 0x00000000 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000001 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000002 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000003 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000004 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000005 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000006 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000007 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000008 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000009 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000a value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000b value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000c value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000d value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000e value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000f value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000010 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000011 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000012 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000013 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000014 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000015 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000016 value 0x00000000 0x00010000____
>
>     IOAPIC: Initializing IOAPIC at 0xfec00000____
>
>     IOAPIC: Bootstrap Processor Local APIC = 0x00____
>
>     IOAPIC: ID = 0x02____
>
>     IOAPIC: 23 interrupts____
>
>     IOAPIC: Enabling interrupts on FSB____
>
>     IOAPIC: reg 0x00000000 value 0x00000000 0x00000700____
>
>     IOAPIC: reg 0x00000001 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000002 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000003 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000004 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000005 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000006 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000007 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000008 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000009 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000a value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000b value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000c value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000d value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000e value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x0000000f value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000010 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000011 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000012 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000013 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000014 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000015 value 0x00000000 0x00010000____
>
>     IOAPIC: reg 0x00000016 value 0x00000000 0x00010000____
>
>     PCI: 00:14.0 [1002/4385] enabled____
>
>     sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
>     it.____
>
>     sb800_enable() hda enabled____
>
>     PCI: 00:14.2 [1002/4383] ops____
>
>     PCI: 00:14.2 [1002/4383] enabled____
>
>     sb800_enable() PCI: 00:14.3 [1002/439d] bus ops____
>
>     PCI: 00:14.3 [1002/439d] enabled____
>
>     sb800_enable() PCI: 00:14.4 [1002/4384] bus ops____
>
>     PCI: 00:14.4 [1002/4384] enabled____
>
>     sb800_enable() PCI: 00:14.5 [1002/4399] ops____
>
>     PCI: 00:14.5 [1002/4399] enabled____
>
>     sb800_enable() sb800_enable() sb800_enable() sb800_enable()
>     sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled____
>
>     PCI: 00:18.1 [1022/1701] enabled____
>
>     PCI: 00:18.2 [1022/1702] enabled____
>
>     PCI: 00:18.3 [1022/1703] enabled____
>
>     PCI: 00:18.4 [1022/1704] enabled____
>
>     PCI: 00:18.5 [1022/1718] enabled____
>
>     PCI: 00:18.6 [1022/1716] enabled____
>
>     PCI: 00:18.7 [1022/1719] enabled____
>
>     POST: 0x25____
>
>     PCI: Left over static devices:____
>
>     PCI: 00:01.1____
>
>     PCI: Check your devicetree.cb.____
>
>     do_pci_scan_bridge for PCI: 00:04.0____
>
>     PCI: pci_scan_bus for bus 01____
>
>     POST: 0x24____
>
>     PCI: 01:00.0 [10ec/8168] enabled____
>
>     POST: 0x25____
>
>     PCI: pci_scan_bus returning with max=001____
>
>     POST: 0x55____
>
>
>     --
>     coreboot mailing list: coreboot at coreboot.org
>     <mailto:coreboot at coreboot.org>
>     http://www.coreboot.org/mailman/listinfo/coreboot
>
>




From gerrit at coreboot.org  Fri Jun  8 05:16:00 2012
From: gerrit at coreboot.org (Zheng Bao (zheng.bao@amd.com))
Date: Fri, 8 Jun 2012 05:16:00 +0200
Subject: [coreboot] New patch to review for coreboot: e3dee5e PCI(E) slots
	on Persimmon
References: <I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e+0@gerrit.coreboot.org>
Message-ID: <I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e+1@gerrit.coreboot.org>

Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1098

-gerrit

commit e3dee5ecf44af9fce33deb44d6e1fa6a671587a6
Author: zbao <fishbaozi at gmail.com>
Date:   Fri Jun 8 12:46:36 2012 +0800

    PCI(E) slots on Persimmon
    
    (routine.asl):Set the correct device number in the pcie interrupt routine in ACPI asl.
    (devicetree.cb): Enable the PCIE bridge which is connected to the PCIE slot.
    
    Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
---
 src/mainboard/amd/persimmon/acpi/routing.asl |   24 ++++++++++++------------
 src/mainboard/amd/persimmon/devicetree.cb    |   10 +++++-----
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
index d7e4687..24bc809 100644
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ b/src/mainboard/amd/persimmon/acpi/routing.asl
@@ -391,17 +391,17 @@ Scope(\_SB) {
 
 	Name(PCIB, Package(){
 		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
+		Package(){0x0003FFFF, 0, 0, 0x14 },
+		Package(){0x0003FFFF, 1, 0, 0x15 },
+		Package(){0x0003FFFF, 2, 0, 0x16 },
+		Package(){0x0003FFFF, 3, 0, 0x17 },
+		Package(){0x0004FFFF, 0, 0, 0x15 },
+		Package(){0x0004FFFF, 1, 0, 0x16 },
+		Package(){0x0004FFFF, 2, 0, 0x17 },
+		Package(){0x0004FFFF, 3, 0, 0x14 },
+		Package(){0x0005FFFF, 0, 0, 0x16 },
+		Package(){0x0005FFFF, 1, 0, 0x17 },
+		Package(){0x0005FFFF, 2, 0, 0x14 },
+		Package(){0x0005FFFF, 3, 0, 0x15 },
 	})
 }
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index e5bbca2..d89b809 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -28,12 +28,12 @@ chip northbridge/amd/agesa/family14/root_complex
 #					device pci 18.0 on #  northbridge
 					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
 						device pci 0.0 on end # Root Complex
-						device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
 						device pci 1.1 on end # Internal Multimedia
-						device pci 4.0 on end # PCIE P2P bridge 0x9604
-						device pci 5.0 off end # PCIE P2P bridge 0x9605
-						device pci 6.0 off end # PCIE P2P bridge 0x9606
-						device pci 7.0 off end # PCIE P2P bridge 0x9607
+						device pci 4.0 on end # PCIE P2P bridge on-board NIC
+						device pci 5.0 off end # PCIE P2P bridge
+						device pci 6.0 on end # PCIE P2P bridge PCI slot
+						device pci 7.0 off end # PCIE P2P bridge
 						device pci 8.0 off end # NB/SB Link P2P bridge
 					end # agesa northbridge
 



From wmkamp at datakamp.de  Fri Jun  8 08:45:35 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Fri, 8 Jun 2012 08:45:35 +0200
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JVR8HQVKn4kTsvirK2d8oERUDXoff-MAmJctx-Q+tBOWw@mail.gmail.com>
References: <CAHgS8JVR8HQVKn4kTsvirK2d8oERUDXoff-MAmJctx-Q+tBOWw@mail.gmail.com>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F241@DATAKAMPONE.datakamp2008.local>

Hello Andy,

I think this issue is due to a failure in the coreboot initialization routine for the SB800 southbridge.
This issue is not yet solved.
I posted about this problem already in January.

I found a problem with the PCI enumeration of the PCIe Ports in the CIMX/SB800 Southbridge for the INAGUA platform.
The .../southbridge/amd/cimx/sb800/late.c routine calls the function sb_Before_PCI_Init after
case (0x16 >>3) | 2. This means when the PCI Express ports (0x15 <<3) | 0 are probed in the routine ../devices/pci_device.c function
pci_probe_dev they are not yet initialized. The probing fails and also devices behind the bridge are not recognized.
Behind the PCIe bridge I have an Intel 82574 LAN chip.
But if I move the call to sb_Before_PCI_Init behind case  (0x15 <<3) | 0 the enumeration succeed but coreboot crashes later into nothing. The Sage Debugger fails.
I can't imagine why.

Regards

Wolfgang


Von: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] Im Auftrag von Andy Sharp
Gesendet: Donnerstag, 7. Juni 2012 22:31
An: coreboot at coreboot.org
Betreff: [coreboot] PCIe devices not enabled on amd/persimmon

Howdy,

I've got an AMD/persimmon board, with the agesa family 14 northbridge on the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on them, but coreboot isn't enabling or enumerating any of the PCIe devices on the SB800.  Does anyone have any ideas for me?  The two devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.


Pasting the console output below for those interested:


coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 starting...
POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000000
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly POST: 0x34
BSP Family_Model: 00500f20
cpu_init_detectedx = 00000001
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly passed.
SLP_TYP type was 0
POST: 0x40
agesawrapper_amdinitpost
EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.

EventLog:       EventClass = 2, EventInfo = 8040100.
            Param1 = a00a, Param2 = 0.
            Param3 = 0, Param4 = 0.
SLP_TYP type was 0
error level: 4
POST: 0x42
agesawrapper_amdinitenv SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
POST: 0x43
POST: 0x44
POST: 0x50
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry @ 0x200000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 booting..
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
 APIC_CLUSTER: 0: enabled 1
  APIC: 00: enabled 1
 PCI_DOMAIN: 0000: enabled 1
  PCI: 00:00.0: enabled 1
  PCI: 00:01.0: enabled 1
  PCI: 00:01.1: enabled 1
  PCI: 00:04.0: enabled 1
  PCI: 00:05.0: enabled 0
  PCI: 00:06.0: enabled 0
  PCI: 00:07.0: enabled 0
  PCI: 00:08.0: enabled 0
  PCI: 00:11.0: enabled 1
  PCI: 00:12.0: enabled 1
  PCI: 00:12.1: enabled 1
  PCI: 00:12.2: enabled 1
  PCI: 00:13.0: enabled 1
  PCI: 00:13.1: enabled 1
  PCI: 00:13.2: enabled 1
  PCI: 00:14.0: enabled 1
   I2C: 00:50: enabled 1
   I2C: 00:51: enabled 1
  PCI: 00:14.1: enabled 1
  PCI: 00:14.2: enabled 1
  PCI: 00:14.3: enabled 1
   PNP: 004e.0: enabled 0
   PNP: 004e.3: enabled 0
   PNP: 004e.4: enabled 0
   PNP: 004e.5: enabled 1
   PNP: 004e.6: enabled 0
   PNP: 004e.a: enabled 0
   PNP: 004e.10: enabled 1
   PNP: 004e.11: enabled 0
  PCI: 00:14.4: enabled 1
  PCI: 00:14.5: enabled 1
  PCI: 00:15.0: enabled 0
  PCI: 00:15.1: enabled 0
  PCI: 00:15.2: enabled 0
  PCI: 00:15.3: enabled 0
  PCI: 00:16.0: enabled 0
  PCI: 00:16.2: enabled 0
  PCI: 00:18.0: enabled 1
  PCI: 00:18.1: enabled 1
  PCI: 00:18.2: enabled 1
  PCI: 00:18.3: enabled 1
  PCI: 00:18.4: enabled 1
  PCI: 00:18.5: enabled 1
  PCI: 00:18.6: enabled 1
  PCI: 00:18.7: enabled 1
Mainboard Persimmon Enable.
SLP_TYP type was 0
persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
persimmon_enable: uma size 0x18000000, memory start 0x67000000
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
  AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [1022/1510] ops
PCI: 00:000 [1022/1510] enabled
PCI: 00:01.0 [1002/9804] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/1512] enabled
sb800_enable() SLP_TYP type was 0
PCI: 00:11.0 [1002/4393] ops
PCI: 00:11.0 [1002/4393] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
POST: 0x25
PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x50
Capability: type 0x10 @ 0x70
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
do_pci_scan_bridge returns max 1
scan_static_bus for PCI: 00:14.3
PNP: 004e.0 disabled
PNP: 004e.3 disabled
PNP: 004e.4 disabled
PNP: 004e.5 enabled
PNP: 004e.6 disabled
PNP: 004e.a disabled
PNP: 004e.10 enabled
PNP: 004e.11 disabled
scan_static_bus for PCI: 00:14.3 done
do_pci_scan_bridge for PCI: 00:14.4
PCI: pci_scan_bus for bus 02
POST: 0x24
POST: 0x25
PCI: pci_scan_bus returning with max=002
POST: 0x55
do_pci_scan_bridge returns max 2
PCI: pci_scan_bus returning with max=002
POST: 0x55
scan_static_bus for Root Device done
done
POST: 0x66
Setting up VGA for PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0

Fam14h - cpu_bus_read_resources.
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC: 01 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done

Fam14h - domain_read_resources.
PCI_DOMAIN: 0000 read_resources bus 0 link: 0

Fam14h - read_resources.
PCI: 00:04.0 read_resources bus 1 link: 0
PCI: 00:04.0 read_resources bus 1 link: 0 done
PCI: 00:14.0 read_resources bus 0 link: 0
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
PCI: 00:14.0 read_resources bus 0 link: 0 done
SB800 - Lpc.c - lpc_read_resources - Start.
SB800 - Lpc.c - lpc_read_resources - End.
PCI: 00:14.3 read_resources bus 0 link: 0
PCI: 00:14.3 read_resources bus 0 link: 0 done
PCI: 00:14.4 read_resources bus 2 link: 0
PCI: 00:14.4 read_resources bus 2 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
   PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
   PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
    PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
    PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
    PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:11.0 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
   PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 01:00.0 10 *  [0x0 - 0xff] io
PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:04.0 1c *  [0x0 - 0xfff] io
PCI: 00:01.0 14 *  [0x1000 - 0x10ff] io
PCI: 00:11.0 20 *  [0x1400 - 0x140f] io
PCI: 00:11.0 10 *  [0x1410 - 0x1417] io
PCI: 00:11.0 18 *  [0x1418 - 0x141f] io
PCI: 00:11.0 14 *  [0x1420 - 0x1423] io
PCI: 00:11.0 1c *  [0x1424 - 0x1427] io
PCI_DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 01:00.0 20 *  [0x0 - 0x3fff] prefmem
PCI: 01:00.0 18 *  [0x4000 - 0x4fff] prefmem
PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 01:00.0 30 *  [0x0 - 0x1ffff] mem
PCI: 00:04.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:01.0 10 *  [0x0 - 0xfffffff] prefmem
PCI: 00:04.0 24 *  [0x10000000 - 0x100fffff] prefmem
PCI: 00:04.0 20 *  [0x10100000 - 0x101fffff] mem
PCI: 00:01.0 18 *  [0x10200000 - 0x1023ffff] mem
PCI: 00:14.2 10 *  [0x10240000 - 0x10243fff] mem
PCI: 00:12.0 10 *  [0x10244000 - 0x10244fff] mem
PCI: 00:13.0 10 *  [0x10245000 - 0x10245fff] mem
PCI: 00:14.5 10 *  [0x10246000 - 0x10246fff] mem
PCI: 00:11.0 24 *  [0x10247000 - 0x102473ff] mem
PCI: 00:12.2 10 *  [0x10247400 - 0x102474ff] mem
PCI: 00:13.2 10 *  [0x10247500 - 0x102475ff] mem
PCI: 00:14.3 a0 *  [0x10247600 - 0x10247600] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 10247601 size: 10247601 align: 28 gran: 0 limit: ffffffff done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 01:00.0
constrain_resources: PCI: 00:11.0
constrain_resources: PCI: 00:12.0
constrain_resources: PCI: 00:122
constrain_resources: PCI: 00:13.0
constrain_resources: PCI: 00:13.2
constrain_resources: PCI: 00:14.0
constrain_resources: I2C: 00:50
constrain_resources: I2C: 00:51
constrain_resources: PCI: 00:14.2
constrain_resources: PCI: 00:14.3
constrain_resources: PNP: 004e.5
skipping PNP: 004e.5 at 62 fixed resource, size=0!
constrain_resources: PNP: 004e.10
constrain_resources: PCI: 00:14.4
constrain_resources: PCI: 00:14.5
constrain_resources: PCI: 00:18.0
constrain_resources: PCI: 00:18.1
constrain_resources: PCI: 00:18.2
constrain_resources: PCI: 00:183
constrain_resources: PCI: 00:18.4
constrain_resources: PCI: 00:18.5
constrain_resources: PCI: 00:18.6
constrain_resources: PCI: 00:18.7
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000000 limit 0000ffff
            lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000 at 10000100 limit ffffffff
            lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0 limit:ffff
Assigned: PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:01.0 14 *  [0x2000 - 0x20ff] io
Assigned: PCI: 00:11.0 20 *  [0x2400 - 0x240f] io
Assigned: PCI: 00:11.0 10 *  [0x2410 - 0x2417] io
Assigned: PCI: 00:11.0 18 *  [0x2418 - 0x241f] io
Assigned: PCI: 00:11.0 14 *  [0x2420 - 0x2423] io
Assigned: PCI: 00:11.0 1c *  [0x2424 - 0x2427] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12 gran: 0 done
PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 01:00.0 10 *  [0x1000 - 0x10ff] io
PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:10247601 align:28 gran:0 limit:febfffff
Assigned: PCI: 00:01.0 10 *  [0xe0000000 - 0xefffffff] prefmem
Assigned: PCI: 00:04.0 24 *  [0xf0000000 - 0xf00fffff] prefmem
Assigned: PCI: 00:04.0 20 *  [0xf0100000 - 0xf01fffff] mem
Assigned: PCI: 00:01.0 18 *  [0xf0200000 - 0xf023ffff] mem
Assigned: PCI: 00:14.2 10 *  [0xf0240000 - 0xf0243fff] mem
Assigned: PCI: 00:12.0 10 *  [0xf0244000 - 0xf0244fff] mem
Assigned: PCI: 00:13.0 10 *  [0xf0245000 - 0xf0245fff] mem
Assigned: PCI: 00:14.5 10 *  [0xf0246000 - 0xf0246fff] mem
Assigned: PCI: 00:11.0 24 *  [0xf0247000 - 0xf02473ff] mem
Assigned: PCI: 00:12.2 10 *  [0xf0247400 - 0xf02474ff] mem
Assigned: PCI: 00:13.2 10 *  [0xf0247500 - 0xf02475ff] mem
Assigned: PCI: 00:14.3 a0 *  [0xf0247600 - 0xf0247600] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f0247601 size: 10247601 align: 28 gran: 0 done
PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:00.0 20 *  [0xf0000000 - 0xf0003fff] prefmem
Assigned: PCI: 01:00.0 18 *  [0xf0004000 - 0xf0004fff] prefmem
PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20 gran:20 limit:febfffff
Assigned: PCI: 01:00.0 30 *  [0xf0100000 - 0xf011ffff] mem
PCI: 00:04.0 allocate_resources_mem: next_base: f0120000 size: 100000 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:14.4 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:14.4 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
Root Device assign_resources, bus 0 link: 0

Fam14h - cpu_bus_set_resources.
APIC_CLUSTER: 0 c0010058 <- [0x00f8000000 - 0x00f8ffffff] size 0x01000000 gran 0x00 mem <mmconfig>
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0
APIC_CLUSTER: 0 assign_resources, bus 0 link: 0

Fam14h - domain_set_resources.
  amsr - incoming dev = 00272248
adsr: (before) basek = 0, limitk = 7effffff.
adsr: (after) basek = 0, limitk = 1fbfff, sizek = 1fc000.
adsr - 0xa0000 to 0xbffff resource.
adsr: mmio_basek=00380000, basek=00000300, limitk=001fbfff
0: mmio_basek=00380000, basek=00000300, limitk=001fbfff
  adsr - uma_memory_base = 67000000.
  adsr - mmio_basek = 380000.
  adsr - high_tables_size = e91000.
adsr - adding uma resource.

Fam14h - Adding UMA memory.
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
PCI: 00:01.0 18 <- [0x00f0200000 - 0x00f023ffff] size 0x00040000 gran 0x12 mem
PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 01 prefmem
PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:00.0 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
PCI: 01:00.0 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
PCI: 01:00.0 30 <- [0x00f0100000 - 0x00f011ffff] size 0x00020000 gran 0x11 romem
PCI: 00:04.0 assign_resources, bus 1 link: 0
PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
PCI: 00:11.0 24 <- [0x00f0247000 - 0x00f02473ff] size 0x00000400 gran 0x0a mem
PCI: 00:12.0 10 <- [0x00f0244000 - 0x00f0244fff] size 0x00001000 gran 0x0c mem
PCI: 00:12.2 10 <- [0x00f0247400 - 0x00f02474ff] size 0x00000100 gran 0x08 mem
PCI: 00:13.0 10 <- [0x00f0245000 - 0x00f0245fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00f0247500 - 0x00f02475ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.2 10 <- [0x00f0240000 - 0x00f0243fff] size 0x00004000 gran 0x0e mem64
SB800 - Lpc.c - lpc_set_resources - Start.
PCI: 00:14.3 a0 <- [0x00f0247600 - 0x00f0247600] size 0x00000001 gran 0x00 mem
PCI: 00:14.3 assign_resources, bus 0 link: 0
PNP: 004e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 004e.5 62 <- [0x0000000064 - 0x0000000063] size 0x00000000 gran 0x00 io
PNP: 004e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
ERROR: PNP: 004e.5 72 irq size: 0x0000000001 not assigned
PNP: 004e.10 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 004e.10 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PCI: 00:14.3 assign_resources, bus 0 link: 0
SB800 - Lpc.c - lpc_set_resources - End.
PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:14.4 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:14.4 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:14.5 10 <- [0x00f0246000 - 0x00f0246fff] size 0x00001000 gran 0x0c mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
  adsr - leaving this lovely routine.
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device child on link 0 APIC_CLUSTER: 0
  APIC_CLUSTER: 0 child on link 0 APIC: 00
  APIC_CLUSTER: 0 resource base f8000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
   APIC: 00
   APIC: 01
  PCI_DOMAIN: 0000 child on link 0 PCI: 00:00.0
  PCI_DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base e0000000 size 10247601 align 28 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
  PCI_DOMAIN: 0000 resource base c0000 size 7ef3fc00 align 0 gran 0 limit 0 flags e0004200 index 20
  PCI_DOMAIN: 0000 resource base 67000000 size 18000000 align 0 gran 0 limit 0 flags f0000200 index 7
   PCI: 00:00.0
   PCI: 00:01.0
   PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10
   PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
   PCI: 00:01.0 resource base f0200000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 18
   PCI: 00:04.0 child on link 0 PCI: 01:00.0
   PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20
    PCI: 01:00.0
    PCI: 01:00.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
    PCI: 01:00.0 resource base f0004000 size 1000 align 12 gran 12 limit febfffff flags 60001201 index 18
    PCI: 01:00.0 resource base f0000000 size 4000 align 14 gran 14 limit febfffff flags 60001201 index 20
    PCI: 01:00.0 resource base f0100000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
   PCI: 00:05.0
   PCI: 00:06.0
   PCI: 00:07.0
   PCI: 00:08.0
   PCI: 00:11.0
   PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:11.0 resource base f0247000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
   PCI: 00:12.0
   PCI: 00:12.0 resource base f0244000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:12.1
   PCI: 00:12.2
   PCI: 00:12.2 resource base f0247400 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:13.0
   PCI: 00:13.0 resource base f0245000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:13.1
   PCI: 00:13.2
   PCI: 00:13.2 resource base f0247500 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10
   PCI: 00:14.0 child on link 0 I2C: 00:50
    I2C: 00:50
    I2C: 00:51
   PCI: 00:14.1
   PCI: 00:14.2
   PCI: 00:14.2 resource base f0240000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10
   PCI: 00:14.3 child on link 0 PNP: 004e.0
   PCI: 00:14.3 resource base f0247600 size 1 align 0 gran 0 limit febfffff flags 60000200 index a0
   PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
    PNP: 004e.0
    PNP: 004e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
    PNP: 004e.3
    PNP: 004e.3 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
    PNP: 004e.4
    PNP: 004e.4 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
    PNP: 004e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.5
    PNP: 004e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
    PNP: 004e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags e0000100 index 62
    PNP: 004e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 004e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 72
    PNP: 004e.6
    PNP: 004e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
    PNP: 004e.a
    PNP: 004e.10
    PNP: 004e.10 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 004e.10 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 004e.11
    PNP: 004e.11 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.11 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
   PCI: 00:14.4
   PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:14.4 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
   PCI: 00:14.5
   PCI: 00:14.5 resource base f0246000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:15.0
   PCI: 00:15.1
   PCI: 00:15.2
   PCI: 00:15.3
   PCI: 00:16.0
   PCI: 00:16.2
   PCI: 00:18.0
   PCI: 00:18.1
   PCI: 00:18.2
   PCI: 00:18.3
   PCI: 00:18.4
   PCI: 00:18.5
   PCI: 00:18.6
   PCI: 00:18.7
Done allocating resources.
POST: 0x88
Enabling resources...

Fam14h - domain_enable_resources: AmdInitMid.
agesawrapper_amdinitmid SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
  ader - leaving domain_enable_resources.
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 subsystem <- 1022/1510
PCI: 00:01.0 cmd <- 07
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 07
PCI: 00:11.0 subsystem <- 1022/1510
PCI: 00:11.0 cmd <- 03
PCI: 00:12.0 subsystem <- 1022/1510
PCI: 00:12.0 cmd <- 02
PCI: 00:12.2 subsystem <- 1022/1510
PCI: 00:12.2 cmd <- 02
PCI: 00:13.0 subsystem <- 1022/1510
PCI: 00:13.0 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/1510
PCI: 00:13.2 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/1510
PCI: 00:14.0 cmd <- 403
PCI: 00:14.2 subsystem <- 1022/1510
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/1510
PCI: 00:14.3 cmd <- 0f
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 subsystem <- 1022/1510
PCI: 00:14.4 cmd <- 21
PCI: 00:14.5 subsystem <- 1022/1510
PCI: 00:14.5 cmd <- 02
PCI: 00:18.0 subsystem <- 1022/1510
PCI: 00:18.0 cmd <- 00
PCI: 00:18.1 subsystem <- 1022/1510
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/1510
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 subsystem <- 1022/1510
PCI: 00:18.3 cmd <- 00
PCI: 00:18.4 subsystem <- 1022/1510
PCI: 00:18.4 cmd <- 00
PCI: 00:18.5 subsystem <- 1022/1510
PCI: 00:18.5 cmd <- 00
PCI: 00:18.6 subsystem <- 1022/1510
PCI: 00:18.6 cmd <- 00
PCI: 00:18.7 subsystem <- 1022/1510
PCI: 00:18.7 cmd <- 00
PCI: 01:00.0 cmd <- 03
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
start_eip=0x00006000, offset=0x00200000, code_size=0x0000005b
Initializing CPU #0
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x00 done.
POST: 0x9b
model_14_init done.
CPU #0 initialized
Asserting INIT.
Waiting for send to finish...
+Deasserting INIT.
Waiting for send to finish...
+#startup loops: 2.
Sending STARTUP #1 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+Sending STARTUP #2 to 1.
After apic_write.
Startup point 1.
Waiting for send to finish...
+After Startup.
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 500f20
CPU: family 14, model 02, stepping 00
Model 14 Init.

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

POST: 0x93
POST: 0x60
Enabling cache
Setting up local apic... apic_id: 0x01 done.
POST: 0x9b
model_14_init done.
CPU #1 initialized
All AP CPUs stopped (5043 loops)
PCI: 00:00.0 init
Northbridge init
PCI: 00:01.0 init
CBFS: Looking for 'pci1002,9804.rom'
CBFS: found.
In CBFS, ROM address for PCI: 00:01.0 = ffe00778
PCI expansion ROM, signature 0xaa55, INIT size 0xe200, data ptr 0x01b0
PCI ROM image, vendor ID 1002, device ID 9804,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from ffe00778 to 0xc0000, 0xe200 bytes
Real mode stub @00000600: 867 bytes
Calling Option ROM...
... Option ROM returned.
Getting information about VESA mode 4117
framebuffer: e0000000
Setting VESA mode 4117
PCI: 00:11.0 init
AHCI controller IOMEM base: 0xF0247000, IRQ: 0x0
Number of Ports: 0x6, Port implemented(bit map): 0x3f
AHCI/RAID controller initialized
PCI: 00:14.0 init
CBFS: Looking for 'pci1002,4385.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1002,4385.rom'.
PCI: 00:14.4 init
PCI: 00:18.0 init
CBFS: Looking for 'pci1022,1700.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1700.rom'.
PCI: 00:18.1 init
CBFS: Looking for 'pci1022,1701.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1701.rom'.
PCI: 00:18.2 init
CBFS: Looking for 'pci1022,1702.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1702.rom'.
PCI: 00:18.3 init
CBFS: Looking for 'pci1022,1703.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1703.rom'.
PCI: 00:18.4 init
CBFS: Looking for 'pci1022,1704.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1704.rom'.
PCI: 00:18.5 init
CBFS: Looking for 'pci1022,1718.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1718.rom'.
PCI: 00:18.6 init
CBFS: Looking for 'pci1022,1716.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1716.rom'.
PCI: 00:18.7 init
CBFS: Looking for 'pci1022,1719.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci1022,1719.rom'.
PCI: 01:00.0 init
CBFS: Looking for 'pci10ec,8168.rom'
CBFS: ERROR: No file header found at fffffc00, attempting to recover by searching for header
CBFS: Could not find file 'pci10ec,8168.rom'.
Option ROM address for PCI: 01:00.0 = f0100000
PCI expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000
Incorrect expansion ROM header signature 0000
PNP: 004e.5 init
Keyboard init...
No PS/2 keyboard detected.
PNP: 004e.10 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 0
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 0
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 0
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
APIC: 01: enabled 1
PCI: 01:00.0: enabled 1
POST: 0x89
Re-Initializing CBMEM area to 0x6616f000
Initializing CBMEM area to 0x6616f000 (15273984 bytes)
dword=6616f000
nvram_pos=f8, dword>>(8*i)=0
nvram_pos=f9, dword>>(8*i)=f0
nvram_pos=fa, dword>>(8*i)=16
nvram_pos=fb, dword>>(8*i)=66
Adding CBMEM entry as no. 1
Moving GDT to 6616f200...ok
POST: 0x8a
High Tables Base is 6616f000.
POST: 0x9a
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
agesawrapper_amdinitlate: AmdLateParamsPtr = 220B2
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
In agesawrapper_amdinitlate, AGESA generated ACPI tables:
   DmiTable:00000000
   AcpiPstate: 00022165
   AcpiSrat:00000000
   AcpiSlit:00000000
   Mce:00022621
   Cmc:000226c7
   Alib:00022765
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
mid=0, did=0
mid=0, did=0
mid=0, did=0
mid=c2, did=14
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Adding CBMEM entry as no. 2
Writing IRQ routing tables to 0x6616f400...write_pirq_routing_table done.
PIRQ table: 48 bytes.
POST: 0x9b
Wrote the mp table end at: 000f0410 - 000f0514
Adding CBMEM entry as no. 3
Wrote the mp table end at: 66170410 - 66170514
MP table: 276 bytes.
POST: 0x9c
Adding CBMEM entry as no. 4
ACPI: Writing ACPI tables at 66171400...
ACPI:  * DSDT at 661714c8
ACPI:  * DSDT @ 661714c8 Length 28cd
ACPI:  * FACS at 66173d98
ACPI:  * FADT at 66173dd8
ACPI_BLK_BASE: 0x0800
ACPI: added table 1/32, length now 40
ACPI:  * HPET at 66173ed0
ACPI: added table 2/32, length now 44
ACPI:  * MADT at 66173f08
ACPI: added table 3/32, length now 48
ACPI: added table 4/32, length now 52
ACPI:  * SRAT at 66174100
  AGESA SRAT table NULL. Skipping.
ACPI:  * SLIT at 66174100
  AGESA SLIT table NULL. Skipping.
ACPI:  * AGESA ALIB SSDT at 66174100
ACPI: added table 5/32, length now 56
ACPI:  * AGESA SSDT Pstate at 66175790
ACPI: added table 6/32, length now 60
ACPI:  * coreboot TOM SSDT2 at 66175aa0
ACPI: added table 7/32, length now 64
ACPI: done.
ACPI tables: 18149 bytes.
Adding CBMEM entry as no. 5
smbios_write_tables: 6617c800
Root Device (AMD Persimmon Mainboard)
APIC_CLUSTER: 0 (AMD Family 14h Root Complex)
APIC: 00 (AMD CPU Family 14h)
PCI_DOMAIN: 0000 (AMD Family 14h Root Complex)
PCI: 00:00.0 (AMD Family 14h Northbridge)
PCI: 00:01.0 (AMD Family 14h Northbridge)
PCI: 00:01.1 (AMD Family 14h Northbridge)
PCI: 00:04.0 (AMD Family 14h Northbridge)
PCI: 00:05.0 (AMD Family 14h Northbridge)
PCI: 00:06.0 (AMD Family 14h Northbridge)
PCI: 00:07.0 (AMD Family 14h Northbridge)
PCI: 00:08.0 (AMD Family 14h Northbridge)
PCI: 00:11.0 (ATI SB800)
PCI: 00:12.0 (ATI SB800)
PCI: 00:12.1 (ATI SB800)
PCI: 00:12.2 (ATI SB800)
PCI: 00:13.0 (ATI SB800)
PCI: 00:13.1 (ATI SB800)
PCI: 00:13.2 (ATI SB800)
PCI: 00:14.0 (ATI SB800)
I2C: 00:50 ()
I2C: 00:51 ()
PCI: 00:14.1 (ATI SB800)
PCI: 00:14.2 (ATI SB800)
PCI: 00:14.3 (ATI SB800)
PNP: 004e.0 (Fintek F81865F Super I/O)
PNP: 004e.3 (Fintek F81865F Super I/O)
PNP: 004e.4 (Fintek F81865F Super I/O)
PNP: 004e.5 (Fintek F81865F Super I/O)
PNP: 004e.6 (Fintek F81865F Super I/O)
PNP: 004e.a (Fintek F81865F Super I/O)
PNP: 004e.10 (Fintek F81865F Super I/O)
PNP: 004e.11 (Fintek F81865F Super I/O)
PCI: 00:14.4 (ATI SB800)
PCI: 00:14.5 (ATI SB800)
PCI: 00:15.0 (ATI SB800)
PCI: 00:15.1 (ATI SB800)
PCI: 00:15.2 (ATI SB800)
PCI: 00:15.3 (ATI SB800)
PCI: 00:16.0 (ATI SB800)
PCI: 00:162 (ATI SB800)
PCI: 00:18.0 (AMD Family 14h Northbridge)
PCI: 00:18.1 (AMD Family 14h Northbridge)
PCI: 00:18.2 (AMD Family 14h Northbridge)
PCI: 00:18.3 (AMD Family 14h Northbridge)
PCI: 00:18.4 (AMD Family 14h Northbridge)
PCI: 00:18.5 (AMD Family 14h Northbridge)
PCI: 00:18.6 (AMD Family 14h Northbridge)
PCI: 00:18.7 (AMD Family 14h Northbridge)
APIC: 01 ()
PCI: 01:00.0 ()
SMBIOS tables: 287 bytes.
POST: 0x9d
Adding CBMEM entry as no. 6
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500, 0x10 bytes, checksum c9c6
New low_table_end: 0x00000528
Now going to write high coreboot table at 0x6617d000
rom_table_end = 0x6617d000
Adjust low_table_end from 0x00000528 to 0x00001000
Adjust rom_table_end from 0x6617d000 to 0x66180000
Adding high table area
uma_memory_start=0x67000000, uma_memory_size=0x18000000
coreboot memory table:
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000c0000-000000006616efff: RAM
 3. 000000006616f000-0000000066ffffff: CONFIGURATION TABLES
 4. 0000000067000000-000000007effffff: RESERVED
 5. 00000000f8000000-00000000f8ffffff: RESERVED
Wrote coreboot table at: 6617d000, 0x1fc bytes, checksum 18f
coreboot table: 532 bytes.
POST: 0x9e
Adding CBMEM entry as no. 7
Adding CBMEM entry as no. 8
POST: 0x9d
Multiboot Information structure has been written.
 0. FREE SPACE 66ff6000 0000a000
 1. GDT        6616f200 00000200
 2. IRQ TABLE  6616f400 00001000
 3. SMP TABLE  66170400 00001000
 4. ACPI       66171400 0000b400
 5. SMBIOS     6617c800 00000800
 6. COREBOOT   6617d000 00008000
 7. ACPI RESUME66185000 00e00000
 8. ACPISCRATCH66f85000 00071000
CBFS: Looking for 'fallback/payload'
CBFS: found.
Got a payload
Loading segment from rom address 0xffee35f8
  code (compression=0)
  New segment dstaddr 0xe74a0 memsize 0x18b60 srcaddr 0xffee3630 filesize 0x18b60
  (cleaned up) New segment addr 0xe74a0 size 0x18b60 offset 0xffee3630 filesize 0x18b60
Loading segment from rom address 0xffee3614
  Entry Point 0x00000000
Loading Segment: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz: 0x0000000000018b60
lb: [0x0000000000200000, 0x0000000000360000)
Post relocation: addr: 0x00000000000e74a0 memsz: 0x0000000000018b60 filesz: 0x0000000000018b60
it's not compressed!
[ 0x000e74a0, 00100000, 0x00100000) <- ffee3630
dest 000e74a0, end 00100000, bouncebuffer 65eaf000
Loaded segments
Jumping to boot code at fc855
POST: 0xf8
entry    = 0x000fc855
lb_start = 0x00200000
lb_size  = 0x00160000
adjust   = 0x65e0f000
buffer   = 0x65eaf000
     elf_boot_notes = 0x00272e18
adjusted_boot_notes = 0x66081e18
Start bios (version rel-1.7.0-0-ga026308-20120523_124912-leaky)
Found mainboard AMD Persimmon
Found CBFS header at 0xfffffbf0
Ram Size=0x6616f000 (0x0000000000000000 high)
Relocating init from 0x000e7b40 to 0x66154ae0 (size 41976)
CPU Mhz=1001
Found 22 PCI devices (max PCI bus is 02)
Found 2 cpu(s) max supported 2 cpu(s)
Copying PIR from 0x6616f400 to 0x000fdbc0
Copying MPTABLE from 0x66170400/66170410 to 0x000fdaa0
Copying ACPI RSDP from 0x66171400 to 0x000fda80
Copying SMBIOS entry point from 0x6617c800 to 0x000fda60
Scan for VGA option rom
Found option rom with bad checksum: loc=0x000c0000 len=57856 sum=b
EHCI init on dev 00:12.2 (regs=0xf0247420)
EHCI init on dev 00:13.2 (regs=0xf0247520)
OHCI init on dev 00:14.5 (regs=0xf0246000)
Found 0 lpt ports
Found 3 serial ports
ebda moved from 9fc00 to 9f400
AHCI controller at 11.0, iobase f0247000, irq 0
OHCI init on dev 00:12.0 (regs=0xf0244000)
Searching bootorder for: /pci at i0cf8/*@11/drive at 3/disk at 0
ebda moved from 9f400 to 9f000
ebda moved from 9f000 to 9ec00
AHCI/3: registering: "AHCI/3: KINGSTON SV100S264G ATA-8 Hard-Disk (61057 MiBytes)"
Got ps2 nak (status=51)
USB keyboard initialized
All threads complete.
Scan for option roms
Press F12 for boot menu.

drive 0x000fda00: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=125045424
Returned 57344 bytes of ZoneHigh
e820 map has 6 items:
  0: 0000000000000000 - 000000000009ec00 = 1 RAM
  1: 000000000009ec00 - 00000000000a0000 = 2 RESERVED
  2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
  3: 0000000000100000 - 000000006616d000 = 1 RAM
  4: 000000006616d000 - 000000007f000000 = 2 RESERVED
  5: 00000000f8000000 - 00000000f9000000 = 2 RESERVED
enter handle_19:
  NULL
Booting from Hard Disk...
Booting from 0000:7c00

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From paulepanter at users.sourceforge.net  Fri Jun  8 09:02:22 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 08 Jun 2012 09:02:22 +0200
Subject: [coreboot] New patch to review for coreboot: e3dee5e PCI(E)
 slots on Persimmon
In-Reply-To: <I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e+1@gerrit.coreboot.org>
References: <I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e+0@gerrit.coreboot.org>
	<I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e+1@gerrit.coreboot.org>
Message-ID: <1339138942.4262.8.camel@mattotaupa>

Dear Zheng,


Am Freitag, den 08.06.2012, 05:16 +0200 schrieb Zheng Bao:
> Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1098
> 
> -gerrit
> 
> commit e3dee5ecf44af9fce33deb44d6e1fa6a671587a6
> Author: zbao <fishbaozi at gmail.com>

please correct the author name to your real name.

    git config user.name Zheng Bao

Also your other commits all use your AMD address.

> Date:   Fri Jun 8 12:46:36 2012 +0800
> 
>     PCI(E) slots on Persimmon

That is not a good summary because you do not write, what you are doing.

>     (routine.asl):Set the correct device number in the pcie interrupt routine in ACPI asl.
>     (devicetree.cb): Enable the PCIE bridge which is connected to the PCIE slot.

I prefer three patches. Could you please split this patch up? That would
be awesome.

1. Persimmon: routine.asl: Set correct device number in PCIE interrupt routine
2. Persimmon: devicetree.cb: change IDs to names
3. Persimmon: devicetree.cb: enable the PCIE bridge (and refer to [1] as
this is the fix for this problem?)

If it is Andy?s Tested-bys would also be appreciated.

>     Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e
>     Signed-off-by: Zheng Bao <zheng.bao at amd.com>
>     Signed-off-by: zbao <fishbaozi at gmail.com>
> ---
>  src/mainboard/amd/persimmon/acpi/routing.asl |   24 ++++++++++++------------
>  src/mainboard/amd/persimmon/devicetree.cb    |   10 +++++-----
>  2 files changed, 17 insertions(+), 17 deletions(-)

[?]


Thanks,

Paul


[1] http://www.coreboot.org/pipermail/coreboot/2012-June/070199.html
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From paulepanter at users.sourceforge.net  Fri Jun  8 09:16:30 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 08 Jun 2012 09:16:30 +0200
Subject: [coreboot] make und Git: fatal: No names found,
 cannot describe anything.
In-Reply-To: <4FBF3107.6020301@secunet.com>
References: <1337890158.11044.13.camel@mattotaupa>
	<4FBF3107.6020301@secunet.com>
Message-ID: <1339139790.4262.13.camel@mattotaupa>

Am Freitag, den 25.05.2012, 09:13 +0200 schrieb Patrick Georgi:
> Am Do 24 Mai 2012 22:09:18 CEST schrieb Paul Menzel:
> > I guess it has to do with cloned SeaBIOS git tree.
> Indeed. I fixed it. Thanks for the heads up.

I did `git remote update`, `git rebase origin/master` but I still get
that error message.

            CONFIG     SeaBIOS origin/master
          Working around non-functional -combine
          Build default config
        #
        # configuration written to /opt/coreboot/build/seabios/.config
        #
            MAKE       SeaBIOS origin/master
          Working around non-functional -combine
          Build Kconfig config file
        /opt/coreboot/build/seabios/.config:89:warning: override: reassigning to symbol COREBOOT
        /opt/coreboot/build/seabios/.config:90:warning: override: reassigning to symbol DEBUG_SERIAL
        /opt/coreboot/build/seabios/.config:95:warning: override: reassigning to symbol VGAHOOKS
        #
        # configuration written to /opt/coreboot/build/seabios/.config
        #
          Compiling whole program /opt/coreboot/build/seabios/out/ccode32flat.o
          Compiling whole program /opt/coreboot/build/seabios/out/code32seg.o
          Compiling whole program /opt/coreboot/build/seabios/out/ccode16.o
          Compiling to assembler /opt/coreboot/build/seabios/out/asm-offsets.s
          Generating offset file /opt/coreboot/build/seabios/out/asm-offsets.h
          Compiling (16bit) /opt/coreboot/build/seabios/out/romlayout.o
          Building ld scripts
        fatal: No names found, cannot describe anything.
        Version: -20120608_090941-xbmc
        Fixed space: 0xe05b-0x10000  total: 8101  slack: 10  Percent slack: 0.1%
        16bit size:           38848
        32bit segmented size: 2307
        32bit flat size:      17309
        32bit flat init size: 40928
        Lowmem size:          2144
          Linking /opt/coreboot/build/seabios/out/rom16.o
          Stripping /opt/coreboot/build/seabios/out/rom16.strip.o
          Linking /opt/coreboot/build/seabios/out/rom32seg.o
          Stripping /opt/coreboot/build/seabios/out/rom32seg.strip.o
          Linking /opt/coreboot/build/seabios/out/rom.o
          Prepping /opt/coreboot/build/seabios/out/bios.bin
        Total size: 104004  Fixed: 58464  Free: 27068 (used 79.3% of 128KiB rom)
            CBFS       coreboot.rom
            PAYLOAD    SeaBIOS (internal, compression: LZMA)
            CONFIG     .config
            CBFSPRINT  coreboot.rom
        
        coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0
        Alignment: 64 bytes
        
        Name                           Offset     Type         Size
        cmos_layout.bin                0x0        cmos layout  1776
        fallback/romstage              0x740      stage        339744
        fallback/coreboot_ram          0x536c0    stage        189059
        fallback/payload               0x81980    payload      53639
        config                         0x8eb40    raw          3371
        (empty)                        0x8f8c0    null         3605256


Thanks,

Paul
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From paulepanter at users.sourceforge.net  Fri Jun  8 11:30:49 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Fri, 08 Jun 2012 11:30:49 +0200
Subject: [coreboot] Decrease 8 MB image to 4 MB image manually
Message-ID: <1339147849.4262.20.camel@mattotaupa>

Dear coreboot folks,


I got a known working 8 MB coreboot image emailed for the ASRock E350M1.
The chip size of the mounted flash chip is 4 MB. Looking at the contents
less than 4 MB are used.

        $ build/util/cbfstool/cbfstool /tmp/coreboot.rom print
        coreboot.rom: 8192 kB, bootblocksize 1288, romsize 8388608, offset 0x0
        Alignment: 64 bytes
        
        Name                           Offset     Type         Size
        cmos_layout.bin                0x0        cmos layout  1956
        pci1002,9802.rom               0x800      optionrom    65536
        bootsplash.jpg                 0x10840    bootsplash   170591
        fallback/romstage              0x3a300    stage        339852
        fallback/coreboot_ram          0x8d300    stage        195164
        fallback/payload               0xbcdc0    payload      53322
        config                         0xc9e80    raw          3807
        (empty)                        0xcadc0    null         7556336

Looking at the contents the empty area is also at the end besides the
following section at the very end.

        007FFAD8   4F 52 42 43  31 31 31 31  00 80 00 00  00 00 05 08  00 00 00 40  00 00 00 00  FF FF FF FF  ORBC1111........... at ........
        007FFAF4   FF FF FF FF  FA 66 89 C5  B0 01 E6 80  66 31 C0 0F  22 D8 8C C8  C1 E0 04 BB  44 FB 29 C3  .....f......f1..".......D.).
        007FFB10   2E 0F 01 1F  BB 3C FB 29  C3 2E 66 0F  01 17 0F 20  C0 66 25 D1  FF FA 7F 66  0D 01 00 00  .....<.)..f.... .f%....f....
        007FFB2C   60 0F 22 C0  66 89 E8 66  EA 73 FB FF  FF 08 00 90  17 00 4C FB  FF FF 66 90  00 00 00 00  `.".f..f.s........L...f.....
        007FFB48   00 00 00 00  17 00 4C FB  FF FF 00 00  FF FF 00 00  00 9B CF 00  FF FF 00 00  00 93 CF 00  ......L.....................
        007FFB64   2E 0F 01 15  4C FB FF FF  EA 73 FB FF  FF 08 00 89  C5 B0 10 E6  80 66 B8 10  00 8E D8 8E  ....L....s...........f......
        007FFB80   C0 8E D0 8E  E0 8E E8 89  E8 89 C5 B9  1B 00 00 00  0F 32 25 00  01 00 00 85  C0 0F 84 40  .................2%........@
        007FFB9C   02 00 00 B8  44 A3 00 80  66 BA F8 0C  EF 66 BA FC  0C ED B8 44  A3 00 80 66  BA F8 0C EF  ....D...f....f.....D...f....
        007FFBB8   B8 FF FF FF  FF 66 BA FC  0C EF B8 48  A3 00 80 66  BA F8 0C EF  66 BA FC 0C  ED 0D 53 00  .....f.....H...f....f.....S.
        007FFBD4   20 00 89 C4  B8 48 A3 00  80 66 BA F8  0C EF 66 BA  FC 0C 89 E0  EF B8 6C A3  00 80 66 BA   ....H...f....f.......l...f.
        007FFBF0   F8 0C EF 66  BA FC 0C 66  ED B8 6C A3  00 80 66 BA  F8 0C EF 66  B8 80 FF 66  BA FC 0C 66  ...f...f..l...f....f...f...f
        007FFC0C   EF B8 B8 A3  00 80 66 BA  F8 0C EF 66  BA FC 0C ED  0D 00 00 00  01 89 C4 B8  B8 A3 00 80  ......f....f................
        007FFC28   66 BA F8 0C  EF 66 BA FC  0C 89 E0 EF  BC 00 00 00  A0 B8 A0 A3  00 80 66 BA  F8 0C EF 66  f....f................f....f
        007FFC44   BA FC 0C ED  89 C7 89 E6  83 CE 02 B8  A0 A3 00 80  66 BA F8 0C  EF 66 BA FC  0C 89 F0 EF  ................f....f......
        007FFC60   89 E6 83 C6  0C 8B 36 81  E6 FF 00 00  00 81 E6 FF  3F FF FF 81  CE 00 40 00  00 89 E2 83  ......6.........?..... at .....
        007FFC7C   C2 0C 89 32  89 E6 83 C6  00 8B 36 81  CE 00 00 04  00 83 C4 00  89 34 24 B8  A0 A3 00 80  ...2......6..........4$.....
        007FFC98   66 BA F8 0C  EF 66 BA FC  0C 89 F8 EF  BC 40 0E D8  FE B0 24 66  BA D6 0C EE  66 BA D7 0C  f....f....... at ....$f....f...
        007FFCB4   EC 0F B6 F8  83 CF 01 83  E7 FD 89 F8  66 BA D7 0C  EE 8B 3C 24  83 E7 FA 83  CF 02 89 3C  ............f.....<$.......<
        007FFCD0   24 EB 00 B0  0D E6 70 E4  71 0F B6 E0  81 E4 80 00  00 00 83 FC  00 0F 94 C0  0F B6 F8 83  $.....p.q...................
        007FFCEC   FC 00 0F 84  81 00 00 00  BC 00 00 00  00 BF 31 00  00 00 EB 45  89 F8 BE 00  00 00 00 81  ..............1....E........
        007FFD08   FF 80 00 00  00 7C 0F BE  02 00 00 00  89 FA 81 EA  80 00 00 00  88 D0 89 F2  83 C2 70 83  .....|....................p.
        007FFD24   C2 00 EE 83  C6 70 83 C6  01 66 89 F2  EC 0F B6 F0  01 F4 81 E4  FF FF 00 00  83 C7 01 81  .....p...f..................
        007FFD40   E7 FF 00 00  00 83 FF 7A  7E B6 EB 00  B0 7B E6 70  E4 71 0F B6  F8 C1 E7 08  81 E7 FF FF  .......z~....{.p.q..........
        007FFD5C   00 00 EB 00  B0 7C E6 70  E4 71 0F B6  F0 09 F7 39  FC 0F 95 C0  0F B6 E0 89  E7 85 FF 74  .....|.p.q.....9...........t
        007FFD78   66 BE E0 FE  FF FF BC 85  FD FF FF EB  79 89 C6 85  F6 74 54 BF  0E 00 00 00  EB 45 89 FC  f...........y....tT......E..
        007FFD94   89 F2 01 E2  0F B6 22 89  FA 81 E2 FF  00 00 00 88  D0 B9 00 00  00 00 81 FA  80 00 00 00  ......".....................
        007FFDB0   7C 0D B9 02  00 00 00 81  EA 80 00 00  00 88 D0 89  CA 83 C2 70  83 C2 00 EE  83 C1 70 83  |..................p......p.
        007FFDCC   C1 01 66 89  CA 89 E0 EE  83 C7 01 81  FF 80 00 00  00 7C B3 BE  ED FE FF FF  BC EB FD FF  ..f..............|..........
        007FFDE8   FF EB 13 89  C4 83 C4 04  8B 24 24 85  E4 74 04 89  E8 FF E4 F4  EB FD FC A1  FC FF FF FF  .........$$..t..............
        007FFE04   8B 48 08 0F  C9 BB 00 00  00 00 29 CB  8B 48 14 0F  C9 01 CB B8  00 00 00 00  80 3C 30 00  .H........)..H...........<0.
        007FFE20   74 05 83 C0  01 EB F5 83  C0 01 8B 3B  39 3D AC FE  FF FF 75 69  8B 7B 04 39  3D B0 FE FF  t..........;9=....ui.{.9=...
        007FFE3C   FF 75 5E 89  DF 83 C7 18  89 C1 F3 A6  75 09 8B 43  14 0F C8 01  D8 FF E4 29  DF 83 EF 18  .u^.........u..C.......)....
        007FFE58   29 FE 8B 4B  14 0F C9 01  D9 8B 7B 08  0F CF 01 F9  8B 3D FC FF  FF FF 8B 7F  10 0F CF 83  )..K......{......=..........
        007FFE74   EF 01 01 F9  F7 D7 21 F9  39 D9 76 16  89 CB 8B 0D  FC FF FF FF  8B 49 0C 0F  C9 F7 D1 83  ......!.9.v..........I......
        007FFE90   C1 01 39 CB  76 94 B8 00  00 00 00 FF  E4 8B 3D FC  FF FF FF 8B  7F 10 0F CF  01 FB EB D6  ..9.v.........=.............
        007FFEAC   4C 41 52 43  48 49 56 45  FF FF FF FF  FF FF FF FF  FF FF FF FF  FF 00 00 00  00 00 00 00  LARCHIVE....................
        007FFEC8   00 00 00 00  00 00 00 00  FF FF 00 00  00 00 00 00  00 00 00 00  00 00 00 00  63 6D 6F 73  ........................cmos
        007FFEE4   2E 64 65 66  61 75 6C 74  00 66 61 6C  6C 62 61 63  6B 2F 72 6F  6D 73 74 61  67 65 00 00  .default.fallback/romstage..
        007FFF00   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFF1C   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFF38   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  34 2E 30 2D  ........................4.0-
        007FFF54   32 34 32 31  2D 67 32 30  36 63 38 39  30 00 41 53  52 4F 43 4B  00 45 33 35  30 4D 31 00  2421-g206c890.ASROCK.E350M1.
        007FFF70   B0 00 00 00  9E 00 00 00  97 00 00 00  00 00 80 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFF8C   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFFA8   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFFC4   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  ............................
        007FFFE0   00 00 00 00  00 00 00 00  00 00 00 00  00 00 00 00  E9 05 FB FF  FF 00 00 00  E9 67 FB FF  .........................g..
        007FFFFC   D8 FA FF FF                                                                                ....

So just `dd`ing the first 4 MB to another image does not seem the way to
go. Can you give me a fool proof way to get that 8 MB image converted to
4 MB? That would be awesome.


Thanks,

Paul
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From patrick at georgi-clan.de  Fri Jun  8 13:07:58 2012
From: patrick at georgi-clan.de (Patrick Georgi)
Date: Fri, 08 Jun 2012 13:07:58 +0200
Subject: [coreboot] Decrease 8 MB image to 4 MB image manually
In-Reply-To: <1339147849.4262.20.camel@mattotaupa>
References: <1339147849.4262.20.camel@mattotaupa>
Message-ID: <4FD1DD0E.6000509@georgi-clan.de>

Am 08.06.2012 11:30, schrieb Paul Menzel:
>         fallback/romstage              0x3a300    stage        339852

> Looking at the contents the empty area is also at the end besides the
> following section at the very end.
The problem is that the romstage resides in a rather low position - it
is hard coded to its absolute position in ROM.


Patrick

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From Zheng.Bao at amd.com  Fri Jun  8 13:37:58 2012
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Fri, 8 Jun 2012 11:37:58 +0000
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JUo0N_G4GDdmSt1es0kOegkvE8aje88GswNxz0GGXAqpA@mail.gmail.com>
References: <4fd1257c.0cbd0e0a.4083.4555SMTPIN_ADDED@mx.google.com>
	<CAHgS8JUo0N_G4GDdmSt1es0kOegkvE8aje88GswNxz0GGXAqpA@mail.gmail.com>
Message-ID: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>

Hi, Andy,
The persimmon board I have got doesn't have any PCIe slot or onboard PCIe device attached to SB800. And I am wondering if you actually use a inagua board, which has the same APU & SB with persimmon and 2 minipcie slots other than that.

Let us assume you are testing on Inagua.
Here is my patch for the PCIe on SB800. There was a bug. It is just a workaround patch, not ready for submitting.

This patch can fix the sb800/pcie issue on Inagua. If you have your work based on persimmon, please note the devicetree.cb should be modify as Inagua.
The dev15func[0123] should be enabled and the gpp_configuration should be 4.

Joe

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 0ce82b3..34cd937 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -29,6 +29,7 @@
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
+#include "smbus.h"
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
 
 
@@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
         .set_resources = pci_dev_set_resources,
         .enable_resources = pci_bus_enable_resources,
         .init = pci_init,
+        .enable = 0,
         .scan_bus = pci_scan_bridge,
         .reset_bus = pci_bus_reset,
         .ops_pci = &lops_pci,
@@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
 	.reset_bus        = pci_bus_reset,
 	.ops_pci          = &lops_pci,
 };
-
+#if 0
 /* 0:15:0 PCIe PortA */
 static const struct pci_driver PORTA_driver __pci_driver = {
         .ops = &bridge_ops,
@@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver __pci_driver = {
         .vendor = PCI_VENDOR_ID_ATI,
         .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
 };
-
+#endif
 
 /**
  * South Bridge CIMx ramstage entry point wrapper.
@@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
 	switch (dev->path.pci.devfn) {
 	case (0x11 << 3) | 0: /* 0:11.0  SATA */
 		/* the first sb800 device */
+		abcfg_reg(0xc0, 0x1FF, 0x0F4);
 		sb800_cimx_config(sb_config);
 
 		if (dev->enabled) {
@@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
 			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 		}
 		break;
+	case (0x15 << 3) | 1:
+	case (0x15 << 3) | 2:
+	case (0x15 << 3) | 3:
+		//abcfg_reg(0xc0, 0xF0, 0x00);
+		break;
 
 	case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 		sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
@@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
 		/* call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
+		abcfg_reg(0xc0, 0x100, 0x100);
 #if CONFIG_HAVE_ACPI_RESUME
 		if (acpi_slp_type != 3)
 			sb_Before_Pci_Init();




From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
Sent: Friday, June 08, 2012 8:57 AM
To: coreboot at coreboot.org
Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon

Hi Steve,

Makes no [substantive] difference. ? All that does is cause 4 extra lines to be added to the console output:

.
.
.
sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling it.
sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling it.
.
.
.


On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich <steve.goodrich at se-eng.com> wrote:
ARG.. Thanks, Outlook.? :P
?
Andy,
?
Check the devicetree.cb file in your ./src/mainboard/amd/persimmon folder.? Mine shows:
?
??????????? device pci 15.0 off end # PCIe PortA
??????????? device pci 15.1 off end # PCIe PortB
??????????? device pci 15.2 off end # PCIe PortC
??????????? device pci 15.3 off end # PCIe PortD
?
I'm not 100% certain, but I suspect that changing these from "off" to "on" will enable the devices.? Try the change and see if the console output starts reflecting the devices you're looking for.
?
??????????? -- Steve G.
?
?
?
From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
Sent: Thursday, June 07, 2012 2:31 PM
To: coreboot at coreboot.org
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
?
Howdy,
?
I've got an AMD/persimmon board, with the agesa family 14 northbridge on the CPU, and the SB800 southbridge. ?Both have 4 PCIe ports on them, but coreboot isn't enabling or enumerating any of the PCIe devices on the SB800. ?Does anyone have any ideas for me? ?The two devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
?
?
Pasting the console output below for those interested:
?
?
coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 starting...
POST: 0x34
BSP Family_Model: 00500f20?
cpu_init_detectedx = 00000000?
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly POST: 0x34
BSP Family_Model: 00500f20?
cpu_init_detectedx = 00000001?
POST: 0x35
agesawrapper_amdinitmmio passed.
POST: 0x37
agesawrapper_amdinitreset passed.
POST: 0x39
agesawrapper_amdinitearly passed.
SLP_TYP type was 0
POST: 0x40
agesawrapper_amdinitpost?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
?
EventLog:???? EventClass = 2, EventInfo = 8040100.
????????? Param1 = a00a, Param2 = 0.
????????? Param3 = 0, Param4 = 0.
SLP_TYP type was 0
error level: 4?
POST: 0x42
agesawrapper_amdinitenv SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
BiosAllocateBuffer BiosHeapBaseAddr: 10000
SLP_TYP type was 0
SLP_TYP type was 0
SLP_TYP type was 0
passed.
POST: 0x43
POST: 0x44
POST: 0x50
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes), entry @ 0x200000
Jumping to image.
POST: 0x80
POST: 0x39
coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012 booting...
POST: 0x40
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
APIC_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
PCI_DOMAIN: 0000: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:01.1: enabled 1
PCI: 00:04.0: enabled 1
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 004e.0: enabled 0
PNP: 004e.3: enabled 0
PNP: 004e.4: enabled 0
PNP: 004e.5: enabled 1
PNP: 004e.6: enabled 0
PNP: 004e.a: enabled 0
PNP: 004e.10: enabled 1
PNP: 004e.11: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:15.0: enabled 0
PCI: 00:15.1: enabled 0
PCI: 00:15.2: enabled 0
PCI: 00:15.3: enabled 0
PCI: 00:16.0: enabled 0
PCI: 00:16.2: enabled 0
PCI: 00:18.0: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
PCI: 00:18.5: enabled 1
PCI: 00:18.6: enabled 1
PCI: 00:18.7: enabled 1
Compare with tree...
Root Device: enabled 1
?APIC_CLUSTER: 0: enabled 1
? APIC: 00: enabled 1
?PCI_DOMAIN: 0000: enabled 1
? PCI: 00:00.0: enabled 1
? PCI: 00:01.0: enabled 1
? PCI: 00:01.1: enabled 1
? PCI: 00:04.0: enabled 1
? PCI: 00:05.0: enabled 0
? PCI: 00:06.0: enabled 0
? PCI: 00:07.0: enabled 0
? PCI: 00:08.0: enabled 0
? PCI: 00:11.0: enabled 1
? PCI: 00:12.0: enabled 1
? PCI: 00:12.1: enabled 1
? PCI: 00:12.2: enabled 1
? PCI: 00:13.0: enabled 1
? PCI: 00:13.1: enabled 1
? PCI: 00:13.2: enabled 1
? PCI: 00:14.0: enabled 1
? ?I2C: 00:50: enabled 1
? ?I2C: 00:51: enabled 1
? PCI: 00:14.1: enabled 1
? PCI: 00:14.2: enabled 1
? PCI: 00:14.3: enabled 1
? ?PNP: 004e.0: enabled 0
? ?PNP: 004e.3: enabled 0
? ?PNP: 004e.4: enabled 0
? ?PNP: 004e.5: enabled 1
? ?PNP: 004e.6: enabled 0
? ?PNP: 004e.a: enabled 0
? ?PNP: 004e.10: enabled 1
? ?PNP: 004e.11: enabled 0
? PCI: 00:14.4: enabled 1
? PCI: 00:14.5: enabled 1
? PCI: 00:15.0: enabled 0
? PCI: 00:15.1: enabled 0
? PCI: 00:15.2: enabled 0
? PCI: 00:15.3: enabled 0
? PCI: 00:16.0: enabled 0
? PCI: 00:16.2: enabled 0
? PCI: 00:18.0: enabled 1
? PCI: 00:18.1: enabled 1
? PCI: 00:18.2: enabled 1
? PCI: 00:18.3: enabled 1
? PCI: 00:18.4: enabled 1
? PCI: 00:18.5: enabled 1
? PCI: 00:18.6: enabled 1
? PCI: 00:18.7: enabled 1
Mainboard Persimmon Enable.
SLP_TYP type was 0
persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
persimmon_enable: uma size 0x18000000, memory start 0x67000000
scan_static_bus for Root Device
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 scanning...
? AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
POST: 0x24
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9804] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
Capability: type 0x05 @ 0xa0
Capability: type 0x0d @ 0xb0
Capability: type 0x08 @ 0xb8
Capability: type 0x01 @ 0x50
Capability: type 0x10 @ 0x58
PCI: 00:04.0 subordinate bus PCI Express
PCI: 00:04.0 [1022/1512] enabled
sb800_enable() SLP_TYP type was 0
PCI: 00:11.0 [1002/4393] ops
PCI: 00:11.0 [1002/4393] enabled
sb800_enable() PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling it.
sb800_enable() PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable() PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling it.
sb800_enable() PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
sb800_enable() sm_init().
IOAPIC: Clearing IOAPIC at 0xfec00000
IOAPIC: 23 interrupts
IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
IOAPIC: 23 interrupts
IOAPIC: Enabling interrupts on FSB
IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
PCI: 00:14.0 [1002/4385] enabled
sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling it.
sb800_enable() hda enabled
PCI: 00:14.2 [1002/4383] ops
PCI: 00:14.2 [1002/4383] enabled
sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
PCI: 00:14.3 [1002/439d] enabled
sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
PCI: 00:14.4 [1002/4384] enabled
sb800_enable() PCI: 00:14.5 [1002/4399] ops
PCI: 00:14.5 [1002/4399] enabled
sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
PCI: 00:18.1 [1022/1701] enabled
PCI: 00:18.2 [1022/1702] enabled
PCI: 00:18.3 [1022/1703] enabled
PCI: 00:18.4 [1022/1704] enabled
PCI: 00:18.5 [1022/1718] enabled
PCI: 00:18.6 [1022/1716] enabled
PCI: 00:18.7 [1022/1719] enabled
POST: 0x25
PCI: Left over static devices:
PCI: 00:01.1
PCI: Check your devicetree.cb.
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 01
POST: 0x24
PCI: 01:00.0 [10ec/8168] enabled
POST: 0x25
PCI: pci_scan_bus returning with max=001
POST: 0x55

--
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From dave at se-eng.com  Fri Jun  8 15:09:36 2012
From: dave at se-eng.com (Dave Frodin)
Date: Fri, 08 Jun 2012 07:09:36 -0600 (MDT)
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>
Message-ID: <2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>

There shouldn't be any need to guess if it is a Persimmon. On a
Persimmon board, next to the SATA connectors there should be 
printing that says "DB FT1".

The Persimmon can also have up to two PCIe Ethernet chips on it.

dave

----- Original Message -----
> From: "Zheng Bao" <Zheng.Bao at amd.com>
> To: "Andy Sharp" <andywyse6 at gmail.com>
> Cc: "coreboot at coreboot.org" <coreboot at coreboot.org>
> Sent: Friday, June 8, 2012 5:37:58 AM
> Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> 
> Hi, Andy,
> The persimmon board I have got doesn't have any PCIe slot or onboard
> PCIe device attached to SB800. And I am wondering if you actually
> use a inagua board, which has the same APU & SB with persimmon and 2
> minipcie slots other than that.
> 
> Let us assume you are testing on Inagua.
> Here is my patch for the PCIe on SB800. There was a bug. It is just a
> workaround patch, not ready for submitting.
> 
> This patch can fix the sb800/pcie issue on Inagua. If you have your
> work based on persimmon, please note the devicetree.cb should be
> modify as Inagua.
> The dev15func[0123] should be enabled and the gpp_configuration
> should be 4.
> 
> Joe
> 
> diff --git a/src/southbridge/amd/cimx/sb800/late.c
> b/src/southbridge/amd/cimx/sb800/late.c
> index 0ce82b3..34cd937 100644
> --- a/src/southbridge/amd/cimx/sb800/late.c
> +++ b/src/southbridge/amd/cimx/sb800/late.c
> @@ -29,6 +29,7 @@
>  #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
>  #include "cfg.h"		/* sb800 Cimx configuration */
>  #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
> +#include "smbus.h"
>  #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
>  
>  
> @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
>          .set_resources = pci_dev_set_resources,
>          .enable_resources = pci_bus_enable_resources,
>          .init = pci_init,
> +        .enable = 0,
>          .scan_bus = pci_scan_bridge,
>          .reset_bus = pci_bus_reset,
>          .ops_pci = &lops_pci,
> @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
>  	.reset_bus        = pci_bus_reset,
>  	.ops_pci          = &lops_pci,
>  };
> -
> +#if 0
>  /* 0:15:0 PCIe PortA */
>  static const struct pci_driver PORTA_driver __pci_driver = {
>          .ops = &bridge_ops,
> @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
> __pci_driver = {
>          .vendor = PCI_VENDOR_ID_ATI,
>          .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
>  };
> -
> +#endif
>  
>  /**
>   * South Bridge CIMx ramstage entry point wrapper.
> @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
>  	switch (dev->path.pci.devfn) {
>  	case (0x11 << 3) | 0: /* 0:11.0  SATA */
>  		/* the first sb800 device */
> +		abcfg_reg(0xc0, 0x1FF, 0x0F4);
>  		sb800_cimx_config(sb_config);
>  
>  		if (dev->enabled) {
> @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
>  			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
>  		}
>  		break;
> +	case (0x15 << 3) | 1:
> +	case (0x15 << 3) | 2:
> +	case (0x15 << 3) | 3:
> +		//abcfg_reg(0xc0, 0xF0, 0x00);
> +		break;
>  
>  	case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
>  		sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
> @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
>  		/* call the CIMX entry at the last sb800 device,
>  		 * so make sure the mainboard devicetree is complete
>  		 */
> +		abcfg_reg(0xc0, 0x100, 0x100);
>  #if CONFIG_HAVE_ACPI_RESUME
>  		if (acpi_slp_type != 3)
>  			sb_Before_Pci_Init();
> 
> 
> 
> 
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> Sent: Friday, June 08, 2012 8:57 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> 
> Hi Steve,
> 
> Makes no [substantive] difference. ? All that does is cause 4 extra
> lines to be added to the console output:
> 
> .
> .
> .
> sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
> it.
> sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
> it.
> sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
> it.
> sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
> it.
> .
> .
> .
> 
> 
> On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
> <steve.goodrich at se-eng.com> wrote:
> ARG.. Thanks, Outlook.? :P
> ?
> Andy,
> ?
> Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
> folder.? Mine shows:
> ?
> ??????????? device pci 15.0 off end # PCIe PortA
> ??????????? device pci 15.1 off end # PCIe PortB
> ??????????? device pci 15.2 off end # PCIe PortC
> ??????????? device pci 15.3 off end # PCIe PortD
> ?
> I'm not 100% certain, but I suspect that changing these from "off" to
> "on" will enable the devices.? Try the change and see if the console
> output starts reflecting the devices you're looking for.
> ?
> ??????????? -- Steve G.
> ?
> ?
> ?
> From: coreboot-bounces at coreboot.org
> [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> Sent: Thursday, June 07, 2012 2:31 PM
> To: coreboot at coreboot.org
> Subject: [coreboot] PCIe devices not enabled on amd/persimmon
> ?
> Howdy,
> ?
> I've got an AMD/persimmon board, with the agesa family 14 northbridge
> on the CPU, and the SB800 southbridge. ?Both have 4 PCIe ports on
> them, but coreboot isn't enabling or enumerating any of the PCIe
> devices on the SB800. ?Does anyone have any ideas for me? ?The two
> devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
> ?
> ?
> Pasting the console output below for those interested:
> ?
> ?
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> starting...
> POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000000
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly POST: 0x34
> BSP Family_Model: 00500f20
> cpu_init_detectedx = 00000001
> POST: 0x35
> agesawrapper_amdinitmmio passed.
> POST: 0x37
> agesawrapper_amdinitreset passed.
> POST: 0x39
> agesawrapper_amdinitearly passed.
> SLP_TYP type was 0
> POST: 0x40
> agesawrapper_amdinitpost
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> ?
> EventLog:???? EventClass = 2, EventInfo = 8040100.
> ????????? Param1 = a00a, Param2 = 0.
> ????????? Param3 = 0, Param4 = 0.
> SLP_TYP type was 0
> error level: 4
> POST: 0x42
> agesawrapper_amdinitenv SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> BiosAllocateBuffer BiosHeapBaseAddr: 10000
> SLP_TYP type was 0
> SLP_TYP type was 0
> SLP_TYP type was 0
> passed.
> POST: 0x43
> POST: 0x44
> POST: 0x50
> Loading image.
> CBFS: Looking for 'fallback/coreboot_ram'
> CBFS: found.
> CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> entry @ 0x200000
> Jumping to image.
> POST: 0x80
> POST: 0x39
> coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> booting...
> POST: 0x40
> Enumerating buses...
> Show all devs...Before device enumeration.
> Root Device: enabled 1
> APIC_CLUSTER: 0: enabled 1
> APIC: 00: enabled 1
> PCI_DOMAIN: 0000: enabled 1
> PCI: 00:00.0: enabled 1
> PCI: 00:01.0: enabled 1
> PCI: 00:01.1: enabled 1
> PCI: 00:04.0: enabled 1
> PCI: 00:05.0: enabled 0
> PCI: 00:06.0: enabled 0
> PCI: 00:07.0: enabled 0
> PCI: 00:08.0: enabled 0
> PCI: 00:11.0: enabled 1
> PCI: 00:12.0: enabled 1
> PCI: 00:12.1: enabled 1
> PCI: 00:12.2: enabled 1
> PCI: 00:13.0: enabled 1
> PCI: 00:13.1: enabled 1
> PCI: 00:13.2: enabled 1
> PCI: 00:14.0: enabled 1
> I2C: 00:50: enabled 1
> I2C: 00:51: enabled 1
> PCI: 00:14.1: enabled 1
> PCI: 00:14.2: enabled 1
> PCI: 00:14.3: enabled 1
> PNP: 004e.0: enabled 0
> PNP: 004e.3: enabled 0
> PNP: 004e.4: enabled 0
> PNP: 004e.5: enabled 1
> PNP: 004e.6: enabled 0
> PNP: 004e.a: enabled 0
> PNP: 004e.10: enabled 1
> PNP: 004e.11: enabled 0
> PCI: 00:14.4: enabled 1
> PCI: 00:14.5: enabled 1
> PCI: 00:15.0: enabled 0
> PCI: 00:15.1: enabled 0
> PCI: 00:15.2: enabled 0
> PCI: 00:15.3: enabled 0
> PCI: 00:16.0: enabled 0
> PCI: 00:16.2: enabled 0
> PCI: 00:18.0: enabled 1
> PCI: 00:18.1: enabled 1
> PCI: 00:18.2: enabled 1
> PCI: 00:18.3: enabled 1
> PCI: 00:18.4: enabled 1
> PCI: 00:18.5: enabled 1
> PCI: 00:18.6: enabled 1
> PCI: 00:18.7: enabled 1
> Compare with tree...
> Root Device: enabled 1
> ?APIC_CLUSTER: 0: enabled 1
> ? APIC: 00: enabled 1
> ?PCI_DOMAIN: 0000: enabled 1
> ? PCI: 00:00.0: enabled 1
> ? PCI: 00:01.0: enabled 1
> ? PCI: 00:01.1: enabled 1
> ? PCI: 00:04.0: enabled 1
> ? PCI: 00:05.0: enabled 0
> ? PCI: 00:06.0: enabled 0
> ? PCI: 00:07.0: enabled 0
> ? PCI: 00:08.0: enabled 0
> ? PCI: 00:11.0: enabled 1
> ? PCI: 00:12.0: enabled 1
> ? PCI: 00:12.1: enabled 1
> ? PCI: 00:12.2: enabled 1
> ? PCI: 00:13.0: enabled 1
> ? PCI: 00:13.1: enabled 1
> ? PCI: 00:13.2: enabled 1
> ? PCI: 00:14.0: enabled 1
> ? ?I2C: 00:50: enabled 1
> ? ?I2C: 00:51: enabled 1
> ? PCI: 00:14.1: enabled 1
> ? PCI: 00:14.2: enabled 1
> ? PCI: 00:14.3: enabled 1
> ? ?PNP: 004e.0: enabled 0
> ? ?PNP: 004e.3: enabled 0
> ? ?PNP: 004e.4: enabled 0
> ? ?PNP: 004e.5: enabled 1
> ? ?PNP: 004e.6: enabled 0
> ? ?PNP: 004e.a: enabled 0
> ? ?PNP: 004e.10: enabled 1
> ? ?PNP: 004e.11: enabled 0
> ? PCI: 00:14.4: enabled 1
> ? PCI: 00:14.5: enabled 1
> ? PCI: 00:15.0: enabled 0
> ? PCI: 00:15.1: enabled 0
> ? PCI: 00:15.2: enabled 0
> ? PCI: 00:15.3: enabled 0
> ? PCI: 00:16.0: enabled 0
> ? PCI: 00:16.2: enabled 0
> ? PCI: 00:18.0: enabled 1
> ? PCI: 00:18.1: enabled 1
> ? PCI: 00:18.2: enabled 1
> ? PCI: 00:18.3: enabled 1
> ? PCI: 00:18.4: enabled 1
> ? PCI: 00:18.5: enabled 1
> ? PCI: 00:18.6: enabled 1
> ? PCI: 00:18.7: enabled 1
> Mainboard Persimmon Enable.
> SLP_TYP type was 0
> persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
> 0x00000000
> persimmon_enable: uma size 0x18000000, memory start 0x67000000
> scan_static_bus for Root Device
> APIC_CLUSTER: 0 enabled
> PCI_DOMAIN: 0000 enabled
> APIC_CLUSTER: 0 scanning...
> ? AP siblings=1
> CPU: APIC: 00 enabled
> CPU: APIC: 01 enabled
> PCI_DOMAIN: 0000 scanning...
> PCI: pci_scan_bus for bus 00
> POST: 0x24
> PCI: 00:00.0 [1022/1510] ops
> PCI: 00:00.0 [1022/1510] enabled
> PCI: 00:01.0 [1002/9804] enabled
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> Capability: type 0x05 @ 0xa0
> Capability: type 0x0d @ 0xb0
> Capability: type 0x08 @ 0xb8
> Capability: type 0x01 @ 0x50
> Capability: type 0x10 @ 0x58
> PCI: 00:04.0 subordinate bus PCI Express
> PCI: 00:04.0 [1022/1512] enabled
> sb800_enable() SLP_TYP type was 0
> PCI: 00:11.0 [1002/4393] ops
> PCI: 00:11.0 [1002/4393] enabled
> sb800_enable() PCI: 00:12.0 [1002/4397] ops
> PCI: 00:12.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
> it.
> sb800_enable() PCI: 00:12.2 [1002/4396] ops
> PCI: 00:12.2 [1002/4396] enabled
> sb800_enable() PCI: 00:13.0 [1002/4397] ops
> PCI: 00:13.0 [1002/4397] enabled
> sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
> it.
> sb800_enable() PCI: 00:13.2 [1002/4396] ops
> PCI: 00:13.2 [1002/4396] enabled
> sb800_enable() sm_init().
> IOAPIC: Clearing IOAPIC at 0xfec00000
> IOAPIC: 23 interrupts
> IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> IOAPIC: Initializing IOAPIC at 0xfec00000
> IOAPIC: Bootstrap Processor Local APIC = 0x00
> IOAPIC: ID = 0x02
> IOAPIC: 23 interrupts
> IOAPIC: Enabling interrupts on FSB
> IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> PCI: 00:14.0 [1002/4385] enabled
> sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
> it.
> sb800_enable() hda enabled
> PCI: 00:14.2 [1002/4383] ops
> PCI: 00:14.2 [1002/4383] enabled
> sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> PCI: 00:14.3 [1002/439d] enabled
> sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> PCI: 00:14.4 [1002/4384] enabled
> sb800_enable() PCI: 00:14.5 [1002/4399] ops
> PCI: 00:14.5 [1002/4399] enabled
> sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> PCI: 00:18.1 [1022/1701] enabled
> PCI: 00:18.2 [1022/1702] enabled
> PCI: 00:18.3 [1022/1703] enabled
> PCI: 00:18.4 [1022/1704] enabled
> PCI: 00:18.5 [1022/1718] enabled
> PCI: 00:18.6 [1022/1716] enabled
> PCI: 00:18.7 [1022/1719] enabled
> POST: 0x25
> PCI: Left over static devices:
> PCI: 00:01.1
> PCI: Check your devicetree.cb.
> do_pci_scan_bridge for PCI: 00:04.0
> PCI: pci_scan_bus for bus 01
> POST: 0x24
> PCI: 01:00.0 [10ec/8168] enabled
> POST: 0x25
> PCI: pci_scan_bus returning with max=001
> POST: 0x55
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
> 
> 
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot



From wmkamp at datakamp.de  Fri Jun  8 16:41:03 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Fri, 8 Jun 2012 16:41:03 +0200
Subject: [coreboot] VGA Option ROM
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>


Hi,

I found a problem with VGA ROM initialization on the AMD  Inagua or Persimmon Board with coreboot and seabios.
If I configure coreboot to scan for VGA ROM, it finds the VGA device and runs the VGA ROM from CBFS.
Later seabios also finds the VGA PCI device and runs the VGA ROM too, so it gets double initialized.
In my case this seems to be a problem, because the DisplayPort to LVDS converter chip gets confused.
If I configure coreboot not to run option ROMs, seabios  does not find  the VGA PCI device (1002:9804).
So option VGA ROM will not be executed.
I have attached two logs which shows the problem in finding the VGA device.
Can anyone help me?

Regards

Wolfgang


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From rminnich at gmail.com  Fri Jun  8 17:15:30 2012
From: rminnich at gmail.com (ron minnich)
Date: Fri, 8 Jun 2012 08:15:30 -0700
Subject: [coreboot] VGA Option ROM
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
Message-ID: <CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>

I wonder if we need another option :-( to configure the rom but not run it?

ron



From wmkamp at datakamp.de  Fri Jun  8 17:42:09 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Fri, 8 Jun 2012 17:42:09 +0200
Subject: [coreboot] VGA Option ROM
In-Reply-To: <CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F245@DATAKAMPONE.datakamp2008.local>

Normally seabios should run the option ROMs. But in my issue seabios cannot run the vga option ROM,
because it cannot find the vga pci device. 
Seabios first looks for the vga pci device and if it finds a vga device it searches in CBFS for the correct ROM file. 
So I think there is a pci enumeration problem which seems to be caused from coreboot.

Wolfgang 

-----Urspr?ngliche Nachricht-----
Von: ron minnich [mailto:rminnich at gmail.com] 
Gesendet: Freitag, 8. Juni 2012 17:16
An: Wolfgang Kamp - datakamp
Cc: coreboot at coreboot.org
Betreff: Re: [coreboot] VGA Option ROM

I wonder if we need another option :-( to configure the rom but not run it?

ron






From andywyse6 at gmail.com  Sat Jun  9 02:16:21 2012
From: andywyse6 at gmail.com (Andy Sharp)
Date: Fri, 8 Jun 2012 17:16:21 -0700
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>
References: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>
	<2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>
Message-ID: <CAHgS8JV9U6kvhnOf4mDBw-nwosZdq5BPDRG=gE9PjLzk=2ffaA@mail.gmail.com>

It's a persimmon board ~:^)

I'd be happy to test any patches.  Meanwhile, I'm working on a patch to
properly enable the southbridge PCIe devices so they can be scanned.
 Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those
PCIe ports happens after the bus is scanned.  When nothing shows up on the
bus scan, the code powers down those devices right after it [too late]
powers them up.  Broken.

This persimmon board is made by iBASE. and is a mini-ITX.  It has a  PCIe
slot and a mini-PCIe card socket on the sb800 PCIe ports.  I may have
earlier said that it had a USB3 ctlr, that was my bad.  So many twisty
passages....

I'll try out various combinations of the various patches you good folks
have been throwing my way, plus some of my own ideas and let the list know
what happens.

Cheers,

a



On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave at se-eng.com> wrote:

> There shouldn't be any need to guess if it is a Persimmon. On a
> Persimmon board, next to the SATA connectors there should be
> printing that says "DB FT1".
>
> The Persimmon can also have up to two PCIe Ethernet chips on it.
>
> dave
>
> ----- Original Message -----
> > From: "Zheng Bao" <Zheng.Bao at amd.com>
> > To: "Andy Sharp" <andywyse6 at gmail.com>
> > Cc: "coreboot at coreboot.org" <coreboot at coreboot.org>
> > Sent: Friday, June 8, 2012 5:37:58 AM
> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Hi, Andy,
> > The persimmon board I have got doesn't have any PCIe slot or onboard
> > PCIe device attached to SB800. And I am wondering if you actually
> > use a inagua board, which has the same APU & SB with persimmon and 2
> > minipcie slots other than that.
> >
> > Let us assume you are testing on Inagua.
> > Here is my patch for the PCIe on SB800. There was a bug. It is just a
> > workaround patch, not ready for submitting.
> >
> > This patch can fix the sb800/pcie issue on Inagua. If you have your
> > work based on persimmon, please note the devicetree.cb should be
> > modify as Inagua.
> > The dev15func[0123] should be enabled and the gpp_configuration
> > should be 4.
> >
> > Joe
> >
> > diff --git a/src/southbridge/amd/cimx/sb800/late.c
> > b/src/southbridge/amd/cimx/sb800/late.c
> > index 0ce82b3..34cd937 100644
> > --- a/src/southbridge/amd/cimx/sb800/late.c
> > +++ b/src/southbridge/amd/cimx/sb800/late.c
> > @@ -29,6 +29,7 @@
> >  #include "SBPLATFORM.h"      /* Platfrom Specific Definitions */
> >  #include "cfg.h"             /* sb800 Cimx configuration */
> >  #include "chip.h"            /* struct
> southbridge_amd_cimx_sb800_config */
> > +#include "smbus.h"
> >  #include "sb_cimx.h"         /* AMD CIMX wrapper entries */
> >
> >
> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
> >          .set_resources = pci_dev_set_resources,
> >          .enable_resources = pci_bus_enable_resources,
> >          .init = pci_init,
> > +        .enable = 0,
> >          .scan_bus = pci_scan_bridge,
> >          .reset_bus = pci_bus_reset,
> >          .ops_pci = &lops_pci,
> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
> >       .reset_bus        = pci_bus_reset,
> >       .ops_pci          = &lops_pci,
> >  };
> > -
> > +#if 0
> >  /* 0:15:0 PCIe PortA */
> >  static const struct pci_driver PORTA_driver __pci_driver = {
> >          .ops = &bridge_ops,
> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
> > __pci_driver = {
> >          .vendor = PCI_VENDOR_ID_ATI,
> >          .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
> >  };
> > -
> > +#endif
> >
> >  /**
> >   * South Bridge CIMx ramstage entry point wrapper.
> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
> >       switch (dev->path.pci.devfn) {
> >       case (0x11 << 3) | 0: /* 0:11.0  SATA */
> >               /* the first sb800 device */
> > +             abcfg_reg(0xc0, 0x1FF, 0x0F4);
> >               sb800_cimx_config(sb_config);
> >
> >               if (dev->enabled) {
> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
> >                       sb_config->GppLinkConfig =
> sb_chip->gpp_configuration;
> >               }
> >               break;
> > +     case (0x15 << 3) | 1:
> > +     case (0x15 << 3) | 2:
> > +     case (0x15 << 3) | 3:
> > +             //abcfg_reg(0xc0, 0xF0, 0x00);
> > +             break;
> >
> >       case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
> >               sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
> >               /* call the CIMX entry at the last sb800 device,
> >                * so make sure the mainboard devicetree is complete
> >                */
> > +             abcfg_reg(0xc0, 0x100, 0x100);
> >  #if CONFIG_HAVE_ACPI_RESUME
> >               if (acpi_slp_type != 3)
> >                       sb_Before_Pci_Init();
> >
> >
> >
> >
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> > Sent: Friday, June 08, 2012 8:57 AM
> > To: coreboot at coreboot.org
> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Hi Steve,
> >
> > Makes no [substantive] difference.   All that does is cause 4 extra
> > lines to be added to the console output:
> >
> > .
> > .
> > .
> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
> > it.
> > .
> > .
> > .
> >
> >
> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
> > <steve.goodrich at se-eng.com> wrote:
> > ARG.. Thanks, Outlook.  :P
> >
> > Andy,
> >
> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
> > folder.  Mine shows:
> >
> >             device pci 15.0 off end # PCIe PortA
> >             device pci 15.1 off end # PCIe PortB
> >             device pci 15.2 off end # PCIe PortC
> >             device pci 15.3 off end # PCIe PortD
> >
> > I'm not 100% certain, but I suspect that changing these from "off" to
> > "on" will enable the devices.  Try the change and see if the console
> > output starts reflecting the devices you're looking for.
> >
> >             -- Steve G.
> >
> >
> >
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> > Sent: Thursday, June 07, 2012 2:31 PM
> > To: coreboot at coreboot.org
> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Howdy,
> >
> > I've got an AMD/persimmon board, with the agesa family 14 northbridge
> > on the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on
> > them, but coreboot isn't enabling or enumerating any of the PCIe
> > devices on the SB800.  Does anyone have any ideas for me?  The two
> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
> >
> >
> > Pasting the console output below for those interested:
> >
> >
> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> > starting...
> > POST: 0x34
> > BSP Family_Model: 00500f20
> > cpu_init_detectedx = 00000000
> > POST: 0x35
> > agesawrapper_amdinitmmio passed.
> > POST: 0x37
> > agesawrapper_amdinitreset passed.
> > POST: 0x39
> > agesawrapper_amdinitearly POST: 0x34
> > BSP Family_Model: 00500f20
> > cpu_init_detectedx = 00000001
> > POST: 0x35
> > agesawrapper_amdinitmmio passed.
> > POST: 0x37
> > agesawrapper_amdinitreset passed.
> > POST: 0x39
> > agesawrapper_amdinitearly passed.
> > SLP_TYP type was 0
> > POST: 0x40
> > agesawrapper_amdinitpost
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> >
> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >           Param1 = a00a, Param2 = 0.
> >           Param3 = 0, Param4 = 0.
> > SLP_TYP type was 0
> > error level: 4
> > POST: 0x42
> > agesawrapper_amdinitenv SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > passed.
> > POST: 0x43
> > POST: 0x44
> > POST: 0x50
> > Loading image.
> > CBFS: Looking for 'fallback/coreboot_ram'
> > CBFS: found.
> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> > entry @ 0x200000
> > Jumping to image.
> > POST: 0x80
> > POST: 0x39
> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> > booting...
> > POST: 0x40
> > Enumerating buses...
> > Show all devs...Before device enumeration.
> > Root Device: enabled 1
> > APIC_CLUSTER: 0: enabled 1
> > APIC: 00: enabled 1
> > PCI_DOMAIN: 0000: enabled 1
> > PCI: 00:00.0: enabled 1
> > PCI: 00:01.0: enabled 1
> > PCI: 00:01.1: enabled 1
> > PCI: 00:04.0: enabled 1
> > PCI: 00:05.0: enabled 0
> > PCI: 00:06.0: enabled 0
> > PCI: 00:07.0: enabled 0
> > PCI: 00:08.0: enabled 0
> > PCI: 00:11.0: enabled 1
> > PCI: 00:12.0: enabled 1
> > PCI: 00:12.1: enabled 1
> > PCI: 00:12.2: enabled 1
> > PCI: 00:13.0: enabled 1
> > PCI: 00:13.1: enabled 1
> > PCI: 00:13.2: enabled 1
> > PCI: 00:14.0: enabled 1
> > I2C: 00:50: enabled 1
> > I2C: 00:51: enabled 1
> > PCI: 00:14.1: enabled 1
> > PCI: 00:14.2: enabled 1
> > PCI: 00:14.3: enabled 1
> > PNP: 004e.0: enabled 0
> > PNP: 004e.3: enabled 0
> > PNP: 004e.4: enabled 0
> > PNP: 004e.5: enabled 1
> > PNP: 004e.6: enabled 0
> > PNP: 004e.a: enabled 0
> > PNP: 004e.10: enabled 1
> > PNP: 004e.11: enabled 0
> > PCI: 00:14.4: enabled 1
> > PCI: 00:14.5: enabled 1
> > PCI: 00:15.0: enabled 0
> > PCI: 00:15.1: enabled 0
> > PCI: 00:15.2: enabled 0
> > PCI: 00:15.3: enabled 0
> > PCI: 00:16.0: enabled 0
> > PCI: 00:16.2: enabled 0
> > PCI: 00:18.0: enabled 1
> > PCI: 00:18.1: enabled 1
> > PCI: 00:18.2: enabled 1
> > PCI: 00:18.3: enabled 1
> > PCI: 00:18.4: enabled 1
> > PCI: 00:18.5: enabled 1
> > PCI: 00:18.6: enabled 1
> > PCI: 00:18.7: enabled 1
> > Compare with tree...
> > Root Device: enabled 1
> >  APIC_CLUSTER: 0: enabled 1
> >   APIC: 00: enabled 1
> >  PCI_DOMAIN: 0000: enabled 1
> >   PCI: 00:00.0: enabled 1
> >   PCI: 00:01.0: enabled 1
> >   PCI: 00:01.1: enabled 1
> >   PCI: 00:04.0: enabled 1
> >   PCI: 00:05.0: enabled 0
> >   PCI: 00:06.0: enabled 0
> >   PCI: 00:07.0: enabled 0
> >   PCI: 00:08.0: enabled 0
> >   PCI: 00:11.0: enabled 1
> >   PCI: 00:12.0: enabled 1
> >   PCI: 00:12.1: enabled 1
> >   PCI: 00:12.2: enabled 1
> >   PCI: 00:13.0: enabled 1
> >   PCI: 00:13.1: enabled 1
> >   PCI: 00:13.2: enabled 1
> >   PCI: 00:14.0: enabled 1
> >    I2C: 00:50: enabled 1
> >    I2C: 00:51: enabled 1
> >   PCI: 00:14.1: enabled 1
> >   PCI: 00:14.2: enabled 1
> >   PCI: 00:14.3: enabled 1
> >    PNP: 004e.0: enabled 0
> >    PNP: 004e.3: enabled 0
> >    PNP: 004e.4: enabled 0
> >    PNP: 004e.5: enabled 1
> >    PNP: 004e.6: enabled 0
> >    PNP: 004e.a: enabled 0
> >    PNP: 004e.10: enabled 1
> >    PNP: 004e.11: enabled 0
> >   PCI: 00:14.4: enabled 1
> >   PCI: 00:14.5: enabled 1
> >   PCI: 00:15.0: enabled 0
> >   PCI: 00:15.1: enabled 0
> >   PCI: 00:15.2: enabled 0
> >   PCI: 00:15.3: enabled 0
> >   PCI: 00:16.0: enabled 0
> >   PCI: 00:16.2: enabled 0
> >   PCI: 00:18.0: enabled 1
> >   PCI: 00:18.1: enabled 1
> >   PCI: 00:18.2: enabled 1
> >   PCI: 00:18.3: enabled 1
> >   PCI: 00:18.4: enabled 1
> >   PCI: 00:18.5: enabled 1
> >   PCI: 00:18.6: enabled 1
> >   PCI: 00:18.7: enabled 1
> > Mainboard Persimmon Enable.
> > SLP_TYP type was 0
> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
> > 0x00000000
> > persimmon_enable: uma size 0x18000000, memory start 0x67000000
> > scan_static_bus for Root Device
> > APIC_CLUSTER: 0 enabled
> > PCI_DOMAIN: 0000 enabled
> > APIC_CLUSTER: 0 scanning...
> >   AP siblings=1
> > CPU: APIC: 00 enabled
> > CPU: APIC: 01 enabled
> > PCI_DOMAIN: 0000 scanning...
> > PCI: pci_scan_bus for bus 00
> > POST: 0x24
> > PCI: 00:00.0 [1022/1510] ops
> > PCI: 00:00.0 [1022/1510] enabled
> > PCI: 00:01.0 [1002/9804] enabled
> > Capability: type 0x01 @ 0x50
> > Capability: type 0x10 @ 0x58
> > Capability: type 0x05 @ 0xa0
> > Capability: type 0x0d @ 0xb0
> > Capability: type 0x08 @ 0xb8
> > Capability: type 0x01 @ 0x50
> > Capability: type 0x10 @ 0x58
> > PCI: 00:04.0 subordinate bus PCI Express
> > PCI: 00:04.0 [1022/1512] enabled
> > sb800_enable() SLP_TYP type was 0
> > PCI: 00:11.0 [1002/4393] ops
> > PCI: 00:11.0 [1002/4393] enabled
> > sb800_enable() PCI: 00:12.0 [1002/4397] ops
> > PCI: 00:12.0 [1002/4397] enabled
> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
> > it.
> > sb800_enable() PCI: 00:12.2 [1002/4396] ops
> > PCI: 00:12.2 [1002/4396] enabled
> > sb800_enable() PCI: 00:13.0 [1002/4397] ops
> > PCI: 00:13.0 [1002/4397] enabled
> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
> > it.
> > sb800_enable() PCI: 00:13.2 [1002/4396] ops
> > PCI: 00:13.2 [1002/4396] enabled
> > sb800_enable() sm_init().
> > IOAPIC: Clearing IOAPIC at 0xfec00000
> > IOAPIC: 23 interrupts
> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> > IOAPIC: Initializing IOAPIC at 0xfec00000
> > IOAPIC: Bootstrap Processor Local APIC = 0x00
> > IOAPIC: ID = 0x02
> > IOAPIC: 23 interrupts
> > IOAPIC: Enabling interrupts on FSB
> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> > PCI: 00:14.0 [1002/4385] enabled
> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
> > it.
> > sb800_enable() hda enabled
> > PCI: 00:14.2 [1002/4383] ops
> > PCI: 00:14.2 [1002/4383] enabled
> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> > PCI: 00:14.3 [1002/439d] enabled
> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> > PCI: 00:14.4 [1002/4384] enabled
> > sb800_enable() PCI: 00:14.5 [1002/4399] ops
> > PCI: 00:14.5 [1002/4399] enabled
> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> > PCI: 00:18.1 [1022/1701] enabled
> > PCI: 00:18.2 [1022/1702] enabled
> > PCI: 00:18.3 [1022/1703] enabled
> > PCI: 00:18.4 [1022/1704] enabled
> > PCI: 00:18.5 [1022/1718] enabled
> > PCI: 00:18.6 [1022/1716] enabled
> > PCI: 00:18.7 [1022/1719] enabled
> > POST: 0x25
> > PCI: Left over static devices:
> > PCI: 00:01.1
> > PCI: Check your devicetree.cb.
> > do_pci_scan_bridge for PCI: 00:04.0
> > PCI: pci_scan_bus for bus 01
> > POST: 0x24
> > PCI: 01:00.0 [10ec/8168] enabled
> > POST: 0x25
> > PCI: pci_scan_bus returning with max=001
> > POST: 0x55
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
>
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From gerrit at coreboot.org  Sat Jun  9 13:11:38 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 9 Jun 2012 13:11:38 +0200
Subject: [coreboot] Patch merged into coreboot/master: b2d5bd2 libpayload:
	Fix an integer overflow in USB mass storage
References: <I3d618497016478ea727c520e866d27dbc3ebf9af+0@gerrit.coreboot.org>
Message-ID: <E1SdJZy-0000BF-2o@ra.coresystems.de>

the following patch was just integrated into master:
commit b2d5bd239402dd8410fdab99fcee678e24ab9308
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 13:59:43 2012 +0200

    libpayload: Fix an integer overflow in USB mass storage
    
    Change-Id: I3d618497016478ea727c520e866d27dbc3ebf9af
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jun  9 13:11:35 2012, giving +2
See http://review.coreboot.org/1070 for details.

-gerrit



From gerrit at coreboot.org  Sat Jun  9 13:13:15 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 9 Jun 2012 13:13:15 +0200
Subject: [coreboot] Patch merged into coreboot/master: 2541489 libpayload:
	Add timeouts in the UHCI USB driver
References: <Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de+0@gerrit.coreboot.org>
Message-ID: <E1SdJbX-0000Qd-OI@ra.coresystems.de>

the following patch was just integrated into master:
commit 2541489b34e3a5d1fa4a96fdd4dfd7bcbaa92ac5
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon May 21 14:23:03 2012 +0200

    libpayload: Add timeouts in the UHCI USB driver
    
    We should always have some timeout when we wait for the hardware. This adds
    missing timeouts to the UHCI driver.
    
    Change-Id: Ic37b95ce12ff3ff5efe3e7ca346090946f6ee7de
    Signed-off-by: Nico Huber <nico.huber at secunet.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Jun  9 13:12:58 2012, giving +2
See http://review.coreboot.org/1073 for details.

-gerrit



From kevin at koconnor.net  Sat Jun  9 15:43:45 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 9 Jun 2012 09:43:45 -0400
Subject: [coreboot] VGA Option ROM
In-Reply-To: <CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
Message-ID: <20120609134345.GA22994@morn.localdomain>

On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote:
> I wonder if we need another option :-( to configure the rom but not run it?

Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but
CONFIG_VGA_ROM_RUN is not?

-Kevin



From shekairui at gmail.com  Sat Jun  9 20:10:43 2012
From: shekairui at gmail.com (She Kairui)
Date: Sun, 10 Jun 2012 02:10:43 +0800
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JV9U6kvhnOf4mDBw-nwosZdq5BPDRG=gE9PjLzk=2ffaA@mail.gmail.com>
References: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>
	<2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>
	<CAHgS8JV9U6kvhnOf4mDBw-nwosZdq5BPDRG=gE9PjLzk=2ffaA@mail.gmail.com>
Message-ID: <CAMZA15fo8=+jBv7ryPVThaXF-g=2r3Kb_5Umze3yWBN-b_knzw@mail.gmail.com>

2012/6/9, Andy Sharp <andywyse6 at gmail.com>:
> It's a persimmon board ~:^)
>
> I'd be happy to test any patches.  Meanwhile, I'm working on a patch to
> properly enable the southbridge PCIe devices so they can be scanned.
>  Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those
> PCIe ports happens after the bus is scanned.  When nothing shows up on the
> bus scan, the code powers down those devices right after it [too late]
> powers them up.  Broken.
>
> This persimmon board is made by iBASE. and is a mini-ITX.  It has a  PCIe
> slot and a mini-PCIe card socket on the sb800 PCIe ports.
I have a persimmon Rev. D board, I found NONE of the PCIe devices is
from SB800 GPP.
You can double check it by booting from the factory BIOS.
Thanks

--
Kerry Sheh
>  I may have earlier said that it had a USB3 ctlr, that was my bad.  So many twisty
> passages....
>
> I'll try out various combinations of the various patches you good folks
> have been throwing my way, plus some of my own ideas and let the list know
> what happens.
>
> Cheers,
>
> a
>
>
>
> On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave at se-eng.com> wrote:
>
>> There shouldn't be any need to guess if it is a Persimmon. On a
>> Persimmon board, next to the SATA connectors there should be
>> printing that says "DB FT1".
>>
>> The Persimmon can also have up to two PCIe Ethernet chips on it.
>>
>> dave
>>
>> ----- Original Message -----
>> > From: "Zheng Bao" <Zheng.Bao at amd.com>
>> > To: "Andy Sharp" <andywyse6 at gmail.com>
>> > Cc: "coreboot at coreboot.org" <coreboot at coreboot.org>
>> > Sent: Friday, June 8, 2012 5:37:58 AM
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Hi, Andy,
>> > The persimmon board I have got doesn't have any PCIe slot or onboard
>> > PCIe device attached to SB800. And I am wondering if you actually
>> > use a inagua board, which has the same APU & SB with persimmon and 2
>> > minipcie slots other than that.
>> >
>> > Let us assume you are testing on Inagua.
>> > Here is my patch for the PCIe on SB800. There was a bug. It is just a
>> > workaround patch, not ready for submitting.
>> >
>> > This patch can fix the sb800/pcie issue on Inagua. If you have your
>> > work based on persimmon, please note the devicetree.cb should be
>> > modify as Inagua.
>> > The dev15func[0123] should be enabled and the gpp_configuration
>> > should be 4.
>> >
>> > Joe
>> >
>> > diff --git a/src/southbridge/amd/cimx/sb800/late.c
>> > b/src/southbridge/amd/cimx/sb800/late.c
>> > index 0ce82b3..34cd937 100644
>> > --- a/src/southbridge/amd/cimx/sb800/late.c
>> > +++ b/src/southbridge/amd/cimx/sb800/late.c
>> > @@ -29,6 +29,7 @@
>> >  #include "SBPLATFORM.h"      /* Platfrom Specific Definitions */
>> >  #include "cfg.h"             /* sb800 Cimx configuration */
>> >  #include "chip.h"            /* struct
>> southbridge_amd_cimx_sb800_config */
>> > +#include "smbus.h"
>> >  #include "sb_cimx.h"         /* AMD CIMX wrapper entries */
>> >
>> >
>> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
>> >          .set_resources = pci_dev_set_resources,
>> >          .enable_resources = pci_bus_enable_resources,
>> >          .init = pci_init,
>> > +        .enable = 0,
>> >          .scan_bus = pci_scan_bridge,
>> >          .reset_bus = pci_bus_reset,
>> >          .ops_pci = &lops_pci,
>> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
>> >       .reset_bus        = pci_bus_reset,
>> >       .ops_pci          = &lops_pci,
>> >  };
>> > -
>> > +#if 0
>> >  /* 0:15:0 PCIe PortA */
>> >  static const struct pci_driver PORTA_driver __pci_driver = {
>> >          .ops = &bridge_ops,
>> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
>> > __pci_driver = {
>> >          .vendor = PCI_VENDOR_ID_ATI,
>> >          .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
>> >  };
>> > -
>> > +#endif
>> >
>> >  /**
>> >   * South Bridge CIMx ramstage entry point wrapper.
>> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
>> >       switch (dev->path.pci.devfn) {
>> >       case (0x11 << 3) | 0: /* 0:11.0  SATA */
>> >               /* the first sb800 device */
>> > +             abcfg_reg(0xc0, 0x1FF, 0x0F4);
>> >               sb800_cimx_config(sb_config);
>> >
>> >               if (dev->enabled) {
>> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
>> >                       sb_config->GppLinkConfig =
>> sb_chip->gpp_configuration;
>> >               }
>> >               break;
>> > +     case (0x15 << 3) | 1:
>> > +     case (0x15 << 3) | 2:
>> > +     case (0x15 << 3) | 3:
>> > +             //abcfg_reg(0xc0, 0xF0, 0x00);
>> > +             break;
>> >
>> >       case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
>> >               sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
>> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
>> >               /* call the CIMX entry at the last sb800 device,
>> >                * so make sure the mainboard devicetree is complete
>> >                */
>> > +             abcfg_reg(0xc0, 0x100, 0x100);
>> >  #if CONFIG_HAVE_ACPI_RESUME
>> >               if (acpi_slp_type != 3)
>> >                       sb_Before_Pci_Init();
>> >
>> >
>> >
>> >
>> > From: coreboot-bounces at coreboot.org
>> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
>> > Sent: Friday, June 08, 2012 8:57 AM
>> > To: coreboot at coreboot.org
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Hi Steve,
>> >
>> > Makes no [substantive] difference.   All that does is cause 4 extra
>> > lines to be added to the console output:
>> >
>> > .
>> > .
>> > .
>> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
>> > it.
>> > .
>> > .
>> > .
>> >
>> >
>> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
>> > <steve.goodrich at se-eng.com> wrote:
>> > ARG.. Thanks, Outlook.  :P
>> >
>> > Andy,
>> >
>> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
>> > folder.  Mine shows:
>> >
>> >             device pci 15.0 off end # PCIe PortA
>> >             device pci 15.1 off end # PCIe PortB
>> >             device pci 15.2 off end # PCIe PortC
>> >             device pci 15.3 off end # PCIe PortD
>> >
>> > I'm not 100% certain, but I suspect that changing these from "off" to
>> > "on" will enable the devices.  Try the change and see if the console
>> > output starts reflecting the devices you're looking for.
>> >
>> >             -- Steve G.
>> >
>> >
>> >
>> > From: coreboot-bounces at coreboot.org
>> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
>> > Sent: Thursday, June 07, 2012 2:31 PM
>> > To: coreboot at coreboot.org
>> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Howdy,
>> >
>> > I've got an AMD/persimmon board, with the agesa family 14 northbridge
>> > on the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on
>> > them, but coreboot isn't enabling or enumerating any of the PCIe
>> > devices on the SB800.  Does anyone have any ideas for me?  The two
>> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
>> >
>> >
>> > Pasting the console output below for those interested:
>> >
>> >
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>> > starting...
>> > POST: 0x34
>> > BSP Family_Model: 00500f20
>> > cpu_init_detectedx = 00000000
>> > POST: 0x35
>> > agesawrapper_amdinitmmio passed.
>> > POST: 0x37
>> > agesawrapper_amdinitreset passed.
>> > POST: 0x39
>> > agesawrapper_amdinitearly POST: 0x34
>> > BSP Family_Model: 00500f20
>> > cpu_init_detectedx = 00000001
>> > POST: 0x35
>> > agesawrapper_amdinitmmio passed.
>> > POST: 0x37
>> > agesawrapper_amdinitreset passed.
>> > POST: 0x39
>> > agesawrapper_amdinitearly passed.
>> > SLP_TYP type was 0
>> > POST: 0x40
>> > agesawrapper_amdinitpost
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> > SLP_TYP type was 0
>> > error level: 4
>> > POST: 0x42
>> > agesawrapper_amdinitenv SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > passed.
>> > POST: 0x43
>> > POST: 0x44
>> > POST: 0x50
>> > Loading image.
>> > CBFS: Looking for 'fallback/coreboot_ram'
>> > CBFS: found.
>> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
>> > entry @ 0x200000
>> > Jumping to image.
>> > POST: 0x80
>> > POST: 0x39
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>> > booting...
>> > POST: 0x40
>> > Enumerating buses...
>> > Show all devs...Before device enumeration.
>> > Root Device: enabled 1
>> > APIC_CLUSTER: 0: enabled 1
>> > APIC: 00: enabled 1
>> > PCI_DOMAIN: 0000: enabled 1
>> > PCI: 00:00.0: enabled 1
>> > PCI: 00:01.0: enabled 1
>> > PCI: 00:01.1: enabled 1
>> > PCI: 00:04.0: enabled 1
>> > PCI: 00:05.0: enabled 0
>> > PCI: 00:06.0: enabled 0
>> > PCI: 00:07.0: enabled 0
>> > PCI: 00:08.0: enabled 0
>> > PCI: 00:11.0: enabled 1
>> > PCI: 00:12.0: enabled 1
>> > PCI: 00:12.1: enabled 1
>> > PCI: 00:12.2: enabled 1
>> > PCI: 00:13.0: enabled 1
>> > PCI: 00:13.1: enabled 1
>> > PCI: 00:13.2: enabled 1
>> > PCI: 00:14.0: enabled 1
>> > I2C: 00:50: enabled 1
>> > I2C: 00:51: enabled 1
>> > PCI: 00:14.1: enabled 1
>> > PCI: 00:14.2: enabled 1
>> > PCI: 00:14.3: enabled 1
>> > PNP: 004e.0: enabled 0
>> > PNP: 004e.3: enabled 0
>> > PNP: 004e.4: enabled 0
>> > PNP: 004e.5: enabled 1
>> > PNP: 004e.6: enabled 0
>> > PNP: 004e.a: enabled 0
>> > PNP: 004e.10: enabled 1
>> > PNP: 004e.11: enabled 0
>> > PCI: 00:14.4: enabled 1
>> > PCI: 00:14.5: enabled 1
>> > PCI: 00:15.0: enabled 0
>> > PCI: 00:15.1: enabled 0
>> > PCI: 00:15.2: enabled 0
>> > PCI: 00:15.3: enabled 0
>> > PCI: 00:16.0: enabled 0
>> > PCI: 00:16.2: enabled 0
>> > PCI: 00:18.0: enabled 1
>> > PCI: 00:18.1: enabled 1
>> > PCI: 00:18.2: enabled 1
>> > PCI: 00:18.3: enabled 1
>> > PCI: 00:18.4: enabled 1
>> > PCI: 00:18.5: enabled 1
>> > PCI: 00:18.6: enabled 1
>> > PCI: 00:18.7: enabled 1
>> > Compare with tree...
>> > Root Device: enabled 1
>> >  APIC_CLUSTER: 0: enabled 1
>> >   APIC: 00: enabled 1
>> >  PCI_DOMAIN: 0000: enabled 1
>> >   PCI: 00:00.0: enabled 1
>> >   PCI: 00:01.0: enabled 1
>> >   PCI: 00:01.1: enabled 1
>> >   PCI: 00:04.0: enabled 1
>> >   PCI: 00:05.0: enabled 0
>> >   PCI: 00:06.0: enabled 0
>> >   PCI: 00:07.0: enabled 0
>> >   PCI: 00:08.0: enabled 0
>> >   PCI: 00:11.0: enabled 1
>> >   PCI: 00:12.0: enabled 1
>> >   PCI: 00:12.1: enabled 1
>> >   PCI: 00:12.2: enabled 1
>> >   PCI: 00:13.0: enabled 1
>> >   PCI: 00:13.1: enabled 1
>> >   PCI: 00:13.2: enabled 1
>> >   PCI: 00:14.0: enabled 1
>> >    I2C: 00:50: enabled 1
>> >    I2C: 00:51: enabled 1
>> >   PCI: 00:14.1: enabled 1
>> >   PCI: 00:14.2: enabled 1
>> >   PCI: 00:14.3: enabled 1
>> >    PNP: 004e.0: enabled 0
>> >    PNP: 004e.3: enabled 0
>> >    PNP: 004e.4: enabled 0
>> >    PNP: 004e.5: enabled 1
>> >    PNP: 004e.6: enabled 0
>> >    PNP: 004e.a: enabled 0
>> >    PNP: 004e.10: enabled 1
>> >    PNP: 004e.11: enabled 0
>> >   PCI: 00:14.4: enabled 1
>> >   PCI: 00:14.5: enabled 1
>> >   PCI: 00:15.0: enabled 0
>> >   PCI: 00:15.1: enabled 0
>> >   PCI: 00:15.2: enabled 0
>> >   PCI: 00:15.3: enabled 0
>> >   PCI: 00:16.0: enabled 0
>> >   PCI: 00:16.2: enabled 0
>> >   PCI: 00:18.0: enabled 1
>> >   PCI: 00:18.1: enabled 1
>> >   PCI: 00:18.2: enabled 1
>> >   PCI: 00:18.3: enabled 1
>> >   PCI: 00:18.4: enabled 1
>> >   PCI: 00:18.5: enabled 1
>> >   PCI: 00:18.6: enabled 1
>> >   PCI: 00:18.7: enabled 1
>> > Mainboard Persimmon Enable.
>> > SLP_TYP type was 0
>> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
>> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
>> > 0x00000000
>> > persimmon_enable: uma size 0x18000000, memory start 0x67000000
>> > scan_static_bus for Root Device
>> > APIC_CLUSTER: 0 enabled
>> > PCI_DOMAIN: 0000 enabled
>> > APIC_CLUSTER: 0 scanning...
>> >   AP siblings=1
>> > CPU: APIC: 00 enabled
>> > CPU: APIC: 01 enabled
>> > PCI_DOMAIN: 0000 scanning...
>> > PCI: pci_scan_bus for bus 00
>> > POST: 0x24
>> > PCI: 00:00.0 [1022/1510] ops
>> > PCI: 00:00.0 [1022/1510] enabled
>> > PCI: 00:01.0 [1002/9804] enabled
>> > Capability: type 0x01 @ 0x50
>> > Capability: type 0x10 @ 0x58
>> > Capability: type 0x05 @ 0xa0
>> > Capability: type 0x0d @ 0xb0
>> > Capability: type 0x08 @ 0xb8
>> > Capability: type 0x01 @ 0x50
>> > Capability: type 0x10 @ 0x58
>> > PCI: 00:04.0 subordinate bus PCI Express
>> > PCI: 00:04.0 [1022/1512] enabled
>> > sb800_enable() SLP_TYP type was 0
>> > PCI: 00:11.0 [1002/4393] ops
>> > PCI: 00:11.0 [1002/4393] enabled
>> > sb800_enable() PCI: 00:12.0 [1002/4397] ops
>> > PCI: 00:12.0 [1002/4397] enabled
>> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: 00:12.2 [1002/4396] ops
>> > PCI: 00:12.2 [1002/4396] enabled
>> > sb800_enable() PCI: 00:13.0 [1002/4397] ops
>> > PCI: 00:13.0 [1002/4397] enabled
>> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: 00:13.2 [1002/4396] ops
>> > PCI: 00:13.2 [1002/4396] enabled
>> > sb800_enable() sm_init().
>> > IOAPIC: Clearing IOAPIC at 0xfec00000
>> > IOAPIC: 23 interrupts
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
>> > IOAPIC: Initializing IOAPIC at 0xfec00000
>> > IOAPIC: Bootstrap Processor Local APIC = 0x00
>> > IOAPIC: ID = 0x02
>> > IOAPIC: 23 interrupts
>> > IOAPIC: Enabling interrupts on FSB
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
>> > PCI: 00:14.0 [1002/4385] enabled
>> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
>> > it.
>> > sb800_enable() hda enabled
>> > PCI: 00:14.2 [1002/4383] ops
>> > PCI: 00:14.2 [1002/4383] enabled
>> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
>> > PCI: 00:14.3 [1002/439d] enabled
>> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
>> > PCI: 00:14.4 [1002/4384] enabled
>> > sb800_enable() PCI: 00:14.5 [1002/4399] ops
>> > PCI: 00:14.5 [1002/4399] enabled
>> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()
>> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
>> > PCI: 00:18.1 [1022/1701] enabled
>> > PCI: 00:18.2 [1022/1702] enabled
>> > PCI: 00:18.3 [1022/1703] enabled
>> > PCI: 00:18.4 [1022/1704] enabled
>> > PCI: 00:18.5 [1022/1718] enabled
>> > PCI: 00:18.6 [1022/1716] enabled
>> > PCI: 00:18.7 [1022/1719] enabled
>> > POST: 0x25
>> > PCI: Left over static devices:
>> > PCI: 00:01.1
>> > PCI: Check your devicetree.cb.
>> > do_pci_scan_bridge for PCI: 00:04.0
>> > PCI: pci_scan_bus for bus 01
>> > POST: 0x24
>> > PCI: 01:00.0 [10ec/8168] enabled
>> > POST: 0x25
>> > PCI: pci_scan_bus returning with max=001
>> > POST: 0x55
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>> >
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>>
>



From wangqingpei at gmail.com  Sat Jun  9 20:48:15 2012
From: wangqingpei at gmail.com (QingPei Wang)
Date: Sun, 10 Jun 2012 02:48:15 +0800
Subject: [coreboot] VGA Option ROM
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DD118F245@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DD118F245@DATAKAMPONE.datakamp2008.local>
Message-ID: <CADuV8k79=3YGsFX8X3pXUJhaeTAJ045s4FcMC_2H-xU7ujU+mw@mail.gmail.com>

 what does "seabios cannot run the vga option ROM" looks like?
did seabios find the vbios from CBFS?
1. found, but vbios executed failed?
2. seabios could not find vbios?



Best wishes
QingPei Wang
Phone: 86+018930528086


On Fri, Jun 8, 2012 at 11:42 PM, Wolfgang Kamp - datakamp <
wmkamp at datakamp.de> wrote:

> Normally seabios should run the option ROMs. But in my issue seabios
> cannot run the vga option ROM,
> because it cannot find the vga pci device.
> Seabios first looks for the vga pci device and if it finds a vga device it
> searches in CBFS for the correct ROM file.
> So I think there is a pci enumeration problem which seems to be caused
> from coreboot.
>
> Wolfgang
>
> -----Urspr?ngliche Nachricht-----
> Von: ron minnich [mailto:rminnich at gmail.com]
> Gesendet: Freitag, 8. Juni 2012 17:16
> An: Wolfgang Kamp - datakamp
> Cc: coreboot at coreboot.org
> Betreff: Re: [coreboot] VGA Option ROM
>
> I wonder if we need another option :-( to configure the rom but not run it?
>
> ron
>
>
>
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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From wmkamp at datakamp.de  Sat Jun  9 21:17:34 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Sat, 9 Jun 2012 21:17:34 +0200
Subject: [coreboot] VGA Option ROM
In-Reply-To: <CADuV8k79=3YGsFX8X3pXUJhaeTAJ045s4FcMC_2H-xU7ujU+mw@mail.gmail.com>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CADuV8k79=3YGsFX8X3pXUJhaeTAJ045s4FcMC_2H-xU7ujU+mw@mail.gmail.com>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F246@DATAKAMPONE.datakamp2008.local>

Hi,

When execution of VGA option ROM is configured in seabios,
seabios first scans all PCI devices and looks for a vga type device as you can see in my  attached log.
If seabios finds a pci vga device then it looks for a suitable VGA BIOS (Vendor id:Device id / 1002:9804) in CBFS.
But if seabios does not find a vga device, it doesn't look for the VGA BIOS. That is what happens.
In my issue seabios can only find the pci VGA device if I first enabled VGA ROM execution in coreboot.
If seabios finds the vga device it will also find the correct VGA BIOS in CBFS and executes it.
The log shows this. The issue is that the pci enumertion fails in seabios and it does not list all available devices.
Why is it broken? It could be a coreboot or seabios problem.

Regards

Wolfgang



Von: QingPei Wang [mailto:wangqingpei at gmail.com]
Gesendet: Samstag, 9. Juni 2012 20:48
An: Wolfgang Kamp - datakamp
Cc: Coreboot
Betreff: Re: [coreboot] VGA Option ROM

 what does "seabios cannot run the vga option ROM" looks like?
did seabios find the vbios from CBFS?
1. found, but vbios executed failed?
2. seabios could not find vbios?



Best wishes
QingPei Wang
Phone: 86+018930528086

On Fri, Jun 8, 2012 at 11:42 PM, Wolfgang Kamp - datakamp <wmkamp at datakamp.de<mailto:wmkamp at datakamp.de>> wrote:
Normally seabios should run the option ROMs. But in my issue seabios cannot run the vga option ROM,
because it cannot find the vga pci device.
Seabios first looks for the vga pci device and if it finds a vga device it searches in CBFS for the correct ROM file.
So I think there is a pci enumeration problem which seems to be caused from coreboot.

Wolfgang

-----Urspr?ngliche Nachricht-----
Von: ron minnich [mailto:rminnich at gmail.com<mailto:rminnich at gmail.com>]
Gesendet: Freitag, 8. Juni 2012 17:16
An: Wolfgang Kamp - datakamp
Cc: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
Betreff: Re: [coreboot] VGA Option ROM

I wonder if we need another option :-( to configure the rom but not run it?

ron




--
coreboot mailing list: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
http://www.coreboot.org/mailman/listinfo/coreboot

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From oliver+list at schinagl.nl  Sat Jun  9 21:18:54 2012
From: oliver+list at schinagl.nl (Oliver Schinagl)
Date: Sat, 09 Jun 2012 21:18:54 +0200
Subject: [coreboot] Boots from PCI add-on card on Intel ICHs
In-Reply-To: <1338020139.2284.599.camel@obelix>
References: <1337502187.2284.250.camel@obelix>
	<1338020139.2284.599.camel@obelix>
Message-ID: <4FD3A19E.3060801@schinagl.nl>

Having been quite intrigued by this I coincidentally found an old raid 
controller of mine.

http://www.highpoint-tech.cn/USA/rr454.htm

Though it only has 64kb flash I'm guessing (the bios image is about 55k) 
after a swap of that chip, it may theoretically be possible, correct?
Hi all,

So why would this only work on ICH based boards? What are changes of 
this working on older chipsets other then intel? Say VIA?

Oliver

On 26-05-12 10:15, Ky?sti M?lkki wrote:
> On Sun, 2012-05-20 at 11:23 +0300, Ky?sti M?lkki wrote:
>> Hi
>>
>> I did not find this method of bypassing the mainboard flash chip and
>> booting from PCI add-on card documented or discussed before. The nice
>> think in this is that neither mainboard or its flash needs to be
>> modified. Good news in the case of a soldered flash and this method may
>> work with mini-PCI slots on laptops too.
>>
>> For pre-ICH6 the key is in subtractive PCI decode. This has been
>> supported in 82801 chipset from the early days and is briefly documented
>> in ICH3 datasheet [1], see 5.1.1. PCI Bus interface. This decode mode is
>> on by default and there is no documentation of a hw bootstrap that could
>> disable it.
> Above is not accurate, ICH6 has hardware bootstrap.
>
>> For ICH7 onwards there are HW bootstraps to select between LPC/SPI/PCI.
>> If you don't know where the bootstraps are, go with SPI and forget about
>> this PCI add-on boot.
> The bootstrap is latched on power cycle, but not PCI reset, and the
> config bit is writeable. So if one has a booting system it should be
> possible to switch to PCI add-on for next reboot. The setting will
> default back to mainboard flash after power-cycle.
>
> Note that "hard/cold" reboot is required to toggle the PCI RST#. If
> vendor BIOS does set the write-protection lock bit, it should be cleared
> on PCI RST#. At least for ICH4 that is the case.
>
> Ky?sti
>
>




From stefan.reinauer at coreboot.org  Sat Jun  9 23:21:50 2012
From: stefan.reinauer at coreboot.org (Stefan Reinauer)
Date: Sat, 09 Jun 2012 14:21:50 -0700
Subject: [coreboot] VGA Option ROM
In-Reply-To: <20120609134345.GA22994@morn.localdomain>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
	<20120609134345.GA22994@morn.localdomain>
Message-ID: <4FD3BE6E.7060408@coreboot.org>

On 6/9/12 6:43 AM, Kevin O'Connor wrote:
> On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote:
>> I wonder if we need another option :-( to configure the rom but not run it?
> Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but
> CONFIG_VGA_ROM_RUN is not?
>
> -Kevin
>
CONFIG_VGA_BRIDGE_SETUP routes VGA legacy IO through the (PCI) bridge 
with the VGA card attached. It does not influence option rom handling.

Stefan



From oliverlist at schinagl.nl  Sat Jun  9 18:13:40 2012
From: oliverlist at schinagl.nl (Oliver Schinagl)
Date: Sat, 09 Jun 2012 18:13:40 +0200
Subject: [coreboot] Boots from PCI add-on card on Intel ICHs
In-Reply-To: <1338020139.2284.599.camel@obelix>
References: <1337502187.2284.250.camel@obelix>
	<1338020139.2284.599.camel@obelix>
Message-ID: <4FD37634.8080308@schinagl.nl>

Having been quite intrigued by this I coincidentally found an old raid 
controller of mine.

http://www.highpoint-tech.cn/USA/rr454.htm

Though it only has 64kb flash I'm guessing (the bios image is about 55k) 
after a swap of that chip, it may theoretically be possible, correct?
Hi all,

So why would this only work on ICH based boards? What are changes of 
this working on older chipsets other then intel? Say VIA?

Oliver

On 26-05-12 10:15, Ky?sti M?lkki wrote:
> On Sun, 2012-05-20 at 11:23 +0300, Ky?sti M?lkki wrote:
>> Hi
>>
>> I did not find this method of bypassing the mainboard flash chip and
>> booting from PCI add-on card documented or discussed before. The nice
>> think in this is that neither mainboard or its flash needs to be
>> modified. Good news in the case of a soldered flash and this method may
>> work with mini-PCI slots on laptops too.
>>
>> For pre-ICH6 the key is in subtractive PCI decode. This has been
>> supported in 82801 chipset from the early days and is briefly documented
>> in ICH3 datasheet [1], see 5.1.1. PCI Bus interface. This decode mode is
>> on by default and there is no documentation of a hw bootstrap that could
>> disable it.
> Above is not accurate, ICH6 has hardware bootstrap.
>
>> For ICH7 onwards there are HW bootstraps to select between LPC/SPI/PCI.
>> If you don't know where the bootstraps are, go with SPI and forget about
>> this PCI add-on boot.
> The bootstrap is latched on power cycle, but not PCI reset, and the
> config bit is writeable. So if one has a booting system it should be
> possible to switch to PCI add-on for next reboot. The setting will
> default back to mainboard flash after power-cycle.
>
> Note that "hard/cold" reboot is required to toggle the PCI RST#. If
> vendor BIOS does set the write-protection lock bit, it should be cleared
> on PCI RST#. At least for ICH4 that is the case.
>
> Ky?sti
>
>




From kevin at koconnor.net  Sun Jun 10 02:34:42 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Sat, 9 Jun 2012 20:34:42 -0400
Subject: [coreboot] VGA Option ROM
In-Reply-To: <4738C8CE0A30FF47AACA9C624746E3E20DD118F246@DATAKAMPONE.datakamp2008.local>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CADuV8k79=3YGsFX8X3pXUJhaeTAJ045s4FcMC_2H-xU7ujU+mw@mail.gmail.com>
	<4738C8CE0A30FF47AACA9C624746E3E20DD118F246@DATAKAMPONE.datakamp2008.local>
Message-ID: <20120610003442.GA10680@morn.localdomain>

On Sat, Jun 09, 2012 at 09:17:34PM +0200, Wolfgang Kamp - datakamp wrote:
> Hi,
> 
> When execution of VGA option ROM is configured in seabios,
> seabios first scans all PCI devices and looks for a vga type device as you can see in my  attached log.
> If seabios finds a pci vga device then it looks for a suitable VGA BIOS (Vendor id:Device id / 1002:9804) in CBFS.
> But if seabios does not find a vga device, it doesn't look for the VGA BIOS. That is what happens.
> In my issue seabios can only find the pci VGA device if I first enabled VGA ROM execution in coreboot.
> If seabios finds the vga device it will also find the correct VGA BIOS in CBFS and executes it.
> The log shows this. The issue is that the pci enumertion fails in seabios and it does not list all available devices.
> Why is it broken? It could be a coreboot or seabios problem.

Looks like a coreboot issue to me.  The PCI device does not appear to
be present when SeaBIOS doesn't find it.  As Ron indicated in another
email, it looks like coreboot needs an option to enable the vga but
not run the rom for your board.

-Kevin



From kyosti.malkki at gmail.com  Sun Jun 10 06:54:24 2012
From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=)
Date: Sun, 10 Jun 2012 07:54:24 +0300
Subject: [coreboot] Boots from PCI add-on card on Intel ICHs
In-Reply-To: <4FD37634.8080308@schinagl.nl>
References: <1337502187.2284.250.camel@obelix>
	<1338020139.2284.599.camel@obelix>  <4FD37634.8080308@schinagl.nl>
Message-ID: <1339304064.10509.124.camel@obelix>

On Sat, 2012-06-09 at 18:13 +0200, Oliver Schinagl wrote:
> Having been quite intrigued by this I coincidentally found an old raid 
> controller of mine.
> 
> http://www.highpoint-tech.cn/USA/rr454.htm
> 
> Though it only has 64kb flash I'm guessing (the bios image is about 55k) 
> after a swap of that chip, it may theoretically be possible, correct?
> Hi all,
> 
> So why would this only work on ICH based boards? What are changes of 
> this working on older chipsets other then intel? Say VIA?
> 
> Oliver

Hi

64 kB is enough for SerialICE. I would first check the raid controller
datasheet and PCB if you have more than 16 address lines in the first
place. 

Chances are there was something similar on most PCI chipsets, as it was
one practical method for production-line programming in the case of
soldered flash chips. Just don't expect that the possible hardware
bootstrap is labeled or easily accessible on the mainboard.

Ky?sti




From gerrit at coreboot.org  Sun Jun 10 19:05:29 2012
From: gerrit at coreboot.org (Sven Schnelle (svens@stackframe.org))
Date: Sun, 10 Jun 2012 19:05:29 +0200
Subject: [coreboot] New patch to review for coreboot: bd563e6 udelay: add
	missing bus frequency
References: <Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6+0@gerrit.coreboot.org>
Message-ID: <Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6+1@gerrit.coreboot.org>

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1099

-gerrit

commit bd563e66681569f8b010f43a2289aa9d82537ec3
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 10 19:03:36 2012 +0200

    udelay: add missing bus frequency
    
    commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
    detection on Sandybridge") reworked the udelay code, but didn't add
    the 333MHz FSB entry used on Model 15 Xeons.
    
    Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/cpu/x86/lapic/apic_timer.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index bb6cca7..a4106d4 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -34,7 +34,7 @@ static int set_timer_fsb(void)
 {
 	struct cpuinfo_x86 c;
 	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
-	int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 };
 
 	get_fms(&c, cpuid_eax(1));
 	if (c.x86 != 6)
@@ -45,7 +45,7 @@ static int set_timer_fsb(void)
 	case 0x1c: /* Atom */
 		timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
 		break;
-	case 0xf:  /* Core 2*/
+	case 0xf:  /* Core 2 or Xeon */
 	case 0x17: /* Enhanced Core */
 		timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
 		break;



From svn at coreboot.org  Mon Jun 11 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 11 Jun 2012 16:00:01 +0200
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1Se5A1-0004gY-QY@ra.coresystems.de>

An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20120611/76a83d66/attachment.html>

From andywyse6 at gmail.com  Mon Jun 11 20:57:57 2012
From: andywyse6 at gmail.com (Andy Sharp)
Date: Mon, 11 Jun 2012 11:57:57 -0700
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAMZA15fo8=+jBv7ryPVThaXF-g=2r3Kb_5Umze3yWBN-b_knzw@mail.gmail.com>
References: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>
	<2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>
	<CAHgS8JV9U6kvhnOf4mDBw-nwosZdq5BPDRG=gE9PjLzk=2ffaA@mail.gmail.com>
	<CAMZA15fo8=+jBv7ryPVThaXF-g=2r3Kb_5Umze3yWBN-b_knzw@mail.gmail.com>
Message-ID: <CAHgS8JVNX5i_wh1yojxB9aYFywZj1z5XTCcyttSp9pkXdL5UgA@mail.gmail.com>

I can now confirm this.  Despite the hardware documentation for the board
clearly showing the PCIe slot as being on the south bridge, it is not.  I
got a PCIe extension cable this morning that would actually fit, and the
device plugged in shows to be a child of device 6.0, which is the third
PCIe port on the northbridge/cpu.  Sigh.

This is a big bummer for me, as my employer has a design based on
persimmon, except all the devices are on the southbridge instead of the
northbridge, and we are struggling to get coreboot to see them and yet not
hang.  I know it can be done, because the BIOS does enable all the devices
and boots, so it's just coreboot that isn't quite getting it right.

Cheers,

a


On Sat, Jun 9, 2012 at 11:10 AM, She Kairui <shekairui at gmail.com> wrote:

> 2012/6/9, Andy Sharp <andywyse6 at gmail.com>:
> > It's a persimmon board ~:^)
> >
> > I'd be happy to test any patches.  Meanwhile, I'm working on a patch to
> > properly enable the southbridge PCIe devices so they can be scanned.
> >  Wolfgang (Wolfie?) is quite correct, the code that enables/deresets
> those
> > PCIe ports happens after the bus is scanned.  When nothing shows up on
> the
> > bus scan, the code powers down those devices right after it [too late]
> > powers them up.  Broken.
> >
> > This persimmon board is made by iBASE. and is a mini-ITX.  It has a  PCIe
> > slot and a mini-PCIe card socket on the sb800 PCIe ports.
> I have a persimmon Rev. D board, I found NONE of the PCIe devices is
> from SB800 GPP.
> You can double check it by booting from the factory BIOS.
> Thanks
>
> --
> Kerry Sheh
> >  I may have earlier said that it had a USB3 ctlr, that was my bad.  So
> many twisty
> > passages....
> >
> > I'll try out various combinations of the various patches you good folks
> > have been throwing my way, plus some of my own ideas and let the list
> know
> > what happens.
> >
> > Cheers,
> >
> > a
> >
> >
> >
> > On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave at se-eng.com> wrote:
> >
> >> There shouldn't be any need to guess if it is a Persimmon. On a
> >> Persimmon board, next to the SATA connectors there should be
> >> printing that says "DB FT1".
> >>
> >> The Persimmon can also have up to two PCIe Ethernet chips on it.
> >>
> >> dave
> >>
> >> ----- Original Message -----
> >> > From: "Zheng Bao" <Zheng.Bao at amd.com>
> >> > To: "Andy Sharp" <andywyse6 at gmail.com>
> >> > Cc: "coreboot at coreboot.org" <coreboot at coreboot.org>
> >> > Sent: Friday, June 8, 2012 5:37:58 AM
> >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >> >
> >> > Hi, Andy,
> >> > The persimmon board I have got doesn't have any PCIe slot or onboard
> >> > PCIe device attached to SB800. And I am wondering if you actually
> >> > use a inagua board, which has the same APU & SB with persimmon and 2
> >> > minipcie slots other than that.
> >> >
> >> > Let us assume you are testing on Inagua.
> >> > Here is my patch for the PCIe on SB800. There was a bug. It is just a
> >> > workaround patch, not ready for submitting.
> >> >
> >> > This patch can fix the sb800/pcie issue on Inagua. If you have your
> >> > work based on persimmon, please note the devicetree.cb should be
> >> > modify as Inagua.
> >> > The dev15func[0123] should be enabled and the gpp_configuration
> >> > should be 4.
> >> >
> >> > Joe
> >> >
> >> > diff --git a/src/southbridge/amd/cimx/sb800/late.c
> >> > b/src/southbridge/amd/cimx/sb800/late.c
> >> > index 0ce82b3..34cd937 100644
> >> > --- a/src/southbridge/amd/cimx/sb800/late.c
> >> > +++ b/src/southbridge/amd/cimx/sb800/late.c
> >> > @@ -29,6 +29,7 @@
> >> >  #include "SBPLATFORM.h"      /* Platfrom Specific Definitions */
> >> >  #include "cfg.h"             /* sb800 Cimx configuration */
> >> >  #include "chip.h"            /* struct
> >> southbridge_amd_cimx_sb800_config */
> >> > +#include "smbus.h"
> >> >  #include "sb_cimx.h"         /* AMD CIMX wrapper entries */
> >> >
> >> >
> >> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
> >> >          .set_resources = pci_dev_set_resources,
> >> >          .enable_resources = pci_bus_enable_resources,
> >> >          .init = pci_init,
> >> > +        .enable = 0,
> >> >          .scan_bus = pci_scan_bridge,
> >> >          .reset_bus = pci_bus_reset,
> >> >          .ops_pci = &lops_pci,
> >> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
> >> >       .reset_bus        = pci_bus_reset,
> >> >       .ops_pci          = &lops_pci,
> >> >  };
> >> > -
> >> > +#if 0
> >> >  /* 0:15:0 PCIe PortA */
> >> >  static const struct pci_driver PORTA_driver __pci_driver = {
> >> >          .ops = &bridge_ops,
> >> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
> >> > __pci_driver = {
> >> >          .vendor = PCI_VENDOR_ID_ATI,
> >> >          .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
> >> >  };
> >> > -
> >> > +#endif
> >> >
> >> >  /**
> >> >   * South Bridge CIMx ramstage entry point wrapper.
> >> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
> >> >       switch (dev->path.pci.devfn) {
> >> >       case (0x11 << 3) | 0: /* 0:11.0  SATA */
> >> >               /* the first sb800 device */
> >> > +             abcfg_reg(0xc0, 0x1FF, 0x0F4);
> >> >               sb800_cimx_config(sb_config);
> >> >
> >> >               if (dev->enabled) {
> >> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
> >> >                       sb_config->GppLinkConfig =
> >> sb_chip->gpp_configuration;
> >> >               }
> >> >               break;
> >> > +     case (0x15 << 3) | 1:
> >> > +     case (0x15 << 3) | 2:
> >> > +     case (0x15 << 3) | 3:
> >> > +             //abcfg_reg(0xc0, 0xF0, 0x00);
> >> > +             break;
> >> >
> >> >       case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
> >> >               sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
> >> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
> >> >               /* call the CIMX entry at the last sb800 device,
> >> >                * so make sure the mainboard devicetree is complete
> >> >                */
> >> > +             abcfg_reg(0xc0, 0x100, 0x100);
> >> >  #if CONFIG_HAVE_ACPI_RESUME
> >> >               if (acpi_slp_type != 3)
> >> >                       sb_Before_Pci_Init();
> >> >
> >> >
> >> >
> >> >
> >> > From: coreboot-bounces at coreboot.org
> >> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> >> > Sent: Friday, June 08, 2012 8:57 AM
> >> > To: coreboot at coreboot.org
> >> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >> >
> >> > Hi Steve,
> >> >
> >> > Makes no [substantive] difference.   All that does is cause 4 extra
> >> > lines to be added to the console output:
> >> >
> >> > .
> >> > .
> >> > .
> >> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
> >> > it.
> >> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
> >> > it.
> >> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
> >> > it.
> >> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
> >> > it.
> >> > .
> >> > .
> >> > .
> >> >
> >> >
> >> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
> >> > <steve.goodrich at se-eng.com> wrote:
> >> > ARG.. Thanks, Outlook.  :P
> >> >
> >> > Andy,
> >> >
> >> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
> >> > folder.  Mine shows:
> >> >
> >> >             device pci 15.0 off end # PCIe PortA
> >> >             device pci 15.1 off end # PCIe PortB
> >> >             device pci 15.2 off end # PCIe PortC
> >> >             device pci 15.3 off end # PCIe PortD
> >> >
> >> > I'm not 100% certain, but I suspect that changing these from "off" to
> >> > "on" will enable the devices.  Try the change and see if the console
> >> > output starts reflecting the devices you're looking for.
> >> >
> >> >             -- Steve G.
> >> >
> >> >
> >> >
> >> > From: coreboot-bounces at coreboot.org
> >> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> >> > Sent: Thursday, June 07, 2012 2:31 PM
> >> > To: coreboot at coreboot.org
> >> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon
> >> >
> >> > Howdy,
> >> >
> >> > I've got an AMD/persimmon board, with the agesa family 14 northbridge
> >> > on the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on
> >> > them, but coreboot isn't enabling or enumerating any of the PCIe
> >> > devices on the SB800.  Does anyone have any ideas for me?  The two
> >> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
> >> >
> >> >
> >> > Pasting the console output below for those interested:
> >> >
> >> >
> >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> >> > starting...
> >> > POST: 0x34
> >> > BSP Family_Model: 00500f20
> >> > cpu_init_detectedx = 00000000
> >> > POST: 0x35
> >> > agesawrapper_amdinitmmio passed.
> >> > POST: 0x37
> >> > agesawrapper_amdinitreset passed.
> >> > POST: 0x39
> >> > agesawrapper_amdinitearly POST: 0x34
> >> > BSP Family_Model: 00500f20
> >> > cpu_init_detectedx = 00000001
> >> > POST: 0x35
> >> > agesawrapper_amdinitmmio passed.
> >> > POST: 0x37
> >> > agesawrapper_amdinitreset passed.
> >> > POST: 0x39
> >> > agesawrapper_amdinitearly passed.
> >> > SLP_TYP type was 0
> >> > POST: 0x40
> >> > agesawrapper_amdinitpost
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> >
> >> > EventLog:     EventClass = 2, EventInfo = 8040100.
> >> >           Param1 = a00a, Param2 = 0.
> >> >           Param3 = 0, Param4 = 0.
> >> > SLP_TYP type was 0
> >> > error level: 4
> >> > POST: 0x42
> >> > agesawrapper_amdinitenv SLP_TYP type was 0
> >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> >> > SLP_TYP type was 0
> >> > SLP_TYP type was 0
> >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> >> > SLP_TYP type was 0
> >> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> >> > SLP_TYP type was 0
> >> > SLP_TYP type was 0
> >> > SLP_TYP type was 0
> >> > passed.
> >> > POST: 0x43
> >> > POST: 0x44
> >> > POST: 0x50
> >> > Loading image.
> >> > CBFS: Looking for 'fallback/coreboot_ram'
> >> > CBFS: found.
> >> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> >> > entry @ 0x200000
> >> > Jumping to image.
> >> > POST: 0x80
> >> > POST: 0x39
> >> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> >> > booting...
> >> > POST: 0x40
> >> > Enumerating buses...
> >> > Show all devs...Before device enumeration.
> >> > Root Device: enabled 1
> >> > APIC_CLUSTER: 0: enabled 1
> >> > APIC: 00: enabled 1
> >> > PCI_DOMAIN: 0000: enabled 1
> >> > PCI: 00:00.0: enabled 1
> >> > PCI: 00:01.0: enabled 1
> >> > PCI: 00:01.1: enabled 1
> >> > PCI: 00:04.0: enabled 1
> >> > PCI: 00:05.0: enabled 0
> >> > PCI: 00:06.0: enabled 0
> >> > PCI: 00:07.0: enabled 0
> >> > PCI: 00:08.0: enabled 0
> >> > PCI: 00:11.0: enabled 1
> >> > PCI: 00:12.0: enabled 1
> >> > PCI: 00:12.1: enabled 1
> >> > PCI: 00:12.2: enabled 1
> >> > PCI: 00:13.0: enabled 1
> >> > PCI: 00:13.1: enabled 1
> >> > PCI: 00:13.2: enabled 1
> >> > PCI: 00:14.0: enabled 1
> >> > I2C: 00:50: enabled 1
> >> > I2C: 00:51: enabled 1
> >> > PCI: 00:14.1: enabled 1
> >> > PCI: 00:14.2: enabled 1
> >> > PCI: 00:14.3: enabled 1
> >> > PNP: 004e.0: enabled 0
> >> > PNP: 004e.3: enabled 0
> >> > PNP: 004e.4: enabled 0
> >> > PNP: 004e.5: enabled 1
> >> > PNP: 004e.6: enabled 0
> >> > PNP: 004e.a: enabled 0
> >> > PNP: 004e.10: enabled 1
> >> > PNP: 004e.11: enabled 0
> >> > PCI: 00:14.4: enabled 1
> >> > PCI: 00:14.5: enabled 1
> >> > PCI: 00:15.0: enabled 0
> >> > PCI: 00:15.1: enabled 0
> >> > PCI: 00:15.2: enabled 0
> >> > PCI: 00:15.3: enabled 0
> >> > PCI: 00:16.0: enabled 0
> >> > PCI: 00:16.2: enabled 0
> >> > PCI: 00:18.0: enabled 1
> >> > PCI: 00:18.1: enabled 1
> >> > PCI: 00:18.2: enabled 1
> >> > PCI: 00:18.3: enabled 1
> >> > PCI: 00:18.4: enabled 1
> >> > PCI: 00:18.5: enabled 1
> >> > PCI: 00:18.6: enabled 1
> >> > PCI: 00:18.7: enabled 1
> >> > Compare with tree...
> >> > Root Device: enabled 1
> >> >  APIC_CLUSTER: 0: enabled 1
> >> >   APIC: 00: enabled 1
> >> >  PCI_DOMAIN: 0000: enabled 1
> >> >   PCI: 00:00.0: enabled 1
> >> >   PCI: 00:01.0: enabled 1
> >> >   PCI: 00:01.1: enabled 1
> >> >   PCI: 00:04.0: enabled 1
> >> >   PCI: 00:05.0: enabled 0
> >> >   PCI: 00:06.0: enabled 0
> >> >   PCI: 00:07.0: enabled 0
> >> >   PCI: 00:08.0: enabled 0
> >> >   PCI: 00:11.0: enabled 1
> >> >   PCI: 00:12.0: enabled 1
> >> >   PCI: 00:12.1: enabled 1
> >> >   PCI: 00:12.2: enabled 1
> >> >   PCI: 00:13.0: enabled 1
> >> >   PCI: 00:13.1: enabled 1
> >> >   PCI: 00:13.2: enabled 1
> >> >   PCI: 00:14.0: enabled 1
> >> >    I2C: 00:50: enabled 1
> >> >    I2C: 00:51: enabled 1
> >> >   PCI: 00:14.1: enabled 1
> >> >   PCI: 00:14.2: enabled 1
> >> >   PCI: 00:14.3: enabled 1
> >> >    PNP: 004e.0: enabled 0
> >> >    PNP: 004e.3: enabled 0
> >> >    PNP: 004e.4: enabled 0
> >> >    PNP: 004e.5: enabled 1
> >> >    PNP: 004e.6: enabled 0
> >> >    PNP: 004e.a: enabled 0
> >> >    PNP: 004e.10: enabled 1
> >> >    PNP: 004e.11: enabled 0
> >> >   PCI: 00:14.4: enabled 1
> >> >   PCI: 00:14.5: enabled 1
> >> >   PCI: 00:15.0: enabled 0
> >> >   PCI: 00:15.1: enabled 0
> >> >   PCI: 00:15.2: enabled 0
> >> >   PCI: 00:15.3: enabled 0
> >> >   PCI: 00:16.0: enabled 0
> >> >   PCI: 00:16.2: enabled 0
> >> >   PCI: 00:18.0: enabled 1
> >> >   PCI: 00:18.1: enabled 1
> >> >   PCI: 00:18.2: enabled 1
> >> >   PCI: 00:18.3: enabled 1
> >> >   PCI: 00:18.4: enabled 1
> >> >   PCI: 00:18.5: enabled 1
> >> >   PCI: 00:18.6: enabled 1
> >> >   PCI: 00:18.7: enabled 1
> >> > Mainboard Persimmon Enable.
> >> > SLP_TYP type was 0
> >> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> >> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
> >> > 0x00000000
> >> > persimmon_enable: uma size 0x18000000, memory start 0x67000000
> >> > scan_static_bus for Root Device
> >> > APIC_CLUSTER: 0 enabled
> >> > PCI_DOMAIN: 0000 enabled
> >> > APIC_CLUSTER: 0 scanning...
> >> >   AP siblings=1
> >> > CPU: APIC: 00 enabled
> >> > CPU: APIC: 01 enabled
> >> > PCI_DOMAIN: 0000 scanning...
> >> > PCI: pci_scan_bus for bus 00
> >> > POST: 0x24
> >> > PCI: 00:00.0 [1022/1510] ops
> >> > PCI: 00:00.0 [1022/1510] enabled
> >> > PCI: 00:01.0 [1002/9804] enabled
> >> > Capability: type 0x01 @ 0x50
> >> > Capability: type 0x10 @ 0x58
> >> > Capability: type 0x05 @ 0xa0
> >> > Capability: type 0x0d @ 0xb0
> >> > Capability: type 0x08 @ 0xb8
> >> > Capability: type 0x01 @ 0x50
> >> > Capability: type 0x10 @ 0x58
> >> > PCI: 00:04.0 subordinate bus PCI Express
> >> > PCI: 00:04.0 [1022/1512] enabled
> >> > sb800_enable() SLP_TYP type was 0
> >> > PCI: 00:11.0 [1002/4393] ops
> >> > PCI: 00:11.0 [1002/4393] enabled
> >> > sb800_enable() PCI: 00:12.0 [1002/4397] ops
> >> > PCI: 00:12.0 [1002/4397] enabled
> >> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
> >> > it.
> >> > sb800_enable() PCI: 00:12.2 [1002/4396] ops
> >> > PCI: 00:12.2 [1002/4396] enabled
> >> > sb800_enable() PCI: 00:13.0 [1002/4397] ops
> >> > PCI: 00:13.0 [1002/4397] enabled
> >> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
> >> > it.
> >> > sb800_enable() PCI: 00:13.2 [1002/4396] ops
> >> > PCI: 00:13.2 [1002/4396] enabled
> >> > sb800_enable() sm_init().
> >> > IOAPIC: Clearing IOAPIC at 0xfec00000
> >> > IOAPIC: 23 interrupts
> >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> >> > IOAPIC: Initializing IOAPIC at 0xfec00000
> >> > IOAPIC: Bootstrap Processor Local APIC = 0x00
> >> > IOAPIC: ID = 0x02
> >> > IOAPIC: 23 interrupts
> >> > IOAPIC: Enabling interrupts on FSB
> >> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> >> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> >> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> >> > PCI: 00:14.0 [1002/4385] enabled
> >> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
> >> > it.
> >> > sb800_enable() hda enabled
> >> > PCI: 00:14.2 [1002/4383] ops
> >> > PCI: 00:14.2 [1002/4383] enabled
> >> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> >> > PCI: 00:14.3 [1002/439d] enabled
> >> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> >> > PCI: 00:14.4 [1002/4384] enabled
> >> > sb800_enable() PCI: 00:14.5 [1002/4399] ops
> >> > PCI: 00:14.5 [1002/4399] enabled
> >> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> >> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> >> > PCI: 00:18.1 [1022/1701] enabled
> >> > PCI: 00:18.2 [1022/1702] enabled
> >> > PCI: 00:18.3 [1022/1703] enabled
> >> > PCI: 00:18.4 [1022/1704] enabled
> >> > PCI: 00:18.5 [1022/1718] enabled
> >> > PCI: 00:18.6 [1022/1716] enabled
> >> > PCI: 00:18.7 [1022/1719] enabled
> >> > POST: 0x25
> >> > PCI: Left over static devices:
> >> > PCI: 00:01.1
> >> > PCI: Check your devicetree.cb.
> >> > do_pci_scan_bridge for PCI: 00:04.0
> >> > PCI: pci_scan_bus for bus 01
> >> > POST: 0x24
> >> > PCI: 01:00.0 [10ec/8168] enabled
> >> > POST: 0x25
> >> > PCI: pci_scan_bus returning with max=001
> >> > POST: 0x55
> >> >
> >> > --
> >> > coreboot mailing list: coreboot at coreboot.org
> >> > http://www.coreboot.org/mailman/listinfo/coreboot
> >> >
> >> >
> >> > --
> >> > coreboot mailing list: coreboot at coreboot.org
> >> > http://www.coreboot.org/mailman/listinfo/coreboot
> >>
> >
>
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From kevin at koconnor.net  Tue Jun 12 03:34:59 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Mon, 11 Jun 2012 21:34:59 -0400
Subject: [coreboot] VGA Option ROM
In-Reply-To: <4FD3BE6E.7060408@coreboot.org>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<CAP6exYLv3Vxwtrtk5h4SAytB38Bb23_utuxYeXJuXsqGtcnBmw@mail.gmail.com>
	<20120609134345.GA22994@morn.localdomain>
	<4FD3BE6E.7060408@coreboot.org>
Message-ID: <20120612013459.GA32217@morn.localdomain>

On Sat, Jun 09, 2012 at 02:21:50PM -0700, Stefan Reinauer wrote:
> On 6/9/12 6:43 AM, Kevin O'Connor wrote:
> >On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote:
> >>I wonder if we need another option :-( to configure the rom but not run it?
> >Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but
> >CONFIG_VGA_ROM_RUN is not?
> >
> >-Kevin
> >
> CONFIG_VGA_BRIDGE_SETUP routes VGA legacy IO through the (PCI)
> bridge with the VGA card attached. It does not influence option rom
> handling.

Right.  Wolfgang is reporting that his VGA card isn't mapped at all if
he doesn't select CONFIG_VGA_ROM_RUN (it doesn't show up as a PCI
device at all).  It should get mapped even if CONFIG_VGA_ROM_RUN isn't
set.

-Kevin



From Zheng.Bao at amd.com  Tue Jun 12 04:05:40 2012
From: Zheng.Bao at amd.com (Bao, Zheng)
Date: Tue, 12 Jun 2012 02:05:40 +0000
Subject: [coreboot] PCIe devices not enabled on amd/persimmon
In-Reply-To: <CAHgS8JVNX5i_wh1yojxB9aYFywZj1z5XTCcyttSp9pkXdL5UgA@mail.gmail.com>
References: <9190E42A2EF0E146B3940E1FFAD11C37028C0F2A@SCYBEXDAG01.amd.com>
	<2a8fe2c4-a54b-4547-aeac-73d1059483ab@judge>
	<CAHgS8JV9U6kvhnOf4mDBw-nwosZdq5BPDRG=gE9PjLzk=2ffaA@mail.gmail.com>
	<CAMZA15fo8=+jBv7ryPVThaXF-g=2r3Kb_5Umze3yWBN-b_knzw@mail.gmail.com>
	<CAHgS8JVNX5i_wh1yojxB9aYFywZj1z5XTCcyttSp9pkXdL5UgA@mail.gmail.com>
Message-ID: <9190E42A2EF0E146B3940E1FFAD11C37028CDE2B@SCYBEXDAG01.amd.com>

Don't worry.
If the hardware is ok, you can try my last patch which was sent to list and CC to you. I am pretty sure it can work.

Joe

From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
Sent: Tuesday, June 12, 2012 2:58 AM
To: She Kairui
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon

I can now confirm this.  Despite the hardware documentation for the board clearly showing the PCIe slot as being on the south bridge, it is not.  I got a PCIe extension cable this morning that would actually fit, and the device plugged in shows to be a child of device 6.0, which is the third PCIe port on the northbridge/cpu.  Sigh.

This is a big bummer for me, as my employer has a design based on persimmon, except all the devices are on the southbridge instead of the northbridge, and we are struggling to get coreboot to see them and yet not hang.  I know it can be done, because the BIOS does enable all the devices and boots, so it's just coreboot that isn't quite getting it right.

Cheers,

a

On Sat, Jun 9, 2012 at 11:10 AM, She Kairui <shekairui at gmail.com<mailto:shekairui at gmail.com>> wrote:
2012/6/9, Andy Sharp <andywyse6 at gmail.com<mailto:andywyse6 at gmail.com>>:
> It's a persimmon board ~:^)
>
> I'd be happy to test any patches.  Meanwhile, I'm working on a patch to
> properly enable the southbridge PCIe devices so they can be scanned.
>  Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those
> PCIe ports happens after the bus is scanned.  When nothing shows up on the
> bus scan, the code powers down those devices right after it [too late]
> powers them up.  Broken.
>
> This persimmon board is made by iBASE. and is a mini-ITX.  It has a  PCIe
> slot and a mini-PCIe card socket on the sb800 PCIe ports.
I have a persimmon Rev. D board, I found NONE of the PCIe devices is
from SB800 GPP.
You can double check it by booting from the factory BIOS.
Thanks

--
Kerry Sheh
>  I may have earlier said that it had a USB3 ctlr, that was my bad.  So many twisty
> passages....
>
> I'll try out various combinations of the various patches you good folks
> have been throwing my way, plus some of my own ideas and let the list know
> what happens.
>
> Cheers,
>
> a
>
>
>
> On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave at se-eng.com<mailto:dave at se-eng.com>> wrote:
>
>> There shouldn't be any need to guess if it is a Persimmon. On a
>> Persimmon board, next to the SATA connectors there should be
>> printing that says "DB FT1".
>>
>> The Persimmon can also have up to two PCIe Ethernet chips on it.
>>
>> dave
>>
>> ----- Original Message -----
>> > From: "Zheng Bao" <Zheng.Bao at amd.com<mailto:Zheng.Bao at amd.com>>
>> > To: "Andy Sharp" <andywyse6 at gmail.com<mailto:andywyse6 at gmail.com>>
>> > Cc: "coreboot at coreboot.org<mailto:coreboot at coreboot.org>" <coreboot at coreboot.org<mailto:coreboot at coreboot.org>>
>> > Sent: Friday, June 8, 2012 5:37:58 AM
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Hi, Andy,
>> > The persimmon board I have got doesn't have any PCIe slot or onboard
>> > PCIe device attached to SB800. And I am wondering if you actually
>> > use a inagua board, which has the same APU & SB with persimmon and 2
>> > minipcie slots other than that.
>> >
>> > Let us assume you are testing on Inagua.
>> > Here is my patch for the PCIe on SB800. There was a bug. It is just a
>> > workaround patch, not ready for submitting.
>> >
>> > This patch can fix the sb800/pcie issue on Inagua. If you have your
>> > work based on persimmon, please note the devicetree.cb should be
>> > modify as Inagua.
>> > The dev15func[0123] should be enabled and the gpp_configuration
>> > should be 4.
>> >
>> > Joe
>> >
>> > diff --git a/src/southbridge/amd/cimx/sb800/late.c
>> > b/src/southbridge/amd/cimx/sb800/late.c
>> > index 0ce82b3..34cd937 100644
>> > --- a/src/southbridge/amd/cimx/sb800/late.c
>> > +++ b/src/southbridge/amd/cimx/sb800/late.c
>> > @@ -29,6 +29,7 @@
>> >  #include "SBPLATFORM.h"      /* Platfrom Specific Definitions */
>> >  #include "cfg.h"             /* sb800 Cimx configuration */
>> >  #include "chip.h"            /* struct
>> southbridge_amd_cimx_sb800_config */
>> > +#include "smbus.h"
>> >  #include "sb_cimx.h"         /* AMD CIMX wrapper entries */
>> >
>> >
>> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
>> >          .set_resources = pci_dev_set_resources,
>> >          .enable_resources = pci_bus_enable_resources,
>> >          .init = pci_init,
>> > +        .enable = 0,
>> >          .scan_bus = pci_scan_bridge,
>> >          .reset_bus = pci_bus_reset,
>> >          .ops_pci = &lops_pci,
>> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
>> >       .reset_bus        = pci_bus_reset,
>> >       .ops_pci          = &lops_pci,
>> >  };
>> > -
>> > +#if 0
>> >  /* 0:15:0 PCIe PortA */
>> >  static const struct pci_driver PORTA_driver __pci_driver = {
>> >          .ops = &bridge_ops,
>> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
>> > __pci_driver = {
>> >          .vendor = PCI_VENDOR_ID_ATI,
>> >          .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
>> >  };
>> > -
>> > +#endif
>> >
>> >  /**
>> >   * South Bridge CIMx ramstage entry point wrapper.
>> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
>> >       switch (dev->path.pci.devfn) {
>> >       case (0x11 << 3) | 0: /* 0:11.0  SATA */
>> >               /* the first sb800 device */
>> > +             abcfg_reg(0xc0, 0x1FF, 0x0F4);
>> >               sb800_cimx_config(sb_config);
>> >
>> >               if (dev->enabled) {
>> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
>> >                       sb_config->GppLinkConfig =
>> sb_chip->gpp_configuration;
>> >               }
>> >               break;
>> > +     case (0x15 << 3) | 1:
>> > +     case (0x15 << 3) | 2:
>> > +     case (0x15 << 3) | 3:
>> > +             //abcfg_reg(0xc0, 0xF0, 0x00);
>> > +             break;
>> >
>> >       case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
>> >               sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
>> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
>> >               /* call the CIMX entry at the last sb800 device,
>> >                * so make sure the mainboard devicetree is complete
>> >                */
>> > +             abcfg_reg(0xc0, 0x100, 0x100);
>> >  #if CONFIG_HAVE_ACPI_RESUME
>> >               if (acpi_slp_type != 3)
>> >                       sb_Before_Pci_Init();
>> >
>> >
>> >
>> >
>> > From: coreboot-bounces at coreboot.org<mailto:coreboot-bounces at coreboot.org>
>> > [mailto:coreboot-bounces at coreboot.org<mailto:coreboot-bounces at coreboot.org>] On Behalf Of Andy Sharp
>> > Sent: Friday, June 08, 2012 8:57 AM
>> > To: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
>> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Hi Steve,
>> >
>> > Makes no [substantive] difference.   All that does is cause 4 extra
>> > lines to be added to the console output:
>> >
>> > .
>> > .
>> > .
>> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
>> > it.
>> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
>> > it.
>> > .
>> > .
>> > .
>> >
>> >
>> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
>> > <steve.goodrich at se-eng.com<mailto:steve.goodrich at se-eng.com>> wrote:
>> > ARG.. Thanks, Outlook.  :P
>> >
>> > Andy,
>> >
>> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
>> > folder.  Mine shows:
>> >
>> >             device pci 15.0 off end # PCIe PortA
>> >             device pci 15.1 off end # PCIe PortB
>> >             device pci 15.2 off end # PCIe PortC
>> >             device pci 15.3 off end # PCIe PortD
>> >
>> > I'm not 100% certain, but I suspect that changing these from "off" to
>> > "on" will enable the devices.  Try the change and see if the console
>> > output starts reflecting the devices you're looking for.
>> >
>> >             -- Steve G.
>> >
>> >
>> >
>> > From: coreboot-bounces at coreboot.org<mailto:coreboot-bounces at coreboot.org>
>> > [mailto:coreboot-bounces at coreboot.org<mailto:coreboot-bounces at coreboot.org>] On Behalf Of Andy Sharp
>> > Sent: Thursday, June 07, 2012 2:31 PM
>> > To: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
>> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon
>> >
>> > Howdy,
>> >
>> > I've got an AMD/persimmon board, with the agesa family 14 northbridge
>> > on the CPU, and the SB800 southbridge.  Both have 4 PCIe ports on
>> > them, but coreboot isn't enabling or enumerating any of the PCIe
>> > devices on the SB800.  Does anyone have any ideas for me?  The two
>> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
>> >
>> >
>> > Pasting the console output below for those interested:
>> >
>> >
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>> > starting...
>> > POST: 0x34
>> > BSP Family_Model: 00500f20
>> > cpu_init_detectedx = 00000000
>> > POST: 0x35
>> > agesawrapper_amdinitmmio passed.
>> > POST: 0x37
>> > agesawrapper_amdinitreset passed.
>> > POST: 0x39
>> > agesawrapper_amdinitearly POST: 0x34
>> > BSP Family_Model: 00500f20
>> > cpu_init_detectedx = 00000001
>> > POST: 0x35
>> > agesawrapper_amdinitmmio passed.
>> > POST: 0x37
>> > agesawrapper_amdinitreset passed.
>> > POST: 0x39
>> > agesawrapper_amdinitearly passed.
>> > SLP_TYP type was 0
>> > POST: 0x40
>> > agesawrapper_amdinitpost
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> >
>> > EventLog:     EventClass = 2, EventInfo = 8040100.
>> >           Param1 = a00a, Param2 = 0.
>> >           Param3 = 0, Param4 = 0.
>> > SLP_TYP type was 0
>> > error level: 4
>> > POST: 0x42
>> > agesawrapper_amdinitenv SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > SLP_TYP type was 0
>> > passed.
>> > POST: 0x43
>> > POST: 0x44
>> > POST: 0x50
>> > Loading image.
>> > CBFS: Looking for 'fallback/coreboot_ram'
>> > CBFS: found.
>> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
>> > entry @ 0x200000
>> > Jumping to image.
>> > POST: 0x80
>> > POST: 0x39
>> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
>> > booting...
>> > POST: 0x40
>> > Enumerating buses...
>> > Show all devs...Before device enumeration.
>> > Root Device: enabled 1
>> > APIC_CLUSTER: 0: enabled 1
>> > APIC: 00: enabled 1
>> > PCI_DOMAIN: 0000: enabled 1
>> > PCI: 00:00.0: enabled 1
>> > PCI: 00:01.0: enabled 1
>> > PCI: 00:01.1: enabled 1
>> > PCI: 00:04.0: enabled 1
>> > PCI: 00:05.0: enabled 0
>> > PCI: 00:06.0: enabled 0
>> > PCI: 00:07.0: enabled 0
>> > PCI: 00:08.0: enabled 0
>> > PCI: 00:11.0: enabled 1
>> > PCI: 00:12.0: enabled 1
>> > PCI: 00:12.1: enabled 1
>> > PCI: 00:12.2: enabled 1
>> > PCI: 00:13.0: enabled 1
>> > PCI: 00:13.1: enabled 1
>> > PCI: 00:13.2: enabled 1
>> > PCI: 00:14.0: enabled 1
>> > I2C: 00:50: enabled 1
>> > I2C: 00:51: enabled 1
>> > PCI: 00:14.1: enabled 1
>> > PCI: 00:14.2: enabled 1
>> > PCI: 00:14.3: enabled 1
>> > PNP: 004e.0: enabled 0
>> > PNP: 004e.3: enabled 0
>> > PNP: 004e.4: enabled 0
>> > PNP: 004e.5: enabled 1
>> > PNP: 004e.6: enabled 0
>> > PNP: 004e.a: enabled 0
>> > PNP: 004e.10: enabled 1
>> > PNP: 004e.11: enabled 0
>> > PCI: 00:14.4: enabled 1
>> > PCI: 00:14.5: enabled 1
>> > PCI: 00:15.0: enabled 0
>> > PCI: 00:15.1: enabled 0
>> > PCI: 00:15.2: enabled 0
>> > PCI: 00:15.3: enabled 0
>> > PCI: 00:16.0: enabled 0
>> > PCI: 00:16.2: enabled 0
>> > PCI: 00:18.0: enabled 1
>> > PCI: 00:18.1: enabled 1
>> > PCI: 00:18.2: enabled 1
>> > PCI: 00:18.3: enabled 1
>> > PCI: 00:18.4: enabled 1
>> > PCI: 00:18.5: enabled 1
>> > PCI: 00:18.6: enabled 1
>> > PCI: 00:18.7: enabled 1
>> > Compare with tree...
>> > Root Device: enabled 1
>> >  APIC_CLUSTER: 0: enabled 1
>> >   APIC: 00: enabled 1
>> >  PCI_DOMAIN: 0000: enabled 1
>> >   PCI: 00:00.0: enabled 1
>> >   PCI: 00:01.0: enabled 1
>> >   PCI: 00:01.1: enabled 1
>> >   PCI: 00:04.0: enabled 1
>> >   PCI: 00:05.0: enabled 0
>> >   PCI: 00:06.0: enabled 0
>> >   PCI: 00:07.0: enabled 0
>> >   PCI: 00:08.0: enabled 0
>> >   PCI: 00:11.0: enabled 1
>> >   PCI: 00:12.0: enabled 1
>> >   PCI: 00:12.1: enabled 1
>> >   PCI: 00:12.2: enabled 1
>> >   PCI: 00:13.0: enabled 1
>> >   PCI: 00:13.1: enabled 1
>> >   PCI: 00:13.2: enabled 1
>> >   PCI: 00:14.0: enabled 1
>> >    I2C: 00:50: enabled 1
>> >    I2C: 00:51: enabled 1
>> >   PCI: 00:14.1: enabled 1
>> >   PCI: 00:14.2: enabled 1
>> >   PCI: 00:14.3: enabled 1
>> >    PNP: 004e.0: enabled 0
>> >    PNP: 004e.3: enabled 0
>> >    PNP: 004e.4: enabled 0
>> >    PNP: 004e.5: enabled 1
>> >    PNP: 004e.6: enabled 0
>> >    PNP: 004e.a: enabled 0
>> >    PNP: 004e.10: enabled 1
>> >    PNP: 004e.11: enabled 0
>> >   PCI: 00:14.4: enabled 1
>> >   PCI: 00:14.5: enabled 1
>> >   PCI: 00:15.0: enabled 0
>> >   PCI: 00:15.1: enabled 0
>> >   PCI: 00:15.2: enabled 0
>> >   PCI: 00:15.3: enabled 0
>> >   PCI: 00:16.0: enabled 0
>> >   PCI: 00:16.2: enabled 0
>> >   PCI: 00:18.0: enabled 1
>> >   PCI: 00:18.1: enabled 1
>> >   PCI: 00:18.2: enabled 1
>> >   PCI: 00:18.3: enabled 1
>> >   PCI: 00:18.4: enabled 1
>> >   PCI: 00:18.5: enabled 1
>> >   PCI: 00:18.6: enabled 1
>> >   PCI: 00:18.7: enabled 1
>> > Mainboard Persimmon Enable.
>> > SLP_TYP type was 0
>> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
>> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
>> > 0x00000000
>> > persimmon_enable: uma size 0x18000000, memory start 0x67000000
>> > scan_static_bus for Root Device
>> > APIC_CLUSTER: 0 enabled
>> > PCI_DOMAIN: 0000 enabled
>> > APIC_CLUSTER: 0 scanning...
>> >   AP siblings=1
>> > CPU: APIC: 00 enabled
>> > CPU: APIC: 01 enabled
>> > PCI_DOMAIN: 0000 scanning...
>> > PCI: pci_scan_bus for bus 00
>> > POST: 0x24
>> > PCI: 00:00.0 [1022/1510] ops
>> > PCI: 00:00.0 [1022/1510] enabled
>> > PCI: 00:01.0 [1002/9804] enabled
>> > Capability: type 0x01 @ 0x50
>> > Capability: type 0x10 @ 0x58
>> > Capability: type 0x05 @ 0xa0
>> > Capability: type 0x0d @ 0xb0
>> > Capability: type 0x08 @ 0xb8
>> > Capability: type 0x01 @ 0x50
>> > Capability: type 0x10 @ 0x58
>> > PCI: 00:04.0 subordinate bus PCI Express
>> > PCI: 00:04.0 [1022/1512] enabled
>> > sb800_enable() SLP_TYP type was 0
>> > PCI: 00:11.0 [1002/4393] ops
>> > PCI: 00:11.0 [1002/4393] enabled
>> > sb800_enable() PCI: 00:12.0 [1002/4397] ops
>> > PCI: 00:12.0 [1002/4397] enabled
>> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: 00:12.2 [1002/4396] ops
>> > PCI: 00:12.2 [1002/4396] enabled
>> > sb800_enable() PCI: 00:13.0 [1002/4397] ops
>> > PCI: 00:13.0 [1002/4397] enabled
>> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
>> > it.
>> > sb800_enable() PCI: 00:13.2 [1002/4396] ops
>> > PCI: 00:13.2 [1002/4396] enabled
>> > sb800_enable() sm_init().
>> > IOAPIC: Clearing IOAPIC at 0xfec00000
>> > IOAPIC: 23 interrupts
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
>> > IOAPIC: Initializing IOAPIC at 0xfec00000
>> > IOAPIC: Bootstrap Processor Local APIC = 0x00
>> > IOAPIC: ID = 0x02
>> > IOAPIC: 23 interrupts
>> > IOAPIC: Enabling interrupts on FSB
>> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
>> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
>> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
>> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
>> > PCI: 00:14.0 [1002/4385] enabled
>> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
>> > it.
>> > sb800_enable() hda enabled
>> > PCI: 00:14.2 [1002/4383] ops
>> > PCI: 00:14.2 [1002/4383] enabled
>> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
>> > PCI: 00:14.3 [1002/439d] enabled
>> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
>> > PCI: 00:14.4 [1002/4384] enabled
>> > sb800_enable() PCI: 00:14.5 [1002/4399] ops
>> > PCI: 00:14.5 [1002/4399] enabled
>> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()
>> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
>> > PCI: 00:18.1 [1022/1701] enabled
>> > PCI: 00:18.2 [1022/1702] enabled
>> > PCI: 00:18.3 [1022/1703] enabled
>> > PCI: 00:18.4 [1022/1704] enabled
>> > PCI: 00:18.5 [1022/1718] enabled
>> > PCI: 00:18.6 [1022/1716] enabled
>> > PCI: 00:18.7 [1022/1719] enabled
>> > POST: 0x25
>> > PCI: Left over static devices:
>> > PCI: 00:01.1
>> > PCI: Check your devicetree.cb.
>> > do_pci_scan_bridge for PCI: 00:04.0
>> > PCI: pci_scan_bus for bus 01
>> > POST: 0x24
>> > PCI: 01:00.0 [10ec/8168] enabled
>> > POST: 0x25
>> > PCI: pci_scan_bus returning with max=001
>> > POST: 0x55
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>> >
>> >
>> > --
>> > coreboot mailing list: coreboot at coreboot.org<mailto:coreboot at coreboot.org>
>> > http://www.coreboot.org/mailman/listinfo/coreboot
>>
>

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From gerrit at coreboot.org  Tue Jun 12 10:01:17 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 12 Jun 2012 10:01:17 +0200
Subject: [coreboot] Patch merged into coreboot/master: bd563e6 udelay: add
	missing bus frequency
References: <Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6+0@gerrit.coreboot.org>
Message-ID: <E1SeM2P-0002D7-Ua@ra.coresystems.de>

the following patch was just integrated into master:
commit bd563e66681569f8b010f43a2289aa9d82537ec3
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 10 19:03:36 2012 +0200

    udelay: add missing bus frequency
    
    commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency
    detection on Sandybridge") reworked the udelay code, but didn't add
    the 333MHz FSB entry used on Model 15 Xeons.
    
    Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6
    Signed-off-by: Sven Schnelle <svens at stackframe.org>

Build-Tested: build bot (Jenkins) at Sun Jun 10 19:34:46 2012, giving +1
Reviewed-By: Sven Schnelle <svens at stackframe.org> at Tue Jun 12 10:01:15 2012, giving +2
See http://review.coreboot.org/1099 for details.

-gerrit



From wmkamp at datakamp.de  Tue Jun 12 16:07:02 2012
From: wmkamp at datakamp.de (Wolfgang Kamp - datakamp)
Date: Tue, 12 Jun 2012 16:07:02 +0200
Subject: [coreboot] AMD Persimmon VGA Option ROM
In-Reply-To: <20120612013459.GA32217@morn.localdomain>
References: <4738C8CE0A30FF47AACA9C624746E3E20DD118F244@DATAKAMPONE.datakamp2008.local>
	<20120612013459.GA32217@morn.localdomain>
Message-ID: <4738C8CE0A30FF47AACA9C624746E3E20DD118F275@DATAKAMPONE.datakamp2008.local>

Hi,

now I have debugged the seabios pci probing. The things happen in pci.c. 
The pci_next function probes all possible Bus:Device:Function combinations in the right manner.
The behavior is that the bdf 00:01:0 returns 0xffff as vendor id.
So the device is really not present at this time. But coreboot earlier has enumerated these device correctly.
How could it be that the graphics unit of the AMD G-series APU T40E is hidden from the pci bus?
The device is only present to seabios when coreboot executes the VGA ROM bios.

Wolfgang


-----Urspr?ngliche Nachricht-----
Von: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org] Im Auftrag von Kevin O'Connor
Gesendet: Dienstag, 12. Juni 2012 03:35
An: Stefan Reinauer
Cc: coreboot at coreboot.org
Betreff: Re: [coreboot] VGA Option ROM

On Sat, Jun 09, 2012 at 02:21:50PM -0700, Stefan Reinauer wrote:
> On 6/9/12 6:43 AM, Kevin O'Connor wrote:
> >On Fri, Jun 08, 2012 at 08:15:30AM -0700, ron minnich wrote:
> >>I wonder if we need another option :-( to configure the rom but not run it?
> >Shouldn't coreboot do that when CONFIG_VGA_BRIDGE_SETUP is set, but
> >CONFIG_VGA_ROM_RUN is not?
> >
> >-Kevin
> >
> CONFIG_VGA_BRIDGE_SETUP routes VGA legacy IO through the (PCI)
> bridge with the VGA card attached. It does not influence option rom
> handling.

Right.  Wolfgang is reporting that his VGA card isn't mapped at all if
he doesn't select CONFIG_VGA_ROM_RUN (it doesn't show up as a PCI
device at all).  It should get mapped even if CONFIG_VGA_ROM_RUN isn't
set.

-Kevin

-- 
coreboot mailing list: coreboot at coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot






From gerrit at coreboot.org  Tue Jun 12 23:35:18 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 12 Jun 2012 23:35:18 +0200
Subject: [coreboot] Patch merged into coreboot/master: 1a649e8 Update SB800
	CIMX FADT
References: <Ib11ef8f9346d42fcf653fae6e2752d62a40a3094+0@gerrit.coreboot.org>
Message-ID: <E1SeYkA-00063q-79@ra.coresystems.de>

the following patch was just integrated into master:
commit 1a649e859f956360dbb01b1e5e10fc6ab99f4dbd
Author: Martin Roth <martin at se-eng.com>
Date:   Fri May 25 12:23:32 2012 -0600

    Update SB800 CIMX FADT
    
     - Add #define to allow the FADT PM Profile to be overridden.
     - Change the location of the PMA_CNT_BLOCK_ADDRESS to match
       current documentation.
     - cst_cnt should be 0 if smi_cmd == 0
     - add a couple of default access sizes.
     - Add a couple of #define values for unsupported C2 & C3 entries.
     - Add PM Profile override value into amd/persimmon platform.
       This does not use the #defines in acpi.h so that the files that
       include this don't all need to start including acpi.h.
    
    Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
    Signed-off-by: Martin L Roth <martin at se-eng.com>

Build-Tested: build bot (Jenkins) at Fri May 25 22:40:06 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Tue Jun 12 23:35:15 2012, giving +2
See http://review.coreboot.org/1055 for details.

-gerrit



From marcj303 at gmail.com  Wed Jun 13 00:42:02 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Tue, 12 Jun 2012 16:42:02 -0600
Subject: [coreboot] crossgcc: make[2]: iasl: command not found
In-Reply-To: <1339110078.4294.18.camel@mattotaupa>
References: <1339110078.4294.18.camel@mattotaupa>
Message-ID: <CALrs_3heE8B45STScwt8DM2w0g6p5capLnj0H7=jFu0xo6JaqQ@mail.gmail.com>

On Thu, Jun 7, 2012 at 5:01 PM, Paul Menzel
<paulepanter at users.sourceforge.net> wrote:
> Dear coreboot folks,
>
>
> with a current clone of coreboot
>
> ? ? ? ?$ git describe
> ? ? ? ?4.0-2451-g2d1758b
>
> and
>
> ? ? ? ?$ make crossgcc
> ? ? ? ? ?Working around non-functional -combine
> ? ? ? ?Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011)
>
> ? ? ? ?Will skip GDB ... ok
> ? ? ? ?Downloading tar balls ...
> ? ? ? ? * gmp-5.0.5.tar.bz2 (downloading)
> ? ? ? ? * mpfr-3.1.0.tar.bz2 (downloading)
> ? ? ? ? * mpc-0.9.tar.gz (downloading)
> ? ? ? ? * libelf-0.8.13.tar.gz (downloading)
> ? ? ? ? * gcc-core-4.6.3.tar.bz2 (downloading)
> ? ? ? ? * binutils-2.22.tar.bz2 (downloading)
> ? ? ? ? * acpica-unix-20120420.tar.gz (downloading)
>
> ? ? ? ?Downloaded tar balls ... ok
> ? ? ? ?Unpacking and patching ...
> ? ? ? ? * gmp-5.0.5.tar.bz2
> ? ? ? ? * mpfr-3.1.0.tar.bz2
> ? ? ? ? * mpc-0.9.tar.gz
> ? ? ? ? * libelf-0.8.13.tar.gz
> ? ? ? ? * gcc-core-4.6.3.tar.bz2
> ? ? ? ? * binutils-2.22.tar.bz2
> ? ? ? ? * acpica-unix-20120420.tar.gz
> ? ? ? ?Unpacked and patched ... ok
> ? ? ? ?Building GMP 5.0.5 ... ok
> ? ? ? ?Building MPFR 3.1.0 ... ok
> ? ? ? ?Building MPC 0.9 ... ok
> ? ? ? ?Building libelf 0.8.13 ... ok
> ? ? ? ?Building binutils 2.22 ... ok
> ? ? ? ?Building GCC 4.6.3 ... ok
> ? ? ? ?Skipping Expat (Python scripting not enabled)
> ? ? ? ?Skipping Python (Python scripting not enabled)
> ? ? ? ?Skipping GDB (GDB support not enabled)
> ? ? ? ?Building IASL 20120420 ... ok
> ? ? ? ?Cleaning up... ok
>
> ? ? ? ?You can now run your i386-elf cross toolchain from /opt/src/coreboot/util/crossgcc/xgcc.
> ? ? ? ?$ make menuconfig # for ASRock E350M1 with SeaBIOS master and 4 MB image
> ? ? ? ?$ make
>
> I got the following error.
>
> ? ? ? ?[?]
> ? ? ? ? ? ?Checking out SeaBIOS revision origin/master
> ? ? ? ?Switched to branch 'master'
> ? ? ? ?Deleted branch coreboot (was e66fb31).
> ? ? ? ?Branch coreboot set up to track remote branch master from
> ? ? ? ?origin.
> ? ? ? ?Switched to a new branch 'coreboot'
> ? ? ? ? ? ?CONFIG ? ? SeaBIOS origin/master
> ? ? ? ? ?Working around non-functional -combine
> ? ? ? ? ?Build default config
> ? ? ? ?#
> ? ? ? ?# configuration written
> ? ? ? ?to /opt/src/coreboot/build/seabios/.config
> ? ? ? ?#
> ? ? ? ? ? ?MAKE ? ? ? SeaBIOS origin/master
> ? ? ? ? ?Working around non-functional -combine
> ? ? ? ? ?Build Kconfig config file
> ? ? ? ?/opt/src/coreboot/build/seabios/.config:89:warning: override:
> ? ? ? ?reassigning to symbol COREBOOT
> ? ? ? ?/opt/src/coreboot/build/seabios/.config:90:warning: override:
> ? ? ? ?reassigning to symbol DEBUG_SERIAL
> ? ? ? ?/opt/src/coreboot/build/seabios/.config:95:warning: override:
> ? ? ? ?reassigning to symbol VGAHOOKS
> ? ? ? ?#
> ? ? ? ?# configuration written
> ? ? ? ?to /opt/src/coreboot/build/seabios/.config
> ? ? ? ?#
> ? ? ? ?Compiling DSDT
> ? ? ? ?make[2]: iasl: Kommando nicht gefunden
> ? ? ? ?make[2]: *** [src/acpi-dsdt.hex] Fehler 127
> ? ? ? ?make[1]: *** [build] Fehler 2
> ? ? ? ?make: *** [seabios] Fehler 2
>
> The file `.xcompile` also contains the correct definition for `IASL`.
>
> ? ? ? ?IASL:=/opt/src/coreboot/util/crossgcc/xgcc/bin/iasl
>
> Running that file works too so no `noexec` flag or something else seems
> to be at fault.
>
>
> Thanks,
>
> Paul
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot

Hi Paul,

I think that the stable version of seabios doesn't pick up the version
from coreboot. Check the git log for:

commit 74f96123e7e37c219403b50e39dabc8e8c450948
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Sun Apr 29 11:20:53 2012 -0600

You can put a softlink to it into you path to get around this.

Marc
-- 
http://se-eng.com



From steve.goodrich at se-eng.com  Wed Jun 13 01:06:11 2012
From: steve.goodrich at se-eng.com (Steve Goodrich)
Date: Tue, 12 Jun 2012 17:06:11 -0600
Subject: [coreboot] One ROM for multiple devices
Message-ID: <015201cd48ef$f5e595a0$e1b0c0e0$@goodrich@se-eng.com>

Please be aware that this is cross-posted to both the SeaBIOS and coreboot
mailing lists.  I know this is generally frowned upon, but I believe the
subject is valid for discussion in both forums.


I have a coreboot/SeaBIOS image containing an option ROM that works for
multiple graphics devices (seven or eight of them).  These graphics devices
come from the same vendor but each device has its own (unique) PCI Device
ID.  If I'm going to load the driver from SeaBIOS, I need to have a copy of
the option ROM file, each with the name of the target PCI device (e.g.
"pci1234,5678.rom").  Having seven or eight copies in the BIOS image file is
a waste of space.

Stefan R. submitted a solution to coreboot to enable mapping one ROM's
vendor/device ID to another and this solution has worked well for
coreboot-centric uses.

Unfortunately, this does not address the problem in SeaBIOS.  I have started
working on a solution that extends what Stefan has done, but moves the data
into a single "translate" file in CBFS.  This file contains simple data to
allow coreboot and/or SeaBIOS to take a PCI device's vendor/device info and
retrieve alternate vendor/device values.

Since both coreboot and SeaBIOS understand CBFS, the basic translation code
would be identical.

The data file consists of sets of four 16-bit binary values:
    u16 vendor1, device1; // translate FROM this PCI v/d
    u16 vendor2, device2; // translate TO this PCI v/d

If you have a single ROM which could support three devices, you would have
two sets of data:
    0x1234, 0x0001, 0x1234, 0x0002
    0x1234, 0x0001, 0x1234, 0x0003
This data would let the ROM for vendor 0x1234, device 0x0001 support devices
0x0002 and 0x0003.  NOTE: there is no data for device 0x0001, since it would
be handled without translation.

The code would work something like this:
    sprintf(name, "pci%04x,%04x.rom", pci->vendor, pci->device);
    rom = cbfs_findfile(name); // load the file
    if (!rom) {
        // ROM not found... try translation
        ven = pci->vendor;
        dev = pci->device;
        if (translate_findFirst(&ven, &dev)) {
            do {
                sprintf(name, "pci%04x,%04x.rom", ven, dev);
                rom = cbfs_findfile(name); // load the file
            while ((rom == null) && translate_findNext(&ven, &dev));
        }
    }

I'm not tied to the findFirst/findNext mechanism nor to the specific format
of the data.  What I would like to see is some mechanism in both coreboot
and SeaBIOS that would allow a given ROM to be used for multiple devices.

In coreboot this would affect the map_oprom_vendev() function.
In SeaBIOS this would affect both lookup_hardcode() and map_pcirom().

Since this problem exists in both codebases, is it reasonable to come up
with a solution that will work in both codebases?

Thoughts?
??????????? -- Steve G.




From peter at stuge.se  Wed Jun 13 01:47:19 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 13 Jun 2012 01:47:19 +0200
Subject: [coreboot] One ROM for multiple devices
Message-ID: <20120612234719.32671.qmail@stuge.se>

Steve Goodrich wrote:
> I would like to see is some mechanism in both coreboot and SeaBIOS
> that would allow a given ROM to be used for multiple devices.
..
> Since this problem exists in both codebases, is it reasonable to
> come up with a solution that will work in both codebases?

I think this should happen in CBFS. The proposal is basically a
special case symlink. It would be nice to have generic symlinks
instead.

Another special case solution yet still CBFS-centered could be to
search for wildcard option ROMs at runtime. (V and D below are
hexits, while x is a literal x.)

1. pciVVVV,DDDD.rom
2. pciVVVV,DDDx.rom
3. pciVVVV,DDxx.rom
4. pciVVVV,Dxxx.rom
5. pciVVVV,xxxx.rom
6. pciVVVx,xxxx.rom
7. pciVVxx,xxxx.rom
8. pciVxxx,xxxx.rom
9. pcixxxx,xxxx.rom

6 through 9 may be debatable, but I'm not neccessarily against them!


//Peter



From kevin at koconnor.net  Wed Jun 13 01:19:31 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Tue, 12 Jun 2012 19:19:31 -0400
Subject: [coreboot] One ROM for multiple devices
In-Reply-To: <4fd7cb83.8e85cd0a.70a1.ffffbd89SMTPIN_ADDED@mx.google.com>
References: <4fd7cb83.8e85cd0a.70a1.ffffbd89SMTPIN_ADDED@mx.google.com>
Message-ID: <20120612231931.GB26443@morn.localdomain>

On Tue, Jun 12, 2012 at 05:06:11PM -0600, Steve Goodrich wrote:
> Please be aware that this is cross-posted to both the SeaBIOS and coreboot
> mailing lists.  I know this is generally frowned upon, but I believe the
> subject is valid for discussion in both forums.
> 
> 
> I have a coreboot/SeaBIOS image containing an option ROM that works for
> multiple graphics devices (seven or eight of them).  These graphics devices
> come from the same vendor but each device has its own (unique) PCI Device
> ID.  If I'm going to load the driver from SeaBIOS, I need to have a copy of
> the option ROM file, each with the name of the target PCI device (e.g.
> "pci1234,5678.rom").  Having seven or eight copies in the BIOS image file is
> a waste of space.

For the SeaBIOS case, is there any reason you can't simply place the
rom in a cbfs file "vgaroms/myrom.rom"?

-Kevin



From kraxel at redhat.com  Wed Jun 13 08:50:00 2012
From: kraxel at redhat.com (Gerd Hoffmann)
Date: Wed, 13 Jun 2012 08:50:00 +0200
Subject: [coreboot] [SeaBIOS] One ROM for multiple devices
In-Reply-To: <015201cd48ef$f5e595a0$e1b0c0e0$@goodrich@se-eng.com>
References: <015201cd48ef$f5e595a0$e1b0c0e0$@goodrich@se-eng.com>
Message-ID: <4FD83818.4060001@redhat.com>

On 06/13/12 01:06, Steve Goodrich wrote:
> Please be aware that this is cross-posted to both the SeaBIOS and coreboot
> mailing lists.  I know this is generally frowned upon, but I believe the
> subject is valid for discussion in both forums.
> 
> 
> I have a coreboot/SeaBIOS image containing an option ROM that works for
> multiple graphics devices (seven or eight of them).  These graphics devices
> come from the same vendor but each device has its own (unique) PCI Device
> ID.  If I'm going to load the driver from SeaBIOS, I need to have a copy of
> the option ROM file, each with the name of the target PCI device (e.g.
> "pci1234,5678.rom").  Having seven or eight copies in the BIOS image file is
> a waste of space.
> 
> Stefan R. submitted a solution to coreboot to enable mapping one ROM's
> vendor/device ID to another and this solution has worked well for
> coreboot-centric uses.
> 
> Unfortunately, this does not address the problem in SeaBIOS.  I have started
> working on a solution that extends what Stefan has done, but moves the data
> into a single "translate" file in CBFS.  This file contains simple data to
> allow coreboot and/or SeaBIOS to take a PCI device's vendor/device info and
> retrieve alternate vendor/device values.
> 
> Since both coreboot and SeaBIOS understand CBFS, the basic translation code
> would be identical.
> 
> The data file consists of sets of four 16-bit binary values:
>     u16 vendor1, device1; // translate FROM this PCI v/d
>     u16 vendor2, device2; // translate TO this PCI v/d

Another possible solution would be to add support for symbolic links to
cbfs.

How do you get around the limitation of a single pci id in the rom
header?  Or does seabios skip the pci id verification for rom files
loaded from cbfs?

cheers,
  Gerd




From paulepanter at users.sourceforge.net  Wed Jun 13 09:36:17 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 13 Jun 2012 09:36:17 +0200
Subject: [coreboot] crossgcc: make[2]: iasl: command not found
In-Reply-To: <CALrs_3heE8B45STScwt8DM2w0g6p5capLnj0H7=jFu0xo6JaqQ@mail.gmail.com>
References: <1339110078.4294.18.camel@mattotaupa>
	<CALrs_3heE8B45STScwt8DM2w0g6p5capLnj0H7=jFu0xo6JaqQ@mail.gmail.com>
Message-ID: <1339572977.4145.12.camel@mattotaupa>

Am Dienstag, den 12.06.2012, 16:42 -0600 schrieb Marc Jones:
> On Thu, Jun 7, 2012 at 5:01 PM, Paul Menzel wrote:

> > with a current clone of coreboot
> >
> >        $ git describe
> >        4.0-2451-g2d1758b
> >
> > and
> >
> >        $ make crossgcc
> >          Working around non-functional -combine
> >        Welcome to the coreboot cross toolchain builder v1.07 (November 1st, 2011)
> >
> >        Will skip GDB ... ok
> >        Downloading tar balls ...
> >         * gmp-5.0.5.tar.bz2 (downloading)
> >         * mpfr-3.1.0.tar.bz2 (downloading)
> >         * mpc-0.9.tar.gz (downloading)
> >         * libelf-0.8.13.tar.gz (downloading)
> >         * gcc-core-4.6.3.tar.bz2 (downloading)
> >         * binutils-2.22.tar.bz2 (downloading)
> >         * acpica-unix-20120420.tar.gz (downloading)
> >
> >        Downloaded tar balls ... ok
> >        Unpacking and patching ...
> >         * gmp-5.0.5.tar.bz2
> >         * mpfr-3.1.0.tar.bz2
> >         * mpc-0.9.tar.gz
> >         * libelf-0.8.13.tar.gz
> >         * gcc-core-4.6.3.tar.bz2
> >         * binutils-2.22.tar.bz2
> >         * acpica-unix-20120420.tar.gz
> >        Unpacked and patched ... ok
> >        Building GMP 5.0.5 ... ok
> >        Building MPFR 3.1.0 ... ok
> >        Building MPC 0.9 ... ok
> >        Building libelf 0.8.13 ... ok
> >        Building binutils 2.22 ... ok
> >        Building GCC 4.6.3 ... ok
> >        Skipping Expat (Python scripting not enabled)
> >        Skipping Python (Python scripting not enabled)
> >        Skipping GDB (GDB support not enabled)
> >        Building IASL 20120420 ... ok
> >        Cleaning up... ok
> >
> >        You can now run your i386-elf cross toolchain from /opt/src/coreboot/util/crossgcc/xgcc.
> >        $ make menuconfig # for ASRock E350M1 with SeaBIOS master and 4 MB image
> >        $ make
> >
> > I got the following error.
> >
> >        [?]
> >            Checking out SeaBIOS revision origin/master
> >        Switched to branch 'master'
> >        Deleted branch coreboot (was e66fb31).
> >        Branch coreboot set up to track remote branch master from
> >        origin.
> >        Switched to a new branch 'coreboot'
> >            CONFIG     SeaBIOS origin/master
> >          Working around non-functional -combine
> >          Build default config
> >        #
> >        # configuration written
> >        to /opt/src/coreboot/build/seabios/.config
> >        #
> >            MAKE       SeaBIOS origin/master
> >          Working around non-functional -combine
> >          Build Kconfig config file
> >        /opt/src/coreboot/build/seabios/.config:89:warning: override:
> >        reassigning to symbol COREBOOT
> >        /opt/src/coreboot/build/seabios/.config:90:warning: override:
> >        reassigning to symbol DEBUG_SERIAL
> >        /opt/src/coreboot/build/seabios/.config:95:warning: override:
> >        reassigning to symbol VGAHOOKS
> >        #
> >        # configuration written
> >        to /opt/src/coreboot/build/seabios/.config
> >        #
> >        Compiling DSDT
> >        make[2]: iasl: Kommando nicht gefunden
> >        make[2]: *** [src/acpi-dsdt.hex] Fehler 127
> >        make[1]: *** [build] Fehler 2
> >        make: *** [seabios] Fehler 2
> >
> > The file `.xcompile` also contains the correct definition for `IASL`.
> >
> >        IASL:=/opt/src/coreboot/util/crossgcc/xgcc/bin/iasl
> >
> > Running that file works too so no `noexec` flag or something else seems
> > to be at fault.

[?]

> I think that the stable version of seabios doesn't pick up the version
> from coreboot. Check the git log for:
> 
> commit 74f96123e7e37c219403b50e39dabc8e8c450948
> Author: Marc Jones <marc.jones at se-eng.com>
> Date:   Sun Apr 29 11:20:53 2012 -0600

Marc, thank you for your suggestion. With that commit the error is gone.

Strangely as seen above I had chosen SeaBIOS master in Kconfig, but it
looks like it was still at stable release at Git tag rel-1.7.0.

        commit a0263083cb4cda172832fbc916dc1417ee930574
        Author: Kevin O'Connor <kevin at koconnor.net>
        Date:   Sat Apr 14 20:22:18 2012 -0400

            Misc compile fixes for gcc v3.4.
            
            Signed-off-by: Kevin O'Connor <kevin at koconnor.net>

> You can put a softlink to it into you path to get around this.

Not necessary anymore thanks to your fix.


Thanks,

Paul
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From hercares at gmail.com  Wed Jun 13 09:38:00 2012
From: hercares at gmail.com (Julian Shulika)
Date: Wed, 13 Jun 2012 10:38:00 +0300
Subject: [coreboot] bios chip
Message-ID: <CA+aqTM9a84RTG1AmOH_5k_dzCkSj7_8EN7MFJt0jX3w=XXeu+g@mail.gmail.com>

Hello,everyone! I'm tired to remove bios chip LPC from motherboard for
flashing updated firmware coreboot all time and I broke bios socket twice.
Is there any flash device I can use instead of bios chip and flash it from
other host directly?
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From paulepanter at users.sourceforge.net  Wed Jun 13 10:17:19 2012
From: paulepanter at users.sourceforge.net (Paul Menzel)
Date: Wed, 13 Jun 2012 10:17:19 +0200
Subject: [coreboot] crossgcc: `make clean` fails for SeaBIOS because IASL
 definition is not passed
Message-ID: <1339575439.4145.24.camel@mattotaupa>

Dear coreboot folks,


running `make clean` I get the following behavior (SeaBIOS 2062f2ba).

        coreboot$ make clean
        The SeaBIOS project requires the 'iasl' package be installed.
        Many Linux distributions have this package.
        Try: sudo yum install iasl
        Or: sudo apt-get install iasl

        Please install iasl and retry.
        Makefile:87: *** "Please upgrade the build environment".  Schluss.
        coreboot$ cd build/seabios/
        coreboot/build/seabios$ make clean
        The SeaBIOS project requires the 'iasl' package be installed.
        Many Linux distributions have this package.
        Try: sudo yum install iasl
        Or: sudo apt-get install iasl

        Please install iasl and retry.
        Makefile:87: *** "Please upgrade the build environment".  Schluss.

        $ more Makefile
        [?]
        IASL:=iasl

        # Default targets
        -include $(KCONFIG_CONFIG)

        target-y = $(OUT) $(OUT)bios.bin
        target-$(CONFIG_BUILD_VGABIOS) += $(OUT)vgabios.bin

        all: $(target-y)

        # Make definitions
        .PHONY : all clean distclean FORCE

        vpath %.c src vgasrc
        vpath %.S src vgasrc


        ################ Common build rules

        # Verify the build environment works.
        TESTGCC:=$(shell CC="$(CC)" LD="$(LD)" IASL="$(IASL)" tools/test-build.sh)
        ifeq "$(TESTGCC)" "-1"
        $(error "Please upgrade the build environment")
        endif

So is there a way that the environment variables from coreboot are
passed to SeaBIOS? `make` with a SeaBIOS containing Marc?s commit
74f96123 ?Add IASL definition to the Makefile.? works fine.


Thanks,

Paul
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From marcj303 at gmail.com  Wed Jun 13 19:37:50 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Wed, 13 Jun 2012 11:37:50 -0600
Subject: [coreboot] [SeaBIOS] One ROM for multiple devices
In-Reply-To: <4FD83818.4060001@redhat.com>
References: <4FD83818.4060001@redhat.com>
Message-ID: <CALrs_3hMW2vjHqMPSnZoMvg-tLVVW2iTBFJ84Xi50uNErhic6g@mail.gmail.com>

On Wed, Jun 13, 2012 at 12:50 AM, Gerd Hoffmann <kraxel at redhat.com> wrote:
> On 06/13/12 01:06, Steve Goodrich wrote:
>> Please be aware that this is cross-posted to both the SeaBIOS and coreboot
>> mailing lists. ?I know this is generally frowned upon, but I believe the
>> subject is valid for discussion in both forums.
>>
>>
>> I have a coreboot/SeaBIOS image containing an option ROM that works for
>> multiple graphics devices (seven or eight of them). ?These graphics devices
>> come from the same vendor but each device has its own (unique) PCI Device
>> ID. ?If I'm going to load the driver from SeaBIOS, I need to have a copy of
>> the option ROM file, each with the name of the target PCI device (e.g.
>> "pci1234,5678.rom"). ?Having seven or eight copies in the BIOS image file is
>> a waste of space.
>>
>> Stefan R. submitted a solution to coreboot to enable mapping one ROM's
>> vendor/device ID to another and this solution has worked well for
>> coreboot-centric uses.
>>
>> Unfortunately, this does not address the problem in SeaBIOS. ?I have started
>> working on a solution that extends what Stefan has done, but moves the data
>> into a single "translate" file in CBFS. ?This file contains simple data to
>> allow coreboot and/or SeaBIOS to take a PCI device's vendor/device info and
>> retrieve alternate vendor/device values.
>>
>> Since both coreboot and SeaBIOS understand CBFS, the basic translation code
>> would be identical.
>>
>> The data file consists of sets of four 16-bit binary values:
>> ? ? u16 vendor1, device1; // translate FROM this PCI v/d
>> ? ? u16 vendor2, device2; // translate TO this PCI v/d
>
> Another possible solution would be to add support for symbolic links to
> cbfs.
>
> How do you get around the limitation of a single pci id in the rom
> header? ?Or does seabios skip the pci id verification for rom files
> loaded from cbfs?

This is why I think it should not be part of cbfs, The problem is not
a file handling issue. It is a function of the PCI ROM handling that
has a special case for onboard ROMs. The PCI rom routine needs to
understand that it is using a compatible ID and skip the ROM header
checking (Seabios doesn't check but coreboot does). VGA ROMs are the
most common case, but happens with ethernet and ahci/raid ROMs as
well.

Marc


-- 
http://se-eng.com



From mxm368 at googlemail.com  Wed Jun 13 10:28:07 2012
From: mxm368 at googlemail.com (Mihai Marchidann)
Date: Wed, 13 Jun 2012 11:28:07 +0300
Subject: [coreboot] P965 / ICH8R coreboot support
Message-ID: <CAHPFaOzBAeu=EPXeR2bcYw6r7MRuQVcQT=sQxXJKBZyrEZrAhw@mail.gmail.com>

Hello,

I would like to know if it is feasible to seek coreboot support
for the LGA775 socket and motherboards based on the P965
and ICH8R chipsets and controllers.
These motherboards, such as ASUS P5B-DE and P5B Deluxe Wifi-AP,
are still offered for sale and their top processors are still competitive
despite a few Intel CPU refreshes in the last 3-4 years.

I am wondering if the following datasheets and specifications would
suffice to start working on this port.
http://ark.intel.com/products/chipsets/22754/config/26953
http://ark.intel.com/products/27687/Intel-82801HR-IO-Controller
http://www.intel.com/content/www/us/en/io/intel-io-controller-hub-8-datasheet.html

http://ark.intel.com/products/27730/Intel-82P965-Memory-Controller
http://www.intel.com/Assets/PDF/datasheet/313053.pdf

http://ark.intel.com/products/29765/Intel-Core2-Quad-Processor-Q6600-%288M-Cache-2_40-GHz-1066-MHz-FSB%29
http://www.intel.com/design/processor/datashts/315592.htm
http://www.intel.com/design/processor/specupdt/315593.htm
http://download.intel.com/design/processor/datashts/31559205.pdf

http://www.intel.com/Assets/PDF/designguide/302666.pdf
http://download.intel.com/design/processor/designex/315594.pdf
http://www.intel.com/Assets/en_US/PDF/designguide/314917.pdf

I would appreciate any advice and help. Thank you.

Best regards,
Mihai Marchidann
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From mihaim_118 at yahoo.com  Thu Jun 14 12:50:10 2012
From: mihaim_118 at yahoo.com (Mihai Marchidann)
Date: Thu, 14 Jun 2012 03:50:10 -0700 (PDT)
Subject: [coreboot] P965 / ICH8R coreboot support
Message-ID: <1339671010.63080.YahooMailNeo@web39401.mail.mud.yahoo.com>

Hello,


I would like to know if it is feasible to seek coreboot support
for the LGA775 socket and motherboards based on the P965
and ICH8R chipsets and controllers.
These motherboards, such as ASUS P5B-DE and P5B Deluxe Wifi-AP,
are still offered for sale and their top processors are still competitive
despite a few Intel CPU refreshes in the last 3-4 years.

I am wondering if the following datasheets and specifications would
suffice to start working on this port.
http://ark.intel.com/products/chipsets/22754/config/26953
http://ark.intel.com/products/27687/Intel-82801HR-IO-Controller
http://www.intel.com/content/www/us/en/io/intel-io-controller-hub-8-datasheet.html

http://ark.intel.com/products/27730/Intel-82P965-Memory-Controller
http://www.intel.com/Assets/PDF/datasheet/313053.pdf

http://ark.intel.com/products/29765/Intel-Core2-Quad-Processor-Q6600-%288M-Cache-2_40-GHz-1066-MHz-FSB%29
http://www.intel.com/design/processor/datashts/315592.htm
http://www.intel.com/design/processor/specupdt/315593.htm
http://download.intel.com/design/processor/datashts/31559205.pdf

http://www.intel.com/Assets/PDF/designguide/302666.pdf
http://download.intel.com/design/processor/designex/315594.pdf
http://www.intel.com/Assets/en_US/PDF/designguide/314917.pdf

I would appreciate any advice and help. Thank you.

Best regards,
Mihai Marchidann
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From gerrit at coreboot.org  Thu Jun 14 15:52:08 2012
From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org))
Date: Thu, 14 Jun 2012 15:52:08 +0200
Subject: [coreboot] New patch to review for coreboot: a71f045 llshell: fix
	build without romcc
References: <I49eded1d18e996afe9441b85dae04ae30c760dd6+0@gerrit.coreboot.org>
Message-ID: <I49eded1d18e996afe9441b85dae04ae30c760dd6+1@gerrit.coreboot.org>

Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1101

-gerrit

commit a71f045e44f42a09c318bb46086616b329ffacc8
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Thu Jun 14 14:19:09 2012 +0200

    llshell: fix build without romcc
    
    Without that fix we have:
          LINK       cbfs/fallback/romstage_null.debug
      build/generated/crt0.romstage.o: In function `ramtest':
      romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt'
      collect2: ld returned 1 exit status
      make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1
    On the M4A785T-M which doesn't have CONFIG_ROMCC.
    
    Change-Id: I49eded1d18e996afe9441b85dae04ae30c760dd6
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
 src/arch/x86/llshell/ramtest.inc |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/llshell/ramtest.inc b/src/arch/x86/llshell/ramtest.inc
index c02cf45..49abd4a 100644
--- a/src/arch/x86/llshell/ramtest.inc
+++ b/src/arch/x86/llshell/ramtest.inc
@@ -112,8 +112,10 @@ ramtest:
 	jmp 3b
 5:
 	CONSOLE_INFO_TX_STRING($rt_toomany)
+#if CONFIG_ROMCC
 	post_code(0xf1)
 	jmp	.Lhlt
+#endif
 
 6:
 	CONSOLE_INFO_TX_STRING($rt_done)



From gerrit at coreboot.org  Thu Jun 14 15:52:08 2012
From: gerrit at coreboot.org (Denis Carikli (GNUtoo@no-log.org))
Date: Thu, 14 Jun 2012 15:52:08 +0200
Subject: [coreboot] New patch to review for coreboot: 5a0f3f4 M4A785-M and
	M4A785T-M: Add support for llshell
References: <Ia9ee1bcd363896a8618407149fafdd354e6c0a88+0@gerrit.coreboot.org>
Message-ID: <Ia9ee1bcd363896a8618407149fafdd354e6c0a88+1@gerrit.coreboot.org>

Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1102

-gerrit

commit 5a0f3f476fd4780495bfe8ba04fb96bf4d646795
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Thu Jun 14 14:21:09 2012 +0200

    M4A785-M and M4A785T-M: Add support for llshell
    
    Change-Id: Ia9ee1bcd363896a8618407149fafdd354e6c0a88
    Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
 src/mainboard/asus/m4a785-m/romstage.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index f0be2f7..338edf4 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -50,6 +50,7 @@
 #include "southbridge/amd/sb700/sb700.h"
 #include "southbridge/amd/sb700/smbus.h"
 #include "northbridge/amd/amdfam10/debug.c"
+#include "arch/llshell.h"
 
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
@@ -221,6 +222,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sb7xx_51xx_before_pci_init();
 
 	post_code(0x42);
+
+#if CONFIG_LLSHELL
+       llshell();
+#endif
+
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
 	post_code(0x43);	// Should never see this post code.
 }



From gerrit at coreboot.org  Thu Jun 14 21:21:07 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 14 Jun 2012 21:21:07 +0200
Subject: [coreboot] Patch merged into coreboot/master: a71f045 llshell: fix
	build without romcc
References: <I49eded1d18e996afe9441b85dae04ae30c760dd6+0@gerrit.coreboot.org>
Message-ID: <E1SfFbP-0007vi-SH@ra.coresystems.de>

the following patch was just integrated into master:
commit a71f045e44f42a09c318bb46086616b329ffacc8
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date:   Thu Jun 14 14:19:09 2012 +0200

    llshell: fix build without romcc
    
    Without that fix we have:
          LINK       cbfs/fallback/romstage_null.debug
      build/generated/crt0.romstage.o: In function `ramtest':
      romstage.c:(.rom.text+0x53f): undefined reference to `.Lhlt'
      collect2: ld returned 1 exit status
      make: *** [build/cbfs/"fallback"/romstage_null.debug] Error 1
    On the M4A785T-M which doesn't have CON