[coreboot] PCIe devices not enabled on amd/persimmon
Andy Sharp
andywyse6 at gmail.com
Sat Jun 9 02:16:21 CEST 2012
It's a persimmon board ~:^)
I'd be happy to test any patches. Meanwhile, I'm working on a patch to
properly enable the southbridge PCIe devices so they can be scanned.
Wolfgang (Wolfie?) is quite correct, the code that enables/deresets those
PCIe ports happens after the bus is scanned. When nothing shows up on the
bus scan, the code powers down those devices right after it [too late]
powers them up. Broken.
This persimmon board is made by iBASE. and is a mini-ITX. It has a PCIe
slot and a mini-PCIe card socket on the sb800 PCIe ports. I may have
earlier said that it had a USB3 ctlr, that was my bad. So many twisty
passages....
I'll try out various combinations of the various patches you good folks
have been throwing my way, plus some of my own ideas and let the list know
what happens.
Cheers,
a
On Fri, Jun 8, 2012 at 6:09 AM, Dave Frodin <dave at se-eng.com> wrote:
> There shouldn't be any need to guess if it is a Persimmon. On a
> Persimmon board, next to the SATA connectors there should be
> printing that says "DB FT1".
>
> The Persimmon can also have up to two PCIe Ethernet chips on it.
>
> dave
>
> ----- Original Message -----
> > From: "Zheng Bao" <Zheng.Bao at amd.com>
> > To: "Andy Sharp" <andywyse6 at gmail.com>
> > Cc: "coreboot at coreboot.org" <coreboot at coreboot.org>
> > Sent: Friday, June 8, 2012 5:37:58 AM
> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Hi, Andy,
> > The persimmon board I have got doesn't have any PCIe slot or onboard
> > PCIe device attached to SB800. And I am wondering if you actually
> > use a inagua board, which has the same APU & SB with persimmon and 2
> > minipcie slots other than that.
> >
> > Let us assume you are testing on Inagua.
> > Here is my patch for the PCIe on SB800. There was a bug. It is just a
> > workaround patch, not ready for submitting.
> >
> > This patch can fix the sb800/pcie issue on Inagua. If you have your
> > work based on persimmon, please note the devicetree.cb should be
> > modify as Inagua.
> > The dev15func[0123] should be enabled and the gpp_configuration
> > should be 4.
> >
> > Joe
> >
> > diff --git a/src/southbridge/amd/cimx/sb800/late.c
> > b/src/southbridge/amd/cimx/sb800/late.c
> > index 0ce82b3..34cd937 100644
> > --- a/src/southbridge/amd/cimx/sb800/late.c
> > +++ b/src/southbridge/amd/cimx/sb800/late.c
> > @@ -29,6 +29,7 @@
> > #include "SBPLATFORM.h" /* Platfrom Specific Definitions */
> > #include "cfg.h" /* sb800 Cimx configuration */
> > #include "chip.h" /* struct
> southbridge_amd_cimx_sb800_config */
> > +#include "smbus.h"
> > #include "sb_cimx.h" /* AMD CIMX wrapper entries */
> >
> >
> > @@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
> > .set_resources = pci_dev_set_resources,
> > .enable_resources = pci_bus_enable_resources,
> > .init = pci_init,
> > + .enable = 0,
> > .scan_bus = pci_scan_bridge,
> > .reset_bus = pci_bus_reset,
> > .ops_pci = &lops_pci,
> > @@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
> > .reset_bus = pci_bus_reset,
> > .ops_pci = &lops_pci,
> > };
> > -
> > +#if 0
> > /* 0:15:0 PCIe PortA */
> > static const struct pci_driver PORTA_driver __pci_driver = {
> > .ops = &bridge_ops,
> > @@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver
> > __pci_driver = {
> > .vendor = PCI_VENDOR_ID_ATI,
> > .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
> > };
> > -
> > +#endif
> >
> > /**
> > * South Bridge CIMx ramstage entry point wrapper.
> > @@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
> > switch (dev->path.pci.devfn) {
> > case (0x11 << 3) | 0: /* 0:11.0 SATA */
> > /* the first sb800 device */
> > + abcfg_reg(0xc0, 0x1FF, 0x0F4);
> > sb800_cimx_config(sb_config);
> >
> > if (dev->enabled) {
> > @@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
> > sb_config->GppLinkConfig =
> sb_chip->gpp_configuration;
> > }
> > break;
> > + case (0x15 << 3) | 1:
> > + case (0x15 << 3) | 2:
> > + case (0x15 << 3) | 3:
> > + //abcfg_reg(0xc0, 0xF0, 0x00);
> > + break;
> >
> > case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
> > sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
> > @@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
> > /* call the CIMX entry at the last sb800 device,
> > * so make sure the mainboard devicetree is complete
> > */
> > + abcfg_reg(0xc0, 0x100, 0x100);
> > #if CONFIG_HAVE_ACPI_RESUME
> > if (acpi_slp_type != 3)
> > sb_Before_Pci_Init();
> >
> >
> >
> >
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> > Sent: Friday, June 08, 2012 8:57 AM
> > To: coreboot at coreboot.org
> > Subject: Re: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Hi Steve,
> >
> > Makes no [substantive] difference. All that does is cause 4 extra
> > lines to be added to the console output:
> >
> > .
> > .
> > .
> > sb800_enable() PCI: Static device PCI: 00:15.0 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.1 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.2 not found, disabling
> > it.
> > sb800_enable() PCI: Static device PCI: 00:15.3 not found, disabling
> > it.
> > .
> > .
> > .
> >
> >
> > On Thu, Jun 7, 2012 at 2:54 PM, Steve Goodrich
> > <steve.goodrich at se-eng.com> wrote:
> > ARG.. Thanks, Outlook. :P
> >
> > Andy,
> >
> > Check the devicetree.cb file in your ./src/mainboard/amd/persimmon
> > folder. Mine shows:
> >
> > device pci 15.0 off end # PCIe PortA
> > device pci 15.1 off end # PCIe PortB
> > device pci 15.2 off end # PCIe PortC
> > device pci 15.3 off end # PCIe PortD
> >
> > I'm not 100% certain, but I suspect that changing these from "off" to
> > "on" will enable the devices. Try the change and see if the console
> > output starts reflecting the devices you're looking for.
> >
> > -- Steve G.
> >
> >
> >
> > From: coreboot-bounces at coreboot.org
> > [mailto:coreboot-bounces at coreboot.org] On Behalf Of Andy Sharp
> > Sent: Thursday, June 07, 2012 2:31 PM
> > To: coreboot at coreboot.org
> > Subject: [coreboot] PCIe devices not enabled on amd/persimmon
> >
> > Howdy,
> >
> > I've got an AMD/persimmon board, with the agesa family 14 northbridge
> > on the CPU, and the SB800 southbridge. Both have 4 PCIe ports on
> > them, but coreboot isn't enabling or enumerating any of the PCIe
> > devices on the SB800. Does anyone have any ideas for me? The two
> > devices on that southbridge are an NEC USB3 and a Mini-PCIe slot.
> >
> >
> > Pasting the console output below for those interested:
> >
> >
> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> > starting...
> > POST: 0x34
> > BSP Family_Model: 00500f20
> > cpu_init_detectedx = 00000000
> > POST: 0x35
> > agesawrapper_amdinitmmio passed.
> > POST: 0x37
> > agesawrapper_amdinitreset passed.
> > POST: 0x39
> > agesawrapper_amdinitearly POST: 0x34
> > BSP Family_Model: 00500f20
> > cpu_init_detectedx = 00000001
> > POST: 0x35
> > agesawrapper_amdinitmmio passed.
> > POST: 0x37
> > agesawrapper_amdinitreset passed.
> > POST: 0x39
> > agesawrapper_amdinitearly passed.
> > SLP_TYP type was 0
> > POST: 0x40
> > agesawrapper_amdinitpost
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> >
> > EventLog: EventClass = 2, EventInfo = 8040100.
> > Param1 = a00a, Param2 = 0.
> > Param3 = 0, Param4 = 0.
> > SLP_TYP type was 0
> > error level: 4
> > POST: 0x42
> > agesawrapper_amdinitenv SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > BiosAllocateBuffer BiosHeapBaseAddr: 10000
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > SLP_TYP type was 0
> > passed.
> > POST: 0x43
> > POST: 0x44
> > POST: 0x50
> > Loading image.
> > CBFS: Looking for 'fallback/coreboot_ram'
> > CBFS: found.
> > CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1441792 bytes),
> > entry @ 0x200000
> > Jumping to image.
> > POST: 0x80
> > POST: 0x39
> > coreboot-persimmon1-278-gbbca20f-dirty Wed May 23 12:48:37 PDT 2012
> > booting...
> > POST: 0x40
> > Enumerating buses...
> > Show all devs...Before device enumeration.
> > Root Device: enabled 1
> > APIC_CLUSTER: 0: enabled 1
> > APIC: 00: enabled 1
> > PCI_DOMAIN: 0000: enabled 1
> > PCI: 00:00.0: enabled 1
> > PCI: 00:01.0: enabled 1
> > PCI: 00:01.1: enabled 1
> > PCI: 00:04.0: enabled 1
> > PCI: 00:05.0: enabled 0
> > PCI: 00:06.0: enabled 0
> > PCI: 00:07.0: enabled 0
> > PCI: 00:08.0: enabled 0
> > PCI: 00:11.0: enabled 1
> > PCI: 00:12.0: enabled 1
> > PCI: 00:12.1: enabled 1
> > PCI: 00:12.2: enabled 1
> > PCI: 00:13.0: enabled 1
> > PCI: 00:13.1: enabled 1
> > PCI: 00:13.2: enabled 1
> > PCI: 00:14.0: enabled 1
> > I2C: 00:50: enabled 1
> > I2C: 00:51: enabled 1
> > PCI: 00:14.1: enabled 1
> > PCI: 00:14.2: enabled 1
> > PCI: 00:14.3: enabled 1
> > PNP: 004e.0: enabled 0
> > PNP: 004e.3: enabled 0
> > PNP: 004e.4: enabled 0
> > PNP: 004e.5: enabled 1
> > PNP: 004e.6: enabled 0
> > PNP: 004e.a: enabled 0
> > PNP: 004e.10: enabled 1
> > PNP: 004e.11: enabled 0
> > PCI: 00:14.4: enabled 1
> > PCI: 00:14.5: enabled 1
> > PCI: 00:15.0: enabled 0
> > PCI: 00:15.1: enabled 0
> > PCI: 00:15.2: enabled 0
> > PCI: 00:15.3: enabled 0
> > PCI: 00:16.0: enabled 0
> > PCI: 00:16.2: enabled 0
> > PCI: 00:18.0: enabled 1
> > PCI: 00:18.1: enabled 1
> > PCI: 00:18.2: enabled 1
> > PCI: 00:18.3: enabled 1
> > PCI: 00:18.4: enabled 1
> > PCI: 00:18.5: enabled 1
> > PCI: 00:18.6: enabled 1
> > PCI: 00:18.7: enabled 1
> > Compare with tree...
> > Root Device: enabled 1
> > APIC_CLUSTER: 0: enabled 1
> > APIC: 00: enabled 1
> > PCI_DOMAIN: 0000: enabled 1
> > PCI: 00:00.0: enabled 1
> > PCI: 00:01.0: enabled 1
> > PCI: 00:01.1: enabled 1
> > PCI: 00:04.0: enabled 1
> > PCI: 00:05.0: enabled 0
> > PCI: 00:06.0: enabled 0
> > PCI: 00:07.0: enabled 0
> > PCI: 00:08.0: enabled 0
> > PCI: 00:11.0: enabled 1
> > PCI: 00:12.0: enabled 1
> > PCI: 00:12.1: enabled 1
> > PCI: 00:12.2: enabled 1
> > PCI: 00:13.0: enabled 1
> > PCI: 00:13.1: enabled 1
> > PCI: 00:13.2: enabled 1
> > PCI: 00:14.0: enabled 1
> > I2C: 00:50: enabled 1
> > I2C: 00:51: enabled 1
> > PCI: 00:14.1: enabled 1
> > PCI: 00:14.2: enabled 1
> > PCI: 00:14.3: enabled 1
> > PNP: 004e.0: enabled 0
> > PNP: 004e.3: enabled 0
> > PNP: 004e.4: enabled 0
> > PNP: 004e.5: enabled 1
> > PNP: 004e.6: enabled 0
> > PNP: 004e.a: enabled 0
> > PNP: 004e.10: enabled 1
> > PNP: 004e.11: enabled 0
> > PCI: 00:14.4: enabled 1
> > PCI: 00:14.5: enabled 1
> > PCI: 00:15.0: enabled 0
> > PCI: 00:15.1: enabled 0
> > PCI: 00:15.2: enabled 0
> > PCI: 00:15.3: enabled 0
> > PCI: 00:16.0: enabled 0
> > PCI: 00:16.2: enabled 0
> > PCI: 00:18.0: enabled 1
> > PCI: 00:18.1: enabled 1
> > PCI: 00:18.2: enabled 1
> > PCI: 00:18.3: enabled 1
> > PCI: 00:18.4: enabled 1
> > PCI: 00:18.5: enabled 1
> > PCI: 00:18.6: enabled 1
> > PCI: 00:18.7: enabled 1
> > Mainboard Persimmon Enable.
> > SLP_TYP type was 0
> > persimmon_enable, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
> > persimmon_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi =
> > 0x00000000
> > persimmon_enable: uma size 0x18000000, memory start 0x67000000
> > scan_static_bus for Root Device
> > APIC_CLUSTER: 0 enabled
> > PCI_DOMAIN: 0000 enabled
> > APIC_CLUSTER: 0 scanning...
> > AP siblings=1
> > CPU: APIC: 00 enabled
> > CPU: APIC: 01 enabled
> > PCI_DOMAIN: 0000 scanning...
> > PCI: pci_scan_bus for bus 00
> > POST: 0x24
> > PCI: 00:00.0 [1022/1510] ops
> > PCI: 00:00.0 [1022/1510] enabled
> > PCI: 00:01.0 [1002/9804] enabled
> > Capability: type 0x01 @ 0x50
> > Capability: type 0x10 @ 0x58
> > Capability: type 0x05 @ 0xa0
> > Capability: type 0x0d @ 0xb0
> > Capability: type 0x08 @ 0xb8
> > Capability: type 0x01 @ 0x50
> > Capability: type 0x10 @ 0x58
> > PCI: 00:04.0 subordinate bus PCI Express
> > PCI: 00:04.0 [1022/1512] enabled
> > sb800_enable() SLP_TYP type was 0
> > PCI: 00:11.0 [1002/4393] ops
> > PCI: 00:11.0 [1002/4393] enabled
> > sb800_enable() PCI: 00:12.0 [1002/4397] ops
> > PCI: 00:12.0 [1002/4397] enabled
> > sb800_enable() PCI: Static device PCI: 00:12.1 not found, disabling
> > it.
> > sb800_enable() PCI: 00:12.2 [1002/4396] ops
> > PCI: 00:12.2 [1002/4396] enabled
> > sb800_enable() PCI: 00:13.0 [1002/4397] ops
> > PCI: 00:13.0 [1002/4397] enabled
> > sb800_enable() PCI: Static device PCI: 00:13.1 not found, disabling
> > it.
> > sb800_enable() PCI: 00:13.2 [1002/4396] ops
> > PCI: 00:13.2 [1002/4396] enabled
> > sb800_enable() sm_init().
> > IOAPIC: Clearing IOAPIC at 0xfec00000
> > IOAPIC: 23 interrupts
> > IOAPIC: reg 0x00000000 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> > IOAPIC: Initializing IOAPIC at 0xfec00000
> > IOAPIC: Bootstrap Processor Local APIC = 0x00
> > IOAPIC: ID = 0x02
> > IOAPIC: 23 interrupts
> > IOAPIC: Enabling interrupts on FSB
> > IOAPIC: reg 0x00000000 value 0x00000000 0x00000700
> > IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
> > IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
> > IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
> > PCI: 00:14.0 [1002/4385] enabled
> > sb800_enable() PCI: Static device PCI: 00:14.1 not found, disabling
> > it.
> > sb800_enable() hda enabled
> > PCI: 00:14.2 [1002/4383] ops
> > PCI: 00:14.2 [1002/4383] enabled
> > sb800_enable() PCI: 00:14.3 [1002/439d] bus ops
> > PCI: 00:14.3 [1002/439d] enabled
> > sb800_enable() PCI: 00:14.4 [1002/4384] bus ops
> > PCI: 00:14.4 [1002/4384] enabled
> > sb800_enable() PCI: 00:14.5 [1002/4399] ops
> > PCI: 00:14.5 [1002/4399] enabled
> > sb800_enable() sb800_enable() sb800_enable() sb800_enable()
> > sb800_enable() sb800_enable() PCI: 00:18.0 [1022/1700] enabled
> > PCI: 00:18.1 [1022/1701] enabled
> > PCI: 00:18.2 [1022/1702] enabled
> > PCI: 00:18.3 [1022/1703] enabled
> > PCI: 00:18.4 [1022/1704] enabled
> > PCI: 00:18.5 [1022/1718] enabled
> > PCI: 00:18.6 [1022/1716] enabled
> > PCI: 00:18.7 [1022/1719] enabled
> > POST: 0x25
> > PCI: Left over static devices:
> > PCI: 00:01.1
> > PCI: Check your devicetree.cb.
> > do_pci_scan_bridge for PCI: 00:04.0
> > PCI: pci_scan_bus for bus 01
> > POST: 0x24
> > PCI: 01:00.0 [10ec/8168] enabled
> > POST: 0x25
> > PCI: pci_scan_bus returning with max=001
> > POST: 0x55
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
> >
> >
> > --
> > coreboot mailing list: coreboot at coreboot.org
> > http://www.coreboot.org/mailman/listinfo/coreboot
>
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