[coreboot] New patch to review for coreboot: 8b6008f i5000: enforce hard reset

[Sven Schnelle (svens@stackframe.org)]

Sven Schnelle (svens at stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1103

-gerrit

commit 8b6008f20e6a1aaed4512e4a506b7c49a945ba0b
Author: Sven Schnelle <svens at stackframe.org>
Date:   Sun Jun 17 14:23:35 2012 +0200

    i5000: enforce hard reset
    
    Not doing a hard reset leaves the BOFL0 register cleared, which
    prevents the BSP selection from working. To make sure we start
    with known values, use the SPAD0 register for soft reset detection.
    If there's a value other than 0, do a hard reset.
    
    Change-Id: I390e3208084cfd32d73cce439ddf2bc9d4436a62
    Signed-off-by: Sven Schnelle <svens at stackframe.org>
---
 src/northbridge/intel/i5000/halt_second_bsp.S |   31 ++++++++++++++++++++++++-
 1 files changed, 30 insertions(+), 1 deletions(-)

diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S
index a1a1b15..2dc533a 100644
--- a/src/northbridge/intel/i5000/halt_second_bsp.S
+++ b/src/northbridge/intel/i5000/halt_second_bsp.S
@@ -2,6 +2,26 @@
 
 	movl	%eax, %ebp
 
+	/* check if SPAD0 is cleared. If yes, it means this was a hard reset */
+	movl	$0x800080d0, %eax
+	movw	$0xcf8, %dx
+	outl	%eax, %dx
+
+	addw	$4, %dx
+	inl	%dx, %eax
+	cmp	$0, %eax
+	je	no_reset
+
+	/* perform hard reset */
+	movw	$0xcf9, %dx
+	movw	$0x06, %ax
+	outw	%ax, %dx
+
+loop0:	hlt
+	jmp	loop
+
+no_reset:
+
 	/* Read the semaphore register of i5000 (BOFL0).
 	   If it returns zero, it means there was already
 	   another read by another CPU */
@@ -25,5 +45,14 @@
 loop:	hlt
 	jmp	loop
 
-1:	/* Restore BIST */
+1:	/* set magic value for soft reset detection */
+	movl    $0x800080d0, %eax
+	movw    $0xcf8, %dx
+	outl    %eax, %dx
+
+	addw    $4, %dx
+	movl	$0x12345678, %eax
+	outl	%eax, %dx
+
+	/* Restore BIST */
 	mov	%ebp, %eax