[coreboot] Patch set updated for coreboot: da1f22a Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Thu Jun 28 11:02:30 CEST 2012
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/639
-gerrit
commit da1f22a5d3b6a88b08de2289111c664d7a6126d1
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Thu Jun 28 11:56:57 2012 +0300
Intel cpus: use CPU_ADDR_BITS from Kconfig during CAR
Default CPU_ADDR_BITS is 36.
For Atom (model_106cx) use 32. This model is known to
fail execution-in-place (XIP) with the default 36.
Pentium M should use 32, but doesn't even with this patch.
Some Xeon and CORE(2) models should use 38 or 40.
Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/cpu/intel/model_106cx/Kconfig | 8 ++++++++
src/cpu/intel/model_106cx/cache_as_ram.inc | 3 +--
src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +--
src/cpu/intel/model_6fx/cache_as_ram.inc | 3 +--
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 09449cb..a08f85a 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -4,3 +4,11 @@ config CPU_INTEL_MODEL_106CX
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_106CX
+
+config CPU_ADDR_BITS
+ int
+ default 32
+
+endif
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index e74e24c..74d0a99 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -23,8 +23,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#define CPU_MAXPHYADDR 32
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index 92337c8..6f13cd9 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -23,8 +23,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#define CPU_MAXPHYADDR 36
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index 61feb1d..d8d25a0 100644
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -23,8 +23,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
-#define CPU_MAXPHYADDR 36
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1)
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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