From gerrit at coreboot.org  Thu Mar  1 00:03:16 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 00:03:16 +0100
Subject: [coreboot] Patch merged into coreboot/master: 448996a Rename vendor
	identifiers in Kconfig
References: <I146384ef6dbe601ad131dada8224f43e6c18433d+0@gerrit.coreboot.org>
Message-ID: <E1S2sYG-00019K-6j@ra.coresystems.de>

the following patch was just integrated into master:
commit 448996ad975da9f3d620a2e4feb1373d1c67dfd9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Jan 10 18:45:34 2012 +0100

    Rename vendor identifiers in Kconfig
    
    Board identifiers use them without underscore, too. Unify that.
    
    Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>


See http://review.coreboot.org/674 for details.

-gerrit



From gerrit at coreboot.org  Thu Mar  1 00:03:36 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 00:03:36 +0100
Subject: [coreboot] Patch merged into coreboot/master: 20a9979 Drop support
	for BROKEN marker
References: <I9d21fdf22c9a8e0e69488fc7896f2a81bf629201+0@gerrit.coreboot.org>
Message-ID: <E1S2sYa-0001I2-2m@ra.coresystems.de>

the following patch was just integrated into master:
commit 20a9979ad93bed52c457dc263d0fe30872c9406c
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Jan 10 19:25:23 2012 +0100

    Drop support for BROKEN marker
    
    We used to support marking boards broken. We don't need that anymore.
    
    Change-Id: I9d21fdf22c9a8e0e69488fc7896f2a81bf629201
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>


See http://review.coreboot.org/675 for details.

-gerrit



From gerrit at coreboot.org  Thu Mar  1 00:04:07 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 00:04:07 +0100
Subject: [coreboot] Patch merged into coreboot/master: a4cc213 Fix lint test
	for build directories
References: <I583c2ab9a822a6f99f838778aa17ffd2d47eaed1+0@gerrit.coreboot.org>
Message-ID: <E1S2sZ5-0001Tq-Rx@ra.coresystems.de>

the following patch was just integrated into master:
commit a4cc21352ce28579466fe338dc4ee6ef3b4711e9
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Feb 25 15:33:43 2012 +0100

    Fix lint test for build directories
    
    config files are rename()d, which fails across filesystem borders.
    So force temporary config files in current directory.
    
    Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>


See http://review.coreboot.org/680 for details.

-gerrit



From gerrit at coreboot.org  Thu Mar  1 00:04:28 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 00:04:28 +0100
Subject: [coreboot] Patch merged into coreboot/master: c0f82a7 lint: create
	two classes of tests, stable and dev
References: <Iaa85d71141606d9756e29b37c7a34c2a15e573ac+0@gerrit.coreboot.org>
Message-ID: <E1S2sZQ-0001aa-CJ@ra.coresystems.de>

the following patch was just integrated into master:
commit c0f82a75b480ad90d9b4eff48a1ebf08ef592aec
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Feb 25 19:42:59 2012 +0100

    lint: create two classes of tests, stable and dev
    
    We have tests that pass (and should be enforced soonish) and those
    that don't pass yet (and thus shouldn't break the build).
    
    The plan is simple: As soon as a test passes, it's marked stable so
    things remain that way.
    
    "make lint" runs all tests,
    "make lint-stable" runs only those that shouldn't fail.
    
    Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>


See http://review.coreboot.org/681 for details.

-gerrit



From gerrit at coreboot.org  Thu Mar  1 00:04:42 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 00:04:42 +0100
Subject: [coreboot] Patch merged into coreboot/master: 5326f5c gitconfig:
	Add lint-stable as pre-commit hook
References: <Ie2a26e87f466c63b24db8dca8827057a18ac7f3e+0@gerrit.coreboot.org>
Message-ID: <E1S2sZe-0001di-2P@ra.coresystems.de>

the following patch was just integrated into master:
commit 5326f5c7e6a9d56bc0f030c81651050d6d280150
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Feb 25 19:52:45 2012 +0100

    gitconfig: Add lint-stable as pre-commit hook
    
    When configuring the tree with "make gitconfig", a pre-commit hook
    is installed that runs the stable lint tests.
    If any of these fail, the log is visible (on stdout) and the
    commit is aborted.
    
    Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>


See http://review.coreboot.org/682 for details.

-gerrit



From c-d.hailfinger.devel.2006 at gmx.net  Thu Mar  1 01:31:22 2012
From: c-d.hailfinger.devel.2006 at gmx.net (Carl-Daniel Hailfinger)
Date: Thu, 01 Mar 2012 01:31:22 +0100
Subject: [coreboot] libpayload alloc() gcc 4.6.2 bug?
In-Reply-To: <4F4DD625.6070906@georgi-clan.de>
References: <CALrs_3hpRJtuNYGvZ4XGTwrg3Ra+xQyPpFv+D29k9UEvYpGo_A@mail.gmail.com>
	<4F4DD625.6070906@georgi-clan.de>
Message-ID: <4F4EC35A.2080200@gmx.net>

Am 29.02.2012 08:39 schrieb Patrick Georgi:
> Am 28.02.2012 23:06, schrieb Marc Jones:
>> I found this bug building tint with libpayload. libpayload is built
>> with defconfig and using the same coreboot crosstools gcc. The bug
>> happens in the first call to alloc() when the first header of the
>> first region is installed. The header memory location is checked,
>> found to be 0, and then loaded with the header. The bug is that the
>> original value of the location is used after the memory was updated.
>> It should have been reloaded. It is pretty easy to see in the
>> disassembly below.
> workaround: mark setup() __attribute__((noinline))
>
> The proper fix is to clean up the various casts so the aliasing based
> optimizations in gcc do the right thing.

Can't you use __attribute__((may_alias)) for the affected variables?

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/




From kgounaris at hotmail.com  Thu Mar  1 08:18:07 2012
From: kgounaris at hotmail.com (Kostas Gounaris)
Date: Thu, 1 Mar 2012 07:18:07 +0000
Subject: [coreboot] (no subject)
Message-ID: <DUB112-W66923F992FBC0A8FE1126BE6C0@phx.gbl>


I would like to test coreboot on my PC, as I trust opensource far more than proprietary and besides the official BIOS for my MB has a couple o infuriating bugs (*) that drive me crazy. My MB is Gigabyte's GA-8I945PL-G v1.x and I am using the latest F8 BIOS. I could not find this model on the supported list, but I can see that the chipsets (945PL/IHC7) are! Is it possible to support my MB and try out coreboot on it? Thanx in advance :)
(*) First, if I enable the onboard NIC PXE BIOS by checking "Enable boot from LAN" in BIOS settings, I can not enter the BIOS setup anymore - I have to clear the CMOS. The second one is not considered a bug, but a feature : the BIOS creates an HPA on the HD and saves a copy of itself there to facilitate recovery just in case... 		 	   		  
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From gerrit at coreboot.org  Thu Mar  1 14:14:25 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Thu, 1 Mar 2012 14:14:25 +0100
Subject: [coreboot] New patch to review for filo: fa8dac1 Remove unused LZMA
	implementation
References: <I477b6425d74dd3a2ad08c3aeee891b013ce8eab4+0@gerrit.coreboot.org>
Message-ID: <I477b6425d74dd3a2ad08c3aeee891b013ce8eab4+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/689

-gerrit

commit fa8dac159f025a9870fabc6859fc4c98039081cd
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Thu Mar 1 13:57:20 2012 +0100

    Remove unused LZMA implementation
    
    This patch complements commit 466dbb3 ("Adapt filo to libpayload
    changes") by also removing the stale LZMA implementation, which is no
    longer needed. We're using the libpayload based CBFS support since.
    
    Change-Id: I477b6425d74dd3a2ad08c3aeee891b013ce8eab4
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 fs/lzma.c       |   47 -------
 fs/lzmadecode.c |  398 -------------------------------------------------------
 fs/lzmadecode.h |   67 ---------
 3 files changed, 0 insertions(+), 512 deletions(-)

diff --git a/fs/lzma.c b/fs/lzma.c
deleted file mode 100644
index a9c5f56..0000000
--- a/fs/lzma.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* 
-
-Coreboot interface to memory-saving variant of LZMA decoder
-
-(C)opyright 2006 Carl-Daniel Hailfinger
-Released under the GNU GPL v2 or later
-
-Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA
-SDK 4.42, which is written and distributed to public domain by Igor Pavlov.
-
-*/
-
-#include "lzmadecode.c"
-#define printk_warning printf
-
-
-unsigned long ulzma(unsigned char * src, unsigned char * dst)
-{
-	unsigned char properties[LZMA_PROPERTIES_SIZE];
-	UInt32 outSize;
-	SizeT inProcessed;
-	SizeT outProcessed;
-	int res;
-	CLzmaDecoderState state;
-	SizeT mallocneeds;
-	unsigned char scratchpad[15980];
-
-	memcpy(properties, src, LZMA_PROPERTIES_SIZE);
-	outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
-	if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
-		printk_warning("lzma: Incorrect stream properties.\n");
-		return 0;
-	}
-	mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
-	if (mallocneeds > 15980) {
-		printk_warning("lzma: Decoder scratchpad too small!\n");
-		return 0;
-	}
-	state.Probs = (CProb *)scratchpad;
-	res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed,
-		dst, outSize, &outProcessed);
-	if (res != 0) {
-		printk_warning("lzma: Decoding error = %d\n", res);
-		return 0;
-	}
-	return outSize;
-}
diff --git a/fs/lzmadecode.c b/fs/lzmadecode.c
deleted file mode 100644
index 65819b5..0000000
--- a/fs/lzmadecode.c
+++ /dev/null
@@ -1,398 +0,0 @@
-/*
-  LzmaDecode.c
-  LZMA Decoder (optimized for Speed version)
-  
-  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
-  http://www.7-zip.org/
-
-  LZMA SDK is licensed under two licenses:
-  1) GNU Lesser General Public License (GNU LGPL)
-  2) Common Public License (CPL)
-  It means that you can select one of these two licenses and 
-  follow rules of that license.
-
-  SPECIAL EXCEPTION:
-  Igor Pavlov, as the author of this Code, expressly permits you to 
-  statically or dynamically link your Code (or bind by name) to the 
-  interfaces of this file without subjecting your linked Code to the 
-  terms of the CPL or GNU LGPL. Any modifications or additions 
-  to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#include "lzmadecode.h"
-
-#define kNumTopBits 24
-#define kTopValue ((UInt32)1 << kNumTopBits)
-
-#define kNumBitModelTotalBits 11
-#define kBitModelTotal (1 << kNumBitModelTotalBits)
-#define kNumMoveBits 5
-
-#define RC_READ_BYTE (*Buffer++)
-
-#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
-  { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
-
-
-#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
-
-#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
- 
-
-#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
-
-#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
-#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
-#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
-
-#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
-  { UpdateBit0(p); mi <<= 1; A0; } else \
-  { UpdateBit1(p); mi = (mi + mi) + 1; A1; } 
-  
-#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)               
-
-#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
-  { int i = numLevels; res = 1; \
-  do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \
-  res -= (1 << numLevels); }
-
-
-#define kNumPosBitsMax 4
-#define kNumPosStatesMax (1 << kNumPosBitsMax)
-
-#define kLenNumLowBits 3
-#define kLenNumLowSymbols (1 << kLenNumLowBits)
-#define kLenNumMidBits 3
-#define kLenNumMidSymbols (1 << kLenNumMidBits)
-#define kLenNumHighBits 8
-#define kLenNumHighSymbols (1 << kLenNumHighBits)
-
-#define LenChoice 0
-#define LenChoice2 (LenChoice + 1)
-#define LenLow (LenChoice2 + 1)
-#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
-#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
-#define kNumLenProbs (LenHigh + kLenNumHighSymbols) 
-
-
-#define kNumStates 12
-#define kNumLitStates 7
-
-#define kStartPosModelIndex 4
-#define kEndPosModelIndex 14
-#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
-
-#define kNumPosSlotBits 6
-#define kNumLenToPosStates 4
-
-#define kNumAlignBits 4
-#define kAlignTableSize (1 << kNumAlignBits)
-
-#define kMatchMinLen 2
-
-#define IsMatch 0
-#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
-#define IsRepG0 (IsRep + kNumStates)
-#define IsRepG1 (IsRepG0 + kNumStates)
-#define IsRepG2 (IsRepG1 + kNumStates)
-#define IsRep0Long (IsRepG2 + kNumStates)
-#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
-#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
-#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
-#define LenCoder (Align + kAlignTableSize)
-#define RepLenCoder (LenCoder + kNumLenProbs)
-#define Literal (RepLenCoder + kNumLenProbs)
-
-#if Literal != LZMA_BASE_SIZE
-StopCompilingDueBUG
-#endif
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
-{
-  unsigned char prop0;
-  if (size < LZMA_PROPERTIES_SIZE)
-    return LZMA_RESULT_DATA_ERROR;
-  prop0 = propsData[0];
-  if (prop0 >= (9 * 5 * 5))
-    return LZMA_RESULT_DATA_ERROR;
-  {
-    for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
-    for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
-    propsRes->lc = prop0;
-    /*
-    unsigned char remainder = (unsigned char)(prop0 / 9);
-    propsRes->lc = prop0 % 9;
-    propsRes->pb = remainder / 5;
-    propsRes->lp = remainder % 5;
-    */
-  }
-
-  return LZMA_RESULT_OK;
-}
-
-#define kLzmaStreamWasFinishedId (-1)
-
-int LzmaDecode(CLzmaDecoderState *vs,
-    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
-    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
-{
-  CProb *p = vs->Probs;
-  SizeT nowPos = 0;
-  Byte previousByte = 0;
-  UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
-  UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
-  int lc = vs->Properties.lc;
-
-
-  int state = 0;
-  UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
-  int len = 0;
-  const Byte *Buffer;
-  const Byte *BufferLim;
-  UInt32 Range;
-  UInt32 Code;
-
-  *inSizeProcessed = 0;
-  *outSizeProcessed = 0;
-
-  {
-    UInt32 i;
-    UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
-    for (i = 0; i < numProbs; i++)
-      p[i] = kBitModelTotal >> 1;
-  }
-  
-  RC_INIT(inStream, inSize);
-
-
-  while(nowPos < outSize)
-  {
-    CProb *prob;
-    UInt32 bound;
-    int posState = (int)(
-        (nowPos 
-        )
-        & posStateMask);
-
-    prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
-    IfBit0(prob)
-    {
-      int symbol = 1;
-      UpdateBit0(prob)
-      prob = p + Literal + (LZMA_LIT_SIZE * 
-        (((
-        (nowPos 
-        )
-        & literalPosMask) << lc) + (previousByte >> (8 - lc))));
-
-      if (state >= kNumLitStates)
-      {
-        int matchByte;
-        matchByte = outStream[nowPos - rep0];
-        do
-        {
-          int bit;
-          CProb *probLit;
-          matchByte <<= 1;
-          bit = (matchByte & 0x100);
-          probLit = prob + 0x100 + bit + symbol;
-          RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
-        }
-        while (symbol < 0x100);
-      }
-      while (symbol < 0x100)
-      {
-        CProb *probLit = prob + symbol;
-        RC_GET_BIT(probLit, symbol)
-      }
-      previousByte = (Byte)symbol;
-
-      outStream[nowPos++] = previousByte;
-      if (state < 4) state = 0;
-      else if (state < 10) state -= 3;
-      else state -= 6;
-    }
-    else             
-    {
-      UpdateBit1(prob);
-      prob = p + IsRep + state;
-      IfBit0(prob)
-      {
-        UpdateBit0(prob);
-        rep3 = rep2;
-        rep2 = rep1;
-        rep1 = rep0;
-        state = state < kNumLitStates ? 0 : 3;
-        prob = p + LenCoder;
-      }
-      else
-      {
-        UpdateBit1(prob);
-        prob = p + IsRepG0 + state;
-        IfBit0(prob)
-        {
-          UpdateBit0(prob);
-          prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
-          IfBit0(prob)
-          {
-            UpdateBit0(prob);
-            
-            if (nowPos == 0)
-              return LZMA_RESULT_DATA_ERROR;
-            
-            state = state < kNumLitStates ? 9 : 11;
-            previousByte = outStream[nowPos - rep0];
-            outStream[nowPos++] = previousByte;
-
-            continue;
-          }
-          else
-          {
-            UpdateBit1(prob);
-          }
-        }
-        else
-        {
-          UInt32 distance;
-          UpdateBit1(prob);
-          prob = p + IsRepG1 + state;
-          IfBit0(prob)
-          {
-            UpdateBit0(prob);
-            distance = rep1;
-          }
-          else 
-          {
-            UpdateBit1(prob);
-            prob = p + IsRepG2 + state;
-            IfBit0(prob)
-            {
-              UpdateBit0(prob);
-              distance = rep2;
-            }
-            else
-            {
-              UpdateBit1(prob);
-              distance = rep3;
-              rep3 = rep2;
-            }
-            rep2 = rep1;
-          }
-          rep1 = rep0;
-          rep0 = distance;
-        }
-        state = state < kNumLitStates ? 8 : 11;
-        prob = p + RepLenCoder;
-      }
-      {
-        int numBits, offset;
-        CProb *probLen = prob + LenChoice;
-        IfBit0(probLen)
-        {
-          UpdateBit0(probLen);
-          probLen = prob + LenLow + (posState << kLenNumLowBits);
-          offset = 0;
-          numBits = kLenNumLowBits;
-        }
-        else
-        {
-          UpdateBit1(probLen);
-          probLen = prob + LenChoice2;
-          IfBit0(probLen)
-          {
-            UpdateBit0(probLen);
-            probLen = prob + LenMid + (posState << kLenNumMidBits);
-            offset = kLenNumLowSymbols;
-            numBits = kLenNumMidBits;
-          }
-          else
-          {
-            UpdateBit1(probLen);
-            probLen = prob + LenHigh;
-            offset = kLenNumLowSymbols + kLenNumMidSymbols;
-            numBits = kLenNumHighBits;
-          }
-        }
-        RangeDecoderBitTreeDecode(probLen, numBits, len);
-        len += offset;
-      }
-
-      if (state < 4)
-      {
-        int posSlot;
-        state += kNumLitStates;
-        prob = p + PosSlot +
-            ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << 
-            kNumPosSlotBits);
-        RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
-        if (posSlot >= kStartPosModelIndex)
-        {
-          int numDirectBits = ((posSlot >> 1) - 1);
-          rep0 = (2 | ((UInt32)posSlot & 1));
-          if (posSlot < kEndPosModelIndex)
-          {
-            rep0 <<= numDirectBits;
-            prob = p + SpecPos + rep0 - posSlot - 1;
-          }
-          else
-          {
-            numDirectBits -= kNumAlignBits;
-            do
-            {
-              RC_NORMALIZE
-              Range >>= 1;
-              rep0 <<= 1;
-              if (Code >= Range)
-              {
-                Code -= Range;
-                rep0 |= 1;
-              }
-            }
-            while (--numDirectBits != 0);
-            prob = p + Align;
-            rep0 <<= kNumAlignBits;
-            numDirectBits = kNumAlignBits;
-          }
-          {
-            int i = 1;
-            int mi = 1;
-            do
-            {
-              CProb *prob3 = prob + mi;
-              RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
-              i <<= 1;
-            }
-            while(--numDirectBits != 0);
-          }
-        }
-        else
-          rep0 = posSlot;
-        if (++rep0 == (UInt32)(0))
-        {
-          /* it's for stream version */
-          len = kLzmaStreamWasFinishedId;
-          break;
-        }
-      }
-
-      len += kMatchMinLen;
-      if (rep0 > nowPos)
-        return LZMA_RESULT_DATA_ERROR;
-
-
-      do
-      {
-        previousByte = outStream[nowPos - rep0];
-        len--;
-        outStream[nowPos++] = previousByte;
-      }
-      while(len != 0 && nowPos < outSize);
-    }
-  }
-  RC_NORMALIZE;
-
-
-  *inSizeProcessed = (SizeT)(Buffer - inStream);
-  *outSizeProcessed = nowPos;
-  return LZMA_RESULT_OK;
-}
diff --git a/fs/lzmadecode.h b/fs/lzmadecode.h
deleted file mode 100644
index dedde0d..0000000
--- a/fs/lzmadecode.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* 
-  LzmaDecode.h
-  LZMA Decoder interface
-
-  LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
-  http://www.7-zip.org/
-
-  LZMA SDK is licensed under two licenses:
-  1) GNU Lesser General Public License (GNU LGPL)
-  2) Common Public License (CPL)
-  It means that you can select one of these two licenses and 
-  follow rules of that license.
-
-  SPECIAL EXCEPTION:
-  Igor Pavlov, as the author of this code, expressly permits you to 
-  statically or dynamically link your code (or bind by name) to the 
-  interfaces of this file without subjecting your linked code to the 
-  terms of the CPL or GNU LGPL. Any modifications or additions 
-  to this file, however, are subject to the LGPL or CPL terms.
-*/
-
-#ifndef __LZMADECODE_H
-#define __LZMADECODE_H
-
-typedef unsigned char Byte;
-typedef unsigned short UInt16;
-typedef unsigned int UInt32;
-typedef UInt32 SizeT;
-
-#define CProb UInt16
-
-#define LZMA_RESULT_OK 0
-#define LZMA_RESULT_DATA_ERROR 1
-
-
-#define LZMA_BASE_SIZE 1846
-#define LZMA_LIT_SIZE 768
-
-#define LZMA_PROPERTIES_SIZE 5
-
-typedef struct _CLzmaProperties
-{
-  int lc;
-  int lp;
-  int pb;
-}CLzmaProperties;
-
-int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
-
-#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
-
-#define kLzmaNeedInitId (-2)
-
-typedef struct _CLzmaDecoderState
-{
-  CLzmaProperties Properties;
-  CProb *Probs;
-
-
-} CLzmaDecoderState;
-
-
-int LzmaDecode(CLzmaDecoderState *vs,
-    const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
-    unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
-
-#endif



From gerrit at coreboot.org  Thu Mar  1 15:42:38 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Thu, 1 Mar 2012 15:42:38 +0100
Subject: [coreboot] Patch merged into filo/master: fa8dac1 Remove unused
	LZMA implementation
References: <I477b6425d74dd3a2ad08c3aeee891b013ce8eab4+0@gerrit.coreboot.org>
Message-ID: <E1S37DK-0003jj-I9@ra.coresystems.de>

the following patch was just integrated into master:
commit fa8dac159f025a9870fabc6859fc4c98039081cd
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Thu Mar 1 13:57:20 2012 +0100

    Remove unused LZMA implementation
    
    This patch complements commit 466dbb3 ("Adapt filo to libpayload
    changes") by also removing the stale LZMA implementation, which is no
    longer needed. We're using the libpayload based CBFS support since.
    
    Change-Id: I477b6425d74dd3a2ad08c3aeee891b013ce8eab4
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Thu Mar  1 14:16:20 2012, giving +1
Reviewed-By: Peter Stuge <peter at stuge.se> at Thu Mar  1 15:42:37 2012, giving +2
See http://review.coreboot.org/689 for details.

-gerrit



From peter at stuge.se  Thu Mar  1 15:49:55 2012
From: peter at stuge.se (Peter Stuge)
Date: Thu, 1 Mar 2012 15:49:55 +0100
Subject: [coreboot] (no subject)
In-Reply-To: <DUB112-W66923F992FBC0A8FE1126BE6C0@phx.gbl>
References: <DUB112-W66923F992FBC0A8FE1126BE6C0@phx.gbl>
Message-ID: <20120301144955.13348.qmail@stuge.se>

Hi Kostas,

Kostas Gounaris wrote:
> I could not find this model on the supported list,

So your mainboard is not supported.


> but I can see that the chipsets (945PL/IHC7) are! Is it possible to
> support my MB

Sure it is. You need to spend some time on studying coreboot and the
other mainboard ports using the 945 chipset, and then you can start
developing the support for your board. Of course the community can
and will give advice during your work. I'm looking forward to your
patches!


//Peter



From mbishton at xes-inc.com  Fri Mar  2 00:54:52 2012
From: mbishton at xes-inc.com (Mike Bishton)
Date: Thu, 01 Mar 2012 17:54:52 -0600
Subject: [coreboot] Core i7 Support?
Message-ID: <4F500C4C.7080805@xes-inc.com>

Is anyone working on porting coreboot to the newer Intel platforms with 
Core i7 CPUs?

Thanks,
Mike



From marcj303 at gmail.com  Fri Mar  2 01:46:17 2012
From: marcj303 at gmail.com (Marc Jones)
Date: Thu, 1 Mar 2012 17:46:17 -0700
Subject: [coreboot] libpayload alloc() gcc 4.6.2 bug?
In-Reply-To: <4F4EC35A.2080200@gmx.net>
References: <CALrs_3hpRJtuNYGvZ4XGTwrg3Ra+xQyPpFv+D29k9UEvYpGo_A@mail.gmail.com>
	<4F4DD625.6070906@georgi-clan.de> <4F4EC35A.2080200@gmx.net>
Message-ID: <CALrs_3h+gKGeVWQK7QjyhZxkSvdkuzryKaF4KPzwW=R+pSDsBQ@mail.gmail.com>

On Wed, Feb 29, 2012 at 5:31 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Am 29.02.2012 08:39 schrieb Patrick Georgi:
>> Am 28.02.2012 23:06, schrieb Marc Jones:
>>> I found this bug building tint with libpayload. libpayload is built
>>> with defconfig and using the same coreboot crosstools gcc. The bug
>>> happens in the first call to alloc() when the first header of the
>>> first region is installed. The header memory location is checked,
>>> found to be 0, and then loaded with the header. The bug is that the
>>> original value of the location is used after the memory was updated.
>>> It should have been reloaded. It is pretty easy to see in the
>>> disassembly below.
>> workaround: mark setup() __attribute__((noinline))
>>
>> The proper fix is to clean up the various casts so the aliasing based
>> optimizations in gcc do the right thing.
>
> Can't you use __attribute__((may_alias)) for the affected variables?
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>

i think that I have resolved the issue by making the pointers
volatile. I wanted to get some comments here before I push it to
gerrit.

The asm generated:

  10b7d7:	8b 15 a0 5f 11 00    	mov    0x115fa0,%edx
  10b7dd:	81 e2 00 00 00 a8    	and    $0xa8000000,%edx
  10b7e3:	81 fa 00 00 00 a8    	cmp    $0xa8000000,%edx
  10b7e9:	74 0f                	je     10b7fa <alloc+0x3a>
  10b7eb:	25 fc ff ff 00       	and    $0xfffffc,%eax
  10b7f0:	0d 00 00 00 aa       	or     $0xaa000000,%eax
  10b7f5:	a3 a0 5f 11 00       	mov    %eax,0x115fa0
  10b7fa:	b8 a0 5f 11 00       	mov    $0x115fa0,%eax
  10b7ff:	90                   	nop
  10b800:	8b 10                	mov    (%eax),%edx
  10b802:	89 d1                	mov    %edx,%ecx


Marc

-- 
http://se-eng.com
-------------- next part --------------
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From gerrit at coreboot.org  Fri Mar  2 23:01:46 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:46 +0100
Subject: [coreboot] New patch to review for coreboot: e3d53a2 Add support
	for the Startech PEX1XS1PMINI
References: <Ie36b67f9628882d516ca34ff164f0e8918955a5b+0@gerrit.coreboot.org>
Message-ID: <Ie36b67f9628882d516ca34ff164f0e8918955a5b+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/690

-gerrit

commit e3d53a2242c3c6dd522c58ad05a74847be80fa84
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon May 9 15:19:29 2011 -0700

    Add support for the Startech PEX1XS1PMINI
    
    It has a smaller footprint than the already supported MPEX2S952
    
    Change-Id: Ie36b67f9628882d516ca34ff164f0e8918955a5b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Tested-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
---
 src/drivers/oxford/oxpcie/oxpcie.c       |    6 ++++++
 src/drivers/oxford/oxpcie/oxpcie_early.c |   26 +++++++++++++++++++++++---
 src/lib/uart8250mem.c                    |    2 ++
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 94c5b64..e1fb65f 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -54,3 +54,9 @@ static const struct pci_driver oxford_oxpcie_driver __pci_driver = {
 	.vendor = 0x1415,
 	.device = 0xc158,
 };
+
+static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc11b,
+};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 3480654..2c7767e 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -31,6 +31,9 @@
 #define OXPCIE_DEVICE \
 	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
 
+#define OXPCIE_DEVICE_3 \
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
+
 void oxford_init(void)
 {
 	u16 reg16;
@@ -72,14 +75,31 @@ void oxford_init(void)
 	while ((id == 0) || (id == 0xffffffff))
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
 
+	u32 device = OXPCIE_DEVICE; /* unknown default */
+	switch (id) {
+	case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+		/* On this device function 0 is the parallel port, and
+		 * function 3 is the serial port. So let's go look for
+		 * the UART.
+		 */
+		id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+		if (id != 0xc11b1415)
+			return;
+		device = OXPCIE_DEVICE_3;
+		break;
+	case 0xc1581415: /* e.g. Startech MPEX2S952 */
+		device = OXPCIE_DEVICE;
+		break;
+	}
+
 	/* Setup base address on device */
-	pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+	pci_write_config32(device, PCI_BASE_ADDRESS_0,
 				CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
 
 	/* Enable memory on device */
-	reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+	reg16 = pci_read_config16(device, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+	pci_write_config16(device, PCI_COMMAND, reg16);
 
 	/* Now the UART initialization */
 	u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 75d51ff..a38623e 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -117,6 +117,8 @@ u32 uart_mem_init(void)
 
 #if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
 	device_t dev = dev_find_device(0x1415, 0xc158, NULL);
+	if (!dev)
+		dev = dev_find_device(0x1415, 0xc11b, NULL);
 
 	if (dev) {
 		struct resource *res = find_resource(dev, 0x10);



From gerrit at coreboot.org  Fri Mar  2 23:01:46 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:46 +0100
Subject: [coreboot] New patch to review for coreboot: fa84bc2 move console
	includes to central console/console.h
References: <I99a9e6edac08df57c50ef3a706fdbd395cad0abc+0@gerrit.coreboot.org>
Message-ID: <I99a9e6edac08df57c50ef3a706fdbd395cad0abc+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/691

-gerrit

commit fa84bc28c757a27cf768989db805e5636219366c
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue May 10 10:46:41 2011 -0700

    move console includes to central console/console.h
    
    Because it's included everywhere anyways.
    
    Change-Id: I99a9e6edac08df57c50ef3a706fdbd395cad0abc
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/console.c         |   24 ++++++------------------
 src/cpu/x86/smm/smiutil.c     |   10 ----------
 src/include/console/console.h |   17 ++++++++++-------
 src/include/uart8250.h        |   31 ++++++++++---------------------
 4 files changed, 26 insertions(+), 56 deletions(-)

diff --git a/src/console/console.c b/src/console/console.c
index 325170d..d933668 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -22,18 +22,6 @@
 #include <arch/hlt.h>
 #include <arch/io.h>
 
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
-
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-
 #ifndef __PRE_RAM__
 #include <string.h>
 #include <pc80/mc146818rtc.h>
@@ -52,21 +40,21 @@ void console_init(void)
 	}
 }
 
-static void __console_tx_byte(unsigned char byte)
+void console_tx_flush(void)
 {
 	struct console_driver *driver;
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
-		driver->tx_byte(byte);
+		if (!driver->tx_flush)
+			continue;
+		driver->tx_flush();
 	}
 }
 
-void console_tx_flush(void)
+static void __console_tx_byte(unsigned char byte)
 {
 	struct console_driver *driver;
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
-		if (!driver->tx_flush)
-			continue;
-		driver->tx_flush();
+		driver->tx_byte(byte);
 	}
 }
 
diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c
index d9057d8..9cd63ed 100644
--- a/src/cpu/x86/smm/smiutil.c
+++ b/src/cpu/x86/smm/smiutil.c
@@ -23,18 +23,8 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-
 #include <console/console.h>
 #include <console/vtxprintf.h>
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
 static u32 serial8250mem_base_address = 0;
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8283f66..54c825c 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -24,15 +24,21 @@
 #include <console/loglevel.h>
 #include <console/post_codes.h>
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
+#include <uart8250.h>
+#endif
+#if CONFIG_USBDEBUG
+#include <usbdebug.h>
+#endif
+#if CONFIG_CONSOLE_NE2K
+#include <console/ne2k.h>
+#endif
+
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);
 unsigned char console_rx_byte(void);
 int console_tst_byte(void);
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-
 struct console_driver {
 	void (*init)(void);
 	void (*tx_byte)(unsigned char byte);
@@ -55,9 +61,6 @@ extern int console_loglevel;
  * we could use the same code on all architectures.
  */
 #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#if CONFIG_CONSOLE_SERIAL8250
-#include <uart8250.h>
-#endif
 #endif
 
 #ifndef __ROMCC__
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 3c8ea09..aa510e5 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -20,26 +20,7 @@
 #ifndef UART8250_H
 #define UART8250_H
 
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3f8
-#endif
-
-#ifndef CONFIG_TTYS0_BAUD
-#define CONFIG_TTYS0_BAUD 115200
-#endif
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-/* Line Control Settings */
-#ifndef CONFIG_TTYS0_LCS
-/* Set 8bit, 1 stop bit, no parity */
-#define CONFIG_TTYS0_LCS	0x3
-#endif
-
-#define UART_LCS	CONFIG_TTYS0_LCS
-
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
 
 /* Data */
 #define UART_RBR 0x00
@@ -126,6 +107,12 @@
 #define UART_SCR 0x07
 #define UART_SPR 0x07
 
+#if ((115200 % CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttyS0 baud rate
+#endif
+
+/* Line Control Settings */
+#define UART_LCS	CONFIG_TTYS0_LCS
 
 #ifndef __ROMCC__
 unsigned char uart8250_rx_byte(unsigned base_port);
@@ -151,6 +138,8 @@ u32 uartmem_getbaseaddr(void);
 /* and special init for OXPCIe based cards */
 void oxford_init(void);
 
-#endif
+#endif /* __ROMCC__ */
+
+#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
 
 #endif /* UART8250_H */



From gerrit at coreboot.org  Fri Mar  2 23:01:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:47 +0100
Subject: [coreboot] New patch to review for coreboot: cb562df OXPCIe:
	Reinitialize UART after pci_dev_set_resources() ... and only
	pull in early init code if the OXPCIe is used for console.
References: <I01feca3b9e8376a75c17554ba1bd200d523dff8d+0@gerrit.coreboot.org>
Message-ID: <I01feca3b9e8376a75c17554ba1bd200d523dff8d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/692

-gerrit

commit cb562dff51087dabab2e1ccebc85ef2cacb99b5a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue May 10 12:54:56 2011 -0700

    OXPCIe: Reinitialize UART after pci_dev_set_resources()
    ... and only pull in early init code if the OXPCIe is used for console.
    
    Change-Id: I01feca3b9e8376a75c17554ba1bd200d523dff8d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/drivers/oxford/oxpcie/Makefile.inc |    2 ++
 src/drivers/oxford/oxpcie/oxpcie.c     |   14 ++++++++++++--
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc
index 7d3a26f..7f4aa58 100644
--- a/src/drivers/oxford/oxpcie/Makefile.inc
+++ b/src/drivers/oxford/oxpcie/Makefile.inc
@@ -1,3 +1,5 @@
 driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
 
+ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
 romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c
+endif
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index e1fb65f..8afdd1f 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <uart8250.h>
 
 static void oxford_oxpcie_enable(device_t dev)
 {
@@ -41,9 +40,20 @@ static void oxford_oxpcie_enable(device_t dev)
 			(read32(res->base + 4) & 3));
 }
 
+
+static void oxford_oxpcie_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+
+#if CONFIG_CONSOLE_SERIAL8250MEM
+	/* Re-initialize OXPCIe base address after set_resources */
+	uartmem_init();
+#endif
+}
+
 static struct device_operations oxford_oxpcie_ops = {
 	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = oxford_oxpcie_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = oxford_oxpcie_enable,
 	.scan_bus         = 0,



From gerrit at coreboot.org  Fri Mar  2 23:01:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:48 +0100
Subject: [coreboot] New patch to review for coreboot: 8dd4a75 Don't try to
	compute I/O for empty sub buses.
References: <I098446deef96a8baae26a7ca1ddd96e626a06dc5+0@gerrit.coreboot.org>
Message-ID: <I098446deef96a8baae26a7ca1ddd96e626a06dc5+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/693

-gerrit

commit 8dd4a750815b2a52a40b8439ec17a854f04fb649
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed May 11 15:57:07 2011 -0700

    Don't try to compute I/O for empty sub buses.
    
    I am not sure if the sub bus being 0 is a problem, or if the assumption
    there has to be at least one non empty link is just wrong. It certainly
    does not hurt to add a small consistency check in either case.
    
    Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/device_util.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..47cf988 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -583,6 +583,8 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask,
 					if (subbus->link_num
 					== IOINDEX_SUBTRACTIVE_LINK(res->index))
 						break;
+					if (!subbus) /* Why can subbus be NULL?  */
+						break;
 				search_bus_resources(subbus, type_mask, type,
 						     search, gp);
 				continue;



From gerrit at coreboot.org  Fri Mar  2 23:01:49 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:49 +0100
Subject: [coreboot] New patch to review for coreboot: 05f4b03 Use -mno-sse
	to prevent overzealous gcc optimizations
References: <I14f0942f300085767ece44cec570fb15c761e88d+0@gerrit.coreboot.org>
Message-ID: <I14f0942f300085767ece44cec570fb15c761e88d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/694

-gerrit

commit 05f4b03fb64999ba373fe61256f358e5371bf8ae
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Jun 23 17:12:08 2011 -0700

    Use -mno-sse to prevent overzealous gcc optimizations
    
    The offending part that made coreboot crash with some toolchains
    was that gcc emits SSE instructions but coreboot did not enable SSE at
    that point.
    
    Since the gain for coreboot using SSE instructions is not measurable,
    let's not use SSE instructions rather than enabling SSE early on.
    One rationale behind this is that other parts of coreboot, like the
    SMM handler would need fixing because the XMM registers are not saved
    on SMM entry. Thus keep it simple.
    
    Change-Id: I14f0942f300085767ece44cec570fb15c761e88d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/xcompile/xcompile |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 4926394..f5d43d0 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -84,6 +84,10 @@ testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none
 # now:
 testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
 	       CFLAGS="$CFLAGS-Wno-unused-but-set-variable "
+# Use bfd linker instead of gold if available:
+testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
+# Prevent SSE instructions sneaking in:
+testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse "
 
 if which gcc 2>/dev/null >/dev/null; then
 	HOSTCC=gcc



From gerrit at coreboot.org  Fri Mar  2 23:01:50 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:50 +0100
Subject: [coreboot] New patch to review for coreboot: 9065d0f Add helper
	function to find a Local APIC by ID in the device tree.
References: <Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7+0@gerrit.coreboot.org>
Message-ID: <Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/695

-gerrit

commit 9065d0fbcdc23cc1e393b65306f7d5b2677555fb
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jul 18 10:41:36 2011 -0700

    Add helper function to find a Local APIC by ID in the device tree.
    
    Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/devices/device_util.c   |   20 ++++++++++++++++++++
 src/include/device/device.h |    1 +
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 47cf988..41c11ee 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -110,6 +110,26 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr)
 }
 
 /**
+ * Given a Local APIC ID, find the device structure.
+ *
+ * @param apic_id The Local APIC ID number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+device_t dev_find_lapic(unsigned apic_id)
+{
+	device_t dev, result = NULL;
+
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (dev->path.type == DEVICE_PATH_APIC &&
+		    dev->path.apic.apic_id == apic_id) {
+			result = dev;
+			break;
+		}
+	}
+	return result;
+}
+
+/**
  * Find a device of a given vendor and type.
  *
  * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
diff --git a/src/include/device/device.h b/src/include/device/device.h
index a7de0c9..c097f57 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -132,6 +132,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from);
 device_t dev_find_class (unsigned int class, device_t from);
 device_t dev_find_slot (unsigned int bus, unsigned int devfn);
 device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_lapic(unsigned apic_id);
 
 /* Debug functions */
 void print_resource_tree(struct device * root, int debug_level,



From gerrit at coreboot.org  Fri Mar  2 23:01:54 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:54 +0100
Subject: [coreboot] New patch to review for coreboot: 7a15982 Fix
	compilation with CONFIG_USE_OPTION_TABLE enabled
References: <I6c5d973442bc1770702180a8964f1bf6ed6062ed+0@gerrit.coreboot.org>
Message-ID: <I6c5d973442bc1770702180a8964f1bf6ed6062ed+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/696

-gerrit

commit 7a15982e4a7e246ca7c094a635d63c143545b1c2
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Jul 29 15:34:14 2011 -0700

    Fix compilation with CONFIG_USE_OPTION_TABLE enabled
    
    Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/Makefile.inc |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 432e24e..b930fcc 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -43,3 +43,11 @@ smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 smm-$(CONFIG_USBDEBUG) += usbdebug.c
 
 $(obj)/lib/version.ramstage.o : $(obj)/build.h
+
+OPTION_TABLE_H:=
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+OPTION_TABLE_H:=$(obj)/option_table.h
+endif
+
+$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+



From gerrit at coreboot.org  Fri Mar  2 23:01:55 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:55 +0100
Subject: [coreboot] New patch to review for coreboot: 14eb8cd Add libfdt
	implementation from u-boot.
References: <Ibad77e83090e4994125e8ac590a4f575c26d263e+0@gerrit.coreboot.org>
Message-ID: <Ibad77e83090e4994125e8ac590a4f575c26d263e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/697

-gerrit

commit 14eb8cdfd4cd8fc7acd99edff0586a86811bc9c2
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Aug 11 10:39:58 2011 -0700

    Add libfdt implementation from u-boot.
    
    This change adds a copy of top of the u-boot tree libfdt library
    (lib/libfdt directory's sha1 is
    d1c6314887c4d6712f7bd9ba7428b6517e7732e0).
    
    It is being added as is to establish the baseline for possible
    future changes. Using an external library was considered but
    decided against, as we don't want too many dependencies between
    the projects and libfdt is a fairly solid and slow changing
    library nowadays.
    
    The code is not yet being compiled.
    
    Change-Id: Ibad77e83090e4994125e8ac590a4f575c26d263e
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/lib/libfdt/Makefile          |   50 ++++
 src/lib/libfdt/README            |   23 ++
 src/lib/libfdt/fdt.c             |  226 +++++++++++++++
 src/lib/libfdt/fdt_ro.c          |  578 ++++++++++++++++++++++++++++++++++++++
 src/lib/libfdt/fdt_rw.c          |  469 +++++++++++++++++++++++++++++++
 src/lib/libfdt/fdt_strerror.c    |  100 +++++++
 src/lib/libfdt/fdt_sw.c          |  256 +++++++++++++++++
 src/lib/libfdt/fdt_wip.c         |  122 ++++++++
 src/lib/libfdt/libfdt_internal.h |   95 +++++++
 9 files changed, 1919 insertions(+), 0 deletions(-)

diff --git a/src/lib/libfdt/Makefile b/src/lib/libfdt/Makefile
new file mode 100644
index 0000000..c965577
--- /dev/null
+++ b/src/lib/libfdt/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)libfdt.o
+
+SOBJS	=
+
+COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
+
+COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
+COBJS-$(CONFIG_FIT) += $(COBJS-libfdt)
+
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/src/lib/libfdt/README b/src/lib/libfdt/README
new file mode 100644
index 0000000..e059876
--- /dev/null
+++ b/src/lib/libfdt/README
@@ -0,0 +1,23 @@
+The libfdt functionality was written by David Gibson.  The original
+source came from the git repository:
+
+URL:		git://ozlabs.org/home/dgibson/git/libfdt.git
+
+author		David Gibson <dgibson at sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+committer	David Gibson <dgibson at sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+commit		857f54e79f74429af20c2b5ecc00ee98af6a3b8b
+tree		2f648f0f88225a51ded452968d28b4402df8ade0
+parent		07a12a08005f3b5cd9337900a6551e450c07b515
+
+To adapt for u-boot usage, only the applicable files were copied and
+imported into the u-boot git repository.
+Omitted:
+* GPL - u-boot comes with a copy of the GPL license
+* test subdirectory - not directly useful for u-boot
+
+After importing, other customizations were performed.  See the git log
+for details.
+
+Jerry Van Baren
diff --git a/src/lib/libfdt/fdt.c b/src/lib/libfdt/fdt.c
new file mode 100644
index 0000000..4157b21
--- /dev/null
+++ b/src/lib/libfdt/fdt.c
@@ -0,0 +1,226 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+int fdt_check_header(const void *fdt)
+{
+	if (fdt_magic(fdt) == FDT_MAGIC) {
+		/* Complete tree */
+		if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+		if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+	} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
+		/* Unfinished sequential-write blob */
+		if (fdt_size_dt_struct(fdt) == 0)
+			return -FDT_ERR_BADSTATE;
+	} else {
+		return -FDT_ERR_BADMAGIC;
+	}
+
+	return 0;
+}
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
+{
+	const char *p;
+
+	if (fdt_version(fdt) >= 0x11)
+		if (((offset + len) < offset)
+		    || ((offset + len) > fdt_size_dt_struct(fdt)))
+			return NULL;
+
+	p = _fdt_offset_ptr(fdt, offset);
+
+	if (p + len < p)
+		return NULL;
+	return p;
+}
+
+uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
+{
+	const uint32_t *tagp, *lenp;
+	uint32_t tag;
+	int offset = startoffset;
+	const char *p;
+
+	*nextoffset = -FDT_ERR_TRUNCATED;
+	tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
+	if (!tagp)
+		return FDT_END; /* premature end */
+	tag = fdt32_to_cpu(*tagp);
+	offset += FDT_TAGSIZE;
+
+	*nextoffset = -FDT_ERR_BADSTRUCTURE;
+	switch (tag) {
+	case FDT_BEGIN_NODE:
+		/* skip name */
+		do {
+			p = fdt_offset_ptr(fdt, offset++, 1);
+		} while (p && (*p != '\0'));
+		if (!p)
+			return FDT_END; /* premature end */
+		break;
+
+	case FDT_PROP:
+		lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
+		if (!lenp)
+			return FDT_END; /* premature end */
+		/* skip-name offset, length and value */
+		offset += sizeof(struct fdt_property) - FDT_TAGSIZE
+			+ fdt32_to_cpu(*lenp);
+		break;
+
+	case FDT_END:
+	case FDT_END_NODE:
+	case FDT_NOP:
+		break;
+
+	default:
+		return FDT_END;
+	}
+
+	if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))
+		return FDT_END; /* premature end */
+
+	*nextoffset = FDT_TAGALIGN(offset);
+	return tag;
+}
+
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int _fdt_check_prop_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int fdt_next_node(const void *fdt, int offset, int *depth)
+{
+	int nextoffset = 0;
+	uint32_t tag;
+
+	if (offset >= 0)
+		if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+			return nextoffset;
+
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_PROP:
+		case FDT_NOP:
+			break;
+
+		case FDT_BEGIN_NODE:
+			if (depth)
+				(*depth)++;
+			break;
+
+		case FDT_END_NODE:
+			if (depth && ((--(*depth)) < 0))
+				return nextoffset;
+			break;
+
+		case FDT_END:
+			if ((nextoffset >= 0)
+			    || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))
+				return -FDT_ERR_NOTFOUND;
+			else
+				return nextoffset;
+		}
+	} while (tag != FDT_BEGIN_NODE);
+
+	return offset;
+}
+
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s)
+{
+	int len = strlen(s) + 1;
+	const char *last = strtab + tabsize - len;
+	const char *p;
+
+	for (p = strtab; p <= last; p++)
+		if (memcmp(p, s, len) == 0)
+			return p;
+	return NULL;
+}
+
+int fdt_move(const void *fdt, void *buf, int bufsize)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_totalsize(fdt) > bufsize)
+		return -FDT_ERR_NOSPACE;
+
+	memmove(buf, fdt, fdt_totalsize(fdt));
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_ro.c b/src/lib/libfdt/fdt_ro.c
new file mode 100644
index 0000000..1933010
--- /dev/null
+++ b/src/lib/libfdt/fdt_ro.c
@@ -0,0 +1,578 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_nodename_eq(const void *fdt, int offset,
+			    const char *s, int len)
+{
+	const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
+
+	if (! p)
+		/* short match */
+		return 0;
+
+	if (memcmp(p, s, len) != 0)
+		return 0;
+
+	if (p[len] == '\0')
+		return 1;
+	else if (!memchr(s, '@', len) && (p[len] == '@'))
+		return 1;
+	else
+		return 0;
+}
+
+const char *fdt_string(const void *fdt, int stroffset)
+{
+	return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset;
+}
+
+static int _fdt_string_eq(const void *fdt, int stroffset,
+			  const char *s, int len)
+{
+	const char *p = fdt_string(fdt, stroffset);
+
+	return (strlen(p) == len) && (memcmp(p, s, len) == 0);
+}
+
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
+{
+	FDT_CHECK_HEADER(fdt);
+	*address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
+	*size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size);
+	return 0;
+}
+
+int fdt_num_mem_rsv(const void *fdt)
+{
+	int i = 0;
+
+	while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0)
+		i++;
+	return i;
+}
+
+static int _nextprop(const void *fdt, int offset)
+{
+	uint32_t tag;
+	int nextoffset;
+
+	do {
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_END:
+			if (nextoffset >= 0)
+				return -FDT_ERR_BADSTRUCTURE;
+			else
+				return nextoffset;
+
+		case FDT_PROP:
+			return offset;
+		}
+		offset = nextoffset;
+	} while (tag == FDT_NOP);
+
+	return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_subnode_offset_namelen(const void *fdt, int offset,
+			       const char *name, int namelen)
+{
+	int depth;
+
+	FDT_CHECK_HEADER(fdt);
+
+	for (depth = 0;
+	     (offset >= 0) && (depth >= 0);
+	     offset = fdt_next_node(fdt, offset, &depth))
+		if ((depth == 1)
+		    && _fdt_nodename_eq(fdt, offset, name, namelen))
+			return offset;
+
+	if (depth < 0)
+		return -FDT_ERR_NOTFOUND;
+	return offset; /* error */
+}
+
+int fdt_subnode_offset(const void *fdt, int parentoffset,
+		       const char *name)
+{
+	return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_path_offset(const void *fdt, const char *path)
+{
+	const char *end = path + strlen(path);
+	const char *p = path;
+	int offset = 0;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* see if we have an alias */
+	if (*path != '/') {
+		const char *q = strchr(path, '/');
+
+		if (!q)
+			q = end;
+
+		p = fdt_get_alias_namelen(fdt, p, q - p);
+		if (!p)
+			return -FDT_ERR_BADPATH;
+		offset = fdt_path_offset(fdt, p);
+
+		p = q;
+	}
+
+	while (*p) {
+		const char *q;
+
+		while (*p == '/')
+			p++;
+		if (! *p)
+			return offset;
+		q = strchr(p, '/');
+		if (! q)
+			q = end;
+
+		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
+		if (offset < 0)
+			return offset;
+
+		p = q;
+	}
+
+	return offset;
+}
+
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
+{
+	const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
+	int err;
+
+	if (((err = fdt_check_header(fdt)) != 0)
+	    || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+			goto fail;
+
+	if (len)
+		*len = strlen(nh->name);
+
+	return nh->name;
+
+ fail:
+	if (len)
+		*len = err;
+	return NULL;
+}
+
+int fdt_first_property_offset(const void *fdt, int nodeoffset)
+{
+	int offset;
+
+	if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+int fdt_next_property_offset(const void *fdt, int offset)
+{
+	if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp)
+{
+	int err;
+	const struct fdt_property *prop;
+
+	if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) {
+		if (lenp)
+			*lenp = err;
+		return NULL;
+	}
+
+	prop = _fdt_offset_ptr(fdt, offset);
+
+	if (lenp)
+		*lenp = fdt32_to_cpu(prop->len);
+
+	return prop;
+}
+
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int offset,
+						    const char *name,
+						    int namelen, int *lenp)
+{
+	for (offset = fdt_first_property_offset(fdt, offset);
+	     (offset >= 0);
+	     (offset = fdt_next_property_offset(fdt, offset))) {
+		const struct fdt_property *prop;
+
+		if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) {
+			offset = -FDT_ERR_INTERNAL;
+			break;
+		}
+		if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff),
+				   name, namelen))
+			return prop;
+	}
+
+	if (lenp)
+		*lenp = offset;
+	return NULL;
+}
+
+const struct fdt_property *fdt_get_property(const void *fdt,
+					    int nodeoffset,
+					    const char *name, int *lenp)
+{
+	return fdt_get_property_namelen(fdt, nodeoffset, name,
+					strlen(name), lenp);
+}
+
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp);
+	if (! prop)
+		return NULL;
+
+	return prop->data;
+}
+
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_by_offset(fdt, offset, lenp);
+	if (!prop)
+		return NULL;
+	if (namep)
+		*namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+	return prop->data;
+}
+
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp)
+{
+	return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
+}
+
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
+{
+	const uint32_t *php;
+	int len;
+
+	/* FIXME: This is a bit sub-optimal, since we potentially scan
+	 * over all the properties twice. */
+	php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
+	if (!php || (len != sizeof(*php))) {
+		php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
+		if (!php || (len != sizeof(*php)))
+			return 0;
+	}
+
+	return fdt32_to_cpu(*php);
+}
+
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen)
+{
+	int aliasoffset;
+
+	aliasoffset = fdt_path_offset(fdt, "/aliases");
+	if (aliasoffset < 0)
+		return NULL;
+
+	return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
+}
+
+const char *fdt_get_alias(const void *fdt, const char *name)
+{
+	return fdt_get_alias_namelen(fdt, name, strlen(name));
+}
+
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
+{
+	int pdepth = 0, p = 0;
+	int offset, depth, namelen;
+	const char *name;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (buflen < 2)
+		return -FDT_ERR_NOSPACE;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		while (pdepth > depth) {
+			do {
+				p--;
+			} while (buf[p-1] != '/');
+			pdepth--;
+		}
+
+		if (pdepth >= depth) {
+			name = fdt_get_name(fdt, offset, &namelen);
+			if (!name)
+				return namelen;
+			if ((p + namelen + 1) <= buflen) {
+				memcpy(buf + p, name, namelen);
+				p += namelen;
+				buf[p++] = '/';
+				pdepth++;
+			}
+		}
+
+		if (offset == nodeoffset) {
+			if (pdepth < (depth + 1))
+				return -FDT_ERR_NOSPACE;
+
+			if (p > 1) /* special case so that root path is "/", not "" */
+				p--;
+			buf[p] = '\0';
+			return 0;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth)
+{
+	int offset, depth;
+	int supernodeoffset = -FDT_ERR_INTERNAL;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (supernodedepth < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (depth == supernodedepth)
+			supernodeoffset = offset;
+
+		if (offset == nodeoffset) {
+			if (nodedepth)
+				*nodedepth = depth;
+
+			if (supernodedepth > depth)
+				return -FDT_ERR_NOTFOUND;
+			else
+				return supernodeoffset;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_depth(const void *fdt, int nodeoffset)
+{
+	int nodedepth;
+	int err;
+
+	err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
+	if (err)
+		return (err < 0) ? err : -FDT_ERR_INTERNAL;
+	return nodedepth;
+}
+
+int fdt_parent_offset(const void *fdt, int nodeoffset)
+{
+	int nodedepth = fdt_node_depth(fdt, nodeoffset);
+
+	if (nodedepth < 0)
+		return nodedepth;
+	return fdt_supernode_atdepth_offset(fdt, nodeoffset,
+					    nodedepth - 1, NULL);
+}
+
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen)
+{
+	int offset;
+	const void *val;
+	int len;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_getprop(), then if that didn't
+	 * find what we want, we scan over them again making our way
+	 * to the next node.  Still it's the easiest to implement
+	 * approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		val = fdt_getprop(fdt, offset, propname, &len);
+		if (val && (len == proplen)
+		    && (memcmp(val, propval, len) == 0))
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
+{
+	int offset;
+
+	if ((phandle == 0) || (phandle == -1))
+		return -FDT_ERR_BADPHANDLE;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we
+	 * potentially scan each property of a node in
+	 * fdt_get_phandle(), then if that didn't find what
+	 * we want, we scan over them again making our way to the next
+	 * node.  Still it's the easiest to implement approach;
+	 * performance can come later. */
+	for (offset = fdt_next_node(fdt, -1, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		if (fdt_get_phandle(fdt, offset) == phandle)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+static int _fdt_stringlist_contains(const char *strlist, int listlen,
+				    const char *str)
+{
+	int len = strlen(str);
+	const char *p;
+
+	while (listlen >= len) {
+		if (memcmp(str, strlist, len+1) == 0)
+			return 1;
+		p = memchr(strlist, '\0', listlen);
+		if (!p)
+			return 0; /* malformed strlist.. */
+		listlen -= (p-strlist) + 1;
+		strlist = p + 1;
+	}
+	return 0;
+}
+
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible)
+{
+	const void *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
+	if (!prop)
+		return len;
+	if (_fdt_stringlist_contains(prop, len, compatible))
+		return 0;
+	else
+		return 1;
+}
+
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible)
+{
+	int offset, err;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_node_check_compatible(), then if
+	 * that didn't find what we want, we scan over them again
+	 * making our way to the next node.  Still it's the easiest to
+	 * implement approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		err = fdt_node_check_compatible(fdt, offset, compatible);
+		if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
+			return err;
+		else if (err == 0)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
diff --git a/src/lib/libfdt/fdt_rw.c b/src/lib/libfdt/fdt_rw.c
new file mode 100644
index 0000000..5c27a67
--- /dev/null
+++ b/src/lib/libfdt/fdt_rw.c
@@ -0,0 +1,469 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_blocks_misordered(const void *fdt,
+			      int mem_rsv_size, int struct_size)
+{
+	return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
+		|| (fdt_off_dt_struct(fdt) <
+		    (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
+		|| (fdt_off_dt_strings(fdt) <
+		    (fdt_off_dt_struct(fdt) + struct_size))
+		|| (fdt_totalsize(fdt) <
+		    (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
+}
+
+static int _fdt_rw_check_header(void *fdt)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_version(fdt) < 17)
+		return -FDT_ERR_BADVERSION;
+	if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
+				   fdt_size_dt_struct(fdt)))
+		return -FDT_ERR_BADLAYOUT;
+	if (fdt_version(fdt) > 17)
+		fdt_set_version(fdt, 17);
+
+	return 0;
+}
+
+#define FDT_RW_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = _fdt_rw_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+static inline int _fdt_data_size(void *fdt)
+{
+	return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+}
+
+static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
+{
+	char *p = splicepoint;
+	char *end = (char *)fdt + _fdt_data_size(fdt);
+
+	if (((p + oldlen) < p) || ((p + oldlen) > end))
+		return -FDT_ERR_BADOFFSET;
+	if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
+		return -FDT_ERR_NOSPACE;
+	memmove(p + newlen, p + oldlen, end - p - oldlen);
+	return 0;
+}
+
+static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
+			       int oldn, int newn)
+{
+	int delta = (newn - oldn) * sizeof(*p);
+	int err;
+	err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
+	if (err)
+		return err;
+	fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_struct(void *fdt, void *p,
+			      int oldlen, int newlen)
+{
+	int delta = newlen - oldlen;
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
+		return err;
+
+	fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_string(void *fdt, int newlen)
+{
+	void *p = (char *)fdt
+		+ fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, 0, newlen)))
+		return err;
+
+	fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
+	const char *p;
+	char *new;
+	int len = strlen(s) + 1;
+	int err;
+
+	p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s);
+	if (p)
+		/* found it */
+		return (p - strtab);
+
+	new = strtab + fdt_size_dt_strings(fdt);
+	err = _fdt_splice_string(fdt, len);
+	if (err)
+		return err;
+
+	memcpy(new, s, len);
+	return (new - strtab);
+}
+
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
+	err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
+	if (err)
+		return err;
+
+	re->address = cpu_to_fdt64(address);
+	re->size = cpu_to_fdt64(size);
+	return 0;
+}
+
+int fdt_del_mem_rsv(void *fdt, int n)
+{
+	struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	if (n >= fdt_num_mem_rsv(fdt))
+		return -FDT_ERR_NOTFOUND;
+
+	err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
+	if (err)
+		return err;
+	return 0;
+}
+
+static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
+				int len, struct fdt_property **prop)
+{
+	int oldlen;
+	int err;
+
+	*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+	if (! (*prop))
+		return oldlen;
+
+	if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
+				      FDT_TAGALIGN(len))))
+		return err;
+
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
+			     int len, struct fdt_property **prop)
+{
+	int proplen;
+	int nextoffset;
+	int namestroff;
+	int err;
+
+	if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return nextoffset;
+
+	namestroff = _fdt_find_add_string(fdt, name);
+	if (namestroff < 0)
+		return namestroff;
+
+	*prop = _fdt_offset_ptr_w(fdt, nextoffset);
+	proplen = sizeof(**prop) + FDT_TAGALIGN(len);
+
+	err = _fdt_splice_struct(fdt, *prop, 0, proplen);
+	if (err)
+		return err;
+
+	(*prop)->tag = cpu_to_fdt32(FDT_PROP);
+	(*prop)->nameoff = cpu_to_fdt32(namestroff);
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+int fdt_set_name(void *fdt, int nodeoffset, const char *name)
+{
+	char *namep;
+	int oldlen, newlen;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
+	if (!namep)
+		return oldlen;
+
+	newlen = strlen(name);
+
+	err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
+				 FDT_TAGALIGN(newlen+1));
+	if (err)
+		return err;
+
+	memcpy(namep, name, newlen+1);
+	return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len)
+{
+	struct fdt_property *prop;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
+	if (err == -FDT_ERR_NOTFOUND)
+		err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+	if (err)
+		return err;
+
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_delprop(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len, proplen;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	proplen = sizeof(*prop) + FDT_TAGALIGN(len);
+	return _fdt_splice_struct(fdt, prop, proplen, 0);
+}
+
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen)
+{
+	struct fdt_node_header *nh;
+	int offset, nextoffset;
+	int nodelen;
+	int err;
+	uint32_t tag;
+	uint32_t *endtag;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
+	if (offset >= 0)
+		return -FDT_ERR_EXISTS;
+	else if (offset != -FDT_ERR_NOTFOUND)
+		return offset;
+
+	/* Try to place the new node after the parent's properties */
+	fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+	} while ((tag == FDT_PROP) || (tag == FDT_NOP));
+
+	nh = _fdt_offset_ptr_w(fdt, offset);
+	nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
+
+	err = _fdt_splice_struct(fdt, nh, 0, nodelen);
+	if (err)
+		return err;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
+	memcpy(nh->name, name, namelen);
+	endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+	*endtag = cpu_to_fdt32(FDT_END_NODE);
+
+	return offset;
+}
+
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
+{
+	return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_del_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
+				  endoffset - nodeoffset, 0);
+}
+
+static void _fdt_packblocks(const char *old, char *new,
+			    int mem_rsv_size, int struct_size)
+{
+	int mem_rsv_off, struct_off, strings_off;
+
+	mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
+	struct_off = mem_rsv_off + mem_rsv_size;
+	strings_off = struct_off + struct_size;
+
+	memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
+	fdt_set_off_mem_rsvmap(new, mem_rsv_off);
+
+	memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
+	fdt_set_off_dt_struct(new, struct_off);
+	fdt_set_size_dt_struct(new, struct_size);
+
+	memmove(new + strings_off, old + fdt_off_dt_strings(old),
+		fdt_size_dt_strings(old));
+	fdt_set_off_dt_strings(new, strings_off);
+	fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
+}
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize)
+{
+	int err;
+	int mem_rsv_size, struct_size;
+	int newsize;
+	const char *fdtstart = fdt;
+	const char *fdtend = fdtstart + fdt_totalsize(fdt);
+	char *tmp;
+
+	FDT_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+
+	if (fdt_version(fdt) >= 17) {
+		struct_size = fdt_size_dt_struct(fdt);
+	} else {
+		struct_size = 0;
+		while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
+			;
+		if (struct_size < 0)
+			return struct_size;
+	}
+
+	if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
+		/* no further work necessary */
+		err = fdt_move(fdt, buf, bufsize);
+		if (err)
+			return err;
+		fdt_set_version(buf, 17);
+		fdt_set_size_dt_struct(buf, struct_size);
+		fdt_set_totalsize(buf, bufsize);
+		return 0;
+	}
+
+	/* Need to reorder */
+	newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+		+ struct_size + fdt_size_dt_strings(fdt);
+
+	if (bufsize < newsize)
+		return -FDT_ERR_NOSPACE;
+
+	/* First attempt to build converted tree at beginning of buffer */
+	tmp = buf;
+	/* But if that overlaps with the old tree... */
+	if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
+		/* Try right after the old tree instead */
+		tmp = (char *)(uintptr_t)fdtend;
+		if ((tmp + newsize) > ((char *)buf + bufsize))
+			return -FDT_ERR_NOSPACE;
+	}
+
+	_fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size);
+	memmove(buf, tmp, newsize);
+
+	fdt_set_magic(buf, FDT_MAGIC);
+	fdt_set_totalsize(buf, bufsize);
+	fdt_set_version(buf, 17);
+	fdt_set_last_comp_version(buf, 16);
+	fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
+
+	return 0;
+}
+
+int fdt_pack(void *fdt)
+{
+	int mem_rsv_size;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+	_fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
+	fdt_set_totalsize(fdt, _fdt_data_size(fdt));
+
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_strerror.c b/src/lib/libfdt/fdt_strerror.c
new file mode 100644
index 0000000..9b00c3a
--- /dev/null
+++ b/src/lib/libfdt/fdt_strerror.c
@@ -0,0 +1,100 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+struct fdt_errtabent {
+	const char *str;
+};
+
+#define FDT_ERRTABENT(val) \
+	[(val)] = { .str = #val, }
+
+static struct fdt_errtabent fdt_errtable[] = {
+	FDT_ERRTABENT(FDT_ERR_NOTFOUND),
+	FDT_ERRTABENT(FDT_ERR_EXISTS),
+	FDT_ERRTABENT(FDT_ERR_NOSPACE),
+
+	FDT_ERRTABENT(FDT_ERR_BADOFFSET),
+	FDT_ERRTABENT(FDT_ERR_BADPATH),
+	FDT_ERRTABENT(FDT_ERR_BADSTATE),
+
+	FDT_ERRTABENT(FDT_ERR_TRUNCATED),
+	FDT_ERRTABENT(FDT_ERR_BADMAGIC),
+	FDT_ERRTABENT(FDT_ERR_BADVERSION),
+	FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
+	FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
+};
+#define FDT_ERRTABSIZE	(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
+
+const char *fdt_strerror(int errval)
+{
+	if (errval > 0)
+		return "<valid offset/length>";
+	else if (errval == 0)
+		return "<no error>";
+	else if (errval > -FDT_ERRTABSIZE) {
+		const char *s = fdt_errtable[-errval].str;
+
+		if (s)
+			return s;
+	}
+
+	return "<unknown error>";
+}
diff --git a/src/lib/libfdt/fdt_sw.c b/src/lib/libfdt/fdt_sw.c
new file mode 100644
index 0000000..55ebebf
--- /dev/null
+++ b/src/lib/libfdt/fdt_sw.c
@@ -0,0 +1,256 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+static int _fdt_sw_check_header(void *fdt)
+{
+	if (fdt_magic(fdt) != FDT_SW_MAGIC)
+		return -FDT_ERR_BADMAGIC;
+	/* FIXME: should check more details about the header state */
+	return 0;
+}
+
+#define FDT_SW_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = _fdt_sw_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+static void *_fdt_grab_space(void *fdt, size_t len)
+{
+	int offset = fdt_size_dt_struct(fdt);
+	int spaceleft;
+
+	spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
+		- fdt_size_dt_strings(fdt);
+
+	if ((offset + len < offset) || (offset + len > spaceleft))
+		return NULL;
+
+	fdt_set_size_dt_struct(fdt, offset + len);
+	return _fdt_offset_ptr_w(fdt, offset);
+}
+
+int fdt_create(void *buf, int bufsize)
+{
+	void *fdt = buf;
+
+	if (bufsize < sizeof(struct fdt_header))
+		return -FDT_ERR_NOSPACE;
+
+	memset(buf, 0, bufsize);
+
+	fdt_set_magic(fdt, FDT_SW_MAGIC);
+	fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
+	fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
+	fdt_set_totalsize(fdt,  bufsize);
+
+	fdt_set_off_mem_rsvmap(fdt, FDT_ALIGN(sizeof(struct fdt_header),
+					      sizeof(struct fdt_reserve_entry)));
+	fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
+	fdt_set_off_dt_strings(fdt, bufsize);
+
+	return 0;
+}
+
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int offset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	if (fdt_size_dt_struct(fdt))
+		return -FDT_ERR_BADSTATE;
+
+	offset = fdt_off_dt_struct(fdt);
+	if ((offset + sizeof(*re)) > fdt_totalsize(fdt))
+		return -FDT_ERR_NOSPACE;
+
+	re = (struct fdt_reserve_entry *)((char *)fdt + offset);
+	re->address = cpu_to_fdt64(addr);
+	re->size = cpu_to_fdt64(size);
+
+	fdt_set_off_dt_struct(fdt, offset + sizeof(*re));
+
+	return 0;
+}
+
+int fdt_finish_reservemap(void *fdt)
+{
+	return fdt_add_reservemap_entry(fdt, 0, 0);
+}
+
+int fdt_begin_node(void *fdt, const char *name)
+{
+	struct fdt_node_header *nh;
+	int namelen = strlen(name) + 1;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
+	if (! nh)
+		return -FDT_ERR_NOSPACE;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memcpy(nh->name, name, namelen);
+	return 0;
+}
+
+int fdt_end_node(void *fdt)
+{
+	uint32_t *en;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	en = _fdt_grab_space(fdt, FDT_TAGSIZE);
+	if (! en)
+		return -FDT_ERR_NOSPACE;
+
+	*en = cpu_to_fdt32(FDT_END_NODE);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_totalsize(fdt);
+	const char *p;
+	int strtabsize = fdt_size_dt_strings(fdt);
+	int len = strlen(s) + 1;
+	int struct_top, offset;
+
+	p = _fdt_find_string(strtab - strtabsize, strtabsize, s);
+	if (p)
+		return p - strtab;
+
+	/* Add it */
+	offset = -strtabsize - len;
+	struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	if (fdt_totalsize(fdt) + offset < struct_top)
+		return 0; /* no more room :( */
+
+	memcpy(strtab + offset, s, len);
+	fdt_set_size_dt_strings(fdt, strtabsize + len);
+	return offset;
+}
+
+int fdt_property(void *fdt, const char *name, const void *val, int len)
+{
+	struct fdt_property *prop;
+	int nameoff;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nameoff = _fdt_find_add_string(fdt, name);
+	if (nameoff == 0)
+		return -FDT_ERR_NOSPACE;
+
+	prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
+	if (! prop)
+		return -FDT_ERR_NOSPACE;
+
+	prop->tag = cpu_to_fdt32(FDT_PROP);
+	prop->nameoff = cpu_to_fdt32(nameoff);
+	prop->len = cpu_to_fdt32(len);
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_finish(void *fdt)
+{
+	char *p = (char *)fdt;
+	uint32_t *end;
+	int oldstroffset, newstroffset;
+	uint32_t tag;
+	int offset, nextoffset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	/* Add terminator */
+	end = _fdt_grab_space(fdt, sizeof(*end));
+	if (! end)
+		return -FDT_ERR_NOSPACE;
+	*end = cpu_to_fdt32(FDT_END);
+
+	/* Relocate the string table */
+	oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);
+	newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));
+	fdt_set_off_dt_strings(fdt, newstroffset);
+
+	/* Walk the structure, correcting string offsets */
+	offset = 0;
+	while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {
+		if (tag == FDT_PROP) {
+			struct fdt_property *prop =
+				_fdt_offset_ptr_w(fdt, offset);
+			int nameoff;
+
+			nameoff = fdt32_to_cpu(prop->nameoff);
+			nameoff += fdt_size_dt_strings(fdt);
+			prop->nameoff = cpu_to_fdt32(nameoff);
+		}
+		offset = nextoffset;
+	}
+	if (nextoffset < 0)
+		return nextoffset;
+
+	/* Finally, adjust the header */
+	fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));
+	fdt_set_magic(fdt, FDT_MAGIC);
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_wip.c b/src/lib/libfdt/fdt_wip.c
new file mode 100644
index 0000000..e373677
--- /dev/null
+++ b/src/lib/libfdt/fdt_wip.c
@@ -0,0 +1,122 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len)
+{
+	void *propval;
+	int proplen;
+
+	propval = fdt_getprop_w(fdt, nodeoffset, name, &proplen);
+	if (! propval)
+		return proplen;
+
+	if (proplen != len)
+		return -FDT_ERR_NOSPACE;
+
+	memcpy(propval, val, len);
+	return 0;
+}
+
+static void _fdt_nop_region(void *start, int len)
+{
+	uint32_t *p;
+
+	for (p = start; (char *)p < ((char *)start + len); p++)
+		*p = cpu_to_fdt32(FDT_NOP);
+}
+
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len;
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	_fdt_nop_region(prop, len + sizeof(*prop));
+
+	return 0;
+}
+
+int _fdt_node_end_offset(void *fdt, int offset)
+{
+	int depth = 0;
+
+	while ((offset >= 0) && (depth >= 0))
+		offset = fdt_next_node(fdt, offset, &depth);
+
+	return offset;
+}
+
+int fdt_nop_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	_fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0),
+			endoffset - nodeoffset);
+	return 0;
+}
diff --git a/src/lib/libfdt/libfdt_internal.h b/src/lib/libfdt/libfdt_internal.h
new file mode 100644
index 0000000..381133b
--- /dev/null
+++ b/src/lib/libfdt/libfdt_internal.h
@@ -0,0 +1,95 @@
+#ifndef _LIBFDT_INTERNAL_H
+#define _LIBFDT_INTERNAL_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fdt.h>
+
+#define FDT_ALIGN(x, a)		(((x) + (a) - 1) & ~((a) - 1))
+#define FDT_TAGALIGN(x)		(FDT_ALIGN((x), FDT_TAGSIZE))
+
+#define FDT_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = fdt_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+int _fdt_check_node_offset(const void *fdt, int offset);
+int _fdt_check_prop_offset(const void *fdt, int offset);
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
+int _fdt_node_end_offset(void *fdt, int nodeoffset);
+
+static inline const void *_fdt_offset_ptr(const void *fdt, int offset)
+{
+	return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;
+}
+
+static inline void *_fdt_offset_ptr_w(void *fdt, int offset)
+{
+	return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset);
+}
+
+static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n)
+{
+	const struct fdt_reserve_entry *rsv_table =
+		(const struct fdt_reserve_entry *)
+		((const char *)fdt + fdt_off_mem_rsvmap(fdt));
+
+	return rsv_table + n;
+}
+static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n)
+{
+	return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n);
+}
+
+#define FDT_SW_MAGIC		(~FDT_MAGIC)
+
+#endif /* _LIBFDT_INTERNAL_H */



From gerrit at coreboot.org  Fri Mar  2 23:01:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:56 +0100
Subject: [coreboot] New patch to review for coreboot: 66caa9d Fix dependency
	problem for uart8250.c as well
References: <I828956ab2e05c48d20c2f7c55616cc8fa19e1227+0@gerrit.coreboot.org>
Message-ID: <I828956ab2e05c48d20c2f7c55616cc8fa19e1227+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/698

-gerrit

commit 66caa9db4f4cbcf112200fcd649e8444f1e082a6
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Aug 11 14:51:31 2011 -0700

    Fix dependency problem for uart8250.c as well
    
    If you build in parallel, option_table.h will occasionally not be there yet
    and the build will fail.
    
    Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/Makefile.inc |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b930fcc..906dfae 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -50,4 +50,5 @@ OPTION_TABLE_H:=$(obj)/option_table.h
 endif
 
 $(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)
 



From gerrit at coreboot.org  Fri Mar  2 23:01:57 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:57 +0100
Subject: [coreboot] New patch to review for coreboot: cb7a365 Add fdt
	interface from u-boot.
References: <Ifb2345dff69d0d4abd1248e4222b8c48b234c82c+0@gerrit.coreboot.org>
Message-ID: <Ifb2345dff69d0d4abd1248e4222b8c48b234c82c+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/699

-gerrit

commit cb7a365e73baaff003e6f502e476bb68868805cd
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Aug 11 15:53:52 2011 -0700

    Add fdt interface from u-boot.
    
    This change adds a copy of top of the u-boot tree fdt interface (all
    u-boot.git:include/*fdt*.h files as of sha1
    fa82f871c8dbc9a15e8dc274b3f99dd5fa0da458)
    
    The files are being added as is to establish the baseline for possible
    future changes.
    
    The code is not yet being compiled.
    
    Change-Id: Ifb2345dff69d0d4abd1248e4222b8c48b234c82c
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/fdt/fdt.h         |   62 ++
 src/include/fdt/fdt_support.h |  100 ++++
 src/include/fdt/libfdt.h      | 1235 +++++++++++++++++++++++++++++++++++++++++
 src/include/fdt/libfdt_env.h  |   33 ++
 4 files changed, 1430 insertions(+), 0 deletions(-)

diff --git a/src/include/fdt/fdt.h b/src/include/fdt/fdt.h
new file mode 100644
index 0000000..c51212e
--- /dev/null
+++ b/src/include/fdt/fdt.h
@@ -0,0 +1,62 @@
+#ifndef _FDT_H
+#define _FDT_H
+
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	uint32_t magic;			 /* magic word FDT_MAGIC */
+	uint32_t totalsize;		 /* total size of DT block */
+	uint32_t off_dt_struct;		 /* offset to structure */
+	uint32_t off_dt_strings;	 /* offset to strings */
+	uint32_t off_mem_rsvmap;	 /* offset to memory reserve map */
+	uint32_t version;		 /* format version */
+	uint32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	uint32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	uint32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	uint32_t size_dt_struct;	 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	uint64_t address;
+	uint64_t size;
+};
+
+struct fdt_node_header {
+	uint32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	uint32_t tag;
+	uint32_t len;
+	uint32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(uint32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(uint32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(uint32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(uint32_t))
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+#endif /* _FDT_H */
diff --git a/src/include/fdt/fdt_support.h b/src/include/fdt/fdt_support.h
new file mode 100644
index 0000000..863024f
--- /dev/null
+++ b/src/include/fdt/fdt_support.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren at cideas.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <fdt.h>
+
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+				const u32 dflt);
+int fdt_chosen(void *fdt, int force);
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
+void do_fixup_by_path(void *fdt, const char *path, const char *prop,
+		      const void *val, int len, int create);
+void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
+			  u32 val, int create);
+void do_fixup_by_prop(void *fdt,
+		      const char *pname, const void *pval, int plen,
+		      const char *prop, const void *val, int len,
+		      int create);
+void do_fixup_by_prop_u32(void *fdt,
+			  const char *pname, const void *pval, int plen,
+			  const char *prop, u32 val, int create);
+void do_fixup_by_compat(void *fdt, const char *compat,
+			const char *prop, const void *val, int len, int create);
+void do_fixup_by_compat_u32(void *fdt, const char *compat,
+			    const char *prop, u32 val, int create);
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+void fdt_fixup_ethernet(void *fdt);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* CONFIG_HAS_FSL_DR_USB */
+
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+
+void set_working_fdt_addr(void *addr);
+int fdt_resize(void *blob);
+int fdt_increase_size(void *fdt, int add_len);
+
+int fdt_fixup_nor_flash_size(void *blob);
+
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
+int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+			      u64 addr);
+u64 fdt_get_base_address(void *fdt, int node);
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/src/include/fdt/libfdt.h b/src/include/fdt/libfdt.h
new file mode 100644
index 0000000..de82ed5
--- /dev/null
+++ b/src/include/fdt/libfdt.h
@@ -0,0 +1,1235 @@
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <libfdt_env.h>
+#include <fdt.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION	0x10
+#define FDT_LAST_SUPPORTED_VERSION	0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND	1
+	/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS		2
+	/* FDT_ERR_EXISTS: Attemped to create a node or property which
+	 * already exists */
+#define FDT_ERR_NOSPACE		3
+	/* FDT_ERR_NOSPACE: Operation needed to expand the device
+	 * tree, but its buffer did not have sufficient space to
+	 * contain the expanded tree. Use fdt_open_into() to move the
+	 * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET	4
+	/* FDT_ERR_BADOFFSET: Function was passed a structure block
+	 * offset which is out-of-bounds, or which points to an
+	 * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH		5
+	/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+	 * (e.g. missing a leading / for a function which requires an
+	 * absolute path) */
+#define FDT_ERR_BADPHANDLE	6
+	/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
+	 * value.  phandle values of 0 and -1 are not permitted. */
+#define FDT_ERR_BADSTATE	7
+	/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+	 * tree created by the sequential-write functions, which is
+	 * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED	8
+	/* FDT_ERR_TRUNCATED: Structure block of the given device tree
+	 * ends without an FDT_END tag. */
+#define FDT_ERR_BADMAGIC	9
+	/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+	 * device tree at all - it is missing the flattened device
+	 * tree magic number. */
+#define FDT_ERR_BADVERSION	10
+	/* FDT_ERR_BADVERSION: Given device tree has a version which
+	 * can't be handled by the requested operation.  For
+	 * read-write functions, this may mean that fdt_open_into() is
+	 * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE	11
+	/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+	 * structure block or other serious error (e.g. misnested
+	 * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT	12
+	/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+	 * device tree has it's sub-blocks in an order that the
+	 * function can't handle (memory reserve map, then structure,
+	 * then strings).  Use fdt_open_into() to reorganize the tree
+	 * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL	13
+	/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+	 * Should never be returned, if it is, it indicates a bug in
+	 * libfdt itself. */
+
+#define FDT_ERR_MAX		13
+
+/**********************************************************************/
+/* Low-level functions (you probably don't need these)                */
+/**********************************************************************/
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
+{
+	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
+
+/**********************************************************************/
+/* Traversal functions                                                */
+/**********************************************************************/
+
+int fdt_next_node(const void *fdt, int offset, int *depth);
+
+/**********************************************************************/
+/* General functions                                                  */
+/**********************************************************************/
+
+#define fdt_get_header(fdt, field) \
+	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt)			(fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt)		(fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt)	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt)	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt)	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
+
+#define __fdt_set_hdr(name) \
+	static inline void fdt_set_##name(void *fdt, uint32_t val) \
+	{ \
+		struct fdt_header *fdth = (struct fdt_header*)fdt; \
+		fdth->name = cpu_to_fdt32(val); \
+	}
+__fdt_set_hdr(magic);
+__fdt_set_hdr(totalsize);
+__fdt_set_hdr(off_dt_struct);
+__fdt_set_hdr(off_dt_strings);
+__fdt_set_hdr(off_mem_rsvmap);
+__fdt_set_hdr(version);
+__fdt_set_hdr(last_comp_version);
+__fdt_set_hdr(boot_cpuid_phys);
+__fdt_set_hdr(size_dt_strings);
+__fdt_set_hdr(size_dt_struct);
+#undef __fdt_set_hdr
+
+/**
+ * fdt_check_header - sanity check a device tree or possible device tree
+ * @fdt: pointer to data which might be a flattened device tree
+ *
+ * fdt_check_header() checks that the given buffer contains what
+ * appears to be a flattened device tree with sane information in its
+ * header.
+ *
+ * returns:
+ *     0, if the buffer appears to contain a valid device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings, as above
+ */
+int fdt_check_header(const void *fdt);
+
+/**
+ * fdt_move - move a device tree around in memory
+ * @fdt: pointer to the device tree to move
+ * @buf: pointer to memory where the device is to be moved
+ * @bufsize: size of the memory space at buf
+ *
+ * fdt_move() relocates, if possible, the device tree blob located at
+ * fdt to the buffer at buf of size bufsize.  The buffer may overlap
+ * with the existing device tree blob at fdt.  Therefore,
+ *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
+ * should always succeed.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/**********************************************************************/
+/* Read-only functions                                                */
+/**********************************************************************/
+
+/**
+ * fdt_string - retrieve a string from the strings block of a device tree
+ * @fdt: pointer to the device tree blob
+ * @stroffset: offset of the string within the strings block (native endian)
+ *
+ * fdt_string() retrieves a pointer to a single string from the
+ * strings block of the device tree blob at fdt.
+ *
+ * returns:
+ *     a pointer to the string, on success
+ *     NULL, if stroffset is out of bounds
+ */
+const char *fdt_string(const void *fdt, int stroffset);
+
+/**
+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
+ * @fdt: pointer to the device tree blob
+ *
+ * Returns the number of entries in the device tree blob's memory
+ * reservation map.  This does not include the terminating 0,0 entry
+ * or any other (0,0) entries reserved for expansion.
+ *
+ * returns:
+ *     the number of entries
+ */
+int fdt_num_mem_rsv(const void *fdt);
+
+/**
+ * fdt_get_mem_rsv - retrieve one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: pointers to 64-bit variables
+ *
+ * On success, *address and *size will contain the address and size of
+ * the n-th reserve map entry from the device tree blob, in
+ * native-endian format.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
+
+/**
+ * fdt_subnode_offset_namelen - find a subnode based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_subnode_offset(), but only examine the first
+ * namelen characters of name for matching the subnode name.  This is
+ * useful for finding subnodes based on a portion of a larger string,
+ * such as a full path.
+ */
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+			       const char *name, int namelen);
+/**
+ * fdt_subnode_offset - find a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node at structure block
+ * offset parentoffset with the given name.  name may include a unit
+ * address, in which case fdt_subnode_offset() will find the subnode
+ * with that unit address, or the unit address may be omitted, in
+ * which case fdt_subnode_offset() will find an arbitrary subnode
+ * whose name excluding unit address matches the given name.
+ *
+ * returns:
+ *	structure block offset of the requested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_path_offset - find a tree node by its full path
+ * @fdt: pointer to the device tree blob
+ * @path: full path of the node to locate
+ *
+ * fdt_path_offset() finds a node of a given path in the device tree.
+ * Each path component may omit the unit address portion, but the
+ * results of this are undefined if any such path component is
+ * ambiguous (that is if there are multiple nodes at the relevant
+ * level matching the given component, differentiated only by unit
+ * address).
+ *
+ * returns:
+ *	structure block offset of the node with the requested path (>=0), on success
+ *	-FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
+ *	-FDT_ERR_NOTFOUND, if the requested node does not exist
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_path_offset(const void *fdt, const char *path);
+
+/**
+ * fdt_get_name - retrieve the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the starting node
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_name() retrieves the name (including unit address) of the
+ * device tree node at structure block offset nodeoffset.  If lenp is
+ * non-NULL, the length of this name is also returned, in the integer
+ * pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the node's name, on success
+ *		If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE, standard meanings
+ */
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
+
+/**
+ * fdt_first_property_offset - find the offset of a node's first property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ *
+ * fdt_first_property_offset() finds the first property of the node at
+ * the given structure block offset.
+ *
+ * returns:
+ *	structure block offset of the property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested node has no properties
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_next_property_offset - step through a node's properties
+ * @fdt: pointer to the device tree blob
+ * @offset: structure block offset of a property
+ *
+ * fdt_next_property_offset() finds the property immediately after the
+ * one at the given structure block offset.  This will be a property
+ * of the same node as the given property.
+ *
+ * returns:
+ *	structure block offset of the next property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the given property is the last in its node
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_next_property_offset(const void *fdt, int offset);
+
+/**
+ * fdt_get_property_by_offset - retrieve the property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the property to retrieve
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property_by_offset() retrieves a pointer to the
+ * fdt_property structure within the device tree blob at the given
+ * offset.  If lenp is non-NULL, the length of the property value is
+ * also returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp);
+
+/**
+ * fdt_get_property_namelen - find a property based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_get_property_namelen(), but only examine the first
+ * namelen characters of name for matching the property name.
+ */
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int nodeoffset,
+						    const char *name,
+						    int namelen, int *lenp);
+
+/**
+ * fdt_get_property - find a given property in a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property() retrieves a pointer to the fdt_property
+ * structure within the device tree blob corresponding to the property
+ * named 'name' of the node at offset nodeoffset.  If lenp is
+ * non-NULL, the length of the property value is also returned, in the
+ * integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+					    const char *name, int *lenp);
+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
+						      const char *name,
+						      int *lenp)
+{
+	return (struct fdt_property *)(uintptr_t)
+		fdt_get_property(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @ffset: offset of the property to read
+ * @namep: pointer to a string variable (will be overwritten) or NULL
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop_by_offset() retrieves a pointer to the value of the
+ * property at structure block offset 'offset' (this will be a pointer
+ * to within the device blob itself, not a copy of the value).  If
+ * lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.  If namep is non-NULL,
+ * the property's namne will also be returned in the char * pointed to
+ * by namep (this will be a pointer to within the device tree's string
+ * block, not a new copy of the name).
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *		if namep is non-NULL *namep contiains a pointer to the property
+ *		name.
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp);
+
+/**
+ * fdt_getprop_namelen - get property value based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_getprop(), but only examine the first namelen
+ * characters of name for matching the property name.
+ */
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp);
+
+/**
+ * fdt_getprop - retrieve the value of a given property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop() retrieves a pointer to the value of the property
+ * named 'name' of the node at offset nodeoffset (this will be a
+ * pointer to within the device blob itself, not a copy of the value).
+ * If lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp);
+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
+				  const char *name, int *lenp)
+{
+	return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_get_phandle - retrieve the phandle of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the node
+ *
+ * fdt_get_phandle() retrieves the phandle of the device tree node at
+ * structure block offset nodeoffset.
+ *
+ * returns:
+ *	the phandle of the node at nodeoffset, on success (!= 0, != -1)
+ *	0, if the node has no phandle, or another error occurs
+ */
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retreive the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias.  That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ *	a pointer to the expansion of the alias named 'name', of it exists
+ *	NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
+/**
+ * fdt_get_path - determine the full path of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose path to find
+ * @buf: character buffer to contain the returned path (will be overwritten)
+ * @buflen: size of the character buffer at buf
+ *
+ * fdt_get_path() computes the full path of the node at offset
+ * nodeoffset, and records that path in the buffer at buf.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	0, on success
+ *		buf contains the absolute path of the node at
+ *		nodeoffset, as a NUL-terminated string.
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
+ *		characters and will not fit in the given buffer.
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
+
+/**
+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ * @supernodedepth: depth of the ancestor to find
+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node
+ * at a specific depth from the root (where the root itself has depth
+ * 0, its immediate subnodes depth 1 and so forth).  So
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
+ * will always return 0, the offset of the root node.  If the node at
+ * nodeoffset has depth D, then:
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
+ * will return nodeoffset itself.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+
+ *	structure block offset of the node at node offset's ancestor
+ *		of depth supernodedepth (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+*	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth);
+
+/**
+ * fdt_node_depth - find the depth of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_node_depth() finds the depth of a given node.  The root node
+ * has depth 0, its immediate subnodes depth 1 and so forth.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	depth of the node at nodeoffset (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_depth(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_parent_offset - find the parent of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_parent_offset() locates the parent node of a given node (that
+ * is, it finds the offset of the node which contains the node at
+ * nodeoffset as a subnode).
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset, *twice*.
+ *
+ * returns:
+ *	structure block offset of the parent of the node at nodeoffset
+ *		(>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_parent_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_node_offset_by_prop_value - find nodes with a given property value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ *
+ * fdt_node_offset_by_prop_value() returns the offset of the first
+ * node after startoffset, which has a property named propname whose
+ * value is of length proplen and has value equal to propval; or if
+ * startoffset is -1, the very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
+ *					       propval, proplen);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
+ *						       propval, proplen);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen);
+
+/**
+ * fdt_node_offset_by_phandle - find the node with a given phandle
+ * @fdt: pointer to the device tree blob
+ * @phandle: phandle value
+ *
+ * fdt_node_offset_by_phandle() returns the offset of the node
+ * which has the given phandle value.  If there is more than one node
+ * in the tree with the given phandle (an invalid tree), results are
+ * undefined.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0), on success
+ *	-FDT_ERR_NOTFOUND, no node with that phandle exists
+ *	-FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
+
+/**
+ * fdt_node_check_compatible: check a node's compatible property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of a tree node
+ * @compatible: string to match against
+ *
+ *
+ * fdt_node_check_compatible() returns 0 if the given node contains a
+ * 'compatible' property with the given string as one of its elements,
+ * it returns non-zero otherwise, or on error.
+ *
+ * returns:
+ *	0, if the node has a 'compatible' property listing the given string
+ *	1, if the node has a 'compatible' property, but it does not list
+ *		the given string
+ *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
+ *	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible);
+
+/**
+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @compatible: 'compatible' string to match against
+ *
+ * fdt_node_offset_by_compatible() returns the offset of the first
+ * node after startoffset, which has a 'compatible' property which
+ * lists the given compatible string; or if startoffset is -1, the
+ * very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible);
+
+/**********************************************************************/
+/* Write-in-place functions                                           */
+/**********************************************************************/
+
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: cell (32-bit integer) value to replace the property with
+ *
+ * fdt_setprop_inplace_cell() replaces the value of a given property
+ * with the 32-bit integer cell value in val, converting val to
+ * big-endian if necessary.  This function cannot change the size of a
+ * property, and so will only work if the property already exists and
+ * has length 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+  *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+					   const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Sequential write functions                                         */
+/**********************************************************************/
+
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &val, sizeof(val));
+}
+#define fdt_property_string(fdt, name, str) \
+	fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+
+/**********************************************************************/
+/* Read-write functions                                               */
+/**********************************************************************/
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_mem_rsv(void *fdt, int n);
+
+/**
+ * fdt_set_name - change the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ * @name: name to give the node
+ *
+ * fdt_set_name() replaces the name (including unit address, if any)
+ * of the given node with the given string.  NOTE: this function can't
+ * efficiently check if the new name is unique amongst the given
+ * node's siblings; results are undefined if this function is invoked
+ * with a name equal to one of the given node's siblings.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob
+ *		to contain the new name
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_set_name(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len);
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_cell() sets the value of the named property in the
+ * given node to the given cell value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+				   uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Debugging / informational functions                                */
+/**********************************************************************/
+
+const char *fdt_strerror(int errval);
+
+#endif /* _LIBFDT_H */
diff --git a/src/include/fdt/libfdt_env.h b/src/include/fdt/libfdt_env.h
new file mode 100644
index 0000000..bf63583
--- /dev/null
+++ b/src/include/fdt/libfdt_env.h
@@ -0,0 +1,33 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren at cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include "compiler.h"
+
+extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
+
+#define fdt32_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_fdt32(x)		cpu_to_be32(x)
+#define fdt64_to_cpu(x)		be64_to_cpu(x)
+#define cpu_to_fdt64(x)		cpu_to_be64(x)
+
+#endif /* _LIBFDT_ENV_H */



From gerrit at coreboot.org  Fri Mar  2 23:01:58 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:01:58 +0100
Subject: [coreboot] New patch to review for coreboot: 0b24054 Add ability to
	pass FDT to the payload.
References: <I50893c9acbea33e50a8e116f48d6383f8f1c0958+0@gerrit.coreboot.org>
Message-ID: <I50893c9acbea33e50a8e116f48d6383f8f1c0958+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/700

-gerrit

commit 0b24054475ba985cf3e6d50410d2fdf3dc3624ac
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Aug 11 15:49:52 2011 -0700

    Add ability to pass FDT to the payload.
    
    When configured, try to find the binary FDT in the CBFS and
    include it into the coreboot table as one of the sections.
    
    The default FDT file name 'u-boot.dtb' can be changed through a
    config dialog. In the spirit of coreboot no check is made if the
    FDT indeed fits into the coreboot table, this check might be
    added if deemed necessary.
    
    Change-Id: I50893c9acbea33e50a8e116f48d6383f8f1c0958
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/Kconfig                        |   16 ++++++++++++++
 src/arch/x86/boot/coreboot_table.c |   40 +++++++++++++++++++++++++++++++++++-
 src/include/boot/coreboot_tables.h |   25 ++++++++++++++++++++++
 src/include/cbfs_core.h            |    2 +-
 src/include/fdt/libfdt_env.h       |    4 +--
 5 files changed, 82 insertions(+), 5 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index c165d93..0dc66a3 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -112,6 +112,22 @@ config INCLUDE_CONFIG_FILE
   help
     Include in CBFS the coreboot config file that was used to compile the ROM image
 
+config ADD_FDT
+	bool "Add FDT to the coreboot table"
+	default n
+	help
+	  Make coreboot look for the Flat Device Tree (FDT) in CBFS and once
+	  found insert the device tree into the coreboot table (potentially
+	  modifying the tree as needed). The FDT is used by the payload.
+
+config FDT_FILE_NAME
+	depends on ADD_FDT
+	string "Name of the CBFS file containing the compiled FDT"
+	default "u-boot.dtb"
+	help
+	  Name of the CBFS file containing the binary representation of the
+	  device tree to be optionally modified and passed to the payload.
+
 endmenu
 
 source src/mainboard/Kconfig
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 78ff97d..fc861a4 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -33,6 +33,10 @@
 #include <option_table.h>
 #include <cbfs.h>
 #endif
+#if (CONFIG_ADD_FDT == 1)
+#include <fdt/fdt.h>
+#include <fdt/libfdt_env.h>
+#endif
 
 static struct lb_header *lb_table_init(unsigned long addr)
 {
@@ -174,6 +178,34 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
+#ifdef CONFIG_ADD_FDT
+static void lb_fdt(struct lb_header *header)
+{
+	struct lb_fdt *fdt_record;
+	struct fdt_header *fdt_header;
+	u32 magic, fdt_size;
+
+	fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
+	if (!fdt_header) {
+		printk(BIOS_ERR, "Can't find FDT (%s)\n", CONFIG_FDT_FILE_NAME);
+		return;
+	}
+
+	magic = fdt32_to_cpu(fdt_header->magic);
+	if (magic != FDT_MAGIC) {
+		printk(BIOS_ERR, "FDT header corrupted (0x%x)\n", magic);
+		return;
+	}
+
+	fdt_size = fdt32_to_cpu(fdt_header->totalsize);
+	fdt_record = (struct lb_fdt *) lb_new_record(header);
+	fdt_record->tag = LB_TAG_FDT;
+	fdt_record->size = sizeof(*fdt_record) + fdt_size;
+	memcpy(fdt_record + 1, fdt_header, fdt_size);
+	printk(BIOS_SPEW, "FDT of %d bytes added\n", fdt_size);
+}
+#endif
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -617,7 +649,13 @@ unsigned long write_coreboot_table(
 	lb_strings(head);
 	/* Record our framebuffer */
 	lb_framebuffer(head);
-
+#ifdef CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head);
+#endif
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 45ba3af..d32aa62 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -195,6 +195,31 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_FDT	0x0014
+struct lb_fdt {
+	uint32_t tag;
+	uint32_t size;		     /* size of the entire entry */
+	/* the actual FDT gets placed here */
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index 70368f8..f9029c0 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -72,7 +72,7 @@
 #define CBFS_TYPE_MICROCODE  0x53
 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
 #define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
-
+#define CBFS_TYPE_FDT       0xac
 
 /** this is the master cbfs header - it need to be
     located somewhere in the bootblock.  Where it
diff --git a/src/include/fdt/libfdt_env.h b/src/include/fdt/libfdt_env.h
index bf63583..755a5a6 100644
--- a/src/include/fdt/libfdt_env.h
+++ b/src/include/fdt/libfdt_env.h
@@ -21,9 +21,7 @@
 #ifndef _LIBFDT_ENV_H
 #define _LIBFDT_ENV_H
 
-#include "compiler.h"
-
-extern struct fdt_header *working_fdt;  /* Pointer to the working fdt */
+#include <arch/byteorder.h>
 
 #define fdt32_to_cpu(x)		be32_to_cpu(x)
 #define cpu_to_fdt32(x)		cpu_to_be32(x)



From gerrit at coreboot.org  Fri Mar  2 23:02:00 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:02:00 +0100
Subject: [coreboot] New patch to review for coreboot: 9006830 Clean up use
	of CONFIG_ variables in coreboot_table.c
References: <Ifcac6ceac5fb34b931281beae500023597b3533b+0@gerrit.coreboot.org>
Message-ID: <Ifcac6ceac5fb34b931281beae500023597b3533b+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/701

-gerrit

commit 90068304b17c7f0f7673c01ecf13d883e0467d24
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Aug 15 11:26:35 2011 -0700

    Clean up use of CONFIG_ variables in coreboot_table.c
    
    CONFIG_ variables are used inconsistently within the file
    src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong
    thing if the option is disabled. #if (CONFIG_FOO == 1) is
    not needed.
    
    Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/coreboot_table.c |   21 +++++++++++----------
 1 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index fc861a4..0bcae4c 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,11 +29,11 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
 #include <cbfs.h>
 #endif
-#if (CONFIG_ADD_FDT == 1)
+#if CONFIG_ADD_FDT
 #include <fdt/fdt.h>
 #include <fdt/libfdt_env.h>
 #endif
@@ -178,7 +178,7 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
-#ifdef CONFIG_ADD_FDT
+#if CONFIG_ADD_FDT
 static void lb_fdt(struct lb_header *header)
 {
 	struct lb_fdt *fdt_record;
@@ -230,7 +230,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -544,7 +544,7 @@ static void add_lb_reserved(struct lb_memory *mem)
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
@@ -555,7 +555,7 @@ unsigned long write_coreboot_table(
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -591,7 +591,7 @@ unsigned long write_coreboot_table(
 	rom_table_end &= ~0xffff;
 	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 	{
 		struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa);
 		if (option_table) {
@@ -616,7 +616,7 @@ unsigned long write_coreboot_table(
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
@@ -626,7 +626,7 @@ unsigned long write_coreboot_table(
 	/* Add reserved regions */
 	add_lb_reserved(mem);
 
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
 	add_mainboard_resources(mem);
 #endif
 
@@ -649,7 +649,8 @@ unsigned long write_coreboot_table(
 	lb_strings(head);
 	/* Record our framebuffer */
 	lb_framebuffer(head);
-#ifdef CONFIG_ADD_FDT
+
+#if CONFIG_ADD_FDT
 	/*
 	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
 	 * along the way.



From gerrit at coreboot.org  Fri Mar  2 23:02:01 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:02:01 +0100
Subject: [coreboot] New patch to review for coreboot: 0c04713 Fix
	compilation when USE_OPTION_TABLE is not defined.
References: <Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d+0@gerrit.coreboot.org>
Message-ID: <Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/702

-gerrit

commit 0c04713dc352826dc62bbd1d9e2b376c8aa49194
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 15 16:35:10 2011 -0700

    Fix compilation when USE_OPTION_TABLE is not defined.
    
    Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/boot/coreboot_table.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 0bcae4c..ba1e358 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,9 +29,9 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
+#include <cbfs.h>
 #if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
-#include <cbfs.h>
 #endif
 #if CONFIG_ADD_FDT
 #include <fdt/fdt.h>



From gerrit at coreboot.org  Fri Mar  2 23:02:03 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:02:03 +0100
Subject: [coreboot] New patch to review for coreboot: 75f77f5 Fix coreboot
	table size calculations.
References: <Ic55501a4ae06fab2bcda9aea58e362325f2edccf+0@gerrit.coreboot.org>
Message-ID: <Ic55501a4ae06fab2bcda9aea58e362325f2edccf+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/703

-gerrit

commit 75f77f5ea36ca5f9f6ee2c3abc93eef3c8616268
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Aug 16 11:44:35 2011 -0700

    Fix coreboot table size calculations.
    
    The code when reporting the coreboot table size did not account
    for the last added table record. This change fixes the problem.
    
     . rebuild coreboot, program it on the target, restart it
     . look for 'Wrote coreboot table at:' in the console log
     . observe the adequate table size reported
    
     $  grep 'Wrote coreboot table:' /tmp/cb.log
     Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f
     Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45
     $
    
    Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index ba1e358..b463409 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -352,9 +352,10 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup)
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p  checksum %x\n",
-		head, rec, head->table_checksum);
-	return (unsigned long)rec;
+	printk(BIOS_DEBUG,
+	       "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
+	       head, head->table_bytes, head->table_checksum);
+	return (unsigned long)rec + rec->size;
 }
 
 static void lb_cleanup_memory_ranges(struct lb_memory *mem)



From gerrit at coreboot.org  Fri Mar  2 23:02:04 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Fri, 2 Mar 2012 23:02:04 +0100
Subject: [coreboot] New patch to review for coreboot: 0e9052f Increase size
	of the coreboot table area
References: <I2025bf070d0adb276c1cd610aa8402b50bdf2525+0@gerrit.coreboot.org>
Message-ID: <I2025bf070d0adb276c1cd610aa8402b50bdf2525+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/704

-gerrit

commit 0e9052fc533f174373fb3b7ad7d2aa23f374f61b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Sun Aug 14 13:52:03 2011 -0700

    Increase size of the coreboot table area
    
    Packing a device tree into the coreboot table can easily make
    the table exceed the current limit of 8KB. However, right now
    there is no error handling in place to catch that case.
    
    Increase the maximum memory usable for all tables from 64KB to
    128KB and increase the maximum coreboot table size from 8KB
    to 32KB.
    
    Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/tables.c |    2 +-
 src/include/cbmem.h        |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 29d2ec0..b7dc4fe 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -202,7 +202,7 @@ struct lb_memory *write_tables(void)
 	}
 #endif
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
 	post_code(0x9d);
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 7c5ec07..9806854 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -20,8 +20,8 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-/* Reserve 64k for ACPI and other tables */
-#define HIGH_MEMORY_DEF_SIZE	( 64 * 1024 )
+/* Reserve 128k for ACPI and other tables */
+#define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
 extern uint64_t high_tables_base, high_tables_size;
 
 #if CONFIG_HAVE_ACPI_RESUME



From gerrit at coreboot.org  Fri Mar  2 23:06:38 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Fri, 2 Mar 2012 23:06:38 +0100
Subject: [coreboot] New patch to review for coreboot: 37a6cac Make libpaylod
	alloc() memory pointers volatile
References: <I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82+0@gerrit.coreboot.org>
Message-ID: <I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82+1@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/705

-gerrit

commit 37a6cacf4e04d0ee9e75f1b1c7ea307d750623c6
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Thu Mar 1 16:12:11 2012 -0700

    Make libpaylod alloc() memory pointers volatile
    
    gcc4.6.2 was optimizing the libpayload alloc() function and failing to
    reload a pointer after the memory had been manipulated by a pointer in
    the inlined function setup(). I changes the pointer type to volatile
    and now pass it to the setup() function. I also cleaned up the
    declaration so that it isn't cast a bunch times in the function.
    
    Change-Id: I1637bd7bd5d9cf82ac88925cbfe76d319aa3cd82
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 payloads/libpayload/libc/malloc.c |   25 +++++++++++--------------
 1 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c
index 6389fc9..9412cab 100644
--- a/payloads/libpayload/libc/malloc.c
+++ b/payloads/libpayload/libc/malloc.c
@@ -73,11 +73,9 @@ static int heap_initialized = 0;
 static int minimal_free = 0;
 #endif
 
-static void setup(void)
+static void setup(hdrtype_t volatile *start, int size)
 {
-	int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE;
-
-	*((hdrtype_t *) hstart) = FREE_BLOCK(size);
+	*start = FREE_BLOCK(size);
 
 #ifdef CONFIG_DEBUG_MALLOC
 	heap_initialized = 1;
@@ -88,7 +86,7 @@ static void setup(void)
 static void *alloc(int len)
 {
 	hdrtype_t header;
-	void *ptr = hstart;
+	hdrtype_t volatile *ptr = (hdrtype_t volatile *) hstart;
 
 	/* Align the size. */
 	len = (len + 3) & ~3;
@@ -97,12 +95,12 @@ static void *alloc(int len)
 		return (void *)NULL;
 
 	/* Make sure the region is setup correctly. */
-	if (!HAS_MAGIC(*((hdrtype_t *) ptr)))
-		setup();
+	if (!HAS_MAGIC(*ptr))
+		setup(ptr, len);
 
 	/* Find some free space. */
 	do {
-		header = *((hdrtype_t *) ptr);
+		header = *ptr;
 		int size = SIZE(header);
 
 		if (!HAS_MAGIC(header) || size == 0) {
@@ -114,7 +112,7 @@ static void *alloc(int len)
 
 		if (header & FLAG_FREE) {
 			if (len <= size) {
-				void *nptr = ptr + (HDRSIZE + len);
+				hdrtype_t volatile *nptr = ptr + (HDRSIZE + len);
 				int nsize = size - (HDRSIZE + len);
 
 				/* If there is still room in this block,
@@ -124,14 +122,13 @@ static void *alloc(int len)
 
 				if (nsize > 0) {
 					/* Mark the block as used. */
-					*((hdrtype_t *) ptr) = USED_BLOCK(len);
+					*ptr = USED_BLOCK(len);
 
 					/* Create a new free block. */
-					*((hdrtype_t *) nptr) =
-					    FREE_BLOCK(nsize);
+					*nptr = FREE_BLOCK(nsize);
 				} else {
 					/* Mark the block as used. */
-					*((hdrtype_t *) ptr) = USED_BLOCK(size);
+					*ptr = USED_BLOCK(size);
 				}
 
 				return (void *)(ptr + HDRSIZE);
@@ -140,7 +137,7 @@ static void *alloc(int len)
 
 		ptr += HDRSIZE + size;
 
-	} while (ptr < hend);
+	} while (ptr < (hdrtype_t *) hend);
 
 	/* Nothing available. */
 	return (void *)NULL;



From gerrit at coreboot.org  Fri Mar  2 23:06:40 2012
From: gerrit at coreboot.org (Marc Jones (marcj303@gmail.com))
Date: Fri, 2 Mar 2012 23:06:40 +0100
Subject: [coreboot] Patch set updated for coreboot: 76db020 Update xcompile
	to search for x86_64 toolchain.
References: <I8b12f3e705157741279c7347f4847fb50ccc2b0e+0@gerrit.coreboot.org>
Message-ID: <I8b12f3e705157741279c7347f4847fb50ccc2b0e+4@gerrit.coreboot.org>

Marc Jones (marcj303 at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673

-gerrit

commit 76db020f22bbe48c3cc78fd4ec5f8b77c66ceed6
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Wed Feb 22 11:46:17 2012 -0700

    Update xcompile to search for x86_64 toolchain.
    
    This adds detection of x86_64 gcc toolchain (which buildgcc can build
    if provided the option).
    
    Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
 util/xcompile/xcompile |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 4926394..3930460 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -36,14 +36,19 @@ done
 
 GCCPREFIX=invalid
 XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"}
-echo '#XGCCPATH='${XGCCPATH}
+echo '# XGCCPATH='${XGCCPATH}
 TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz`
 touch $TMPFILE
 
-# This should be a loop over all supported architectures
-TARCH=i386
+# This loops over all supported architectures in TARCH
+TARCH=('i386' 'x86_64')
 TWIDTH=32
-for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do
+for search_for in "${TARCH[@]}"; do
+	TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-)
+done
+echo '# TARCH_SEARCH='${TARCH_SEARCH[@]}
+
+for gccprefixes in "${TARCH_SEARCH[@]}" ""; do
 	if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then
 		continue
 	fi
@@ -63,8 +68,8 @@ for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do
 		if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then
 			GCCPREFIX=$gccprefixes
 			ASFLAGS=--32
-			CFLAGS="-m32 "
-			LDFLAGS="-b elf32-i386"
+			CFLAGS="-m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 "
+			LDFLAGS="-b elf32-i386 -melf_i386"
 			break
 		fi
 	fi



From gerrit at coreboot.org  Fri Mar  2 23:36:05 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Fri, 2 Mar 2012 23:36:05 +0100
Subject: [coreboot] Patch merged into coreboot/master: 15e268e Fix ECC
	disable option for AMD Fam10 DDR2 and DDR3.
References: <I60bffb6149d96cac65011247ef51cd06ed2210c6+0@gerrit.coreboot.org>
Message-ID: <E1S3b53-0001yt-Q6@ra.coresystems.de>

the following patch was just integrated into master:
commit 15e268ee435d7d6f8d76997336efb38c4732042e
Author: Marc Jones <marc.jones at se-eng.com>
Date:   Tue Feb 21 17:06:40 2012 -0700

    Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
    
    The logic was backwards on the ECC enable/disable option. Also added better
    debug output when the debug RAM init feature is enabled.
    
    Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
    Signed-off-by: Marc Jones <marc.jones at se-eng.com>

Build-Tested: build bot (Jenkins) at Wed Feb 22 02:31:23 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Thu Mar  1 18:18:12 2012, giving +2
See http://review.coreboot.org/670 for details.

-gerrit



From gerrit at coreboot.org  Sat Mar  3 09:15:12 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Sat, 3 Mar 2012 09:15:12 +0100
Subject: [coreboot] Patch merged into coreboot/master: 05f4b03 Use -mno-sse
	to prevent overzealous gcc optimizations
References: <I14f0942f300085767ece44cec570fb15c761e88d+0@gerrit.coreboot.org>
Message-ID: <E1S3k7U-0006bA-6e@ra.coresystems.de>

the following patch was just integrated into master:
commit 05f4b03fb64999ba373fe61256f358e5371bf8ae
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Jun 23 17:12:08 2011 -0700

    Use -mno-sse to prevent overzealous gcc optimizations
    
    The offending part that made coreboot crash with some toolchains
    was that gcc emits SSE instructions but coreboot did not enable SSE at
    that point.
    
    Since the gain for coreboot using SSE instructions is not measurable,
    let's not use SSE instructions rather than enabling SSE early on.
    One rationale behind this is that other parts of coreboot, like the
    SMM handler would need fixing because the XMM registers are not saved
    on SMM entry. Thus keep it simple.
    
    Change-Id: I14f0942f300085767ece44cec570fb15c761e88d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Sat Mar  3 09:15:10 2012, giving +2
See http://review.coreboot.org/694 for details.

-gerrit



From gerrit at coreboot.org  Sat Mar  3 10:46:26 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Sat, 3 Mar 2012 10:46:26 +0100
Subject: [coreboot] New patch to review for coreboot: 7c48e07 Revert "Use
	-mno-sse to prevent overzealous gcc optimizations"
References: <I7c48e07a261eafda2119354d282bd05eac5a14b6+0@gerrit.coreboot.org>
Message-ID: <I7c48e07a261eafda2119354d282bd05eac5a14b6+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/706

-gerrit

commit 7c48e07a261eafda2119354d282bd05eac5a14b6
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Mar 3 10:46:26 2012 +0100

    Revert "Use -mno-sse to prevent overzealous gcc optimizations"
    
    AGESA uses SSE intrinsics :-(
    
    This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae
---
 util/xcompile/xcompile |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index f5d43d0..4926394 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -84,10 +84,6 @@ testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none
 # now:
 testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
 	       CFLAGS="$CFLAGS-Wno-unused-but-set-variable "
-# Use bfd linker instead of gold if available:
-testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
-# Prevent SSE instructions sneaking in:
-testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse "
 
 if which gcc 2>/dev/null >/dev/null; then
 	HOSTCC=gcc



From christian.suehs at online.de  Sun Mar  4 20:01:41 2012
From: christian.suehs at online.de (Christian)
Date: Sun, 04 Mar 2012 20:01:41 +0100
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
Message-ID: <1330887701.6905.17.camel@dance-or-die3.athome.de>

Hey list
I currently working on a Igel Thin Client 3210.
The board is very closer to bcom/winnetp680.
CN700 northbridge
VT8237R southbridge
W83679HF SuperIO
A try with this tree did not work.
I'm not new to coreboot and think that the first debug message should
apear on the serial-console, but nothing happens.

I have compiled nearly all via boards to test the ROMs with qemu.
And get always this message:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000

EAX=00000004 EBX=00000000 ECX=00000000 EDX=00000001
ESI=00000000 EDI=00000000 EBP=ffef7fe8 ESP=ffef7fb8
EIP=0009ff66 EFL=00000002 [-------] CPL=0 II=0 A20=1 SMM=0 HLT=0
ES =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
CS =0008 00000000 ffffffff 00cf9b00 DPL=0 CS32 [-RA]
SS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
DS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
FS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
GS =0010 00000000 ffffffff 00cf9300 DPL=0 DS   [-WA]
LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
GDT=     fff8df54 00000017
IDT=     00000000 00000000
CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
DR0=00000000 DR1=00000000 DR2=00000000 DR3=00000000 
DR6=ffff0ff0 DR7=00000400
CCS=00000004 CCD=000000c4 CCO=ADDB    
EFER=0000000000000000
FCW=037f FSW=0000 [ST=0] FTW=ff MXCSR=00001f80
FPR0=0000000000000000 0000 FPR1=0000000000000000 0000
FPR2=0000000000000000 0000 FPR3=0000000000000000 0000
FPR4=0000000000000000 0000 FPR5=0000000000000000 0000
FPR6=0000000000000000 0000 FPR7=0000000000000000 0000
XMM00=00000000000000000000000000000000
XMM01=00000000000000000000000000000000
XMM02=00000000000000000000000000000000
XMM03=00000000000000000000000000000000
XMM04=00000000000000000000000000000000
XMM05=00000000000000000000000000000000
XMM06=00000000000000000000000000000000
XMM07=00000000000000000000000000000000
Abgebrochen
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
nothing more ...
There is no "Coreboot Starting bla, bla" message

Amd or Intel boards break later.

Is it a problem with Qemu and Via C7 CPUs or is their something wrong in
the via tree.

Is anybody working on a cn700 board for now.
There are hints for Rev. 3566 code for the southbridge? Is this
important. Does the current code not working?

Thanks Chris




From rminnich at gmail.com  Sun Mar  4 20:19:20 2012
From: rminnich at gmail.com (ron minnich)
Date: Sun, 4 Mar 2012 11:19:20 -0800
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <1330887701.6905.17.camel@dance-or-die3.athome.de>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
Message-ID: <CAP6exYKUKwb8zOqxV_JDCmYbr2qE=vvPL-oGe5O5jYPTqMFLUQ@mail.gmail.com>

For problems at this level with qemu I would usually use Bochs with
debug enabled so I could watch every instruction. You might want to
try that.

ron



From eldmannen at gmail.com  Sat Mar  3 21:35:57 2012
From: eldmannen at gmail.com (Fred .)
Date: Sat, 3 Mar 2012 21:35:57 +0100
Subject: [coreboot] Linux-ready Firmware Kit
Message-ID: <CAJgfmqVMis7u13v7RCVHC5zn_r2cMhEmXioKciBCA3d+rDTyHA@mail.gmail.com>

# yum install pmtools
# acpidump > acpi.dump
# acpixtract -l acpi.dump
# dmidecode

Intel provides a Linux-ready Firmware Kit, available on a LiveCD (79
MB) ( http://linuxfirmwarekit.org/download/firmwarekit-r3.iso ). You
only have to launch it, wait 1 or 2 minutes, and there is a summary of
the results based on different topics (memory handling, PCI resources,
HPET, ACPI tables, and more). The results is a number of "Fail",
"Warn" and "Pass" flags. This Linux-ready Firmware Kit seems to not be
developed anymore, but I guess it can give us a idea of the quality of
the BIOS.



From makarovdenis11 at gmail.com  Sat Mar  3 22:02:40 2012
From: makarovdenis11 at gmail.com (=?UTF-8?B?0JTQtdC90LjRgQ==?=)
Date: Sun, 04 Mar 2012 01:02:40 +0400
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
Message-ID: <4F5286F0.9050903@gmail.com>

Ok, I've downloaded coreboot, did it /make menuconfig /and saved 
configuration. Then I wrote

$ make


/Cloning SeaBIOS from Git
Cloning into /home/denis/????????/coreboot/build/seabios...
remote: Counting objects: 7460, done.
remote: Compressing objects: 100% (2358/2358), done.
remote: Total 7460 (delta 5915), reused 6374 (delta 5096)
Receiving objects: 100% (7460/7460), 1.77 MiB | 269 KiB/s, done.
Resolving deltas: 100% (5915/5915), done.
     Checking out SeaBIOS revision e66fb31eac3e6be6aaab548c229af9bb1ba55c33
Already on 'master'
Switched to a new branch 'coreboot'
     CONFIG     SeaBIOS e66fb31eac3e6be6aaab548c229af9bb1ba55c33
The version of LD on this system does not properly handle
alignments.  As a result, this project can not be built.

The problem may be the result of this LD bug report:
  http://sourceware.org/bugzilla/show_bug.cgi?id=12726

Please update to a working version of binutils and retry.
Makefile:75: *** "Please upgrade GCC and/or binutils".  ???????.
make[1]: *** [config] Error 2
make: *** [seabios] Error 2


/Then, I tried

/$ make crossgcc/

Thereafter

/$ make/

/`IntelDisplayType' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/vgahooks.c.170' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`IntelDisplayId' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/vgahooks.c.170' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`pmode_IDT_info' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`rmode_IDT_info' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.132' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`RamSize' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.14' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/mouse.c.104' 
referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/mouse.c.104' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`RamSize' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.14' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`e820_count' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/system.c.295' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`e820_list' referenced in section `.text.handle_15' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/system.c.294' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`cdemu_drive_gf' referenced in section `.text.handle_13' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/cdrom.c.20' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`pmode_IDT_info' referenced in section `.text.asm.transition32' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`rombios32_gdt_48' referenced in section `.text.asm.transition32' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.166' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`rmode_IDT_info' referenced in section `.text.asm.transition16' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.132' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`pmode_IDT_info' referenced in section `.text.asm.export.entry_elf' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`rombios32_gdt_48' referenced in section `.text.asm.export.entry_elf' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.166' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
`HaveRunPost' referenced in section `.fixedaddr.0xe05b' of 
/home/denis/????????/coreboot/build/seabios/out/code16.o: defined in 
discarded section 
`.data16./home/denis/????????/coreboot/build/seabios/out/../src/resume.c.18' 
of /home/denis/????????/coreboot/build/seabios/out/code16.o
make[2]: *** [/home/denis/????????/coreboot/build/seabios/out/rom16.o] 
?????? 1
make[1]: *** [build] Error 2
make: *** [seabios] Error 2/

Please, help me fixed this problem.

    Best Regards, *Denis*


/


/
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From gerrit at coreboot.org  Mon Mar  5 08:34:15 2012
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Mon, 5 Mar 2012 08:34:15 +0100
Subject: [coreboot] New patch to review for coreboot: bdab48d Fix address of
	IDT in real-mode entry
References: <I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+0@gerrit.coreboot.org>
Message-ID: <I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/707

-gerrit

commit bdab48d3f13d117bd1100be616837e6d1dbb55fc
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Mon Mar 5 09:25:12 2012 +0200

    Fix address of IDT in real-mode entry
    
    In a case of CS & 0x0fff != 0x0, lidt memory operand does not point
    to nullidt, this can raise an exception and shutdown the CPU.
    
    When an AP CPU receives 8-bit Start-Up IPI vector yzH, it starts
    execute at physical address 000yz000H. Seems this translates to
    either yz00:0000 or y000:z000 (CS:IP), depending of the CPU model.
    With the change entry16.inc is relocatable as the commentary suggests
    and can be used as ap_sipi_vector on SMP systems.
    
    Change-Id: I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/cpu/x86/16bit/entry16.inc |   15 ++++++++-------
 1 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 0fa8c11..e4613bf 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -57,13 +57,6 @@ _start:
 	 * entry16.inc.
 	 */
 
-	/* Load an IDT with NULL limit to prevent the 16bit IDT being used
-	 * in protected mode before c_start.S sets up a 32bit IDT when entering
-	 * ram stage.
-	 */
-	movw $nullidt_offset, %bx
-	lidt %cs:(%bx)
-
 	/* Note: gas handles memory addresses in 16 bit code very poorly.
 	 * In particular it doesn't appear to have a directive allowing you
 	 * associate a section or even an absolute offset with a segment register.
@@ -98,10 +91,18 @@ _start:
 	 * the low 16 bits.  This means that the intial segment used
 	 * when start is called must be 64K aligned.  This should not
 	 * restrict the address as the ip address can be anything.
+	 *
+	 * Also load an IDT with NULL limit to prevent the 16bit IDT being used
+	 * in protected mode before c_start.S sets up a 32bit IDT when entering
+	 * ram stage. In practise: CPU will shutdown on any exception.
+	 * See IA32 manual Vol 3A 19.26 Interrupts.
 	 */
 
 	movw	%cs, %ax
 	shlw	$4, %ax
+	movw	$nullidt_offset, %bx
+	subw	%ax, %bx
+	lidt	%cs:(%bx)
 	movw	$gdtptr16_offset, %bx
 	subw	%ax, %bx
 	data32  lgdt %cs:(%bx)



From nrubinstein at proformatique.com  Mon Mar  5 10:56:56 2012
From: nrubinstein at proformatique.com (=?iso-8859-1?B?Tm/p?= Rubinstein)
Date: Mon, 5 Mar 2012 10:56:56 +0100
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <4F5286F0.9050903@gmail.com>
References: <4F5286F0.9050903@gmail.com>
Message-ID: <20120305095656.GD11392@xivo-clients.proformatique.com>

Did you try to "make clean" before re-making with the new gcc?

On Sun, Mar 04, 2012 at 01:02:40AM +0400, ????? wrote:
> Ok, I've downloaded coreboot, did it /make menuconfig /and saved
> configuration. Then I wrote
> 
> $ make
> 
> 
> /Cloning SeaBIOS from Git
> Cloning into /home/denis/????????/coreboot/build/seabios...
> remote: Counting objects: 7460, done.
> remote: Compressing objects: 100% (2358/2358), done.
> remote: Total 7460 (delta 5915), reused 6374 (delta 5096)
> Receiving objects: 100% (7460/7460), 1.77 MiB | 269 KiB/s, done.
> Resolving deltas: 100% (5915/5915), done.
>     Checking out SeaBIOS revision e66fb31eac3e6be6aaab548c229af9bb1ba55c33
> Already on 'master'
> Switched to a new branch 'coreboot'
>     CONFIG     SeaBIOS e66fb31eac3e6be6aaab548c229af9bb1ba55c33
> The version of LD on this system does not properly handle
> alignments.  As a result, this project can not be built.
> 
> The problem may be the result of this LD bug report:
>  http://sourceware.org/bugzilla/show_bug.cgi?id=12726
> 
> Please update to a working version of binutils and retry.
> Makefile:75: *** "Please upgrade GCC and/or binutils".  ???????.
> make[1]: *** [config] Error 2
> make: *** [seabios] Error 2
> 
> 
> /Then, I tried
> 
> /$ make crossgcc/
> 
> Thereafter
> 
> /$ make/
> 
> /`IntelDisplayType' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/vgahooks.c.170'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `IntelDisplayId' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/vgahooks.c.170'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `pmode_IDT_info' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `rmode_IDT_info' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.132'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `RamSize' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.14'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `.data16./home/denis/????????/coreboot/build/seabios/out/../src/mouse.c.104'
> referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/mouse.c.104'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `RamSize' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.14'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `e820_count' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/system.c.295'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `e820_list' referenced in section `.text.handle_15' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/system.c.294'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `cdemu_drive_gf' referenced in section `.text.handle_13' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/cdrom.c.20'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `pmode_IDT_info' referenced in section `.text.asm.transition32' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `rombios32_gdt_48' referenced in section `.text.asm.transition32' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.166'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `rmode_IDT_info' referenced in section `.text.asm.transition16' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.132'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `pmode_IDT_info' referenced in section `.text.asm.export.entry_elf'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o: defined
> in discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.142'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `rombios32_gdt_48' referenced in section
> `.text.asm.export.entry_elf' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/misc.c.166'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> `HaveRunPost' referenced in section `.fixedaddr.0xe05b' of
> /home/denis/????????/coreboot/build/seabios/out/code16.o: defined in
> discarded section `.data16./home/denis/????????/coreboot/build/seabios/out/../src/resume.c.18'
> of /home/denis/????????/coreboot/build/seabios/out/code16.o
> make[2]: ***
> [/home/denis/????????/coreboot/build/seabios/out/rom16.o] ?????? 1
> make[1]: *** [build] Error 2
> make: *** [seabios] Error 2/
> 
> Please, help me fixed this problem.
> 
>    Best Regards, *Denis*
> 
> 
> /
> 
> 
> /

> -- 
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot


-- 
No? Rubinstein
Proformatique (groupe Avencall) - XiVO IPBX OpenHardware
10 bis, rue Lucien VOILIN - 92800 Puteaux



From svn at coreboot.org  Mon Mar  5 16:00:01 2012
From: svn at coreboot.org (coreboot tracker)
Date: Mon, 05 Mar 2012 16:00:01 +0100
Subject: [coreboot] Trac reminder: list of new ticket(s)
Message-ID: <E1S4ZOL-0004Qh-O4@ra.coresystems.de>

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From christian.suehs at online.de  Mon Mar  5 21:54:27 2012
From: christian.suehs at online.de (christian.suehs at online.de)
Date: Mon, 5 Mar 2012 21:54:27 +0100 (CET)
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <1330887701.6905.17.camel@dance-or-die3.athome.de>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
Message-ID: <869159867.480944.1330980867000.JavaMail.tomcat55@mrmseu5.kundenserver.de>


Ok,

qemu says

qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000

bochs means

>>PANIC<< prefetch: getHostMemAddr vetoed direct read, pAddr=0x00000000000a0000

it should be 0xf0000

chris



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From gerrit at coreboot.org  Mon Mar  5 21:58:10 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 21:58:10 +0100
Subject: [coreboot] Patch set updated for coreboot: 5405656 Don't try to
	compute I/O for empty sub buses.
References: <I098446deef96a8baae26a7ca1ddd96e626a06dc5+0@gerrit.coreboot.org>
Message-ID: <I098446deef96a8baae26a7ca1ddd96e626a06dc5+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/693

-gerrit

commit 540565641844bdc3e6fae44a73ce05b9bd0e9d07
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed May 11 15:57:07 2011 -0700

    Don't try to compute I/O for empty sub buses.
    
    I am not sure if the sub bus being 0 is a problem, or if the assumption
    there has to be at least one non empty link is just wrong. It certainly
    does not hurt to add a small consistency check in either case.
    
    Change-Id: I098446deef96a8baae26a7ca1ddd96e626a06dc5
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/device_util.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..84fb115 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -583,6 +583,8 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask,
 					if (subbus->link_num
 					== IOINDEX_SUBTRACTIVE_LINK(res->index))
 						break;
+				if (!subbus) /* Why can subbus be NULL?  */
+					break;
 				search_bus_resources(subbus, type_mask, type,
 						     search, gp);
 				continue;



From gerrit at coreboot.org  Mon Mar  5 22:03:34 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:34 +0100
Subject: [coreboot] New patch to review for coreboot: 618c314 Add an
	implementation for the memchr library function
References: <Icded479d246f7cce8a3d2154c69f75178fa513e1+0@gerrit.coreboot.org>
Message-ID: <Icded479d246f7cce8a3d2154c69f75178fa513e1+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/708

-gerrit

commit 618c314d845a4fc23f8fc8902bcff334c1d8fd12
Author: Gabe Black <gabeblack at google.com>
Date:   Fri Sep 16 02:18:56 2011 -0700

    Add an implementation for the memchr library function
    
    This function is declared in string.h, but no implementation was compiled in
    this change adds a very simple, naive implementation.
    
    Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/lib/Makefile.inc |    2 ++
 src/lib/memchr.c     |   11 +++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 906dfae..e0e5e75 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,6 +1,7 @@
 
 
 romstage-y += memset.c
+romstage-y += memchr.c
 romstage-y += memcpy.c
 romstage-y += memcmp.c
 romstage-y += cbfs.c
@@ -15,6 +16,7 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 
 ramstage-y += memset.c
+ramstage-y += memchr.c
 ramstage-y += memcpy.c
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
diff --git a/src/lib/memchr.c b/src/lib/memchr.c
new file mode 100644
index 0000000..a890dce
--- /dev/null
+++ b/src/lib/memchr.c
@@ -0,0 +1,11 @@
+#include <string.h>
+void *memchr(const void *s, int c, size_t n)
+{
+	const unsigned char *sc = s;
+	while (n--) {
+		if (*sc == (unsigned char)c)
+			return (void *)sc;
+		sc++;
+	}
+	return NULL;
+}



From gerrit at coreboot.org  Mon Mar  5 22:03:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:39 +0100
Subject: [coreboot] New patch to review for coreboot: 0e771e7 Since
	cbfs_core.h provides a macro that uses ntohl,
	make sure ntohl is available
References: <I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f+0@gerrit.coreboot.org>
Message-ID: <I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/709

-gerrit

commit 0e771e77afd8f12d8c4971deee73bd422b9664a8
Author: Gabe Black <gabeblack at google.com>
Date:   Fri Sep 16 02:24:03 2011 -0700

    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available
    
    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by
    including byteorder.h
    
    Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/include/cbfs_core.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index 70368f8..43e6b9b 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -49,6 +49,8 @@
 #ifndef _CBFS_CORE_H_
 #define _CBFS_CORE_H_
 
+#include <arch/byteorder.h>
+
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
     payloads.  Of course, other CBFS users can use whatever



From gerrit at coreboot.org  Mon Mar  5 22:03:40 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:40 +0100
Subject: [coreboot] New patch to review for coreboot: 19b7323 Introduce
	config option to initialize CBMEM early.
References: <I6736fdc264ecd0b63369b28462d7bb96e4c2b012+0@gerrit.coreboot.org>
Message-ID: <I6736fdc264ecd0b63369b28462d7bb96e4c2b012+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/710

-gerrit

commit 19b732385037e1a8a2ee710ad9c4e5d6b169a874
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Sep 20 16:46:46 2011 -0700

    Introduce config option to initialize CBMEM early.
    
    We want to be able to communicate information between rom and ram
    stages of coreboot. This configuration option will be used to
    compile such ability in.
    
    Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/Kconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index c165d93..544b61b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE
   help
     Include in CBFS the coreboot config file that was used to compile the ROM image
 
+config EARLY_CBMEM_INIT
+	bool "Initialize CBMEM while in ROM stage"
+	default n
+	help
+	  Make coreboot initialize the cbmem structures while running in rom
+	  stage. This could be useful when the rom stage wants to communicate
+	  some, for instance, execution timestamps.
+
 endmenu
 
 source src/mainboard/Kconfig



From gerrit at coreboot.org  Mon Mar  5 22:03:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:41 +0100
Subject: [coreboot] New patch to review for coreboot: 566c472 Initialize
	CBMEM early.
References: <I81691d45e28de59496fb227f2cca4e8c15ece717+0@gerrit.coreboot.org>
Message-ID: <I81691d45e28de59496fb227f2cca4e8c15ece717+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/711

-gerrit

commit 566c472c98872ea51b16dc428dc48e1988fa582b
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Sep 20 17:07:14 2011 -0700

    Initialize CBMEM early.
    
    We want to be able to share data between different phases of firmware
    (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
    location for this data, but normally it is not initialized
    until coreboot reaches the ram stage.
    
    This change initializes the CBMEM while still in rom stage in
    case CONFIG_EARLY_CBMEM_INIT is set.
    
    Note that there is a discrepancy in how coreboot determines the
    size of DRAM at rom and ram stages, get_top_of_ram() is used at
    rom stage and is not defined for all platforms. Those platforms
    will have to define this function should they enable the
    CONFIG_EARLY_CBMEM_INIT flag.
    
    Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    4 +++-
 src/lib/cbmem.c     |   39 +++++++++++++++++++++++----------------
 2 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 9806854..a681c36 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -22,7 +22,9 @@
 
 /* Reserve 128k for ACPI and other tables */
 #define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
+#endif
 
 #if CONFIG_HAVE_ACPI_RESUME
 #define HIGH_MEMORY_SIZE	((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE)
@@ -41,7 +43,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_NONE		0x00000000
 
-void cbmem_initialize(void);
+int cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
 int cbmem_reinit(u64 baseaddr);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 202f521..f5c3d3a 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -183,30 +183,38 @@ void *cbmem_find(u32 id)
 	return (void *)NULL;
 }
 
-#ifndef __PRE_RAM__
-#if CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
 extern u8 acpi_slp_type;
 #endif
 
-void cbmem_initialize(void)
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+/* Returns True if it was not intialized before. */
+int cbmem_initialize(void)
 {
-#if CONFIG_HAVE_ACPI_RESUME
-	printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type);
-	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
-		if (!cbmem_reinit(high_tables_base)) {
-			printk(BIOS_DEBUG, "cbmem_reinit failed\n");
-			/* Something went wrong, our high memory area got wiped */
+	int rv = 0;
+
+#ifdef __PRE_RAM__
+	extern unsigned long get_top_of_ram(void);
+	uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+	uint64_t high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+
+	/* We expect the romstage to always initialize it. */
+	if (!cbmem_reinit(high_tables_base)) {
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+		/* Something went wrong, our high memory area got wiped */
+		if (acpi_slp_type == 3 || acpi_slp_type == 2)
 			acpi_slp_type = 0;
-			cbmem_init(high_tables_base, high_tables_size);
-		}
-	} else {
+#endif
 		cbmem_init(high_tables_base, high_tables_size);
+		rv = 1;
 	}
-#else
-	cbmem_init(high_tables_base, high_tables_size);
-#endif
+#ifndef __PRE_RAM__
 	cbmem_arch_init();
+#endif
+	return rv;
 }
+#endif
 
 #ifndef __PRE_RAM__
 void cbmem_list(void)
@@ -240,5 +248,4 @@ void cbmem_list(void)
 }
 #endif
 
-#endif
 



From gerrit at coreboot.org  Mon Mar  5 22:03:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:42 +0100
Subject: [coreboot] Patch set updated for coreboot: 40dea3f Fix compilation
	when USE_OPTION_TABLE is not defined.
References: <Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d+0@gerrit.coreboot.org>
Message-ID: <Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/702

-gerrit

commit 40dea3f447fc9976a9cf781243480b411b064d82
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 15 16:35:10 2011 -0700

    Fix compilation when USE_OPTION_TABLE is not defined.
    
    Change-Id: Id622e4e96b6c8e87b00a96c324a0b4dbfac3391d
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/boot/coreboot_table.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 77a1126..a001259 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,9 +29,9 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
+#include <cbfs.h>
 #if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
-#include <cbfs.h>
 #endif
 
 static struct lb_header *lb_table_init(unsigned long addr)



From gerrit at coreboot.org  Mon Mar  5 22:03:43 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:43 +0100
Subject: [coreboot] Patch set updated for coreboot: 5972775 Fix coreboot
	table size calculations.
References: <Ic55501a4ae06fab2bcda9aea58e362325f2edccf+0@gerrit.coreboot.org>
Message-ID: <Ic55501a4ae06fab2bcda9aea58e362325f2edccf+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/703

-gerrit

commit 597277514a7ea03d0a4494460a33b33d3463455b
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Aug 16 11:44:35 2011 -0700

    Fix coreboot table size calculations.
    
    The code when reporting the coreboot table size did not account
    for the last added table record. This change fixes the problem.
    
     . rebuild coreboot, program it on the target, restart it
     . look for 'Wrote coreboot table at:' in the console log
     . observe the adequate table size reported
    
     $  grep 'Wrote coreboot table:' /tmp/cb.log
     Wrote coreboot table at: 00000500, 0x10 bytes, checksum c06f
     Wrote coreboot table at: 7f6fc000, 0x1a73 bytes, checksum 3e45
     $
    
    Change-Id: Ic55501a4ae06fab2bcda9aea58e362325f2edccf
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index a001259..b0dcc9e 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -320,9 +320,10 @@ static unsigned long lb_table_fini(struct lb_header *head, int fixup)
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p  checksum %x\n",
-		head, rec, head->table_checksum);
-	return (unsigned long)rec;
+	printk(BIOS_DEBUG,
+	       "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
+	       head, head->table_bytes, head->table_checksum);
+	return (unsigned long)rec + rec->size;
 }
 
 static void lb_cleanup_memory_ranges(struct lb_memory *mem)



From gerrit at coreboot.org  Mon Mar  5 22:03:45 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:45 +0100
Subject: [coreboot] Patch set updated for coreboot: 116004a Clean up use of
	CONFIG_ variables in coreboot_table.c
References: <Ifcac6ceac5fb34b931281beae500023597b3533b+0@gerrit.coreboot.org>
Message-ID: <Ifcac6ceac5fb34b931281beae500023597b3533b+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/701

-gerrit

commit 116004afe7d1796bfdad3a71ae04afad0fa8d462
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Aug 15 11:26:35 2011 -0700

    Clean up use of CONFIG_ variables in coreboot_table.c
    
    CONFIG_ variables are used inconsistently within the file
    src/arch/x86/boot/coreboot_table.c. #ifdef will do the wrong
    thing if the option is disabled. #if (CONFIG_FOO == 1) is
    not needed.
    
    Change-Id: Ifcac6ceac5fb34b931281beae500023597b3533b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/coreboot_table.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 78ff97d..77a1126 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
 #include <cbfs.h>
 #endif
@@ -198,7 +198,7 @@ static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 	return mainboard;
 }
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -512,7 +512,7 @@ static void add_lb_reserved(struct lb_memory *mem)
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 extern uint64_t high_tables_base, high_tables_size;
 #endif
 
@@ -523,7 +523,7 @@ unsigned long write_coreboot_table(
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -559,7 +559,7 @@ unsigned long write_coreboot_table(
 	rom_table_end &= ~0xffff;
 	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 	{
 		struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa);
 		if (option_table) {
@@ -584,7 +584,7 @@ unsigned long write_coreboot_table(
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
@@ -594,7 +594,7 @@ unsigned long write_coreboot_table(
 	/* Add reserved regions */
 	add_lb_reserved(mem);
 
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
 	add_mainboard_resources(mem);
 #endif
 



From gerrit at coreboot.org  Mon Mar  5 22:03:46 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:46 +0100
Subject: [coreboot] Patch set updated for coreboot: 9271105 Fix dependency
	problem for uart8250.c as well
References: <I828956ab2e05c48d20c2f7c55616cc8fa19e1227+0@gerrit.coreboot.org>
Message-ID: <I828956ab2e05c48d20c2f7c55616cc8fa19e1227+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/698

-gerrit

commit 927110510039eee5c16036b6e74607ae84950fcc
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Aug 11 14:51:31 2011 -0700

    Fix dependency problem for uart8250.c as well
    
    If you build in parallel, option_table.h will occasionally not be there yet
    and the build will fail.
    
    Change-Id: I828956ab2e05c48d20c2f7c55616cc8fa19e1227
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/Makefile.inc |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index b930fcc..906dfae 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -50,4 +50,5 @@ OPTION_TABLE_H:=$(obj)/option_table.h
 endif
 
 $(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)
 



From gerrit at coreboot.org  Mon Mar  5 22:03:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:47 +0100
Subject: [coreboot] Patch set updated for coreboot: 5365441 Fix compilation
	with CONFIG_USE_OPTION_TABLE enabled
References: <I6c5d973442bc1770702180a8964f1bf6ed6062ed+0@gerrit.coreboot.org>
Message-ID: <I6c5d973442bc1770702180a8964f1bf6ed6062ed+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/696

-gerrit

commit 536544151d45351e129b6ce018cd2128eca1da6f
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Jul 29 15:34:14 2011 -0700

    Fix compilation with CONFIG_USE_OPTION_TABLE enabled
    
    Change-Id: I6c5d973442bc1770702180a8964f1bf6ed6062ed
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/Makefile.inc |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 432e24e..b930fcc 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -43,3 +43,11 @@ smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 smm-$(CONFIG_USBDEBUG) += usbdebug.c
 
 $(obj)/lib/version.ramstage.o : $(obj)/build.h
+
+OPTION_TABLE_H:=
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+OPTION_TABLE_H:=$(obj)/option_table.h
+endif
+
+$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+



From gerrit at coreboot.org  Mon Mar  5 22:03:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:48 +0100
Subject: [coreboot] Patch set updated for coreboot: bb904b2 Increase size of
	the coreboot table area
References: <I2025bf070d0adb276c1cd610aa8402b50bdf2525+0@gerrit.coreboot.org>
Message-ID: <I2025bf070d0adb276c1cd610aa8402b50bdf2525+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/704

-gerrit

commit bb904b224e508d1fa0cd06bfeb1c450732a04ec1
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Sun Aug 14 13:52:03 2011 -0700

    Increase size of the coreboot table area
    
    Packing a device tree into the coreboot table can easily make
    the table exceed the current limit of 8KB. However, right now
    there is no error handling in place to catch that case.
    
    Increase the maximum memory usable for all tables from 64KB to
    128KB and increase the maximum coreboot table size from 8KB
    to 32KB.
    
    Change-Id: I2025bf070d0adb276c1cd610aa8402b50bdf2525
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/tables.c |    2 +-
 src/include/cbmem.h        |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 29d2ec0..b7dc4fe 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -202,7 +202,7 @@ struct lb_memory *write_tables(void)
 	}
 #endif
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
 	post_code(0x9d);
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 7c5ec07..9806854 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -20,8 +20,8 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-/* Reserve 64k for ACPI and other tables */
-#define HIGH_MEMORY_DEF_SIZE	( 64 * 1024 )
+/* Reserve 128k for ACPI and other tables */
+#define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
 extern uint64_t high_tables_base, high_tables_size;
 
 #if CONFIG_HAVE_ACPI_RESUME



From gerrit at coreboot.org  Mon Mar  5 22:03:49 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Mon, 5 Mar 2012 22:03:49 +0100
Subject: [coreboot] Patch set updated for coreboot: 8689912 Add helper
	function to find a Local APIC by ID in the device tree.
References: <Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7+0@gerrit.coreboot.org>
Message-ID: <Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/695

-gerrit

commit 86899127de3f98718453192a15bd0344d90063f6
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jul 18 10:41:36 2011 -0700

    Add helper function to find a Local APIC by ID in the device tree.
    
    Change-Id: Ie2d7d8e1f647a0c92d2de09e32454fbea688b1e7
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/devices/device_util.c   |   20 ++++++++++++++++++++
 src/include/device/device.h |    1 +
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 84fb115..5b182e1 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -110,6 +110,26 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr)
 }
 
 /**
+ * Given a Local APIC ID, find the device structure.
+ *
+ * @param apic_id The Local APIC ID number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+device_t dev_find_lapic(unsigned apic_id)
+{
+	device_t dev, result = NULL;
+
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (dev->path.type == DEVICE_PATH_APIC &&
+		    dev->path.apic.apic_id == apic_id) {
+			result = dev;
+			break;
+		}
+	}
+	return result;
+}
+
+/**
  * Find a device of a given vendor and type.
  *
  * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
diff --git a/src/include/device/device.h b/src/include/device/device.h
index a7de0c9..c097f57 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -132,6 +132,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from);
 device_t dev_find_class (unsigned int class, device_t from);
 device_t dev_find_slot (unsigned int bus, unsigned int devfn);
 device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_lapic(unsigned apic_id);
 
 /* Debug functions */
 void print_resource_tree(struct device * root, int debug_level,



From gerrit at coreboot.org  Tue Mar  6 00:52:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:39 +0100
Subject: [coreboot] New patch to review for coreboot: 6135be8 Add a config
	flag to enable time stamp collection.
References: <Idbebcaf298238f31a73e9eb4a9af7b03e857bc74+0@gerrit.coreboot.org>
Message-ID: <Idbebcaf298238f31a73e9eb4a9af7b03e857bc74+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/712

-gerrit

commit 6135be8c41d82ee84c6417c901f42b60ec6bec59
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 21 14:46:43 2011 -0700

    Add a config flag to enable time stamp collection.
    
    Add a new flag, make it dependent on EARLY_CBMEM_INIT
    
    Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/Kconfig |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 544b61b..573868f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE
   help
     Include in CBFS the coreboot config file that was used to compile the ROM image
 
+config FDT_FILE_NAME
+	depends on ADD_FDT
+	string "Name of the CBFS file containing the compiled FDT"
+	default "u-boot.dtb"
+	help
+	  Name of the CBFS file containing the binary representation of the
+	  device tree to be optionally modified and passed to the payload.
+
 config EARLY_CBMEM_INIT
 	bool "Initialize CBMEM while in ROM stage"
 	default n
@@ -120,6 +128,13 @@ config EARLY_CBMEM_INIT
 	  stage. This could be useful when the rom stage wants to communicate
 	  some, for instance, execution timestamps.
 
+config COLLECT_TIMESTAMPS
+	bool "Create a table of timestamps collected during boot"
+	depends on EARLY_CBMEM_INIT
+	help
+	  Make coreboot create a table of timer id/timer value pairs to
+	  allow measuring time spent at different phases of the boot
+	  process.
 endmenu
 
 source src/mainboard/Kconfig



From gerrit at coreboot.org  Tue Mar  6 00:52:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:39 +0100
Subject: [coreboot] New patch to review for coreboot: 4030efb Add timestamp
	collecting to coreboot.
References: <I7ed9f5c400bc5432f228348b41fd19a67c36d533+0@gerrit.coreboot.org>
Message-ID: <I7ed9f5c400bc5432f228348b41fd19a67c36d533+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/713

-gerrit

commit 4030efb3234d9f40543fea820d19c76438aad0c2
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 21 16:12:39 2011 -0700

    Add timestamp collecting to coreboot.
    
    This patch adds code to initialize the time stamp collection
    facility in coreboot. It adds a table in the CBMEM section, which
    provides the base timer reading value (all other readings are
    offsets of this one) and an array of timestamp id/timestamp value
    pairs.
    
    Just two values are being added now, this will have to be used
    more extensively and also integrated into payloads to provide more
    comprehensive boot process time measurements.
    
    Also, since the CBMEM area could already contain a section (from the
    previous run, before reset), when processing a section addition
    request we should check if a section already exists and return its
    address, if so.
    
    Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h     |    1 +
 src/include/timestamp.h |   46 +++++++++++++++++++++++++++++
 src/lib/Makefile.inc    |    2 +
 src/lib/cbmem.c         |   17 +++++++++++
 src/lib/timestamp.c     |   74 +++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 140 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a681c36..c3f10ef 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_RESUME		0x5245534d
 #define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_TIMESTAMP	0x54494d45
 #define CBMEM_ID_NONE		0x00000000
 
 int cbmem_initialize(void);
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
new file mode 100644
index 0000000..cfa06e2
--- /dev/null
+++ b/src/include/timestamp.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef __TIMESTAMP_H__
+#define __TIMESTAMP_H__
+
+#include <cpu/x86/tsc.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint32_t	max_entries;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_BEFORE_INITRAM = 1,
+	TS_AFTER_INITRAM = 2,
+};
+
+void timestamp_init(tsc_t base);
+void timestamp_add(enum timestamp_id id, tsc_t ts_time);
+void timestamp_add_now(enum timestamp_id id);
+
+#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index e0e5e75..db640dc 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-y += memset.c
 ramstage-y += memchr.c
@@ -36,6 +37,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index f5c3d3a..6597840 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -118,6 +118,22 @@ void *cbmem_add(u32 id, u64 size)
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
+	void *p;
+
+	/*
+	 * This could be a restart, check if the section is there already. It
+	 * is remotely possible that the dram contents persisted over the
+	 * bootloader upgrade AND the same section now needs more room, but
+	 * this is quite a remote possibility and it is ignored here.
+	 */
+	p = cbmem_find(id);
+	if (p) {
+		printk(BIOS_NOTICE,
+		       "CBMEM section %x: using existing location at %p.\n",
+		       id, p);
+		return p;
+	}
+
 	cbmem_toc = get_cbmem_toc();
 
 	if (cbmem_toc == NULL) {
@@ -240,6 +256,7 @@ void cbmem_list(void)
 		case CBMEM_ID_MPTABLE:	 printk(BIOS_DEBUG, "SMP TABLE  "); break;
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
 		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
+		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
new file mode 100644
index 0000000..bbb8197d
--- /dev/null
+++ b/src/lib/timestamp.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <timestamp.h>
+
+#define MAX_TIMESTAMPS 30
+
+#ifndef __PRE_RAM__
+static struct timestamp_table* ts_table;
+#endif
+
+static uint64_t tsc_to_uint64(tsc_t tstamp)
+{
+	return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
+}
+
+void timestamp_init(tsc_t base)
+{
+	struct timestamp_table* tst;
+
+	tst = cbmem_add(CBMEM_ID_TIMESTAMP,
+			sizeof(struct timestamp_table) +
+			MAX_TIMESTAMPS * sizeof(struct timestamp_entry));
+
+	if (!tst) {
+		printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n");
+		return;
+	}
+
+	tst->base_time = tsc_to_uint64(base);
+	tst->max_entries = MAX_TIMESTAMPS;
+	tst->num_entries = 0;
+}
+
+void timestamp_add(enum timestamp_id id, tsc_t ts_time)
+{
+	struct timestamp_entry *tse;
+#ifdef __PRE_RAM__
+	struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#else
+	if (!ts_table)
+		ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#endif
+	if (!ts_table || (ts_table->num_entries == ts_table->max_entries))
+		return;
+
+	tse = &ts_table->entries[ts_table->num_entries++];
+	tse->entry_id = id;
+	tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time;
+}
+
+void timestamp_add_now(enum timestamp_id id)
+{
+	timestamp_add(id, rdtsc());
+}



From gerrit at coreboot.org  Tue Mar  6 00:52:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:39 +0100
Subject: [coreboot] New patch to review for coreboot: 484acec Include
	arch/acpi.h instead of manually adding acpi_slp_type.
References: <Ia5eb420364c15ab5a764bc328bbd201ca9cb7837+0@gerrit.coreboot.org>
Message-ID: <Ia5eb420364c15ab5a764bc328bbd201ca9cb7837+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/714

-gerrit

commit 484acec01d2b55a648cf810ae37a8f405b529ba6
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Sep 23 10:24:49 2011 -0700

    Include arch/acpi.h instead of manually adding acpi_slp_type.
    
    acpi_slp_type is defined in arch/acpi.h, so let's use that instead
    of manually spreading extern u8 acpi_slp_type throughout the code.
    
    Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/cbmem.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 6597840..f800b04 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -21,6 +21,9 @@
 #include <string.h>
 #include <cbmem.h>
 #include <console/console.h>
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+#include <arch/acpi.h>
+#endif
 
 // The CBMEM TOC reserves 512 bytes to keep
 // the other entries somewhat aligned.
@@ -199,10 +202,6 @@ void *cbmem_find(u32 id)
 	return (void *)NULL;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
-extern u8 acpi_slp_type;
-#endif
-
 #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
 /* Returns True if it was not intialized before. */
 int cbmem_initialize(void)



From gerrit at coreboot.org  Tue Mar  6 00:52:40 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:40 +0100
Subject: [coreboot] New patch to review for coreboot: 2d9ed13 Don't run VGA
	option ROMs on S3 resume.
References: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+0@gerrit.coreboot.org>
Message-ID: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/715

-gerrit

commit 2d9ed13c22a4a37b4ef9f30c9e9b1136dff2a9ee
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Sep 23 10:33:58 2011 -0700

    Don't run VGA option ROMs on S3 resume.
    
    This will save us a few 100 ms on resume.
    
    Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig      |    7 +++++++
 src/devices/pci_device.c |   11 +++++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 9e5ea6e..572addc 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -33,6 +33,13 @@ config VGA_ROM_RUN
 	  Execute VGA option ROMs, if found. This is required to enable
 	  PCI/AGP/PCI-E video cards.
 
+config S3_VGA_ROM_RUN
+	bool "Re-run VGA option ROMs on S3 resume"
+	default y
+	depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+	help
+	  Execute VGA option ROMs when coming out of an S3 resume.
+
 config PCI_ROM_RUN
 	bool "Run non-VGA option ROMs"
 	default y
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..1f36679 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -51,6 +51,9 @@
 #if CONFIG_PC80_SYSTEM == 1
 #include <pc80/i8259.h>
 #endif
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+#include <arch/acpi.h>
+#endif
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
@@ -672,6 +675,14 @@ void pci_dev_init(struct device *dev)
 	if (ram == NULL)
 		return;
 
+#if !CONFIG_S3_VGA_ROM_RUN
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if ((acpi_slp_type == 3) &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return;
+#endif
 	run_bios(dev, (unsigned long)ram);
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 }



From gerrit at coreboot.org  Tue Mar  6 00:52:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:41 +0100
Subject: [coreboot] New patch to review for coreboot: 56c20fc Add timestamp
	table pointer to the coreboot table.
References: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+0@gerrit.coreboot.org>
Message-ID: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/716

-gerrit

commit 56c20fcc646838e17e44f2a90c14996315698643
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 23 09:56:11 2011 -0700

    Add timestamp table pointer to the coreboot table.
    
    This change exports the timestamp table pointer through coreboot
    table to make it possible for u-boot to add timestamps to the
    table.
    
    Inclusion of cbmem.h allows to drop external declarations in
    coreboot_table.c.
    
    Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   25 +++++++++++++++++++++----
 src/include/boot/coreboot_tables.h |    8 ++++++++
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index b0dcc9e..f189e76 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -30,6 +30,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
 #endif
@@ -174,6 +175,23 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
+#if CONFIG_COLLECT_TIMESTAMPS
+static void lb_tsamp(struct lb_header *header)
+{
+	struct lb_tstamp *tstamp;
+	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+
+	if (!tstamp_table)
+		return;
+
+	tstamp = (struct lb_tstamp *)lb_new_record(header);
+	tstamp->tag = LB_TAG_TIMESTAMPS;
+	tstamp->size = sizeof(*tstamp);
+	tstamp->tstamp_tab = tstamp_table;
+
+}
+#endif
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -513,10 +531,6 @@ static void add_lb_reserved(struct lb_memory *mem)
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
@@ -619,6 +633,9 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	lb_tsamp(head);
+#endif
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 45ba3af..46d6489 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -195,6 +195,14 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_TIMESTAMPS	0x0016
+struct lb_tstamp {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*tstamp_tab;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */



From gerrit at coreboot.org  Tue Mar  6 00:52:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:41 +0100
Subject: [coreboot] New patch to review for coreboot: 0739dfa Add cmos
	helper functions for reading/writing a dword
References: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+0@gerrit.coreboot.org>
Message-ID: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/717

-gerrit

commit 0739dfa33e71e00d87ba9fd107a73d9758c9ebb9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 26 13:24:40 2011 -0700

    Add cmos helper functions for reading/writing a dword
    
    These get used later for saving/restoring the MRC scrambler
    seed values on each boot.
    
    Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/include/pc80/mc146818rtc.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 3e5a61a..24dac2c 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -104,6 +104,22 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
 	outb(addr, RTC_BASE_PORT + offs + 0);
 	outb(val, RTC_BASE_PORT + offs + 1);
 }
+
+static inline u32 cmos_read32(u8 offset)
+{
+	u32 value = 0;
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		value |= cmos_read(offset + i) << (i << 3);
+	return value;
+}
+
+static inline void cmos_write32(u8 offset, u32 value)
+{
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		cmos_write((value >> (i << 3)) & 0xff, offset + i);
+}
 #endif
 
 #if !defined(__ROMCC__)



From gerrit at coreboot.org  Tue Mar  6 00:52:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:42 +0100
Subject: [coreboot] New patch to review for coreboot: b26c9b0 CBMEM CONSOLE:
	Add config option for CBMEM stored console log.
References: <I209603f516244ae136631e6281ba21ebc6fb1710+0@gerrit.coreboot.org>
Message-ID: <I209603f516244ae136631e6281ba21ebc6fb1710+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718

-gerrit

commit b26c9b0c087f14a84b08b62f6f0c2796ac9253d1
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 28 13:51:30 2011 -0700

    CBMEM CONSOLE: Add config option for CBMEM stored console log.
    
    Some experiments have demonstrated that total amount of text
    generated by coreboot console when BIOS_SPEW level is enabled
    exceeds 40KB.
    
    Console output generated before DRAM is initialized can exceed
    2KB. This patch introduces the new configuration option and
    assigns adequate default values to cache based and DRAM based
    console buffers.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
     . run the following commands in the root directory
    
       cp config.stumpy .config
       make menuconfig
    
     . enable the new option (Console->Send console output to a CBMEM buffer)
     . save the configuration
    
    Observe the following settings added to the config:
    +CONFIG_CONSOLE_CBMEM=y
    +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
    +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
    
    Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5855
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index dbd11f6..fefbe2e 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT
 	  32 bytes of IO spaces will be used (and align on 32 bytes
 	  boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+	depends on EARLY_CBMEM_INIT
+	bool "Send console output to a CBMEM buffer"
+	default n
+	help
+	  Enable this to save the console output in a CBMEM buffer. This would
+	  allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in CBMEM"
+	default 0xae00
+	help
+	  Space allocated for console output storage in CBMEM. The default
+	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+	  even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in cash as RAM"
+	default 0xc00
+	help
+	  Console is used before RAM is initialized. This is the room reserved
+	  in the DCACHE based RAM to keep console output before it can be
+	  saved in a CBMEM buffer. 3K bytes should be enough even for the
+	  BIOS_SPEW level.
+
 
 choice
 	prompt "Maximum console log level"



From gerrit at coreboot.org  Tue Mar  6 00:52:43 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:43 +0100
Subject: [coreboot] New patch to review for coreboot: a14055f CBMEM CONSOLE:
	Add CBMEM console driver implementation.
References: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+0@gerrit.coreboot.org>
Message-ID: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/719

-gerrit

commit a14055f63ad05cc8e69e0a1999d1ea90f6889185
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Sep 29 17:27:15 2011 -0700

    CBMEM CONSOLE: Add CBMEM console driver implementation.
    
    The CBMEM console driver saves console output in a CBMEM area, which
    then is made available to Linux applications for perusing.
    
    There are some system limitations which need to be worked around
    to achieve this goal:
    
    - some console traffic is generated before DRAM is initialized,
      leave alone CBMEM initialized.
    
    - after the RAM based stage starts, a lot of traffic is generated
      before CBMEM is initialized.
    
    As a result, the console log lives in three different places -
    the bottom of the cache as RAM space, the CBMEM buffer (where it
    is expected to be) and a static buffer used early in the RAM
    stage.
    
    When execution starts (in the cache as RAM mode), the console
    buffer is allocated at the bottom of the cache as RAM memory
    address range. Once DRAM is initialized, the CBMEM structure is
    initialized, and then the console buffer contents are copied from
    the bottom of the cache as RAM space into the CBMEM area right
    before the cache as RAM mode is disabled. The
    src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
    copying.
    
    At this point the cache as RAM memory is about to be disabled,
    but the ROM stage is still going generating console output. To
    make sure this output is not lost, cbmemc_reinit() saves the new
    buffer address at a fixed location (0x600 was chosen for this),
    and the actual "printing" function checks to see if the RAM is
    already initialized (the stack is in RAM), and if so, gets the
    console buffer pointer from this location instead of using the
    cache as RAM address.
    
    When the RAM stage starts, a static buffer is used to store the
    console output, as the CBMEM buffer location is not known. Then,
    when CBMEM is reinitialized, cbmemc_reinit() again takes care of
    the copying.
    
    In case the allocated buffers are not large enough, the excessive
    data is dropped, and the copying routine adds some text to the
    output buffer to indicate that there has been data lost and how
    many characters were dropped.
    
    Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/cbmem_console.c         |   35 ++++++
 src/include/console/cbmem_console.h |   26 +++++
 src/include/console/console.h       |    3 +
 src/lib/cbmem_console.c             |  195 +++++++++++++++++++++++++++++++++++
 4 files changed, 259 insertions(+), 0 deletions(-)

diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c
new file mode 100644
index 0000000..2c43f5c
--- /dev/null
+++ b/src/console/cbmem_console.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+
+static void cbmemc_init_(void)
+{
+	cbmemc_init();
+}
+
+static void cbmemc_tx_byte_(unsigned char data)
+{
+	cbmemc_tx_byte(data);
+}
+
+static const struct console_driver cbmem_console __console = {
+	.init     = cbmemc_init_,
+	.tx_byte  = cbmemc_tx_byte_,
+};
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
new file mode 100644
index 0000000..37ea4d8
--- /dev/null
+++ b/src/include/console/cbmem_console.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+#ifndef _CONSOLE_CBMEM_CONSOLE_H_
+#define _CONSOLE_CBMEM_CONSOLE_H_
+
+void cbmemc_init(void);
+void cbmemc_reinit(void);
+void cbmemc_tx_byte(unsigned char data);
+
+#endif
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 54c825c..56e202d 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -33,6 +33,9 @@
 #if CONFIG_CONSOLE_NE2K
 #include <console/ne2k.h>
 #endif
+#if CONFIG_CONSOLE_CBMEM
+#include <console/cbmem_console.h>
+#endif
 
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
new file mode 100644
index 0000000..b58de48
--- /dev/null
+++ b/src/lib/cbmem_console.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <string.h>
+
+/*
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * whith buffer_body covering the extent of the memory. Once the buffer is
+ * full, the cursor keeps going but the data is dropped on the floor. This
+ * allows to tell how much data was lost in the process.
+ */
+struct cbmem_console {
+	u32 buffer_size;
+	u32 buffer_cursor;
+	u8  buffer_body[0];
+}  __attribute__ ((__packed__));
+
+#ifdef __PRE_RAM__
+/*
+ * While running from ROM, before DRAM is initialized, some area in cache as
+ * ram space is used for the console buffer storage. The size and location of
+ * the area are defined in the config.
+ */
+#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+/*
+ * Once DRAM is initialized and the cache as ram mode is disabled, while still
+ * running from ROM, the console buffer in the cache as RAM area becomes
+ * unavailable.
+ *
+ * By this time the console log buffer is already available in
+ * CBMEM. The location at 0x600 is used as the redirect pointer allowing to
+ * find out where the actual console log buffer is.
+ */
+#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600))
+#else
+
+/*
+ * When running from RAM, a lot of console output is generated before CBMEM is
+ * reinitialized. This static buffer is used to store that output temporarily,
+ * to be concatenated with the CBMEM console buffer contents accumulated
+ * during the ROM stage, once CBMEM becomes avaiklable at RAM stage.
+ */
+static u8 static_console[40000];
+static struct cbmem_console *cbmem_console_p;
+#endif
+
+void cbmemc_init(void)
+{
+#ifdef __PRE_RAM__
+	cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+#else
+	/*
+	 * Initializing before CBMEM is available, use static buffer to store
+	 * the log.
+	 */
+	cbmem_console_p = (struct cbmem_console *) static_console;
+	cbmem_console_p->buffer_size = sizeof(static_console) -
+		sizeof(struct cbmem_console);
+#endif
+	cbmem_console_p->buffer_cursor = 0;
+}
+
+void cbmemc_tx_byte(unsigned char data)
+{
+	struct cbmem_console *cbm_cons_p = cbmem_console_p;
+	u32 cursor;
+#ifdef __PRE_RAM__
+	/*
+	 * This check allows to tell if the cache as RAM mode has been exited
+	 * or not. If it has been exited, the real memory is being used
+	 * (resulting in the variable on the stack located below
+	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
+	 * actual console buffer is.
+	 */
+	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
+#endif
+	if (!cbm_cons_p)
+		return;
+
+	cursor = cbm_cons_p->buffer_cursor++;
+	if (cursor < cbm_cons_p->buffer_size)
+		cbm_cons_p->buffer_body[cursor] = data;
+}
+
+/*
+ * Copy the current console buffer (either from the cache as RAM area, or from
+ * the static buffer, pointed at by cbmem_console_p) into the CBMEM console
+ * buffer space (pointed at by new_cons_p), concatenating the copied data with
+ * the CBMEM console buffer contents.
+ *
+ * If there is overflow - add to the destination area a string, reporting the
+ * overflow and the number of dropped charactes.
+ */
+static void copy_console_buffer(struct cbmem_console *new_cons_p)
+{
+	u32 copy_size;
+	u32 cursor = new_cons_p->buffer_cursor;
+	int overflow = cbmem_console_p->buffer_cursor >
+		cbmem_console_p->buffer_size;
+
+	copy_size = overflow ?
+		cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor;
+
+	memcpy(new_cons_p->buffer_body + cursor,
+	       cbmem_console_p->buffer_body,
+	       copy_size);
+
+	cursor += copy_size;
+
+	if (overflow) {
+		const char loss_str1[] = "\n\n*** Log truncated, ";
+		const char loss_str2[] = " characters dropped. ***\n\n";
+		u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size;
+
+		/*
+		 * When running from ROM sprintf is not available, a simple
+		 * itoa implementation is used instead.
+		 */
+		int got_first_digit = 0;
+
+		/* Way more than possible number of dropped characters. */
+		u32 mult = 100000;
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1);
+		cursor += sizeof(loss_str1) - 1;
+
+		while (mult) {
+			int digit = dropped_chars / mult;
+			if (got_first_digit || digit) {
+				new_cons_p->buffer_body[cursor++] = digit + '0';
+				dropped_chars %= mult;
+				/* Excessive, but keeps it simple */
+				got_first_digit = 1;
+			}
+			mult /= 10;
+		}
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2);
+		cursor += sizeof(loss_str2) - 1;
+	}
+	new_cons_p->buffer_cursor = cursor;
+}
+
+void cbmemc_reinit(void)
+{
+	struct cbmem_console *cbm_cons_p;
+
+#ifdef __PRE_RAM__
+	cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE,
+			       CONFIG_CONSOLE_CBMEM_BUFFER_SIZE);
+	if (!cbm_cons_p) {
+		CBMEM_CONSOLE_REDIRECT = NULL;
+		return;
+	}
+
+	cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+
+	cbm_cons_p->buffer_cursor = 0;
+
+	copy_console_buffer(cbm_cons_p);
+
+	CBMEM_CONSOLE_REDIRECT = cbm_cons_p;
+#else
+	cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (!cbm_cons_p)
+		return;
+
+	copy_console_buffer(cbm_cons_p);
+
+	cbmem_console_p = cbm_cons_p;
+#endif
+}



From gerrit at coreboot.org  Tue Mar  6 00:52:44 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:44 +0100
Subject: [coreboot] New patch to review for coreboot: 48ce747 CBMEM CONSOLE:
	Add CBMEM type for console buffer.
References: <I02757c06d71e46af77b02b90b0e6018a37b62406+0@gerrit.coreboot.org>
Message-ID: <I02757c06d71e46af77b02b90b0e6018a37b62406+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720

-gerrit

commit 48ce747d48a0cc6c633e290fb1e66ada7c4142fd
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:13:06 2011 -0700

    CBMEM CONSOLE: Add CBMEM type for console buffer.
    
    Add CBMEM type for the console buffer section.
    
    Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    1 +
 src/lib/cbmem.c     |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index c3f10ef..a19ec5a 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_RESUME		0x5245534d
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_CONSOLE	0x434f4e53
 #define CBMEM_ID_NONE		0x00000000
 
 int cbmem_initialize(void);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index f800b04..b09b070 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -256,6 +256,7 @@ void cbmem_list(void)
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
 		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
 		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
+		case CBMEM_ID_CONSOLE:   printk(BIOS_DEBUG, "CONSOLE    "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);



From gerrit at coreboot.org  Tue Mar  6 00:52:45 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:45 +0100
Subject: [coreboot] New patch to review for coreboot: 7f3e86b CBMEM CONSOLE:
	Add code using the new console driver.
References: <Ifd1f492ce6321412a014333babbc5b3f14635988+0@gerrit.coreboot.org>
Message-ID: <Ifd1f492ce6321412a014333babbc5b3f14635988+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721

-gerrit

commit 7f3e86be5f19f90695f5247c7ff00746b84b1183
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:16:49 2011 -0700

    CBMEM CONSOLE: Add code using the new console driver.
    
    The new added code is compiled in when the CBMEM_CONSOLE config
    flag is enabled.
    
    Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/lib/romcc_console.c    |    3 +++
 src/arch/x86/lib/romstage_console.c |    3 +++
 src/boot/hardwaremain.c             |    3 +++
 src/console/console.c               |    5 ++++-
 4 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 13ee1f0..0e1f4e6 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void __console_tx_nibble(unsigned nibble)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 8adb3ba..0f22727 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void console_tx_flush(void)
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 3d15b55..9b293c0 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -92,6 +92,9 @@ void hardwaremain(int boot_complete)
 
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
diff --git a/src/console/console.c b/src/console/console.c
index d933668..8f60f04 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -87,7 +87,7 @@ int console_tst_byte(void)
 	return 0;
 }
 
-#else
+#else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
 void console_init(void)
 {
@@ -104,6 +104,9 @@ void console_init(void)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_init();
+#endif
 	static const char console_test[] =
 		"\n\ncoreboot-"
 		COREBOOT_VERSION



From gerrit at coreboot.org  Tue Mar  6 00:52:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:47 +0100
Subject: [coreboot] New patch to review for coreboot: 8d75b03 CBMEM CONSOLE:
	Enable coreboot CBMEM console.
References: <I91842b1ba0f89d611d3249b63c020a2713a9124f+0@gerrit.coreboot.org>
Message-ID: <I91842b1ba0f89d611d3249b63c020a2713a9124f+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722

-gerrit

commit 8d75b037fa5d497f0a4c6d0e82cbf5241e749f88
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 12:02:18 2011 -0700

    CBMEM CONSOLE: Enable coreboot CBMEM console.
    
    The appropriate Makefiles are modified to include the required
    source code in compilation.
    
    Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/Makefile.inc |    2 ++
 src/lib/Makefile.inc     |    2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..f3b8758 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
+driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
 $(obj)/console/console.romstage.o : $(obj)/build.h
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index db640dc..45cb788 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@@ -34,6 +35,7 @@ ramstage-y += clog2.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c



From gerrit at coreboot.org  Tue Mar  6 00:52:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:47 +0100
Subject: [coreboot] New patch to review for coreboot: c8604fe Introduce
	utility for parsing CBMEM contents.
References: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+0@gerrit.coreboot.org>
Message-ID: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723

-gerrit

commit c8604fe38a12fbd8cab09a6692f5574dccca234c
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 14:21:03 2011 -0700

    Introduce utility for parsing CBMEM contents.
    
    This is a python script which is supposed to run on a target
    which is controlled by coreboot. The script examines top of
    memory looking for the CBMEM signature at addresses aligned at
    128K boundary. Once the script finds the CBMEM, it iterates
    through the CBMEM table of contents and parses two entries: the
    timestamps and the console log.
    
    This submission is just a template to build upon to create a
    utility for displaying CBMEM information while running Linux on
    the target.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
    See test description of d81e6b8c8d41f2d6 for test procedure.
    
    Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5942
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbmem/cbmem.py |  204 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 204 insertions(+), 0 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
new file mode 100755
index 0000000..3e8476d
--- /dev/null
+++ b/util/cbmem/cbmem.py
@@ -0,0 +1,204 @@
+#!/usr/bin/python
+#
+# cbmem.py - Linux space CBMEM contents parser
+#
+# Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+'''
+Parse and display CBMEM contents.
+
+This module is meant to run on systems with coreboot based firmware.
+
+When started, it determines the amount of DRAM installed on the system, and
+then scans the top area of DRAM (right above the available memory size)
+looking for the CBMEM base signature at locations aligned at 0x20000
+boundaries.
+
+Once it finds the CBMEM signature, the utility parses the contents, reporting
+the section IDs/sizes and also reporting the contents of the tiemstamp and
+console sections.
+'''
+
+import mmap
+import re
+import struct
+import sys
+import time
+
+# These definitions follow src/include/cbmem.h
+CBMEM_MAGIC = 0x434f5245
+CBMEM_MAX_ENTRIES = 16
+
+CBMEM_ENTRY_FORMAT = '@LLQQ'
+CONSOLE_HEADER_FORMAT = '@LL'
+TIMESTAMP_HEADER_FORMAT = '@QLL'
+TIMESTAMP_ENTRY_FORMAT = '@LQ'
+
+mf_fileno = 0  # File number of the file providing access to memory.
+
+def align_up(base, alignment):
+    '''Increment to the alignment boundary.
+
+    Return the next integer larger than 'base' and divisible by 'alignment'.
+    '''
+
+    return base + alignment - base % alignment
+
+def normalize_timer(value, freq):
+    '''Convert timer reading into microseconds.
+
+    Get the free running clock counter value, divide it by the clock frequency
+    and multiply by 1 million to get reading in microseconds.
+
+    Then convert the value into an ASCII string with groups of three digits
+    separated by commas.
+
+    Inputs:
+      value: int, the clock reading
+      freq: float, the clock frequency
+
+    Returns:
+      A string presenting 'value' in microseconds.
+    '''
+
+    result = []
+    value = int(value * 1000000.0 / freq)
+    svalue = '%d' % value
+    vlength = len(svalue)
+    remainder = vlength % 3
+    if remainder:
+        result.append(svalue[0:remainder])
+    while remainder < vlength:
+        result.append(svalue[remainder:remainder+3])
+        remainder = remainder + 3
+    return ','.join(result)
+
+def get_cpu_freq():
+    '''Retrieve CPU frequency from sysfs.
+
+    Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source.
+    '''
+    freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq'
+                    ).read()
+    # Convert reading into Hertz
+    return float(freq_str) * 1000.0
+
+def get_mem_size():
+    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
+    mult = {
+        'kB': 1024
+        }
+    meminfo = open('/proc/meminfo').read()
+    m = re.search('MemTotal:.*\n', meminfo)
+    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
+    (_, size, mult_name) = mem_string.split()
+    return int(size) * mult[mult_name]
+
+def parse_mem_at(addr, format):
+    '''Read and parse a memory location.
+
+    This function reads memory at the passed in address, parses it according
+    to the passed in format specification and returns a list of values.
+
+    The first value in the list is the size of data matching the format
+    expression, and the rest of the elements of the list are the actual values
+    retrieved using the format.
+    '''
+
+    size = struct.calcsize(format)
+    delta = addr % 4096   # mmap requires the offset to be page size aligned.
+    mm = mmap.mmap(mf_fileno, size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mm.close()
+    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
+    return rv
+
+def dprint(text):
+    '''Debug print function.
+
+    Edit it to get the debug output.
+    '''
+
+    if False:
+        print text
+
+def process_timers(base):
+    '''Scan the array of timestamps found in CBMEM at address base.
+
+    For each timestamp print the timer ID and the value in microseconds.
+    '''
+
+    (step, base_time, max_entr, entr) = parse_mem_at(
+        base, TIMESTAMP_HEADER_FORMAT)
+
+    print('\ntime base %d, total entries %d' % (base_time, entr))
+    clock_freq = get_cpu_freq()
+    base = base + step
+    for i in range(entr):
+        (step, timer_id, timer_value) = parse_mem_at(
+            base, TIMESTAMP_ENTRY_FORMAT)
+        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
+        base = base + step
+    print
+
+def process_console(base):
+    '''Dump the console log buffer contents found at address base.'''
+
+    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
+    print 'cursor at %d\n' % cursor
+
+    cons_string_format = '%ds' % min(cursor, size)
+    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    print cons_text
+    print '\n'
+
+mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
+table_alignment = 128 * 1024
+
+mem_size = get_mem_size()
+
+# start at memory address aligned at 128K.
+offset = align_up(mem_size, table_alignment)
+
+dprint('mem_size %x offset %x' %(mem_size, offset))
+mf = open("/dev/mem")
+mf_fileno = mf.fileno()
+
+while offset % mem_alignment: # do not cross the 1G boundary while searching
+    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if magic == CBMEM_MAGIC:
+        offset = offset + step
+        break
+    offset += table_alignment
+else:
+    print 'Did not find the CBMEM'
+    sys.exit(0)
+
+for i in (range(1, CBMEM_MAX_ENTRIES)):
+    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if mid == 0:
+        break
+
+    print '%x, %x, %x' % (mid, base, size)
+    if mid == 0x54494d45:
+        process_timers(base)
+    if mid == 0x434f4e53:
+        process_console(base)
+
+    offset = offset + step
+
+mf.close()



From gerrit at coreboot.org  Tue Mar  6 00:52:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:48 +0100
Subject: [coreboot] New patch to review for coreboot: 34b7fda Refactor
	publishing CBMEM addresses through coreboot table.
References: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+0@gerrit.coreboot.org>
Message-ID: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724

-gerrit

commit 34b7fdad7c6865aeabc6024b1b3123c87b7c4ea6
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Mon Oct 3 14:58:57 2011 -0700

    Refactor publishing CBMEM addresses through coreboot table.
    
    We need to provide u-boot access to several different CBMEM
    sections. To do that, a common coreboot table structure is used,
    just different tags match different coreboot table sections.
    
    Also, the code is added to export CBMEM console and MRC cache
    addresses through the same mechanism.
    
    Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   59 +++++++++++++++++++++++++++++-------
 src/include/boot/coreboot_tables.h |    6 ++-
 2 files changed, 52 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f189e76..f29481b 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
-#if CONFIG_COLLECT_TIMESTAMPS
-static void lb_tsamp(struct lb_header *header)
+static void add_cbmem_pointers(struct lb_header *header)
 {
-	struct lb_tstamp *tstamp;
-	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+	/*
+	 * These CBMEM sections' addresses are included in the coreboot table
+	 * with the appropriate tags.
+	 */
+	const struct section_id {
+		int cbmem_id;
+		int table_tag;
+	} section_ids[] = {
+		{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+		{CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE},
+		{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+	};
+	int i;
 
-	if (!tstamp_table)
-		return;
+	for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+		const struct section_id *sid = section_ids + i;
+		struct lb_cbmem_ref *cbmem_ref;
+		void *cbmem_addr = cbmem_find(sid->cbmem_id);
 
-	tstamp = (struct lb_tstamp *)lb_new_record(header);
-	tstamp->tag = LB_TAG_TIMESTAMPS;
-	tstamp->size = sizeof(*tstamp);
-	tstamp->tstamp_tab = tstamp_table;
+		if (!cbmem_addr)
+			continue;  /* This section is not present */
 
+		cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+		if (!cbmem_ref) {
+			printk(BIOS_ERR, "No more room in coreboot table!\n");
+			break;
+		}
+		cbmem_ref->tag = sid->table_tag;
+		cbmem_ref->size = sizeof(*cbmem_ref);
+		cbmem_ref->cbmem_addr = cbmem_addr;
+	}
 }
-#endif
 
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
@@ -633,9 +651,28 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+<<<<<<< HEAD
 #if CONFIG_COLLECT_TIMESTAMPS
 	lb_tsamp(head);
 #endif
+=======
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+#endif
+#if CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head, serial);
+#endif
+	add_cbmem_pointers(head);
+
+>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table.
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 46d6489..5535a38 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -196,11 +196,13 @@ struct lb_framebuffer {
 };
 
 #define LB_TAG_TIMESTAMPS	0x0016
-struct lb_tstamp {
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+struct lb_cbmem_ref {
 	uint32_t tag;
 	uint32_t size;
 
-	void	*tstamp_tab;
+	void	*cbmem_addr;
 };
 
 /* The following structures are for the cmos definitions table */



From gerrit at coreboot.org  Tue Mar  6 00:52:49 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:49 +0100
Subject: [coreboot] New patch to review for coreboot: 43da2e7 Increase CBMEM
	to accommodate larger console.
References: <If583013dfb210de5028d69577675095c6fe2f3ab+0@gerrit.coreboot.org>
Message-ID: <If583013dfb210de5028d69577675095c6fe2f3ab+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725

-gerrit

commit 43da2e7b7483f2b640a8f8d7c06be684735c1e08
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Oct 4 10:44:16 2011 -0700

    Increase CBMEM to accommodate larger console.
    
    This change adds 128K to the memory amount set aside for CBMEM in
    case the CBMEM console is enabled (to keep the CBMEM 128K byte
    aligned). The console buffer size is being set to 64K, which is
    enough to accommodate the most verbose coreboot console and
    u-boot console.
    
    Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a19ec5a..6a48dd2 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,12 @@
 #define _CBMEM_H_
 
 /* Reserve 128k for ACPI and other tables */
+#if CONFIG_CONSOLE_CBMEM
+#define HIGH_MEMORY_DEF_SIZE	( 256 * 1024 )
+#else
 #define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#endif
+
 #ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
 #endif



From gerrit at coreboot.org  Tue Mar  6 00:52:51 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:51 +0100
Subject: [coreboot] New patch to review for coreboot: 474841c Fix typos in
	src/console/Kconfig
References: <Ia906077257e93622ad56bc54a42f8184ade78b29+0@gerrit.coreboot.org>
Message-ID: <Ia906077257e93622ad56bc54a42f8184ade78b29+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726

-gerrit

commit 474841cf56e9de1b3323bcb676567bfe09e4b187
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 4 16:21:17 2011 -0700

    Fix typos in src/console/Kconfig
    
    - cash -> Cache
    - make the new size of the cbmem console buffer the default
    
    Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index fefbe2e..2cfc4db 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -201,7 +201,7 @@ config CONSOLE_CBMEM
 config CONSOLE_CBMEM_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
 	hex "Room allocated for console output in CBMEM"
-	default 0xae00
+	default 0x10000
 	help
 	  Space allocated for console output storage in CBMEM. The default
 	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
@@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 
 config CONSOLE_CAR_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
-	hex "Room allocated for console output in cash as RAM"
+	hex "Room allocated for console output in Cache as RAM"
 	default 0xc00
 	help
 	  Console is used before RAM is initialized. This is the room reserved



From gerrit at coreboot.org  Tue Mar  6 00:52:52 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:52 +0100
Subject: [coreboot] New patch to review for coreboot: 7947060 Add
	infrastructure for global data in the CAR phase of boot.
References: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+0@gerrit.coreboot.org>
Message-ID: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727

-gerrit

commit 79470609d653dbd34cab2ebe1126047a9425c4e1
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Oct 1 04:27:32 2011 -0700

    Add infrastructure for global data in the CAR phase of boot.
    
    The cbmem console structure and car global data are put in their own section,
    with the cbmem console coming after the global data. These areas are linked
    to be where CAR is available and at the very bottom of the stack.
    
    There is one shortcoming of this change:
    The section created by this change needs to be stripped out by the Makefile
    since leaving it in confuses cbfstool when it installs the stage in the image.
    I would like to make the tools link those symbols at the right location but
    leave allocation of that space out of the ELF.
    
    Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/Makefile.inc      |    2 +-
 src/arch/x86/init/bootblock.ld |    7 +++++++
 src/include/cpu/x86/car.h      |   31 +++++++++++++++++++++++++++++++
 src/lib/cbmem_console.c        |    7 +++++--
 4 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 624b510..aeb4875 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	rm -f $@
 	cp $(obj)/coreboot.pre1 $@
 	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
-            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index bde0430..6f8ade8 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -51,5 +51,12 @@ SECTIONS
 		*(.eh_frame);
 	}
 
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h
new file mode 100644
index 0000000..2d2af03
--- /dev/null
+++ b/src/include/cpu/x86/car.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef CPU_X86_CAR_H
+#define CPU_X86_CAR_H
+
+#ifdef __PRE_RAM__
+#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\", at nobits#")))
+#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\", at nobits#")))
+#else
+#define CAR_GLOBAL
+#define CAR_CBMEM
+#endif
+
+#endif
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index b58de48..431ea1f 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <cbmem.h>
+#include <cpu/x86/car.h>
 #include <string.h>
 
 /*
@@ -39,7 +40,9 @@ struct cbmem_console {
  * ram space is used for the console buffer storage. The size and location of
  * the area are defined in the config.
  */
-#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+static struct cbmem_console car_cbmem_console CAR_CBMEM;
+#define cbmem_console_p (&car_cbmem_console)
 
 /*
  * Once DRAM is initialized and the cache as ram mode is disabled, while still
@@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data)
 	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
 	 * actual console buffer is.
 	 */
-	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+	if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console)
 		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
 #endif
 	if (!cbm_cons_p)



From gerrit at coreboot.org  Tue Mar  6 00:52:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:53 +0100
Subject: [coreboot] New patch to review for coreboot: 4b11a08 Detect whether
	the OXPCIE card is really present while in the ROM stage.
References: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+0@gerrit.coreboot.org>
Message-ID: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728

-gerrit

commit 4b11a084dd22603b3db7c8d58919732ec2dc063e
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:52:08 2011 -0700

    Detect whether the OXPCIE card is really present while in the ROM stage.
    
    Use an int in CAR global data to store whether or not the OXPCIE serial card
    is actually there. Also, time out if the card doesn't show up quickly enough,
    don't continue initialization if it's not there, and don't make the
    initialization routine default to a card if none is found.
    
    Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/lib/romstage_console.c      |    5 ++++-
 src/drivers/oxford/oxpcie/oxpcie_early.c |   20 +++++++++++++++++---
 src/include/uart8250.h                   |    5 +++++
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 0f22727..25eda9b 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte)
 		console_tx_byte('\r');
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
-	uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	if (oxford_oxpcie_present) {
+		uart8250_mem_tx_byte(
+			CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	}
 #endif
 #if CONFIG_CONSOLE_SERIAL8250
 	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 2c7767e..4f7a3cb 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -34,9 +36,13 @@
 #define OXPCIE_DEVICE_3 \
 	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
 
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
+
 void oxford_init(void)
 {
 	u16 reg16;
+	oxford_oxpcie_present = 1;
 
 	/* First we reset the secondary bus */
 	reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -69,11 +75,14 @@ void oxford_init(void)
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if
-	// no device is in the slot.
+	u32 timeout = 20000; // Timeout in 10s of microseconds.
 	u32 id = 0;
-	while ((id == 0) || (id == 0xffffffff))
+	for (;;) {
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+		if (!timeout-- || (id != 0 && id != 0xffffffff))
+			break;
+		udelay(10);
+	}
 
 	u32 device = OXPCIE_DEVICE; /* unknown default */
 	switch (id) {
@@ -90,6 +99,10 @@ void oxford_init(void)
 	case 0xc1581415: /* e.g. Startech MPEX2S952 */
 		device = OXPCIE_DEVICE;
 		break;
+	default:
+		/* No UART here. */
+		oxford_oxpcie_present = 0;
+		return;
 	}
 
 	/* Setup base address on device */
@@ -107,3 +120,4 @@ void oxford_init(void)
 	uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index aa510e5..71b9a5f 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
 u32 uartmem_getbaseaddr(void);
 
+#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
+	CONFIG_CONSOLE_SERIAL8250MEM
 /* and special init for OXPCIe based cards */
+extern int oxford_oxpcie_present;
+
 void oxford_init(void);
+#endif
 
 #endif /* __ROMCC__ */
 



From gerrit at coreboot.org  Tue Mar  6 00:52:54 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:54 +0100
Subject: [coreboot] New patch to review for coreboot: 5133024 If the memory
	mapped UART isn't present, leave it out of the cb tables.
References: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+0@gerrit.coreboot.org>
Message-ID: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729

-gerrit

commit 5133024b140f999487d9af0598406f06a7bdf92e
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:57:03 2011 -0700

    If the memory mapped UART isn't present, leave it out of the cb tables.
    
    This way u-boot won't try to use a UART that isn't plugged in.
    
    Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/boot/coreboot_table.c |   24 ++++++++++++++----------
 1 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f29481b..d24d7c4 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header)
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #elif CONFIG_CONSOLE_SERIAL8250MEM
-	struct lb_record *rec;
-	struct lb_serial *serial;
-	rec = lb_new_record(header);
-	serial = (struct lb_serial *)rec;
-	serial->tag = LB_TAG_SERIAL;
-	serial->size = sizeof(*serial);
-	serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial->baseaddr = uartmem_getbaseaddr();
-	serial->baud = CONFIG_TTYS0_BAUD;
-	return serial;
+	if (uartmem_getbaseaddr()) {
+		struct lb_record *rec;
+		struct lb_serial *serial;
+		rec = lb_new_record(header);
+		serial = (struct lb_serial *)rec;
+		serial->tag = LB_TAG_SERIAL;
+		serial->size = sizeof(*serial);
+		serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+		serial->baseaddr = uartmem_getbaseaddr();
+		serial->baud = CONFIG_TTYS0_BAUD;
+		return serial;
+	} else {
+		return NULL;
+	}
 #else
 	return NULL;
 #endif



From gerrit at coreboot.org  Tue Mar  6 00:52:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:52:56 +0100
Subject: [coreboot] New patch to review for coreboot: f2462af Don't run any
	option roms stored outside of the system flash
References: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+0@gerrit.coreboot.org>
Message-ID: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730

-gerrit

commit f2462af4c374f16da3fbd7bc630652623acf260e
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 6 16:47:51 2011 -0700

    Don't run any option roms stored outside of the system flash
    
    Right now coreboot only executes vga option roms. However, this is not
    good enough. For security reasons we want to execute only option roms
    stored in our RO CBFS.
    
    This patch adds a new option to disable execution of arbitrary option
    ROMs and enables it for all our boards.
    
    Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig   |   13 +++++++++++++
 src/devices/pci_rom.c |    6 ++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 572addc..98e8d9f 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -49,6 +49,19 @@ config PCI_ROM_RUN
 	  Examples include IDE/SATA controller option ROMs and option ROMs
 	  for network cards (NICs).
 
+config ON_DEVICE_ROM_RUN
+	bool "Run option ROMs on PCI devices"
+	default y
+	help
+	  Execute option ROMs that are stored on PCI/PCIe/AGP devices.
+
+	  If disabled, only option ROMs stored in CBFS will be executed. If
+	  you are concerned about security, you might want to disable this
+	  option, but it might leave your system in a state of degraded
+	  functionality.
+
+	  If unsure, say Y
+
 choice
 	prompt "Option ROM execution type"
 	default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 471c7e2..1b6f1da 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev)
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
+#if CONFIG_ON_DEVICE_ROM_RUN
 		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+#else
+		printk(BIOS_DEBUG, "On card option ROM execution disabled "
+			"for %s\n", dev_path(dev));
+		return NULL;
+#endif
 	}
 
 	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "



From gerrit at coreboot.org  Tue Mar  6 00:53:12 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:12 +0100
Subject: [coreboot] New patch to review for coreboot: e6e259b Add TPM
	support to coreboot
References: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+0@gerrit.coreboot.org>
Message-ID: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731

-gerrit

commit e6e259bc37761ddaaf6c1644bf23724bf561b827
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 11 14:46:25 2011 -0700

    Add TPM support to coreboot
    
    and initialize the TPM on S3 resume
    
    This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
    resume without including any other parts of vboot.
    
    We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
    (that are incompatible with coreboot's) and it does a lot more than we
    want it to do.
    
    Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig                            |    4 +
 src/arch/x86/boot/acpi.c               |    8 +
 src/include/pc80/tpm.h                 |   29 ++
 src/pc80/Makefile.inc                  |    1 +
 src/pc80/tpm.c                         |  554 ++++++++++++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot.c |  201 ++++++++++++
 6 files changed, 797 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 573868f..26e6dde 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -262,6 +262,10 @@ config IOAPIC
 	bool
 	default n
 
+config TPM
+	bool
+	default n
+
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
 	int
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..eb2e4e1 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void)
 	if (!acpi_is_wakeup())
 		return NULL;
 
+#ifdef CONFIG_CHROMEOS
+	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+	init_vboot();
+#endif
+
 	printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n");
 
 	/* Find RSDP. */
diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h
new file mode 100644
index 0000000..2eff15a
--- /dev/null
+++ b/src/include/pc80/tpm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef TPM_H_
+#define TPM_H_
+
+int tis_init(void);
+int tis_open(void);
+int tis_close(void);
+int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
+			size_t *recv_len);
+
+#endif /* TPM_H_ */
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 2c8a80e..cd6ea33 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -4,6 +4,7 @@ ramstage-y += i8254.c
 ramstage-y += i8259.c
 ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
 ramstage-y += keyboard.c
+ramstage-$(CONFIG_TPM) += tpm.c
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 subdirs-y += vga
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
new file mode 100644
index 0000000..1cbf800
--- /dev/null
+++ b/src/pc80/tpm.c
@@ -0,0 +1,554 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The code in this file has been heavily based on the article "Writing a TPM
+ * Device Driver" published on http://ptgmedia.pearsoncmg.com and the
+ * submission by Stefan Berger on Qemu-devel mailing list.
+ *
+ * One principal difference is that in the simplest config the other than 0
+ * TPM localities do not get mapped by some devices (for instance, by
+ * Infineon slb9635), so this driver provides access to locality 0 only.
+ */
+
+/* #define DEBUG */
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/byteorder.h>
+#include <console/console.h>
+#include <pc80/tpm.h>
+
+#ifdef DEBUG
+#define TPM_DEBUG_ON	1
+#else
+#define TPM_DEBUG_ON	0
+#endif
+
+#define PREFIX "lpc_tpm: "
+
+/* coreboot wrapper for TPM driver (start) */
+#define	TPM_DEBUG(fmt, args...)		\
+	if (TPM_DEBUG_ON) {		\
+		printk(BIOS_DEBUG, PREFIX);		\
+		printk(BIOS_DEBUG, fmt , ##args);	\
+	}
+#define printf(x...) printk(BIOS_ERR, x)
+
+#define min(a,b) MIN(a,b)
+#define max(a,b) MAX(a,b)
+#define readb(_a) (*(volatile unsigned char *) (_a))
+#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v))
+#define readl(_a) (*(volatile unsigned long *) (_a))
+#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v))
+/* coreboot wrapper for TPM driver (end) */
+
+#ifndef CONFIG_TPM_TIS_BASE_ADDRESS
+/* Base TPM address standard for x86 systems */
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+#endif
+
+/* the macro accepts the locality value, but only locality 0 is operational */
+#define TIS_REG(LOCALITY, REG) \
+    (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+
+/* hardware registers' offsets */
+#define TIS_REG_ACCESS                 0x0
+#define TIS_REG_INT_ENABLE             0x8
+#define TIS_REG_INT_VECTOR             0xc
+#define TIS_REG_INT_STATUS             0x10
+#define TIS_REG_INTF_CAPABILITY        0x14
+#define TIS_REG_STS                    0x18
+#define TIS_REG_DATA_FIFO              0x24
+#define TIS_REG_DID_VID                0xf00
+#define TIS_REG_RID                    0xf04
+
+/* Some registers' bit field definitions */
+#define TIS_STS_VALID                  (1 << 7) /* 0x80 */
+#define TIS_STS_COMMAND_READY          (1 << 6) /* 0x40 */
+#define TIS_STS_TPM_GO                 (1 << 5) /* 0x20 */
+#define TIS_STS_DATA_AVAILABLE         (1 << 4) /* 0x10 */
+#define TIS_STS_EXPECT                 (1 << 3) /* 0x08 */
+#define TIS_STS_RESPONSE_RETRY         (1 << 1) /* 0x02 */
+
+#define TIS_ACCESS_TPM_REG_VALID_STS   (1 << 7) /* 0x80 */
+#define TIS_ACCESS_ACTIVE_LOCALITY     (1 << 5) /* 0x20 */
+#define TIS_ACCESS_BEEN_SEIZED         (1 << 4) /* 0x10 */
+#define TIS_ACCESS_SEIZE               (1 << 3) /* 0x08 */
+#define TIS_ACCESS_PENDING_REQUEST     (1 << 2) /* 0x04 */
+#define TIS_ACCESS_REQUEST_USE         (1 << 1) /* 0x02 */
+#define TIS_ACCESS_TPM_ESTABLISHMENT   (1 << 0) /* 0x01 */
+
+#define TIS_STS_BURST_COUNT_MASK       (0xffff)
+#define TIS_STS_BURST_COUNT_SHIFT      (8)
+
+/*
+ * Error value returned if a tpm register does not enter the expected state
+ * after continuous polling. No actual TPM register reading ever returns ~0,
+ * so this value is a safe error indication to be mixed with possible status
+ * register values.
+ */
+#define TPM_TIMEOUT_ERR			(~0)
+
+/* Error value returned on various TPM driver errors */
+#define TPM_DRIVER_ERR		(~0)
+
+ /* 1 second is plenty for anything TPM does.*/
+#define MAX_DELAY_US	(1000 * 1000)
+
+/* Retrieve burst count value out of the status register contents. */
+#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \
+				   TIS_STS_BURST_COUNT_MASK))
+
+/*
+ * Structures defined below allow creating descriptions of TPM vendor/device
+ * ID information for run time discovery. The only device the system knows
+ * about at this time is Infineon slb9635
+ */
+struct device_name {
+	u16 dev_id;
+	const char * const dev_name;
+};
+
+struct vendor_name {
+	u16 vendor_id;
+	const char * vendor_name;
+	struct device_name* dev_names;
+};
+
+static struct device_name infineon_devices[] = {
+	{0xb, "SLB9635 TT 1.2"},
+	{0}
+};
+
+static const struct vendor_name vendor_names[] = {
+	{0x15d1, "Infineon", infineon_devices},
+};
+
+/*
+ * Cached vendor/device ID pair to indicate that the device has been already
+ * discovered
+ */
+static u32 vendor_dev_id;
+
+static int is_byte_reg(u32 reg)
+{
+	/*
+	 * These TPM registers are 8 bits wide and as such require byte access
+	 * on writes and truncated value on reads.
+	 */
+	return ((reg == TIS_REG_ACCESS)	||
+		(reg == TIS_REG_INT_VECTOR) ||
+		(reg == TIS_REG_DATA_FIFO));
+}
+
+/* TPM access functions are carved out to make tracing easier. */
+static u32 tpm_read(int locality, u32 reg)
+{
+	u32 value;
+	/*
+	 * Data FIFO register must be read and written in byte access mode,
+	 * otherwise the FIFO values are returned 4 bytes at a time.
+	 */
+	if (is_byte_reg(reg))
+		value = readb(TIS_REG(locality, reg));
+	else
+		value = readl(TIS_REG(locality, reg));
+
+	TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value);
+	return value;
+}
+
+static void tpm_write(u32 value, int locality,  u32 reg)
+{
+	TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value);
+
+	if (is_byte_reg(reg))
+		writeb(value & 0xff, TIS_REG(locality, reg));
+	else
+		writel(value, TIS_REG(locality, reg));
+}
+
+/*
+ * tis_wait_reg()
+ *
+ * Wait for at least a second for a register to change its state to match the
+ * expected state. Normally the transition happens within microseconds.
+ *
+ * @reg - the TPM register offset
+ * @locality - locality
+ * @mask - bitmask for the bitfield(s) to watch
+ * @expected - value the field(s) are supposed to be set to
+ *
+ * Returns the register contents in case the expected value was found in the
+ * appropriate register bits, or TPM_TIMEOUT_ERR on timeout.
+ */
+static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
+{
+	u32 time_us = MAX_DELAY_US;
+	while (time_us > 0) {
+		u32 value = tpm_read(locality, reg);
+		if ((value & mask) == expected)
+			return value;
+		udelay(1); /* 1 us */
+		time_us--;
+	}
+	return TPM_TIMEOUT_ERR;
+}
+
+/*
+ * Probe the TPM device and try determining its manufacturer/device name.
+ *
+ * Returns 0 on success (the device is found or was found during an earlier
+ * invocation) or TPM_DRIVER_ERR if the device is not found.
+ */
+static u32 tis_probe(void)
+{
+	u32 didvid = tpm_read(0, TIS_REG_DID_VID);
+	int i;
+	const char *device_name = "unknown";
+	const char *vendor_name = device_name;
+	u16 vid, did;
+
+	if (vendor_dev_id)
+		return 0;  /* Already probed. */
+
+	if (!didvid || (didvid == 0xffffffff)) {
+		printf("%s: No TPM device found\n", __FUNCTION__);
+		return TPM_DRIVER_ERR;
+	}
+
+	vendor_dev_id = didvid;
+
+	vid = didvid & 0xffff;
+	did = (didvid >> 16) & 0xffff;
+	for (i = 0; i < ARRAY_SIZE(vendor_names); i++) {
+		int j = 0;
+		u16 known_did;
+		if (vid == vendor_names[i].vendor_id) {
+			vendor_name = vendor_names[i].vendor_name;
+		}
+		while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+			if (known_did == did) {
+				device_name =
+					vendor_names[i].dev_names[j].dev_name;
+				break;
+			}
+			j++;
+		}
+		break;
+	}
+	/* this will have to be converted into debug printout */
+	TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name);
+	return 0;
+}
+
+/*
+ * tis_senddata()
+ *
+ * send the passed in data to the TPM device.
+ *
+ * @data - address of the data to send, byte by byte
+ * @len - length of the data to send
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
+ * not accept the entire command).
+ */
+static u32 tis_senddata(const u8 * const data, u32 len)
+{
+	u32 offset = 0;
+	u16 burst = 0;
+	u32 max_cycles = 0;
+	u8 locality = 0;
+	u32 value;
+
+	value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY,
+			     TIS_STS_COMMAND_READY);
+	if (value == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to get 'command_ready' status\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+	burst = BURST_COUNT(value);
+
+	while (1) {
+		unsigned count;
+
+		/* Wait till the device is ready to accept more data. */
+		while (!burst) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d failed to feed %d bytes of %d\n",
+				       __FILE__, __LINE__, len - offset, len);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS));
+		}
+
+		max_cycles = 0;
+
+		/*
+		 * Calculate number of bytes the TPM is ready to accept in one
+		 * shot.
+		 *
+		 * We want to send the last byte outside of the loop (hence
+		 * the -1 below) to make sure that the 'expected' status bit
+		 * changes to zero exactly after the last byte is fed into the
+		 * FIFO.
+		 */
+		count = min(burst, len - offset - 1);
+		while (count--)
+			tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+		value = tis_wait_reg(TIS_REG_STS, locality,
+				     TIS_STS_VALID, TIS_STS_VALID);
+
+		if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) {
+			printf("%s:%d TPM command feed overflow\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		burst = BURST_COUNT(value);
+		if ((offset == (len - 1)) && burst)
+			/*
+			 * We need to be able to send the last byte to the
+			 * device, so burst size must be nonzero before we
+			 * break out.
+			 */
+			break;
+	}
+
+	/* Send the last byte. */
+	tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+	/*
+	 * Verify that TPM does not expect any more data as part of this
+	 * command.
+	 */
+	value = tis_wait_reg(TIS_REG_STS, locality,
+			     TIS_STS_VALID, TIS_STS_VALID);
+	if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) {
+		printf("%s:%d unexpected TPM status 0x%x\n",
+		       __FILE__, __LINE__, value);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* OK, sitting pretty, let's start the command execution. */
+	tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_readresponse()
+ *
+ * read the TPM device response after a command was issued.
+ *
+ * @buffer - address where to read the response, byte by byte.
+ * @len - pointer to the size of buffer
+ *
+ * On success stores the number of received bytes to len and returns 0. On
+ * errors (misformatted TPM data or synchronization problems) returns
+ * TPM_DRIVER_ERR.
+ */
+static u32 tis_readresponse(u8 *buffer, size_t *len)
+{
+	u16 burst_count;
+	u32 status;
+	u32 offset = 0;
+	u8 locality = 0;
+	const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+	u32 expected_count = *len;
+	int max_cycles = 0;
+
+	/* Wait for the TPM to process the command */
+	status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data);
+	if (status == TPM_TIMEOUT_ERR) {
+		printf("%s:%d failed processing command\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	do {
+		while ((burst_count = BURST_COUNT(status)) == 0) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d TPM stuck on read\n",
+				       __FILE__, __LINE__);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			status = tpm_read(locality, TIS_REG_STS);
+		}
+
+		max_cycles = 0;
+
+		while (burst_count-- && (offset < expected_count)) {
+			buffer[offset++] = (u8) tpm_read(locality,
+							 TIS_REG_DATA_FIFO);
+			if (offset == 6) {
+				/*
+				 * We got the first six bytes of the reply,
+				 * let's figure out how many bytes to expect
+				 * total - it is stored as a 4 byte number in
+				 * network order, starting with offset 2 into
+				 * the body of the reply.
+				 */
+				u32 real_length;
+				memcpy(&real_length,
+				       buffer + 2,
+				       sizeof(real_length));
+				expected_count = be32_to_cpu(real_length);
+
+				if ((expected_count < offset) ||
+				    (expected_count > *len)) {
+					printf("%s:%d bad response size %d\n",
+					       __FILE__, __LINE__,
+					       expected_count);
+					return TPM_DRIVER_ERR;
+				}
+			}
+		}
+
+		/* Wait for the next portion */
+		status = tis_wait_reg(TIS_REG_STS, locality,
+				      TIS_STS_VALID, TIS_STS_VALID);
+		if (status == TPM_TIMEOUT_ERR) {
+			printf("%s:%d failed to read response\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		if (offset == expected_count)
+			break;	/* We got all we need */
+
+	} while ((status & has_data) == has_data);
+
+	/*
+	 * Make sure we indeed read all there was. The TIS_STS_VALID bit is
+	 * known to be set.
+	 */
+	if (status & TIS_STS_DATA_AVAILABLE) {
+		printf("%s:%d wrong receive status %x\n",
+		       __FILE__, __LINE__, status);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* Tell the TPM that we are done. */
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	*len = offset;
+	return 0;
+}
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void)
+{
+	if (tis_probe())
+		return TPM_DRIVER_ERR;
+	return 0;
+}
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on failure.
+ */
+int tis_open(void)
+{
+	u8 locality = 0; /* we use locality zero for everything */
+
+	if (tis_close())
+		return TPM_DRIVER_ERR;
+
+	/* now request access to locality */
+	tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS);
+
+	/* did we get a lock? */
+	if (tis_wait_reg(TIS_REG_ACCESS, locality,
+			 TIS_ACCESS_ACTIVE_LOCALITY,
+			 TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to lock locality %d\n",
+		       __FILE__, __LINE__, locality);
+		return TPM_DRIVER_ERR;
+	}
+
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void)
+{
+	u8 locality = 0;
+	if (tpm_read(locality, TIS_REG_ACCESS) &
+	    TIS_ACCESS_ACTIVE_LOCALITY) {
+		tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS);
+
+		if (tis_wait_reg(TIS_REG_ACCESS, locality,
+				 TIS_ACCESS_ACTIVE_LOCALITY, 0) ==
+		    TPM_TIMEOUT_ERR) {
+			printf("%s:%d - failed to release locality %d\n",
+			       __FILE__, __LINE__, locality);
+			return TPM_DRIVER_ERR;
+		}
+	}
+	return 0;
+}
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or TPM_DRIVER_ERR on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size,
+		 uint8_t *recvbuf, size_t *recv_len)
+{
+	if (tis_senddata(sendbuf, send_size)) {
+		printf("%s:%d failed sending data to TPM\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	return tis_readresponse(recvbuf, recv_len);
+}
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
new file mode 100644
index 0000000..e0a8c9b
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <pc80/tpm.h>
+#include "chromeos.h"
+
+//#define EXTRA_LOGGING
+
+#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
+
+#define TPM_SUCCESS               ((u32)0x00000000)
+
+#define TPM_E_IOERROR             ((u32)0x0000001f)
+#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004)
+#define TPM_E_NON_FATAL           ((u32)0x00000800)
+#define TPM_E_INVALID_POSTINIT    ((u32)0x00000026)
+
+#define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
+#define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
+
+static const struct {
+	u8 buffer[12];
+} tpm_resume_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 }
+};
+
+static const struct {
+	u8 buffer[10];
+} tpm_continueselftest_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 }
+};
+
+static inline void FromTpmUint32(const u8 * buffer, u32 * x)
+{
+	*x = ((buffer[0] << 24) |
+	      (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]);
+}
+
+static inline int TpmCommandSize(const u8 * buffer)
+{
+	u32 size;
+	FromTpmUint32(buffer + sizeof(u16), &size);
+	return (int)size;
+}
+
+/* Gets the code field of a TPM command. */
+static inline int TpmCommandCode(const u8 * buffer)
+{
+	u32 code;
+	FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code);
+	return code;
+}
+
+/* Gets the return code field of a TPM result. */
+static inline int TpmReturnCode(const u8 * buffer)
+{
+	return TpmCommandCode(buffer);
+}
+
+/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or
+ * DOING_SELFTEST errors are returned.
+ */
+static u32 TlclSendReceiveNoRetry(const u8 * request,
+				  u8 * response, int max_length)
+{
+	size_t response_length = max_length;
+	u32 result;
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n",
+	       request[0], request[1],
+	       request[2], request[3], request[4], request[5],
+	       request[6], request[7], request[8], request[9]);
+#endif
+
+	result = TPM_SUCCESS;
+	if (tis_sendrecv
+	    (request, TpmCommandSize(request), response, &response_length))
+		result = TPM_E_IOERROR;
+
+	if (0 != result) {
+		/* Communication with TPM failed, so response is garbage */
+		printk(BIOS_DEBUG,
+		       "TPM: command 0x%x send/receive failed: 0x%x\n",
+		       TpmCommandCode(request), result);
+		return TPM_E_COMMUNICATION_ERROR;
+	}
+	/* Otherwise, use the result code from the response */
+	result = TpmReturnCode(response);
+
+/* TODO: add paranoia about returned response_length vs. max_length
+ * (and possibly expected length from the response header).  See
+ * crosbug.com/17017 */
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n",
+	       response[0], response[1],
+	       response[2], response[3], response[4], response[5],
+	       response[6], response[7], response[8], response[9]);
+#endif
+
+	printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n",
+	       TpmCommandCode(request), result);
+
+	return result;
+}
+
+static inline u32 TlclContinueSelfTest(void)
+{
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+	printk(BIOS_DEBUG, "TPM: Continue self test\n");
+	/* Call the No Retry version of SendReceive to avoid recursion. */
+	return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer,
+				      response, sizeof(response));
+}
+
+/* Sends a TPM command and gets a response.  Returns 0 if success or the TPM
+ * error code if error. In the firmware, waits for the self test to complete
+ * if needed. In the host, reports the first error without retries. */
+static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
+{
+	u32 result = TlclSendReceiveNoRetry(request, response, max_length);
+	/* When compiling for the firmware, hide command failures due to the self
+	 * test not having run or completed. */
+	/* If the command fails because the self test has not completed, try it
+	 * again after attempting to ensure that the self test has completed. */
+	if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) {
+		result = TlclContinueSelfTest();
+		if (result != TPM_SUCCESS) {
+			return result;
+		}
+#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE)
+		/* Retry only once */
+		result = TlclSendReceiveNoRetry(request, response, max_length);
+#else
+		/* This needs serious testing.  The TPM specification says:
+		 * "iii. The caller MUST wait for the actions of
+		 * TPM_ContinueSelfTest to complete before reissuing the
+		 * command C1."  But, if ContinueSelfTest is non-blocking, how
+		 * do we know that the actions have completed other than trying
+		 * again? */
+		do {
+			result =
+			    TlclSendReceiveNoRetry(request, response,
+						   max_length);
+		} while (result == TPM_E_DOING_SELFTEST);
+#endif
+	}
+
+	return result;
+}
+
+void init_vboot(void)
+{
+	u32 result;
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+
+	printk(BIOS_DEBUG, "TPM: Init\n");
+	if (tis_init())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Open\n");
+	if (tis_open())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Resume\n");
+
+	result =
+	    TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response));
+
+	if (result == TPM_E_INVALID_POSTINIT) {
+		/* We're on a platform where the TPM maintains power in S3, so
+		 * it's already initialized. */
+		printk(BIOS_DEBUG, "TPM: Already initialized.\n");
+		return;
+	}
+	if (result == TPM_SUCCESS) {
+		printk(BIOS_DEBUG, "TPM: OK.\n");
+		return;
+	}
+	// TODO(reinauer) hard reboot?
+}



From gerrit at coreboot.org  Tue Mar  6 00:53:17 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:17 +0100
Subject: [coreboot] New patch to review for coreboot: 3cf8407 selfboot:
	Allow loading SeaBIOS into a reserved region in the lower 1MB
	This fixes loading SeaBIOS when lower memory is reserved.
References: <Idbdcaf95f3307f97307f304d6d677406d059927d+0@gerrit.coreboot.org>
Message-ID: <Idbdcaf95f3307f97307f304d6d677406d059927d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732

-gerrit

commit 3cf8407dff32d39a8e6365f17bd4455b2f009964
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 18 15:11:04 2011 -0700

    selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB
    This fixes loading SeaBIOS when lower memory is reserved.
    
    Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index fe56653..bbf160e 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer,
 		}
 	}
 	if (i == mem_entries) {
+		if (start < (1024*1024) && end <=(1024*1024)) {
+			printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded"
+				" into a reserved area in the lower 1MB\n");
+			return 1;
+		}
 		printk(BIOS_ERR, "No matching ram area found for range:\n");
 		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
 		printk(BIOS_ERR, "Ram areas\n");



From gerrit at coreboot.org  Tue Mar  6 00:53:18 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:18 +0100
Subject: [coreboot] New patch to review for coreboot: a58c8a3 Add timestamps
	for selfboot and acpi wake
References: <I28224867610b947739d940d25c98399d219f10f4+0@gerrit.coreboot.org>
Message-ID: <I28224867610b947739d940d25c98399d219f10f4+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733

-gerrit

commit a58c8a3e3a4226a9eadd63f65e0f262ac1e74c57
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Oct 19 15:32:39 2011 -0700

    Add timestamps for selfboot and acpi wake
    
    Change-Id: I28224867610b947739d940d25c98399d219f10f4
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/boot/acpi.c |    7 +++++++
 src/boot/selfboot.c      |    7 +++++++
 src/include/timestamp.h  |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index eb2e4e1..d4d554c 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
@@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector)
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
 }
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index bbf160e..d4ab8c8 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -29,6 +29,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <lib.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 
 /* Maximum physical address we can use for the coreboot bounce buffer. */
 #ifndef MAX_ADDR
@@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(POST_ENTER_ELF_BOOT);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_SELFBOOT_JUMP);
+#endif
+
 	/* Jump to kernel */
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index cfa06e2..8b9a89a 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -37,6 +37,8 @@ struct timestamp_table {
 enum timestamp_id {
 	TS_BEFORE_INITRAM = 1,
 	TS_AFTER_INITRAM = 2,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
 };
 
 void timestamp_init(tsc_t base);



From gerrit at coreboot.org  Tue Mar  6 00:53:19 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:19 +0100
Subject: [coreboot] New patch to review for coreboot: 311ab73 tell
	superiotool about the ITE 8772
References: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+0@gerrit.coreboot.org>
Message-ID: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734

-gerrit

commit 311ab730491b4846a499a4a2694176bec93070ae
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 17:12:53 2011 +0000

    tell superiotool about the ITE 8772
    
    no dumping yet
    
    Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/superiotool/ite.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index c83d788..e186e10 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = {
 		{EOT}}},
 	{0x8761, "IT8761E", {
 		{EOT}}},
+	{0x8772, "IT8772F", {
+		{EOT}}},
 	{0x8780, "IT8780F", {
 		{EOT}}},
 	{EOT}



From gerrit at coreboot.org  Tue Mar  6 00:53:20 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:20 +0100
Subject: [coreboot] New patch to review for coreboot: 6e237f3 Add support
	for enabling PCIe Common Clock and ASPM
References: <I3fe46282eada67629e9eeeed07e487dff54f2729+0@gerrit.coreboot.org>
Message-ID: <I3fe46282eada67629e9eeeed07e487dff54f2729+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735

-gerrit

commit 6e237f330edcfee3ec6ca0202e919ab9e2441966
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Oct 25 14:15:11 2011 -0700

    Add support for enabling PCIe Common Clock and ASPM
    
    These are guarded by individual Kconfig entries. The deprecated
    CONFIG_PCIE_TUNING defines have been removed in favor of using specific
    config options.
    
    This is the generic half, there is board-specific pieces
    still to come that tune before and after ASPM is enabled.
    
    Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/devices/Kconfig          |   14 +++
 src/devices/pciexp_device.c  |  188 +++++++++++++++++++++++++++++++++++++++---
 src/include/device/pci_def.h |    7 ++
 src/include/device/pciexp.h  |    7 ++
 4 files changed, 205 insertions(+), 11 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 98e8d9f..7429bda 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	default y
+
+config PCIEXP_COMMON_CLOCK
+	prompt "Enable PCIe Common Clock"
+	bool
+	default n
+	help
+	  Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+	prompt "Enable PCIe ASPM"
+	bool
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 5d33942..36f3e6a 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -19,31 +19,197 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
+#if CONFIG_PCIEXP_COMMON_CLOCK
+/*
+ * Re-train a PCIe link
+ */
+#define PCIE_TRAIN_RETRY 10000
+static int pciexp_retrain_link(device_t dev, unsigned cap)
+{
+	unsigned try = PCIE_TRAIN_RETRY;
+	u16 lnk;
+
+	/* Start link retraining */
+	lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
+	lnk |= PCI_EXP_LNKCTL_RL;
+	pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
+
+	/* Wait for training to complete */
+	while (try--) {
+		lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+		if (!(lnk & PCI_EXP_LNKSTA_LT))
+			return 0;
+		udelay(100);
+	}
+
+	printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+	return -1;
+}
+
+/*
+ * Check the Slot Clock Configuration for root port and endpoint
+ * and enable Common Clock Configuration if possible.  If CCC is
+ * enabled the link must be retrained.
+ */
+static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
+				       device_t endp, unsigned endp_cap)
+{
+	u16 root_scc, endp_scc, lnkctl;
+
+	/* Get Slot Clock Configuration for root port */
+	root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
+	root_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Get Slot Clock Configuration for endpoint */
+	endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
+	endp_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Enable Common Clock Configuration and retrain */
+	if (root_scc && endp_scc) {
+		printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
+
+		/* Set in endpoint */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set in root port */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Retrain link if CCC was enabled */
+		pciexp_retrain_link(root, root_cap);
+	}
+}
+#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
+
+#if CONFIG_PCIEXP_ASPM
+/*
+ * Determine the ASPM L0s or L1 exit latency for a link
+ * by checking both root port and endpoint and returning
+ * the highest latency value.
+ */
+static int pciexp_aspm_latency(device_t root, unsigned root_cap,
+			       device_t endp, unsigned endp_cap,
+			       enum aspm_type type)
+{
+	int root_lat = 0, endp_lat = 0;
+	u32 root_lnkcap, endp_lnkcap;
+
+	root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+	endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
+
+	/* Make sure the link supports this ASPM type by checking
+	 * capability bits 11:10 with aspm_type offset by 1 */
+	if (!(root_lnkcap & (1 << (type + 9))) ||
+	    !(endp_lnkcap & (1 << (type + 9))))
+		return -1;
+
+	/* Find the one with higher latency */
+	switch (type) {
+	case PCIE_ASPM_L0S:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		break;
+	case PCIE_ASPM_L1:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		break;
+	default:
+		return -1;
+	}
+
+	return (endp_lat > root_lat) ? endp_lat : root_lat;
+}
+
+/*
+ * Enable ASPM on PCIe root port and endpoint.
+ *
+ * Returns APMC value:
+ *   -1 = Error
+ *    0 = no ASPM
+ *    1 = L0s Enabled
+ *    2 = L1 Enabled
+ *    3 = L0s and L1 Enabled
+ */
+static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
+					 device_t endp, unsigned endp_cap)
+{
+	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	int exit_latency, ok_latency;
+	u16 lnkctl;
+	u32 devcap;
+
+	/* Get endpoint device capabilities for acceptable limits */
+	devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
+
+	/* Enable L0s if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L0S);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L0S;
+
+	/* Enable L1 if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L1);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L1;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set APMC in root port first */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set APMC in endpoint device next */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+	}
+
+	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
+	return apmc;
+}
+#endif /* CONFIG_PCIEXP_ASPM */
+
 static void pciexp_tune_dev(device_t dev)
 {
-	unsigned int cap;
-#if CONFIG_PCIE_TUNING
-	u32 reg32;
-#endif
+	device_t root = dev->bus->dev;
+	unsigned int root_cap, cap;
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
 		return;
 
-#if CONFIG_PCIE_TUNING
-	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
+	root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+	if (!root_cap)
+		return;
+
+#if CONFIG_PCIEXP_COMMON_CLOCK
+	/* Check for and enable Common Clock */
+	pciexp_enable_common_clock(root, root_cap, dev, cap);
+#endif
 
-	// TODO make this depending on ASPM.
+#if CONFIG_PCIEXP_ASPM
+	/* Check for and enable ASPM */
+	enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
 
-	/* Enable ASPM role based error reporting. */
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Enable ASPM role based error reporting. */
+		u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+		reg32 |= PCI_EXP_DEVCAP_RBER;
+		pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	}
 #endif
 }
 
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1..58a7321 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
 #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
+#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
+#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
 #define PCI_EXP_SLTCTL		24	/* Slot Control */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211..87a5002 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
 #define DEVICE_PCIEXP_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+enum aspm_type {
+	PCIE_ASPM_NONE = 0,
+	PCIE_ASPM_L0S  = 1,
+	PCIE_ASPM_L1   = 2,
+	PCIE_ASPM_BOTH = 3,
+};
+
 unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn, unsigned int max);
 unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);



From gerrit at coreboot.org  Tue Mar  6 00:53:22 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:22 +0100
Subject: [coreboot] New patch to review for coreboot: 6c49581 Add faster,
	architecture dependent memcpy()
References: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+0@gerrit.coreboot.org>
Message-ID: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736

-gerrit

commit 6c495814c7da47fff7db57267915f5290ab1d560
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 23:43:34 2011 +0000

    Add faster, architecture dependent memcpy()
    
    Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/Kconfig          |    4 ++++
 src/arch/x86/lib/Makefile.inc |    4 ++++
 src/arch/x86/lib/memcpy.c     |   13 +++++++++++++
 src/lib/Makefile.inc          |    9 ++++++++-
 4 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..74933af 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMCPY
+	bool
+	default y
+
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3388a9d..f99e429 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memcpy.c
+
+smm-y += memcpy.c
 
 $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h
diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c
new file mode 100644
index 0000000..de21092
--- /dev/null
+++ b/src/arch/x86/lib/memcpy.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+void *memcpy(void *__restrict __dest,
+	     __const void *__restrict __src, size_t __n)
+{
+	asm("cld\n"
+	    "rep\n"
+	    "movsb"
+	    :	/* no input (?) */
+	    :"S"(__src), "D"(__dest), "c"(__n)
+	);
+	return __dest;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 45cb788..61b6451 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -2,7 +2,9 @@
 
 romstage-y += memset.c
 romstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
+endif
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-y += memset.c
 ramstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c
+endif
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
 ramstage-y += malloc.c
@@ -43,7 +47,10 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
-smm-y += memcpy.c cbfs.c memset.c memcmp.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
+smm-y += memcpy.c
+endif
+smm-y += cbfs.c memset.c memcmp.c
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 smm-$(CONFIG_USBDEBUG) += usbdebug.c



From gerrit at coreboot.org  Tue Mar  6 00:53:22 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:22 +0100
Subject: [coreboot] New patch to review for coreboot: 02adb9a add native
	memset() function on x86.
References: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+0@gerrit.coreboot.org>
Message-ID: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/737

-gerrit

commit 02adb9a045c12eda0797fbe1b7e832cd742b3de7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 26 22:11:52 2011 +0000

    add native memset() function on x86.
    
    Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig          |    4 ++
 src/arch/x86/lib/Makefile.inc |    2 +
 src/arch/x86/lib/memset.c     |   86 +++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc          |    4 ++
 4 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 74933af..078ae95 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMSET
+	bool
+	default y
+
 config HAVE_ARCH_MEMCPY
 	bool
 	default y
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index f99e429..3f4dc95 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,10 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memset.c
 ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memset.c
 romstage-y += memcpy.c
 
 smm-y += memcpy.c
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
new file mode 100644
index 0000000..e850726
--- /dev/null
+++ b/src/arch/x86/lib/memset.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <string.h>
+#include <stdint.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+	int d0;
+	unsigned long int dstp = (unsigned long int) dstpp;
+
+	/* This explicit register allocation improves code very much indeed. */
+	register op_t x asm("ax");
+
+	x = (unsigned char) c;
+
+	/* Clear the direction flag, so filling will move forward.  */
+	asm volatile("cld");
+
+	/* This threshold value is optimal.  */
+	if (len >= 12) {
+		/* Fill X with four copies of the char we want to fill with. */
+		x |= (x << 8);
+		x |= (x << 16);
+
+		/* Adjust LEN for the bytes handled in the first loop.  */
+		len -= (-dstp) % sizeof(op_t);
+
+		/*
+		 * There are at least some bytes to set. No need to test for
+		 * LEN == 0 in this alignment loop.
+		 */
+
+		/* Fill bytes until DSTP is aligned on a longword boundary. */
+		asm volatile(
+			"rep\n"
+			"stosb" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+			"memory");
+
+		/* Fill longwords.  */
+		asm volatile(
+			"rep\n"
+			"stosl" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+			"memory");
+		len %= sizeof(op_t);
+	}
+
+	/* Write the last few bytes. */
+	asm volatile(
+		"rep\n"
+		"stosb" /* %0, %2, %3 */ :
+		"=D" (dstp), "=c" (d0) :
+		"0" (dstp), "1" (len), "a" (x) :
+		"memory");
+
+	return dstpp;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 61b6451..8ce72b2 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,6 +1,8 @@
 
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 romstage-y += memset.c
+endif
 romstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
+endif
 ramstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c



From gerrit at coreboot.org  Tue Mar  6 00:53:23 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:23 +0100
Subject: [coreboot] New patch to review for coreboot: cbc6faa Make TPM
	driver work in rom stage.
References: <Ifc827d0cd0159aa3f6752d395974f2812334f262+0@gerrit.coreboot.org>
Message-ID: <Ifc827d0cd0159aa3f6752d395974f2812334f262+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738

-gerrit

commit cbc6faa6960ec494785b24688c3872e2a74721ff
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 27 21:28:25 2011 +0000

    Make TPM driver work in rom stage.
    
    Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/tpm.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 1cbf800..8e94303 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -35,6 +35,7 @@
 #include <arch/byteorder.h>
 #include <console/console.h>
 #include <pc80/tpm.h>
+#include <cpu/x86/car.h>
 
 #ifdef DEBUG
 #define TPM_DEBUG_ON	1
@@ -130,10 +131,10 @@ struct device_name {
 struct vendor_name {
 	u16 vendor_id;
 	const char * vendor_name;
-	struct device_name* dev_names;
+	const struct device_name* dev_names;
 };
 
-static struct device_name infineon_devices[] = {
+static const struct device_name infineon_devices[] = {
 	{0xb, "SLB9635 TT 1.2"},
 	{0}
 };
@@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = {
  * Cached vendor/device ID pair to indicate that the device has been already
  * discovered
  */
-static u32 vendor_dev_id;
+static u32 vendor_dev_id CAR_GLOBAL;
 
 static int is_byte_reg(u32 reg)
 {



From gerrit at coreboot.org  Tue Mar  6 00:53:25 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Tue, 6 Mar 2012 00:53:25 +0100
Subject: [coreboot] New patch to review for coreboot: c927439 Add an option
	to keep the ROM cached after romstage
References: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+0@gerrit.coreboot.org>
Message-ID: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739

-gerrit

commit c927439853e094f4e687f5069c4a577104c7ac56
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 2 16:12:34 2011 -0700

    Add an option to keep the ROM cached after romstage
    
    Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/include/arch/acpi.h |    4 +++-
 src/cpu/x86/Kconfig              |    4 +++-
 src/cpu/x86/lapic/Makefile.inc   |    1 +
 src/cpu/x86/lapic/boot_cpu.c     |    3 ++-
 src/cpu/x86/mtrr/mtrr.c          |   14 +++++++++++++-
 src/include/cpu/x86/lapic.h      |    4 ++++
 6 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..504d71b 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,6 +435,7 @@ void generate_cpu_entries(void);
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
 
 #endif
 
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 348f0ef..fdbd527 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -39,4 +39,6 @@ config LOGICAL_CPUS
 	bool
 	default y
 
-
+config CACHE_ROM
+	bool
+	default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956..f3fcadc 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0..0fb9d5d 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d..9015ad4 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
 	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
-
 void enable_fixed_mtrr(void)
 {
 	msr_t msr;
@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	while(var_state.reg < MTRRS) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
+
+#if CONFIG_CACHE_ROM
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	if (boot_cpu() && (acpi_slp_type != 3)) {
+		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+			MTRR_TYPE_WRPROT, address_bits);
+	}
+#endif
+
 	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6c..016870d 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,6 +1,7 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#ifndef __ROMCC__
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
@@ -156,4 +157,7 @@ int start_cpu(struct device *cpu);
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */



From rminnich at gmail.com  Tue Mar  6 01:01:45 2012
From: rminnich at gmail.com (ron minnich)
Date: Mon, 5 Mar 2012 16:01:45 -0800
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <20120305095656.GD11392@xivo-clients.proformatique.com>
References: <4F5286F0.9050903@gmail.com>
	<20120305095656.GD11392@xivo-clients.proformatique.com>
Message-ID: <CAP6exYLVJMMM-9aW8k24j4m_y5me7sZZsPKKGuJgRCdDJm_Fxg@mail.gmail.com>

I'm seeing the ld problem on all my linux systems.

ron



From peter at stuge.se  Tue Mar  6 01:35:12 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 01:35:12 +0100
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <20120305095656.GD11392@xivo-clients.proformatique.com>
References: <4F5286F0.9050903@gmail.com>
	<20120305095656.GD11392@xivo-clients.proformatique.com>
Message-ID: <20120306003512.6888.qmail@stuge.se>

No? Rubinstein wrote:
> Did you try to "make clean" before re-making with the new gcc?

I recommend rm -rf build instead of make clean. I'm not sure if
make clean will in fact do a complete clean.

In any case we should run make clean or rm -rf build automatically
as part of make crossgcc.


//Peter



From peter at stuge.se  Tue Mar  6 01:39:49 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 01:39:49 +0100
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <20120306003512.6888.qmail@stuge.se>
References: <4F5286F0.9050903@gmail.com>
	<20120305095656.GD11392@xivo-clients.proformatique.com>
	<20120306003512.6888.qmail@stuge.se>
Message-ID: <20120306003949.7195.qmail@stuge.se>

Peter Stuge wrote:
> In any case we should run make clean or rm -rf build automatically
> as part of make crossgcc.

The clean-for-update target is a dependency for crossgcc, so the
build dir "should" have been cleaned out. I don't know if it is
complete? Help?


//Peter



From peter at stuge.se  Tue Mar  6 01:47:33 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 01:47:33 +0100
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <1330887701.6905.17.camel@dance-or-die3.athome.de>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
Message-ID: <20120306004733.7814.qmail@stuge.se>

Christian wrote:
> I currently working on a Igel Thin Client 3210.
> The board is very closer to bcom/winnetp680.
> CN700 northbridge
> VT8237R southbridge
> W83679HF SuperIO
> A try with this tree did not work.

What CPU do you have? Is CN700 usable exclusively with C7? What
generation C7 do you have? Does VIA have updated setup code for
your model CPU?


> I have compiled nearly all via boards to test the ROMs with qemu.
> And get always this message:
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000
> 
> EAX=00000004 EBX=00000000 ECX=00000000 EDX=00000001
> ESI=00000000 EDI=00000000 EBP=ffef7fe8 ESP=ffef7fb8
> EIP=0009ff66

So code at 9ff66 is trying to jump to a0000. This is all sorts of
wrong. Start by looking at what is going on at 9ff66. Obviously make
sure that your toolchain is working. I believe VIA startup has some
assembly. Verify that your disassembled binaries have 1:1 of the
source. All basic bringup.


> Is anybody working on a cn700 board for now.

No, I don't think anyone is.


> There are hints for Rev. 3566 code for the southbridge? Is this
> important.

A more precise reference to the code you have in mind would allow
more efficient collaboration.


Thanks.

//Peter



From peter at stuge.se  Tue Mar  6 03:59:43 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 03:59:43 +0100
Subject: [coreboot] New patch to review for coreboot: bdab48d
	Fix	address of IDT in real-mode entry
In-Reply-To: <I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+1@gerrit.coreboot.org>
References: <I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+0@gerrit.coreboot.org>
	<I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+1@gerrit.coreboot.org>
Message-ID: <20120306025943.17745.qmail@stuge.se>

Ky?sti M?lkki wrote:
> commit bdab48d3f13d117bd1100be616837e6d1dbb55fc
> Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
> Date:   Mon Mar 5 09:25:12 2012 +0200
> 
>     Fix address of IDT in real-mode entry

Was this tested not to cause regression?


//Peter



From peter at stuge.se  Tue Mar  6 04:04:06 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 04:04:06 +0100
Subject: [coreboot] Linux-ready Firmware Kit
In-Reply-To: <CAJgfmqVMis7u13v7RCVHC5zn_r2cMhEmXioKciBCA3d+rDTyHA@mail.gmail.com>
References: <CAJgfmqVMis7u13v7RCVHC5zn_r2cMhEmXioKciBCA3d+rDTyHA@mail.gmail.com>
Message-ID: <20120306030406.18127.qmail@stuge.se>

Fred . wrote:
> Intel provides a Linux-ready Firmware Kit

This is well-known in the community since many years.

If you want to contribute then please *USE* the software and either
just report results, or even better send fixes for any problems which
are found.

As you know, you can do limited testing completely using software.


//Peter



From oliver at schinagl.nl  Tue Mar  6 10:11:07 2012
From: oliver at schinagl.nl (Oliver Schinagl)
Date: Tue, 06 Mar 2012 10:11:07 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <20120306085546.14938.qmail@stuge.se>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se>
Message-ID: <4F55D4AB.20805@schinagl.nl>

Well My electrical engineering knowledge does not reach as far that I 
would know where to connect what :) I can read a schematic and solder 
based on that, but those pictures from the wiki that I linked, 
http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash  has a small 
PCB, with 2 flash chips on it, but I can't figure out where to connect what.

I do think it's a great idea, and maybe it would be an idea to draw the 
PCB in kicad/geda or the like, and actually have small batches made. I 
know dangerousprototypes.com has loads of small PCB's made for a few 
bux. Having a few on hand of these, and be able to send them to people 
would be great! Stuff one in an envelope and mail it out for the price 
of a stamp.

On 06-03-12 09:55, Peter Stuge wrote:
> Oliver Schinagl wrote:
>> Oh wow, that's some nice work there, unfortunatly I only have 1 bios
>> socket on my motherboard(s) and would use have to 'stack' the bios
>> chips.
> It works fine if you keep the switch wires very short.
>
> Or you can build a transistor-based or IC-based switch circuit which
> stays very close by, and then gets remote controlled by a switch on a
> long cable.
>
>
> //Peter



From peter at stuge.se  Tue Mar  6 10:22:28 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 10:22:28 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <4F55D4AB.20805@schinagl.nl>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
Message-ID: <20120306092229.17022.qmail@stuge.se>

Oliver Schinagl wrote:
> Well My electrical engineering knowledge does not reach as far that I would 
> know where to connect what :) I can read a schematic and solder based on 
> that, but those pictures from the wiki that I linked, 
> http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash  has a small PCB, 
> with 2 flash chips on it, but I can't figure out where to connect what.

That's the simple mod with some photos showing the principle at
http://stuge.se/m57sli/

A variation to the concept is to have a switch pull down the HOLD#
pin to GND. This should also work fine as long as the switch is not
toggled while the flash chip is being accessed.


> I do think it's a great idea, and maybe it would be an idea to draw the PCB 
> in kicad/geda or the like, and actually have small batches made. I know 
> dangerousprototypes.com has loads of small PCB's made for a few bux.

I guess whoever made the PCB can publish source and gerbers so that
others can order the same board if they want.


//Peter



From kyosti.malkki at gmail.com  Tue Mar  6 10:35:42 2012
From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=)
Date: Tue, 06 Mar 2012 11:35:42 +0200
Subject: [coreboot] New patch to review for coreboot: bdab48d Fix
 address of IDT in real-mode entry
In-Reply-To: <20120306025943.17745.qmail@stuge.se>
References: <I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+0@gerrit.coreboot.org>
	<I885a2888179700ba6e2b11d4f2d6a64ddea4c2dc+1@gerrit.coreboot.org>
	<20120306025943.17745.qmail@stuge.se>
Message-ID: <1331026542.19415.62.camel@obelix>

On Tue, 2012-03-06 at 03:59 +0100, Peter Stuge wrote:
> Ky?sti M?lkki wrote:
> > commit bdab48d3f13d117bd1100be616837e6d1dbb55fc
> > Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
> > Date:   Mon Mar 5 09:25:12 2012 +0200
> > 
> >     Fix address of IDT in real-mode entry
> 
> Was this tested not to cause regression?
> 

1. Tested as a fix to boot AP CPU on a hyper-threaded Intel
P4 models f29 and f49.

2. Tested to cause no regression to boot a non-hyper-threaded
Intel P4 CPU model f27 on the same platform as #1 testing.

3. Tested to cause no regression to boot AP CPUs on an Intel
P4 Xeon platform with dual socket604 and hyper-threaded model
f25 CPUs. The patch was not required for this platform to boot.

I have no possibility to test other platforms, so any feedback
with AMDs and VIAs is much appreciated.

For these tests, I considered it as a "fix" or "no regression"
if romstage executed with proper console output. Idwer Vollering
proceeded with the tests #1 and #2 for me on a platform with no
supported memory controller.

Test #3 is the A-Open board [1]. Gerrit version is outdated, I have
postponed updates for that until all the dependencies are merged.


Thanks,
KM

[1] http://review.coreboot.org/#/c/303/






From oliver at schinagl.nl  Tue Mar  6 10:41:34 2012
From: oliver at schinagl.nl (Oliver Schinagl)
Date: Tue, 06 Mar 2012 10:41:34 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <20120306092229.17022.qmail@stuge.se>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
	<20120306092229.17022.qmail@stuge.se>
Message-ID: <4F55DBCE.3090300@schinagl.nl>



On 06-03-12 10:22, Peter Stuge wrote:
> Oliver Schinagl wrote:
>> Well My electrical engineering knowledge does not reach as far that I would
>> know where to connect what :) I can read a schematic and solder based on
>> that, but those pictures from the wiki that I linked,
>> http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash  has a small PCB,
>> with 2 flash chips on it, but I can't figure out where to connect what.
> That's the simple mod with some photos showing the principle at
> http://stuge.se/m57sli/
>
> A variation to the concept is to have a switch pull down the HOLD#
> pin to GND. This should also work fine as long as the switch is not
> toggled while the flash chip is being accessed.
>
>
>> I do think it's a great idea, and maybe it would be an idea to draw the PCB
>> in kicad/geda or the like, and actually have small batches made. I know
>> dangerousprototypes.com has loads of small PCB's made for a few bux.
> I guess whoever made the PCB can publish source and gerbers so that
> others can order the same board if they want.
That would be probably the best idea to start with. I've been staring at 
the foto of the pvb for a while, and did notice as you said, only one 
pin is being diverted. Mrtadis is the one who uploaded the foto, his 
user page on the wiki however is quite empty, other then mentioning 
wanting to become a GSoC student.
>
>
> //Peter
>



From peter at stuge.se  Tue Mar  6 10:42:59 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 10:42:59 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <4F55DBCE.3090300@schinagl.nl>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
	<20120306092229.17022.qmail@stuge.se>
	<4F55DBCE.3090300@schinagl.nl>
Message-ID: <20120306094259.18684.qmail@stuge.se>

Oliver Schinagl wrote:
>> I guess whoever made the PCB can publish source and gerbers so that
>> others can order the same board if they want.
> That would be probably the best idea to start with. I've been staring at 
> the foto of the pvb for a while, and did notice as you said, only one pin 
> is being diverted.

So check which one and compare with the flash chip data sheet.


//Peter



From oliver at schinagl.nl  Tue Mar  6 15:59:35 2012
From: oliver at schinagl.nl (Oliver Schinagl)
Date: Tue, 06 Mar 2012 16:59:35 +0200
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <20120306094259.18684.qmail@stuge.se>
References: <4F460122.9000304@schinagl.nl>
	<20120223131646.4021.qmail@stuge.se> <4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
	<20120306092229.17022.qmail@stuge.se> <4F55DBCE.3090300@schinagl.nl>
	<20120306094259.18684.qmail@stuge.se>
Message-ID: <0776ab61c8dc620d2507f6d442fa1454@webmail.schinagl.nl>

  

Pin 1, 'chip select enable' is an inverted? pin. enables and
disables device operation. When chip select is high, the device is
de-selected and the serial data pins are at 'high impedance'.

 When
chip select is brought low, the device will be selected and instructions
can be written to and data read from the device.

 After power-up, Chip
Select must transition from high to low before a new instruction will be
accepted.

 So if I understand all this correctly, the chip can be
connected in parallel with the exception of the Chip Select Enable. A
simple switch to either connect it directly to the board/socket/other
end and toggle it to connect to ground (via 'some' resistor').

 I tried
to make a simple schematic in ascii, but failed horribly so i've
attached it to this message as monochrome BMP (only format that I could
quickly think of to be smallest in size). I don't know what value those
resistors need to be (and if the schematic can be even more simplified,
with a single resistor), but I belive this is the schematic used for the
dual-SPI flash 'module' 

This seems sensible to me, but my knowledge in
this field is very limited. 

On 06-03-12 10:42, Peter Stuge wrote: 

>
Oliver Schinagl wrote:
> 
>>> I guess whoever made the PCB can publish
source and gerbers so that
>>> others can order the same board if they
want.
>> 
>> That would be probably the best idea to start with. I've
been staring at 
>> the foto of the pvb for a while, and did notice as
you said, only one pin 
>> is being diverted.
> 
> So check which one
and compare with the flash chip data sheet.
> 
> //Peter

  
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From gerrit at coreboot.org  Tue Mar  6 16:42:27 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:27 +0100
Subject: [coreboot] New patch to review for filo: f1f9d46 makefile: don't
	evaluate empty input
References: <I0f482c4b680ca3eded4664c0a57e8525c068feaf+0@gerrit.coreboot.org>
Message-ID: <I0f482c4b680ca3eded4664c0a57e8525c068feaf+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/740

-gerrit

commit f1f9d467747176421a793ed0302730ee4b6a4bd2
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 5 11:23:24 2012 +0100

    makefile: don't evaluate empty input
    
    The output from util/xcompile/xcompile is redirected, so there is
    nothing left for make to $(eval)uate.
    
    Change-Id: I0f482c4b680ca3eded4664c0a57e8525c068feaf
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/Makefile b/Makefile
index debb816..d880f68 100644
--- a/Makefile
+++ b/Makefile
@@ -49,7 +49,7 @@ ifneq ($(Q),)
 endif
 endif
 
-$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile)))
+$(if $(wildcard .xcompile),,$(shell bash util/xcompile/xcompile > .xcompile))
 include .xcompile
 
 CROSS_PREFIX =



From gerrit at coreboot.org  Tue Mar  6 16:42:27 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:27 +0100
Subject: [coreboot] New patch to review for filo: df119be makefile: rebuild
	config.h when needed
References: <Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a+0@gerrit.coreboot.org>
Message-ID: <Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/741

-gerrit

commit df119bed3bad665af86209cb41111ccc8754f2f6
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:16:29 2012 +0100

    makefile: rebuild config.h when needed
    
    The dependencies for filo are quite awkward. Fix this by moving them
    where they belong to be, namely:
    * object files (not filo) depend on config.h
    * config.h (not filo) depends on .config to fix build problems when
      build/ gets removed or .config gets manually edited
    
    Change-Id: Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index d880f68..41486a9 100644
--- a/Makefile
+++ b/Makefile
@@ -129,7 +129,7 @@ libpayload: $(src)/$(LIB_CONFIG)
 	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(src)/build install
 endif
 
-$(obj)/filo: $(src)/.config $(OBJS)  libpayload
+$(obj)/filo: $(OBJS) libpayload
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
@@ -141,7 +141,11 @@ $(TARGET): $(obj)/filo libpayload
 
 include util/kconfig/Makefile
 
-$(obj)/%.o: $(src)/%.c libpayload
+$(KCONFIG_AUTOHEADER): $(src)/.config
+	$(MAKE) silentoldconfig
+
+$(OBJS): $(KCONFIG_AUTOHEADER) libpayload
+$(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
 



From gerrit at coreboot.org  Tue Mar  6 16:42:27 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:27 +0100
Subject: [coreboot] New patch to review for filo: ba947af makefile: create
	directories on demand
References: <Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079+0@gerrit.coreboot.org>
Message-ID: <Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/742

-gerrit

commit ba947af8efc8d7d5b403150ed16a8c61cdd9750d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:31:38 2012 +0100

    makefile: create directories on demand
    
    Use makefile dependencies to created needed directories instead of
    trying to recreate them on each make invocation.
    
    Change-Id: Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/Makefile b/Makefile
index 41486a9..6603612 100644
--- a/Makefile
+++ b/Makefile
@@ -161,16 +161,16 @@ $(obj)/version.h: FORCE
 	echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
 	echo '#define BUILD_INFO "$(BUILD_INFO)"' >> $@
 
-prepare:
-	mkdir -p $(obj)/util/kconfig/lxdialog
-	mkdir -p $(obj)/i386 $(obj)/fs $(obj)/drivers/flash
-	mkdir -p $(obj)/main/grub
+$(obj)/%/:
+	mkdir -p $@
+
+prepare: $(sort $(dir $(OBJS))) $(obj)/util/kconfig/lxdialog/
 
 clean:
-	rm -rf $(obj)/i386 $(obj)/fs $(obj)/drivers $(obj)/main $(obj)/util
+	rm -rf $(sort $(dir $(OBJS))) $(obj)/util
 
 distclean: clean
-	rm -rf build
+	rm -rf $(obj)
 	rm -f .config lib.config .config.old .xcompile ..config.tmp .kconfig.d .tmpconfig*
 
 FORCE:



From gerrit at coreboot.org  Tue Mar  6 16:42:27 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:27 +0100
Subject: [coreboot] New patch to review for filo: 27ba025 makefile: create
	filo.map in separate step
References: <If010b4ce269a47a99de06db16e0290c3fd90b559+0@gerrit.coreboot.org>
Message-ID: <If010b4ce269a47a99de06db16e0290c3fd90b559+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/743

-gerrit

commit 27ba025fa013ec555e28983942a5b1d4e006864a
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:42:18 2012 +0100

    makefile: create filo.map in separate step
    
    Instead of copying files around and creating files make is not aware of,
    use a dedicated target and rule to create filo.map. Also skip piping the
    result through sort as nm as an option to sort the symbols itself.
    
    Also drop the bogus dependency to libpayload as filo.elf is only the
    striped version of filo and needs no further linking.
    
    Change-Id: If010b4ce269a47a99de06db16e0290c3fd90b559
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 6603612..3461614 100644
--- a/Makefile
+++ b/Makefile
@@ -133,11 +133,9 @@ $(obj)/filo: $(OBJS) libpayload
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
-$(TARGET): $(obj)/filo libpayload
-	cp $(obj)/filo $@
-	$(NM) $(obj)/filo | sort > $(obj)/filo.map
+$(TARGET): $(obj)/filo $(obj)/filo.map
 	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
-	$(STRIP) -s $@
+	$(STRIP) -s $< -o $@
 
 include util/kconfig/Makefile
 
@@ -153,6 +151,10 @@ $(obj)/%.S.o: $(src)/%.S
 	printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(AS) $(ASFLAGS) -o $@ $<
 
+$(obj)/%.map: $(obj)/%
+	printf "  SYMS    $(subst $(shell pwd)/,,$(@))\n"
+	$(NM) -n $< > $@
+
 endif
 
 $(obj)/version.h: FORCE



From gerrit at coreboot.org  Tue Mar  6 16:42:27 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:27 +0100
Subject: [coreboot] New patch to review for filo: 2bc5424 makefile: avoid
	unnecessary rebuilds
References: <Ifa42362ba1d8c88c9996d645314cfdbdf2994759+0@gerrit.coreboot.org>
Message-ID: <Ifa42362ba1d8c88c9996d645314cfdbdf2994759+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/744

-gerrit

commit 2bc5424a1d455622e8168e4c30873f9fff1a15ac
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:14:47 2012 +0100

    makefile: avoid unnecessary rebuilds
    
    The make target libpayload is a phony target which makes filo and all
    the object files get rebuild on every make invokation. Avoid this by
    lifting the dependencies and rebuild, i.e. relink filo only when
    libpayload has changed.
    
    Also, when building libpayload as a prerequisite, use $(obj) as DESTDIR,
    as the user might want to use a different build directory then $(src)/build.
    
    Change-Id: Ifa42362ba1d8c88c9996d645314cfdbdf2994759
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 3461614..3b4a468 100644
--- a/Makefile
+++ b/Makefile
@@ -118,18 +118,19 @@ all: prepare $(obj)/version.h $(TARGET)
 HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD))
 ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
 libpayload:
-	@printf "Found Libpayload $(LIBPAYLOAD).\n"
+	@printf "Found libpayload as $(LIBPAYLOAD)\n"
 else
-libpayload: $(src)/$(LIB_CONFIG)
-	printf "building libpayload.\n"
+libpayload: $(LIBPAYLOAD)
+$(LIBPAYLOAD): $(src)/$(LIB_CONFIG)
+	@printf "Building libpayload...\n"
 	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build distclean
 	cp lib.config $(LIBCONFIG_PATH)/.config
 	mkdir -p $(LIBCONFIG_PATH)/build
 	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build oldconfig
-	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(src)/build install
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(obj) install
 endif
 
-$(obj)/filo: $(OBJS) libpayload
+$(obj)/filo: $(OBJS) $(LIBPAYLOAD)
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
@@ -142,7 +143,7 @@ include util/kconfig/Makefile
 $(KCONFIG_AUTOHEADER): $(src)/.config
 	$(MAKE) silentoldconfig
 
-$(OBJS): $(KCONFIG_AUTOHEADER) libpayload
+$(OBJS): $(KCONFIG_AUTOHEADER) | libpayload
 $(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
@@ -177,5 +178,4 @@ distclean: clean
 
 FORCE:
 
-.PHONY: $(PHONY) prepare clean distclean FORCE
-
+.PHONY: $(PHONY) prepare clean distclean libpayload FORCE



From gerrit at coreboot.org  Tue Mar  6 16:42:28 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:28 +0100
Subject: [coreboot] New patch to review for filo: 0c3a13b makefile: recreate
	version.h only when needed
References: <I27a057be25902233ac0751db8061e9ad4cd50642+0@gerrit.coreboot.org>
Message-ID: <I27a057be25902233ac0751db8061e9ad4cd50642+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/745

-gerrit

commit 0c3a13b773ee21af4c1380c01bacc2d9d00f6784
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:26:48 2012 +0100

    makefile: recreate version.h only when needed
    
    Don't recreate version.h on each make invokation but only when needed, i.e.
    when the make variables have changed. Also make version.h a prerequisite for
    the object files to rebuild them when the version information changes.
    
    Change-Id: I27a057be25902233ac0751db8061e9ad4cd50642
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 3b4a468..46a265f 100644
--- a/Makefile
+++ b/Makefile
@@ -112,8 +112,8 @@ TARGET  = $(obj)/filo.elf
 
 HAVE_LIBCONFIG := $(wildcard $(LIBCONFIG_PATH))
 
-all: prepare $(obj)/version.h $(TARGET)
 
+all: prepare $(TARGET)
 
 HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD))
 ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
@@ -143,7 +143,7 @@ include util/kconfig/Makefile
 $(KCONFIG_AUTOHEADER): $(src)/.config
 	$(MAKE) silentoldconfig
 
-$(OBJS): $(KCONFIG_AUTOHEADER) | libpayload
+$(OBJS): $(KCONFIG_AUTOHEADER) $(obj)/version.h | libpayload
 $(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
@@ -158,7 +158,8 @@ $(obj)/%.map: $(obj)/%
 
 endif
 
-$(obj)/version.h: FORCE
+$(obj)/version.h: Makefile
+	printf "  GEN     $(subst $(shell pwd)/,,$(@))\n"
 	echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
 	echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
 	echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
@@ -171,6 +172,7 @@ prepare: $(sort $(dir $(OBJS))) $(obj)/util/kconfig/lxdialog/
 
 clean:
 	rm -rf $(sort $(dir $(OBJS))) $(obj)/util
+	rm -rf $(obj)/version.h
 
 distclean: clean
 	rm -rf $(obj)



From gerrit at coreboot.org  Tue Mar  6 16:42:28 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:28 +0100
Subject: [coreboot] New patch to review for filo: 447421d makefile: build
	system cleanup
References: <I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b+0@gerrit.coreboot.org>
Message-ID: <I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/746

-gerrit

commit 447421d98e73791e8483a263e4a293700847a9d0
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:37:05 2012 +0100

    makefile: build system cleanup
    
    This patch cleans up the include hierarchies for the Makefile system to
    decrease the knowledge of the main Makefile about every subdirectory.
    This allows us to add new drivers without the need to patch the main
    Makefile but, instead, just add a line to the appropriate Makeflie.inc.
    
    Also all standard make variables are cleanup up (e.g. CFLAGS,
    CPPFLAGS,..). This, in turn, allows modifying them as needed in the
    included Makefile.inc to add flags or even library dependencies.
    
    It's no Linux Kbuild yet, but we're close ;)
    
    Change-Id: I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile                   |   63 +++++++++++++++++++++-----------------------
 drivers/Makefile.inc       |    5 ++-
 drivers/flash/Makefile.inc |    1 -
 i386/Makefile.inc          |    3 +-
 main/Makefile.inc          |    5 ++-
 main/grub/Makefile.inc     |    2 -
 6 files changed, 38 insertions(+), 41 deletions(-)

diff --git a/Makefile b/Makefile
index 46a265f..20b21bf 100644
--- a/Makefile
+++ b/Makefile
@@ -49,17 +49,27 @@ ifneq ($(Q),)
 endif
 endif
 
+try-run = $(shell set -e;		\
+	TMP=".$$$$.tmp";		\
+	if ($(1)) > /dev/null 2>&1;	\
+	then echo "$(2)";		\
+	else echo "$(3)";		\
+	fi;				\
+	rm -rf "$$TMP")
+
+cc-option = $(call try-run,$(CC) $(1) -S -xc /dev/null -o "$$TMP",$(1),$(2))
+
 $(if $(wildcard .xcompile),,$(shell bash util/xcompile/xcompile > .xcompile))
 include .xcompile
 
-CROSS_PREFIX =
+CROSS_PREFIX ?=
 CC ?= $(CROSS_PREFIX)gcc -m32
 AS ?= $(CROSS_PREFIX)as --32
 LD ?= $(CROSS_PREFIX)ld -belf32-i386
-STRIP ?= $(CROSS_PREFIX)strip
 NM ?= $(CROSS_PREFIX)nm
-HOSTCC = gcc
-HOSTCXX = g++
+STRIP ?= $(CROSS_PREFIX)strip
+HOSTCC ?= gcc
+HOSTCXX ?= g++
 HOSTCFLAGS := -I$(srck) -I$(objk) -pipe
 HOSTCXXFLAGS := -I$(srck) -I$(objk) -pipe
 
@@ -72,45 +82,32 @@ else
 
 include $(src)/.config
 
-ARCHDIR-$(CONFIG_TARGET_I386) := i386
-
-PLATFORM-y += $(ARCHDIR-y)/Makefile.inc
-TARGETS-y :=
-
-BUILD-y := main/Makefile.inc main/grub/Makefile.inc fs/Makefile.inc 
-BUILD-y += drivers/Makefile.inc
-BUILD-y += drivers/flash/Makefile.inc
-
-include $(PLATFORM-y) $(BUILD-y)
-
 LIBPAYLOAD_PREFIX ?= $(obj)/libpayload
 LIBPAYLOAD = $(LIBPAYLOAD_PREFIX)/lib/libpayload.a
 INCPAYLOAD = $(LIBPAYLOAD_PREFIX)/include
 LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+GCCINCDIR = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
 
-OBJS     := $(patsubst %,$(obj)/%,$(TARGETS-y))
-INCLUDES := -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y) -Iinclude -I$(ARCHDIR-y)/include -Ibuild
-INCLUDES += -I$(GCCINCDIR)
+ARCHDIR-$(CONFIG_TARGET_I386) := i386
 
-try-run= $(shell set -e; \
-TMP=".$$$$.tmp"; \
-if ($(1)) > /dev/null 2>&1; \
-then echo "$(2)"; \
-else echo "$(3)"; \
-fi; rm -rf "$$TMP")
+CPPFLAGS := -nostdinc -imacros $(obj)/config.h
+CPPFLAGS += -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y)
+CPPFLAGS += -I$(ARCHDIR-y)/include -Iinclude -I$(obj)
+CPPFLAGS += -I$(GCCINCDIR)
 
-cc-option= $(call try-run,\
-$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
+CFLAGS := -Wall -Wshadow -Os -pipe
+CFLAGS += -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing
+CFLAGS += $(call cc-option, -fno-stack-protector,)
 
-STACKPROTECT += $(call cc-option, -fno-stack-protector,)
+LIBS := $(LIBPAYLOAD) $(LIBGCC)
 
-GCCINCDIR = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
-CPPFLAGS = -nostdinc -imacros $(obj)/config.h -Iinclude -I$(GCCINCDIR) -MD
-CFLAGS += $(STACKPROTECT) $(INCLUDES) -Wall -Os -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing -Wshadow -pipe
+SUBDIRS-y += main/ fs/ drivers/
+SUBDIRS-y += $(ARCHDIR-y)/
 
-TARGET  = $(obj)/filo.elf
+$(foreach subdir,$(SUBDIRS-y),$(eval include $(subdir)/Makefile.inc))
 
-HAVE_LIBCONFIG := $(wildcard $(LIBCONFIG_PATH))
+TARGET := $(obj)/filo.elf
+OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y))
 
 
 all: prepare $(TARGET)
@@ -132,7 +129,7 @@ endif
 
 $(obj)/filo: $(OBJS) $(LIBPAYLOAD)
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
+	$(LD) -N -T $(ARCHDIR-y)/ldscript $(OBJS) --start-group $(LIBS) --end-group -o $@
 
 $(TARGET): $(obj)/filo $(obj)/filo.map
 	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
diff --git a/drivers/Makefile.inc b/drivers/Makefile.inc
index 8f814e0..f93c287 100644
--- a/drivers/Makefile.inc
+++ b/drivers/Makefile.inc
@@ -16,9 +16,10 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
+include drivers/flash/Makefile.inc
+
 TARGETS-$(CONFIG_IDE_DISK) += drivers/ide.o
 TARGETS-$(CONFIG_IDE_NEW_DISK) += drivers/ide_new.o
 TARGETS-$(CONFIG_VIA_SOUND) += drivers/via-sound.o
 TARGETS-$(CONFIG_USB_DISK) += drivers/usb.o
-TARGETS-y += drivers/intel.o
-
+TARGETS-$(CONFIG_TARGET_I386) += drivers/intel.o
diff --git a/drivers/flash/Makefile.inc b/drivers/flash/Makefile.inc
index a862773..48bf1a1 100644
--- a/drivers/flash/Makefile.inc
+++ b/drivers/flash/Makefile.inc
@@ -17,4 +17,3 @@
 #
 
 TARGETS-$(CONFIG_FLASH_DISK) += drivers/flash/lxflash.o
-
diff --git a/i386/Makefile.inc b/i386/Makefile.inc
index 8f1a305..ce3e5c8 100644
--- a/i386/Makefile.inc
+++ b/i386/Makefile.inc
@@ -16,7 +16,8 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-TARGETS-y += i386/context.o i386/switch.S.o i386/segment.o i386/timer.o i386/sys_info.o
+TARGETS-$(CONFIG_TARGET_I386) += i386/context.o i386/switch.S.o i386/segment.o
+TARGETS-$(CONFIG_TARGET_I386) += i386/timer.o i386/sys_info.o
 TARGETS-$(CONFIG_LINUX_LOADER) += i386/linux_load.o
 TARGETS-$(CONFIG_WINCE_LOADER) += i386/wince_load.o
 TARGETS-$(CONFIG_ARTEC_BOOT) += i386/artecboot.o
diff --git a/main/Makefile.inc b/main/Makefile.inc
index e2fab04..fc7c851 100644
--- a/main/Makefile.inc
+++ b/main/Makefile.inc
@@ -16,8 +16,9 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
+include main/grub/Makefile.inc
+
 TARGETS-y += main/filo.o main/strtox.o
 TARGETS-y += main/elfload.o main/ipchecksum.o 
 TARGETS-$(CONFIG_SUPPORT_SOUND) += main/sound.o
-
+TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
diff --git a/main/grub/Makefile.inc b/main/grub/Makefile.inc
index b79f08f..00273f3 100644
--- a/main/grub/Makefile.inc
+++ b/main/grub/Makefile.inc
@@ -16,9 +16,7 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/grub.o main/grub/builtins.o
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/cmdline.o main/grub/char_io.o
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/completions.o
 TARGETS-$(CONFIG_USE_MD5_PASSWORDS) += main/grub/md5.o
-



From gerrit at coreboot.org  Tue Mar  6 16:42:28 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Tue, 6 Mar 2012 16:42:28 +0100
Subject: [coreboot] New patch to review for filo: fd0f87b Fix some compiler
	warnings
References: <I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299+0@gerrit.coreboot.org>
Message-ID: <I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299+1@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/747

-gerrit

commit fd0f87b5695eeb3ec120dcdbb9409473582c4949
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 16:10:27 2012 +0100

    Fix some compiler warnings
    
    The makefile cleanup brought up quite a few compiler warnings about
    unused functions and/or variables, undefined behaviour, missing return
    values and type mismatches. Fix those.
    
    Change-Id: I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 drivers/flash/lxflash.c |   14 ++------------
 fs/blockdev.c           |   14 +++++++-------
 fs/fsys_cramfs.c        |    6 +++---
 fs/fsys_ext2fs.c        |    5 ++---
 fs/fsys_xfs.c           |    2 +-
 fs/mini_inflate.c       |    5 ++++-
 i386/wince_load.c       |    2 +-
 include/fs.h            |    2 +-
 main/grub/builtins.c    |    6 +++---
 main/grub/completions.c |    2 +-
 main/grub/grub.c        |    2 ++
 11 files changed, 27 insertions(+), 33 deletions(-)

diff --git a/drivers/flash/lxflash.c b/drivers/flash/lxflash.c
index ba76741..df18c8d 100644
--- a/drivers/flash/lxflash.c
+++ b/drivers/flash/lxflash.c
@@ -345,16 +345,6 @@ static __inline void NAND_writeByte(u8 b)
 	outb(b, g_baseAddr + IO_NAND_DATA);
 }
 
-static void NAND_writeData(u8 *pData, int nSize)
-{
-	int i;
-	if(nSize > 528) return;	// oversized buffer?
-
-	// write byte by byte, pedestrian way
-	for(i=0; i<nSize; i++)
-		NAND_writeByte(pData[i]);
-}
-
 ////////////////////////////////////////////////////////////////////////////////
 //
 // NAND_getStatus()
@@ -521,7 +511,7 @@ __inline int IsECCWritten(u8 *pECC)
 ////////////////////////////////////////////////////////////////////////////////
 // 
 
-int NAND_close(void)
+void NAND_close(void)
 {
 	if (g_chipID >= 0)
 		wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, g_orig_flsh);
@@ -650,7 +640,7 @@ int NAND_readPage(u32 pageAddr, u8 *pPageBuff)
 	// sanity check
 	if (pageAddr < (g_flashInfo.numBlocks * g_flashInfo.pagesPerBlock))
 	{
-		u8 bData = 0, bBadBlock = 0, bReserved = 0;
+		u8 bBadBlock = 0, bReserved = 0;
 
 		u8 addr1 = (u8)(pageAddr & 0xff);
 		u8 addr2 = (u8)((pageAddr >> 8) & 0xff);
diff --git a/fs/blockdev.c b/fs/blockdev.c
index 21d2c29..e1e9d57 100644
--- a/fs/blockdev.c
+++ b/fs/blockdev.c
@@ -385,8 +385,10 @@ static void *read_sector(unsigned long sector)
 			int count = (NUM_CACHE-hash>8)?8:(NUM_CACHE-hash);
 			int ret;
 			ret = ide_read_blocks(dev_drive, sector, count, buf);
-			if (ret == 2)
-				goto nomedium;
+			if (ret == 2) {
+				printf("No disk in drive.\n");
+				goto err_out;
+			}
 			if (ret != 0)
 				goto readerr;
 			while (--count>0) {
@@ -426,11 +428,9 @@ static void *read_sector(unsigned long sector)
       readerr:
 	printf("Disk read error dev=%d drive=%d sector=%lu\n",
 	       dev_type, dev_drive, sector);
-	flush_cache();
-	dev_name[0] = '\0';	/* force re-open the device next time */
-	return 0;
-      nomedium:
-	printf("No disk in drive.\n");
+#ifdef CONFIG_IDE_NEW_DISK
+      err_out:
+#endif
 	flush_cache();
 	dev_name[0] = '\0';	/* force re-open the device next time */
 	return 0;
diff --git a/fs/fsys_cramfs.c b/fs/fsys_cramfs.c
index c5a9247..d7cb19b 100644
--- a/fs/fsys_cramfs.c
+++ b/fs/fsys_cramfs.c
@@ -103,8 +103,8 @@ struct cramfs_buf {
 	struct cramfs_inode inode;
 	char name[NAMELEN_MAX + 1];
 	u32 block_ptrs[CRAMFS_MAX_BLOCKS];
-	char data[CRAMFS_BLOCK * 2];
-	char temp[CRAMFS_BLOCK];
+	unsigned char data[CRAMFS_BLOCK * 2];
+	unsigned char temp[CRAMFS_BLOCK];
 	/* menu.lst is read 1 byte at a time, try to aleviate *
 	 * the performance problem */
 	long cached_block;		/* the uncompressed block in cramfs_buf->data */
@@ -246,7 +246,7 @@ cramfs_read (char *buf, int len)
 				memcpy(buf, cramfs_buf->temp + (filepos % CRAMFS_BLOCK), size);		
 		} else  {
 			/* just another full block read */
-			size = decompress_block(buf, cramfs_buf->data + 2, memcpy);
+			size = decompress_block((unsigned char *)buf, cramfs_buf->data + 2, memcpy);
 		}
 		if (size < 0) {
 			debug_cramfs("error in decomp (error %d)\n", size);
diff --git a/fs/fsys_ext2fs.c b/fs/fsys_ext2fs.c
index 30a78ec..96e2e68 100644
--- a/fs/fsys_ext2fs.c
+++ b/fs/fsys_ext2fs.c
@@ -631,10 +631,9 @@ static int
 ext4fs_block_map (int logical_block)
 {
   struct ext4_extent_header *eh;
-  struct ext4_extent *ex, *extent;
-  struct ext4_extent_idx *ei, *index;
+  struct ext4_extent_idx *ei;
+  struct ext4_extent *ex;
   int depth;
-  int i;
 
 #ifdef E2DEBUG
   unsigned char *i;
diff --git a/fs/fsys_xfs.c b/fs/fsys_xfs.c
index 4011479..c71af98 100644
--- a/fs/fsys_xfs.c
+++ b/fs/fsys_xfs.c
@@ -365,7 +365,7 @@ next_dentry (xfs_ino_t *ino)
 		default:
 			namelen = sfe->namelen;
 			*ino = sf_ino ((char *)sfe, namelen);
-			name = sfe->name;
+			name = (char *) sfe->name;
 			sfe = (xfs_dir2_sf_entry_t *)
 				  ((char *)sfe + namelen + 11 - xfs.i8param);
 		}
diff --git a/fs/mini_inflate.c b/fs/mini_inflate.c
index 17e3390..eae371d 100644
--- a/fs/mini_inflate.c
+++ b/fs/mini_inflate.c
@@ -185,7 +185,10 @@ static void decompress_huffman(struct bitstream *stream, unsigned char *dest)
 				dist += (symbol % 2) << ((symbol - 2) >> 1);
 			}
 			stream->decoded += length;
-			for (i = 0; i < length; i++) *(dest++) = dest[-dist];
+			for (i = 0; i < length; i++) {
+				*dest = dest[-dist];
+				dest++;
+			}
 		}
 	} while (symbol != 256); /* 256 is the end of the data block */
 }
diff --git a/i386/wince_load.c b/i386/wince_load.c
index f3e5475..993815f 100644
--- a/i386/wince_load.c
+++ b/i386/wince_load.c
@@ -240,7 +240,7 @@ void wince_init_bootarg(u32 entryPoint)
 	g_pBootArgs->dwEdbgBaseAddr = 0;
 
 	// set the KITL device name to something adequate
-	strcpy(g_pBootArgs->szDeviceNameRoot, "FILO");
+	strcpy((char *) g_pBootArgs->szDeviceNameRoot, "FILO");
 
 	g_pBootArgs->dwSig = BOOTARG_SIGNATURE;
 	g_pBootArgs->dwLen = sizeof(BOOT_ARGS);
diff --git a/include/fs.h b/include/fs.h
index 1bd8ec7..3138ab5 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -46,7 +46,7 @@ int usb_read(const int drive, const sector_t sector, const int size, void *buffe
 #ifdef CONFIG_FLASH_DISK
 int flash_probe(int drive);
 int flash_read(int drive, sector_t sector, void *buffer);
-int NAND_close(void);
+void NAND_close(void);
 #endif
 
 #define DISK_IDE 1
diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index e2f4612..3451071 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -379,9 +379,9 @@ static int dumpmem_func(char *arg, int flags)
 	}
 
 	// FIXME
-	if (!safe_parse_maxint(&string_argv[1], &mem_base))
+	if (!safe_parse_maxint(&string_argv[1], (int *)&mem_base))
 		return 1;
-	if (!safe_parse_maxint(&string_argv[2], &mem_len))
+	if (!safe_parse_maxint(&string_argv[2], (int *)&mem_len))
 		return 1;
 
 	grub_printf("Dumping memory at 0x%08x (0x%x bytes)\n",
@@ -668,7 +668,7 @@ void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int appe
 	char drivername[16];
 	int disk, part;
 	unsigned long addr;
-	int i, len;
+	int i;
 
 	memset(devicename, 0, 16);
 	memset(drivername, 0, 16);
diff --git a/main/grub/completions.c b/main/grub/completions.c
index a3aeba2..abfe1d9 100644
--- a/main/grub/completions.c
+++ b/main/grub/completions.c
@@ -120,7 +120,7 @@ int print_completions(int is_filename, int is_completion)
 		if (*buf == '(' && (incomplete || ! *ptr)) {
 			if (!part_choice) {
 				/* disk completions */
-				int disk_no, i, j;
+				int i, j;
 
 				if (!is_completion)
 					grub_printf (" Possible disks are: ");
diff --git a/main/grub/grub.c b/main/grub/grub.c
index b4bee04..b629435 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -201,6 +201,7 @@ old:
 
 }
 
+#ifdef CONFIG_NON_INTERACTIVE
 static void reboot(void) {
 	for (;;) {
 		grub_printf("Press any key to reboot.\n");
@@ -210,6 +211,7 @@ static void reboot(void) {
 		}
 	}
 }
+#endif
 
 /* Define if there is user specified preset menu string */
 /* #undef PRESET_MENU_STRING */



From peter at stuge.se  Tue Mar  6 19:33:39 2012
From: peter at stuge.se (Peter Stuge)
Date: Tue, 6 Mar 2012 19:33:39 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <0776ab61c8dc620d2507f6d442fa1454@webmail.schinagl.nl>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
	<20120306092229.17022.qmail@stuge.se>
	<4F55DBCE.3090300@schinagl.nl>
	<20120306094259.18684.qmail@stuge.se>
	<0776ab61c8dc620d2507f6d442fa1454@webmail.schinagl.nl>
Message-ID: <20120306183339.713.qmail@stuge.se>

Oliver Schinagl wrote:
> Pin 1, 'chip select enable' is an inverted? pin. enables and
> disables device operation. When chip select is high, the device is
> de-selected and the serial data pins are at 'high impedance'.

Correct.


> So if I understand all this correctly, the chip can be
> connected in parallel with the exception of the Chip Select Enable.
> A simple switch to either connect it directly to the
> board/socket/other end and toggle it to connect to ground (via
> 'some' resistor').

Right. This is what you can see demonstrated in the photos linked to
at the bottom of http://stuge.se/m57sli/ i.e.:

http://stuge.se/m57sli/overview.jpg
http://stuge.se/m57sli/U5.jpg
http://stuge.se/m57sli/U9.jpg

These photos are not from a PC mainboard but the principle hopefully
shows. The connection you describe is indeed how GIGABYTE boards
implement Dual BIOS. What is not shown in my photos are the
resistors, which are mounted onto the GIGABYTE board on pads for that
very purpose.


> I tried to make a simple schematic in ascii, but failed horribly so i've
> attached it to this message as monochrome BMP (only format that I could
> quickly think of to be smallest in size).

Hint: png


> I don't know what value those resistors need to be (and if the
> schematic can be even more simplified, with a single resistor), but
> I belive this is the schematic used for the dual-SPI flash 'module' 

Not quite, the resistors need to be pull-up and not pull-down. See
e.g. http://stuge.se/flash_switch.png which shows the principle with
resistors, but connects the switch common to GND, instead of to the
mainboard as must be done.


> This seems sensible to me, but my knowledge in
> this field is very limited. 

You're already learning more. Your schematic is correct, but
resistors need to pull up to 3.3V and not down to GND. The values
are, as I wrote earlier, not really critical, just don't go too
much under 1k or you will potentially waste some current.

Also make sure that your switch is the break-before-make type.


//Peter



From gerrit at coreboot.org  Tue Mar  6 21:11:25 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Tue, 6 Mar 2012 21:11:25 +0100
Subject: [coreboot] New patch to review for coreboot: 3adfa8c xcompile: Tell
	gcc to use pentium-class instructions
References: <Ief4a6faba236f215e7dc23872cd7e4ee405a33d2+0@gerrit.coreboot.org>
Message-ID: <Ief4a6faba236f215e7dc23872cd7e4ee405a33d2+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/748

-gerrit

commit 3adfa8caa49ad8f072767076725fceb4b4dfa969
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Mar 6 21:13:47 2012 +0100

    xcompile: Tell gcc to use pentium-class instructions
    
    Instead of hardcoding "no-sse" (which disables various intrinsics)
    xcompile now tests for -march=pentium, which tells gcc to restrict
    itself to pentium class instructions (but allows the developer to
    override it by using intrinsics and asm).
    
    Change-Id: Ief4a6faba236f215e7dc23872cd7e4ee405a33d2
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/xcompile/xcompile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index f5d43d0..3c82eea 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -87,7 +87,7 @@ testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
 # Use bfd linker instead of gold if available:
 testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
 # Prevent SSE instructions sneaking in:
-testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse "
+testcc "$CC" "$CFLAGS-march=pentium " && CFLAGS="$CFLAGS-march=pentium "
 
 if which gcc 2>/dev/null >/dev/null; then
 	HOSTCC=gcc



From gerrit at coreboot.org  Tue Mar  6 22:32:32 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Tue, 6 Mar 2012 22:32:32 +0100
Subject: [coreboot] Patch set updated for coreboot: 73392a7 xcompile: Tell
	gcc to use i486-class instructions
References: <Ief4a6faba236f215e7dc23872cd7e4ee405a33d2+0@gerrit.coreboot.org>
Message-ID: <Ief4a6faba236f215e7dc23872cd7e4ee405a33d2+2@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/748

-gerrit

commit 73392a7c2993a6c4dcf47cb2ae8118e89ef3b5d1
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Tue Mar 6 21:13:47 2012 +0100

    xcompile: Tell gcc to use i486-class instructions
    
    Instead of hardcoding "no-sse" (which disables various intrinsics)
    xcompile now tests for -march=i486, which tells gcc to restrict
    itself to i486 class instructions (but allows the developer to
    override it by using intrinsics and asm).
    
    Change-Id: Ief4a6faba236f215e7dc23872cd7e4ee405a33d2
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/xcompile/xcompile |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index f5d43d0..d4eaab0 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -87,7 +87,7 @@ testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
 # Use bfd linker instead of gold if available:
 testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
 # Prevent SSE instructions sneaking in:
-testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse "
+testcc "$CC" "$CFLAGS-march=i486 " && CFLAGS="$CFLAGS-march=i486 "
 
 if which gcc 2>/dev/null >/dev/null; then
 	HOSTCC=gcc



From gerrit at coreboot.org  Tue Mar  6 22:45:25 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Tue, 6 Mar 2012 22:45:25 +0100
Subject: [coreboot] Patch merged into coreboot/master: 7c48e07 Revert "Use
	-mno-sse to prevent overzealous gcc optimizations"
References: <I7c48e07a261eafda2119354d282bd05eac5a14b6+0@gerrit.coreboot.org>
Message-ID: <E1S52CD-0004Ro-U7@ra.coresystems.de>

the following patch was just integrated into master:
commit 7c48e07a261eafda2119354d282bd05eac5a14b6
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Sat Mar 3 10:46:26 2012 +0100

    Revert "Use -mno-sse to prevent overzealous gcc optimizations"
    
    AGESA uses SSE intrinsics :-(
    
    This reverts commit 05f4b03fb64999ba373fe61256f358e5371bf8ae

Build-Tested: build bot (Jenkins) at Tue Mar  6 22:24:46 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue Mar  6 21:50:48 2012, giving +2
See http://review.coreboot.org/706 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 00:38:03 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 00:38:03 +0100
Subject: [coreboot] New patch to review for coreboot: 1e798a5 Fix coreboot
	makefiles not to produce half baked output.
References: <I7c17f033ee5937eb712b1a594122430cee5c9146+0@gerrit.coreboot.org>
Message-ID: <I7c17f033ee5937eb712b1a594122430cee5c9146+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750

-gerrit

commit 1e798a5792e9838f282128561ef6824785d831a7
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Nov 5 02:07:01 2011 +0000

    Fix coreboot makefiles not to produce half baked output.
    
    It looks like the cbfstool utility generates the output file even when
    it fails to generate it properly. This causes make, if started second
    time in a row, after cbfstool failure, to continue beyond the point of
    failure (as the corrupted output file is present in the output tree,
    the second make invocation presumes that it is valid, as it is newer
    than the dependencies).
    
    The output file should be created only when successful, in an atomic
    operation. There could be other places in the make system which
    require a similar fix, this needs to be investigated further.
    
    Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/Makefile.inc |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index aeb4875..b2b9143 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2)))
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	$(foreach file,$(cbfs-files), \
-		$(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
+	$(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \
+	$(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \
+	$(call extract_nth,4,$(file)) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL)
-	rm -f $@
-	$(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
-	$(prebuild-files)
+	$(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
+	$(prebuild-files) true
+	mv $@.tmp $@
 else
 .PHONY: $(obj)/coreboot.pre1
 $(obj)/coreboot.pre1: $(CBFSTOOL)
@@ -269,10 +271,10 @@ endif
 
 $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
+	cp $(obj)/coreboot.pre1 $@.tmp
+	$(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \
 	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	mv $@.tmp $@
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################



From gerrit at coreboot.org  Wed Mar  7 00:37:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 00:37:48 +0100
Subject: [coreboot] New patch to review for coreboot: e1a7cc5 Add more
	timestamps in coreboot.
References: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+0@gerrit.coreboot.org>
Message-ID: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749

-gerrit

commit e1a7cc59d1dd5642d4fa83d5cbe4fe18194310d3
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Nov 4 12:31:58 2011 -0700

    Add more timestamps in coreboot.
    
    This adds a number of timestamps in ramstage and romstage
    so we can figure out where execution time goes.
    
    Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/lib/cbfs_and_run.c |    3 +++
 src/boot/hardwaremain.c         |   21 +++++++++++++++++++++
 src/include/timestamp.h         |   22 ++++++++++++++++++++--
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index ad36ddc..53f06ee 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -20,16 +20,19 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include <arch/stages.h>
+#include <timestamp.h>
 
 static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 
+	timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
 	if ((void *)dst == (void *) -1)
 		die("FATAL: Essential component is missing.\n");
 
+	timestamp_add_now(TS_END_COPYRAM);
 	print_debug("Jumping to image.\n");
 	__asm__ volatile (
 		"movl %%eax, %%ebp\n"
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 9b293c0..489caa3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,6 +41,7 @@ it with the version available from LANL.
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
@@ -56,7 +57,9 @@ void hardwaremain(int boot_complete);
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
+	timestamps[0] = rdtsc();
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
@@ -78,18 +81,26 @@ void hardwaremain(int boot_complete)
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
 	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
 	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
 #if CONFIG_CONSOLE_CBMEM
@@ -101,10 +112,20 @@ void hardwaremain(int boot_complete)
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 8b9a89a..0bb323c 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -35,14 +35,32 @@ struct timestamp_table {
 } __attribute__((packed));
 
 enum timestamp_id {
-	TS_BEFORE_INITRAM = 1,
-	TS_AFTER_INITRAM = 2,
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
 	TS_ACPI_WAKE_JUMP = 98,
 	TS_SELFBOOT_JUMP = 99,
 };
 
+#if CONFIG_COLLECT_TIMESTAMPS
 void timestamp_init(tsc_t base);
 void timestamp_add(enum timestamp_id id, tsc_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
+#else
+#define timestamp_init(base)
+#define timestamp_add(id, time)
+#define timestamp_add_now(id)
+#endif
 
 #endif



From gerrit at coreboot.org  Wed Mar  7 01:24:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:53 +0100
Subject: [coreboot] New patch to review for coreboot: 2e72f8a Allow
	components smaller than declared size.
References: <I1b04f90051b91157391943c9bad0eb06dd297431+0@gerrit.coreboot.org>
Message-ID: <I1b04f90051b91157391943c9bad0eb06dd297431+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751

-gerrit

commit 2e72f8ad4e057c8fc932902f70bc266358561020
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Nov 9 14:11:26 2011 -0800

    Allow components smaller than declared size.
    
    idftool was failing to add the ME blobs into the output image in case
    the blob size does not exactly match the size allocated for it in the
    flashrom structure.
    
    It is difficult to set the field in the structure to exactly match the
    size (for some reason Intel flash tool fails to insert the correct
    size even when given the exact ME blob). On the other hand there is no
    harm in using am ME blob smaller than the allocated size, this change
    modifies the tool building the image to allow for smaller components.
    
    Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/ifdtool/ifdtool.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index eb91b2c..8c1077c 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type,
 	printf("File %s is %d bytes\n", region_fname, region_size);
 
 	if ( (region_size > region.size) || ((region_type != 1) &&
-		(region_size != region.size))) {
+		(region_size > region.size))) {
 		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
 				" bytes. Not injecting.\n",
 				region_name(region_type), region.size,



From gerrit at coreboot.org  Wed Mar  7 01:24:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:53 +0100
Subject: [coreboot] New patch to review for coreboot: 71ce35a Fix warnings
	in coreboot utilities.
References: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+0@gerrit.coreboot.org>
Message-ID: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752

-gerrit

commit 71ce35ac0b8a3a2ba4a931cf9fb9284086adfec8
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Nov 14 12:40:34 2011 -0800

    Fix warnings in coreboot utilities.
    
    Fix some poor programming practice (breaks of strict aliasing as well as not
    checking the return value of read)
    
    Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/inteltool/cpu.c           |    6 ++++--
 util/inteltool/inteltool.c     |    4 +++-
 util/nvramtool/cli/nvramtool.c |    3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 20748bd..3bffa4e 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -67,8 +67,10 @@ msr_t rdmsr(int addr)
 	}
 
 	if (read(fd_msr, buf, 8) == 8) {
-		msr.lo = *(uint32_t *)buf;
-		msr.hi = *(uint32_t *)(buf + 4);
+		msr.lo = buf[0] | (buf[1] << 8) |
+			 (buf[2] << 16) | (buf[3] << 24);
+		msr.hi = buf[4] | (buf[5] << 8) |
+			 (buf[6] << 16) | (buf[7] << 24);
 
 		return msr;
 	}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6b99605..e5c2b86 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -21,6 +21,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <inttypes.h>
 #include <getopt.h>
 #include <fcntl.h>
 #include <sys/mman.h>
@@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len)
 		    fd_mem, (off_t) phys_addr);
 
 	if (virt_addr == MAP_FAILED) {
-		printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len);
+		printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
+			phys_addr, len);
 		return NULL;
 	}
 
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index 11a1a70..20097b8 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -143,7 +143,8 @@ int main(int argc, char *argv[])
 
 		if (fd_stat.st_size < 128) {
 			lseek(fd, 127, SEEK_SET);
-			write(fd, "\0", 1);
+			if (write(fd, "\0", 1) != 1)
+				fprintf(stderr, "Write failed.\n");
 			fsync(fd);
 		}
 



From gerrit at coreboot.org  Wed Mar  7 01:24:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:53 +0100
Subject: [coreboot] New patch to review for coreboot: 1fd9ee4 vga_io.c is
	not needed unless CONFIG_VGA is set
References: <I7b406251a2f3830748140a111f76f2792fe923ed+0@gerrit.coreboot.org>
Message-ID: <I7b406251a2f3830748140a111f76f2792fe923ed+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753

-gerrit

commit 1fd9ee46c839bd1db159335297bfad96b894d865
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 11:13:36 2011 -0800

    vga_io.c is not needed unless CONFIG_VGA is set
    
    hence disable it.
    
    Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/vga/Makefile.inc |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc
index 0ca7896..d4b726a 100644
--- a/src/pc80/vga/Makefile.inc
+++ b/src/pc80/vga/Makefile.inc
@@ -1,4 +1,4 @@
-ramstage-y += vga_io.c
+ramstage-$(CONFIG_VGA) += vga_io.c
 ramstage-$(CONFIG_VGA) += vga_palette.c
 ramstage-$(CONFIG_VGA) += vga_font_8x16.c
 ramstage-$(CONFIG_VGA) += vga.c



From gerrit at coreboot.org  Wed Mar  7 01:24:54 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:54 +0100
Subject: [coreboot] New patch to review for coreboot: 426e9a3 labels should
	start at the beginning of the line
References: <I60d0fa90656f85ecb8acc357fe6518baa773505b+0@gerrit.coreboot.org>
Message-ID: <I60d0fa90656f85ecb8acc357fe6518baa773505b+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/754

-gerrit

commit 426e9a32189f52b8abf03400a0a7872ef58797af
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:52:30 2011 -0800

    labels should start at the beginning of the line
    
    cosmetical fix
    
    Change-Id: I60d0fa90656f85ecb8acc357fe6518baa773505b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/secondary.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 5c1e760..dc00b08 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -47,7 +47,7 @@ _secondary_start:
 1:	hlt
 	jmp	1b
 
-	gdtaddr:
+gdtaddr:
 	.word   gdt_limit	/* the table limit */
 	.long   gdt             /* we know the offset */
 



From gerrit at coreboot.org  Wed Mar  7 01:24:55 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:55 +0100
Subject: [coreboot] New patch to review for coreboot: fb66503 use movsl for
	copying resume memory back
References: <Ibab0b478873912d67bf1f07743f628586353368a+0@gerrit.coreboot.org>
Message-ID: <Ibab0b478873912d67bf1f07743f628586353368a+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755

-gerrit

commit fb665036abbbaf8face05df7d70fce4d0247bf0b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:03:38 2011 -0800

    use movsl for copying resume memory back
    
    It's not significantly faster, but easier to read and smaller.
    
    Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/wakeup.S |   20 ++++----------------
 1 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..f12b176 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
 	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)



From gerrit at coreboot.org  Wed Mar  7 01:24:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:56 +0100
Subject: [coreboot] New patch to review for coreboot: 075dfb2 Don't
	unconditionally add support for cardbus and pci-x devices
References: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+0@gerrit.coreboot.org>
Message-ID: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756

-gerrit

commit 075dfb2195058ea398d7b47adb7c0afec0818261
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 30 12:45:14 2011 -0800

    Don't unconditionally add support for cardbus and pci-x devices
    
    It's still on by default.
    
    Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Makefile.inc |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
index 86b4d21..9ffc0bb 100644
--- a/src/devices/Makefile.inc
+++ b/src/devices/Makefile.inc
@@ -3,10 +3,10 @@ ramstage-y += root_device.c
 ramstage-y += device_util.c
 ramstage-y += pci_device.c
 ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
-ramstage-y += pcix_device.c
+ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
 ramstage-y += pciexp_device.c
-ramstage-y += agp_device.c
-ramstage-y += cardbus_device.c
+ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c
+ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
 ramstage-y += pnp_device.c
 ramstage-y += pci_ops.c
 ramstage-y += smbus_ops.c



From gerrit at coreboot.org  Wed Mar  7 01:24:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:56 +0100
Subject: [coreboot] New patch to review for coreboot: 35cd061 Add DEBUG_TPM
	option to Debugging menu
References: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+0@gerrit.coreboot.org>
Message-ID: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757

-gerrit

commit 35cd0615e09f887036311b104c218d9743a3501b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:50:54 2011 -0800

    Add DEBUG_TPM option to Debugging menu
    
    instead of having to edit the source code of tpm.c
    
    Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig    |    7 +++++++
 src/pc80/tpm.c |    9 +--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 26e6dde..41c5dbf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO
 
 	  If unsure, say N.
 
+config DEBUG_TPM
+	bool "Output verbose TPM debug messages"
+	default n
+	depends on TPM
+	help
+	  This option enables additional TPM related debug messages.
+
 config LLSHELL
 	bool "Built-in low-level shell"
 	default n
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 8e94303..17e1ed7 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -27,7 +27,6 @@
  * Infineon slb9635), so this driver provides access to locality 0 only.
  */
 
-/* #define DEBUG */
 #include <stdlib.h>
 #include <string.h>
 #include <delay.h>
@@ -37,17 +36,11 @@
 #include <pc80/tpm.h>
 #include <cpu/x86/car.h>
 
-#ifdef DEBUG
-#define TPM_DEBUG_ON	1
-#else
-#define TPM_DEBUG_ON	0
-#endif
-
 #define PREFIX "lpc_tpm: "
 
 /* coreboot wrapper for TPM driver (start) */
 #define	TPM_DEBUG(fmt, args...)		\
-	if (TPM_DEBUG_ON) {		\
+	if (CONFIG_DEBUG_TPM) {		\
 		printk(BIOS_DEBUG, PREFIX);		\
 		printk(BIOS_DEBUG, fmt , ##args);	\
 	}



From gerrit at coreboot.org  Wed Mar  7 01:24:57 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:57 +0100
Subject: [coreboot] New patch to review for coreboot: 973a340 Make PCI CONF2
	support a compile time option.
References: <I17df94a8a77b9338fde10a6b114b44d393776e66+0@gerrit.coreboot.org>
Message-ID: <I17df94a8a77b9338fde10a6b114b44d393776e66+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758

-gerrit

commit 973a3407658fd138e1f0d1c243b3525b2b9f9dc3
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:05:31 2011 -0800

    Make PCI CONF2 support a compile time option.
    
    It's not used on any board supported by coreboot but has been
    detected at run time since ages. No new boards (since 2000?)
    are using the CONF2 method, so it is unlikely we ever have to
    turn this on for a board.
    
    Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig            |    4 ++++
 src/arch/x86/lib/Makefile.inc   |    4 +---
 src/arch/x86/lib/pci_ops_auto.c |    9 ++++++++-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 078ae95..bc01c9c 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -96,4 +96,8 @@ config LITTLE_ENDIAN
 	bool
 	default !BIG_ENDIAN
 
+config PCI_CONF2
+	bool
+	default n
+
 endmenu
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3f4dc95..96fb9b0 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -1,10 +1,8 @@
 ramstage-y += c_start.S
 ramstage-y += cpu.c
 ramstage-y += pci_ops_conf1.c
-ramstage-y += pci_ops_conf2.c
-
+ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
 ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
index 92eedd3..58e098b 100644
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ b/src/arch/x86/lib/pci_ops_auto.c
@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#if CONFIG_PCI_CONF2
 /*
  * Before we decide to use direct hardware access mechanisms, we try to do some
  * trivial checks to ensure it at least _seems_ to be working -- we just test
@@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
 	return 0;
 }
 
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
+static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
 
 static const struct pci_bus_operations *pci_check_direct(void)
 {
@@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void)
 		pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
 	return pci_bus_fallback_ops;
 }
+#else
+const struct pci_bus_operations *pci_remember_direct(void)
+{
+	return &pci_cf8_conf1;
+}
+#endif
 
 /** Set the method to be used for PCI, type I or type II
  */



From gerrit at coreboot.org  Wed Mar  7 01:24:58 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:58 +0100
Subject: [coreboot] New patch to review for coreboot: 4a17211 Fix romcc to
	compile cleanly
References: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+0@gerrit.coreboot.org>
Message-ID: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759

-gerrit

commit 4a17211d7305877119606e9cbef9239830ec031d
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Dec 6 22:14:57 2011 +0000

    Fix romcc to compile cleanly
    
    There have been many unused variable assignments in the romcc source
    file. They cause multiple warning messages during build process which
    in turn make it harder to see the actual error message, when they are
    present.
    
    The fix is to remove dead code and to add -Werror to romcc compilation
    to avoid issues like this creeping in in the future.
    
    Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/romcc/Makefile |    2 +-
 util/romcc/romcc.c  |    3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/util/romcc/Makefile b/util/romcc/Makefile
index 6543fbb..8242eb5 100644
--- a/util/romcc/Makefile
+++ b/util/romcc/Makefile
@@ -1,7 +1,7 @@
 # Move the configuration defines to makefile.conf
 CC=gcc
 CPPFLAGS=
-CFLAGS= -g -Wall $(CPPFLAGS)
+CFLAGS= -g -Wall -Werror $(CPPFLAGS)
 CPROF_FLAGS=-pg -fprofile-arcs
 
 all: romcc test
diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c
index c7ef223..7eee439 100644
--- a/util/romcc/romcc.c
+++ b/util/romcc/romcc.c
@@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state)
 {
 	struct triple *ins, *next, *first;
 #if DEBUG_DECOMPOSE_HIRES
-	FILE *fp;
-	fp = state->dbgout;
+	FILE *fp = state->dbgout;
 #endif
 	first = state->first;
 	ins = first;



From gerrit at coreboot.org  Wed Mar  7 01:24:58 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 01:24:58 +0100
Subject: [coreboot] New patch to review for coreboot: c40f6dd drop use of
	MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
References: <Idf875ddec417e627f1e72a6d834860e7fd324a50+0@gerrit.coreboot.org>
Message-ID: <Idf875ddec417e627f1e72a6d834860e7fd324a50+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760

-gerrit

commit c40f6dde3b7c1cdcd18f223fceeb39c05b8e2b73
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Dec 15 09:24:40 2011 -0800

    drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
    
    Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/lapic_cpu_init.c |    6 ------
 src/cpu/x86/pae/Makefile.inc       |    2 +-
 2 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fc22ea4..99c3c4e 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -363,9 +363,7 @@ void secondary_cpu_init(void)
 {
 	atomic_inc(&active_cpus);
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_lock(&start_cpu_lock);
-  #endif
 #endif
 
 #ifdef __SSE3__
@@ -380,9 +378,7 @@ void secondary_cpu_init(void)
 #endif
 	cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_unlock(&start_cpu_lock);
-  #endif
 #endif
 
 	atomic_dec(&active_cpus);
@@ -419,9 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 				cpu->path.apic.apic_id);
 		}
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 		udelay(10);
-  #endif
 #endif
 	}
 
diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc
index 0ecec47..060720c 100644
--- a/src/cpu/x86/pae/Makefile.inc
+++ b/src/cpu/x86/pae/Makefile.inc
@@ -1 +1 @@
-ramstage-y += pgtbl.c
+ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c



From gerrit at coreboot.org  Wed Mar  7 01:27:00 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 01:27:00 +0100
Subject: [coreboot] Patch merged into filo/master: f1f9d46 makefile: don't
	evaluate empty input
References: <I0f482c4b680ca3eded4664c0a57e8525c068feaf+0@gerrit.coreboot.org>
Message-ID: <E1S54ia-0000nN-Ln@ra.coresystems.de>

the following patch was just integrated into master:
commit f1f9d467747176421a793ed0302730ee4b6a4bd2
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Mon Mar 5 11:23:24 2012 +0100

    makefile: don't evaluate empty input
    
    The output from util/xcompile/xcompile is redirected, so there is
    nothing left for make to $(eval)uate.
    
    Change-Id: I0f482c4b680ca3eded4664c0a57e8525c068feaf
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Tue Mar  6 16:44:14 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue Mar  6 21:52:45 2012, giving +2
See http://review.coreboot.org/740 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 01:39:33 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 01:39:33 +0100
Subject: [coreboot] Patch merged into filo/master: df119be makefile: rebuild
	config.h when needed
References: <Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a+0@gerrit.coreboot.org>
Message-ID: <E1S54uj-0005Eq-IW@ra.coresystems.de>

the following patch was just integrated into master:
commit df119bed3bad665af86209cb41111ccc8754f2f6
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:16:29 2012 +0100

    makefile: rebuild config.h when needed
    
    The dependencies for filo are quite awkward. Fix this by moving them
    where they belong to be, namely:
    * object files (not filo) depend on config.h
    * config.h (not filo) depends on .config to fix build problems when
      build/ gets removed or .config gets manually edited
    
    Change-Id: Ic107ad4d37cb6ce128ee3ad62cb8d271b457f91a
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Tue Mar  6 16:45:39 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue Mar  6 21:53:10 2012, giving +2
See http://review.coreboot.org/741 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 01:39:49 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 01:39:49 +0100
Subject: [coreboot] Patch merged into filo/master: ba947af makefile: create
	directories on demand
References: <Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079+0@gerrit.coreboot.org>
Message-ID: <E1S54uz-0005kT-6V@ra.coresystems.de>

the following patch was just integrated into master:
commit ba947af8efc8d7d5b403150ed16a8c61cdd9750d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:31:38 2012 +0100

    makefile: create directories on demand
    
    Use makefile dependencies to created needed directories instead of
    trying to recreate them on each make invocation.
    
    Change-Id: Ia06b1042f2a2c4905f5c8277a48ec4b8188f3079
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Tue Mar  6 16:47:07 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Tue Mar  6 21:53:30 2012, giving +2
See http://review.coreboot.org/742 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 02:06:14 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:14 +0100
Subject: [coreboot] New patch to review for coreboot: 0ccdd00 MTRR: add
	alternate allocation method for odd memory maps With >= 4GB
	memory installed we get a memory map split in the middle due
	to remap that has boundaries that are inconveniently aligned
	for MTRRs due to the various UMA regions.
References: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+0@gerrit.coreboot.org>
Message-ID: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761

-gerrit

commit 0ccdd0053d3704f7039097ed629ef5602748816c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 22 10:59:40 2011 -0800

    MTRR: add alternate allocation method for odd memory maps
    With >= 4GB memory installed we get a memory map split in the middle
    due to remap that has boundaries that are inconveniently aligned for
    MTRRs due to the various UMA regions.
    
    0000MB-2780MB  2780MB  RAM     (writeback)
    2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
    2782MB-2784MB     2MB  GFX GTT (uncached)
    2784MB-2816MB    32MB  GFX UMA (uncached)
    2816MB-4096MB  1280MB  EMPTY   (N/A)
    4096MB-5368MB  1272MB  RAM     (writeback)
    5368MB-5376MB     8MB  ME UMA  (uncached)
    
    The default MTRR allocation method of trying to cover everything
    with one MTRR and then carve out a single uncached region does
    not work for the GPU aperture which needs write-combining type,
    and it also has issues trying to cover the uneven boundaries
    in the avaiable variable MTRRs.
    
    My goal was to make a minimal set of changes and avoid modifying
    behavior on existing systems with an algorithm that is not always
    optimal for a typical memory layout.  So the flag 'above4gb=2'
    will change these allocation behaviors:
    
    1) Detect the number of available variable MTRRs rather than
    limiting to hardcoded value.  We need every last MTRR.
    
    2) Don't try to cover all RAM with one MTRR, instead let each
    RAM region get covered independently.
    
    3) Don't assume uma_memory_base is part of the last region
    and increase the size of that region.  In this case the UMA
    region is carved out from the lower memory region and it is
    already declared as part of the ram region.
    
    4) If a memory region can't be covered with MTRRs >= 16MB then
    instead make a larger region and trim it with uncached MTRRs.
    
    Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |   52 ++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 9015ad4..8dccfef 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x)
 #endif
 #define MTRRS        (BIOS_MTRRS + OS_MTRRS)
 
+static int total_mtrrs = MTRRS;
+static int bios_mtrrs = BIOS_MTRRS;
+
+static void detect_var_mtrrs(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MTRRcap_MSR);
+
+	total_mtrrs = msr.lo & 0xff;
+	bios_mtrrs = total_mtrrs - 2;
+}
 
 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
 {
@@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
 	unsigned long next_range_startk, unsigned char type,
 	unsigned int address_bits, unsigned int above4gb)
 {
+	unsigned long hole_startk = 0, hole_sizek = 0;
+
 	if (!range_sizek) {
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
@@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (reg >= BIOS_MTRRS) {
+	if (reg >= bios_mtrrs) {
 		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
@@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+		/*
+		 * If this range is not divisible by 16MB then instead
+		 * make a larger range and carve out an uncached hole.
+		 */
+		hole_startk = range_startk + range_sizek;
+		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		range_sizek += hole_sizek;
+	}
+
 	while(range_sizek) {
 		unsigned long max_align, align;
 		unsigned long sizek;
@@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg,
 			set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
-		if (reg >= BIOS_MTRRS) {
+		if (reg >= bios_mtrrs) {
 			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
+
+	if (hole_sizek) {
+		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
+		       hole_startk, hole_startk + hole_sizek);
+		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
+			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
+			      address_bits, above4gb);
+	}
+
 	return reg;
 }
 
@@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 {
 	struct var_mtrr_state *state = gp;
 	unsigned long basek, sizek;
-	if (state->reg >= BIOS_MTRRS)
+	if (state->reg >= bios_mtrrs)
 		return;
 	basek = resk(res->base);
 	sizek = resk(res->size);
@@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
 #if CONFIG_VAR_MTRR_HOLE
-		if (state->hole_sizek == 0) {
+		if (state->hole_sizek == 0 && state->above4gb != 2) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
@@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	var_state.address_bits = address_bits;
 	var_state.above4gb = above4gb;
 
+	/* Detect number of variable MTRRs */
+	if (above4gb == 2)
+		detect_var_mtrrs();
+
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
@@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	} else {
 #if CONFIG_VAR_MTRR_HOLE
 		// Increase the base range and set up UMA as an UC hole instead
-		var_state.range_sizek += (uma_memory_size >> 10);
+		if (above4gb != 2)
+			var_state.range_sizek += (uma_memory_size >> 10);
 
 		var_state.hole_startk = (uma_memory_base >> 10);
 		var_state.hole_sizek = (uma_memory_size >> 10);
@@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
 	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
-	while(var_state.reg < MTRRS) {
+	while(var_state.reg < total_mtrrs) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
 
@@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	 * complete ROM now that we actually have RAM.
 	 */
 	if (boot_cpu() && (acpi_slp_type != 3)) {
-		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+		set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024,
 			MTRR_TYPE_WRPROT, address_bits);
 	}
 #endif



From gerrit at coreboot.org  Wed Mar  7 02:06:15 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:15 +0100
Subject: [coreboot] New patch to review for coreboot: eeec1ae Revamp
	cbmem.py to use the coreboot tables.
References: <I51833055a50c2d76423520ba6e059bf8fc50adea+0@gerrit.coreboot.org>
Message-ID: <I51833055a50c2d76423520ba6e059bf8fc50adea+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/762

-gerrit

commit eeec1aec41c3bc12baa1a00039c9197e352a2674
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Jan 7 01:03:42 2012 -0800

    Revamp cbmem.py to use the coreboot tables.
    
    This change makes significant changes to cbmem.py to make it use the
    coreboot tables to find the memory console and timestamp areas instead
    of looking for the in memory table TOC structure. That appears to be
    more robust and gets cbmem.py working again after some unrelated
    changes that affected memory layout.
    
    It also introduces some small infrastructure to make accessing C style
    structures in physical memory easier and more transparent.
    
    Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 util/cbmem/cbmem.py |  267 ++++++++++++++++++++++++++++++---------------------
 1 files changed, 158 insertions(+), 109 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
index 3e8476d..f4f3e88 100755
--- a/util/cbmem/cbmem.py
+++ b/util/cbmem/cbmem.py
@@ -33,29 +33,46 @@ console sections.
 '''
 
 import mmap
-import re
 import struct
 import sys
-import time
 
-# These definitions follow src/include/cbmem.h
-CBMEM_MAGIC = 0x434f5245
-CBMEM_MAX_ENTRIES = 16
+def get_phys_mem(addr, size):
+    '''Read size bytes from address addr by mmaping /dev/mem'''
 
-CBMEM_ENTRY_FORMAT = '@LLQQ'
-CONSOLE_HEADER_FORMAT = '@LL'
-TIMESTAMP_HEADER_FORMAT = '@QLL'
-TIMESTAMP_ENTRY_FORMAT = '@LQ'
-
-mf_fileno = 0  # File number of the file providing access to memory.
-
-def align_up(base, alignment):
-    '''Increment to the alignment boundary.
-
-    Return the next integer larger than 'base' and divisible by 'alignment'.
-    '''
-
-    return base + alignment - base % alignment
+    mf = open("/dev/mem")
+    delta = addr % 4096
+    mm = mmap.mmap(mf.fileno(), size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mf.close()
+    return buf[delta:]
+
+# This class and metaclass make it easier to define and access structures
+# which live in physical memory. To use them, inherit from CStruct and define
+# a class member called struct_members which is a tuple of pairs. The first
+# item in the pair is the type format specifier that should be used with
+# struct.unpack to read that member from memory. The second item is the name
+# that member should have in the resulting object.
+
+class MetaCStruct(type):
+    def __init__(cls, name, bases, dct):
+        struct_members = dct["struct_members"]
+        cls.struct_fmt = "@"
+        for char, name in struct_members:
+            cls.struct_fmt += char
+        cls.struct_len = struct.calcsize(cls.struct_fmt)
+        super(MetaCStruct, cls).__init__(name, bases, dct)
+
+class CStruct(object):
+    __metaclass__ = MetaCStruct
+    struct_members = ()
+
+    def __init__(self, addr):
+        self.raw_memory = get_phys_mem(addr, self.struct_len)
+        values = struct.unpack(self.struct_fmt, self.raw_memory)
+        names = (name for char, name in self.struct_members)
+        for name, value in zip(names, values):
+            setattr(self, name, value)
 
 def normalize_timer(value, freq):
     '''Convert timer reading into microseconds.
@@ -96,109 +113,141 @@ def get_cpu_freq():
     # Convert reading into Hertz
     return float(freq_str) * 1000.0
 
-def get_mem_size():
-    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
-    mult = {
-        'kB': 1024
-        }
-    meminfo = open('/proc/meminfo').read()
-    m = re.search('MemTotal:.*\n', meminfo)
-    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
-    (_, size, mult_name) = mem_string.split()
-    return int(size) * mult[mult_name]
-
-def parse_mem_at(addr, format):
-    '''Read and parse a memory location.
-
-    This function reads memory at the passed in address, parses it according
-    to the passed in format specification and returns a list of values.
-
-    The first value in the list is the size of data matching the format
-    expression, and the rest of the elements of the list are the actual values
-    retrieved using the format.
-    '''
-
-    size = struct.calcsize(format)
-    delta = addr % 4096   # mmap requires the offset to be page size aligned.
-    mm = mmap.mmap(mf_fileno, size + delta,
-                   mmap.MAP_PRIVATE, offset=(addr - delta))
-    buf = mm.read(size + delta)
-    mm.close()
-    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
-    return rv
-
-def dprint(text):
-    '''Debug print function.
-
-    Edit it to get the debug output.
-    '''
-
-    if False:
-        print text
-
 def process_timers(base):
     '''Scan the array of timestamps found in CBMEM at address base.
 
     For each timestamp print the timer ID and the value in microseconds.
     '''
 
-    (step, base_time, max_entr, entr) = parse_mem_at(
-        base, TIMESTAMP_HEADER_FORMAT)
-
-    print('\ntime base %d, total entries %d' % (base_time, entr))
+    class TimestampHeader(CStruct):
+        struct_members = (
+            ("Q", "base_time"),
+            ("L", "max_entr"),
+            ("L", "entr")
+        )
+
+    class TimestampEntry(CStruct):
+        struct_members = (
+            ("L", "timer_id"),
+            ("Q", "timer_value")
+        )
+
+    header = TimestampHeader(base)
+    print('\ntime base %d, total entries %d' % (header.base_time, header.entr))
     clock_freq = get_cpu_freq()
-    base = base + step
-    for i in range(entr):
-        (step, timer_id, timer_value) = parse_mem_at(
-            base, TIMESTAMP_ENTRY_FORMAT)
-        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
-        base = base + step
+    base = base + header.struct_len
+    for i in range(header.entr):
+        timestamp = TimestampEntry(base)
+        print '%d:%s ' % (timestamp.timer_id,
+            normalize_timer(timestamp.timer_value, clock_freq)),
+        base = base + timestamp.struct_len
     print
 
 def process_console(base):
     '''Dump the console log buffer contents found at address base.'''
 
-    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
-    print 'cursor at %d\n' % cursor
+    class ConsoleHeader(CStruct):
+        struct_members = (
+            ("L", "size"),
+            ("L", "cursor")
+        )
 
-    cons_string_format = '%ds' % min(cursor, size)
-    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    header = ConsoleHeader(base)
+    print 'cursor at %d\n' % header.cursor
+
+    cons_addr = base + header.struct_len
+    cons_length = min(header.cursor, header.size)
+    cons_text = get_phys_mem(cons_addr, cons_length)
     print cons_text
     print '\n'
 
-mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
-table_alignment = 128 * 1024
-
-mem_size = get_mem_size()
-
-# start at memory address aligned at 128K.
-offset = align_up(mem_size, table_alignment)
-
-dprint('mem_size %x offset %x' %(mem_size, offset))
-mf = open("/dev/mem")
-mf_fileno = mf.fileno()
-
-while offset % mem_alignment: # do not cross the 1G boundary while searching
-    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if magic == CBMEM_MAGIC:
-        offset = offset + step
-        break
-    offset += table_alignment
-else:
-    print 'Did not find the CBMEM'
-    sys.exit(0)
-
-for i in (range(1, CBMEM_MAX_ENTRIES)):
-    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if mid == 0:
-        break
-
-    print '%x, %x, %x' % (mid, base, size)
-    if mid == 0x54494d45:
-        process_timers(base)
-    if mid == 0x434f4e53:
-        process_console(base)
-
-    offset = offset + step
-
-mf.close()
+def ipchksum(buf):
+    '''Checksumming function used on the coreboot tables. The buffer being
+    checksummed is summed up as if it was an array of 16 bit unsigned
+    integers. If there are an odd number of bytes, the last element is zero
+    extended.'''
+
+    size = len(buf)
+    odd = size % 2
+    fmt = "<%dH" % ((size - odd) / 2)
+    if odd:
+        fmt += "B"
+    shorts = struct.unpack(fmt, buf)
+    checksum = sum(shorts)
+    checksum = (checksum >> 16) + (checksum & 0xffff)
+    checksum += (checksum >> 16)
+    checksum = ~checksum & 0xffff
+    return checksum
+
+def parse_tables(base, length):
+    '''Find the coreboot tables in memory and process whatever we can.'''
+
+    class CBTableHeader(CStruct):
+        struct_members = (
+            ("4s", "signature"),
+            ("I", "header_bytes"),
+            ("I", "header_checksum"),
+            ("I", "table_bytes"),
+            ("I", "table_checksum"),
+            ("I", "table_entries")
+        )
+
+    class CBTableEntry(CStruct):
+        struct_members = (
+            ("I", "tag"),
+            ("I", "size")
+        )
+
+    class CBTableForward(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("Q", "forward"),
+        )
+
+    class CBMemTab(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("L", "cbmem_tab"),
+        )
+
+    for addr in range(base, base + length, 16):
+        header = CBTableHeader(addr)
+        if header.signature == "LBIO":
+            break
+    else:
+        return -1
+
+    if header.header_bytes == 0:
+        return -1
+
+    if ipchksum(header.raw_memory) != 0:
+        print "Bad header checksum"
+        return -1
+
+    addr += header.header_bytes
+    table = get_phys_mem(addr, header.table_bytes)
+    if ipchksum(table) != header.table_checksum:
+        print "Bad table checksum"
+        return -1
+
+    for i in range(header.table_entries):
+        entry = CBTableEntry(addr)
+        if entry.tag == 0x11: # Forwarding entry
+            return parse_tables(CBTableForward(addr).forward, length)
+        elif entry.tag == 0x16: # Timestamps
+            process_timers(CBMemTab(addr).cbmem_tab)
+        elif entry.tag == 0x17: # CBMEM console
+            process_console(CBMemTab(addr).cbmem_tab)
+
+        addr += entry.size
+
+    return 0
+
+def main():
+    for base, length in (0x00000000, 0x1000), (0x000f0000, 0x1000):
+        if parse_tables(base, length):
+            break
+    else:
+        print "Didn't find the coreboot tables"
+        return 0
+
+if __name__ == "__main__":
+    sys.exit(main())



From gerrit at coreboot.org  Wed Mar  7 02:06:17 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:17 +0100
Subject: [coreboot] New patch to review for coreboot: 748e349 Fix MB
	calculation in the reporting of the MTRR hole
References: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+0@gerrit.coreboot.org>
Message-ID: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763

-gerrit

commit 748e349a427ffe71324173a80c1d1a6e9762f06c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Jan 6 15:49:30 2012 -0800

    Fix MB calculation in the reporting of the MTRR hole
    
    Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8dccfef..5f5e02b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 
 	if (hole_sizek) {
 		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
-		       hole_startk, hole_startk + hole_sizek);
+		       hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
 		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
 			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
 			      address_bits, above4gb);



From gerrit at coreboot.org  Wed Mar  7 02:06:18 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:18 +0100
Subject: [coreboot] New patch to review for coreboot: 3b05660 Make cpuid
	functions usable when compiled with PIC
References: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+0@gerrit.coreboot.org>
Message-ID: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764

-gerrit

commit 3b0566044cdf94f37e3227b4423dd4d84735d064
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:00:30 2012 -0800

    Make cpuid functions usable when compiled with PIC
    
    This avoids using EBX and instead uses EDI where possible,
    and ESI when necessary to get the EBX value out.
    
    This allows me to enable -fpic for SMM TSEG code.
    
    Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/include/arch/cpu.h |   57 ++++++++++++++++++++++++++++++--------
 1 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 85357d7..508b7d6 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op)
 {
 	struct cpuid_result result;
 	asm volatile(
-		"cpuid"
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
 		: "=a" (result.eax),
-		  "=b" (result.ebx),
+		  "=S" (result.ebx),
 		  "=c" (result.ecx),
 		  "=d" (result.edx)
-		: "0" (op));
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
 	return result;
 }
 
@@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op)
 {
 	unsigned int eax;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax)
 		: "0" (op)
-		: "ebx", "ecx", "edx");
+		: "ecx", "edx", "edi");
 	return eax;
 }
 
@@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op)
 {
 	unsigned int eax, ebx;
 
-	__asm__("cpuid"
-		: "=a" (eax), "=b" (ebx)
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		"mov %%edi, %%esi;"
+		: "=a" (eax), "=S" (ebx)
 		: "0" (op)
-		: "ecx", "edx" );
+		: "ecx", "edx", "edi");
 	return ebx;
 }
 
@@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op)
 {
 	unsigned int eax, ecx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=c" (ecx)
 		: "0" (op)
-		: "ebx", "edx" );
+		: "edx", "edi");
 	return ecx;
 }
 
@@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op)
 {
 	unsigned int eax, edx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=d" (edx)
 		: "0" (op)
-		: "ebx", "ecx");
+		: "ecx", "edi");
 	return edx;
 }
 



From gerrit at coreboot.org  Wed Mar  7 02:06:20 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:20 +0100
Subject: [coreboot] New patch to review for coreboot: 8819294 Make MTRR min
	hole alignment 64MB
References: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+0@gerrit.coreboot.org>
Message-ID: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765

-gerrit

commit 8819294696d2d2aa89bf760a9b8529991255f6fd
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:05:18 2012 -0800

    Make MTRR min hole alignment 64MB
    
    This affects the algorithm when determining when to
    transform a range into a larger range with a hole.
    
    It is needed when for when I switch on an 8MB TSEG
    and cause the memory maps to go crazy.
    
    Also add header defines for the SMRR.
    
    Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c    |    9 ++++++---
 src/include/cpu/x86/mtrr.h |    3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02b..ed7d93b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
 		/*
-		 * If this range is not divisible by 16MB then instead
+		 * If this range is not divisible then instead
 		 * make a larger range and carve out an uncached hole.
 		 */
 		hole_startk = range_startk + range_sizek;
-		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
 		range_sizek += hole_sizek;
 	}
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7..8b5cc28 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 



From gerrit at coreboot.org  Wed Mar  7 02:06:26 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:26 +0100
Subject: [coreboot] New patch to review for coreboot: b0ba5e3 Add Kconfig
	options to enable TSEG and set a size
References: <I1432569ece4371d6e12c997e90d66c175fa54c5c+0@gerrit.coreboot.org>
Message-ID: <I1432569ece4371d6e12c997e90d66c175fa54c5c+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766

-gerrit

commit b0ba5e3a291611e2389755c6037ea289207b74fe
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:11:25 2012 -0800

    Add Kconfig options to enable TSEG and set a size
    
    Future CPUs will require TSEG use for SMM
    
    Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/Kconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index fdbd527..2033a0a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -42,3 +42,11 @@ config LOGICAL_CPUS
 config CACHE_ROM
 	bool
 	default n
+
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0



From gerrit at coreboot.org  Wed Mar  7 02:06:35 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:35 +0100
Subject: [coreboot] New patch to review for coreboot: 990fa2a correctly mark
	code segments as code in SELF
References: <I82eaad23f08c02f4ed75744affa8835255cf5c17+0@gerrit.coreboot.org>
Message-ID: <I82eaad23f08c02f4ed75744affa8835255cf5c17+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/767

-gerrit

commit 990fa2ac2da79f8dbbdd3d1ad3abd7c2a749a5df
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 12:40:14 2012 -0800

    correctly mark code segments as code in SELF
    
    In bios_log, find that the first segment of the payload is shown
    as code rather than data.
    
    Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
    Sample:
           Got a payload
           Loading segment from rom address 0xfff29378
             code (compression=1)
           ...
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbfstool/cbfs-mkpayload.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index ff6479d..e4ef5c8 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -161,7 +161,10 @@ int parse_elf_to_payload(unsigned char *input, unsigned char **output,
 			continue;
 		}
 
-		segs[segments].type = PAYLOAD_SEGMENT_DATA;
+		if (phdr[i].p_flags & PF_X)
+			segs[segments].type = PAYLOAD_SEGMENT_CODE;
+		else
+			segs[segments].type = PAYLOAD_SEGMENT_DATA;
 		segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr);
 		segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz);
 		segs[segments].compression = htonl(algo);



From gerrit at coreboot.org  Wed Mar  7 02:06:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:39 +0100
Subject: [coreboot] New patch to review for coreboot: f1424d7 selfboot: drop
	dead code As a left over from elfboot times,
	selfboot keeps the segments to load in the order in which they
	appeared in the original file as well as in the order they
	will later appear in memory. This is not needed in selfboot,
	so drop the code and structure members that handle the in-file order.
References: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+0@gerrit.coreboot.org>
Message-ID: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/768

-gerrit

commit f1424d7b0eabbc2fc6c320469ad25a57cbb8e0b6
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 14:07:39 2012 -0800

    selfboot: drop dead code
    As a left over from elfboot times, selfboot keeps the segments to
    load in the order in which they appeared in the original file as
    well as in the order they will later appear in memory. This is not
    needed in selfboot, so drop the code and structure members that handle
    the in-file order.
    
    Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |   25 ++++---------------------
 1 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index d4ab8c8..1675474 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -48,8 +48,6 @@ static const unsigned long lb_end = (unsigned long)&_eram_seg;
 struct segment {
 	struct segment *next;
 	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
 	unsigned long s_dstaddr;
 	unsigned long s_srcaddr;
 	unsigned long s_memsz;
@@ -234,11 +232,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg->prev;
 			seg->prev->next = new;
 			seg->prev = new;
-			/* Order by original program header order */
-			new->phdr_next = seg;
-			new->phdr_prev = seg->phdr_prev;
-			seg->phdr_prev->phdr_next = new;
-			seg->phdr_prev = new;
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
@@ -274,11 +267,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg;
 			seg->next->prev = new;
 			seg->next = new;
-			/* Order by original program header order */
-			new->phdr_next = seg->phdr_next;
-			new->phdr_prev = seg;
-			seg->phdr_next->phdr_prev = new;
-			seg->phdr_next = new;
 
 			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
@@ -312,7 +300,6 @@ static int build_self_segment_list(
 	struct segment *ptr;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
 	head->next = head->prev = head;
 	first_segment = segment = &payload->segments;
 
@@ -375,9 +362,10 @@ static int build_self_segment_list(
 			return -1;
 		}
 
+		/* We have found another CODE, DATA or BSS segment */
 		segment++;
 
-		// FIXME: Explain what this is
+		/* Find place where to insert our segment */
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohll(segment->load_addr))
 				break;
@@ -388,12 +376,6 @@ static int build_self_segment_list(
 		new->prev = ptr->prev;
 		ptr->prev->next = new;
 		ptr->prev = new;
-
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
 	}
 
 	return 1;
@@ -408,7 +390,8 @@ static int load_self_segments(
 
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		if (!overlaps_coreboot(ptr)) continue;
+		if (!overlaps_coreboot(ptr))
+			continue;
 		if (ptr->s_dstaddr + ptr->s_memsz > bounce_high)
 			bounce_high = ptr->s_dstaddr + ptr->s_memsz;
 	}



From gerrit at coreboot.org  Wed Mar  7 02:06:40 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:40 +0100
Subject: [coreboot] New patch to review for coreboot: 73b5bba Prepare the
	BIOS data areas before device init.
References: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+0@gerrit.coreboot.org>
Message-ID: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/769

-gerrit

commit 73b5bba34054ac4901739c92c5235ee15e756847
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jan 17 09:03:11 2012 -0800

    Prepare the BIOS data areas before device init.
    
    Since we do not run option roms in normal mode nothing was
    initializing the BDA/EBDA and yet Linux depends very much
    on it having sane values here.  For the most part the kernel
    tries to work around this not being initialized, but every
    once in awhile (1/300 boots or so) it would end up reading
    something that looked sane from BDA but was not and then
    it would panic.
    
    In this change the EBDA is unconditionally setup before devices
    are initialized.  I'm not set on the location in dev_initialize()
    but there does not seem to be another place to hook it in so
    that it runs just once for ALL platforms regardless of whether
    they use option roms or not. (possibly hardwaremain?)
    
    The EBDA setup code has been moved into its own location in
    arch/x86/lib/ebda.c so it can be compiled in even if the option
    rom code is not.
    
    The low memory size is still set to 1MB which is enough to make
    linux happy without having to hook into each mainboard to get a
    more appropriate value.  The setup_ebda() function takes inputs
    so it could be changed for a mainboard if needed.
    
    OLD/BROKEN would read garbage.  Examples from different boots:
    ebda_addr=0x75e80 lowmem=0x1553400
    ebda_addr=0x5e080 lowmem=0x3e51400
    ebda_addr=0x7aa80 lowmem=0x2f8a800
    
    NEW/FIXED now reads consistent values:
    ebda_addr=0xf6000 lowmem=0x100000
    
    Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/include/arch/ebda.h |   37 +++++++++++++++++++++++++++++
 src/arch/x86/lib/Makefile.inc    |    1 +
 src/arch/x86/lib/ebda.c          |   48 ++++++++++++++++++++++++++++++++++++++
 src/devices/device.c             |    8 ++++++
 src/devices/oprom/x86.c          |   16 ------------
 5 files changed, 94 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
new file mode 100644
index 0000000..1de6097
--- /dev/null
+++ b/src/arch/x86/include/arch/ebda.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_EBDA_H
+#define __ARCH_EBDA_H
+
+#define X86_BDA_SIZE		0x200
+#define X86_BDA_BASE		0x400
+#define X86_EBDA_SEGMENT	0x40e
+#define X86_EBDA_LOWMEM		0x413
+
+#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
+#define DEFAULT_EBDA_SEGMENT	0xF600
+#define DEFAULT_EBDA_SIZE	0x400
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size);
+void setup_default_ebda(void);
+
+#endif
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 96fb9b0..8f5fd5f 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,6 +8,7 @@ ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
 ramstage-y += memset.c
 ramstage-y += memcpy.c
+ramstage-y += ebda.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
new file mode 100644
index 0000000..faf1451
--- /dev/null
+++ b/src/arch/x86/lib/ebda.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/ebda.h>
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
+{
+	if (!low_memory_size || !ebda_segment || !ebda_size)
+		return;
+
+	/* clear BIOS DATA AREA */
+	memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE);
+
+	write16(X86_EBDA_LOWMEM, (low_memory_size >> 10));
+	write16(X86_EBDA_SEGMENT, ebda_segment);
+
+	/* Set up EBDA */
+	memset((void *)(ebda_segment << 4), 0, ebda_size);
+	write16((ebda_segment << 4), (ebda_size >> 10));
+}
+
+void setup_default_ebda(void)
+{
+	setup_ebda(DEFAULT_EBDA_LOWMEM,
+		   DEFAULT_EBDA_SEGMENT,
+		   DEFAULT_EBDA_SIZE);
+}
diff --git a/src/devices/device.c b/src/devices/device.c
index a2619bf..f559da5 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -41,6 +41,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
+#if CONFIG_ARCH_X86
+#include <arch/ebda.h>
+#endif
 
 /** Linked list of ALL devices */
 struct device *all_devices = &dev_root;
@@ -1102,6 +1105,11 @@ void dev_initialize(void)
 
 	printk(BIOS_INFO, "Initializing devices...\n");
 
+#if CONFIG_ARCH_X86
+	/* Ensure EBDA is prepared before Option ROMs. */
+	setup_default_ebda();
+#endif
+
 	/* First call the mainboard init. */
 	init_dev(&dev_root);
 
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 0c15b15..564017d 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -40,19 +40,6 @@ void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0))) =
 						(void *)&__realmode_interrupt;
 
-static void setup_bda(void)
-{
-	/* clear BIOS DATA AREA */
-	memset((void *)0x400, 0, 0x200);
-
-	write16(0x413, FAKE_MEMORY_SIZE / 1024);
-	write16(0x40e, INITIAL_EBDA_SEGMENT);
-
-	/* Set up EBDA */
-	memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE);
-	write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024);
-}
-
 static void setup_rombios(void)
 {
 	const char date[] = "06/11/99";
@@ -272,9 +259,6 @@ void run_bios(struct device *dev, unsigned long addr)
 	 */
 	setup_i8259();
 
-	/* Set up BIOS Data Area */
-	setup_bda();
-
 	/* Set up some legacy information in the F segment */
 	setup_rombios();
 



From gerrit at coreboot.org  Wed Mar  7 02:06:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:06:41 +0100
Subject: [coreboot] New patch to review for coreboot: 8963535 Don't re-init
	EBDA in S3 resume path.
References: <I950ac260f251e2683693d9bd20a0dd5e041aa26e+0@gerrit.coreboot.org>
Message-ID: <I950ac260f251e2683693d9bd20a0dd5e041aa26e+1@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/770

-gerrit

commit 8963535f0da1e1e464c48b200fab3288fe3db75b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jan 18 10:05:18 2012 -0800

    Don't re-init EBDA in S3 resume path.
    
    I forgot to implement this the first time around.
    
    It does not seem to cause noticeable problems but
    in heavy suspend/resume testing I saw a suspicious
    crash in the kernel when trying to bring one of the
    CPUs back online.
    
    Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/lib/ebda.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index faf1451..fb407b6 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -23,9 +23,18 @@
 #include <string.h>
 #include <arch/io.h>
 #include <arch/ebda.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
 
 void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 {
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Skip in S3 resume path */
+	if (acpi_slp_type == 3)
+		return;
+#endif
+
 	if (!low_memory_size || !ebda_segment || !ebda_size)
 		return;
 



From gerrit at coreboot.org  Wed Mar  7 02:11:51 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:51 +0100
Subject: [coreboot] Patch set updated for coreboot: 2c403e4 Don't re-init
	EBDA in S3 resume path.
References: <I950ac260f251e2683693d9bd20a0dd5e041aa26e+0@gerrit.coreboot.org>
Message-ID: <I950ac260f251e2683693d9bd20a0dd5e041aa26e+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/770

-gerrit

commit 2c403e49c56e818e669e4c095c3f7a2124e0032c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jan 18 10:05:18 2012 -0800

    Don't re-init EBDA in S3 resume path.
    
    I forgot to implement this the first time around.
    
    It does not seem to cause noticeable problems but
    in heavy suspend/resume testing I saw a suspicious
    crash in the kernel when trying to bring one of the
    CPUs back online.
    
    Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/lib/ebda.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
index faf1451..fb407b6 100644
--- a/src/arch/x86/lib/ebda.c
+++ b/src/arch/x86/lib/ebda.c
@@ -23,9 +23,18 @@
 #include <string.h>
 #include <arch/io.h>
 #include <arch/ebda.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
 
 void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 {
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Skip in S3 resume path */
+	if (acpi_slp_type == 3)
+		return;
+#endif
+
 	if (!low_memory_size || !ebda_segment || !ebda_size)
 		return;
 



From gerrit at coreboot.org  Wed Mar  7 02:11:52 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:52 +0100
Subject: [coreboot] Patch set updated for coreboot: 0196d91 selfboot: drop
	dead code As a left over from elfboot times,
	selfboot keeps the segments to load in the order in which they
	appeared in the original file as well as in the order they
	will later appear in memory. This is not needed in selfboot,
	so drop the code and structure members that handle the in-file order.
References: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+0@gerrit.coreboot.org>
Message-ID: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/768

-gerrit

commit 0196d911dfa20c442c0b52a667a30c5922ec1710
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 14:07:39 2012 -0800

    selfboot: drop dead code
    As a left over from elfboot times, selfboot keeps the segments to
    load in the order in which they appeared in the original file as
    well as in the order they will later appear in memory. This is not
    needed in selfboot, so drop the code and structure members that handle
    the in-file order.
    
    Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |   25 ++++---------------------
 1 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index d4ab8c8..1675474 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -48,8 +48,6 @@ static const unsigned long lb_end = (unsigned long)&_eram_seg;
 struct segment {
 	struct segment *next;
 	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
 	unsigned long s_dstaddr;
 	unsigned long s_srcaddr;
 	unsigned long s_memsz;
@@ -234,11 +232,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg->prev;
 			seg->prev->next = new;
 			seg->prev = new;
-			/* Order by original program header order */
-			new->phdr_next = seg;
-			new->phdr_prev = seg->phdr_prev;
-			seg->phdr_prev->phdr_next = new;
-			seg->phdr_prev = new;
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
@@ -274,11 +267,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg;
 			seg->next->prev = new;
 			seg->next = new;
-			/* Order by original program header order */
-			new->phdr_next = seg->phdr_next;
-			new->phdr_prev = seg;
-			seg->phdr_next->phdr_prev = new;
-			seg->phdr_next = new;
 
 			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
@@ -312,7 +300,6 @@ static int build_self_segment_list(
 	struct segment *ptr;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
 	head->next = head->prev = head;
 	first_segment = segment = &payload->segments;
 
@@ -375,9 +362,10 @@ static int build_self_segment_list(
 			return -1;
 		}
 
+		/* We have found another CODE, DATA or BSS segment */
 		segment++;
 
-		// FIXME: Explain what this is
+		/* Find place where to insert our segment */
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohll(segment->load_addr))
 				break;
@@ -388,12 +376,6 @@ static int build_self_segment_list(
 		new->prev = ptr->prev;
 		ptr->prev->next = new;
 		ptr->prev = new;
-
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
 	}
 
 	return 1;
@@ -408,7 +390,8 @@ static int load_self_segments(
 
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		if (!overlaps_coreboot(ptr)) continue;
+		if (!overlaps_coreboot(ptr))
+			continue;
 		if (ptr->s_dstaddr + ptr->s_memsz > bounce_high)
 			bounce_high = ptr->s_dstaddr + ptr->s_memsz;
 	}



From gerrit at coreboot.org  Wed Mar  7 02:11:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:53 +0100
Subject: [coreboot] Patch set updated for coreboot: a8d94d6 Prepare the BIOS
	data areas before device init.
References: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+0@gerrit.coreboot.org>
Message-ID: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/769

-gerrit

commit a8d94d6de75a653c0f58a4dbb2522bab6ce56c52
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jan 17 09:03:11 2012 -0800

    Prepare the BIOS data areas before device init.
    
    Since we do not run option roms in normal mode nothing was
    initializing the BDA/EBDA and yet Linux depends very much
    on it having sane values here.  For the most part the kernel
    tries to work around this not being initialized, but every
    once in awhile (1/300 boots or so) it would end up reading
    something that looked sane from BDA but was not and then
    it would panic.
    
    In this change the EBDA is unconditionally setup before devices
    are initialized.  I'm not set on the location in dev_initialize()
    but there does not seem to be another place to hook it in so
    that it runs just once for ALL platforms regardless of whether
    they use option roms or not. (possibly hardwaremain?)
    
    The EBDA setup code has been moved into its own location in
    arch/x86/lib/ebda.c so it can be compiled in even if the option
    rom code is not.
    
    The low memory size is still set to 1MB which is enough to make
    linux happy without having to hook into each mainboard to get a
    more appropriate value.  The setup_ebda() function takes inputs
    so it could be changed for a mainboard if needed.
    
    OLD/BROKEN would read garbage.  Examples from different boots:
    ebda_addr=0x75e80 lowmem=0x1553400
    ebda_addr=0x5e080 lowmem=0x3e51400
    ebda_addr=0x7aa80 lowmem=0x2f8a800
    
    NEW/FIXED now reads consistent values:
    ebda_addr=0xf6000 lowmem=0x100000
    
    Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/include/arch/ebda.h |   37 +++++++++++++++++++++++++++++
 src/arch/x86/lib/Makefile.inc    |    1 +
 src/arch/x86/lib/ebda.c          |   48 ++++++++++++++++++++++++++++++++++++++
 src/devices/device.c             |    8 ++++++
 src/devices/oprom/x86.c          |   16 ------------
 5 files changed, 94 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
new file mode 100644
index 0000000..1de6097
--- /dev/null
+++ b/src/arch/x86/include/arch/ebda.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_EBDA_H
+#define __ARCH_EBDA_H
+
+#define X86_BDA_SIZE		0x200
+#define X86_BDA_BASE		0x400
+#define X86_EBDA_SEGMENT	0x40e
+#define X86_EBDA_LOWMEM		0x413
+
+#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
+#define DEFAULT_EBDA_SEGMENT	0xF600
+#define DEFAULT_EBDA_SIZE	0x400
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size);
+void setup_default_ebda(void);
+
+#endif
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 96fb9b0..8f5fd5f 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,6 +8,7 @@ ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
 ramstage-y += memset.c
 ramstage-y += memcpy.c
+ramstage-y += ebda.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
new file mode 100644
index 0000000..faf1451
--- /dev/null
+++ b/src/arch/x86/lib/ebda.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/ebda.h>
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
+{
+	if (!low_memory_size || !ebda_segment || !ebda_size)
+		return;
+
+	/* clear BIOS DATA AREA */
+	memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE);
+
+	write16(X86_EBDA_LOWMEM, (low_memory_size >> 10));
+	write16(X86_EBDA_SEGMENT, ebda_segment);
+
+	/* Set up EBDA */
+	memset((void *)(ebda_segment << 4), 0, ebda_size);
+	write16((ebda_segment << 4), (ebda_size >> 10));
+}
+
+void setup_default_ebda(void)
+{
+	setup_ebda(DEFAULT_EBDA_LOWMEM,
+		   DEFAULT_EBDA_SEGMENT,
+		   DEFAULT_EBDA_SIZE);
+}
diff --git a/src/devices/device.c b/src/devices/device.c
index a2619bf..f559da5 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -41,6 +41,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
+#if CONFIG_ARCH_X86
+#include <arch/ebda.h>
+#endif
 
 /** Linked list of ALL devices */
 struct device *all_devices = &dev_root;
@@ -1102,6 +1105,11 @@ void dev_initialize(void)
 
 	printk(BIOS_INFO, "Initializing devices...\n");
 
+#if CONFIG_ARCH_X86
+	/* Ensure EBDA is prepared before Option ROMs. */
+	setup_default_ebda();
+#endif
+
 	/* First call the mainboard init. */
 	init_dev(&dev_root);
 
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 0c15b15..564017d 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -40,19 +40,6 @@ void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx,
 		u32 esi, u32 edi) __attribute__((regparm(0))) =
 						(void *)&__realmode_interrupt;
 
-static void setup_bda(void)
-{
-	/* clear BIOS DATA AREA */
-	memset((void *)0x400, 0, 0x200);
-
-	write16(0x413, FAKE_MEMORY_SIZE / 1024);
-	write16(0x40e, INITIAL_EBDA_SEGMENT);
-
-	/* Set up EBDA */
-	memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE);
-	write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024);
-}
-
 static void setup_rombios(void)
 {
 	const char date[] = "06/11/99";
@@ -272,9 +259,6 @@ void run_bios(struct device *dev, unsigned long addr)
 	 */
 	setup_i8259();
 
-	/* Set up BIOS Data Area */
-	setup_bda();
-
 	/* Set up some legacy information in the F segment */
 	setup_rombios();
 



From gerrit at coreboot.org  Wed Mar  7 02:11:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:56 +0100
Subject: [coreboot] Patch set updated for coreboot: 3bbcbe8 Allow components
	smaller than declared size.
References: <I1b04f90051b91157391943c9bad0eb06dd297431+0@gerrit.coreboot.org>
Message-ID: <I1b04f90051b91157391943c9bad0eb06dd297431+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751

-gerrit

commit 3bbcbe8d46d047f2ff2dc5b7ee1d156a25be08b5
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Nov 9 14:11:26 2011 -0800

    Allow components smaller than declared size.
    
    idftool was failing to add the ME blobs into the output image in case
    the blob size does not exactly match the size allocated for it in the
    flashrom structure.
    
    It is difficult to set the field in the structure to exactly match the
    size (for some reason Intel flash tool fails to insert the correct
    size even when given the exact ME blob). On the other hand there is no
    harm in using am ME blob smaller than the allocated size, this change
    modifies the tool building the image to allow for smaller components.
    
    Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/ifdtool/ifdtool.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index eb91b2c..8c1077c 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type,
 	printf("File %s is %d bytes\n", region_fname, region_size);
 
 	if ( (region_size > region.size) || ((region_type != 1) &&
-		(region_size != region.size))) {
+		(region_size > region.size))) {
 		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
 				" bytes. Not injecting.\n",
 				region_name(region_type), region.size,



From gerrit at coreboot.org  Wed Mar  7 02:11:57 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:57 +0100
Subject: [coreboot] Patch set updated for coreboot: 7beb072 Fix coreboot
	makefiles not to produce half baked output.
References: <I7c17f033ee5937eb712b1a594122430cee5c9146+0@gerrit.coreboot.org>
Message-ID: <I7c17f033ee5937eb712b1a594122430cee5c9146+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750

-gerrit

commit 7beb072eab7678c45319fd52e5c7d5372342d24b
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Nov 5 02:07:01 2011 +0000

    Fix coreboot makefiles not to produce half baked output.
    
    It looks like the cbfstool utility generates the output file even when
    it fails to generate it properly. This causes make, if started second
    time in a row, after cbfstool failure, to continue beyond the point of
    failure (as the corrupted output file is present in the output tree,
    the second make invocation presumes that it is valid, as it is newer
    than the dependencies).
    
    The output file should be created only when successful, in an atomic
    operation. There could be other places in the make system which
    require a similar fix, this needs to be investigated further.
    
    Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/Makefile.inc |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index aeb4875..b2b9143 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2)))
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	$(foreach file,$(cbfs-files), \
-		$(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
+	$(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \
+	$(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \
+	$(call extract_nth,4,$(file)) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL)
-	rm -f $@
-	$(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
-	$(prebuild-files)
+	$(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
+	$(prebuild-files) true
+	mv $@.tmp $@
 else
 .PHONY: $(obj)/coreboot.pre1
 $(obj)/coreboot.pre1: $(CBFSTOOL)
@@ -269,10 +271,10 @@ endif
 
 $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
+	cp $(obj)/coreboot.pre1 $@.tmp
+	$(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \
 	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	mv $@.tmp $@
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################



From gerrit at coreboot.org  Wed Mar  7 02:11:58 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:11:58 +0100
Subject: [coreboot] Patch set updated for coreboot: f26187b Add more
	timestamps in coreboot.
References: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+0@gerrit.coreboot.org>
Message-ID: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749

-gerrit

commit f26187b7794b7d4b9f41e630b474f7cf904ef406
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Nov 4 12:31:58 2011 -0700

    Add more timestamps in coreboot.
    
    This adds a number of timestamps in ramstage and romstage
    so we can figure out where execution time goes.
    
    Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/lib/cbfs_and_run.c |    3 +++
 src/boot/hardwaremain.c         |   21 +++++++++++++++++++++
 src/include/timestamp.h         |   22 ++++++++++++++++++++--
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index ad36ddc..53f06ee 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -20,16 +20,19 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include <arch/stages.h>
+#include <timestamp.h>
 
 static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 
+	timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
 	if ((void *)dst == (void *) -1)
 		die("FATAL: Essential component is missing.\n");
 
+	timestamp_add_now(TS_END_COPYRAM);
 	print_debug("Jumping to image.\n");
 	__asm__ volatile (
 		"movl %%eax, %%ebp\n"
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 9b293c0..489caa3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,6 +41,7 @@ it with the version available from LANL.
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
@@ -56,7 +57,9 @@ void hardwaremain(int boot_complete);
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
+	timestamps[0] = rdtsc();
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
@@ -78,18 +81,26 @@ void hardwaremain(int boot_complete)
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
 	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
 	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
 #if CONFIG_CONSOLE_CBMEM
@@ -101,10 +112,20 @@ void hardwaremain(int boot_complete)
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 8b9a89a..0bb323c 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -35,14 +35,32 @@ struct timestamp_table {
 } __attribute__((packed));
 
 enum timestamp_id {
-	TS_BEFORE_INITRAM = 1,
-	TS_AFTER_INITRAM = 2,
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
 	TS_ACPI_WAKE_JUMP = 98,
 	TS_SELFBOOT_JUMP = 99,
 };
 
+#if CONFIG_COLLECT_TIMESTAMPS
 void timestamp_init(tsc_t base);
 void timestamp_add(enum timestamp_id id, tsc_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
+#else
+#define timestamp_init(base)
+#define timestamp_add(id, time)
+#define timestamp_add_now(id)
+#endif
 
 #endif



From gerrit at coreboot.org  Wed Mar  7 02:12:00 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:00 +0100
Subject: [coreboot] Patch set updated for coreboot: ab2fdae Add an option to
	keep the ROM cached after romstage
References: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+0@gerrit.coreboot.org>
Message-ID: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739

-gerrit

commit ab2fdae0e94cf63934bb7cc7b789dd5840dcdb73
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 2 16:12:34 2011 -0700

    Add an option to keep the ROM cached after romstage
    
    Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/include/arch/acpi.h |    4 +++-
 src/cpu/x86/Kconfig              |    4 +++-
 src/cpu/x86/lapic/Makefile.inc   |    1 +
 src/cpu/x86/lapic/boot_cpu.c     |    3 ++-
 src/cpu/x86/mtrr/mtrr.c          |   14 +++++++++++++-
 src/include/cpu/x86/lapic.h      |    4 ++++
 6 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..504d71b 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,6 +435,7 @@ void generate_cpu_entries(void);
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
 
 #endif
 
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 348f0ef..fdbd527 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -39,4 +39,6 @@ config LOGICAL_CPUS
 	bool
 	default y
 
-
+config CACHE_ROM
+	bool
+	default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956..f3fcadc 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0..0fb9d5d 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d..9015ad4 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
 	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
-
 void enable_fixed_mtrr(void)
 {
 	msr_t msr;
@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	while(var_state.reg < MTRRS) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
+
+#if CONFIG_CACHE_ROM
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	if (boot_cpu() && (acpi_slp_type != 3)) {
+		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+			MTRR_TYPE_WRPROT, address_bits);
+	}
+#endif
+
 	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6c..016870d 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,6 +1,7 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#ifndef __ROMCC__
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
@@ -156,4 +157,7 @@ int start_cpu(struct device *cpu);
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */



From gerrit at coreboot.org  Wed Mar  7 02:12:02 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:02 +0100
Subject: [coreboot] Patch set updated for coreboot: 4500344 Make TPM driver
	work in rom stage.
References: <Ifc827d0cd0159aa3f6752d395974f2812334f262+0@gerrit.coreboot.org>
Message-ID: <Ifc827d0cd0159aa3f6752d395974f2812334f262+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738

-gerrit

commit 4500344a59c6e8f1ce06dea896fcb553220fc790
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 27 21:28:25 2011 +0000

    Make TPM driver work in rom stage.
    
    Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/tpm.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 1cbf800..8e94303 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -35,6 +35,7 @@
 #include <arch/byteorder.h>
 #include <console/console.h>
 #include <pc80/tpm.h>
+#include <cpu/x86/car.h>
 
 #ifdef DEBUG
 #define TPM_DEBUG_ON	1
@@ -130,10 +131,10 @@ struct device_name {
 struct vendor_name {
 	u16 vendor_id;
 	const char * vendor_name;
-	struct device_name* dev_names;
+	const struct device_name* dev_names;
 };
 
-static struct device_name infineon_devices[] = {
+static const struct device_name infineon_devices[] = {
 	{0xb, "SLB9635 TT 1.2"},
 	{0}
 };
@@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = {
  * Cached vendor/device ID pair to indicate that the device has been already
  * discovered
  */
-static u32 vendor_dev_id;
+static u32 vendor_dev_id CAR_GLOBAL;
 
 static int is_byte_reg(u32 reg)
 {



From gerrit at coreboot.org  Wed Mar  7 02:12:04 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:04 +0100
Subject: [coreboot] Patch set updated for coreboot: 0ad6291 add native
	memset() function on x86.
References: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+0@gerrit.coreboot.org>
Message-ID: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/737

-gerrit

commit 0ad6291b03bec0e508421cf991864109fbbd5e97
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 26 22:11:52 2011 +0000

    add native memset() function on x86.
    
    Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig          |    4 ++
 src/arch/x86/lib/Makefile.inc |    2 +
 src/arch/x86/lib/memset.c     |   86 +++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc          |    4 ++
 4 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 74933af..078ae95 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMSET
+	bool
+	default y
+
 config HAVE_ARCH_MEMCPY
 	bool
 	default y
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index f99e429..3f4dc95 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,10 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memset.c
 ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memset.c
 romstage-y += memcpy.c
 
 smm-y += memcpy.c
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
new file mode 100644
index 0000000..e850726
--- /dev/null
+++ b/src/arch/x86/lib/memset.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <string.h>
+#include <stdint.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+	int d0;
+	unsigned long int dstp = (unsigned long int) dstpp;
+
+	/* This explicit register allocation improves code very much indeed. */
+	register op_t x asm("ax");
+
+	x = (unsigned char) c;
+
+	/* Clear the direction flag, so filling will move forward.  */
+	asm volatile("cld");
+
+	/* This threshold value is optimal.  */
+	if (len >= 12) {
+		/* Fill X with four copies of the char we want to fill with. */
+		x |= (x << 8);
+		x |= (x << 16);
+
+		/* Adjust LEN for the bytes handled in the first loop.  */
+		len -= (-dstp) % sizeof(op_t);
+
+		/*
+		 * There are at least some bytes to set. No need to test for
+		 * LEN == 0 in this alignment loop.
+		 */
+
+		/* Fill bytes until DSTP is aligned on a longword boundary. */
+		asm volatile(
+			"rep\n"
+			"stosb" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+			"memory");
+
+		/* Fill longwords.  */
+		asm volatile(
+			"rep\n"
+			"stosl" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+			"memory");
+		len %= sizeof(op_t);
+	}
+
+	/* Write the last few bytes. */
+	asm volatile(
+		"rep\n"
+		"stosb" /* %0, %2, %3 */ :
+		"=D" (dstp), "=c" (d0) :
+		"0" (dstp), "1" (len), "a" (x) :
+		"memory");
+
+	return dstpp;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 61b6451..8ce72b2 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,6 +1,8 @@
 
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 romstage-y += memset.c
+endif
 romstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
+endif
 ramstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c



From gerrit at coreboot.org  Wed Mar  7 02:12:06 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:06 +0100
Subject: [coreboot] Patch set updated for coreboot: 51f1e1a Add faster,
	architecture dependent memcpy()
References: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+0@gerrit.coreboot.org>
Message-ID: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736

-gerrit

commit 51f1e1aa4c3c59e6c95792feb13f5ee91ead7432
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 23:43:34 2011 +0000

    Add faster, architecture dependent memcpy()
    
    Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/Kconfig          |    4 ++++
 src/arch/x86/lib/Makefile.inc |    4 ++++
 src/arch/x86/lib/memcpy.c     |   13 +++++++++++++
 src/lib/Makefile.inc          |    9 ++++++++-
 4 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..74933af 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMCPY
+	bool
+	default y
+
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3388a9d..f99e429 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memcpy.c
+
+smm-y += memcpy.c
 
 $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h
diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c
new file mode 100644
index 0000000..de21092
--- /dev/null
+++ b/src/arch/x86/lib/memcpy.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+void *memcpy(void *__restrict __dest,
+	     __const void *__restrict __src, size_t __n)
+{
+	asm("cld\n"
+	    "rep\n"
+	    "movsb"
+	    :	/* no input (?) */
+	    :"S"(__src), "D"(__dest), "c"(__n)
+	);
+	return __dest;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 45cb788..61b6451 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -2,7 +2,9 @@
 
 romstage-y += memset.c
 romstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
+endif
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-y += memset.c
 ramstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c
+endif
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
 ramstage-y += malloc.c
@@ -43,7 +47,10 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
-smm-y += memcpy.c cbfs.c memset.c memcmp.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
+smm-y += memcpy.c
+endif
+smm-y += cbfs.c memset.c memcmp.c
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 smm-$(CONFIG_USBDEBUG) += usbdebug.c



From gerrit at coreboot.org  Wed Mar  7 02:12:08 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:08 +0100
Subject: [coreboot] Patch set updated for coreboot: 93beab8 Revamp cbmem.py
	to use the coreboot tables.
References: <I51833055a50c2d76423520ba6e059bf8fc50adea+0@gerrit.coreboot.org>
Message-ID: <I51833055a50c2d76423520ba6e059bf8fc50adea+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/762

-gerrit

commit 93beab8640ca83f3d62731aecb9d4d56e201dc05
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Jan 7 01:03:42 2012 -0800

    Revamp cbmem.py to use the coreboot tables.
    
    This change makes significant changes to cbmem.py to make it use the
    coreboot tables to find the memory console and timestamp areas instead
    of looking for the in memory table TOC structure. That appears to be
    more robust and gets cbmem.py working again after some unrelated
    changes that affected memory layout.
    
    It also introduces some small infrastructure to make accessing C style
    structures in physical memory easier and more transparent.
    
    Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 util/cbmem/cbmem.py |  267 ++++++++++++++++++++++++++++++---------------------
 1 files changed, 158 insertions(+), 109 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
index 3e8476d..f4f3e88 100755
--- a/util/cbmem/cbmem.py
+++ b/util/cbmem/cbmem.py
@@ -33,29 +33,46 @@ console sections.
 '''
 
 import mmap
-import re
 import struct
 import sys
-import time
 
-# These definitions follow src/include/cbmem.h
-CBMEM_MAGIC = 0x434f5245
-CBMEM_MAX_ENTRIES = 16
+def get_phys_mem(addr, size):
+    '''Read size bytes from address addr by mmaping /dev/mem'''
 
-CBMEM_ENTRY_FORMAT = '@LLQQ'
-CONSOLE_HEADER_FORMAT = '@LL'
-TIMESTAMP_HEADER_FORMAT = '@QLL'
-TIMESTAMP_ENTRY_FORMAT = '@LQ'
-
-mf_fileno = 0  # File number of the file providing access to memory.
-
-def align_up(base, alignment):
-    '''Increment to the alignment boundary.
-
-    Return the next integer larger than 'base' and divisible by 'alignment'.
-    '''
-
-    return base + alignment - base % alignment
+    mf = open("/dev/mem")
+    delta = addr % 4096
+    mm = mmap.mmap(mf.fileno(), size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mf.close()
+    return buf[delta:]
+
+# This class and metaclass make it easier to define and access structures
+# which live in physical memory. To use them, inherit from CStruct and define
+# a class member called struct_members which is a tuple of pairs. The first
+# item in the pair is the type format specifier that should be used with
+# struct.unpack to read that member from memory. The second item is the name
+# that member should have in the resulting object.
+
+class MetaCStruct(type):
+    def __init__(cls, name, bases, dct):
+        struct_members = dct["struct_members"]
+        cls.struct_fmt = "@"
+        for char, name in struct_members:
+            cls.struct_fmt += char
+        cls.struct_len = struct.calcsize(cls.struct_fmt)
+        super(MetaCStruct, cls).__init__(name, bases, dct)
+
+class CStruct(object):
+    __metaclass__ = MetaCStruct
+    struct_members = ()
+
+    def __init__(self, addr):
+        self.raw_memory = get_phys_mem(addr, self.struct_len)
+        values = struct.unpack(self.struct_fmt, self.raw_memory)
+        names = (name for char, name in self.struct_members)
+        for name, value in zip(names, values):
+            setattr(self, name, value)
 
 def normalize_timer(value, freq):
     '''Convert timer reading into microseconds.
@@ -96,109 +113,141 @@ def get_cpu_freq():
     # Convert reading into Hertz
     return float(freq_str) * 1000.0
 
-def get_mem_size():
-    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
-    mult = {
-        'kB': 1024
-        }
-    meminfo = open('/proc/meminfo').read()
-    m = re.search('MemTotal:.*\n', meminfo)
-    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
-    (_, size, mult_name) = mem_string.split()
-    return int(size) * mult[mult_name]
-
-def parse_mem_at(addr, format):
-    '''Read and parse a memory location.
-
-    This function reads memory at the passed in address, parses it according
-    to the passed in format specification and returns a list of values.
-
-    The first value in the list is the size of data matching the format
-    expression, and the rest of the elements of the list are the actual values
-    retrieved using the format.
-    '''
-
-    size = struct.calcsize(format)
-    delta = addr % 4096   # mmap requires the offset to be page size aligned.
-    mm = mmap.mmap(mf_fileno, size + delta,
-                   mmap.MAP_PRIVATE, offset=(addr - delta))
-    buf = mm.read(size + delta)
-    mm.close()
-    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
-    return rv
-
-def dprint(text):
-    '''Debug print function.
-
-    Edit it to get the debug output.
-    '''
-
-    if False:
-        print text
-
 def process_timers(base):
     '''Scan the array of timestamps found in CBMEM at address base.
 
     For each timestamp print the timer ID and the value in microseconds.
     '''
 
-    (step, base_time, max_entr, entr) = parse_mem_at(
-        base, TIMESTAMP_HEADER_FORMAT)
-
-    print('\ntime base %d, total entries %d' % (base_time, entr))
+    class TimestampHeader(CStruct):
+        struct_members = (
+            ("Q", "base_time"),
+            ("L", "max_entr"),
+            ("L", "entr")
+        )
+
+    class TimestampEntry(CStruct):
+        struct_members = (
+            ("L", "timer_id"),
+            ("Q", "timer_value")
+        )
+
+    header = TimestampHeader(base)
+    print('\ntime base %d, total entries %d' % (header.base_time, header.entr))
     clock_freq = get_cpu_freq()
-    base = base + step
-    for i in range(entr):
-        (step, timer_id, timer_value) = parse_mem_at(
-            base, TIMESTAMP_ENTRY_FORMAT)
-        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
-        base = base + step
+    base = base + header.struct_len
+    for i in range(header.entr):
+        timestamp = TimestampEntry(base)
+        print '%d:%s ' % (timestamp.timer_id,
+            normalize_timer(timestamp.timer_value, clock_freq)),
+        base = base + timestamp.struct_len
     print
 
 def process_console(base):
     '''Dump the console log buffer contents found at address base.'''
 
-    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
-    print 'cursor at %d\n' % cursor
+    class ConsoleHeader(CStruct):
+        struct_members = (
+            ("L", "size"),
+            ("L", "cursor")
+        )
 
-    cons_string_format = '%ds' % min(cursor, size)
-    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    header = ConsoleHeader(base)
+    print 'cursor at %d\n' % header.cursor
+
+    cons_addr = base + header.struct_len
+    cons_length = min(header.cursor, header.size)
+    cons_text = get_phys_mem(cons_addr, cons_length)
     print cons_text
     print '\n'
 
-mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
-table_alignment = 128 * 1024
-
-mem_size = get_mem_size()
-
-# start at memory address aligned at 128K.
-offset = align_up(mem_size, table_alignment)
-
-dprint('mem_size %x offset %x' %(mem_size, offset))
-mf = open("/dev/mem")
-mf_fileno = mf.fileno()
-
-while offset % mem_alignment: # do not cross the 1G boundary while searching
-    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if magic == CBMEM_MAGIC:
-        offset = offset + step
-        break
-    offset += table_alignment
-else:
-    print 'Did not find the CBMEM'
-    sys.exit(0)
-
-for i in (range(1, CBMEM_MAX_ENTRIES)):
-    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if mid == 0:
-        break
-
-    print '%x, %x, %x' % (mid, base, size)
-    if mid == 0x54494d45:
-        process_timers(base)
-    if mid == 0x434f4e53:
-        process_console(base)
-
-    offset = offset + step
-
-mf.close()
+def ipchksum(buf):
+    '''Checksumming function used on the coreboot tables. The buffer being
+    checksummed is summed up as if it was an array of 16 bit unsigned
+    integers. If there are an odd number of bytes, the last element is zero
+    extended.'''
+
+    size = len(buf)
+    odd = size % 2
+    fmt = "<%dH" % ((size - odd) / 2)
+    if odd:
+        fmt += "B"
+    shorts = struct.unpack(fmt, buf)
+    checksum = sum(shorts)
+    checksum = (checksum >> 16) + (checksum & 0xffff)
+    checksum += (checksum >> 16)
+    checksum = ~checksum & 0xffff
+    return checksum
+
+def parse_tables(base, length):
+    '''Find the coreboot tables in memory and process whatever we can.'''
+
+    class CBTableHeader(CStruct):
+        struct_members = (
+            ("4s", "signature"),
+            ("I", "header_bytes"),
+            ("I", "header_checksum"),
+            ("I", "table_bytes"),
+            ("I", "table_checksum"),
+            ("I", "table_entries")
+        )
+
+    class CBTableEntry(CStruct):
+        struct_members = (
+            ("I", "tag"),
+            ("I", "size")
+        )
+
+    class CBTableForward(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("Q", "forward"),
+        )
+
+    class CBMemTab(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("L", "cbmem_tab"),
+        )
+
+    for addr in range(base, base + length, 16):
+        header = CBTableHeader(addr)
+        if header.signature == "LBIO":
+            break
+    else:
+        return -1
+
+    if header.header_bytes == 0:
+        return -1
+
+    if ipchksum(header.raw_memory) != 0:
+        print "Bad header checksum"
+        return -1
+
+    addr += header.header_bytes
+    table = get_phys_mem(addr, header.table_bytes)
+    if ipchksum(table) != header.table_checksum:
+        print "Bad table checksum"
+        return -1
+
+    for i in range(header.table_entries):
+        entry = CBTableEntry(addr)
+        if entry.tag == 0x11: # Forwarding entry
+            return parse_tables(CBTableForward(addr).forward, length)
+        elif entry.tag == 0x16: # Timestamps
+            process_timers(CBMemTab(addr).cbmem_tab)
+        elif entry.tag == 0x17: # CBMEM console
+            process_console(CBMemTab(addr).cbmem_tab)
+
+        addr += entry.size
+
+    return 0
+
+def main():
+    for base, length in (0x00000000, 0x1000), (0x000f0000, 0x1000):
+        if parse_tables(base, length):
+            break
+    else:
+        print "Didn't find the coreboot tables"
+        return 0
+
+if __name__ == "__main__":
+    sys.exit(main())



From gerrit at coreboot.org  Wed Mar  7 02:12:09 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:09 +0100
Subject: [coreboot] Patch set updated for coreboot: 1cfa4a3 Fix MB
	calculation in the reporting of the MTRR hole
References: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+0@gerrit.coreboot.org>
Message-ID: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763

-gerrit

commit 1cfa4a37189df5595e1f51b98340f2e016a11d29
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Jan 6 15:49:30 2012 -0800

    Fix MB calculation in the reporting of the MTRR hole
    
    Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8dccfef..5f5e02b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 
 	if (hole_sizek) {
 		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
-		       hole_startk, hole_startk + hole_sizek);
+		       hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
 		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
 			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
 			      address_bits, above4gb);



From gerrit at coreboot.org  Wed Mar  7 02:12:10 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:10 +0100
Subject: [coreboot] Patch set updated for coreboot: 9c36aa5 drop use of
	MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
References: <Idf875ddec417e627f1e72a6d834860e7fd324a50+0@gerrit.coreboot.org>
Message-ID: <Idf875ddec417e627f1e72a6d834860e7fd324a50+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760

-gerrit

commit 9c36aa5171f0a0810305ed71a781f9d78536907e
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Dec 15 09:24:40 2011 -0800

    drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
    
    Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/lapic_cpu_init.c |    6 ------
 src/cpu/x86/pae/Makefile.inc       |    2 +-
 2 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fc22ea4..99c3c4e 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -363,9 +363,7 @@ void secondary_cpu_init(void)
 {
 	atomic_inc(&active_cpus);
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_lock(&start_cpu_lock);
-  #endif
 #endif
 
 #ifdef __SSE3__
@@ -380,9 +378,7 @@ void secondary_cpu_init(void)
 #endif
 	cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_unlock(&start_cpu_lock);
-  #endif
 #endif
 
 	atomic_dec(&active_cpus);
@@ -419,9 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 				cpu->path.apic.apic_id);
 		}
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 		udelay(10);
-  #endif
 #endif
 	}
 
diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc
index 0ecec47..060720c 100644
--- a/src/cpu/x86/pae/Makefile.inc
+++ b/src/cpu/x86/pae/Makefile.inc
@@ -1 +1 @@
-ramstage-y += pgtbl.c
+ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c



From gerrit at coreboot.org  Wed Mar  7 02:12:11 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:11 +0100
Subject: [coreboot] Patch set updated for coreboot: 9059486 MTRR: add
	alternate allocation method for odd memory maps With >= 4GB
	memory installed we get a memory map split in the middle due
	to remap that has boundaries that are inconveniently aligned
	for MTRRs due to the various UMA regions.
References: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+0@gerrit.coreboot.org>
Message-ID: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761

-gerrit

commit 9059486ecb849c71626d41d8e4ef7a59d17b4b52
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 22 10:59:40 2011 -0800

    MTRR: add alternate allocation method for odd memory maps
    With >= 4GB memory installed we get a memory map split in the middle
    due to remap that has boundaries that are inconveniently aligned for
    MTRRs due to the various UMA regions.
    
    0000MB-2780MB  2780MB  RAM     (writeback)
    2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
    2782MB-2784MB     2MB  GFX GTT (uncached)
    2784MB-2816MB    32MB  GFX UMA (uncached)
    2816MB-4096MB  1280MB  EMPTY   (N/A)
    4096MB-5368MB  1272MB  RAM     (writeback)
    5368MB-5376MB     8MB  ME UMA  (uncached)
    
    The default MTRR allocation method of trying to cover everything
    with one MTRR and then carve out a single uncached region does
    not work for the GPU aperture which needs write-combining type,
    and it also has issues trying to cover the uneven boundaries
    in the avaiable variable MTRRs.
    
    My goal was to make a minimal set of changes and avoid modifying
    behavior on existing systems with an algorithm that is not always
    optimal for a typical memory layout.  So the flag 'above4gb=2'
    will change these allocation behaviors:
    
    1) Detect the number of available variable MTRRs rather than
    limiting to hardcoded value.  We need every last MTRR.
    
    2) Don't try to cover all RAM with one MTRR, instead let each
    RAM region get covered independently.
    
    3) Don't assume uma_memory_base is part of the last region
    and increase the size of that region.  In this case the UMA
    region is carved out from the lower memory region and it is
    already declared as part of the ram region.
    
    4) If a memory region can't be covered with MTRRs >= 16MB then
    instead make a larger region and trim it with uncached MTRRs.
    
    Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |   52 ++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 9015ad4..8dccfef 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x)
 #endif
 #define MTRRS        (BIOS_MTRRS + OS_MTRRS)
 
+static int total_mtrrs = MTRRS;
+static int bios_mtrrs = BIOS_MTRRS;
+
+static void detect_var_mtrrs(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MTRRcap_MSR);
+
+	total_mtrrs = msr.lo & 0xff;
+	bios_mtrrs = total_mtrrs - 2;
+}
 
 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
 {
@@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
 	unsigned long next_range_startk, unsigned char type,
 	unsigned int address_bits, unsigned int above4gb)
 {
+	unsigned long hole_startk = 0, hole_sizek = 0;
+
 	if (!range_sizek) {
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
@@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (reg >= BIOS_MTRRS) {
+	if (reg >= bios_mtrrs) {
 		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
@@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+		/*
+		 * If this range is not divisible by 16MB then instead
+		 * make a larger range and carve out an uncached hole.
+		 */
+		hole_startk = range_startk + range_sizek;
+		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		range_sizek += hole_sizek;
+	}
+
 	while(range_sizek) {
 		unsigned long max_align, align;
 		unsigned long sizek;
@@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg,
 			set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
-		if (reg >= BIOS_MTRRS) {
+		if (reg >= bios_mtrrs) {
 			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
+
+	if (hole_sizek) {
+		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
+		       hole_startk, hole_startk + hole_sizek);
+		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
+			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
+			      address_bits, above4gb);
+	}
+
 	return reg;
 }
 
@@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 {
 	struct var_mtrr_state *state = gp;
 	unsigned long basek, sizek;
-	if (state->reg >= BIOS_MTRRS)
+	if (state->reg >= bios_mtrrs)
 		return;
 	basek = resk(res->base);
 	sizek = resk(res->size);
@@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
 #if CONFIG_VAR_MTRR_HOLE
-		if (state->hole_sizek == 0) {
+		if (state->hole_sizek == 0 && state->above4gb != 2) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
@@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	var_state.address_bits = address_bits;
 	var_state.above4gb = above4gb;
 
+	/* Detect number of variable MTRRs */
+	if (above4gb == 2)
+		detect_var_mtrrs();
+
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
@@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	} else {
 #if CONFIG_VAR_MTRR_HOLE
 		// Increase the base range and set up UMA as an UC hole instead
-		var_state.range_sizek += (uma_memory_size >> 10);
+		if (above4gb != 2)
+			var_state.range_sizek += (uma_memory_size >> 10);
 
 		var_state.hole_startk = (uma_memory_base >> 10);
 		var_state.hole_sizek = (uma_memory_size >> 10);
@@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
 	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
-	while(var_state.reg < MTRRS) {
+	while(var_state.reg < total_mtrrs) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
 
@@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	 * complete ROM now that we actually have RAM.
 	 */
 	if (boot_cpu() && (acpi_slp_type != 3)) {
-		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+		set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024,
 			MTRR_TYPE_WRPROT, address_bits);
 	}
 #endif



From gerrit at coreboot.org  Wed Mar  7 02:12:13 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:13 +0100
Subject: [coreboot] Patch set updated for coreboot: d92bae9 Add Kconfig
	options to enable TSEG and set a size
References: <I1432569ece4371d6e12c997e90d66c175fa54c5c+0@gerrit.coreboot.org>
Message-ID: <I1432569ece4371d6e12c997e90d66c175fa54c5c+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766

-gerrit

commit d92bae997cea9dcba57f7d5416ef8feddb55dd7c
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:11:25 2012 -0800

    Add Kconfig options to enable TSEG and set a size
    
    Future CPUs will require TSEG use for SMM
    
    Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/Kconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index fdbd527..2033a0a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -42,3 +42,11 @@ config LOGICAL_CPUS
 config CACHE_ROM
 	bool
 	default n
+
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0



From gerrit at coreboot.org  Wed Mar  7 02:12:14 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:14 +0100
Subject: [coreboot] Patch set updated for coreboot: 15113e2 correctly mark
	code segments as code in SELF
References: <I82eaad23f08c02f4ed75744affa8835255cf5c17+0@gerrit.coreboot.org>
Message-ID: <I82eaad23f08c02f4ed75744affa8835255cf5c17+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/767

-gerrit

commit 15113e2ebca3657600bd9f682eafae3ba3f26575
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 12:40:14 2012 -0800

    correctly mark code segments as code in SELF
    
    In bios_log, find that the first segment of the payload is shown
    as code rather than data.
    
    Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
    Sample:
           Got a payload
           Loading segment from rom address 0xfff29378
             code (compression=1)
           ...
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbfstool/cbfs-mkpayload.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index ff6479d..e4ef5c8 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -161,7 +161,10 @@ int parse_elf_to_payload(unsigned char *input, unsigned char **output,
 			continue;
 		}
 
-		segs[segments].type = PAYLOAD_SEGMENT_DATA;
+		if (phdr[i].p_flags & PF_X)
+			segs[segments].type = PAYLOAD_SEGMENT_CODE;
+		else
+			segs[segments].type = PAYLOAD_SEGMENT_DATA;
 		segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr);
 		segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz);
 		segs[segments].compression = htonl(algo);



From gerrit at coreboot.org  Wed Mar  7 02:12:15 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:15 +0100
Subject: [coreboot] Patch set updated for coreboot: 0abb86d Make cpuid
	functions usable when compiled with PIC
References: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+0@gerrit.coreboot.org>
Message-ID: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764

-gerrit

commit 0abb86d60d69218872391e96a0587ed145f0ffdc
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:00:30 2012 -0800

    Make cpuid functions usable when compiled with PIC
    
    This avoids using EBX and instead uses EDI where possible,
    and ESI when necessary to get the EBX value out.
    
    This allows me to enable -fpic for SMM TSEG code.
    
    Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/include/arch/cpu.h |   57 ++++++++++++++++++++++++++++++--------
 1 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 85357d7..508b7d6 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op)
 {
 	struct cpuid_result result;
 	asm volatile(
-		"cpuid"
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
 		: "=a" (result.eax),
-		  "=b" (result.ebx),
+		  "=S" (result.ebx),
 		  "=c" (result.ecx),
 		  "=d" (result.edx)
-		: "0" (op));
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
 	return result;
 }
 
@@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op)
 {
 	unsigned int eax;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax)
 		: "0" (op)
-		: "ebx", "ecx", "edx");
+		: "ecx", "edx", "edi");
 	return eax;
 }
 
@@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op)
 {
 	unsigned int eax, ebx;
 
-	__asm__("cpuid"
-		: "=a" (eax), "=b" (ebx)
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		"mov %%edi, %%esi;"
+		: "=a" (eax), "=S" (ebx)
 		: "0" (op)
-		: "ecx", "edx" );
+		: "ecx", "edx", "edi");
 	return ebx;
 }
 
@@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op)
 {
 	unsigned int eax, ecx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=c" (ecx)
 		: "0" (op)
-		: "ebx", "edx" );
+		: "edx", "edi");
 	return ecx;
 }
 
@@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op)
 {
 	unsigned int eax, edx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=d" (edx)
 		: "0" (op)
-		: "ebx", "ecx");
+		: "ecx", "edi");
 	return edx;
 }
 



From gerrit at coreboot.org  Wed Mar  7 02:12:16 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 0077bb7 Make MTRR min
	hole alignment 64MB
References: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+0@gerrit.coreboot.org>
Message-ID: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765

-gerrit

commit 0077bb72e00748699551856abef8645ca1652a67
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:05:18 2012 -0800

    Make MTRR min hole alignment 64MB
    
    This affects the algorithm when determining when to
    transform a range into a larger range with a hole.
    
    It is needed when for when I switch on an 8MB TSEG
    and cause the memory maps to go crazy.
    
    Also add header defines for the SMRR.
    
    Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c    |    9 ++++++---
 src/include/cpu/x86/mtrr.h |    3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02b..ed7d93b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
 		/*
-		 * If this range is not divisible by 16MB then instead
+		 * If this range is not divisible then instead
 		 * make a larger range and carve out an uncached hole.
 		 */
 		hole_startk = range_startk + range_sizek;
-		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
 		range_sizek += hole_sizek;
 	}
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7..8b5cc28 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 



From gerrit at coreboot.org  Wed Mar  7 02:12:22 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:22 +0100
Subject: [coreboot] Patch set updated for coreboot: c9ea9ae labels should
	start at the beginning of the line
References: <I60d0fa90656f85ecb8acc357fe6518baa773505b+0@gerrit.coreboot.org>
Message-ID: <I60d0fa90656f85ecb8acc357fe6518baa773505b+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/754

-gerrit

commit c9ea9aed220ad8d0580040d1a29353c9b1566349
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:52:30 2011 -0800

    labels should start at the beginning of the line
    
    cosmetical fix
    
    Change-Id: I60d0fa90656f85ecb8acc357fe6518baa773505b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/secondary.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 5c1e760..dc00b08 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -47,7 +47,7 @@ _secondary_start:
 1:	hlt
 	jmp	1b
 
-	gdtaddr:
+gdtaddr:
 	.word   gdt_limit	/* the table limit */
 	.long   gdt             /* we know the offset */
 



From gerrit at coreboot.org  Wed Mar  7 02:12:29 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:29 +0100
Subject: [coreboot] Patch set updated for coreboot: d202b26 use movsl for
	copying resume memory back
References: <Ibab0b478873912d67bf1f07743f628586353368a+0@gerrit.coreboot.org>
Message-ID: <Ibab0b478873912d67bf1f07743f628586353368a+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755

-gerrit

commit d202b262c5d0bbc6bb22a9a7550b7f1b285c22f2
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:03:38 2011 -0800

    use movsl for copying resume memory back
    
    It's not significantly faster, but easier to read and smaller.
    
    Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/wakeup.S |   20 ++++----------------
 1 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..f12b176 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
 	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)



From gerrit at coreboot.org  Wed Mar  7 02:12:31 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:31 +0100
Subject: [coreboot] Patch set updated for coreboot: d9f5a72 Fix warnings in
	coreboot utilities.
References: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+0@gerrit.coreboot.org>
Message-ID: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752

-gerrit

commit d9f5a7240b4f694d94afd64924f167d78a6f6b16
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Nov 14 12:40:34 2011 -0800

    Fix warnings in coreboot utilities.
    
    Fix some poor programming practice (breaks of strict aliasing as well as not
    checking the return value of read)
    
    Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/inteltool/cpu.c           |    6 ++++--
 util/inteltool/inteltool.c     |    4 +++-
 util/nvramtool/cli/nvramtool.c |    3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 20748bd..3bffa4e 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -67,8 +67,10 @@ msr_t rdmsr(int addr)
 	}
 
 	if (read(fd_msr, buf, 8) == 8) {
-		msr.lo = *(uint32_t *)buf;
-		msr.hi = *(uint32_t *)(buf + 4);
+		msr.lo = buf[0] | (buf[1] << 8) |
+			 (buf[2] << 16) | (buf[3] << 24);
+		msr.hi = buf[4] | (buf[5] << 8) |
+			 (buf[6] << 16) | (buf[7] << 24);
 
 		return msr;
 	}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6b99605..e5c2b86 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -21,6 +21,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <inttypes.h>
 #include <getopt.h>
 #include <fcntl.h>
 #include <sys/mman.h>
@@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len)
 		    fd_mem, (off_t) phys_addr);
 
 	if (virt_addr == MAP_FAILED) {
-		printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len);
+		printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
+			phys_addr, len);
 		return NULL;
 	}
 
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index 11a1a70..20097b8 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -143,7 +143,8 @@ int main(int argc, char *argv[])
 
 		if (fd_stat.st_size < 128) {
 			lseek(fd, 127, SEEK_SET);
-			write(fd, "\0", 1);
+			if (write(fd, "\0", 1) != 1)
+				fprintf(stderr, "Write failed.\n");
 			fsync(fd);
 		}
 



From gerrit at coreboot.org  Wed Mar  7 02:12:33 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:33 +0100
Subject: [coreboot] Patch set updated for coreboot: 93c0132 vga_io.c is not
	needed unless CONFIG_VGA is set
References: <I7b406251a2f3830748140a111f76f2792fe923ed+0@gerrit.coreboot.org>
Message-ID: <I7b406251a2f3830748140a111f76f2792fe923ed+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753

-gerrit

commit 93c01328938eafd9ef98414da4d709e75af5b6be
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 11:13:36 2011 -0800

    vga_io.c is not needed unless CONFIG_VGA is set
    
    hence disable it.
    
    Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/vga/Makefile.inc |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc
index 0ca7896..d4b726a 100644
--- a/src/pc80/vga/Makefile.inc
+++ b/src/pc80/vga/Makefile.inc
@@ -1,4 +1,4 @@
-ramstage-y += vga_io.c
+ramstage-$(CONFIG_VGA) += vga_io.c
 ramstage-$(CONFIG_VGA) += vga_palette.c
 ramstage-$(CONFIG_VGA) += vga_font_8x16.c
 ramstage-$(CONFIG_VGA) += vga.c



From gerrit at coreboot.org  Wed Mar  7 02:12:34 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:34 +0100
Subject: [coreboot] Patch set updated for coreboot: 38c5140 Make PCI CONF2
	support a compile time option.
References: <I17df94a8a77b9338fde10a6b114b44d393776e66+0@gerrit.coreboot.org>
Message-ID: <I17df94a8a77b9338fde10a6b114b44d393776e66+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758

-gerrit

commit 38c51408f7c7568f164b93988dd98fc2fbe86e23
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:05:31 2011 -0800

    Make PCI CONF2 support a compile time option.
    
    It's not used on any board supported by coreboot but has been
    detected at run time since ages. No new boards (since 2000?)
    are using the CONF2 method, so it is unlikely we ever have to
    turn this on for a board.
    
    Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig            |    4 ++++
 src/arch/x86/lib/Makefile.inc   |    4 +---
 src/arch/x86/lib/pci_ops_auto.c |    9 ++++++++-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 078ae95..bc01c9c 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -96,4 +96,8 @@ config LITTLE_ENDIAN
 	bool
 	default !BIG_ENDIAN
 
+config PCI_CONF2
+	bool
+	default n
+
 endmenu
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3f4dc95..96fb9b0 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -1,10 +1,8 @@
 ramstage-y += c_start.S
 ramstage-y += cpu.c
 ramstage-y += pci_ops_conf1.c
-ramstage-y += pci_ops_conf2.c
-
+ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
 ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
index 92eedd3..58e098b 100644
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ b/src/arch/x86/lib/pci_ops_auto.c
@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#if CONFIG_PCI_CONF2
 /*
  * Before we decide to use direct hardware access mechanisms, we try to do some
  * trivial checks to ensure it at least _seems_ to be working -- we just test
@@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
 	return 0;
 }
 
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
+static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
 
 static const struct pci_bus_operations *pci_check_direct(void)
 {
@@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void)
 		pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
 	return pci_bus_fallback_ops;
 }
+#else
+const struct pci_bus_operations *pci_remember_direct(void)
+{
+	return &pci_cf8_conf1;
+}
+#endif
 
 /** Set the method to be used for PCI, type I or type II
  */



From gerrit at coreboot.org  Wed Mar  7 02:12:35 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:35 +0100
Subject: [coreboot] Patch set updated for coreboot: 4a0a79e Fix romcc to
	compile cleanly
References: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+0@gerrit.coreboot.org>
Message-ID: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759

-gerrit

commit 4a0a79ea8bf263a724fd545fc4205adc26fba0ab
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Dec 6 22:14:57 2011 +0000

    Fix romcc to compile cleanly
    
    There have been many unused variable assignments in the romcc source
    file. They cause multiple warning messages during build process which
    in turn make it harder to see the actual error message, when they are
    present.
    
    The fix is to remove dead code and to add -Werror to romcc compilation
    to avoid issues like this creeping in in the future.
    
    Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/romcc/Makefile |    2 +-
 util/romcc/romcc.c  |    3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/util/romcc/Makefile b/util/romcc/Makefile
index 6543fbb..8242eb5 100644
--- a/util/romcc/Makefile
+++ b/util/romcc/Makefile
@@ -1,7 +1,7 @@
 # Move the configuration defines to makefile.conf
 CC=gcc
 CPPFLAGS=
-CFLAGS= -g -Wall $(CPPFLAGS)
+CFLAGS= -g -Wall -Werror $(CPPFLAGS)
 CPROF_FLAGS=-pg -fprofile-arcs
 
 all: romcc test
diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c
index c7ef223..7eee439 100644
--- a/util/romcc/romcc.c
+++ b/util/romcc/romcc.c
@@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state)
 {
 	struct triple *ins, *next, *first;
 #if DEBUG_DECOMPOSE_HIRES
-	FILE *fp;
-	fp = state->dbgout;
+	FILE *fp = state->dbgout;
 #endif
 	first = state->first;
 	ins = first;



From gerrit at coreboot.org  Wed Mar  7 02:12:37 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:37 +0100
Subject: [coreboot] Patch set updated for coreboot: c146b6e Don't
	unconditionally add support for cardbus and pci-x devices
References: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+0@gerrit.coreboot.org>
Message-ID: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756

-gerrit

commit c146b6e2d53b9444405985b50ed5834edeb42169
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 30 12:45:14 2011 -0800

    Don't unconditionally add support for cardbus and pci-x devices
    
    It's still on by default.
    
    Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Makefile.inc |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
index 86b4d21..9ffc0bb 100644
--- a/src/devices/Makefile.inc
+++ b/src/devices/Makefile.inc
@@ -3,10 +3,10 @@ ramstage-y += root_device.c
 ramstage-y += device_util.c
 ramstage-y += pci_device.c
 ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
-ramstage-y += pcix_device.c
+ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
 ramstage-y += pciexp_device.c
-ramstage-y += agp_device.c
-ramstage-y += cardbus_device.c
+ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c
+ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
 ramstage-y += pnp_device.c
 ramstage-y += pci_ops.c
 ramstage-y += smbus_ops.c



From gerrit at coreboot.org  Wed Mar  7 02:12:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:39 +0100
Subject: [coreboot] Patch set updated for coreboot: d4cd739 Add DEBUG_TPM
	option to Debugging menu
References: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+0@gerrit.coreboot.org>
Message-ID: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757

-gerrit

commit d4cd73928fc73e0fe9138d4d9094d2e120dce707
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:50:54 2011 -0800

    Add DEBUG_TPM option to Debugging menu
    
    instead of having to edit the source code of tpm.c
    
    Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig    |    7 +++++++
 src/pc80/tpm.c |    9 +--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 26e6dde..41c5dbf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO
 
 	  If unsure, say N.
 
+config DEBUG_TPM
+	bool "Output verbose TPM debug messages"
+	default n
+	depends on TPM
+	help
+	  This option enables additional TPM related debug messages.
+
 config LLSHELL
 	bool "Built-in low-level shell"
 	default n
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 8e94303..17e1ed7 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -27,7 +27,6 @@
  * Infineon slb9635), so this driver provides access to locality 0 only.
  */
 
-/* #define DEBUG */
 #include <stdlib.h>
 #include <string.h>
 #include <delay.h>
@@ -37,17 +36,11 @@
 #include <pc80/tpm.h>
 #include <cpu/x86/car.h>
 
-#ifdef DEBUG
-#define TPM_DEBUG_ON	1
-#else
-#define TPM_DEBUG_ON	0
-#endif
-
 #define PREFIX "lpc_tpm: "
 
 /* coreboot wrapper for TPM driver (start) */
 #define	TPM_DEBUG(fmt, args...)		\
-	if (TPM_DEBUG_ON) {		\
+	if (CONFIG_DEBUG_TPM) {		\
 		printk(BIOS_DEBUG, PREFIX);		\
 		printk(BIOS_DEBUG, fmt , ##args);	\
 	}



From gerrit at coreboot.org  Wed Mar  7 02:12:40 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:40 +0100
Subject: [coreboot] Patch set updated for coreboot: adafaf4 Add timestamp
	collecting to coreboot.
References: <I7ed9f5c400bc5432f228348b41fd19a67c36d533+0@gerrit.coreboot.org>
Message-ID: <I7ed9f5c400bc5432f228348b41fd19a67c36d533+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/713

-gerrit

commit adafaf4f8aa27b66253ce2e281ee2f6fbde144df
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 21 16:12:39 2011 -0700

    Add timestamp collecting to coreboot.
    
    This patch adds code to initialize the time stamp collection
    facility in coreboot. It adds a table in the CBMEM section, which
    provides the base timer reading value (all other readings are
    offsets of this one) and an array of timestamp id/timestamp value
    pairs.
    
    Just two values are being added now, this will have to be used
    more extensively and also integrated into payloads to provide more
    comprehensive boot process time measurements.
    
    Also, since the CBMEM area could already contain a section (from the
    previous run, before reset), when processing a section addition
    request we should check if a section already exists and return its
    address, if so.
    
    Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h     |    1 +
 src/include/timestamp.h |   46 +++++++++++++++++++++++++++++
 src/lib/Makefile.inc    |    2 +
 src/lib/cbmem.c         |   17 +++++++++++
 src/lib/timestamp.c     |   74 +++++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 140 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a681c36..c3f10ef 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -41,6 +41,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_RESUME		0x5245534d
 #define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_TIMESTAMP	0x54494d45
 #define CBMEM_ID_NONE		0x00000000
 
 int cbmem_initialize(void);
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
new file mode 100644
index 0000000..cfa06e2
--- /dev/null
+++ b/src/include/timestamp.h
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef __TIMESTAMP_H__
+#define __TIMESTAMP_H__
+
+#include <cpu/x86/tsc.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint32_t	max_entries;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_BEFORE_INITRAM = 1,
+	TS_AFTER_INITRAM = 2,
+};
+
+void timestamp_init(tsc_t base);
+void timestamp_add(enum timestamp_id id, tsc_t ts_time);
+void timestamp_add_now(enum timestamp_id id);
+
+#endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index e0e5e75..db640dc 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -14,6 +14,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-y += memset.c
 ramstage-y += memchr.c
@@ -36,6 +37,7 @@ ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index f5c3d3a..6597840 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -118,6 +118,22 @@ void *cbmem_add(u32 id, u64 size)
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
+	void *p;
+
+	/*
+	 * This could be a restart, check if the section is there already. It
+	 * is remotely possible that the dram contents persisted over the
+	 * bootloader upgrade AND the same section now needs more room, but
+	 * this is quite a remote possibility and it is ignored here.
+	 */
+	p = cbmem_find(id);
+	if (p) {
+		printk(BIOS_NOTICE,
+		       "CBMEM section %x: using existing location at %p.\n",
+		       id, p);
+		return p;
+	}
+
 	cbmem_toc = get_cbmem_toc();
 
 	if (cbmem_toc == NULL) {
@@ -240,6 +256,7 @@ void cbmem_list(void)
 		case CBMEM_ID_MPTABLE:	 printk(BIOS_DEBUG, "SMP TABLE  "); break;
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
 		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
+		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
new file mode 100644
index 0000000..bbb8197d
--- /dev/null
+++ b/src/lib/timestamp.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <timestamp.h>
+
+#define MAX_TIMESTAMPS 30
+
+#ifndef __PRE_RAM__
+static struct timestamp_table* ts_table;
+#endif
+
+static uint64_t tsc_to_uint64(tsc_t tstamp)
+{
+	return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
+}
+
+void timestamp_init(tsc_t base)
+{
+	struct timestamp_table* tst;
+
+	tst = cbmem_add(CBMEM_ID_TIMESTAMP,
+			sizeof(struct timestamp_table) +
+			MAX_TIMESTAMPS * sizeof(struct timestamp_entry));
+
+	if (!tst) {
+		printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n");
+		return;
+	}
+
+	tst->base_time = tsc_to_uint64(base);
+	tst->max_entries = MAX_TIMESTAMPS;
+	tst->num_entries = 0;
+}
+
+void timestamp_add(enum timestamp_id id, tsc_t ts_time)
+{
+	struct timestamp_entry *tse;
+#ifdef __PRE_RAM__
+	struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#else
+	if (!ts_table)
+		ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#endif
+	if (!ts_table || (ts_table->num_entries == ts_table->max_entries))
+		return;
+
+	tse = &ts_table->entries[ts_table->num_entries++];
+	tse->entry_id = id;
+	tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time;
+}
+
+void timestamp_add_now(enum timestamp_id id)
+{
+	timestamp_add(id, rdtsc());
+}



From gerrit at coreboot.org  Wed Mar  7 02:12:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:41 +0100
Subject: [coreboot] Patch set updated for coreboot: aea088a Add a config
	flag to enable time stamp collection.
References: <Idbebcaf298238f31a73e9eb4a9af7b03e857bc74+0@gerrit.coreboot.org>
Message-ID: <Idbebcaf298238f31a73e9eb4a9af7b03e857bc74+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/712

-gerrit

commit aea088a31b2b64a37a1f3a8126f3d1dd956c4442
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 21 14:46:43 2011 -0700

    Add a config flag to enable time stamp collection.
    
    Add a new flag, make it dependent on EARLY_CBMEM_INIT
    
    Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/Kconfig |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 544b61b..573868f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE
   help
     Include in CBFS the coreboot config file that was used to compile the ROM image
 
+config FDT_FILE_NAME
+	depends on ADD_FDT
+	string "Name of the CBFS file containing the compiled FDT"
+	default "u-boot.dtb"
+	help
+	  Name of the CBFS file containing the binary representation of the
+	  device tree to be optionally modified and passed to the payload.
+
 config EARLY_CBMEM_INIT
 	bool "Initialize CBMEM while in ROM stage"
 	default n
@@ -120,6 +128,13 @@ config EARLY_CBMEM_INIT
 	  stage. This could be useful when the rom stage wants to communicate
 	  some, for instance, execution timestamps.
 
+config COLLECT_TIMESTAMPS
+	bool "Create a table of timestamps collected during boot"
+	depends on EARLY_CBMEM_INIT
+	help
+	  Make coreboot create a table of timer id/timer value pairs to
+	  allow measuring time spent at different phases of the boot
+	  process.
 endmenu
 
 source src/mainboard/Kconfig



From gerrit at coreboot.org  Wed Mar  7 02:12:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:41 +0100
Subject: [coreboot] Patch set updated for coreboot: d64e652 Don't run VGA
	option ROMs on S3 resume.
References: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+0@gerrit.coreboot.org>
Message-ID: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/715

-gerrit

commit d64e6524e33baf0b5d1c49d939efab5d1da31611
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Sep 23 10:33:58 2011 -0700

    Don't run VGA option ROMs on S3 resume.
    
    This will save us a few 100 ms on resume.
    
    Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig      |    7 +++++++
 src/devices/pci_device.c |   11 +++++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 9e5ea6e..572addc 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -33,6 +33,13 @@ config VGA_ROM_RUN
 	  Execute VGA option ROMs, if found. This is required to enable
 	  PCI/AGP/PCI-E video cards.
 
+config S3_VGA_ROM_RUN
+	bool "Re-run VGA option ROMs on S3 resume"
+	default y
+	depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+	help
+	  Execute VGA option ROMs when coming out of an S3 resume.
+
 config PCI_ROM_RUN
 	bool "Run non-VGA option ROMs"
 	default y
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..1f36679 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -51,6 +51,9 @@
 #if CONFIG_PC80_SYSTEM == 1
 #include <pc80/i8259.h>
 #endif
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+#include <arch/acpi.h>
+#endif
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
@@ -672,6 +675,14 @@ void pci_dev_init(struct device *dev)
 	if (ram == NULL)
 		return;
 
+#if !CONFIG_S3_VGA_ROM_RUN
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if ((acpi_slp_type == 3) &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return;
+#endif
 	run_bios(dev, (unsigned long)ram);
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 }



From gerrit at coreboot.org  Wed Mar  7 02:12:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:42 +0100
Subject: [coreboot] Patch set updated for coreboot: fb11f95 Include
	arch/acpi.h instead of manually adding acpi_slp_type.
References: <Ia5eb420364c15ab5a764bc328bbd201ca9cb7837+0@gerrit.coreboot.org>
Message-ID: <Ia5eb420364c15ab5a764bc328bbd201ca9cb7837+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/714

-gerrit

commit fb11f95b8b0edc2fd459d16f057b04c31c2dbee4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Sep 23 10:24:49 2011 -0700

    Include arch/acpi.h instead of manually adding acpi_slp_type.
    
    acpi_slp_type is defined in arch/acpi.h, so let's use that instead
    of manually spreading extern u8 acpi_slp_type throughout the code.
    
    Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/lib/cbmem.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 6597840..f800b04 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -21,6 +21,9 @@
 #include <string.h>
 #include <cbmem.h>
 #include <console/console.h>
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+#include <arch/acpi.h>
+#endif
 
 // The CBMEM TOC reserves 512 bytes to keep
 // the other entries somewhat aligned.
@@ -199,10 +202,6 @@ void *cbmem_find(u32 id)
 	return (void *)NULL;
 }
 
-#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
-extern u8 acpi_slp_type;
-#endif
-
 #if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
 /* Returns True if it was not intialized before. */
 int cbmem_initialize(void)



From gerrit at coreboot.org  Wed Mar  7 02:12:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:42 +0100
Subject: [coreboot] Patch set updated for coreboot: 39cb658 Add cmos helper
	functions for reading/writing a dword
References: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+0@gerrit.coreboot.org>
Message-ID: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/717

-gerrit

commit 39cb658135000259b97ed6dde6a3fe8cb96ee0ce
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 26 13:24:40 2011 -0700

    Add cmos helper functions for reading/writing a dword
    
    These get used later for saving/restoring the MRC scrambler
    seed values on each boot.
    
    Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/include/pc80/mc146818rtc.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 3e5a61a..24dac2c 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -104,6 +104,22 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
 	outb(addr, RTC_BASE_PORT + offs + 0);
 	outb(val, RTC_BASE_PORT + offs + 1);
 }
+
+static inline u32 cmos_read32(u8 offset)
+{
+	u32 value = 0;
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		value |= cmos_read(offset + i) << (i << 3);
+	return value;
+}
+
+static inline void cmos_write32(u8 offset, u32 value)
+{
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		cmos_write((value >> (i << 3)) & 0xff, offset + i);
+}
 #endif
 
 #if !defined(__ROMCC__)



From gerrit at coreboot.org  Wed Mar  7 02:12:44 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:44 +0100
Subject: [coreboot] Patch set updated for coreboot: ca767f8 Add timestamp
	table pointer to the coreboot table.
References: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+0@gerrit.coreboot.org>
Message-ID: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/716

-gerrit

commit ca767f8729c52806a64419af18515480fa9e2c87
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 23 09:56:11 2011 -0700

    Add timestamp table pointer to the coreboot table.
    
    This change exports the timestamp table pointer through coreboot
    table to make it possible for u-boot to add timestamps to the
    table.
    
    Inclusion of cbmem.h allows to drop external declarations in
    coreboot_table.c.
    
    Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   25 +++++++++++++++++++++----
 src/include/boot/coreboot_tables.h |    8 ++++++++
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index b0dcc9e..f189e76 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -30,6 +30,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
 #endif
@@ -174,6 +175,23 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
+#if CONFIG_COLLECT_TIMESTAMPS
+static void lb_tsamp(struct lb_header *header)
+{
+	struct lb_tstamp *tstamp;
+	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+
+	if (!tstamp_table)
+		return;
+
+	tstamp = (struct lb_tstamp *)lb_new_record(header);
+	tstamp->tag = LB_TAG_TIMESTAMPS;
+	tstamp->size = sizeof(*tstamp);
+	tstamp->tstamp_tab = tstamp_table;
+
+}
+#endif
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -513,10 +531,6 @@ static void add_lb_reserved(struct lb_memory *mem)
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
@@ -619,6 +633,9 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	lb_tsamp(head);
+#endif
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 45ba3af..46d6489 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -195,6 +195,14 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_TIMESTAMPS	0x0016
+struct lb_tstamp {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*tstamp_tab;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */



From gerrit at coreboot.org  Wed Mar  7 02:12:46 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:46 +0100
Subject: [coreboot] Patch set updated for coreboot: ffbfbae CBMEM CONSOLE:
	Add CBMEM console driver implementation.
References: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+0@gerrit.coreboot.org>
Message-ID: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/719

-gerrit

commit ffbfbae12081b20d7818685f3490a9b2fd70aaeb
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Sep 29 17:27:15 2011 -0700

    CBMEM CONSOLE: Add CBMEM console driver implementation.
    
    The CBMEM console driver saves console output in a CBMEM area, which
    then is made available to Linux applications for perusing.
    
    There are some system limitations which need to be worked around
    to achieve this goal:
    
    - some console traffic is generated before DRAM is initialized,
      leave alone CBMEM initialized.
    
    - after the RAM based stage starts, a lot of traffic is generated
      before CBMEM is initialized.
    
    As a result, the console log lives in three different places -
    the bottom of the cache as RAM space, the CBMEM buffer (where it
    is expected to be) and a static buffer used early in the RAM
    stage.
    
    When execution starts (in the cache as RAM mode), the console
    buffer is allocated at the bottom of the cache as RAM memory
    address range. Once DRAM is initialized, the CBMEM structure is
    initialized, and then the console buffer contents are copied from
    the bottom of the cache as RAM space into the CBMEM area right
    before the cache as RAM mode is disabled. The
    src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
    copying.
    
    At this point the cache as RAM memory is about to be disabled,
    but the ROM stage is still going generating console output. To
    make sure this output is not lost, cbmemc_reinit() saves the new
    buffer address at a fixed location (0x600 was chosen for this),
    and the actual "printing" function checks to see if the RAM is
    already initialized (the stack is in RAM), and if so, gets the
    console buffer pointer from this location instead of using the
    cache as RAM address.
    
    When the RAM stage starts, a static buffer is used to store the
    console output, as the CBMEM buffer location is not known. Then,
    when CBMEM is reinitialized, cbmemc_reinit() again takes care of
    the copying.
    
    In case the allocated buffers are not large enough, the excessive
    data is dropped, and the copying routine adds some text to the
    output buffer to indicate that there has been data lost and how
    many characters were dropped.
    
    Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/cbmem_console.c         |   35 ++++++
 src/include/console/cbmem_console.h |   26 +++++
 src/include/console/console.h       |    3 +
 src/lib/cbmem_console.c             |  195 +++++++++++++++++++++++++++++++++++
 4 files changed, 259 insertions(+), 0 deletions(-)

diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c
new file mode 100644
index 0000000..2c43f5c
--- /dev/null
+++ b/src/console/cbmem_console.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+
+static void cbmemc_init_(void)
+{
+	cbmemc_init();
+}
+
+static void cbmemc_tx_byte_(unsigned char data)
+{
+	cbmemc_tx_byte(data);
+}
+
+static const struct console_driver cbmem_console __console = {
+	.init     = cbmemc_init_,
+	.tx_byte  = cbmemc_tx_byte_,
+};
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
new file mode 100644
index 0000000..37ea4d8
--- /dev/null
+++ b/src/include/console/cbmem_console.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+#ifndef _CONSOLE_CBMEM_CONSOLE_H_
+#define _CONSOLE_CBMEM_CONSOLE_H_
+
+void cbmemc_init(void);
+void cbmemc_reinit(void);
+void cbmemc_tx_byte(unsigned char data);
+
+#endif
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 54c825c..56e202d 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -33,6 +33,9 @@
 #if CONFIG_CONSOLE_NE2K
 #include <console/ne2k.h>
 #endif
+#if CONFIG_CONSOLE_CBMEM
+#include <console/cbmem_console.h>
+#endif
 
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
new file mode 100644
index 0000000..b58de48
--- /dev/null
+++ b/src/lib/cbmem_console.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <string.h>
+
+/*
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * whith buffer_body covering the extent of the memory. Once the buffer is
+ * full, the cursor keeps going but the data is dropped on the floor. This
+ * allows to tell how much data was lost in the process.
+ */
+struct cbmem_console {
+	u32 buffer_size;
+	u32 buffer_cursor;
+	u8  buffer_body[0];
+}  __attribute__ ((__packed__));
+
+#ifdef __PRE_RAM__
+/*
+ * While running from ROM, before DRAM is initialized, some area in cache as
+ * ram space is used for the console buffer storage. The size and location of
+ * the area are defined in the config.
+ */
+#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+/*
+ * Once DRAM is initialized and the cache as ram mode is disabled, while still
+ * running from ROM, the console buffer in the cache as RAM area becomes
+ * unavailable.
+ *
+ * By this time the console log buffer is already available in
+ * CBMEM. The location at 0x600 is used as the redirect pointer allowing to
+ * find out where the actual console log buffer is.
+ */
+#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600))
+#else
+
+/*
+ * When running from RAM, a lot of console output is generated before CBMEM is
+ * reinitialized. This static buffer is used to store that output temporarily,
+ * to be concatenated with the CBMEM console buffer contents accumulated
+ * during the ROM stage, once CBMEM becomes avaiklable at RAM stage.
+ */
+static u8 static_console[40000];
+static struct cbmem_console *cbmem_console_p;
+#endif
+
+void cbmemc_init(void)
+{
+#ifdef __PRE_RAM__
+	cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+#else
+	/*
+	 * Initializing before CBMEM is available, use static buffer to store
+	 * the log.
+	 */
+	cbmem_console_p = (struct cbmem_console *) static_console;
+	cbmem_console_p->buffer_size = sizeof(static_console) -
+		sizeof(struct cbmem_console);
+#endif
+	cbmem_console_p->buffer_cursor = 0;
+}
+
+void cbmemc_tx_byte(unsigned char data)
+{
+	struct cbmem_console *cbm_cons_p = cbmem_console_p;
+	u32 cursor;
+#ifdef __PRE_RAM__
+	/*
+	 * This check allows to tell if the cache as RAM mode has been exited
+	 * or not. If it has been exited, the real memory is being used
+	 * (resulting in the variable on the stack located below
+	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
+	 * actual console buffer is.
+	 */
+	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
+#endif
+	if (!cbm_cons_p)
+		return;
+
+	cursor = cbm_cons_p->buffer_cursor++;
+	if (cursor < cbm_cons_p->buffer_size)
+		cbm_cons_p->buffer_body[cursor] = data;
+}
+
+/*
+ * Copy the current console buffer (either from the cache as RAM area, or from
+ * the static buffer, pointed at by cbmem_console_p) into the CBMEM console
+ * buffer space (pointed at by new_cons_p), concatenating the copied data with
+ * the CBMEM console buffer contents.
+ *
+ * If there is overflow - add to the destination area a string, reporting the
+ * overflow and the number of dropped charactes.
+ */
+static void copy_console_buffer(struct cbmem_console *new_cons_p)
+{
+	u32 copy_size;
+	u32 cursor = new_cons_p->buffer_cursor;
+	int overflow = cbmem_console_p->buffer_cursor >
+		cbmem_console_p->buffer_size;
+
+	copy_size = overflow ?
+		cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor;
+
+	memcpy(new_cons_p->buffer_body + cursor,
+	       cbmem_console_p->buffer_body,
+	       copy_size);
+
+	cursor += copy_size;
+
+	if (overflow) {
+		const char loss_str1[] = "\n\n*** Log truncated, ";
+		const char loss_str2[] = " characters dropped. ***\n\n";
+		u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size;
+
+		/*
+		 * When running from ROM sprintf is not available, a simple
+		 * itoa implementation is used instead.
+		 */
+		int got_first_digit = 0;
+
+		/* Way more than possible number of dropped characters. */
+		u32 mult = 100000;
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1);
+		cursor += sizeof(loss_str1) - 1;
+
+		while (mult) {
+			int digit = dropped_chars / mult;
+			if (got_first_digit || digit) {
+				new_cons_p->buffer_body[cursor++] = digit + '0';
+				dropped_chars %= mult;
+				/* Excessive, but keeps it simple */
+				got_first_digit = 1;
+			}
+			mult /= 10;
+		}
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2);
+		cursor += sizeof(loss_str2) - 1;
+	}
+	new_cons_p->buffer_cursor = cursor;
+}
+
+void cbmemc_reinit(void)
+{
+	struct cbmem_console *cbm_cons_p;
+
+#ifdef __PRE_RAM__
+	cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE,
+			       CONFIG_CONSOLE_CBMEM_BUFFER_SIZE);
+	if (!cbm_cons_p) {
+		CBMEM_CONSOLE_REDIRECT = NULL;
+		return;
+	}
+
+	cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+
+	cbm_cons_p->buffer_cursor = 0;
+
+	copy_console_buffer(cbm_cons_p);
+
+	CBMEM_CONSOLE_REDIRECT = cbm_cons_p;
+#else
+	cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (!cbm_cons_p)
+		return;
+
+	copy_console_buffer(cbm_cons_p);
+
+	cbmem_console_p = cbm_cons_p;
+#endif
+}



From gerrit at coreboot.org  Wed Mar  7 02:12:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:47 +0100
Subject: [coreboot] Patch set updated for coreboot: 0297308 CBMEM CONSOLE:
	Add config option for CBMEM stored console log.
References: <I209603f516244ae136631e6281ba21ebc6fb1710+0@gerrit.coreboot.org>
Message-ID: <I209603f516244ae136631e6281ba21ebc6fb1710+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718

-gerrit

commit 0297308be444a7128f227c2784d6c8addf1cb176
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 28 13:51:30 2011 -0700

    CBMEM CONSOLE: Add config option for CBMEM stored console log.
    
    Some experiments have demonstrated that total amount of text
    generated by coreboot console when BIOS_SPEW level is enabled
    exceeds 40KB.
    
    Console output generated before DRAM is initialized can exceed
    2KB. This patch introduces the new configuration option and
    assigns adequate default values to cache based and DRAM based
    console buffers.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
     . run the following commands in the root directory
    
       cp config.stumpy .config
       make menuconfig
    
     . enable the new option (Console->Send console output to a CBMEM buffer)
     . save the configuration
    
    Observe the following settings added to the config:
    +CONFIG_CONSOLE_CBMEM=y
    +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
    +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
    
    Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5855
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index dbd11f6..fefbe2e 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT
 	  32 bytes of IO spaces will be used (and align on 32 bytes
 	  boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+	depends on EARLY_CBMEM_INIT
+	bool "Send console output to a CBMEM buffer"
+	default n
+	help
+	  Enable this to save the console output in a CBMEM buffer. This would
+	  allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in CBMEM"
+	default 0xae00
+	help
+	  Space allocated for console output storage in CBMEM. The default
+	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+	  even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in cash as RAM"
+	default 0xc00
+	help
+	  Console is used before RAM is initialized. This is the room reserved
+	  in the DCACHE based RAM to keep console output before it can be
+	  saved in a CBMEM buffer. 3K bytes should be enough even for the
+	  BIOS_SPEW level.
+
 
 choice
 	prompt "Maximum console log level"



From gerrit at coreboot.org  Wed Mar  7 02:12:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:48 +0100
Subject: [coreboot] Patch set updated for coreboot: 356ee5f Since
	cbfs_core.h provides a macro that uses ntohl,
	make sure ntohl is available
References: <I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f+0@gerrit.coreboot.org>
Message-ID: <I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/709

-gerrit

commit 356ee5f62fec68644dba49951ebc97cc3412befb
Author: Gabe Black <gabeblack at google.com>
Date:   Fri Sep 16 02:24:03 2011 -0700

    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available
    
    Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is available by
    including byteorder.h
    
    Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/include/cbfs_core.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index 70368f8..43e6b9b 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -49,6 +49,8 @@
 #ifndef _CBFS_CORE_H_
 #define _CBFS_CORE_H_
 
+#include <arch/byteorder.h>
+
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
     payloads.  Of course, other CBFS users can use whatever



From gerrit at coreboot.org  Wed Mar  7 02:12:49 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:49 +0100
Subject: [coreboot] Patch set updated for coreboot: 47697f1 Add an
	implementation for the memchr library function
References: <Icded479d246f7cce8a3d2154c69f75178fa513e1+0@gerrit.coreboot.org>
Message-ID: <Icded479d246f7cce8a3d2154c69f75178fa513e1+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/708

-gerrit

commit 47697f1d75a2f22e828e672ad6da6786e82b9361
Author: Gabe Black <gabeblack at google.com>
Date:   Fri Sep 16 02:18:56 2011 -0700

    Add an implementation for the memchr library function
    
    Change-Id: Icded479d246f7cce8a3d2154c69f75178fa513e1
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/include/string.h |    1 +
 src/lib/Makefile.inc |    2 ++
 src/lib/memchr.c     |   11 +++++++++++
 3 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/src/include/string.h b/src/include/string.h
index 2168947..708961b 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -8,6 +8,7 @@ void *memcpy(void *dest, const void *src, size_t n);
 void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t n);
+void *memchr(const void *s, int c, size_t n);
 #if !defined(__PRE_RAM__)
 int sprintf(char * buf, const char *fmt, ...);
 #endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 906dfae..e0e5e75 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,6 +1,7 @@
 
 
 romstage-y += memset.c
+romstage-y += memchr.c
 romstage-y += memcpy.c
 romstage-y += memcmp.c
 romstage-y += cbfs.c
@@ -15,6 +16,7 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 
 ramstage-y += memset.c
+ramstage-y += memchr.c
 ramstage-y += memcpy.c
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
diff --git a/src/lib/memchr.c b/src/lib/memchr.c
new file mode 100644
index 0000000..a890dce
--- /dev/null
+++ b/src/lib/memchr.c
@@ -0,0 +1,11 @@
+#include <string.h>
+void *memchr(const void *s, int c, size_t n)
+{
+	const unsigned char *sc = s;
+	while (n--) {
+		if (*sc == (unsigned char)c)
+			return (void *)sc;
+		sc++;
+	}
+	return NULL;
+}



From gerrit at coreboot.org  Wed Mar  7 02:12:50 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:50 +0100
Subject: [coreboot] Patch set updated for coreboot: 804886b Initialize CBMEM
	early.
References: <I81691d45e28de59496fb227f2cca4e8c15ece717+0@gerrit.coreboot.org>
Message-ID: <I81691d45e28de59496fb227f2cca4e8c15ece717+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/711

-gerrit

commit 804886b2a737261e85e5b5dd0e43bc5c3a4fd096
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Sep 20 17:07:14 2011 -0700

    Initialize CBMEM early.
    
    We want to be able to share data between different phases of firmware
    (rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
    location for this data, but normally it is not initialized
    until coreboot reaches the ram stage.
    
    This change initializes the CBMEM while still in rom stage in
    case CONFIG_EARLY_CBMEM_INIT is set.
    
    Note that there is a discrepancy in how coreboot determines the
    size of DRAM at rom and ram stages, get_top_of_ram() is used at
    rom stage and is not defined for all platforms. Those platforms
    will have to define this function should they enable the
    CONFIG_EARLY_CBMEM_INIT flag.
    
    Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    4 +++-
 src/lib/cbmem.c     |   39 +++++++++++++++++++++++----------------
 2 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 9806854..a681c36 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -22,7 +22,9 @@
 
 /* Reserve 128k for ACPI and other tables */
 #define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
+#endif
 
 #if CONFIG_HAVE_ACPI_RESUME
 #define HIGH_MEMORY_SIZE	((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE)
@@ -41,7 +43,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_NONE		0x00000000
 
-void cbmem_initialize(void);
+int cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
 int cbmem_reinit(u64 baseaddr);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 202f521..f5c3d3a 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -183,30 +183,38 @@ void *cbmem_find(u32 id)
 	return (void *)NULL;
 }
 
-#ifndef __PRE_RAM__
-#if CONFIG_HAVE_ACPI_RESUME
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
 extern u8 acpi_slp_type;
 #endif
 
-void cbmem_initialize(void)
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+/* Returns True if it was not intialized before. */
+int cbmem_initialize(void)
 {
-#if CONFIG_HAVE_ACPI_RESUME
-	printk(BIOS_DEBUG, "%s: acpi_slp_type=%d\n", __func__, acpi_slp_type);
-	if (acpi_slp_type == 3 || acpi_slp_type == 2) {
-		if (!cbmem_reinit(high_tables_base)) {
-			printk(BIOS_DEBUG, "cbmem_reinit failed\n");
-			/* Something went wrong, our high memory area got wiped */
+	int rv = 0;
+
+#ifdef __PRE_RAM__
+	extern unsigned long get_top_of_ram(void);
+	uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+	uint64_t high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+
+	/* We expect the romstage to always initialize it. */
+	if (!cbmem_reinit(high_tables_base)) {
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+		/* Something went wrong, our high memory area got wiped */
+		if (acpi_slp_type == 3 || acpi_slp_type == 2)
 			acpi_slp_type = 0;
-			cbmem_init(high_tables_base, high_tables_size);
-		}
-	} else {
+#endif
 		cbmem_init(high_tables_base, high_tables_size);
+		rv = 1;
 	}
-#else
-	cbmem_init(high_tables_base, high_tables_size);
-#endif
+#ifndef __PRE_RAM__
 	cbmem_arch_init();
+#endif
+	return rv;
 }
+#endif
 
 #ifndef __PRE_RAM__
 void cbmem_list(void)
@@ -240,5 +248,4 @@ void cbmem_list(void)
 }
 #endif
 
-#endif
 



From gerrit at coreboot.org  Wed Mar  7 02:12:51 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:51 +0100
Subject: [coreboot] Patch set updated for coreboot: 380481b Introduce config
	option to initialize CBMEM early.
References: <I6736fdc264ecd0b63369b28462d7bb96e4c2b012+0@gerrit.coreboot.org>
Message-ID: <I6736fdc264ecd0b63369b28462d7bb96e4c2b012+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/710

-gerrit

commit 380481bf48bd5f9e5b9c0251f0162f5ccbd04b26
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Sep 20 16:46:46 2011 -0700

    Introduce config option to initialize CBMEM early.
    
    We want to be able to communicate information between rom and ram
    stages of coreboot. This configuration option will be used to
    compile such ability in.
    
    Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/Kconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index c165d93..544b61b 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -112,6 +112,14 @@ config INCLUDE_CONFIG_FILE
   help
     Include in CBFS the coreboot config file that was used to compile the ROM image
 
+config EARLY_CBMEM_INIT
+	bool "Initialize CBMEM while in ROM stage"
+	default n
+	help
+	  Make coreboot initialize the cbmem structures while running in rom
+	  stage. This could be useful when the rom stage wants to communicate
+	  some, for instance, execution timestamps.
+
 endmenu
 
 source src/mainboard/Kconfig



From gerrit at coreboot.org  Wed Mar  7 02:12:52 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:52 +0100
Subject: [coreboot] Patch set updated for coreboot: 4d2426c Detect whether
	the OXPCIE card is really present while in the ROM stage.
References: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+0@gerrit.coreboot.org>
Message-ID: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728

-gerrit

commit 4d2426cf9e0ad1353aadbc49b96ecdb4a0e771cb
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:52:08 2011 -0700

    Detect whether the OXPCIE card is really present while in the ROM stage.
    
    Use an int in CAR global data to store whether or not the OXPCIE serial card
    is actually there. Also, time out if the card doesn't show up quickly enough,
    don't continue initialization if it's not there, and don't make the
    initialization routine default to a card if none is found.
    
    Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/lib/romstage_console.c      |    5 ++++-
 src/drivers/oxford/oxpcie/oxpcie_early.c |   20 +++++++++++++++++---
 src/include/uart8250.h                   |    5 +++++
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 0f22727..25eda9b 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte)
 		console_tx_byte('\r');
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
-	uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	if (oxford_oxpcie_present) {
+		uart8250_mem_tx_byte(
+			CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	}
 #endif
 #if CONFIG_CONSOLE_SERIAL8250
 	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 2c7767e..4f7a3cb 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -34,9 +36,13 @@
 #define OXPCIE_DEVICE_3 \
 	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
 
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
+
 void oxford_init(void)
 {
 	u16 reg16;
+	oxford_oxpcie_present = 1;
 
 	/* First we reset the secondary bus */
 	reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -69,11 +75,14 @@ void oxford_init(void)
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if
-	// no device is in the slot.
+	u32 timeout = 20000; // Timeout in 10s of microseconds.
 	u32 id = 0;
-	while ((id == 0) || (id == 0xffffffff))
+	for (;;) {
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+		if (!timeout-- || (id != 0 && id != 0xffffffff))
+			break;
+		udelay(10);
+	}
 
 	u32 device = OXPCIE_DEVICE; /* unknown default */
 	switch (id) {
@@ -90,6 +99,10 @@ void oxford_init(void)
 	case 0xc1581415: /* e.g. Startech MPEX2S952 */
 		device = OXPCIE_DEVICE;
 		break;
+	default:
+		/* No UART here. */
+		oxford_oxpcie_present = 0;
+		return;
 	}
 
 	/* Setup base address on device */
@@ -107,3 +120,4 @@ void oxford_init(void)
 	uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index aa510e5..71b9a5f 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
 u32 uartmem_getbaseaddr(void);
 
+#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
+	CONFIG_CONSOLE_SERIAL8250MEM
 /* and special init for OXPCIe based cards */
+extern int oxford_oxpcie_present;
+
 void oxford_init(void);
+#endif
 
 #endif /* __ROMCC__ */
 



From gerrit at coreboot.org  Wed Mar  7 02:12:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:53 +0100
Subject: [coreboot] Patch set updated for coreboot: 8e35db0 If the memory
	mapped UART isn't present, leave it out of the cb tables.
References: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+0@gerrit.coreboot.org>
Message-ID: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729

-gerrit

commit 8e35db00aa4fa92ead0a286d9b8ebe691d232a53
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:57:03 2011 -0700

    If the memory mapped UART isn't present, leave it out of the cb tables.
    
    This way u-boot won't try to use a UART that isn't plugged in.
    
    Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/boot/coreboot_table.c |   24 ++++++++++++++----------
 1 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f29481b..d24d7c4 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header)
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #elif CONFIG_CONSOLE_SERIAL8250MEM
-	struct lb_record *rec;
-	struct lb_serial *serial;
-	rec = lb_new_record(header);
-	serial = (struct lb_serial *)rec;
-	serial->tag = LB_TAG_SERIAL;
-	serial->size = sizeof(*serial);
-	serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial->baseaddr = uartmem_getbaseaddr();
-	serial->baud = CONFIG_TTYS0_BAUD;
-	return serial;
+	if (uartmem_getbaseaddr()) {
+		struct lb_record *rec;
+		struct lb_serial *serial;
+		rec = lb_new_record(header);
+		serial = (struct lb_serial *)rec;
+		serial->tag = LB_TAG_SERIAL;
+		serial->size = sizeof(*serial);
+		serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+		serial->baseaddr = uartmem_getbaseaddr();
+		serial->baud = CONFIG_TTYS0_BAUD;
+		return serial;
+	} else {
+		return NULL;
+	}
 #else
 	return NULL;
 #endif



From gerrit at coreboot.org  Wed Mar  7 02:12:54 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:54 +0100
Subject: [coreboot] Patch set updated for coreboot: b213a6d Don't run any
	option roms stored outside of the system flash
References: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+0@gerrit.coreboot.org>
Message-ID: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730

-gerrit

commit b213a6d254dd2a9a9ebdca982576e7072a89db04
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 6 16:47:51 2011 -0700

    Don't run any option roms stored outside of the system flash
    
    Right now coreboot only executes vga option roms. However, this is not
    good enough. For security reasons we want to execute only option roms
    stored in our RO CBFS.
    
    This patch adds a new option to disable execution of arbitrary option
    ROMs and enables it for all our boards.
    
    Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig   |   13 +++++++++++++
 src/devices/pci_rom.c |    6 ++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 572addc..98e8d9f 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -49,6 +49,19 @@ config PCI_ROM_RUN
 	  Examples include IDE/SATA controller option ROMs and option ROMs
 	  for network cards (NICs).
 
+config ON_DEVICE_ROM_RUN
+	bool "Run option ROMs on PCI devices"
+	default y
+	help
+	  Execute option ROMs that are stored on PCI/PCIe/AGP devices.
+
+	  If disabled, only option ROMs stored in CBFS will be executed. If
+	  you are concerned about security, you might want to disable this
+	  option, but it might leave your system in a state of degraded
+	  functionality.
+
+	  If unsure, say Y
+
 choice
 	prompt "Option ROM execution type"
 	default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 471c7e2..1b6f1da 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev)
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
+#if CONFIG_ON_DEVICE_ROM_RUN
 		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+#else
+		printk(BIOS_DEBUG, "On card option ROM execution disabled "
+			"for %s\n", dev_path(dev));
+		return NULL;
+#endif
 	}
 
 	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "



From gerrit at coreboot.org  Wed Mar  7 02:12:55 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:55 +0100
Subject: [coreboot] Patch set updated for coreboot: 4532872 Add TPM support
	to coreboot
References: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+0@gerrit.coreboot.org>
Message-ID: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731

-gerrit

commit 4532872237d30da130d3a30551df3cd25a30f0f8
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 11 14:46:25 2011 -0700

    Add TPM support to coreboot
    
    and initialize the TPM on S3 resume
    
    This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
    resume without including any other parts of vboot.
    
    We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
    (that are incompatible with coreboot's) and it does a lot more than we
    want it to do.
    
    Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig                            |    4 +
 src/arch/x86/boot/acpi.c               |    8 +
 src/include/pc80/tpm.h                 |   29 ++
 src/pc80/Makefile.inc                  |    1 +
 src/pc80/tpm.c                         |  554 ++++++++++++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot.c |  201 ++++++++++++
 6 files changed, 797 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 573868f..26e6dde 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -262,6 +262,10 @@ config IOAPIC
 	bool
 	default n
 
+config TPM
+	bool
+	default n
+
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
 	int
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..eb2e4e1 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void)
 	if (!acpi_is_wakeup())
 		return NULL;
 
+#ifdef CONFIG_CHROMEOS
+	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+	init_vboot();
+#endif
+
 	printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n");
 
 	/* Find RSDP. */
diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h
new file mode 100644
index 0000000..2eff15a
--- /dev/null
+++ b/src/include/pc80/tpm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef TPM_H_
+#define TPM_H_
+
+int tis_init(void);
+int tis_open(void);
+int tis_close(void);
+int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
+			size_t *recv_len);
+
+#endif /* TPM_H_ */
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 2c8a80e..cd6ea33 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -4,6 +4,7 @@ ramstage-y += i8254.c
 ramstage-y += i8259.c
 ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
 ramstage-y += keyboard.c
+ramstage-$(CONFIG_TPM) += tpm.c
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 subdirs-y += vga
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
new file mode 100644
index 0000000..1cbf800
--- /dev/null
+++ b/src/pc80/tpm.c
@@ -0,0 +1,554 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The code in this file has been heavily based on the article "Writing a TPM
+ * Device Driver" published on http://ptgmedia.pearsoncmg.com and the
+ * submission by Stefan Berger on Qemu-devel mailing list.
+ *
+ * One principal difference is that in the simplest config the other than 0
+ * TPM localities do not get mapped by some devices (for instance, by
+ * Infineon slb9635), so this driver provides access to locality 0 only.
+ */
+
+/* #define DEBUG */
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/byteorder.h>
+#include <console/console.h>
+#include <pc80/tpm.h>
+
+#ifdef DEBUG
+#define TPM_DEBUG_ON	1
+#else
+#define TPM_DEBUG_ON	0
+#endif
+
+#define PREFIX "lpc_tpm: "
+
+/* coreboot wrapper for TPM driver (start) */
+#define	TPM_DEBUG(fmt, args...)		\
+	if (TPM_DEBUG_ON) {		\
+		printk(BIOS_DEBUG, PREFIX);		\
+		printk(BIOS_DEBUG, fmt , ##args);	\
+	}
+#define printf(x...) printk(BIOS_ERR, x)
+
+#define min(a,b) MIN(a,b)
+#define max(a,b) MAX(a,b)
+#define readb(_a) (*(volatile unsigned char *) (_a))
+#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v))
+#define readl(_a) (*(volatile unsigned long *) (_a))
+#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v))
+/* coreboot wrapper for TPM driver (end) */
+
+#ifndef CONFIG_TPM_TIS_BASE_ADDRESS
+/* Base TPM address standard for x86 systems */
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+#endif
+
+/* the macro accepts the locality value, but only locality 0 is operational */
+#define TIS_REG(LOCALITY, REG) \
+    (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+
+/* hardware registers' offsets */
+#define TIS_REG_ACCESS                 0x0
+#define TIS_REG_INT_ENABLE             0x8
+#define TIS_REG_INT_VECTOR             0xc
+#define TIS_REG_INT_STATUS             0x10
+#define TIS_REG_INTF_CAPABILITY        0x14
+#define TIS_REG_STS                    0x18
+#define TIS_REG_DATA_FIFO              0x24
+#define TIS_REG_DID_VID                0xf00
+#define TIS_REG_RID                    0xf04
+
+/* Some registers' bit field definitions */
+#define TIS_STS_VALID                  (1 << 7) /* 0x80 */
+#define TIS_STS_COMMAND_READY          (1 << 6) /* 0x40 */
+#define TIS_STS_TPM_GO                 (1 << 5) /* 0x20 */
+#define TIS_STS_DATA_AVAILABLE         (1 << 4) /* 0x10 */
+#define TIS_STS_EXPECT                 (1 << 3) /* 0x08 */
+#define TIS_STS_RESPONSE_RETRY         (1 << 1) /* 0x02 */
+
+#define TIS_ACCESS_TPM_REG_VALID_STS   (1 << 7) /* 0x80 */
+#define TIS_ACCESS_ACTIVE_LOCALITY     (1 << 5) /* 0x20 */
+#define TIS_ACCESS_BEEN_SEIZED         (1 << 4) /* 0x10 */
+#define TIS_ACCESS_SEIZE               (1 << 3) /* 0x08 */
+#define TIS_ACCESS_PENDING_REQUEST     (1 << 2) /* 0x04 */
+#define TIS_ACCESS_REQUEST_USE         (1 << 1) /* 0x02 */
+#define TIS_ACCESS_TPM_ESTABLISHMENT   (1 << 0) /* 0x01 */
+
+#define TIS_STS_BURST_COUNT_MASK       (0xffff)
+#define TIS_STS_BURST_COUNT_SHIFT      (8)
+
+/*
+ * Error value returned if a tpm register does not enter the expected state
+ * after continuous polling. No actual TPM register reading ever returns ~0,
+ * so this value is a safe error indication to be mixed with possible status
+ * register values.
+ */
+#define TPM_TIMEOUT_ERR			(~0)
+
+/* Error value returned on various TPM driver errors */
+#define TPM_DRIVER_ERR		(~0)
+
+ /* 1 second is plenty for anything TPM does.*/
+#define MAX_DELAY_US	(1000 * 1000)
+
+/* Retrieve burst count value out of the status register contents. */
+#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \
+				   TIS_STS_BURST_COUNT_MASK))
+
+/*
+ * Structures defined below allow creating descriptions of TPM vendor/device
+ * ID information for run time discovery. The only device the system knows
+ * about at this time is Infineon slb9635
+ */
+struct device_name {
+	u16 dev_id;
+	const char * const dev_name;
+};
+
+struct vendor_name {
+	u16 vendor_id;
+	const char * vendor_name;
+	struct device_name* dev_names;
+};
+
+static struct device_name infineon_devices[] = {
+	{0xb, "SLB9635 TT 1.2"},
+	{0}
+};
+
+static const struct vendor_name vendor_names[] = {
+	{0x15d1, "Infineon", infineon_devices},
+};
+
+/*
+ * Cached vendor/device ID pair to indicate that the device has been already
+ * discovered
+ */
+static u32 vendor_dev_id;
+
+static int is_byte_reg(u32 reg)
+{
+	/*
+	 * These TPM registers are 8 bits wide and as such require byte access
+	 * on writes and truncated value on reads.
+	 */
+	return ((reg == TIS_REG_ACCESS)	||
+		(reg == TIS_REG_INT_VECTOR) ||
+		(reg == TIS_REG_DATA_FIFO));
+}
+
+/* TPM access functions are carved out to make tracing easier. */
+static u32 tpm_read(int locality, u32 reg)
+{
+	u32 value;
+	/*
+	 * Data FIFO register must be read and written in byte access mode,
+	 * otherwise the FIFO values are returned 4 bytes at a time.
+	 */
+	if (is_byte_reg(reg))
+		value = readb(TIS_REG(locality, reg));
+	else
+		value = readl(TIS_REG(locality, reg));
+
+	TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value);
+	return value;
+}
+
+static void tpm_write(u32 value, int locality,  u32 reg)
+{
+	TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value);
+
+	if (is_byte_reg(reg))
+		writeb(value & 0xff, TIS_REG(locality, reg));
+	else
+		writel(value, TIS_REG(locality, reg));
+}
+
+/*
+ * tis_wait_reg()
+ *
+ * Wait for at least a second for a register to change its state to match the
+ * expected state. Normally the transition happens within microseconds.
+ *
+ * @reg - the TPM register offset
+ * @locality - locality
+ * @mask - bitmask for the bitfield(s) to watch
+ * @expected - value the field(s) are supposed to be set to
+ *
+ * Returns the register contents in case the expected value was found in the
+ * appropriate register bits, or TPM_TIMEOUT_ERR on timeout.
+ */
+static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
+{
+	u32 time_us = MAX_DELAY_US;
+	while (time_us > 0) {
+		u32 value = tpm_read(locality, reg);
+		if ((value & mask) == expected)
+			return value;
+		udelay(1); /* 1 us */
+		time_us--;
+	}
+	return TPM_TIMEOUT_ERR;
+}
+
+/*
+ * Probe the TPM device and try determining its manufacturer/device name.
+ *
+ * Returns 0 on success (the device is found or was found during an earlier
+ * invocation) or TPM_DRIVER_ERR if the device is not found.
+ */
+static u32 tis_probe(void)
+{
+	u32 didvid = tpm_read(0, TIS_REG_DID_VID);
+	int i;
+	const char *device_name = "unknown";
+	const char *vendor_name = device_name;
+	u16 vid, did;
+
+	if (vendor_dev_id)
+		return 0;  /* Already probed. */
+
+	if (!didvid || (didvid == 0xffffffff)) {
+		printf("%s: No TPM device found\n", __FUNCTION__);
+		return TPM_DRIVER_ERR;
+	}
+
+	vendor_dev_id = didvid;
+
+	vid = didvid & 0xffff;
+	did = (didvid >> 16) & 0xffff;
+	for (i = 0; i < ARRAY_SIZE(vendor_names); i++) {
+		int j = 0;
+		u16 known_did;
+		if (vid == vendor_names[i].vendor_id) {
+			vendor_name = vendor_names[i].vendor_name;
+		}
+		while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+			if (known_did == did) {
+				device_name =
+					vendor_names[i].dev_names[j].dev_name;
+				break;
+			}
+			j++;
+		}
+		break;
+	}
+	/* this will have to be converted into debug printout */
+	TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name);
+	return 0;
+}
+
+/*
+ * tis_senddata()
+ *
+ * send the passed in data to the TPM device.
+ *
+ * @data - address of the data to send, byte by byte
+ * @len - length of the data to send
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
+ * not accept the entire command).
+ */
+static u32 tis_senddata(const u8 * const data, u32 len)
+{
+	u32 offset = 0;
+	u16 burst = 0;
+	u32 max_cycles = 0;
+	u8 locality = 0;
+	u32 value;
+
+	value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY,
+			     TIS_STS_COMMAND_READY);
+	if (value == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to get 'command_ready' status\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+	burst = BURST_COUNT(value);
+
+	while (1) {
+		unsigned count;
+
+		/* Wait till the device is ready to accept more data. */
+		while (!burst) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d failed to feed %d bytes of %d\n",
+				       __FILE__, __LINE__, len - offset, len);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS));
+		}
+
+		max_cycles = 0;
+
+		/*
+		 * Calculate number of bytes the TPM is ready to accept in one
+		 * shot.
+		 *
+		 * We want to send the last byte outside of the loop (hence
+		 * the -1 below) to make sure that the 'expected' status bit
+		 * changes to zero exactly after the last byte is fed into the
+		 * FIFO.
+		 */
+		count = min(burst, len - offset - 1);
+		while (count--)
+			tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+		value = tis_wait_reg(TIS_REG_STS, locality,
+				     TIS_STS_VALID, TIS_STS_VALID);
+
+		if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) {
+			printf("%s:%d TPM command feed overflow\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		burst = BURST_COUNT(value);
+		if ((offset == (len - 1)) && burst)
+			/*
+			 * We need to be able to send the last byte to the
+			 * device, so burst size must be nonzero before we
+			 * break out.
+			 */
+			break;
+	}
+
+	/* Send the last byte. */
+	tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+	/*
+	 * Verify that TPM does not expect any more data as part of this
+	 * command.
+	 */
+	value = tis_wait_reg(TIS_REG_STS, locality,
+			     TIS_STS_VALID, TIS_STS_VALID);
+	if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) {
+		printf("%s:%d unexpected TPM status 0x%x\n",
+		       __FILE__, __LINE__, value);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* OK, sitting pretty, let's start the command execution. */
+	tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_readresponse()
+ *
+ * read the TPM device response after a command was issued.
+ *
+ * @buffer - address where to read the response, byte by byte.
+ * @len - pointer to the size of buffer
+ *
+ * On success stores the number of received bytes to len and returns 0. On
+ * errors (misformatted TPM data or synchronization problems) returns
+ * TPM_DRIVER_ERR.
+ */
+static u32 tis_readresponse(u8 *buffer, size_t *len)
+{
+	u16 burst_count;
+	u32 status;
+	u32 offset = 0;
+	u8 locality = 0;
+	const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+	u32 expected_count = *len;
+	int max_cycles = 0;
+
+	/* Wait for the TPM to process the command */
+	status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data);
+	if (status == TPM_TIMEOUT_ERR) {
+		printf("%s:%d failed processing command\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	do {
+		while ((burst_count = BURST_COUNT(status)) == 0) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d TPM stuck on read\n",
+				       __FILE__, __LINE__);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			status = tpm_read(locality, TIS_REG_STS);
+		}
+
+		max_cycles = 0;
+
+		while (burst_count-- && (offset < expected_count)) {
+			buffer[offset++] = (u8) tpm_read(locality,
+							 TIS_REG_DATA_FIFO);
+			if (offset == 6) {
+				/*
+				 * We got the first six bytes of the reply,
+				 * let's figure out how many bytes to expect
+				 * total - it is stored as a 4 byte number in
+				 * network order, starting with offset 2 into
+				 * the body of the reply.
+				 */
+				u32 real_length;
+				memcpy(&real_length,
+				       buffer + 2,
+				       sizeof(real_length));
+				expected_count = be32_to_cpu(real_length);
+
+				if ((expected_count < offset) ||
+				    (expected_count > *len)) {
+					printf("%s:%d bad response size %d\n",
+					       __FILE__, __LINE__,
+					       expected_count);
+					return TPM_DRIVER_ERR;
+				}
+			}
+		}
+
+		/* Wait for the next portion */
+		status = tis_wait_reg(TIS_REG_STS, locality,
+				      TIS_STS_VALID, TIS_STS_VALID);
+		if (status == TPM_TIMEOUT_ERR) {
+			printf("%s:%d failed to read response\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		if (offset == expected_count)
+			break;	/* We got all we need */
+
+	} while ((status & has_data) == has_data);
+
+	/*
+	 * Make sure we indeed read all there was. The TIS_STS_VALID bit is
+	 * known to be set.
+	 */
+	if (status & TIS_STS_DATA_AVAILABLE) {
+		printf("%s:%d wrong receive status %x\n",
+		       __FILE__, __LINE__, status);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* Tell the TPM that we are done. */
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	*len = offset;
+	return 0;
+}
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void)
+{
+	if (tis_probe())
+		return TPM_DRIVER_ERR;
+	return 0;
+}
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on failure.
+ */
+int tis_open(void)
+{
+	u8 locality = 0; /* we use locality zero for everything */
+
+	if (tis_close())
+		return TPM_DRIVER_ERR;
+
+	/* now request access to locality */
+	tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS);
+
+	/* did we get a lock? */
+	if (tis_wait_reg(TIS_REG_ACCESS, locality,
+			 TIS_ACCESS_ACTIVE_LOCALITY,
+			 TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to lock locality %d\n",
+		       __FILE__, __LINE__, locality);
+		return TPM_DRIVER_ERR;
+	}
+
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void)
+{
+	u8 locality = 0;
+	if (tpm_read(locality, TIS_REG_ACCESS) &
+	    TIS_ACCESS_ACTIVE_LOCALITY) {
+		tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS);
+
+		if (tis_wait_reg(TIS_REG_ACCESS, locality,
+				 TIS_ACCESS_ACTIVE_LOCALITY, 0) ==
+		    TPM_TIMEOUT_ERR) {
+			printf("%s:%d - failed to release locality %d\n",
+			       __FILE__, __LINE__, locality);
+			return TPM_DRIVER_ERR;
+		}
+	}
+	return 0;
+}
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or TPM_DRIVER_ERR on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size,
+		 uint8_t *recvbuf, size_t *recv_len)
+{
+	if (tis_senddata(sendbuf, send_size)) {
+		printf("%s:%d failed sending data to TPM\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	return tis_readresponse(recvbuf, recv_len);
+}
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
new file mode 100644
index 0000000..e0a8c9b
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <pc80/tpm.h>
+#include "chromeos.h"
+
+//#define EXTRA_LOGGING
+
+#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
+
+#define TPM_SUCCESS               ((u32)0x00000000)
+
+#define TPM_E_IOERROR             ((u32)0x0000001f)
+#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004)
+#define TPM_E_NON_FATAL           ((u32)0x00000800)
+#define TPM_E_INVALID_POSTINIT    ((u32)0x00000026)
+
+#define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
+#define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
+
+static const struct {
+	u8 buffer[12];
+} tpm_resume_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 }
+};
+
+static const struct {
+	u8 buffer[10];
+} tpm_continueselftest_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 }
+};
+
+static inline void FromTpmUint32(const u8 * buffer, u32 * x)
+{
+	*x = ((buffer[0] << 24) |
+	      (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]);
+}
+
+static inline int TpmCommandSize(const u8 * buffer)
+{
+	u32 size;
+	FromTpmUint32(buffer + sizeof(u16), &size);
+	return (int)size;
+}
+
+/* Gets the code field of a TPM command. */
+static inline int TpmCommandCode(const u8 * buffer)
+{
+	u32 code;
+	FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code);
+	return code;
+}
+
+/* Gets the return code field of a TPM result. */
+static inline int TpmReturnCode(const u8 * buffer)
+{
+	return TpmCommandCode(buffer);
+}
+
+/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or
+ * DOING_SELFTEST errors are returned.
+ */
+static u32 TlclSendReceiveNoRetry(const u8 * request,
+				  u8 * response, int max_length)
+{
+	size_t response_length = max_length;
+	u32 result;
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n",
+	       request[0], request[1],
+	       request[2], request[3], request[4], request[5],
+	       request[6], request[7], request[8], request[9]);
+#endif
+
+	result = TPM_SUCCESS;
+	if (tis_sendrecv
+	    (request, TpmCommandSize(request), response, &response_length))
+		result = TPM_E_IOERROR;
+
+	if (0 != result) {
+		/* Communication with TPM failed, so response is garbage */
+		printk(BIOS_DEBUG,
+		       "TPM: command 0x%x send/receive failed: 0x%x\n",
+		       TpmCommandCode(request), result);
+		return TPM_E_COMMUNICATION_ERROR;
+	}
+	/* Otherwise, use the result code from the response */
+	result = TpmReturnCode(response);
+
+/* TODO: add paranoia about returned response_length vs. max_length
+ * (and possibly expected length from the response header).  See
+ * crosbug.com/17017 */
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n",
+	       response[0], response[1],
+	       response[2], response[3], response[4], response[5],
+	       response[6], response[7], response[8], response[9]);
+#endif
+
+	printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n",
+	       TpmCommandCode(request), result);
+
+	return result;
+}
+
+static inline u32 TlclContinueSelfTest(void)
+{
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+	printk(BIOS_DEBUG, "TPM: Continue self test\n");
+	/* Call the No Retry version of SendReceive to avoid recursion. */
+	return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer,
+				      response, sizeof(response));
+}
+
+/* Sends a TPM command and gets a response.  Returns 0 if success or the TPM
+ * error code if error. In the firmware, waits for the self test to complete
+ * if needed. In the host, reports the first error without retries. */
+static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
+{
+	u32 result = TlclSendReceiveNoRetry(request, response, max_length);
+	/* When compiling for the firmware, hide command failures due to the self
+	 * test not having run or completed. */
+	/* If the command fails because the self test has not completed, try it
+	 * again after attempting to ensure that the self test has completed. */
+	if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) {
+		result = TlclContinueSelfTest();
+		if (result != TPM_SUCCESS) {
+			return result;
+		}
+#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE)
+		/* Retry only once */
+		result = TlclSendReceiveNoRetry(request, response, max_length);
+#else
+		/* This needs serious testing.  The TPM specification says:
+		 * "iii. The caller MUST wait for the actions of
+		 * TPM_ContinueSelfTest to complete before reissuing the
+		 * command C1."  But, if ContinueSelfTest is non-blocking, how
+		 * do we know that the actions have completed other than trying
+		 * again? */
+		do {
+			result =
+			    TlclSendReceiveNoRetry(request, response,
+						   max_length);
+		} while (result == TPM_E_DOING_SELFTEST);
+#endif
+	}
+
+	return result;
+}
+
+void init_vboot(void)
+{
+	u32 result;
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+
+	printk(BIOS_DEBUG, "TPM: Init\n");
+	if (tis_init())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Open\n");
+	if (tis_open())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Resume\n");
+
+	result =
+	    TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response));
+
+	if (result == TPM_E_INVALID_POSTINIT) {
+		/* We're on a platform where the TPM maintains power in S3, so
+		 * it's already initialized. */
+		printk(BIOS_DEBUG, "TPM: Already initialized.\n");
+		return;
+	}
+	if (result == TPM_SUCCESS) {
+		printk(BIOS_DEBUG, "TPM: OK.\n");
+		return;
+	}
+	// TODO(reinauer) hard reboot?
+}



From gerrit at coreboot.org  Wed Mar  7 02:12:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:56 +0100
Subject: [coreboot] Patch set updated for coreboot: efcb447 selfboot: Allow
	loading SeaBIOS into a reserved region in the lower 1MB This
	fixes loading SeaBIOS when lower memory is reserved.
References: <Idbdcaf95f3307f97307f304d6d677406d059927d+0@gerrit.coreboot.org>
Message-ID: <Idbdcaf95f3307f97307f304d6d677406d059927d+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732

-gerrit

commit efcb44797d8cb116926eb6876cbbf59b373da804
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 18 15:11:04 2011 -0700

    selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB
    This fixes loading SeaBIOS when lower memory is reserved.
    
    Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index fe56653..bbf160e 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer,
 		}
 	}
 	if (i == mem_entries) {
+		if (start < (1024*1024) && end <=(1024*1024)) {
+			printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded"
+				" into a reserved area in the lower 1MB\n");
+			return 1;
+		}
 		printk(BIOS_ERR, "No matching ram area found for range:\n");
 		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
 		printk(BIOS_ERR, "Ram areas\n");



From gerrit at coreboot.org  Wed Mar  7 02:12:57 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:57 +0100
Subject: [coreboot] Patch set updated for coreboot: 395e6db Add timestamps
	for selfboot and acpi wake
References: <I28224867610b947739d940d25c98399d219f10f4+0@gerrit.coreboot.org>
Message-ID: <I28224867610b947739d940d25c98399d219f10f4+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733

-gerrit

commit 395e6db059da6cbc0048ed9a082fe1906df43c11
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Oct 19 15:32:39 2011 -0700

    Add timestamps for selfboot and acpi wake
    
    Change-Id: I28224867610b947739d940d25c98399d219f10f4
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/boot/acpi.c |    7 +++++++
 src/boot/selfboot.c      |    7 +++++++
 src/include/timestamp.h  |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index eb2e4e1..d4d554c 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
@@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector)
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
 }
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index bbf160e..d4ab8c8 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -29,6 +29,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <lib.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 
 /* Maximum physical address we can use for the coreboot bounce buffer. */
 #ifndef MAX_ADDR
@@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(POST_ENTER_ELF_BOOT);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_SELFBOOT_JUMP);
+#endif
+
 	/* Jump to kernel */
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index cfa06e2..8b9a89a 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -37,6 +37,8 @@ struct timestamp_table {
 enum timestamp_id {
 	TS_BEFORE_INITRAM = 1,
 	TS_AFTER_INITRAM = 2,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
 };
 
 void timestamp_init(tsc_t base);



From gerrit at coreboot.org  Wed Mar  7 02:12:57 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:57 +0100
Subject: [coreboot] Patch set updated for coreboot: 2c1ca17 tell superiotool
	about the ITE 8772
References: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+0@gerrit.coreboot.org>
Message-ID: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734

-gerrit

commit 2c1ca1793b591e9b205259174e72f0658281eab0
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 17:12:53 2011 +0000

    tell superiotool about the ITE 8772
    
    no dumping yet
    
    Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/superiotool/ite.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index c83d788..e186e10 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = {
 		{EOT}}},
 	{0x8761, "IT8761E", {
 		{EOT}}},
+	{0x8772, "IT8772F", {
+		{EOT}}},
 	{0x8780, "IT8780F", {
 		{EOT}}},
 	{EOT}



From gerrit at coreboot.org  Wed Mar  7 02:12:58 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:58 +0100
Subject: [coreboot] Patch set updated for coreboot: 2b1db7b Add support for
	enabling PCIe Common Clock and ASPM
References: <I3fe46282eada67629e9eeeed07e487dff54f2729+0@gerrit.coreboot.org>
Message-ID: <I3fe46282eada67629e9eeeed07e487dff54f2729+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735

-gerrit

commit 2b1db7b02a9d12962a396e81dbe2d2828d8525a9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Oct 25 14:15:11 2011 -0700

    Add support for enabling PCIe Common Clock and ASPM
    
    These are guarded by individual Kconfig entries. The deprecated
    CONFIG_PCIE_TUNING defines have been removed in favor of using specific
    config options.
    
    This is the generic half, there is board-specific pieces
    still to come that tune before and after ASPM is enabled.
    
    Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/devices/Kconfig          |   14 +++
 src/devices/pciexp_device.c  |  188 +++++++++++++++++++++++++++++++++++++++---
 src/include/device/pci_def.h |    7 ++
 src/include/device/pciexp.h  |    7 ++
 4 files changed, 205 insertions(+), 11 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 98e8d9f..7429bda 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	default y
+
+config PCIEXP_COMMON_CLOCK
+	prompt "Enable PCIe Common Clock"
+	bool
+	default n
+	help
+	  Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+	prompt "Enable PCIe ASPM"
+	bool
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 5d33942..36f3e6a 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -19,31 +19,197 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
+#if CONFIG_PCIEXP_COMMON_CLOCK
+/*
+ * Re-train a PCIe link
+ */
+#define PCIE_TRAIN_RETRY 10000
+static int pciexp_retrain_link(device_t dev, unsigned cap)
+{
+	unsigned try = PCIE_TRAIN_RETRY;
+	u16 lnk;
+
+	/* Start link retraining */
+	lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
+	lnk |= PCI_EXP_LNKCTL_RL;
+	pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
+
+	/* Wait for training to complete */
+	while (try--) {
+		lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+		if (!(lnk & PCI_EXP_LNKSTA_LT))
+			return 0;
+		udelay(100);
+	}
+
+	printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+	return -1;
+}
+
+/*
+ * Check the Slot Clock Configuration for root port and endpoint
+ * and enable Common Clock Configuration if possible.  If CCC is
+ * enabled the link must be retrained.
+ */
+static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
+				       device_t endp, unsigned endp_cap)
+{
+	u16 root_scc, endp_scc, lnkctl;
+
+	/* Get Slot Clock Configuration for root port */
+	root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
+	root_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Get Slot Clock Configuration for endpoint */
+	endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
+	endp_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Enable Common Clock Configuration and retrain */
+	if (root_scc && endp_scc) {
+		printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
+
+		/* Set in endpoint */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set in root port */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Retrain link if CCC was enabled */
+		pciexp_retrain_link(root, root_cap);
+	}
+}
+#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
+
+#if CONFIG_PCIEXP_ASPM
+/*
+ * Determine the ASPM L0s or L1 exit latency for a link
+ * by checking both root port and endpoint and returning
+ * the highest latency value.
+ */
+static int pciexp_aspm_latency(device_t root, unsigned root_cap,
+			       device_t endp, unsigned endp_cap,
+			       enum aspm_type type)
+{
+	int root_lat = 0, endp_lat = 0;
+	u32 root_lnkcap, endp_lnkcap;
+
+	root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+	endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
+
+	/* Make sure the link supports this ASPM type by checking
+	 * capability bits 11:10 with aspm_type offset by 1 */
+	if (!(root_lnkcap & (1 << (type + 9))) ||
+	    !(endp_lnkcap & (1 << (type + 9))))
+		return -1;
+
+	/* Find the one with higher latency */
+	switch (type) {
+	case PCIE_ASPM_L0S:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		break;
+	case PCIE_ASPM_L1:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		break;
+	default:
+		return -1;
+	}
+
+	return (endp_lat > root_lat) ? endp_lat : root_lat;
+}
+
+/*
+ * Enable ASPM on PCIe root port and endpoint.
+ *
+ * Returns APMC value:
+ *   -1 = Error
+ *    0 = no ASPM
+ *    1 = L0s Enabled
+ *    2 = L1 Enabled
+ *    3 = L0s and L1 Enabled
+ */
+static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
+					 device_t endp, unsigned endp_cap)
+{
+	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	int exit_latency, ok_latency;
+	u16 lnkctl;
+	u32 devcap;
+
+	/* Get endpoint device capabilities for acceptable limits */
+	devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
+
+	/* Enable L0s if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L0S);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L0S;
+
+	/* Enable L1 if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L1);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L1;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set APMC in root port first */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set APMC in endpoint device next */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+	}
+
+	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
+	return apmc;
+}
+#endif /* CONFIG_PCIEXP_ASPM */
+
 static void pciexp_tune_dev(device_t dev)
 {
-	unsigned int cap;
-#if CONFIG_PCIE_TUNING
-	u32 reg32;
-#endif
+	device_t root = dev->bus->dev;
+	unsigned int root_cap, cap;
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
 		return;
 
-#if CONFIG_PCIE_TUNING
-	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
+	root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+	if (!root_cap)
+		return;
+
+#if CONFIG_PCIEXP_COMMON_CLOCK
+	/* Check for and enable Common Clock */
+	pciexp_enable_common_clock(root, root_cap, dev, cap);
+#endif
 
-	// TODO make this depending on ASPM.
+#if CONFIG_PCIEXP_ASPM
+	/* Check for and enable ASPM */
+	enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
 
-	/* Enable ASPM role based error reporting. */
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Enable ASPM role based error reporting. */
+		u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+		reg32 |= PCI_EXP_DEVCAP_RBER;
+		pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	}
 #endif
 }
 
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1..58a7321 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
 #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
+#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
+#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
 #define PCI_EXP_SLTCTL		24	/* Slot Control */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211..87a5002 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
 #define DEVICE_PCIEXP_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+enum aspm_type {
+	PCIE_ASPM_NONE = 0,
+	PCIE_ASPM_L0S  = 1,
+	PCIE_ASPM_L1   = 2,
+	PCIE_ASPM_BOTH = 3,
+};
+
 unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn, unsigned int max);
 unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);



From gerrit at coreboot.org  Wed Mar  7 02:12:59 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:12:59 +0100
Subject: [coreboot] Patch set updated for coreboot: 6992fdf CBMEM CONSOLE:
	Add CBMEM type for console buffer.
References: <I02757c06d71e46af77b02b90b0e6018a37b62406+0@gerrit.coreboot.org>
Message-ID: <I02757c06d71e46af77b02b90b0e6018a37b62406+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720

-gerrit

commit 6992fdf6d151541af2bdf246acf9ccc1d3a6ad45
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:13:06 2011 -0700

    CBMEM CONSOLE: Add CBMEM type for console buffer.
    
    Add CBMEM type for the console buffer section.
    
    Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    1 +
 src/lib/cbmem.c     |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index c3f10ef..a19ec5a 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_RESUME		0x5245534d
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_CONSOLE	0x434f4e53
 #define CBMEM_ID_NONE		0x00000000
 
 int cbmem_initialize(void);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index f800b04..b09b070 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -256,6 +256,7 @@ void cbmem_list(void)
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
 		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
 		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
+		case CBMEM_ID_CONSOLE:   printk(BIOS_DEBUG, "CONSOLE    "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);



From gerrit at coreboot.org  Wed Mar  7 02:13:00 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:00 +0100
Subject: [coreboot] Patch set updated for coreboot: 3a3a281 CBMEM CONSOLE:
	Add code using the new console driver.
References: <Ifd1f492ce6321412a014333babbc5b3f14635988+0@gerrit.coreboot.org>
Message-ID: <Ifd1f492ce6321412a014333babbc5b3f14635988+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721

-gerrit

commit 3a3a28165b4c3e4d7e21326568646e8acefc96ad
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:16:49 2011 -0700

    CBMEM CONSOLE: Add code using the new console driver.
    
    The new added code is compiled in when the CBMEM_CONSOLE config
    flag is enabled.
    
    Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/lib/romcc_console.c    |    3 +++
 src/arch/x86/lib/romstage_console.c |    3 +++
 src/boot/hardwaremain.c             |    3 +++
 src/console/console.c               |    5 ++++-
 4 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 13ee1f0..0e1f4e6 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void __console_tx_nibble(unsigned nibble)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 8adb3ba..0f22727 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void console_tx_flush(void)
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 3d15b55..9b293c0 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -92,6 +92,9 @@ void hardwaremain(int boot_complete)
 
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
diff --git a/src/console/console.c b/src/console/console.c
index d933668..8f60f04 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -87,7 +87,7 @@ int console_tst_byte(void)
 	return 0;
 }
 
-#else
+#else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
 void console_init(void)
 {
@@ -104,6 +104,9 @@ void console_init(void)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_init();
+#endif
 	static const char console_test[] =
 		"\n\ncoreboot-"
 		COREBOOT_VERSION



From gerrit at coreboot.org  Wed Mar  7 02:13:01 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:01 +0100
Subject: [coreboot] Patch set updated for coreboot: 54747a4 CBMEM CONSOLE:
	Enable coreboot CBMEM console.
References: <I91842b1ba0f89d611d3249b63c020a2713a9124f+0@gerrit.coreboot.org>
Message-ID: <I91842b1ba0f89d611d3249b63c020a2713a9124f+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722

-gerrit

commit 54747a4361b36a6ea516116f7486ec1c8bd94669
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 12:02:18 2011 -0700

    CBMEM CONSOLE: Enable coreboot CBMEM console.
    
    The appropriate Makefiles are modified to include the required
    source code in compilation.
    
    Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/Makefile.inc |    2 ++
 src/lib/Makefile.inc     |    2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..f3b8758 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
+driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
 $(obj)/console/console.romstage.o : $(obj)/build.h
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index db640dc..45cb788 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@@ -34,6 +35,7 @@ ramstage-y += clog2.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c



From gerrit at coreboot.org  Wed Mar  7 02:13:02 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:02 +0100
Subject: [coreboot] Patch set updated for coreboot: 9c59105 Introduce
	utility for parsing CBMEM contents.
References: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+0@gerrit.coreboot.org>
Message-ID: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723

-gerrit

commit 9c591059993e49c5bbb841e8bcf47f2ff3987191
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 14:21:03 2011 -0700

    Introduce utility for parsing CBMEM contents.
    
    This is a python script which is supposed to run on a target
    which is controlled by coreboot. The script examines top of
    memory looking for the CBMEM signature at addresses aligned at
    128K boundary. Once the script finds the CBMEM, it iterates
    through the CBMEM table of contents and parses two entries: the
    timestamps and the console log.
    
    This submission is just a template to build upon to create a
    utility for displaying CBMEM information while running Linux on
    the target.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
    See test description of d81e6b8c8d41f2d6 for test procedure.
    
    Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5942
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbmem/cbmem.py |  204 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 204 insertions(+), 0 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
new file mode 100755
index 0000000..3e8476d
--- /dev/null
+++ b/util/cbmem/cbmem.py
@@ -0,0 +1,204 @@
+#!/usr/bin/python
+#
+# cbmem.py - Linux space CBMEM contents parser
+#
+# Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+'''
+Parse and display CBMEM contents.
+
+This module is meant to run on systems with coreboot based firmware.
+
+When started, it determines the amount of DRAM installed on the system, and
+then scans the top area of DRAM (right above the available memory size)
+looking for the CBMEM base signature at locations aligned at 0x20000
+boundaries.
+
+Once it finds the CBMEM signature, the utility parses the contents, reporting
+the section IDs/sizes and also reporting the contents of the tiemstamp and
+console sections.
+'''
+
+import mmap
+import re
+import struct
+import sys
+import time
+
+# These definitions follow src/include/cbmem.h
+CBMEM_MAGIC = 0x434f5245
+CBMEM_MAX_ENTRIES = 16
+
+CBMEM_ENTRY_FORMAT = '@LLQQ'
+CONSOLE_HEADER_FORMAT = '@LL'
+TIMESTAMP_HEADER_FORMAT = '@QLL'
+TIMESTAMP_ENTRY_FORMAT = '@LQ'
+
+mf_fileno = 0  # File number of the file providing access to memory.
+
+def align_up(base, alignment):
+    '''Increment to the alignment boundary.
+
+    Return the next integer larger than 'base' and divisible by 'alignment'.
+    '''
+
+    return base + alignment - base % alignment
+
+def normalize_timer(value, freq):
+    '''Convert timer reading into microseconds.
+
+    Get the free running clock counter value, divide it by the clock frequency
+    and multiply by 1 million to get reading in microseconds.
+
+    Then convert the value into an ASCII string with groups of three digits
+    separated by commas.
+
+    Inputs:
+      value: int, the clock reading
+      freq: float, the clock frequency
+
+    Returns:
+      A string presenting 'value' in microseconds.
+    '''
+
+    result = []
+    value = int(value * 1000000.0 / freq)
+    svalue = '%d' % value
+    vlength = len(svalue)
+    remainder = vlength % 3
+    if remainder:
+        result.append(svalue[0:remainder])
+    while remainder < vlength:
+        result.append(svalue[remainder:remainder+3])
+        remainder = remainder + 3
+    return ','.join(result)
+
+def get_cpu_freq():
+    '''Retrieve CPU frequency from sysfs.
+
+    Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source.
+    '''
+    freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq'
+                    ).read()
+    # Convert reading into Hertz
+    return float(freq_str) * 1000.0
+
+def get_mem_size():
+    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
+    mult = {
+        'kB': 1024
+        }
+    meminfo = open('/proc/meminfo').read()
+    m = re.search('MemTotal:.*\n', meminfo)
+    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
+    (_, size, mult_name) = mem_string.split()
+    return int(size) * mult[mult_name]
+
+def parse_mem_at(addr, format):
+    '''Read and parse a memory location.
+
+    This function reads memory at the passed in address, parses it according
+    to the passed in format specification and returns a list of values.
+
+    The first value in the list is the size of data matching the format
+    expression, and the rest of the elements of the list are the actual values
+    retrieved using the format.
+    '''
+
+    size = struct.calcsize(format)
+    delta = addr % 4096   # mmap requires the offset to be page size aligned.
+    mm = mmap.mmap(mf_fileno, size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mm.close()
+    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
+    return rv
+
+def dprint(text):
+    '''Debug print function.
+
+    Edit it to get the debug output.
+    '''
+
+    if False:
+        print text
+
+def process_timers(base):
+    '''Scan the array of timestamps found in CBMEM at address base.
+
+    For each timestamp print the timer ID and the value in microseconds.
+    '''
+
+    (step, base_time, max_entr, entr) = parse_mem_at(
+        base, TIMESTAMP_HEADER_FORMAT)
+
+    print('\ntime base %d, total entries %d' % (base_time, entr))
+    clock_freq = get_cpu_freq()
+    base = base + step
+    for i in range(entr):
+        (step, timer_id, timer_value) = parse_mem_at(
+            base, TIMESTAMP_ENTRY_FORMAT)
+        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
+        base = base + step
+    print
+
+def process_console(base):
+    '''Dump the console log buffer contents found at address base.'''
+
+    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
+    print 'cursor at %d\n' % cursor
+
+    cons_string_format = '%ds' % min(cursor, size)
+    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    print cons_text
+    print '\n'
+
+mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
+table_alignment = 128 * 1024
+
+mem_size = get_mem_size()
+
+# start at memory address aligned at 128K.
+offset = align_up(mem_size, table_alignment)
+
+dprint('mem_size %x offset %x' %(mem_size, offset))
+mf = open("/dev/mem")
+mf_fileno = mf.fileno()
+
+while offset % mem_alignment: # do not cross the 1G boundary while searching
+    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if magic == CBMEM_MAGIC:
+        offset = offset + step
+        break
+    offset += table_alignment
+else:
+    print 'Did not find the CBMEM'
+    sys.exit(0)
+
+for i in (range(1, CBMEM_MAX_ENTRIES)):
+    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if mid == 0:
+        break
+
+    print '%x, %x, %x' % (mid, base, size)
+    if mid == 0x54494d45:
+        process_timers(base)
+    if mid == 0x434f4e53:
+        process_console(base)
+
+    offset = offset + step
+
+mf.close()



From gerrit at coreboot.org  Wed Mar  7 02:13:12 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:12 +0100
Subject: [coreboot] Patch set updated for coreboot: 255707f Refactor
	publishing CBMEM addresses through coreboot table.
References: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+0@gerrit.coreboot.org>
Message-ID: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724

-gerrit

commit 255707f46e18ff3d563c95e6fc4f98c7b9c8438d
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Mon Oct 3 14:58:57 2011 -0700

    Refactor publishing CBMEM addresses through coreboot table.
    
    We need to provide u-boot access to several different CBMEM
    sections. To do that, a common coreboot table structure is used,
    just different tags match different coreboot table sections.
    
    Also, the code is added to export CBMEM console and MRC cache
    addresses through the same mechanism.
    
    Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   59 +++++++++++++++++++++++++++++-------
 src/include/boot/coreboot_tables.h |    6 ++-
 2 files changed, 52 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f189e76..f29481b 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
-#if CONFIG_COLLECT_TIMESTAMPS
-static void lb_tsamp(struct lb_header *header)
+static void add_cbmem_pointers(struct lb_header *header)
 {
-	struct lb_tstamp *tstamp;
-	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+	/*
+	 * These CBMEM sections' addresses are included in the coreboot table
+	 * with the appropriate tags.
+	 */
+	const struct section_id {
+		int cbmem_id;
+		int table_tag;
+	} section_ids[] = {
+		{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+		{CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE},
+		{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+	};
+	int i;
 
-	if (!tstamp_table)
-		return;
+	for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+		const struct section_id *sid = section_ids + i;
+		struct lb_cbmem_ref *cbmem_ref;
+		void *cbmem_addr = cbmem_find(sid->cbmem_id);
 
-	tstamp = (struct lb_tstamp *)lb_new_record(header);
-	tstamp->tag = LB_TAG_TIMESTAMPS;
-	tstamp->size = sizeof(*tstamp);
-	tstamp->tstamp_tab = tstamp_table;
+		if (!cbmem_addr)
+			continue;  /* This section is not present */
 
+		cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+		if (!cbmem_ref) {
+			printk(BIOS_ERR, "No more room in coreboot table!\n");
+			break;
+		}
+		cbmem_ref->tag = sid->table_tag;
+		cbmem_ref->size = sizeof(*cbmem_ref);
+		cbmem_ref->cbmem_addr = cbmem_addr;
+	}
 }
-#endif
 
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
@@ -633,9 +651,28 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+<<<<<<< HEAD
 #if CONFIG_COLLECT_TIMESTAMPS
 	lb_tsamp(head);
 #endif
+=======
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+#endif
+#if CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head, serial);
+#endif
+	add_cbmem_pointers(head);
+
+>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table.
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 46d6489..5535a38 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -196,11 +196,13 @@ struct lb_framebuffer {
 };
 
 #define LB_TAG_TIMESTAMPS	0x0016
-struct lb_tstamp {
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+struct lb_cbmem_ref {
 	uint32_t tag;
 	uint32_t size;
 
-	void	*tstamp_tab;
+	void	*cbmem_addr;
 };
 
 /* The following structures are for the cmos definitions table */



From gerrit at coreboot.org  Wed Mar  7 02:13:19 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:19 +0100
Subject: [coreboot] Patch set updated for coreboot: 1121a0d Increase CBMEM
	to accommodate larger console.
References: <If583013dfb210de5028d69577675095c6fe2f3ab+0@gerrit.coreboot.org>
Message-ID: <If583013dfb210de5028d69577675095c6fe2f3ab+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725

-gerrit

commit 1121a0d8314e5d6021c92fa0dd3fccd6d8a0197c
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Oct 4 10:44:16 2011 -0700

    Increase CBMEM to accommodate larger console.
    
    This change adds 128K to the memory amount set aside for CBMEM in
    case the CBMEM console is enabled (to keep the CBMEM 128K byte
    aligned). The console buffer size is being set to 64K, which is
    enough to accommodate the most verbose coreboot console and
    u-boot console.
    
    Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a19ec5a..6a48dd2 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,12 @@
 #define _CBMEM_H_
 
 /* Reserve 128k for ACPI and other tables */
+#if CONFIG_CONSOLE_CBMEM
+#define HIGH_MEMORY_DEF_SIZE	( 256 * 1024 )
+#else
 #define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#endif
+
 #ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
 #endif



From gerrit at coreboot.org  Wed Mar  7 02:13:19 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:19 +0100
Subject: [coreboot] Patch set updated for coreboot: 1e073bf Fix typos in
	src/console/Kconfig
References: <Ia906077257e93622ad56bc54a42f8184ade78b29+0@gerrit.coreboot.org>
Message-ID: <Ia906077257e93622ad56bc54a42f8184ade78b29+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726

-gerrit

commit 1e073bf8e1fe234169f0700af6d738b46d9d1246
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 4 16:21:17 2011 -0700

    Fix typos in src/console/Kconfig
    
    - cash -> Cache
    - make the new size of the cbmem console buffer the default
    
    Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index fefbe2e..2cfc4db 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -201,7 +201,7 @@ config CONSOLE_CBMEM
 config CONSOLE_CBMEM_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
 	hex "Room allocated for console output in CBMEM"
-	default 0xae00
+	default 0x10000
 	help
 	  Space allocated for console output storage in CBMEM. The default
 	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
@@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 
 config CONSOLE_CAR_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
-	hex "Room allocated for console output in cash as RAM"
+	hex "Room allocated for console output in Cache as RAM"
 	default 0xc00
 	help
 	  Console is used before RAM is initialized. This is the room reserved



From gerrit at coreboot.org  Wed Mar  7 02:13:21 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 02:13:21 +0100
Subject: [coreboot] Patch set updated for coreboot: 1450d34 Add
	infrastructure for global data in the CAR phase of boot.
References: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+0@gerrit.coreboot.org>
Message-ID: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+2@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727

-gerrit

commit 1450d34a9a25113a37067ef7ab61f432ced8dee8
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Oct 1 04:27:32 2011 -0700

    Add infrastructure for global data in the CAR phase of boot.
    
    The cbmem console structure and car global data are put in their own section,
    with the cbmem console coming after the global data. These areas are linked
    to be where CAR is available and at the very bottom of the stack.
    
    There is one shortcoming of this change:
    The section created by this change needs to be stripped out by the Makefile
    since leaving it in confuses cbfstool when it installs the stage in the image.
    I would like to make the tools link those symbols at the right location but
    leave allocation of that space out of the ELF.
    
    Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/Makefile.inc      |    2 +-
 src/arch/x86/init/bootblock.ld |    7 +++++++
 src/include/cpu/x86/car.h      |   31 +++++++++++++++++++++++++++++++
 src/lib/cbmem_console.c        |    7 +++++--
 4 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 624b510..aeb4875 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	rm -f $@
 	cp $(obj)/coreboot.pre1 $@
 	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
-            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index bde0430..6f8ade8 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -51,5 +51,12 @@ SECTIONS
 		*(.eh_frame);
 	}
 
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h
new file mode 100644
index 0000000..2d2af03
--- /dev/null
+++ b/src/include/cpu/x86/car.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef CPU_X86_CAR_H
+#define CPU_X86_CAR_H
+
+#ifdef __PRE_RAM__
+#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\", at nobits#")))
+#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\", at nobits#")))
+#else
+#define CAR_GLOBAL
+#define CAR_CBMEM
+#endif
+
+#endif
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index b58de48..431ea1f 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <cbmem.h>
+#include <cpu/x86/car.h>
 #include <string.h>
 
 /*
@@ -39,7 +40,9 @@ struct cbmem_console {
  * ram space is used for the console buffer storage. The size and location of
  * the area are defined in the config.
  */
-#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+static struct cbmem_console car_cbmem_console CAR_CBMEM;
+#define cbmem_console_p (&car_cbmem_console)
 
 /*
  * Once DRAM is initialized and the cache as ram mode is disabled, while still
@@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data)
 	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
 	 * actual console buffer is.
 	 */
-	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+	if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console)
 		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
 #endif
 	if (!cbm_cons_p)



From gerrit at coreboot.org  Wed Mar  7 08:31:01 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 08:31:01 +0100
Subject: [coreboot] Patch set updated for coreboot: aa352de selfboot: drop
	dead code
References: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+0@gerrit.coreboot.org>
Message-ID: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/768

-gerrit

commit aa352de0cd09bdf80f5898eefd4537400ed7cc66
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 14:07:39 2012 -0800

    selfboot: drop dead code
    
    As a left over from elfboot times, selfboot keeps the segments to
    load in the order in which they appeared in the original file as
    well as in the order they will later appear in memory. This is not
    needed in selfboot, so drop the code and structure members that handle
    the in-file order.
    
    Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |   25 ++++---------------------
 1 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index fe56653..c45fa63 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -45,8 +45,6 @@ static const unsigned long lb_end = (unsigned long)&_eram_seg;
 struct segment {
 	struct segment *next;
 	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
 	unsigned long s_dstaddr;
 	unsigned long s_srcaddr;
 	unsigned long s_memsz;
@@ -226,11 +224,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg->prev;
 			seg->prev->next = new;
 			seg->prev = new;
-			/* Order by original program header order */
-			new->phdr_next = seg;
-			new->phdr_prev = seg->phdr_prev;
-			seg->phdr_prev->phdr_next = new;
-			seg->phdr_prev = new;
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
@@ -266,11 +259,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg)
 			new->prev = seg;
 			seg->next->prev = new;
 			seg->next = new;
-			/* Order by original program header order */
-			new->phdr_next = seg->phdr_next;
-			new->phdr_prev = seg;
-			seg->phdr_next->phdr_prev = new;
-			seg->phdr_next = new;
 
 			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
@@ -304,7 +292,6 @@ static int build_self_segment_list(
 	struct segment *ptr;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
 	head->next = head->prev = head;
 	first_segment = segment = &payload->segments;
 
@@ -367,9 +354,10 @@ static int build_self_segment_list(
 			return -1;
 		}
 
+		/* We have found another CODE, DATA or BSS segment */
 		segment++;
 
-		// FIXME: Explain what this is
+		/* Find place where to insert our segment */
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohll(segment->load_addr))
 				break;
@@ -380,12 +368,6 @@ static int build_self_segment_list(
 		new->prev = ptr->prev;
 		ptr->prev->next = new;
 		ptr->prev = new;
-
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
 	}
 
 	return 1;
@@ -400,7 +382,8 @@ static int load_self_segments(
 
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		if (!overlaps_coreboot(ptr)) continue;
+		if (!overlaps_coreboot(ptr))
+			continue;
 		if (ptr->s_dstaddr + ptr->s_memsz > bounce_high)
 			bounce_high = ptr->s_dstaddr + ptr->s_memsz;
 	}



From gerrit at coreboot.org  Wed Mar  7 09:27:43 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 09:27:43 +0100
Subject: [coreboot] Patch set updated for coreboot: 017a78a correctly mark
	code segments as code in SELF
References: <I82eaad23f08c02f4ed75744affa8835255cf5c17+0@gerrit.coreboot.org>
Message-ID: <I82eaad23f08c02f4ed75744affa8835255cf5c17+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/767

-gerrit

commit 017a78ac20a97394921f53b29875f0ec76c73a9b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 12:40:14 2012 -0800

    correctly mark code segments as code in SELF
    
    In bios_log, find that the first segment of the payload is shown
    as code rather than data.
    
    Sample:
           Got a payload
           Loading segment from rom address 0xfff29378
             code (compression=1)
           ...
    
    Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbfstool/cbfs-mkpayload.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index ff6479d..e4ef5c8 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -161,7 +161,10 @@ int parse_elf_to_payload(unsigned char *input, unsigned char **output,
 			continue;
 		}
 
-		segs[segments].type = PAYLOAD_SEGMENT_DATA;
+		if (phdr[i].p_flags & PF_X)
+			segs[segments].type = PAYLOAD_SEGMENT_CODE;
+		else
+			segs[segments].type = PAYLOAD_SEGMENT_DATA;
 		segs[segments].load_addr = (uint64_t)htonll(phdr[i].p_paddr);
 		segs[segments].mem_len = (uint32_t)htonl(phdr[i].p_memsz);
 		segs[segments].compression = htonl(algo);



From gerrit at coreboot.org  Wed Mar  7 09:41:57 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 09:41:57 +0100
Subject: [coreboot] Patch set updated for coreboot: 74b3208 use movsl for
	copying resume memory back
References: <Ibab0b478873912d67bf1f07743f628586353368a+0@gerrit.coreboot.org>
Message-ID: <Ibab0b478873912d67bf1f07743f628586353368a+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755

-gerrit

commit 74b3208ebd54eb195dcd7c65b9f5bbf9b96e88a1
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:03:38 2011 -0800

    use movsl for copying resume memory back
    
    It's not significantly faster, but easier to read and smaller.
    
    Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/wakeup.S |   20 ++++----------------
 1 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..f12b176 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
 	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)



From gerrit at coreboot.org  Wed Mar  7 13:06:42 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 13:06:42 +0100
Subject: [coreboot] Patch set updated for coreboot: 95dc6ef Unify IO APIC
	address specification
References: <I3941c1ff62972ce56a5bc466eab7134f901773d3+0@gerrit.coreboot.org>
Message-ID: <I3941c1ff62972ce56a5bc466eab7134f901773d3+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/677

-gerrit

commit 95dc6efcd0601d90a4a3ea89ce44f4293b78a11b
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Thu Feb 16 18:54:37 2012 +0100

    Unify IO APIC address specification
    
    Some places still hardcoded the address instead of using IO_APIC_ADDR.
    
    Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/mainboard/amd/torpedo/platform_cfg.h       |    2 +-
 src/mainboard/iwave/iWRainbowG6/mptable.c      |    2 +-
 src/northbridge/intel/i945/acpi/hostbridge.asl |    3 ++-
 src/northbridge/intel/sch/acpi/hostbridge.asl  |    3 ++-
 src/southbridge/amd/cimx/sb700/lpc.c           |    5 +++--
 src/southbridge/amd/cimx/sb800/lpc.c           |    5 +++--
 src/southbridge/amd/cimx/sb900/lpc.c           |    5 +++--
 src/southbridge/amd/sb800/lpc.c                |    4 ++--
 src/southbridge/amd/sb800/sm.c                 |    8 +++-----
 src/southbridge/intel/sch/lpc.c                |    5 +++--
 10 files changed, 23 insertions(+), 19 deletions(-)

diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index d97d034..cf31c6a 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -137,7 +137,7 @@
  *   @section WatchDogTimerBase
  */
 // #ifndef WATCHDOG_TIMER_BASE_ADDRESS
-//   #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
+//   #define WATCHDOG_TIMER_BASE_ADDRESS IO_APIC_ADDR
 // #endif
 
 /**
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index 953f16a..87de022 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -34,7 +34,7 @@ void *smp_write_config_table(void *v)
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &isa_bus);
 
-	smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
 	{
 		device_t dev;
 		struct resource *res;
diff --git a/src/northbridge/intel/i945/acpi/hostbridge.asl b/src/northbridge/intel/i945/acpi/hostbridge.asl
index a76d8e2..8dcadd7 100644
--- a/src/northbridge/intel/i945/acpi/hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/hostbridge.asl
@@ -19,6 +19,7 @@
  * MA 02110-1301 USA
  */
 
+#include <arch/ioapic.h>
 
 Name(_HID,EISAID("PNP0A08"))	// PCIe
 Name(_CID,EISAID("PNP0A03"))	// PCI
@@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				IO_APIC_ADDR,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/northbridge/intel/sch/acpi/hostbridge.asl b/src/northbridge/intel/sch/acpi/hostbridge.asl
index 7e92a0e..44a8be0 100644
--- a/src/northbridge/intel/sch/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sch/acpi/hostbridge.asl
@@ -19,6 +19,7 @@
  * MA 02110-1301 USA
  */
 
+#include <arch/ioapic.h>
 
 Name(_HID,EISAID("PNP0A08"))	// PCIe
 Name(_CID,EISAID("PNP0A03"))	// PCI
@@ -211,7 +212,7 @@ Method (_CRS, 0, Serialized)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
 				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				IO_APIC_ADDR,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
index e43193a..7157a55 100644
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ b/src/southbridge/amd/cimx/sb700/lpc.c
@@ -21,6 +21,7 @@
 #include "lpc.h"
 #include <bitops.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <console/console.h>	/* printk */
 #include <cbmem.h>
 
@@ -61,8 +62,8 @@ void lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = 0xfec00000;
+	res = new_resource(dev, 3);
+	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index bc643b5..856b8b3 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <device/pci.h>
+#include <arch/ioapic.h>
 #include "lpc.h"
 
 
@@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = 0xfec00000;
+	res = new_resource(dev, 3);
+	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 48bfe36..9873d37 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include "lpc.h"
 #include <console/console.h>	/* printk */
+#include <arch/ioapic.h>
 
 
 void lpc_read_resources(device_t dev)
@@ -45,8 +46,8 @@ void lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = 0xfec00000;
+	res = new_resource(dev, 3);
+	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 6b72a62..4e2031f 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -91,8 +91,8 @@ static void sb800_lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	//res = new_resource(dev, 3); /* IOAPIC */
-	//res->base = 0xfec00000;
+	//res = new_resource(dev, 3);
+	//res->base = IO_APIC_ADDR;
 	//res->size = 0x00001000;
 	//res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 9347c42..50a8f0b 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -84,16 +84,14 @@
 static void sm_init(device_t dev)
 {
 	u8 byte;
-	u32 ioapic_base;
 
 	printk(BIOS_INFO, "sm_init().\n");
 
-	ioapic_base = 0xFEC00000;//pci_read_config32(dev, 0x74) & (0xffffffe0);	/* some like mem resource, but does not have  enable bit */
 	/* Don't rename APIC ID */
 	/* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8.
 	 * We need to check out why and change back. */
-	clear_ioapic(ioapic_base);
-	//setup_ioapic(ioapic_base, 0);
+	clear_ioapic(IO_APIC_ADDR);
+	//setup_ioapic(IO_APIC_ADDR, 0);
 
 	/* enable serial irq */
 	byte = pm_ioread(0x54);
@@ -277,7 +275,7 @@ static void sb800_sm_read_resources(device_t dev)
 
 	/* apic */
 	res = new_resource(dev, 0x74);
-	res->base  = 0xfec00000;
+	res->base  = IO_APIC_ADDR;
 	res->size = 256 * 0x10;
 	res->limit = 0xFEFFFFFUL;	/* res->base + res->size -1; */
 	res->align = 8;
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index ab180bb..977e01b 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -23,6 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include "chip.h"
 
 /* SCH LPC defines */
@@ -164,8 +165,8 @@ static void sch_lpc_read_resources(device_t dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
-	res = new_resource(dev, 3); /* IOAPIC */
-	res->base = 0xfec00000;
+	res = new_resource(dev, 3);
+	res->base = IO_APIC_ADDR;
 	res->size = 0x00001000;
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }



From gerrit at coreboot.org  Wed Mar  7 13:06:51 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 13:06:51 +0100
Subject: [coreboot] Patch set updated for coreboot: 962d508 Unify Local APIC
	address definitions
References: <I1d4be73b1984f22b7e84681edfadf0588a7589b6+0@gerrit.coreboot.org>
Message-ID: <I1d4be73b1984f22b7e84681edfadf0588a7589b6+3@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/676

-gerrit

commit 962d50868d9c91a4c8c8a9c78a6bd9cc59d516e3
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Thu Feb 16 18:43:25 2012 +0100

    Unify Local APIC address definitions
    
    We used several names for that same value, and hardcoded the value
    at some more places.
    
    They're all LOCAL_APIC_ADDR now (except for lapic specific code
    that still uses LAPIC_DEFAULT_BASE).
    
    Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 Makefile.inc                                       |    2 +-
 src/arch/x86/boot/acpi.c                           |    3 +--
 src/arch/x86/include/arch/ioapic.h                 |    4 +++-
 src/arch/x86/include/arch/smp/mpspec.h             |    5 ++---
 src/include/cpu/x86/lapic_def.h                    |    3 ++-
 src/mainboard/advansus/a785e-i/mptable.c           |    2 +-
 src/mainboard/amd/bimini_fam10/mptable.c           |    2 +-
 src/mainboard/amd/dbm690t/mptable.c                |    2 +-
 src/mainboard/amd/dinar/mptable.c                  |    2 +-
 src/mainboard/amd/inagua/mptable.c                 |    2 +-
 src/mainboard/amd/mahogany/mptable.c               |    2 +-
 src/mainboard/amd/mahogany_fam10/mptable.c         |    2 +-
 src/mainboard/amd/persimmon/mptable.c              |    2 +-
 src/mainboard/amd/pistachio/mptable.c              |    2 +-
 .../amd/serengeti_cheetah/acpi/amd8111_isa.asl     |    7 +++++--
 src/mainboard/amd/serengeti_cheetah/mptable.c      |    2 +-
 .../serengeti_cheetah_fam10/acpi/amd8111_isa.asl   |    7 +++++--
 .../amd/serengeti_cheetah_fam10/mptable.c          |    2 +-
 src/mainboard/amd/south_station/mptable.c          |    2 +-
 src/mainboard/amd/tilapia_fam10/mptable.c          |    2 +-
 src/mainboard/amd/torpedo/mptable.c                |    2 +-
 src/mainboard/amd/union_station/mptable.c          |    2 +-
 src/mainboard/arima/hdama/mptable.c                |    2 +-
 src/mainboard/asrock/939a785gmh/mptable.c          |    2 +-
 src/mainboard/asrock/e350m1/mptable.c              |    2 +-
 src/mainboard/asus/a8n_e/mptable.c                 |    2 +-
 src/mainboard/asus/a8v-e_deluxe/mptable.c          |    2 +-
 src/mainboard/asus/a8v-e_se/mptable.c              |    2 +-
 src/mainboard/asus/k8v-x/mptable.c                 |    2 +-
 src/mainboard/asus/m2n-e/mptable.c                 |    2 +-
 src/mainboard/asus/m2v/mptable.c                   |    2 +-
 src/mainboard/asus/m4a78-em/mptable.c              |    2 +-
 src/mainboard/asus/m4a785-m/mptable.c              |    2 +-
 src/mainboard/asus/m5a88-v/mptable.c               |    2 +-
 src/mainboard/asus/p2b-d/mptable.c                 |    2 +-
 src/mainboard/asus/p2b-ds/mptable.c                |    2 +-
 src/mainboard/avalue/eax-785e/mptable.c            |    2 +-
 src/mainboard/broadcom/blast/mptable.c             |    2 +-
 src/mainboard/dell/s1850/mptable.c                 |    2 +-
 src/mainboard/emulation/qemu-x86/northbridge.c     |    3 ++-
 src/mainboard/getac/p470/mptable.c                 |    2 +-
 src/mainboard/gigabyte/ga_2761gxdk/mptable.c       |    2 +-
 src/mainboard/gigabyte/m57sli/mptable.c            |    2 +-
 src/mainboard/gigabyte/ma785gmt/mptable.c          |    2 +-
 src/mainboard/gigabyte/ma78gm/mptable.c            |    2 +-
 src/mainboard/hp/dl145_g1/mptable.c                |    2 +-
 src/mainboard/hp/dl145_g3/mptable.c                |    2 +-
 src/mainboard/hp/dl165_g6_fam10/mptable.c          |    2 +-
 src/mainboard/ibase/mb899/mptable.c                |    2 +-
 src/mainboard/ibm/e325/mptable.c                   |    2 +-
 src/mainboard/ibm/e326/mptable.c                   |    2 +-
 src/mainboard/iei/kino-780am2-fam10/mptable.c      |    2 +-
 src/mainboard/intel/d945gclf/mptable.c             |    2 +-
 src/mainboard/intel/eagleheights/mptable.c         |    2 +-
 src/mainboard/intel/jarrell/mptable.c              |    2 +-
 src/mainboard/intel/mtarvon/mptable.c              |    2 +-
 src/mainboard/intel/truxton/mptable.c              |    2 +-
 src/mainboard/intel/xe7501devkit/mptable.c         |    2 +-
 src/mainboard/iwave/iWRainbowG6/mptable.c          |    2 +-
 src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl   |    7 +++++--
 src/mainboard/iwill/dk8_htx/mptable.c              |    2 +-
 src/mainboard/iwill/dk8s2/mptable.c                |    2 +-
 src/mainboard/iwill/dk8x/mptable.c                 |    2 +-
 src/mainboard/jetway/pa78vm5/mptable.c             |    2 +-
 src/mainboard/kontron/986lcd-m/mptable.c           |    2 +-
 src/mainboard/kontron/kt690/mptable.c              |    2 +-
 src/mainboard/lenovo/t60/mptable.c                 |    2 +-
 src/mainboard/lenovo/x60/mptable.c                 |    2 +-
 src/mainboard/msi/ms7135/mptable.c                 |    2 +-
 src/mainboard/msi/ms7260/mptable.c                 |    2 +-
 src/mainboard/msi/ms9185/mptable.c                 |    2 +-
 src/mainboard/msi/ms9282/mptable.c                 |    2 +-
 src/mainboard/msi/ms9652_fam10/mptable.c           |    2 +-
 src/mainboard/newisys/khepri/mptable.c             |    2 +-
 src/mainboard/nvidia/l1_2pvv/mptable.c             |    2 +-
 src/mainboard/roda/rk886ex/mptable.c               |    2 +-
 src/mainboard/siemens/sitemp_g1p1/dsdt.asl         |    6 ++++--
 src/mainboard/siemens/sitemp_g1p1/mptable.c        |    2 +-
 src/mainboard/sunw/ultra40/mptable.c               |    2 +-
 src/mainboard/supermicro/h8dme/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr/mptable.c           |    2 +-
 src/mainboard/supermicro/h8dmr_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8qgi/mptable.c           |    2 +-
 src/mainboard/supermicro/h8qme_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/h8scm_fam10/mptable.c     |    2 +-
 src/mainboard/supermicro/x6dai_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g/mptable.c         |    2 +-
 src/mainboard/supermicro/x6dhe_g2/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig/mptable.c        |    2 +-
 src/mainboard/supermicro/x6dhr_ig2/mptable.c       |    2 +-
 src/mainboard/technexion/tim5690/mptable.c         |    2 +-
 src/mainboard/technexion/tim8690/mptable.c         |    2 +-
 src/mainboard/tyan/s2735/mptable.c                 |    2 +-
 src/mainboard/tyan/s2850/mptable.c                 |    2 +-
 src/mainboard/tyan/s2875/mptable.c                 |    2 +-
 src/mainboard/tyan/s2880/mptable.c                 |    2 +-
 src/mainboard/tyan/s2881/mptable.c                 |    2 +-
 src/mainboard/tyan/s2882/mptable.c                 |    2 +-
 src/mainboard/tyan/s2885/mptable.c                 |    2 +-
 src/mainboard/tyan/s2891/mptable.c                 |    2 +-
 src/mainboard/tyan/s2892/mptable.c                 |    2 +-
 src/mainboard/tyan/s2895/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912/mptable.c                 |    2 +-
 src/mainboard/tyan/s2912_fam10/mptable.c           |    2 +-
 src/mainboard/tyan/s4880/mptable.c                 |    2 +-
 src/mainboard/tyan/s4882/mptable.c                 |    2 +-
 src/mainboard/via/epia-n/mainboard.c               |    3 ++-
 src/mainboard/via/epia-n/mptable.c                 |    2 +-
 src/mainboard/via/pc2500e/mptable.c                |    2 +-
 src/mainboard/via/vt8454c/mptable.c                |    2 +-
 110 files changed, 131 insertions(+), 117 deletions(-)

diff --git a/Makefile.inc b/Makefile.inc
index 2f61a45..e495f45 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -69,7 +69,7 @@ romstage-c-deps:=$$(OPTION_TABLE_H)
 define ramstage-objs_asl_template
 $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
-	$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
+	$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-y)/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
 	cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$(basename $$@)).asl
 	mv $$(basename $$@).hex $$(basename $$@).c
 	$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..168933a 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,7 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#include <cpu/x86/lapic_def.h>
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -188,8 +189,6 @@ int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu,
 
 void acpi_create_madt(acpi_madt_t *madt)
 {
-#define LOCAL_APIC_ADDR	0xfee00000ULL
-
 	acpi_header_t *header = &(madt->header);
 	unsigned long current = (unsigned long)madt + sizeof(acpi_madt_t);
 
diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h
index 623f617..5d7e196 100644
--- a/src/arch/x86/include/arch/ioapic.h
+++ b/src/arch/x86/include/arch/ioapic.h
@@ -20,7 +20,7 @@
 #ifndef __I386_ARCH_IOAPIC_H
 #define __I386_ARCH_IOAPIC_H
 
-#define IO_APIC_ADDR	0xfec00000UL
+#define IO_APIC_ADDR	0xfec00000
 #define IO_APIC_INTERRUPTS 24
 
 #define ALL		(0xff << 24)
@@ -38,7 +38,9 @@
 #define SMI		(2 << 8)
 #define INT		(1 << 8)
 
+#ifndef __ACPI__
 void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
 void clear_ioapic(u32 ioapic_base);
+#endif
 
 #endif
diff --git a/src/arch/x86/include/arch/smp/mpspec.h b/src/arch/x86/include/arch/smp/mpspec.h
index 2eb1813..e5e6195 100644
--- a/src/arch/x86/include/arch/smp/mpspec.h
+++ b/src/arch/x86/include/arch/smp/mpspec.h
@@ -2,6 +2,8 @@
 #define __ASM_MPSPEC_H
 
 #include <device/device.h>
+#include <cpu/x86/lapic_def.h>
+
 /*
  * Structure definitions for SMP machines following the
  * Intel Multiprocessing Specification 1.1 and 1.4.
@@ -229,9 +231,6 @@ struct mp_exten_compatibility_address_space {
 	 */
 } __attribute__((packed));
 
-/* Default local apic addr */
-#define LAPIC_ADDR 0xFEE00000
-
 void mptable_init(struct mp_config_table *mc, u32 lapic_addr);
 
 void *smp_next_mpc_entry(struct mp_config_table *mc);
diff --git a/src/include/cpu/x86/lapic_def.h b/src/include/cpu/x86/lapic_def.h
index 6035273..f96b53b 100644
--- a/src/include/cpu/x86/lapic_def.h
+++ b/src/include/cpu/x86/lapic_def.h
@@ -6,7 +6,8 @@
 #define LAPIC_BASE_MSR_ENABLE (1 << 11)
 #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000
 
-#define LAPIC_DEFAULT_BASE 0xfee00000
+#define LOCAL_APIC_ADDR 0xfee00000
+#define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR
 
 #define LAPIC_ID		0x020
 #define LAPIC_LVR	0x030
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index 6504049..8643320 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index 2ab3f24..ae81411 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index 901591a..cf98ae3 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c
index b43080d..4938be0 100644
--- a/src/mainboard/amd/dinar/mptable.c
+++ b/src/mainboard/amd/dinar/mptable.c
@@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v)
 	u32 dword;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	get_bus_conf();
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index b339348..b5a507f 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -55,7 +55,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 	memcpy(mc->mpc_oem, "AMD     ", 8);
 
 	smp_write_processors(mc);
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index f79a579..dabd2ed 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index b1a658b..c56952e 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 18a7707..61ddef1 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 	memcpy(mc->mpc_oem, "AMD	 ", 8);
 
 	smp_write_processors(mc);
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index 901591a..cf98ae3 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl
index 0f7efc9..56c0a16 100644
--- a/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl
+++ b/src/mainboard/amd/serengeti_cheetah/acpi/amd8111_isa.asl
@@ -1,3 +1,6 @@
+#include <arch/ioapic.h>
+#include <cpu/x86/lapic_def.h>
+
 /*
  * Copyright 2005 AMD
  */
@@ -125,9 +128,9 @@
                         {
                             Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
                             Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
-                            Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+                            Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
                             Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
-                            Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+                            Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
                             Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
                             Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
                             Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index ebd4cbc..4214408 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl
index f00069f..3b79453 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi/amd8111_isa.asl
@@ -17,6 +17,9 @@
 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 //
 
+#include <arch/ioapic.h>
+#include <cpu/x86/lapic_def.h>
+
 //AMD8111 isa
 
 	Device (ISA)
@@ -141,9 +144,9 @@
 				{
 					Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
 					Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
-					Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+					Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
 					Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
-					Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+					Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
 					Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
 					Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
 					Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index d527f9c..e90b348 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 5242f69..99004b3 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
+  mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
   smp_write_processors(mc);
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 4bf3480..4a276fb 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 97db2b9..936a417 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -84,7 +84,7 @@ static void *smp_write_config_table(void *v)
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
+  mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
   /*Inagua used dure core cpu with one die */
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 5242f69..99004b3 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -51,7 +51,7 @@ static void *smp_write_config_table(void *v)
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
+  mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "AMD     ", 8);
 
   smp_write_processors(mc);
diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c
index 466ba88..f67327e 100644
--- a/src/mainboard/arima/hdama/mptable.c
+++ b/src/mainboard/arima/hdama/mptable.c
@@ -75,7 +75,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index 95b1271..c0ca550 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index de9d7f4..7e8c947 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -50,7 +50,7 @@ static void *smp_write_config_table(void *v)
 
   mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-  mptable_init(mc, LAPIC_ADDR);
+  mptable_init(mc, LOCAL_APIC_ADDR);
   memcpy(mc->mpc_oem, "ASROCK  ", 8);
 
   smp_write_processors(mc);
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 349ae74..9defdb5 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index 999dd6c..eb7790f 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 999dd6c..eb7790f 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 673dfbe..48eee71 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
index 29b9d07..680dfa7 100644
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ b/src/mainboard/asus/m2n-e/mptable.c
@@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
index 5dc340a..e6e600a 100644
--- a/src/mainboard/asus/m2v/mptable.c
+++ b/src/mainboard/asus/m2v/mptable.c
@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &bus_isa);
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 4bf3480..4a276fb 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 4bf3480..4a276fb 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index 516b915..ac8ed5e 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b-d/mptable.c
index 43f3a85..4eed581 100644
--- a/src/mainboard/asus/p2b-d/mptable.c
+++ b/src/mainboard/asus/p2b-d/mptable.c
@@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c
index 153c62c..5333418 100644
--- a/src/mainboard/asus/p2b-ds/mptable.c
+++ b/src/mainboard/asus/p2b-ds/mptable.c
@@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 021f635..6f541a0 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index b747d2e..5a1bf28 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/dell/s1850/mptable.c b/src/mainboard/dell/s1850/mptable.c
index a71dab0..0c7562c 100644
--- a/src/mainboard/dell/s1850/mptable.c
+++ b/src/mainboard/dell/s1850/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index 3f22437..b961e8b 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -1,4 +1,5 @@
 #include <console/console.h>
+#include <cpu/x86/lapic_def.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <stdint.h>
@@ -80,7 +81,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	/* Reserve space for the LAPIC.  There's one in every processor, but
 	 * the space only needs to be reserved once, so we do it here. */
 	res = new_resource(dev, 3);
-	res->base = 0xfee00000UL;
+	res->base = LOCAL_APIC_ADDR;
 	res->size = 0x10000UL;
 	res->limit = 0xffffffffUL;
 	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c
index 5954c97..9b59bb4 100644
--- a/src/mainboard/getac/p470/mptable.c
+++ b/src/mainboard/getac/p470/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index b52cda9..914b25a 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 5aa7e61..f493514 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 4bf3480..4a276fb 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 4bf3480..4a276fb 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index e33f681..35dedde 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 466b7fc..609432a 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -47,7 +47,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index c246721..00234a3 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -48,7 +48,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/ibase/mb899/mptable.c b/src/mainboard/ibase/mb899/mptable.c
index 0ff1896..1baf728 100644
--- a/src/mainboard/ibase/mb899/mptable.c
+++ b/src/mainboard/ibase/mb899/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/ibm/e325/mptable.c b/src/mainboard/ibm/e325/mptable.c
index 6431f32..7d1b8f3 100644
--- a/src/mainboard/ibm/e325/mptable.c
+++ b/src/mainboard/ibm/e325/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/ibm/e326/mptable.c b/src/mainboard/ibm/e326/mptable.c
index e81bf8f..b963a0c 100644
--- a/src/mainboard/ibm/e326/mptable.c
+++ b/src/mainboard/ibm/e326/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 66423e5..a26fbde 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index ab537cb..b0360bf 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -32,7 +32,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 8571864..809feec 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -78,7 +78,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/jarrell/mptable.c b/src/mainboard/intel/jarrell/mptable.c
index b665703..6662329 100644
--- a/src/mainboard/intel/jarrell/mptable.c
+++ b/src/mainboard/intel/jarrell/mptable.c
@@ -19,7 +19,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 0c025f0..364d077 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 506a1d0..0cc8f6b 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 99fd5af..cc7eda5 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -122,7 +122,7 @@ static void *smp_write_config_table(void* v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/iwave/iWRainbowG6/mptable.c b/src/mainboard/iwave/iWRainbowG6/mptable.c
index bf94b8c..953f16a 100644
--- a/src/mainboard/iwave/iWRainbowG6/mptable.c
+++ b/src/mainboard/iwave/iWRainbowG6/mptable.c
@@ -29,7 +29,7 @@ void *smp_write_config_table(void *v)
 	int isa_bus;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &isa_bus);
diff --git a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl
index 0f7efc9..56c0a16 100644
--- a/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl
+++ b/src/mainboard/iwill/dk8_htx/acpi/amd8111_isa.asl
@@ -1,3 +1,6 @@
+#include <arch/ioapic.h>
+#include <cpu/x86/lapic_def.h>
+
 /*
  * Copyright 2005 AMD
  */
@@ -125,9 +128,9 @@
                         {
                             Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
                             Memory32Fixed (ReadWrite, 0x000C0000, 0x00010000) // video BIOS c0000-c8404
-                            Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+                            Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000)
                             Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
-                            Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+                            Memory32Fixed (ReadWrite, LOCAL_APIC_ADDR, 0x00001000)
                             Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
                             Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
                             Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index fd53bd7..3977673 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -18,7 +18,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/iwill/dk8s2/mptable.c b/src/mainboard/iwill/dk8s2/mptable.c
index d78ce20..f22fd9d 100644
--- a/src/mainboard/iwill/dk8s2/mptable.c
+++ b/src/mainboard/iwill/dk8s2/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/iwill/dk8x/mptable.c b/src/mainboard/iwill/dk8x/mptable.c
index d78ce20..f22fd9d 100644
--- a/src/mainboard/iwill/dk8x/mptable.c
+++ b/src/mainboard/iwill/dk8x/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index 11b4357..b8caa23 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/kontron/986lcd-m/mptable.c b/src/mainboard/kontron/986lcd-m/mptable.c
index ab63b45..03f7370 100644
--- a/src/mainboard/kontron/986lcd-m/mptable.c
+++ b/src/mainboard/kontron/986lcd-m/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 21a0d05..4ffba6f 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/lenovo/t60/mptable.c b/src/mainboard/lenovo/t60/mptable.c
index a74aca8..312e30d 100644
--- a/src/mainboard/lenovo/t60/mptable.c
+++ b/src/mainboard/lenovo/t60/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/lenovo/x60/mptable.c b/src/mainboard/lenovo/x60/mptable.c
index 0ce10ed..f21e76f 100644
--- a/src/mainboard/lenovo/x60/mptable.c
+++ b/src/mainboard/lenovo/x60/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/msi/ms7135/mptable.c b/src/mainboard/msi/ms7135/mptable.c
index 4262af1..7d7ba53 100644
--- a/src/mainboard/msi/ms7135/mptable.c
+++ b/src/mainboard/msi/ms7135/mptable.c
@@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &bus_isa);
diff --git a/src/mainboard/msi/ms7260/mptable.c b/src/mainboard/msi/ms7260/mptable.c
index bef81ef..41f5bf7 100644
--- a/src/mainboard/msi/ms7260/mptable.c
+++ b/src/mainboard/msi/ms7260/mptable.c
@@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index 0f97dca..fe65d7d 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/msi/ms9282/mptable.c b/src/mainboard/msi/ms9282/mptable.c
index baba6b5..0559844 100644
--- a/src/mainboard/msi/ms9282/mptable.c
+++ b/src/mainboard/msi/ms9282/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 5e45380..35d1172 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/newisys/khepri/mptable.c b/src/mainboard/newisys/khepri/mptable.c
index 4017fce..8ee6e15 100644
--- a/src/mainboard/newisys/khepri/mptable.c
+++ b/src/mainboard/newisys/khepri/mptable.c
@@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/nvidia/l1_2pvv/mptable.c b/src/mainboard/nvidia/l1_2pvv/mptable.c
index 5d13701..b7e1a88 100644
--- a/src/mainboard/nvidia/l1_2pvv/mptable.c
+++ b/src/mainboard/nvidia/l1_2pvv/mptable.c
@@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/roda/rk886ex/mptable.c b/src/mainboard/roda/rk886ex/mptable.c
index 5954c97..9b59bb4 100644
--- a/src/mainboard/roda/rk886ex/mptable.c
+++ b/src/mainboard/roda/rk886ex/mptable.c
@@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
index 8ad0f82..e03e665 100644
--- a/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
+++ b/src/mainboard/siemens/sitemp_g1p1/dsdt.asl
@@ -18,6 +18,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
+#include <arch/ioapic.h>
+#include <cpu/x86/lapic_def.h>
 
 DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
 {
@@ -418,8 +420,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
                     CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
                     If (PCIF)
                     {
-                        Store (0xFEC00000, MB01)
-                        Store (0xFEE00000, MB02)
+                        Store (IO_APIC_ADDR, MB01)
+                        Store (LOCAL_APIC_ADDR, MB02)
                         Store (0x1000, ML01)
                         Store (0x1000, ML02)
                     }
diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c
index ba2c1e4..dc98382 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mptable.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 	int isa_bus;
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 	smp_write_processors(mc);
 
 	get_bus_conf();
diff --git a/src/mainboard/sunw/ultra40/mptable.c b/src/mainboard/sunw/ultra40/mptable.c
index c00c4b8..1ba1dcf 100644
--- a/src/mainboard/sunw/ultra40/mptable.c
+++ b/src/mainboard/sunw/ultra40/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/h8dme/mptable.c b/src/mainboard/supermicro/h8dme/mptable.c
index cdbe7d6..93fea87 100644
--- a/src/mainboard/supermicro/h8dme/mptable.c
+++ b/src/mainboard/supermicro/h8dme/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/h8dmr/mptable.c b/src/mainboard/supermicro/h8dmr/mptable.c
index 734fac9..f54e18f 100644
--- a/src/mainboard/supermicro/h8dmr/mptable.c
+++ b/src/mainboard/supermicro/h8dmr/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index f2ee7a8..6ed5840 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c
index 92771bd..61a7bd4 100644
--- a/src/mainboard/supermicro/h8qgi/mptable.c
+++ b/src/mainboard/supermicro/h8qgi/mptable.c
@@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v)
 	u32 dword;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	get_bus_conf();
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 2e7c4af..e6d4280 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index b2c1c92..0c75d1a 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/x6dai_g/mptable.c b/src/mainboard/supermicro/x6dai_g/mptable.c
index acd719d..6ba5309 100644
--- a/src/mainboard/supermicro/x6dai_g/mptable.c
+++ b/src/mainboard/supermicro/x6dai_g/mptable.c
@@ -13,7 +13,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/x6dhe_g/mptable.c b/src/mainboard/supermicro/x6dhe_g/mptable.c
index f5f4100..4504d34 100644
--- a/src/mainboard/supermicro/x6dhe_g/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g/mptable.c
@@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/x6dhe_g2/mptable.c b/src/mainboard/supermicro/x6dhe_g2/mptable.c
index e39a700..087bb9e 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mptable.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mptable.c
@@ -16,7 +16,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/x6dhr_ig/mptable.c b/src/mainboard/supermicro/x6dhr_ig/mptable.c
index 143138d..5d0a08d 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mptable.c b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
index a374f5c..b6c94d3 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mptable.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mptable.c
@@ -17,7 +17,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 21a0d05..4ffba6f 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 21a0d05..4ffba6f 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -40,7 +40,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 9612a4c..9073728 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -12,7 +12,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &isa_bus);
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 5144cec..08027f4 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -53,7 +53,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
         {
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 67de027..c3765f2 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index e0058fa..2d34c8b 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2881/mptable.c b/src/mainboard/tyan/s2881/mptable.c
index 80b35bc..7df5e87 100644
--- a/src/mainboard/tyan/s2881/mptable.c
+++ b/src/mainboard/tyan/s2881/mptable.c
@@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index b028abb..47c39a7 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -58,7 +58,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
         {
diff --git a/src/mainboard/tyan/s2885/mptable.c b/src/mainboard/tyan/s2885/mptable.c
index fc5109f..26081c7 100644
--- a/src/mainboard/tyan/s2885/mptable.c
+++ b/src/mainboard/tyan/s2885/mptable.c
@@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c
index 12d6e78..cb49434 100644
--- a/src/mainboard/tyan/s2891/mptable.c
+++ b/src/mainboard/tyan/s2891/mptable.c
@@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2892/mptable.c b/src/mainboard/tyan/s2892/mptable.c
index 7af319a..882ac69 100644
--- a/src/mainboard/tyan/s2892/mptable.c
+++ b/src/mainboard/tyan/s2892/mptable.c
@@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2895/mptable.c b/src/mainboard/tyan/s2895/mptable.c
index a383cb2..20fa92c 100644
--- a/src/mainboard/tyan/s2895/mptable.c
+++ b/src/mainboard/tyan/s2895/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2912/mptable.c b/src/mainboard/tyan/s2912/mptable.c
index 49720dc..9fe7ab7 100644
--- a/src/mainboard/tyan/s2912/mptable.c
+++ b/src/mainboard/tyan/s2912/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 393362b..8b5f365 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index 6646718..9111a63 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index c1da3e5..bca26a0 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -57,7 +57,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
 
diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c
index 9227f0a..6e11a00 100644
--- a/src/mainboard/via/epia-n/mainboard.c
+++ b/src/mainboard/via/epia-n/mainboard.c
@@ -25,6 +25,7 @@
 #include <boot/tables.h>
 #include <arch/ioapic.h>
 #include <southbridge/via/vt8237r/vt8237r.h>
+#include <cpu/x86/lapic_def.h>
 #include "chip.h"
 
 int add_mainboard_resources(struct lb_memory *mem)
@@ -33,7 +34,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		IO_APIC_ADDR, 0x1000);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
-		0xFEE00000ULL, 0x1000);
+		LOCAL_APIC_ADDR, 0x1000);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		0xFFFF0000ULL, 0x10000);
 #endif
diff --git a/src/mainboard/via/epia-n/mptable.c b/src/mainboard/via/epia-n/mptable.c
index c7c554a..de25d0e 100644
--- a/src/mainboard/via/epia-n/mptable.c
+++ b/src/mainboard/via/epia-n/mptable.c
@@ -14,7 +14,7 @@ static void *smp_write_config_table(void *v)
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
         smp_write_processors(mc);
         mptable_write_buses(mc, NULL, &isa_bus);
diff --git a/src/mainboard/via/pc2500e/mptable.c b/src/mainboard/via/pc2500e/mptable.c
index 939f21d..fa69bbe 100644
--- a/src/mainboard/via/pc2500e/mptable.c
+++ b/src/mainboard/via/pc2500e/mptable.c
@@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &isa_bus);
diff --git a/src/mainboard/via/vt8454c/mptable.c b/src/mainboard/via/vt8454c/mptable.c
index 575237f..fc9cb99 100644
--- a/src/mainboard/via/vt8454c/mptable.c
+++ b/src/mainboard/via/vt8454c/mptable.c
@@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v)
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
-	mptable_init(mc, LAPIC_ADDR);
+	mptable_init(mc, LOCAL_APIC_ADDR);
 
 	smp_write_processors(mc);
 	mptable_write_buses(mc, NULL, &isa_bus);



From ajg4tadpole at gmail.com  Wed Mar  7 13:05:07 2012
From: ajg4tadpole at gmail.com (Andrew Goodbody)
Date: Wed, 07 Mar 2012 12:05:07 +0000
Subject: [coreboot] New patch to review for coreboot: 73b5bba Prepare
 the BIOS data areas before device init.
In-Reply-To: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+1@gerrit.coreboot.org>
References: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+0@gerrit.coreboot.org>
	<I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+1@gerrit.coreboot.org>
Message-ID: <4F574EF3.7020407@gmail.com>

On 07/03/12 01:06, Stefan Reinauer (stefan.reinauer at coreboot.org) wrote:
>      NEW/FIXED now reads consistent values:
>      ebda_addr=0xf6000 lowmem=0x100000

OK, now this worries me. Any time you move away from the classic PC 
memory map you are risking problems.

0xe0000-0xfffff would normally be for shadowed firmware.
0xc0000-0xdffff would normally be for option ROMS
0xa0000-0xbffff would normally be for legacy VGA memory

So I would expect to see the EBDA at 0x9c000 for 1KB and hence the top 
of usable real mode memory to be at 0x9ffff. Now I may be speaking out 
of turn as I have no idea how coreboot organises its memory map or how 
that relates to SeaBIOS etc. but unless you can guarantee that no 
software that will run on this machine will be upset by your values I 
would suggest sticking with the classic legacy values instead.

Andrew



From jakllsch at kollasch.net  Wed Mar  7 13:37:31 2012
From: jakllsch at kollasch.net (Jonathan A. Kollasch)
Date: Wed, 7 Mar 2012 06:37:31 -0600
Subject: [coreboot] New patch to review for coreboot: 73b5bba Prepare
 the BIOS data areas before device init.
In-Reply-To: <4F574EF3.7020407@gmail.com>
References: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+0@gerrit.coreboot.org>
	<I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+1@gerrit.coreboot.org>
	<4F574EF3.7020407@gmail.com>
Message-ID: <20120307123731.GC16379@tazenda.kollasch.net>

On Wed, Mar 07, 2012 at 12:05:07PM +0000, Andrew Goodbody wrote:
> On 07/03/12 01:06, Stefan Reinauer (stefan.reinauer at coreboot.org) wrote:
> >     NEW/FIXED now reads consistent values:
> >     ebda_addr=0xf6000 lowmem=0x100000
> 
> OK, now this worries me. Any time you move away from the classic PC
> memory map you are risking problems.

First of all, INITIAL_EBDA_SEGMENT has been 0xF600 prior to this change.

I believe loading a SeaBIOS payload will obliterate the coreboot EBDA at
this location.  SeaBIOS almost certainly replaces/updates the BDA and
will position its own EBDA at an appropriate place.

	Jonathan Kollasch



From gerrit at coreboot.org  Wed Mar  7 14:20:11 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 14:20:11 +0100
Subject: [coreboot] Patch merged into coreboot/master: aa352de selfboot:
	drop dead code
References: <I6be7a3a1bdf717fec1ee8e5b3227c63150580b41+0@gerrit.coreboot.org>
Message-ID: <E1S5Gmp-0005pw-1U@ra.coresystems.de>

the following patch was just integrated into master:
commit aa352de0cd09bdf80f5898eefd4537400ed7cc66
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 14:07:39 2012 -0800

    selfboot: drop dead code
    
    As a left over from elfboot times, selfboot keeps the segments to
    load in the order in which they appeared in the original file as
    well as in the order they will later appear in memory. This is not
    needed in selfboot, so drop the code and structure members that handle
    the in-file order.
    
    Change-Id: I6be7a3a1bdf717fec1ee8e5b3227c63150580b41
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Wed Mar  7 14:18:13 2012, giving +2
See http://review.coreboot.org/768 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 14:20:14 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 14:20:14 +0100
Subject: [coreboot] Patch merged into coreboot/master: 017a78a correctly
	mark code segments as code in SELF
References: <I82eaad23f08c02f4ed75744affa8835255cf5c17+0@gerrit.coreboot.org>
Message-ID: <E1S5Gms-0005wE-8p@ra.coresystems.de>

the following patch was just integrated into master:
commit 017a78ac20a97394921f53b29875f0ec76c73a9b
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Jan 11 12:40:14 2012 -0800

    correctly mark code segments as code in SELF
    
    In bios_log, find that the first segment of the payload is shown
    as code rather than data.
    
    Sample:
           Got a payload
           Loading segment from rom address 0xfff29378
             code (compression=1)
           ...
    
    Change-Id: I82eaad23f08c02f4ed75744affa8835255cf5c17
    Signed-off-by: Stefan Reinauer <reinauer at google.com>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Wed Mar  7 14:18:30 2012, giving +2
See http://review.coreboot.org/767 for details.

-gerrit



From ajg4tadpole at gmail.com  Wed Mar  7 14:24:12 2012
From: ajg4tadpole at gmail.com (Andrew Goodbody)
Date: Wed, 07 Mar 2012 13:24:12 +0000
Subject: [coreboot] New patch to review for coreboot: 73b5bba Prepare
 the BIOS data areas before device init.
In-Reply-To: <20120307123731.GC16379@tazenda.kollasch.net>
References: <I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+0@gerrit.coreboot.org>
	<I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949+1@gerrit.coreboot.org>
	<4F574EF3.7020407@gmail.com>
	<20120307123731.GC16379@tazenda.kollasch.net>
Message-ID: <4F57617C.2090503@gmail.com>

On 07/03/12 12:37, Jonathan A. Kollasch wrote:
> First of all, INITIAL_EBDA_SEGMENT has been 0xF600 prior to this change.

OK, I guess it works then. At least most of the time anyway.

> I believe loading a SeaBIOS payload will obliterate the coreboot EBDA at
> this location.  SeaBIOS almost certainly replaces/updates the BDA and
> will position its own EBDA at an appropriate place.

I guess there is no need to go back to coreboot code at that point so 
this is OK. It just seems to me that it would be neater and more 
consistent if the EBDA were in an appropriate place to begin with.

What is the reason to have it up at 0xf6000? Linux will boot happily 
with it at 0x9c000 or even somewhat lower, as it must to boot with a 
standard BIOS.

Andrew



From towardsoss at gmail.com  Wed Mar  7 14:13:54 2012
From: towardsoss at gmail.com (Niklas Cholmkvist)
Date: Wed, 07 Mar 2012 15:13:54 +0200
Subject: [coreboot] RSS/Atom feed for commits on review.coreboot.org
Message-ID: <4F575F12.6050701@gmail.com>

Hi,

is there any rss or atom feed for commits or any other contributions
made on gerrit?
-- 
Niklas Cholmkvist

Public GPG/PGP key block
ID:           1024D/C09E670B
Fingerprint:  8487 ECE3 8ED9 870B BB56  95E7 9AD2 946A C09E 670B
Key download:
https://sites.google.com/site/towardsfloss/main-page/NiklasCholmkvist.asc
[For authenticity and privacy on the internet with prime number based
mathematics]

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From peter at stuge.se  Wed Mar  7 15:02:52 2012
From: peter at stuge.se (Peter Stuge)
Date: Wed, 7 Mar 2012 15:02:52 +0100
Subject: [coreboot] RSS/Atom feed for commits on review.coreboot.org
In-Reply-To: <4F575F12.6050701@gmail.com>
References: <4F575F12.6050701@gmail.com>
Message-ID: <20120307140252.29005.qmail@stuge.se>

Hi,

Niklas Cholmkvist wrote:
> is there any rss or atom feed for commits or any other
> contributions made on gerrit?

You can get RSS for merged commits via gitweb:

http://review.coreboot.org/gitweb?p=coreboot.git

Links are at the bottom of the page.

It doesn't look like Gerrit has an RSS feed though.


//Peter
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From kevin at koconnor.net  Wed Mar  7 14:47:03 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 7 Mar 2012 08:47:03 -0500
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <CAP6exYLVJMMM-9aW8k24j4m_y5me7sZZsPKKGuJgRCdDJm_Fxg@mail.gmail.com>
References: <4F5286F0.9050903@gmail.com>
	<20120305095656.GD11392@xivo-clients.proformatique.com>
	<CAP6exYLVJMMM-9aW8k24j4m_y5me7sZZsPKKGuJgRCdDJm_Fxg@mail.gmail.com>
Message-ID: <20120307134703.GA7267@morn.localdomain>

On Mon, Mar 05, 2012 at 04:01:45PM -0800, ron minnich wrote:
> I'm seeing the ld problem on all my linux systems.

What distro do you have?  This got fixed in Fedora updates at least.

I would normally work around build tool defects (and have done so on
many occasions).  Unfortunately, this LD one is too severe.  The issue
is that SeaBIOS needs to have certain tables and code entry points at
specific memory locations - this is a requirement for compatibility.
The SeaBIOS build generates an LD script to locate the appropriate
sections at the correct addresses.  Unfortunately, the broken version
of LD gets confused with alignment and refuses to place data at the
locations they need to be.  Not much that can be done - any solution
would effectively require not using LD - might as well write our own
LD (with the limited requirements of seabios) than try to work around
it.

-Kevin



From gerrit at coreboot.org  Wed Mar  7 15:58:10 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 15:58:10 +0100
Subject: [coreboot] New patch to review for coreboot: cc2b317 lint: test
	that labels begin at start-of-line
References: <Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2+0@gerrit.coreboot.org>
Message-ID: <Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/771

-gerrit

commit cc2b3173570a49dae0c780c1e1b8d2e12a0f5975
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Mar 7 15:49:07 2012 +0100

    lint: test that labels begin at start-of-line
    
    Some attempt at enforcing style
    
    Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 util/lint/lint-004-style-labels |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/util/lint/lint-004-style-labels b/util/lint/lint-004-style-labels
new file mode 100755
index 0000000..31ad74e
--- /dev/null
+++ b/util/lint/lint-004-style-labels
@@ -0,0 +1,22 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Patrick Georgi <patrick at georgi-clan.de>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# DESCR: Check that C labels begin at start-of-line
+
+LC_ALL=C export LC_ALL
+find src -name '*.[scS]' -exec grep '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' {} + |grep -v "[^a-z_]default:"



From gerrit at coreboot.org  Wed Mar  7 15:58:11 2012
From: gerrit at coreboot.org (Patrick Georgi (patrick@georgi-clan.de))
Date: Wed, 7 Mar 2012 15:58:11 +0100
Subject: [coreboot] New patch to review for coreboot: f7a8b4e Move C labels
	to start-of-line
References: <Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f+0@gerrit.coreboot.org>
Message-ID: <Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f+1@gerrit.coreboot.org>

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/772

-gerrit

commit f7a8b4e8327349825c0c2e51d44e3dd323372cb1
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Mar 7 15:55:47 2012 +0100

    Move C labels to start-of-line
    
    Also mark the corresponding lint test stable.
    
    Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
 src/arch/x86/boot/mpspec.c                    |    2 +-
 src/arch/x86/lib/cpu.c                        |    2 +-
 src/boot/selfboot.c                           |    2 +-
 src/console/vtxprintf.c                       |    2 +-
 src/cpu/x86/lapic/secondary.S                 |    2 +-
 src/devices/oprom/yabel/pmm.c                 |    2 +-
 src/lib/xmodem.c                              |    2 +-
 src/northbridge/amd/amdk8/raminit.c           |    2 +-
 src/northbridge/amd/amdk8/raminit_f.c         |    6 +++---
 src/northbridge/amd/amdk8/raminit_test.c      |    2 +-
 src/northbridge/intel/e7520/raminit.c         |    6 +++---
 src/northbridge/intel/e7525/raminit.c         |    6 +++---
 src/northbridge/intel/i3100/raminit.c         |    6 +++---
 src/northbridge/intel/i3100/raminit_ep80579.c |    2 +-
 src/northbridge/intel/i945/raminit.c          |    2 +-
 src/southbridge/amd/cs5536/early_smbus.c      |    2 +-
 util/lint/lint-004-style-labels               |   22 ----------------------
 util/lint/lint-stable-004-style-labels        |   22 ++++++++++++++++++++++
 18 files changed, 46 insertions(+), 46 deletions(-)

diff --git a/src/arch/x86/boot/mpspec.c b/src/arch/x86/boot/mpspec.c
index d519cfa..e7d767b 100644
--- a/src/arch/x86/boot/mpspec.c
+++ b/src/arch/x86/boot/mpspec.c
@@ -267,7 +267,7 @@ void smp_write_intsrc_pci_bridge(struct mp_config_table *mc,
 				smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x);
 			}
 
-		next:
+next:
 			child = child->sibling;
 		}
 
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 8aacaac..a7f7b32 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -227,7 +227,7 @@ static void set_cpu_ops(struct device *cpu)
 		}
 	}
 	return;
- found:
+found:
 	cpu->ops = driver->ops;
 }
 
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index c45fa63..99b1493 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -511,7 +511,7 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
 
- out:
+out:
 	return 0;
 }
 
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index 944fd5b..4053023 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -123,7 +123,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args
 
 		/* process flags */
 		flags = 0;
-		repeat:
+repeat:
 			++fmt;		/* this also skips first '%' */
 			switch (*fmt) {
 				case '-': flags |= LEFT; goto repeat;
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 5c1e760..dc00b08 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -47,7 +47,7 @@ _secondary_start:
 1:	hlt
 	jmp	1b
 
-	gdtaddr:
+gdtaddr:
 	.word   gdt_limit	/* the table limit */
 	.long   gdt             /* we know the offset */
 
diff --git a/src/devices/oprom/yabel/pmm.c b/src/devices/oprom/yabel/pmm.c
index 989bde4..19d14d4 100644
--- a/src/devices/oprom/yabel/pmm.c
+++ b/src/devices/oprom/yabel/pmm.c
@@ -267,7 +267,7 @@ void pmm_handleInt()
 		rval = 0xFFFFFFFF;
 		goto exit;
 	}
-      exit:
+exit:
 	/* exit handler of this function, restore registers, put return value in DX:AX */
 	M.x86 = backup_regs;
 	M.x86.R_DX = (u16) ((rval >> 16) & 0xFFFF);
diff --git a/src/lib/xmodem.c b/src/lib/xmodem.c
index 2d553be..a00653a 100644
--- a/src/lib/xmodem.c
+++ b/src/lib/xmodem.c
@@ -166,7 +166,7 @@ int xmodemReceive(unsigned char *dest, int destsz)
 			_outbyte(ACK);
 			continue;
 		}
-	reject:
+reject:
 		flushinput();
 		_outbyte(NAK);
 	}
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index eb33a39..9cb7c60 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -681,7 +681,7 @@ hw_err:
 #if CONFIG_QRANK_DIMM_SUPPORT
 	sz.rank = 0;
 #endif
- out:
+out:
 	return sz;
 }
 
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index dc3addb..33df485 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -49,7 +49,7 @@
 	/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
 	 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
 	/*
-		index:
+index:
 		[29: 0] DctOffset (Dram Controller Offset)
 		[30:30] DctAccessWrite (Dram Controller Read/Write Select)
 			0 = read access
@@ -659,7 +659,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
 	/* for PCI_ADDR(0, 0x18, 2, 0x98) index,
 	 and PCI_ADDR(0x, 0x18, 2, 0x9c) data */
 	/*
-		index:
+index:
 		[29: 0] DctOffset (Dram Controller Offset)
 		[30:30] DctAccessWrite (Dram Controller Read/Write Select)
 			0 = read access
@@ -820,7 +820,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
 	sz->col = 0;
 	sz->bank = 0;
 	sz->rank = 0;
- out:
+out:
 	return;
 }
 
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index e2a13a3..fd2107c 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -419,7 +419,7 @@ static void do_test2(int i)
 
 	raminit_main();
 
- done:
+done:
 	memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
 }
 
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index e9a60f1..d226085 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -161,7 +161,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	return sz;
 
 }
@@ -286,7 +286,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	dra = 0;
- out:
+out:
 	return dra;
 
 }
@@ -658,7 +658,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	drc = 0;
- out:
+out:
 	return drc;
 }
 
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index e341596..b5895bc 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -164,7 +164,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
 hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	return sz;
 
 }
@@ -291,7 +291,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	dra = 0;
- out:
+out:
 	return dra;
 
 }
@@ -664,7 +664,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	drc = 0;
- out:
+out:
 	return drc;
 }
 
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index ced3de1..926d5b3 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -154,7 +154,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
  hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	return sz;
 
 }
@@ -281,7 +281,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	dra = 0;
- out:
+out:
 	return dra;
 
 }
@@ -597,7 +597,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	drc = 0;
- out:
+out:
 	return drc;
 }
 
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index de3ffce..79fc5f7 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -126,7 +126,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
  hw_err:
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	print_debug("dimm ");
 	print_debug_hex8(device);
 	print_debug(" size = ");
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index d92c006..a4512d7 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1478,7 +1478,7 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno
 	 */
 	sz.side1 = 0;
 	sz.side2 = 0;
- out:
+out:
 	return sz;
 }
 
diff --git a/src/southbridge/amd/cs5536/early_smbus.c b/src/southbridge/amd/cs5536/early_smbus.c
index 5cb815d..814bc5a 100644
--- a/src/southbridge/amd/cs5536/early_smbus.c
+++ b/src/southbridge/amd/cs5536/early_smbus.c
@@ -194,7 +194,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
 
 	return smbus_get_result(smbus_io_base);
 
-      err:
+err:
 	print_debug("SMBUS READ ERROR:");
 	print_debug_hex8(error);
 	print_debug(" device:");
diff --git a/util/lint/lint-004-style-labels b/util/lint/lint-004-style-labels
deleted file mode 100755
index 31ad74e..0000000
--- a/util/lint/lint-004-style-labels
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/bin/sh
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Patrick Georgi <patrick at georgi-clan.de>
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-#
-# DESCR: Check that C labels begin at start-of-line
-
-LC_ALL=C export LC_ALL
-find src -name '*.[scS]' -exec grep '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' {} + |grep -v "[^a-z_]default:"
diff --git a/util/lint/lint-stable-004-style-labels b/util/lint/lint-stable-004-style-labels
new file mode 100755
index 0000000..31ad74e
--- /dev/null
+++ b/util/lint/lint-stable-004-style-labels
@@ -0,0 +1,22 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Patrick Georgi <patrick at georgi-clan.de>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+# DESCR: Check that C labels begin at start-of-line
+
+LC_ALL=C export LC_ALL
+find src -name '*.[scS]' -exec grep '^[[:space:]][[:space:]]*[a-z][a-z]*:[[:space:]]*$' {} + |grep -v "[^a-z_]default:"



From oliver at schinagl.nl  Wed Mar  7 16:28:59 2012
From: oliver at schinagl.nl (Oliver Schinagl)
Date: Wed, 07 Mar 2012 16:28:59 +0100
Subject: [coreboot] Dual SPI Flash
In-Reply-To: <20120306183339.713.qmail@stuge.se>
References: <4F460122.9000304@schinagl.nl> <20120223131646.4021.qmail@stuge.se>
	<4F55D059.7080203@schinagl.nl>
	<20120306085546.14938.qmail@stuge.se> <4F55D4AB.20805@schinagl.nl>
	<20120306092229.17022.qmail@stuge.se>
	<4F55DBCE.3090300@schinagl.nl>
	<20120306094259.18684.qmail@stuge.se>
	<0776ab61c8dc620d2507f6d442fa1454@webmail.schinagl.nl>
	<20120306183339.713.qmail@stuge.se>
Message-ID: <4F577EBB.7000305@schinagl.nl>

On 06-03-12 19:33, Peter Stuge wrote:
> Oliver Schinagl wrote:
>> Pin 1, 'chip select enable' is an inverted? pin. enables and
>> disables device operation. When chip select is high, the device is
>> de-selected and the serial data pins are at 'high impedance'.
> Correct.
>
>
>> So if I understand all this correctly, the chip can be
>> connected in parallel with the exception of the Chip Select Enable.
>> A simple switch to either connect it directly to the
>> board/socket/other end and toggle it to connect to ground (via
>> 'some' resistor').
> Right. This is what you can see demonstrated in the photos linked to
> at the bottom of http://stuge.se/m57sli/ i.e.:
>
> http://stuge.se/m57sli/overview.jpg
> http://stuge.se/m57sli/U5.jpg
> http://stuge.se/m57sli/U9.jpg
>
> These photos are not from a PC mainboard but the principle hopefully
> shows. The connection you describe is indeed how GIGABYTE boards
> implement Dual BIOS. What is not shown in my photos are the
> resistors, which are mounted onto the GIGABYTE board on pads for that
> very purpose.
After this mail-conversation, those images make perfect sense!
>
>
>> I tried to make a simple schematic in ascii, but failed horribly so i've
>> attached it to this message as monochrome BMP (only format that I could
>> quickly think of to be smallest in size).
> Hint: png
I thought I tried and came out to 54kb, I redid them in this new version 
and it is only 998 bytes! Nice!
>
>
>> I don't know what value those resistors need to be (and if the
>> schematic can be even more simplified, with a single resistor), but
>> I belive this is the schematic used for the dual-SPI flash 'module'
> Not quite, the resistors need to be pull-up and not pull-down. See
> e.g. http://stuge.se/flash_switch.png which shows the principle with
> resistors, but connects the switch common to GND, instead of to the
> mainboard as must be done.
Hmm, I made a new 'design' and I put the common of the switch to the 
GND, but you say it should connect to the motherboard? Why is this?
>
>> This seems sensible to me, but my knowledge in
>> this field is very limited.
> You're already learning more. Your schematic is correct, but
> resistors need to pull up to 3.3V and not down to GND. The values
> are, as I wrote earlier, not really critical, just don't go too
> much under 1k or you will potentially waste some current.
>
> Also make sure that your switch is the break-before-make type.
Learn I did, I'll now try to learn some gEDA and design a basic PCB for 
this purpose!
>
> //Peter
>
-------------- next part --------------
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From gerrit at coreboot.org  Wed Mar  7 16:41:46 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Wed, 7 Mar 2012 16:41:46 +0100
Subject: [coreboot] Patch set updated for filo: dfc652a Fix some compiler
	warnings
References: <I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299+0@gerrit.coreboot.org>
Message-ID: <I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299+2@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/747

-gerrit

commit dfc652ad783639baabc71e83b2ac76a583c08975
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 16:10:27 2012 +0100

    Fix some compiler warnings
    
    The makefile cleanup brought up quite a few compiler warnings about
    unused functions and/or variables, undefined behaviour, missing return
    values and type mismatches. Fix those.
    
    Change-Id: I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 drivers/flash/lxflash.c |   14 ++------------
 fs/blockdev.c           |   14 +++++++-------
 fs/fsys_cramfs.c        |    6 +++---
 fs/fsys_ext2fs.c        |    5 ++---
 fs/fsys_xfs.c           |    2 +-
 fs/mini_inflate.c       |    5 ++++-
 i386/wince_load.c       |    2 +-
 include/fs.h            |    2 +-
 main/grub/builtins.c    |    6 +++---
 main/grub/completions.c |    2 +-
 main/grub/grub.c        |    2 ++
 11 files changed, 27 insertions(+), 33 deletions(-)

diff --git a/drivers/flash/lxflash.c b/drivers/flash/lxflash.c
index ba76741..df18c8d 100644
--- a/drivers/flash/lxflash.c
+++ b/drivers/flash/lxflash.c
@@ -345,16 +345,6 @@ static __inline void NAND_writeByte(u8 b)
 	outb(b, g_baseAddr + IO_NAND_DATA);
 }
 
-static void NAND_writeData(u8 *pData, int nSize)
-{
-	int i;
-	if(nSize > 528) return;	// oversized buffer?
-
-	// write byte by byte, pedestrian way
-	for(i=0; i<nSize; i++)
-		NAND_writeByte(pData[i]);
-}
-
 ////////////////////////////////////////////////////////////////////////////////
 //
 // NAND_getStatus()
@@ -521,7 +511,7 @@ __inline int IsECCWritten(u8 *pECC)
 ////////////////////////////////////////////////////////////////////////////////
 // 
 
-int NAND_close(void)
+void NAND_close(void)
 {
 	if (g_chipID >= 0)
 		wrmsr(MSR_DIVIL_LBAR_FLSH0 + g_chipID, g_orig_flsh);
@@ -650,7 +640,7 @@ int NAND_readPage(u32 pageAddr, u8 *pPageBuff)
 	// sanity check
 	if (pageAddr < (g_flashInfo.numBlocks * g_flashInfo.pagesPerBlock))
 	{
-		u8 bData = 0, bBadBlock = 0, bReserved = 0;
+		u8 bBadBlock = 0, bReserved = 0;
 
 		u8 addr1 = (u8)(pageAddr & 0xff);
 		u8 addr2 = (u8)((pageAddr >> 8) & 0xff);
diff --git a/fs/blockdev.c b/fs/blockdev.c
index 21d2c29..e1e9d57 100644
--- a/fs/blockdev.c
+++ b/fs/blockdev.c
@@ -385,8 +385,10 @@ static void *read_sector(unsigned long sector)
 			int count = (NUM_CACHE-hash>8)?8:(NUM_CACHE-hash);
 			int ret;
 			ret = ide_read_blocks(dev_drive, sector, count, buf);
-			if (ret == 2)
-				goto nomedium;
+			if (ret == 2) {
+				printf("No disk in drive.\n");
+				goto err_out;
+			}
 			if (ret != 0)
 				goto readerr;
 			while (--count>0) {
@@ -426,11 +428,9 @@ static void *read_sector(unsigned long sector)
       readerr:
 	printf("Disk read error dev=%d drive=%d sector=%lu\n",
 	       dev_type, dev_drive, sector);
-	flush_cache();
-	dev_name[0] = '\0';	/* force re-open the device next time */
-	return 0;
-      nomedium:
-	printf("No disk in drive.\n");
+#ifdef CONFIG_IDE_NEW_DISK
+      err_out:
+#endif
 	flush_cache();
 	dev_name[0] = '\0';	/* force re-open the device next time */
 	return 0;
diff --git a/fs/fsys_cramfs.c b/fs/fsys_cramfs.c
index c5a9247..d7cb19b 100644
--- a/fs/fsys_cramfs.c
+++ b/fs/fsys_cramfs.c
@@ -103,8 +103,8 @@ struct cramfs_buf {
 	struct cramfs_inode inode;
 	char name[NAMELEN_MAX + 1];
 	u32 block_ptrs[CRAMFS_MAX_BLOCKS];
-	char data[CRAMFS_BLOCK * 2];
-	char temp[CRAMFS_BLOCK];
+	unsigned char data[CRAMFS_BLOCK * 2];
+	unsigned char temp[CRAMFS_BLOCK];
 	/* menu.lst is read 1 byte at a time, try to aleviate *
 	 * the performance problem */
 	long cached_block;		/* the uncompressed block in cramfs_buf->data */
@@ -246,7 +246,7 @@ cramfs_read (char *buf, int len)
 				memcpy(buf, cramfs_buf->temp + (filepos % CRAMFS_BLOCK), size);		
 		} else  {
 			/* just another full block read */
-			size = decompress_block(buf, cramfs_buf->data + 2, memcpy);
+			size = decompress_block((unsigned char *)buf, cramfs_buf->data + 2, memcpy);
 		}
 		if (size < 0) {
 			debug_cramfs("error in decomp (error %d)\n", size);
diff --git a/fs/fsys_ext2fs.c b/fs/fsys_ext2fs.c
index 30a78ec..96e2e68 100644
--- a/fs/fsys_ext2fs.c
+++ b/fs/fsys_ext2fs.c
@@ -631,10 +631,9 @@ static int
 ext4fs_block_map (int logical_block)
 {
   struct ext4_extent_header *eh;
-  struct ext4_extent *ex, *extent;
-  struct ext4_extent_idx *ei, *index;
+  struct ext4_extent_idx *ei;
+  struct ext4_extent *ex;
   int depth;
-  int i;
 
 #ifdef E2DEBUG
   unsigned char *i;
diff --git a/fs/fsys_xfs.c b/fs/fsys_xfs.c
index 4011479..c71af98 100644
--- a/fs/fsys_xfs.c
+++ b/fs/fsys_xfs.c
@@ -365,7 +365,7 @@ next_dentry (xfs_ino_t *ino)
 		default:
 			namelen = sfe->namelen;
 			*ino = sf_ino ((char *)sfe, namelen);
-			name = sfe->name;
+			name = (char *) sfe->name;
 			sfe = (xfs_dir2_sf_entry_t *)
 				  ((char *)sfe + namelen + 11 - xfs.i8param);
 		}
diff --git a/fs/mini_inflate.c b/fs/mini_inflate.c
index 17e3390..eae371d 100644
--- a/fs/mini_inflate.c
+++ b/fs/mini_inflate.c
@@ -185,7 +185,10 @@ static void decompress_huffman(struct bitstream *stream, unsigned char *dest)
 				dist += (symbol % 2) << ((symbol - 2) >> 1);
 			}
 			stream->decoded += length;
-			for (i = 0; i < length; i++) *(dest++) = dest[-dist];
+			for (i = 0; i < length; i++) {
+				*dest = dest[-dist];
+				dest++;
+			}
 		}
 	} while (symbol != 256); /* 256 is the end of the data block */
 }
diff --git a/i386/wince_load.c b/i386/wince_load.c
index f3e5475..993815f 100644
--- a/i386/wince_load.c
+++ b/i386/wince_load.c
@@ -240,7 +240,7 @@ void wince_init_bootarg(u32 entryPoint)
 	g_pBootArgs->dwEdbgBaseAddr = 0;
 
 	// set the KITL device name to something adequate
-	strcpy(g_pBootArgs->szDeviceNameRoot, "FILO");
+	strcpy((char *) g_pBootArgs->szDeviceNameRoot, "FILO");
 
 	g_pBootArgs->dwSig = BOOTARG_SIGNATURE;
 	g_pBootArgs->dwLen = sizeof(BOOT_ARGS);
diff --git a/include/fs.h b/include/fs.h
index 1bd8ec7..3138ab5 100644
--- a/include/fs.h
+++ b/include/fs.h
@@ -46,7 +46,7 @@ int usb_read(const int drive, const sector_t sector, const int size, void *buffe
 #ifdef CONFIG_FLASH_DISK
 int flash_probe(int drive);
 int flash_read(int drive, sector_t sector, void *buffer);
-int NAND_close(void);
+void NAND_close(void);
 #endif
 
 #define DISK_IDE 1
diff --git a/main/grub/builtins.c b/main/grub/builtins.c
index e2f4612..3451071 100644
--- a/main/grub/builtins.c
+++ b/main/grub/builtins.c
@@ -379,9 +379,9 @@ static int dumpmem_func(char *arg, int flags)
 	}
 
 	// FIXME
-	if (!safe_parse_maxint(&string_argv[1], &mem_base))
+	if (!safe_parse_maxint(&string_argv[1], (int *)&mem_base))
 		return 1;
-	if (!safe_parse_maxint(&string_argv[2], &mem_len))
+	if (!safe_parse_maxint(&string_argv[2], (int *)&mem_len))
 		return 1;
 
 	grub_printf("Dumping memory at 0x%08x (0x%x bytes)\n",
@@ -668,7 +668,7 @@ void copy_path_to_filo_bootline(char *arg, char *path, int use_rootdev, int appe
 	char drivername[16];
 	int disk, part;
 	unsigned long addr;
-	int i, len;
+	int i;
 
 	memset(devicename, 0, 16);
 	memset(drivername, 0, 16);
diff --git a/main/grub/completions.c b/main/grub/completions.c
index a3aeba2..abfe1d9 100644
--- a/main/grub/completions.c
+++ b/main/grub/completions.c
@@ -120,7 +120,7 @@ int print_completions(int is_filename, int is_completion)
 		if (*buf == '(' && (incomplete || ! *ptr)) {
 			if (!part_choice) {
 				/* disk completions */
-				int disk_no, i, j;
+				int i, j;
 
 				if (!is_completion)
 					grub_printf (" Possible disks are: ");
diff --git a/main/grub/grub.c b/main/grub/grub.c
index b4bee04..b629435 100644
--- a/main/grub/grub.c
+++ b/main/grub/grub.c
@@ -201,6 +201,7 @@ old:
 
 }
 
+#ifdef CONFIG_NON_INTERACTIVE
 static void reboot(void) {
 	for (;;) {
 		grub_printf("Press any key to reboot.\n");
@@ -210,6 +211,7 @@ static void reboot(void) {
 		}
 	}
 }
+#endif
 
 /* Define if there is user specified preset menu string */
 /* #undef PRESET_MENU_STRING */



From gerrit at coreboot.org  Wed Mar  7 16:41:46 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Wed, 7 Mar 2012 16:41:46 +0100
Subject: [coreboot] Patch set updated for filo: baf1339 makefile: build
	system cleanup
References: <I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b+0@gerrit.coreboot.org>
Message-ID: <I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b+2@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/746

-gerrit

commit baf1339a1334616c73cbbf9cd7743d54b4a86ff3
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:37:05 2012 +0100

    makefile: build system cleanup
    
    This patch cleans up the include hierarchies for the Makefile system to
    decrease the knowledge of the main Makefile about every subdirectory.
    This allows us to add new drivers without the need to patch the main
    Makefile but, instead, just add a line to the appropriate Makefile.inc.
    
    Also all standard make variables are cleaned up (e.g. CFLAGS,
    CPPFLAGS,..). This, in turn, allows modifying them as needed in the
    included Makefile.inc to add flags or even library dependencies.
    
    It's no Linux Kbuild yet, but we're close ;)
    
    Change-Id: I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile                   |   63 +++++++++++++++++++++-----------------------
 drivers/Makefile.inc       |    5 ++-
 drivers/flash/Makefile.inc |    1 -
 i386/Makefile.inc          |    3 +-
 main/Makefile.inc          |    5 ++-
 main/grub/Makefile.inc     |    2 -
 6 files changed, 38 insertions(+), 41 deletions(-)

diff --git a/Makefile b/Makefile
index 46a265f..20b21bf 100644
--- a/Makefile
+++ b/Makefile
@@ -49,17 +49,27 @@ ifneq ($(Q),)
 endif
 endif
 
+try-run = $(shell set -e;		\
+	TMP=".$$$$.tmp";		\
+	if ($(1)) > /dev/null 2>&1;	\
+	then echo "$(2)";		\
+	else echo "$(3)";		\
+	fi;				\
+	rm -rf "$$TMP")
+
+cc-option = $(call try-run,$(CC) $(1) -S -xc /dev/null -o "$$TMP",$(1),$(2))
+
 $(if $(wildcard .xcompile),,$(shell bash util/xcompile/xcompile > .xcompile))
 include .xcompile
 
-CROSS_PREFIX =
+CROSS_PREFIX ?=
 CC ?= $(CROSS_PREFIX)gcc -m32
 AS ?= $(CROSS_PREFIX)as --32
 LD ?= $(CROSS_PREFIX)ld -belf32-i386
-STRIP ?= $(CROSS_PREFIX)strip
 NM ?= $(CROSS_PREFIX)nm
-HOSTCC = gcc
-HOSTCXX = g++
+STRIP ?= $(CROSS_PREFIX)strip
+HOSTCC ?= gcc
+HOSTCXX ?= g++
 HOSTCFLAGS := -I$(srck) -I$(objk) -pipe
 HOSTCXXFLAGS := -I$(srck) -I$(objk) -pipe
 
@@ -72,45 +82,32 @@ else
 
 include $(src)/.config
 
-ARCHDIR-$(CONFIG_TARGET_I386) := i386
-
-PLATFORM-y += $(ARCHDIR-y)/Makefile.inc
-TARGETS-y :=
-
-BUILD-y := main/Makefile.inc main/grub/Makefile.inc fs/Makefile.inc 
-BUILD-y += drivers/Makefile.inc
-BUILD-y += drivers/flash/Makefile.inc
-
-include $(PLATFORM-y) $(BUILD-y)
-
 LIBPAYLOAD_PREFIX ?= $(obj)/libpayload
 LIBPAYLOAD = $(LIBPAYLOAD_PREFIX)/lib/libpayload.a
 INCPAYLOAD = $(LIBPAYLOAD_PREFIX)/include
 LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+GCCINCDIR = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
 
-OBJS     := $(patsubst %,$(obj)/%,$(TARGETS-y))
-INCLUDES := -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y) -Iinclude -I$(ARCHDIR-y)/include -Ibuild
-INCLUDES += -I$(GCCINCDIR)
+ARCHDIR-$(CONFIG_TARGET_I386) := i386
 
-try-run= $(shell set -e; \
-TMP=".$$$$.tmp"; \
-if ($(1)) > /dev/null 2>&1; \
-then echo "$(2)"; \
-else echo "$(3)"; \
-fi; rm -rf "$$TMP")
+CPPFLAGS := -nostdinc -imacros $(obj)/config.h
+CPPFLAGS += -I$(INCPAYLOAD) -I$(INCPAYLOAD)/$(ARCHDIR-y)
+CPPFLAGS += -I$(ARCHDIR-y)/include -Iinclude -I$(obj)
+CPPFLAGS += -I$(GCCINCDIR)
 
-cc-option= $(call try-run,\
-$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
+CFLAGS := -Wall -Wshadow -Os -pipe
+CFLAGS += -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing
+CFLAGS += $(call cc-option, -fno-stack-protector,)
 
-STACKPROTECT += $(call cc-option, -fno-stack-protector,)
+LIBS := $(LIBPAYLOAD) $(LIBGCC)
 
-GCCINCDIR = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
-CPPFLAGS = -nostdinc -imacros $(obj)/config.h -Iinclude -I$(GCCINCDIR) -MD
-CFLAGS += $(STACKPROTECT) $(INCLUDES) -Wall -Os -fomit-frame-pointer -fno-common -ffreestanding -fno-strict-aliasing -Wshadow -pipe
+SUBDIRS-y += main/ fs/ drivers/
+SUBDIRS-y += $(ARCHDIR-y)/
 
-TARGET  = $(obj)/filo.elf
+$(foreach subdir,$(SUBDIRS-y),$(eval include $(subdir)/Makefile.inc))
 
-HAVE_LIBCONFIG := $(wildcard $(LIBCONFIG_PATH))
+TARGET := $(obj)/filo.elf
+OBJS := $(patsubst %,$(obj)/%,$(TARGETS-y))
 
 
 all: prepare $(TARGET)
@@ -132,7 +129,7 @@ endif
 
 $(obj)/filo: $(OBJS) $(LIBPAYLOAD)
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
-	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
+	$(LD) -N -T $(ARCHDIR-y)/ldscript $(OBJS) --start-group $(LIBS) --end-group -o $@
 
 $(TARGET): $(obj)/filo $(obj)/filo.map
 	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
diff --git a/drivers/Makefile.inc b/drivers/Makefile.inc
index 8f814e0..f93c287 100644
--- a/drivers/Makefile.inc
+++ b/drivers/Makefile.inc
@@ -16,9 +16,10 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
+include drivers/flash/Makefile.inc
+
 TARGETS-$(CONFIG_IDE_DISK) += drivers/ide.o
 TARGETS-$(CONFIG_IDE_NEW_DISK) += drivers/ide_new.o
 TARGETS-$(CONFIG_VIA_SOUND) += drivers/via-sound.o
 TARGETS-$(CONFIG_USB_DISK) += drivers/usb.o
-TARGETS-y += drivers/intel.o
-
+TARGETS-$(CONFIG_TARGET_I386) += drivers/intel.o
diff --git a/drivers/flash/Makefile.inc b/drivers/flash/Makefile.inc
index a862773..48bf1a1 100644
--- a/drivers/flash/Makefile.inc
+++ b/drivers/flash/Makefile.inc
@@ -17,4 +17,3 @@
 #
 
 TARGETS-$(CONFIG_FLASH_DISK) += drivers/flash/lxflash.o
-
diff --git a/i386/Makefile.inc b/i386/Makefile.inc
index 8f1a305..ce3e5c8 100644
--- a/i386/Makefile.inc
+++ b/i386/Makefile.inc
@@ -16,7 +16,8 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-TARGETS-y += i386/context.o i386/switch.S.o i386/segment.o i386/timer.o i386/sys_info.o
+TARGETS-$(CONFIG_TARGET_I386) += i386/context.o i386/switch.S.o i386/segment.o
+TARGETS-$(CONFIG_TARGET_I386) += i386/timer.o i386/sys_info.o
 TARGETS-$(CONFIG_LINUX_LOADER) += i386/linux_load.o
 TARGETS-$(CONFIG_WINCE_LOADER) += i386/wince_load.o
 TARGETS-$(CONFIG_ARTEC_BOOT) += i386/artecboot.o
diff --git a/main/Makefile.inc b/main/Makefile.inc
index e2fab04..fc7c851 100644
--- a/main/Makefile.inc
+++ b/main/Makefile.inc
@@ -16,8 +16,9 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
+include main/grub/Makefile.inc
+
 TARGETS-y += main/filo.o main/strtox.o
 TARGETS-y += main/elfload.o main/ipchecksum.o 
 TARGETS-$(CONFIG_SUPPORT_SOUND) += main/sound.o
-
+TARGETS-$(CONFIG_MULTIBOOT_IMAGE) += main/mb_hdr.o
diff --git a/main/grub/Makefile.inc b/main/grub/Makefile.inc
index b79f08f..00273f3 100644
--- a/main/grub/Makefile.inc
+++ b/main/grub/Makefile.inc
@@ -16,9 +16,7 @@
 # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 #
 
-
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/grub.o main/grub/builtins.o
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/cmdline.o main/grub/char_io.o
 TARGETS-$(CONFIG_USE_GRUB) += main/grub/completions.o
 TARGETS-$(CONFIG_USE_MD5_PASSWORDS) += main/grub/md5.o
-



From gerrit at coreboot.org  Wed Mar  7 16:41:47 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Wed, 7 Mar 2012 16:41:47 +0100
Subject: [coreboot] Patch set updated for filo: 00e82ca makefile: recreate
	version.h only when needed
References: <I27a057be25902233ac0751db8061e9ad4cd50642+0@gerrit.coreboot.org>
Message-ID: <I27a057be25902233ac0751db8061e9ad4cd50642+2@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/745

-gerrit

commit 00e82ca97042907951ee977ead2e93039ab1da6d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:26:48 2012 +0100

    makefile: recreate version.h only when needed
    
    Don't recreate version.h on each make invokation but only when needed, i.e.
    when the make variables have changed. Also make version.h a prerequisite for
    the object files to rebuild them when the version information changes.
    
    Change-Id: I27a057be25902233ac0751db8061e9ad4cd50642
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 3b4a468..46a265f 100644
--- a/Makefile
+++ b/Makefile
@@ -112,8 +112,8 @@ TARGET  = $(obj)/filo.elf
 
 HAVE_LIBCONFIG := $(wildcard $(LIBCONFIG_PATH))
 
-all: prepare $(obj)/version.h $(TARGET)
 
+all: prepare $(TARGET)
 
 HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD))
 ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
@@ -143,7 +143,7 @@ include util/kconfig/Makefile
 $(KCONFIG_AUTOHEADER): $(src)/.config
 	$(MAKE) silentoldconfig
 
-$(OBJS): $(KCONFIG_AUTOHEADER) | libpayload
+$(OBJS): $(KCONFIG_AUTOHEADER) $(obj)/version.h | libpayload
 $(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
@@ -158,7 +158,8 @@ $(obj)/%.map: $(obj)/%
 
 endif
 
-$(obj)/version.h: FORCE
+$(obj)/version.h: Makefile
+	printf "  GEN     $(subst $(shell pwd)/,,$(@))\n"
 	echo '#define PROGRAM_NAME "$(PROGRAM_NAME)"' > $@
 	echo '#define PROGRAM_VERSION "$(PROGRAM_VERSION)"' >> $@
 	echo '#define PROGRAM_VERSION_FULL "$(PROGRAM_VERSION) $(BUILD_INFO)"' >> $@
@@ -171,6 +172,7 @@ prepare: $(sort $(dir $(OBJS))) $(obj)/util/kconfig/lxdialog/
 
 clean:
 	rm -rf $(sort $(dir $(OBJS))) $(obj)/util
+	rm -rf $(obj)/version.h
 
 distclean: clean
 	rm -rf $(obj)



From gerrit at coreboot.org  Wed Mar  7 16:41:47 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Wed, 7 Mar 2012 16:41:47 +0100
Subject: [coreboot] Patch set updated for filo: 1b31017 makefile: avoid
	unnecessary rebuilds
References: <Ifa42362ba1d8c88c9996d645314cfdbdf2994759+0@gerrit.coreboot.org>
Message-ID: <Ifa42362ba1d8c88c9996d645314cfdbdf2994759+2@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/744

-gerrit

commit 1b310177b04d265622ca220ce27f696b41fd786e
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:14:47 2012 +0100

    makefile: avoid unnecessary rebuilds
    
    The make target libpayload is a phony target which makes filo and all
    the object files get rebuild on every make invokation. Avoid this by
    lifting the dependencies and rebuild, i.e. relink filo only when
    libpayload has changed.
    
    Also, when building libpayload as a prerequisite, use $(obj) as DESTDIR,
    as the user might want to use a different build directory then $(src)/build.
    
    Change-Id: Ifa42362ba1d8c88c9996d645314cfdbdf2994759
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Makefile b/Makefile
index 3461614..3b4a468 100644
--- a/Makefile
+++ b/Makefile
@@ -118,18 +118,19 @@ all: prepare $(obj)/version.h $(TARGET)
 HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD))
 ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
 libpayload:
-	@printf "Found Libpayload $(LIBPAYLOAD).\n"
+	@printf "Found libpayload as $(LIBPAYLOAD)\n"
 else
-libpayload: $(src)/$(LIB_CONFIG)
-	printf "building libpayload.\n"
+libpayload: $(LIBPAYLOAD)
+$(LIBPAYLOAD): $(src)/$(LIB_CONFIG)
+	@printf "Building libpayload...\n"
 	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build distclean
 	cp lib.config $(LIBCONFIG_PATH)/.config
 	mkdir -p $(LIBCONFIG_PATH)/build
 	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build oldconfig
-	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(src)/build install
+	$(MAKE) -C $(LIBCONFIG_PATH) obj=$(obj)/libpayload-build DESTDIR=$(obj) install
 endif
 
-$(obj)/filo: $(OBJS) libpayload
+$(obj)/filo: $(OBJS) $(LIBPAYLOAD)
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
@@ -142,7 +143,7 @@ include util/kconfig/Makefile
 $(KCONFIG_AUTOHEADER): $(src)/.config
 	$(MAKE) silentoldconfig
 
-$(OBJS): $(KCONFIG_AUTOHEADER) libpayload
+$(OBJS): $(KCONFIG_AUTOHEADER) | libpayload
 $(obj)/%.o: $(src)/%.c
 	printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) $(CPPFLAGS) -c -o $@ $<
@@ -177,5 +178,4 @@ distclean: clean
 
 FORCE:
 
-.PHONY: $(PHONY) prepare clean distclean FORCE
-
+.PHONY: $(PHONY) prepare clean distclean libpayload FORCE



From gerrit at coreboot.org  Wed Mar  7 16:41:47 2012
From: gerrit at coreboot.org (Mathias Krause (mathias.krause@secunet.com))
Date: Wed, 7 Mar 2012 16:41:47 +0100
Subject: [coreboot] Patch set updated for filo: 348f295 makefile: create
	filo.map in separate step
References: <If010b4ce269a47a99de06db16e0290c3fd90b559+0@gerrit.coreboot.org>
Message-ID: <If010b4ce269a47a99de06db16e0290c3fd90b559+2@gerrit.coreboot.org>

Mathias Krause (mathias.krause at secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/743

-gerrit

commit 348f295d107eeabab00f80dbe371838a355b3e3d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:42:18 2012 +0100

    makefile: create filo.map in separate step
    
    Instead of copying files around and creating files make is not aware of,
    use a dedicated target and rule to create filo.map. Also skip piping the
    result through sort as nm has an option to sort the symbols.
    
    Also drop the bogus dependency to libpayload as filo.elf is only the
    striped version of filo.
    
    Change-Id: If010b4ce269a47a99de06db16e0290c3fd90b559
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>
---
 Makefile |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 6603612..3461614 100644
--- a/Makefile
+++ b/Makefile
@@ -133,11 +133,9 @@ $(obj)/filo: $(OBJS) libpayload
 	printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(LD) -N -T $(ARCHDIR-y)/ldscript -o $@ $(OBJS) $(LIBPAYLOAD) $(LIBGCC)
 
-$(TARGET): $(obj)/filo libpayload
-	cp $(obj)/filo $@
-	$(NM) $(obj)/filo | sort > $(obj)/filo.map
+$(TARGET): $(obj)/filo $(obj)/filo.map
 	printf "  STRIP   $(subst $(shell pwd)/,,$(@))\n"
-	$(STRIP) -s $@
+	$(STRIP) -s $< -o $@
 
 include util/kconfig/Makefile
 
@@ -153,6 +151,10 @@ $(obj)/%.S.o: $(src)/%.S
 	printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(AS) $(ASFLAGS) -o $@ $<
 
+$(obj)/%.map: $(obj)/%
+	printf "  SYMS    $(subst $(shell pwd)/,,$(@))\n"
+	$(NM) -n $< > $@
+
 endif
 
 $(obj)/version.h: FORCE



From gerrit at coreboot.org  Wed Mar  7 17:44:13 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:44:13 +0100
Subject: [coreboot] Patch merged into filo/master: 348f295 makefile: create
	filo.map in separate step
References: <If010b4ce269a47a99de06db16e0290c3fd90b559+0@gerrit.coreboot.org>
Message-ID: <E1S5JyH-0008CY-CT@ra.coresystems.de>

the following patch was just integrated into master:
commit 348f295d107eeabab00f80dbe371838a355b3e3d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 09:42:18 2012 +0100

    makefile: create filo.map in separate step
    
    Instead of copying files around and creating files make is not aware of,
    use a dedicated target and rule to create filo.map. Also skip piping the
    result through sort as nm has an option to sort the symbols.
    
    Also drop the bogus dependency to libpayload as filo.elf is only the
    striped version of filo.
    
    Change-Id: If010b4ce269a47a99de06db16e0290c3fd90b559
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:49:46 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:44:12 2012, giving +2
See http://review.coreboot.org/743 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:44:29 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:44:29 +0100
Subject: [coreboot] Patch merged into filo/master: 1b31017 makefile: avoid
	unnecessary rebuilds
References: <Ifa42362ba1d8c88c9996d645314cfdbdf2994759+0@gerrit.coreboot.org>
Message-ID: <E1S5JyX-0008K0-S3@ra.coresystems.de>

the following patch was just integrated into master:
commit 1b310177b04d265622ca220ce27f696b41fd786e
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:14:47 2012 +0100

    makefile: avoid unnecessary rebuilds
    
    The make target libpayload is a phony target which makes filo and all
    the object files get rebuild on every make invokation. Avoid this by
    lifting the dependencies and rebuild, i.e. relink filo only when
    libpayload has changed.
    
    Also, when building libpayload as a prerequisite, use $(obj) as DESTDIR,
    as the user might want to use a different build directory then $(src)/build.
    
    Change-Id: Ifa42362ba1d8c88c9996d645314cfdbdf2994759
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:48:17 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:44:28 2012, giving +2
See http://review.coreboot.org/744 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:44:45 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:44:45 +0100
Subject: [coreboot] Patch merged into filo/master: 00e82ca makefile:
	recreate version.h only when needed
References: <I27a057be25902233ac0751db8061e9ad4cd50642+0@gerrit.coreboot.org>
Message-ID: <E1S5Jyn-0008R9-LO@ra.coresystems.de>

the following patch was just integrated into master:
commit 00e82ca97042907951ee977ead2e93039ab1da6d
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:26:48 2012 +0100

    makefile: recreate version.h only when needed
    
    Don't recreate version.h on each make invokation but only when needed, i.e.
    when the make variables have changed. Also make version.h a prerequisite for
    the object files to rebuild them when the version information changes.
    
    Change-Id: I27a057be25902233ac0751db8061e9ad4cd50642
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:46:48 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:44:44 2012, giving +2
See http://review.coreboot.org/745 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:45:10 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:45:10 +0100
Subject: [coreboot] Patch merged into filo/master: baf1339 makefile: build
	system cleanup
References: <I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b+0@gerrit.coreboot.org>
Message-ID: <E1S5JzC-0000OH-8w@ra.coresystems.de>

the following patch was just integrated into master:
commit baf1339a1334616c73cbbf9cd7743d54b4a86ff3
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 13:37:05 2012 +0100

    makefile: build system cleanup
    
    This patch cleans up the include hierarchies for the Makefile system to
    decrease the knowledge of the main Makefile about every subdirectory.
    This allows us to add new drivers without the need to patch the main
    Makefile but, instead, just add a line to the appropriate Makefile.inc.
    
    Also all standard make variables are cleaned up (e.g. CFLAGS,
    CPPFLAGS,..). This, in turn, allows modifying them as needed in the
    included Makefile.inc to add flags or even library dependencies.
    
    It's no Linux Kbuild yet, but we're close ;)
    
    Change-Id: I67be4fcdd07d6960a7e46bfb6a3c0ea41f280e2b
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:45:22 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:45:09 2012, giving +2
See http://review.coreboot.org/746 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:45:25 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:45:25 +0100
Subject: [coreboot] Patch merged into filo/master: dfc652a Fix some compiler
	warnings
References: <I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299+0@gerrit.coreboot.org>
Message-ID: <E1S5JzR-0000Sc-KK@ra.coresystems.de>

the following patch was just integrated into master:
commit dfc652ad783639baabc71e83b2ac76a583c08975
Author: Mathias Krause <mathias.krause at secunet.com>
Date:   Tue Mar 6 16:10:27 2012 +0100

    Fix some compiler warnings
    
    The makefile cleanup brought up quite a few compiler warnings about
    unused functions and/or variables, undefined behaviour, missing return
    values and type mismatches. Fix those.
    
    Change-Id: I0e01b5fafd9d7594ec41c01d849f6ef9a2d56299
    Signed-off-by: Mathias Krause <mathias.krause at secunet.com>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:43:55 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:45:23 2012, giving +2
See http://review.coreboot.org/747 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:47:39 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:47:39 +0100
Subject: [coreboot] Patch merged into coreboot/master: cc2b317 lint: test
	that labels begin at start-of-line
References: <Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2+0@gerrit.coreboot.org>
Message-ID: <E1S5K1b-0001YL-SD@ra.coresystems.de>

the following patch was just integrated into master:
commit cc2b3173570a49dae0c780c1e1b8d2e12a0f5975
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Mar 7 15:49:07 2012 +0100

    lint: test that labels begin at start-of-line
    
    Some attempt at enforcing style
    
    Change-Id: Ibbfb86402ecc57e8db6c3857c8e0193085ed4fc2
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:12:29 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:47:38 2012, giving +2
See http://review.coreboot.org/771 for details.

-gerrit



From gerrit at coreboot.org  Wed Mar  7 17:48:04 2012
From: gerrit at coreboot.org (gerrit at coreboot.org)
Date: Wed, 7 Mar 2012 17:48:04 +0100
Subject: [coreboot] Patch merged into coreboot/master: f7a8b4e Move C labels
	to start-of-line
References: <Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f+0@gerrit.coreboot.org>
Message-ID: <E1S5K20-0001gr-Ur@ra.coresystems.de>

the following patch was just integrated into master:
commit f7a8b4e8327349825c0c2e51d44e3dd323372cb1
Author: Patrick Georgi <patrick at georgi-clan.de>
Date:   Wed Mar 7 15:55:47 2012 +0100

    Move C labels to start-of-line
    
    Also mark the corresponding lint test stable.
    
    Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
    Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>

Build-Tested: build bot (Jenkins) at Wed Mar  7 16:26:57 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Wed Mar  7 17:48:02 2012, giving +2
See http://review.coreboot.org/772 for details.

-gerrit



From rminnich at gmail.com  Wed Mar  7 19:30:17 2012
From: rminnich at gmail.com (ron minnich)
Date: Wed, 7 Mar 2012 10:30:17 -0800
Subject: [coreboot] Bug when I compiling coreboot with SeaBIOS
In-Reply-To: <20120307134703.GA7267@morn.localdomain>
References: <4F5286F0.9050903@gmail.com>
	<20120305095656.GD11392@xivo-clients.proformatique.com>
	<CAP6exYLVJMMM-9aW8k24j4m_y5me7sZZsPKKGuJgRCdDJm_Fxg@mail.gmail.com>
	<20120307134703.GA7267@morn.localdomain>
Message-ID: <CAP6exY+SKzoBXEbmQaevLuscdk65MC5=VPe9Tp20wy7QrJW79w@mail.gmail.com>

The solution in other projects I have worked on is to have an
initialized struct and just copy it at runtime to the right place.
This gets around all the issues with ld (which have been issues in
various ways for 12 years now ... just different ones :)

How big are the tables? If they're not that big then just copying them
to where they need to be at startup might be the best solution. LD is
going to continue to break, always has and always will. Just a
thought.

This fails on recent arch and ubuntu. If you can find a way not to use
this kind of LD trick, life will be easier.

Of course if this is going to mess up entry points then we're out of luck.

thanks

ron



From gerrit at coreboot.org  Wed Mar  7 20:22:35 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:35 +0100
Subject: [coreboot] Patch set updated for coreboot: 349c6fa Allow components
	smaller than declared size.
References: <I1b04f90051b91157391943c9bad0eb06dd297431+0@gerrit.coreboot.org>
Message-ID: <I1b04f90051b91157391943c9bad0eb06dd297431+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/751

-gerrit

commit 349c6faddb682c6c9932e3107cb02e9c0acdea36
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Nov 9 14:11:26 2011 -0800

    Allow components smaller than declared size.
    
    idftool was failing to add the ME blobs into the output image in case
    the blob size does not exactly match the size allocated for it in the
    flashrom structure.
    
    It is difficult to set the field in the structure to exactly match the
    size (for some reason Intel flash tool fails to insert the correct
    size even when given the exact ME blob). On the other hand there is no
    harm in using am ME blob smaller than the allocated size, this change
    modifies the tool building the image to allow for smaller components.
    
    Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/ifdtool/ifdtool.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index eb91b2c..8c1077c 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -334,7 +334,7 @@ void inject_region(char *filename, char *image, int size, int region_type,
 	printf("File %s is %d bytes\n", region_fname, region_size);
 
 	if ( (region_size > region.size) || ((region_type != 1) &&
-		(region_size != region.size))) {
+		(region_size > region.size))) {
 		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
 				" bytes. Not injecting.\n",
 				region_name(region_type), region.size,



From gerrit at coreboot.org  Wed Mar  7 20:22:35 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:35 +0100
Subject: [coreboot] Patch set updated for coreboot: ac302ea Fix coreboot
	makefiles not to produce half baked output.
References: <I7c17f033ee5937eb712b1a594122430cee5c9146+0@gerrit.coreboot.org>
Message-ID: <I7c17f033ee5937eb712b1a594122430cee5c9146+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/750

-gerrit

commit ac302ea88301f29f982c0d6191cb07c687b2e09c
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Sat Nov 5 02:07:01 2011 +0000

    Fix coreboot makefiles not to produce half baked output.
    
    It looks like the cbfstool utility generates the output file even when
    it fails to generate it properly. This causes make, if started second
    time in a row, after cbfstool failure, to continue beyond the point of
    failure (as the corrupted output file is present in the output tree,
    the second make invocation presumes that it is valid, as it is newer
    than the dependencies).
    
    The output file should be created only when successful, in an atomic
    operation. There could be other places in the make system which
    require a similar fix, this needs to be investigated further.
    
    Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/Makefile.inc |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index aeb4875..b2b9143 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -58,13 +58,15 @@ extract_nth=$(word $(1), $(subst |, ,$(2)))
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	$(foreach file,$(cbfs-files), \
-		$(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
+	$(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \
+	$(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \
+	$(call extract_nth,4,$(file)) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL)
-	rm -f $@
-	$(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
-	$(prebuild-files)
+	$(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
+	$(prebuild-files) true
+	mv $@.tmp $@
 else
 .PHONY: $(obj)/coreboot.pre1
 $(obj)/coreboot.pre1: $(CBFSTOOL)
@@ -269,10 +271,10 @@ endif
 
 $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
+	cp $(obj)/coreboot.pre1 $@.tmp
+	$(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \
 	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	mv $@.tmp $@
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################



From gerrit at coreboot.org  Wed Mar  7 20:22:36 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:36 +0100
Subject: [coreboot] Patch set updated for coreboot: 33e6810 Add more
	timestamps in coreboot.
References: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+0@gerrit.coreboot.org>
Message-ID: <Iea17c08774e623fc1ca3fa4505b70523ba4cbf01+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/749

-gerrit

commit 33e681093f5ea71ef0acd3151c9ff3c9cb6291b1
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Nov 4 12:31:58 2011 -0700

    Add more timestamps in coreboot.
    
    This adds a number of timestamps in ramstage and romstage
    so we can figure out where execution time goes.
    
    Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/lib/cbfs_and_run.c |    3 +++
 src/boot/hardwaremain.c         |   21 +++++++++++++++++++++
 src/include/timestamp.h         |   22 ++++++++++++++++++++--
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index ad36ddc..53f06ee 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -20,16 +20,19 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include <arch/stages.h>
+#include <timestamp.h>
 
 static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 
+	timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
 	if ((void *)dst == (void *) -1)
 		die("FATAL: Essential component is missing.\n");
 
+	timestamp_add_now(TS_END_COPYRAM);
 	print_debug("Jumping to image.\n");
 	__asm__ volatile (
 		"movl %%eax, %%ebp\n"
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 9b293c0..489caa3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,6 +41,7 @@ it with the version available from LANL.
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
@@ -56,7 +57,9 @@ void hardwaremain(int boot_complete);
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
+	timestamps[0] = rdtsc();
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
@@ -78,18 +81,26 @@ void hardwaremain(int boot_complete)
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
 	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
 	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
 #if CONFIG_CONSOLE_CBMEM
@@ -101,10 +112,20 @@ void hardwaremain(int boot_complete)
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index 8b9a89a..0bb323c 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -35,14 +35,32 @@ struct timestamp_table {
 } __attribute__((packed));
 
 enum timestamp_id {
-	TS_BEFORE_INITRAM = 1,
-	TS_AFTER_INITRAM = 2,
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
 	TS_ACPI_WAKE_JUMP = 98,
 	TS_SELFBOOT_JUMP = 99,
 };
 
+#if CONFIG_COLLECT_TIMESTAMPS
 void timestamp_init(tsc_t base);
 void timestamp_add(enum timestamp_id id, tsc_t ts_time);
 void timestamp_add_now(enum timestamp_id id);
+#else
+#define timestamp_init(base)
+#define timestamp_add(id, time)
+#define timestamp_add_now(id)
+#endif
 
 #endif



From gerrit at coreboot.org  Wed Mar  7 20:22:36 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:36 +0100
Subject: [coreboot] Patch set updated for coreboot: cb46d2a Add an option to
	keep the ROM cached after romstage
References: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+0@gerrit.coreboot.org>
Message-ID: <I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/739

-gerrit

commit cb46d2aac3cbd2ae2a92ceacc7db527e43316c31
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 2 16:12:34 2011 -0700

    Add an option to keep the ROM cached after romstage
    
    Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/include/arch/acpi.h |    4 +++-
 src/cpu/x86/Kconfig              |    4 +++-
 src/cpu/x86/lapic/Makefile.inc   |    1 +
 src/cpu/x86/lapic/boot_cpu.c     |    3 ++-
 src/cpu/x86/mtrr/mtrr.c          |   14 +++++++++++++-
 src/include/cpu/x86/lapic.h      |    4 ++++
 6 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..504d71b 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -422,7 +422,8 @@ void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,6 +435,7 @@ void generate_cpu_entries(void);
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
 
 #endif
 
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 348f0ef..fdbd527 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -39,4 +39,6 @@ config LOGICAL_CPUS
 	bool
 	default y
 
-
+config CACHE_ROM
+	bool
+	default n
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956..f3fcadc 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0..0fb9d5d 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 46d8e2d..9015ad4 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,7 +36,9 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
 #include <arch/cpu.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -48,7 +50,6 @@ static unsigned int mtrr_msr[] = {
 	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
-
 void enable_fixed_mtrr(void)
 {
 	msr_t msr;
@@ -456,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	while(var_state.reg < MTRRS) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
+
+#if CONFIG_CACHE_ROM
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	if (boot_cpu() && (acpi_slp_type != 3)) {
+		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+			MTRR_TYPE_WRPROT, address_bits);
+	}
+#endif
+
 	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6c..016870d 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,6 +1,7 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#ifndef __ROMCC__
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
@@ -156,4 +157,7 @@ int start_cpu(struct device *cpu);
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */



From gerrit at coreboot.org  Wed Mar  7 20:22:37 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:37 +0100
Subject: [coreboot] Patch set updated for coreboot: 3ce67ca Make TPM driver
	work in rom stage.
References: <Ifc827d0cd0159aa3f6752d395974f2812334f262+0@gerrit.coreboot.org>
Message-ID: <Ifc827d0cd0159aa3f6752d395974f2812334f262+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/738

-gerrit

commit 3ce67caeb820b0e33cf791ea18d79218d4769318
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 27 21:28:25 2011 +0000

    Make TPM driver work in rom stage.
    
    Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/tpm.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 1cbf800..8e94303 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -35,6 +35,7 @@
 #include <arch/byteorder.h>
 #include <console/console.h>
 #include <pc80/tpm.h>
+#include <cpu/x86/car.h>
 
 #ifdef DEBUG
 #define TPM_DEBUG_ON	1
@@ -130,10 +131,10 @@ struct device_name {
 struct vendor_name {
 	u16 vendor_id;
 	const char * vendor_name;
-	struct device_name* dev_names;
+	const struct device_name* dev_names;
 };
 
-static struct device_name infineon_devices[] = {
+static const struct device_name infineon_devices[] = {
 	{0xb, "SLB9635 TT 1.2"},
 	{0}
 };
@@ -146,7 +147,7 @@ static const struct vendor_name vendor_names[] = {
  * Cached vendor/device ID pair to indicate that the device has been already
  * discovered
  */
-static u32 vendor_dev_id;
+static u32 vendor_dev_id CAR_GLOBAL;
 
 static int is_byte_reg(u32 reg)
 {



From gerrit at coreboot.org  Wed Mar  7 20:22:38 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:38 +0100
Subject: [coreboot] Patch set updated for coreboot: 5759ace add native
	memset() function on x86.
References: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+0@gerrit.coreboot.org>
Message-ID: <Ia118ebe0a4b59bdcefd78895141a365170f6aed2+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/737

-gerrit

commit 5759acef0583e960ded791b6c962365f5813ac63
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Oct 26 22:11:52 2011 +0000

    add native memset() function on x86.
    
    Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig          |    4 ++
 src/arch/x86/lib/Makefile.inc |    2 +
 src/arch/x86/lib/memset.c     |   86 +++++++++++++++++++++++++++++++++++++++++
 src/lib/Makefile.inc          |    4 ++
 4 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 74933af..078ae95 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMSET
+	bool
+	default y
+
 config HAVE_ARCH_MEMCPY
 	bool
 	default y
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index f99e429..3f4dc95 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,10 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memset.c
 ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memset.c
 romstage-y += memcpy.c
 
 smm-y += memcpy.c
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
new file mode 100644
index 0000000..e850726
--- /dev/null
+++ b/src/arch/x86/lib/memset.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <string.h>
+#include <stdint.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+	int d0;
+	unsigned long int dstp = (unsigned long int) dstpp;
+
+	/* This explicit register allocation improves code very much indeed. */
+	register op_t x asm("ax");
+
+	x = (unsigned char) c;
+
+	/* Clear the direction flag, so filling will move forward.  */
+	asm volatile("cld");
+
+	/* This threshold value is optimal.  */
+	if (len >= 12) {
+		/* Fill X with four copies of the char we want to fill with. */
+		x |= (x << 8);
+		x |= (x << 16);
+
+		/* Adjust LEN for the bytes handled in the first loop.  */
+		len -= (-dstp) % sizeof(op_t);
+
+		/*
+		 * There are at least some bytes to set. No need to test for
+		 * LEN == 0 in this alignment loop.
+		 */
+
+		/* Fill bytes until DSTP is aligned on a longword boundary. */
+		asm volatile(
+			"rep\n"
+			"stosb" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+			"memory");
+
+		/* Fill longwords.  */
+		asm volatile(
+			"rep\n"
+			"stosl" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+			"memory");
+		len %= sizeof(op_t);
+	}
+
+	/* Write the last few bytes. */
+	asm volatile(
+		"rep\n"
+		"stosb" /* %0, %2, %3 */ :
+		"=D" (dstp), "=c" (d0) :
+		"0" (dstp), "1" (len), "a" (x) :
+		"memory");
+
+	return dstpp;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 61b6451..8ce72b2 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,6 +1,8 @@
 
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 romstage-y += memset.c
+endif
 romstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
 romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
+endif
 ramstage-y += memchr.c
 ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c



From gerrit at coreboot.org  Wed Mar  7 20:22:38 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:38 +0100
Subject: [coreboot] Patch set updated for coreboot: 5487e3d Add faster,
	architecture dependent memcpy()
References: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+0@gerrit.coreboot.org>
Message-ID: <I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/736

-gerrit

commit 5487e3d1d7f285333f67d8713b8f0642289df4a2
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 23:43:34 2011 +0000

    Add faster, architecture dependent memcpy()
    
    Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    Reviewed-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/Kconfig          |    4 ++++
 src/arch/x86/lib/Makefile.inc |    4 ++++
 src/arch/x86/lib/memcpy.c     |   13 +++++++++++++
 src/lib/Makefile.inc          |    9 ++++++++-
 4 files changed, 29 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index e71d0f3..74933af 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -80,6 +80,10 @@ config CMOS_DEFAULT_FILE
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMCPY
+	bool
+	default y
+
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3388a9d..f99e429 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -8,8 +8,12 @@ ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memcpy.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memcpy.c
+
+smm-y += memcpy.c
 
 $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h
diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c
new file mode 100644
index 0000000..de21092
--- /dev/null
+++ b/src/arch/x86/lib/memcpy.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+void *memcpy(void *__restrict __dest,
+	     __const void *__restrict __src, size_t __n)
+{
+	asm("cld\n"
+	    "rep\n"
+	    "movsb"
+	    :	/* no input (?) */
+	    :"S"(__src), "D"(__dest), "c"(__n)
+	);
+	return __dest;
+}
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 45cb788..61b6451 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -2,7 +2,9 @@
 
 romstage-y += memset.c
 romstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
+endif
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
@@ -19,7 +21,9 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 ramstage-y += memset.c
 ramstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c
+endif
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
 ramstage-y += malloc.c
@@ -43,7 +47,10 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
-smm-y += memcpy.c cbfs.c memset.c memcmp.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
+smm-y += memcpy.c
+endif
+smm-y += cbfs.c memset.c memcmp.c
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
 smm-$(CONFIG_USBDEBUG) += usbdebug.c



From gerrit at coreboot.org  Wed Mar  7 20:22:39 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:39 +0100
Subject: [coreboot] Patch set updated for coreboot: c1969e4 Revamp cbmem.py
	to use the coreboot tables.
References: <I51833055a50c2d76423520ba6e059bf8fc50adea+0@gerrit.coreboot.org>
Message-ID: <I51833055a50c2d76423520ba6e059bf8fc50adea+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/762

-gerrit

commit c1969e45cad06752cf8288a4320043a8b8bfe6a7
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Jan 7 01:03:42 2012 -0800

    Revamp cbmem.py to use the coreboot tables.
    
    This change makes significant changes to cbmem.py to make it use the
    coreboot tables to find the memory console and timestamp areas instead
    of looking for the in memory table TOC structure. That appears to be
    more robust and gets cbmem.py working again after some unrelated
    changes that affected memory layout.
    
    It also introduces some small infrastructure to make accessing C style
    structures in physical memory easier and more transparent.
    
    Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 util/cbmem/cbmem.py |  267 ++++++++++++++++++++++++++++++---------------------
 1 files changed, 158 insertions(+), 109 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
index 3e8476d..f4f3e88 100755
--- a/util/cbmem/cbmem.py
+++ b/util/cbmem/cbmem.py
@@ -33,29 +33,46 @@ console sections.
 '''
 
 import mmap
-import re
 import struct
 import sys
-import time
 
-# These definitions follow src/include/cbmem.h
-CBMEM_MAGIC = 0x434f5245
-CBMEM_MAX_ENTRIES = 16
+def get_phys_mem(addr, size):
+    '''Read size bytes from address addr by mmaping /dev/mem'''
 
-CBMEM_ENTRY_FORMAT = '@LLQQ'
-CONSOLE_HEADER_FORMAT = '@LL'
-TIMESTAMP_HEADER_FORMAT = '@QLL'
-TIMESTAMP_ENTRY_FORMAT = '@LQ'
-
-mf_fileno = 0  # File number of the file providing access to memory.
-
-def align_up(base, alignment):
-    '''Increment to the alignment boundary.
-
-    Return the next integer larger than 'base' and divisible by 'alignment'.
-    '''
-
-    return base + alignment - base % alignment
+    mf = open("/dev/mem")
+    delta = addr % 4096
+    mm = mmap.mmap(mf.fileno(), size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mf.close()
+    return buf[delta:]
+
+# This class and metaclass make it easier to define and access structures
+# which live in physical memory. To use them, inherit from CStruct and define
+# a class member called struct_members which is a tuple of pairs. The first
+# item in the pair is the type format specifier that should be used with
+# struct.unpack to read that member from memory. The second item is the name
+# that member should have in the resulting object.
+
+class MetaCStruct(type):
+    def __init__(cls, name, bases, dct):
+        struct_members = dct["struct_members"]
+        cls.struct_fmt = "@"
+        for char, name in struct_members:
+            cls.struct_fmt += char
+        cls.struct_len = struct.calcsize(cls.struct_fmt)
+        super(MetaCStruct, cls).__init__(name, bases, dct)
+
+class CStruct(object):
+    __metaclass__ = MetaCStruct
+    struct_members = ()
+
+    def __init__(self, addr):
+        self.raw_memory = get_phys_mem(addr, self.struct_len)
+        values = struct.unpack(self.struct_fmt, self.raw_memory)
+        names = (name for char, name in self.struct_members)
+        for name, value in zip(names, values):
+            setattr(self, name, value)
 
 def normalize_timer(value, freq):
     '''Convert timer reading into microseconds.
@@ -96,109 +113,141 @@ def get_cpu_freq():
     # Convert reading into Hertz
     return float(freq_str) * 1000.0
 
-def get_mem_size():
-    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
-    mult = {
-        'kB': 1024
-        }
-    meminfo = open('/proc/meminfo').read()
-    m = re.search('MemTotal:.*\n', meminfo)
-    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
-    (_, size, mult_name) = mem_string.split()
-    return int(size) * mult[mult_name]
-
-def parse_mem_at(addr, format):
-    '''Read and parse a memory location.
-
-    This function reads memory at the passed in address, parses it according
-    to the passed in format specification and returns a list of values.
-
-    The first value in the list is the size of data matching the format
-    expression, and the rest of the elements of the list are the actual values
-    retrieved using the format.
-    '''
-
-    size = struct.calcsize(format)
-    delta = addr % 4096   # mmap requires the offset to be page size aligned.
-    mm = mmap.mmap(mf_fileno, size + delta,
-                   mmap.MAP_PRIVATE, offset=(addr - delta))
-    buf = mm.read(size + delta)
-    mm.close()
-    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
-    return rv
-
-def dprint(text):
-    '''Debug print function.
-
-    Edit it to get the debug output.
-    '''
-
-    if False:
-        print text
-
 def process_timers(base):
     '''Scan the array of timestamps found in CBMEM at address base.
 
     For each timestamp print the timer ID and the value in microseconds.
     '''
 
-    (step, base_time, max_entr, entr) = parse_mem_at(
-        base, TIMESTAMP_HEADER_FORMAT)
-
-    print('\ntime base %d, total entries %d' % (base_time, entr))
+    class TimestampHeader(CStruct):
+        struct_members = (
+            ("Q", "base_time"),
+            ("L", "max_entr"),
+            ("L", "entr")
+        )
+
+    class TimestampEntry(CStruct):
+        struct_members = (
+            ("L", "timer_id"),
+            ("Q", "timer_value")
+        )
+
+    header = TimestampHeader(base)
+    print('\ntime base %d, total entries %d' % (header.base_time, header.entr))
     clock_freq = get_cpu_freq()
-    base = base + step
-    for i in range(entr):
-        (step, timer_id, timer_value) = parse_mem_at(
-            base, TIMESTAMP_ENTRY_FORMAT)
-        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
-        base = base + step
+    base = base + header.struct_len
+    for i in range(header.entr):
+        timestamp = TimestampEntry(base)
+        print '%d:%s ' % (timestamp.timer_id,
+            normalize_timer(timestamp.timer_value, clock_freq)),
+        base = base + timestamp.struct_len
     print
 
 def process_console(base):
     '''Dump the console log buffer contents found at address base.'''
 
-    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
-    print 'cursor at %d\n' % cursor
+    class ConsoleHeader(CStruct):
+        struct_members = (
+            ("L", "size"),
+            ("L", "cursor")
+        )
 
-    cons_string_format = '%ds' % min(cursor, size)
-    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    header = ConsoleHeader(base)
+    print 'cursor at %d\n' % header.cursor
+
+    cons_addr = base + header.struct_len
+    cons_length = min(header.cursor, header.size)
+    cons_text = get_phys_mem(cons_addr, cons_length)
     print cons_text
     print '\n'
 
-mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
-table_alignment = 128 * 1024
-
-mem_size = get_mem_size()
-
-# start at memory address aligned at 128K.
-offset = align_up(mem_size, table_alignment)
-
-dprint('mem_size %x offset %x' %(mem_size, offset))
-mf = open("/dev/mem")
-mf_fileno = mf.fileno()
-
-while offset % mem_alignment: # do not cross the 1G boundary while searching
-    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if magic == CBMEM_MAGIC:
-        offset = offset + step
-        break
-    offset += table_alignment
-else:
-    print 'Did not find the CBMEM'
-    sys.exit(0)
-
-for i in (range(1, CBMEM_MAX_ENTRIES)):
-    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
-    if mid == 0:
-        break
-
-    print '%x, %x, %x' % (mid, base, size)
-    if mid == 0x54494d45:
-        process_timers(base)
-    if mid == 0x434f4e53:
-        process_console(base)
-
-    offset = offset + step
-
-mf.close()
+def ipchksum(buf):
+    '''Checksumming function used on the coreboot tables. The buffer being
+    checksummed is summed up as if it was an array of 16 bit unsigned
+    integers. If there are an odd number of bytes, the last element is zero
+    extended.'''
+
+    size = len(buf)
+    odd = size % 2
+    fmt = "<%dH" % ((size - odd) / 2)
+    if odd:
+        fmt += "B"
+    shorts = struct.unpack(fmt, buf)
+    checksum = sum(shorts)
+    checksum = (checksum >> 16) + (checksum & 0xffff)
+    checksum += (checksum >> 16)
+    checksum = ~checksum & 0xffff
+    return checksum
+
+def parse_tables(base, length):
+    '''Find the coreboot tables in memory and process whatever we can.'''
+
+    class CBTableHeader(CStruct):
+        struct_members = (
+            ("4s", "signature"),
+            ("I", "header_bytes"),
+            ("I", "header_checksum"),
+            ("I", "table_bytes"),
+            ("I", "table_checksum"),
+            ("I", "table_entries")
+        )
+
+    class CBTableEntry(CStruct):
+        struct_members = (
+            ("I", "tag"),
+            ("I", "size")
+        )
+
+    class CBTableForward(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("Q", "forward"),
+        )
+
+    class CBMemTab(CBTableEntry):
+        struct_members = CBTableEntry.struct_members + (
+            ("L", "cbmem_tab"),
+        )
+
+    for addr in range(base, base + length, 16):
+        header = CBTableHeader(addr)
+        if header.signature == "LBIO":
+            break
+    else:
+        return -1
+
+    if header.header_bytes == 0:
+        return -1
+
+    if ipchksum(header.raw_memory) != 0:
+        print "Bad header checksum"
+        return -1
+
+    addr += header.header_bytes
+    table = get_phys_mem(addr, header.table_bytes)
+    if ipchksum(table) != header.table_checksum:
+        print "Bad table checksum"
+        return -1
+
+    for i in range(header.table_entries):
+        entry = CBTableEntry(addr)
+        if entry.tag == 0x11: # Forwarding entry
+            return parse_tables(CBTableForward(addr).forward, length)
+        elif entry.tag == 0x16: # Timestamps
+            process_timers(CBMemTab(addr).cbmem_tab)
+        elif entry.tag == 0x17: # CBMEM console
+            process_console(CBMemTab(addr).cbmem_tab)
+
+        addr += entry.size
+
+    return 0
+
+def main():
+    for base, length in (0x00000000, 0x1000), (0x000f0000, 0x1000):
+        if parse_tables(base, length):
+            break
+    else:
+        print "Didn't find the coreboot tables"
+        return 0
+
+if __name__ == "__main__":
+    sys.exit(main())



From gerrit at coreboot.org  Wed Mar  7 20:22:40 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:40 +0100
Subject: [coreboot] Patch set updated for coreboot: d6f9227 Fix MB
	calculation in the reporting of the MTRR hole
References: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+0@gerrit.coreboot.org>
Message-ID: <I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/763

-gerrit

commit d6f9227b7db84e57197806c973b5c393b97c7e82
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Jan 6 15:49:30 2012 -0800

    Fix MB calculation in the reporting of the MTRR hole
    
    Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8dccfef..5f5e02b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -306,7 +306,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 
 	if (hole_sizek) {
 		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
-		       hole_startk, hole_startk + hole_sizek);
+		       hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
 		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
 			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
 			      address_bits, above4gb);



From gerrit at coreboot.org  Wed Mar  7 20:22:41 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:41 +0100
Subject: [coreboot] Patch set updated for coreboot: cee2e40 drop use of
	MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
References: <Idf875ddec417e627f1e72a6d834860e7fd324a50+0@gerrit.coreboot.org>
Message-ID: <Idf875ddec417e627f1e72a6d834860e7fd324a50+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/760

-gerrit

commit cee2e40eafb8a7515ad7f3810c60def42bf9d5aa
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Dec 15 09:24:40 2011 -0800

    drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
    
    Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/lapic_cpu_init.c |    6 ------
 src/cpu/x86/pae/Makefile.inc       |    2 +-
 2 files changed, 1 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index fc22ea4..99c3c4e 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -363,9 +363,7 @@ void secondary_cpu_init(void)
 {
 	atomic_inc(&active_cpus);
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_lock(&start_cpu_lock);
-  #endif
 #endif
 
 #ifdef __SSE3__
@@ -380,9 +378,7 @@ void secondary_cpu_init(void)
 #endif
 	cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 	spin_unlock(&start_cpu_lock);
-  #endif
 #endif
 
 	atomic_dec(&active_cpus);
@@ -419,9 +415,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 				cpu->path.apic.apic_id);
 		}
 #if CONFIG_SERIAL_CPU_INIT == 1
-  #if CONFIG_MAX_CPUS>2
 		udelay(10);
-  #endif
 #endif
 	}
 
diff --git a/src/cpu/x86/pae/Makefile.inc b/src/cpu/x86/pae/Makefile.inc
index 0ecec47..060720c 100644
--- a/src/cpu/x86/pae/Makefile.inc
+++ b/src/cpu/x86/pae/Makefile.inc
@@ -1 +1 @@
-ramstage-y += pgtbl.c
+ramstage-$(CONFIG_CPU_AMD_MODEL_FXX) += pgtbl.c



From gerrit at coreboot.org  Wed Mar  7 20:22:42 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:42 +0100
Subject: [coreboot] Patch set updated for coreboot: 0230c2e MTRR: add
	alternate allocation method for odd memory maps With >= 4GB
	memory installed we get a memory map split in the middle due
	to remap that has boundaries that are inconveniently aligned
	for MTRRs due to the various UMA regions.
References: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+0@gerrit.coreboot.org>
Message-ID: <I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/761

-gerrit

commit 0230c2e6b6635ae9aeec21406501e3df5325b0d9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Dec 22 10:59:40 2011 -0800

    MTRR: add alternate allocation method for odd memory maps
    With >= 4GB memory installed we get a memory map split in the middle
    due to remap that has boundaries that are inconveniently aligned for
    MTRRs due to the various UMA regions.
    
    0000MB-2780MB  2780MB  RAM     (writeback)
    2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
    2782MB-2784MB     2MB  GFX GTT (uncached)
    2784MB-2816MB    32MB  GFX UMA (uncached)
    2816MB-4096MB  1280MB  EMPTY   (N/A)
    4096MB-5368MB  1272MB  RAM     (writeback)
    5368MB-5376MB     8MB  ME UMA  (uncached)
    
    The default MTRR allocation method of trying to cover everything
    with one MTRR and then carve out a single uncached region does
    not work for the GPU aperture which needs write-combining type,
    and it also has issues trying to cover the uneven boundaries
    in the avaiable variable MTRRs.
    
    My goal was to make a minimal set of changes and avoid modifying
    behavior on existing systems with an algorithm that is not always
    optimal for a typical memory layout.  So the flag 'above4gb=2'
    will change these allocation behaviors:
    
    1) Detect the number of available variable MTRRs rather than
    limiting to hardcoded value.  We need every last MTRR.
    
    2) Don't try to cover all RAM with one MTRR, instead let each
    RAM region get covered independently.
    
    3) Don't assume uma_memory_base is part of the last region
    and increase the size of that region.  In this case the UMA
    region is carved out from the lower memory region and it is
    already declared as part of the ram region.
    
    4) If a memory region can't be covered with MTRRs >= 16MB then
    instead make a larger region and trim it with uncached MTRRs.
    
    Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c |   52 ++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 9015ad4..8dccfef 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -179,6 +179,18 @@ static inline unsigned int fls(unsigned int x)
 #endif
 #define MTRRS        (BIOS_MTRRS + OS_MTRRS)
 
+static int total_mtrrs = MTRRS;
+static int bios_mtrrs = BIOS_MTRRS;
+
+static void detect_var_mtrrs(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MTRRcap_MSR);
+
+	total_mtrrs = msr.lo & 0xff;
+	bios_mtrrs = total_mtrrs - 2;
+}
 
 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
 {
@@ -235,6 +247,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
 	unsigned long next_range_startk, unsigned char type,
 	unsigned int address_bits, unsigned int above4gb)
 {
+	unsigned long hole_startk = 0, hole_sizek = 0;
+
 	if (!range_sizek) {
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
@@ -243,7 +257,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (reg >= BIOS_MTRRS) {
+	if (reg >= bios_mtrrs) {
 		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
@@ -251,6 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+		/*
+		 * If this range is not divisible by 16MB then instead
+		 * make a larger range and carve out an uncached hole.
+		 */
+		hole_startk = range_startk + range_sizek;
+		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		range_sizek += hole_sizek;
+	}
+
 	while(range_sizek) {
 		unsigned long max_align, align;
 		unsigned long sizek;
@@ -274,11 +298,20 @@ static unsigned int range_to_mtrr(unsigned int reg,
 			set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
-		if (reg >= BIOS_MTRRS) {
+		if (reg >= bios_mtrrs) {
 			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
+
+	if (hole_sizek) {
+		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
+		       hole_startk, hole_startk + hole_sizek);
+		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
+			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
+			      address_bits, above4gb);
+	}
+
 	return reg;
 }
 
@@ -325,7 +358,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 {
 	struct var_mtrr_state *state = gp;
 	unsigned long basek, sizek;
-	if (state->reg >= BIOS_MTRRS)
+	if (state->reg >= bios_mtrrs)
 		return;
 	basek = resk(res->base);
 	sizek = resk(res->size);
@@ -341,7 +374,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
 #if CONFIG_VAR_MTRR_HOLE
-		if (state->hole_sizek == 0) {
+		if (state->hole_sizek == 0 && state->above4gb != 2) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
@@ -424,6 +457,10 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	var_state.address_bits = address_bits;
 	var_state.above4gb = above4gb;
 
+	/* Detect number of variable MTRRs */
+	if (above4gb == 2)
+		detect_var_mtrrs();
+
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
@@ -435,7 +472,8 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	} else {
 #if CONFIG_VAR_MTRR_HOLE
 		// Increase the base range and set up UMA as an UC hole instead
-		var_state.range_sizek += (uma_memory_size >> 10);
+		if (above4gb != 2)
+			var_state.range_sizek += (uma_memory_size >> 10);
 
 		var_state.hole_startk = (uma_memory_base >> 10);
 		var_state.hole_sizek = (uma_memory_size >> 10);
@@ -454,7 +492,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
 	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
-	while(var_state.reg < MTRRS) {
+	while(var_state.reg < total_mtrrs) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
 
@@ -463,7 +501,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 	 * complete ROM now that we actually have RAM.
 	 */
 	if (boot_cpu() && (acpi_slp_type != 3)) {
-		set_var_mtrr(7, (4096-4)*1024, 4*1024,
+		set_var_mtrr(total_mtrrs-1, (4096-4)*1024, 4*1024,
 			MTRR_TYPE_WRPROT, address_bits);
 	}
 #endif



From gerrit at coreboot.org  Wed Mar  7 20:22:44 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:44 +0100
Subject: [coreboot] Patch set updated for coreboot: 44a318b Add Kconfig
	options to enable TSEG and set a size
References: <I1432569ece4371d6e12c997e90d66c175fa54c5c+0@gerrit.coreboot.org>
Message-ID: <I1432569ece4371d6e12c997e90d66c175fa54c5c+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/766

-gerrit

commit 44a318b924ebd63ca8a6fcb0c452d095df28132a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:11:25 2012 -0800

    Add Kconfig options to enable TSEG and set a size
    
    Future CPUs will require TSEG use for SMM
    
    Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/Kconfig |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index fdbd527..2033a0a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -42,3 +42,11 @@ config LOGICAL_CPUS
 config CACHE_ROM
 	bool
 	default n
+
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0



From gerrit at coreboot.org  Wed Mar  7 20:22:44 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:44 +0100
Subject: [coreboot] Patch set updated for coreboot: 9b5b512 Make cpuid
	functions usable when compiled with PIC
References: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+0@gerrit.coreboot.org>
Message-ID: <I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/764

-gerrit

commit 9b5b5123da87c34dd72eab4486415cd31c71ae9f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:00:30 2012 -0800

    Make cpuid functions usable when compiled with PIC
    
    This avoids using EBX and instead uses EDI where possible,
    and ESI when necessary to get the EBX value out.
    
    This allows me to enable -fpic for SMM TSEG code.
    
    Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/include/arch/cpu.h |   57 ++++++++++++++++++++++++++++++--------
 1 files changed, 45 insertions(+), 12 deletions(-)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 85357d7..508b7d6 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -36,12 +36,36 @@ static inline struct cpuid_result cpuid(int op)
 {
 	struct cpuid_result result;
 	asm volatile(
-		"cpuid"
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
 		: "=a" (result.eax),
-		  "=b" (result.ebx),
+		  "=S" (result.ebx),
 		  "=c" (result.ecx),
 		  "=d" (result.edx)
-		: "0" (op));
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
 	return result;
 }
 
@@ -52,10 +76,12 @@ static inline unsigned int cpuid_eax(unsigned int op)
 {
 	unsigned int eax;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax)
 		: "0" (op)
-		: "ebx", "ecx", "edx");
+		: "ecx", "edx", "edi");
 	return eax;
 }
 
@@ -63,10 +89,13 @@ static inline unsigned int cpuid_ebx(unsigned int op)
 {
 	unsigned int eax, ebx;
 
-	__asm__("cpuid"
-		: "=a" (eax), "=b" (ebx)
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		"mov %%edi, %%esi;"
+		: "=a" (eax), "=S" (ebx)
 		: "0" (op)
-		: "ecx", "edx" );
+		: "ecx", "edx", "edi");
 	return ebx;
 }
 
@@ -74,10 +103,12 @@ static inline unsigned int cpuid_ecx(unsigned int op)
 {
 	unsigned int eax, ecx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=c" (ecx)
 		: "0" (op)
-		: "ebx", "edx" );
+		: "edx", "edi");
 	return ecx;
 }
 
@@ -85,10 +116,12 @@ static inline unsigned int cpuid_edx(unsigned int op)
 {
 	unsigned int eax, edx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=d" (edx)
 		: "0" (op)
-		: "ebx", "ecx");
+		: "ecx", "edi");
 	return edx;
 }
 



From gerrit at coreboot.org  Wed Mar  7 20:22:45 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:45 +0100
Subject: [coreboot] Patch set updated for coreboot: 4b848d6 Make MTRR min
	hole alignment 64MB
References: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+0@gerrit.coreboot.org>
Message-ID: <I1a06ccc28ef139cc79f655a8b19fd3533aca0401+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/765

-gerrit

commit 4b848d668c4d804cc7512078805f5b6d7adf0052
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jan 9 22:05:18 2012 -0800

    Make MTRR min hole alignment 64MB
    
    This affects the algorithm when determining when to
    transform a range into a larger range with a hole.
    
    It is needed when for when I switch on an 8MB TSEG
    and cause the memory maps to go crazy.
    
    Also add header defines for the SMRR.
    
    Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/cpu/x86/mtrr/mtrr.c    |    9 ++++++---
 src/include/cpu/x86/mtrr.h |    3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 5f5e02b..ed7d93b 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -265,13 +265,16 @@ static unsigned int range_to_mtrr(unsigned int reg,
 		return reg;
 	}
 
-	if (above4gb == 2 && type == MTRR_TYPE_WRBACK && range_sizek % 0x4000) {
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
 		/*
-		 * If this range is not divisible by 16MB then instead
+		 * If this range is not divisible then instead
 		 * make a larger range and carve out an uncached hole.
 		 */
 		hole_startk = range_startk + range_sizek;
-		hole_sizek = 0x4000 - (range_sizek % 0x4000);
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
 		range_sizek += hole_sizek;
 	}
 
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 62cb8b7..8b5cc28 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 



From gerrit at coreboot.org  Wed Mar  7 20:22:45 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:45 +0100
Subject: [coreboot] Patch set updated for coreboot: 19d4751 labels should
	start at the beginning of the line
References: <I60d0fa90656f85ecb8acc357fe6518baa773505b+0@gerrit.coreboot.org>
Message-ID: <I60d0fa90656f85ecb8acc357fe6518baa773505b+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/754

-gerrit

commit 19d475190af5a6bced0a07bd79b6432e232eef18
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:52:30 2011 -0800

    labels should start at the beginning of the line
    
    cosmetical fix
    
    Change-Id: I60d0fa90656f85ecb8acc357fe6518baa773505b
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/cpu/x86/lapic/secondary.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index 5c1e760..dc00b08 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -47,7 +47,7 @@ _secondary_start:
 1:	hlt
 	jmp	1b
 
-	gdtaddr:
+gdtaddr:
 	.word   gdt_limit	/* the table limit */
 	.long   gdt             /* we know the offset */
 



From gerrit at coreboot.org  Wed Mar  7 20:22:46 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:46 +0100
Subject: [coreboot] Patch set updated for coreboot: ea93a3c use movsl for
	copying resume memory back
References: <Ibab0b478873912d67bf1f07743f628586353368a+0@gerrit.coreboot.org>
Message-ID: <Ibab0b478873912d67bf1f07743f628586353368a+4@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/755

-gerrit

commit ea93a3c17ffcdf9e8cf08a189195a141af646cc7
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:03:38 2011 -0800

    use movsl for copying resume memory back
    
    It's not significantly faster, but easier to read and smaller.
    
    Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/boot/wakeup.S |   20 ++++----------------
 1 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..f12b176 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@ __wakeup:
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
 	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)



From gerrit at coreboot.org  Wed Mar  7 20:22:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:47 +0100
Subject: [coreboot] Patch set updated for coreboot: c4df5da Fix warnings in
	coreboot utilities.
References: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+0@gerrit.coreboot.org>
Message-ID: <I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/752

-gerrit

commit c4df5da25f4e8f76c51e593306d94bf648ad4142
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Nov 14 12:40:34 2011 -0800

    Fix warnings in coreboot utilities.
    
    Fix some poor programming practice (breaks of strict aliasing as well as not
    checking the return value of read)
    
    Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/inteltool/cpu.c           |    6 ++++--
 util/inteltool/inteltool.c     |    4 +++-
 util/nvramtool/cli/nvramtool.c |    3 ++-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 20748bd..3bffa4e 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -67,8 +67,10 @@ msr_t rdmsr(int addr)
 	}
 
 	if (read(fd_msr, buf, 8) == 8) {
-		msr.lo = *(uint32_t *)buf;
-		msr.hi = *(uint32_t *)(buf + 4);
+		msr.lo = buf[0] | (buf[1] << 8) |
+			 (buf[2] << 16) | (buf[3] << 24);
+		msr.hi = buf[4] | (buf[5] << 8) |
+			 (buf[6] << 16) | (buf[7] << 24);
 
 		return msr;
 	}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 6b99605..e5c2b86 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -21,6 +21,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <inttypes.h>
 #include <getopt.h>
 #include <fcntl.h>
 #include <sys/mman.h>
@@ -99,7 +100,8 @@ void *map_physical(uint64_t phys_addr, size_t len)
 		    fd_mem, (off_t) phys_addr);
 
 	if (virt_addr == MAP_FAILED) {
-		printf("Error mapping physical memory 0x%08lx[0x%zx]\n", phys_addr, len);
+		printf("Error mapping physical memory 0x%08" PRIx64 "[0x%zx]\n",
+			phys_addr, len);
 		return NULL;
 	}
 
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index 11a1a70..20097b8 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -143,7 +143,8 @@ int main(int argc, char *argv[])
 
 		if (fd_stat.st_size < 128) {
 			lseek(fd, 127, SEEK_SET);
-			write(fd, "\0", 1);
+			if (write(fd, "\0", 1) != 1)
+				fprintf(stderr, "Write failed.\n");
 			fsync(fd);
 		}
 



From gerrit at coreboot.org  Wed Mar  7 20:22:47 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:47 +0100
Subject: [coreboot] Patch set updated for coreboot: 3759c0a vga_io.c is not
	needed unless CONFIG_VGA is set
References: <I7b406251a2f3830748140a111f76f2792fe923ed+0@gerrit.coreboot.org>
Message-ID: <I7b406251a2f3830748140a111f76f2792fe923ed+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/753

-gerrit

commit 3759c0aade0964783da50516075c3caebb8e0ed4
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 11:13:36 2011 -0800

    vga_io.c is not needed unless CONFIG_VGA is set
    
    hence disable it.
    
    Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/pc80/vga/Makefile.inc |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/pc80/vga/Makefile.inc b/src/pc80/vga/Makefile.inc
index 0ca7896..d4b726a 100644
--- a/src/pc80/vga/Makefile.inc
+++ b/src/pc80/vga/Makefile.inc
@@ -1,4 +1,4 @@
-ramstage-y += vga_io.c
+ramstage-$(CONFIG_VGA) += vga_io.c
 ramstage-$(CONFIG_VGA) += vga_palette.c
 ramstage-$(CONFIG_VGA) += vga_font_8x16.c
 ramstage-$(CONFIG_VGA) += vga.c



From gerrit at coreboot.org  Wed Mar  7 20:22:48 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:48 +0100
Subject: [coreboot] Patch set updated for coreboot: ef76c56 Make PCI CONF2
	support a compile time option.
References: <I17df94a8a77b9338fde10a6b114b44d393776e66+0@gerrit.coreboot.org>
Message-ID: <I17df94a8a77b9338fde10a6b114b44d393776e66+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/758

-gerrit

commit ef76c56da3a73f82cb284cd16a186bfb30afd07a
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 13:05:31 2011 -0800

    Make PCI CONF2 support a compile time option.
    
    It's not used on any board supported by coreboot but has been
    detected at run time since ages. No new boards (since 2000?)
    are using the CONF2 method, so it is unlikely we ever have to
    turn this on for a board.
    
    Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/arch/x86/Kconfig            |    4 ++++
 src/arch/x86/lib/Makefile.inc   |    4 +---
 src/arch/x86/lib/pci_ops_auto.c |    9 ++++++++-
 3 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 078ae95..bc01c9c 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -96,4 +96,8 @@ config LITTLE_ENDIAN
 	bool
 	default !BIG_ENDIAN
 
+config PCI_CONF2
+	bool
+	default n
+
 endmenu
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3f4dc95..96fb9b0 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -1,10 +1,8 @@
 ramstage-y += c_start.S
 ramstage-y += cpu.c
 ramstage-y += pci_ops_conf1.c
-ramstage-y += pci_ops_conf2.c
-
+ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
 ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
index 92eedd3..58e098b 100644
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ b/src/arch/x86/lib/pci_ops_auto.c
@@ -6,6 +6,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 
+#if CONFIG_PCI_CONF2
 /*
  * Before we decide to use direct hardware access mechanisms, we try to do some
  * trivial checks to ensure it at least _seems_ to be working -- we just test
@@ -41,7 +42,7 @@ static int pci_sanity_check(const struct pci_bus_operations *o)
 	return 0;
 }
 
-struct pci_bus_operations *pci_bus_fallback_ops = NULL;
+static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
 
 static const struct pci_bus_operations *pci_check_direct(void)
 {
@@ -89,6 +90,12 @@ const struct pci_bus_operations *pci_remember_direct(void)
 		pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
 	return pci_bus_fallback_ops;
 }
+#else
+const struct pci_bus_operations *pci_remember_direct(void)
+{
+	return &pci_cf8_conf1;
+}
+#endif
 
 /** Set the method to be used for PCI, type I or type II
  */



From gerrit at coreboot.org  Wed Mar  7 20:22:49 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:49 +0100
Subject: [coreboot] Patch set updated for coreboot: 484a702 Fix romcc to
	compile cleanly
References: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+0@gerrit.coreboot.org>
Message-ID: <I6f42684f39a4135b0fe64219b8c7f058275c9fee+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/759

-gerrit

commit 484a7021d3876b265039c8e242c48b2e7bf98a68
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Dec 6 22:14:57 2011 +0000

    Fix romcc to compile cleanly
    
    There have been many unused variable assignments in the romcc source
    file. They cause multiple warning messages during build process which
    in turn make it harder to see the actual error message, when they are
    present.
    
    The fix is to remove dead code and to add -Werror to romcc compilation
    to avoid issues like this creeping in in the future.
    
    Change-Id: I6f42684f39a4135b0fe64219b8c7f058275c9fee
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 util/romcc/Makefile |    2 +-
 util/romcc/romcc.c  |    3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/util/romcc/Makefile b/util/romcc/Makefile
index 6543fbb..8242eb5 100644
--- a/util/romcc/Makefile
+++ b/util/romcc/Makefile
@@ -1,7 +1,7 @@
 # Move the configuration defines to makefile.conf
 CC=gcc
 CPPFLAGS=
-CFLAGS= -g -Wall $(CPPFLAGS)
+CFLAGS= -g -Wall -Werror $(CPPFLAGS)
 CPROF_FLAGS=-pg -fprofile-arcs
 
 all: romcc test
diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c
index c7ef223..7eee439 100644
--- a/util/romcc/romcc.c
+++ b/util/romcc/romcc.c
@@ -9161,8 +9161,7 @@ static void decompose_compound_types(struct compile_state *state)
 {
 	struct triple *ins, *next, *first;
 #if DEBUG_DECOMPOSE_HIRES
-	FILE *fp;
-	fp = state->dbgout;
+	FILE *fp = state->dbgout;
 #endif
 	first = state->first;
 	ins = first;



From gerrit at coreboot.org  Wed Mar  7 20:22:50 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:50 +0100
Subject: [coreboot] Patch set updated for coreboot: 7f7ba8b Don't
	unconditionally add support for cardbus and pci-x devices
References: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+0@gerrit.coreboot.org>
Message-ID: <I8b6539eaf2f8d6a4fa975deb14789a00f2090d34+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/756

-gerrit

commit 7f7ba8b34c759012009f39d5929eec2125d42254
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Wed Nov 30 12:45:14 2011 -0800

    Don't unconditionally add support for cardbus and pci-x devices
    
    It's still on by default.
    
    Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Makefile.inc |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
index 86b4d21..9ffc0bb 100644
--- a/src/devices/Makefile.inc
+++ b/src/devices/Makefile.inc
@@ -3,10 +3,10 @@ ramstage-y += root_device.c
 ramstage-y += device_util.c
 ramstage-y += pci_device.c
 ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
-ramstage-y += pcix_device.c
+ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
 ramstage-y += pciexp_device.c
-ramstage-y += agp_device.c
-ramstage-y += cardbus_device.c
+ramstage-$(CONFIG_AGP_PLUGIN_SUPPORT) += agp_device.c
+ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
 ramstage-y += pnp_device.c
 ramstage-y += pci_ops.c
 ramstage-y += smbus_ops.c



From gerrit at coreboot.org  Wed Mar  7 20:22:50 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:50 +0100
Subject: [coreboot] Patch set updated for coreboot: fe0b190 Add DEBUG_TPM
	option to Debugging menu
References: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+0@gerrit.coreboot.org>
Message-ID: <I519d9ada14dd383e668a2da4219e5373a24c7c3d+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/757

-gerrit

commit fe0b190cb629fdb6884aa96c0ca01582680bb804
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Nov 17 12:50:54 2011 -0800

    Add DEBUG_TPM option to Debugging menu
    
    instead of having to edit the source code of tpm.c
    
    Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig    |    7 +++++++
 src/pc80/tpm.c |    9 +--------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 26e6dde..41c5dbf 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -870,6 +870,13 @@ config X86EMU_DEBUG_IO
 
 	  If unsure, say N.
 
+config DEBUG_TPM
+	bool "Output verbose TPM debug messages"
+	default n
+	depends on TPM
+	help
+	  This option enables additional TPM related debug messages.
+
 config LLSHELL
 	bool "Built-in low-level shell"
 	default n
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
index 8e94303..17e1ed7 100644
--- a/src/pc80/tpm.c
+++ b/src/pc80/tpm.c
@@ -27,7 +27,6 @@
  * Infineon slb9635), so this driver provides access to locality 0 only.
  */
 
-/* #define DEBUG */
 #include <stdlib.h>
 #include <string.h>
 #include <delay.h>
@@ -37,17 +36,11 @@
 #include <pc80/tpm.h>
 #include <cpu/x86/car.h>
 
-#ifdef DEBUG
-#define TPM_DEBUG_ON	1
-#else
-#define TPM_DEBUG_ON	0
-#endif
-
 #define PREFIX "lpc_tpm: "
 
 /* coreboot wrapper for TPM driver (start) */
 #define	TPM_DEBUG(fmt, args...)		\
-	if (TPM_DEBUG_ON) {		\
+	if (CONFIG_DEBUG_TPM) {		\
 		printk(BIOS_DEBUG, PREFIX);		\
 		printk(BIOS_DEBUG, fmt , ##args);	\
 	}



From gerrit at coreboot.org  Wed Mar  7 20:22:51 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:51 +0100
Subject: [coreboot] Patch set updated for coreboot: e14abc7 Don't run VGA
	option ROMs on S3 resume.
References: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+0@gerrit.coreboot.org>
Message-ID: <Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/715

-gerrit

commit e14abc76e6fb9f82436e3710959a5505f659d315
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Fri Sep 23 10:33:58 2011 -0700

    Don't run VGA option ROMs on S3 resume.
    
    This will save us a few 100 ms on resume.
    
    Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig      |    7 +++++++
 src/devices/pci_device.c |   11 +++++++++++
 2 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 9e5ea6e..572addc 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -33,6 +33,13 @@ config VGA_ROM_RUN
 	  Execute VGA option ROMs, if found. This is required to enable
 	  PCI/AGP/PCI-E video cards.
 
+config S3_VGA_ROM_RUN
+	bool "Re-run VGA option ROMs on S3 resume"
+	default y
+	depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+	help
+	  Execute VGA option ROMs when coming out of an S3 resume.
+
 config PCI_ROM_RUN
 	bool "Run non-VGA option ROMs"
 	default y
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..0a870b8 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -51,6 +51,9 @@
 #if CONFIG_PC80_SYSTEM == 1
 #include <pc80/i8259.h>
 #endif
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+#include <arch/acpi.h>
+#endif
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
@@ -672,6 +675,14 @@ void pci_dev_init(struct device *dev)
 	if (ram == NULL)
 		return;
 
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if ((acpi_slp_type == 3) &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return;
+#endif
 	run_bios(dev, (unsigned long)ram);
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 }



From gerrit at coreboot.org  Wed Mar  7 20:22:52 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:52 +0100
Subject: [coreboot] Patch set updated for coreboot: a6e3815 Add cmos helper
	functions for reading/writing a dword
References: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+0@gerrit.coreboot.org>
Message-ID: <I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/717

-gerrit

commit a6e3815e02d6e7eaf381fbf64ff8fe6f22dabf3a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Sep 26 13:24:40 2011 -0700

    Add cmos helper functions for reading/writing a dword
    
    These get used later for saving/restoring the MRC scrambler
    seed values on each boot.
    
    Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/include/pc80/mc146818rtc.h |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 3e5a61a..24dac2c 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -104,6 +104,22 @@ static inline void cmos_write(unsigned char val, unsigned char addr)
 	outb(addr, RTC_BASE_PORT + offs + 0);
 	outb(val, RTC_BASE_PORT + offs + 1);
 }
+
+static inline u32 cmos_read32(u8 offset)
+{
+	u32 value = 0;
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		value |= cmos_read(offset + i) << (i << 3);
+	return value;
+}
+
+static inline void cmos_write32(u8 offset, u32 value)
+{
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		cmos_write((value >> (i << 3)) & 0xff, offset + i);
+}
 #endif
 
 #if !defined(__ROMCC__)



From gerrit at coreboot.org  Wed Mar  7 20:22:53 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:53 +0100
Subject: [coreboot] Patch set updated for coreboot: c98f469 Add timestamp
	table pointer to the coreboot table.
References: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+0@gerrit.coreboot.org>
Message-ID: <Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/716

-gerrit

commit c98f469e29f49887d16d94392e6888d5ca66ebd0
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 23 09:56:11 2011 -0700

    Add timestamp table pointer to the coreboot table.
    
    This change exports the timestamp table pointer through coreboot
    table to make it possible for u-boot to add timestamps to the
    table.
    
    Inclusion of cbmem.h allows to drop external declarations in
    coreboot_table.c.
    
    Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   25 +++++++++++++++++++++----
 src/include/boot/coreboot_tables.h |    8 ++++++++
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index b0dcc9e..f189e76 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -30,6 +30,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <cbfs.h>
+#include <cbmem.h>
 #if CONFIG_USE_OPTION_TABLE
 #include <option_table.h>
 #endif
@@ -174,6 +175,23 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
+#if CONFIG_COLLECT_TIMESTAMPS
+static void lb_tsamp(struct lb_header *header)
+{
+	struct lb_tstamp *tstamp;
+	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+
+	if (!tstamp_table)
+		return;
+
+	tstamp = (struct lb_tstamp *)lb_new_record(header);
+	tstamp->tag = LB_TAG_TIMESTAMPS;
+	tstamp->size = sizeof(*tstamp);
+	tstamp->tstamp_tab = tstamp_table;
+
+}
+#endif
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -513,10 +531,6 @@ static void add_lb_reserved(struct lb_memory *mem)
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
@@ -619,6 +633,9 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	lb_tsamp(head);
+#endif
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 45ba3af..46d6489 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -195,6 +195,14 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_TIMESTAMPS	0x0016
+struct lb_tstamp {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*tstamp_tab;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */



From gerrit at coreboot.org  Wed Mar  7 20:22:54 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:54 +0100
Subject: [coreboot] Patch set updated for coreboot: f24a9b9 CBMEM CONSOLE:
	Add CBMEM console driver implementation.
References: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+0@gerrit.coreboot.org>
Message-ID: <I8c126e31db6cb2141f7f4f97c5047f39a8db44fc+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/719

-gerrit

commit f24a9b904926af4039bc2530918d77a886f029b7
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Thu Sep 29 17:27:15 2011 -0700

    CBMEM CONSOLE: Add CBMEM console driver implementation.
    
    The CBMEM console driver saves console output in a CBMEM area, which
    then is made available to Linux applications for perusing.
    
    There are some system limitations which need to be worked around
    to achieve this goal:
    
    - some console traffic is generated before DRAM is initialized,
      leave alone CBMEM initialized.
    
    - after the RAM based stage starts, a lot of traffic is generated
      before CBMEM is initialized.
    
    As a result, the console log lives in three different places -
    the bottom of the cache as RAM space, the CBMEM buffer (where it
    is expected to be) and a static buffer used early in the RAM
    stage.
    
    When execution starts (in the cache as RAM mode), the console
    buffer is allocated at the bottom of the cache as RAM memory
    address range. Once DRAM is initialized, the CBMEM structure is
    initialized, and then the console buffer contents are copied from
    the bottom of the cache as RAM space into the CBMEM area right
    before the cache as RAM mode is disabled. The
    src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
    copying.
    
    At this point the cache as RAM memory is about to be disabled,
    but the ROM stage is still going generating console output. To
    make sure this output is not lost, cbmemc_reinit() saves the new
    buffer address at a fixed location (0x600 was chosen for this),
    and the actual "printing" function checks to see if the RAM is
    already initialized (the stack is in RAM), and if so, gets the
    console buffer pointer from this location instead of using the
    cache as RAM address.
    
    When the RAM stage starts, a static buffer is used to store the
    console output, as the CBMEM buffer location is not known. Then,
    when CBMEM is reinitialized, cbmemc_reinit() again takes care of
    the copying.
    
    In case the allocated buffers are not large enough, the excessive
    data is dropped, and the copying routine adds some text to the
    output buffer to indicate that there has been data lost and how
    many characters were dropped.
    
    Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/cbmem_console.c         |   35 ++++++
 src/include/console/cbmem_console.h |   26 +++++
 src/include/console/console.h       |    3 +
 src/lib/cbmem_console.c             |  195 +++++++++++++++++++++++++++++++++++
 4 files changed, 259 insertions(+), 0 deletions(-)

diff --git a/src/console/cbmem_console.c b/src/console/cbmem_console.c
new file mode 100644
index 0000000..2c43f5c
--- /dev/null
+++ b/src/console/cbmem_console.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+
+static void cbmemc_init_(void)
+{
+	cbmemc_init();
+}
+
+static void cbmemc_tx_byte_(unsigned char data)
+{
+	cbmemc_tx_byte(data);
+}
+
+static const struct console_driver cbmem_console __console = {
+	.init     = cbmemc_init_,
+	.tx_byte  = cbmemc_tx_byte_,
+};
diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h
new file mode 100644
index 0000000..37ea4d8
--- /dev/null
+++ b/src/include/console/cbmem_console.h
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+#ifndef _CONSOLE_CBMEM_CONSOLE_H_
+#define _CONSOLE_CBMEM_CONSOLE_H_
+
+void cbmemc_init(void);
+void cbmemc_reinit(void);
+void cbmemc_tx_byte(unsigned char data);
+
+#endif
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 54c825c..56e202d 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -33,6 +33,9 @@
 #if CONFIG_CONSOLE_NE2K
 #include <console/ne2k.h>
 #endif
+#if CONFIG_CONSOLE_CBMEM
+#include <console/cbmem_console.h>
+#endif
 
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
new file mode 100644
index 0000000..b58de48
--- /dev/null
+++ b/src/lib/cbmem_console.c
@@ -0,0 +1,195 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <string.h>
+
+/*
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * whith buffer_body covering the extent of the memory. Once the buffer is
+ * full, the cursor keeps going but the data is dropped on the floor. This
+ * allows to tell how much data was lost in the process.
+ */
+struct cbmem_console {
+	u32 buffer_size;
+	u32 buffer_cursor;
+	u8  buffer_body[0];
+}  __attribute__ ((__packed__));
+
+#ifdef __PRE_RAM__
+/*
+ * While running from ROM, before DRAM is initialized, some area in cache as
+ * ram space is used for the console buffer storage. The size and location of
+ * the area are defined in the config.
+ */
+#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+/*
+ * Once DRAM is initialized and the cache as ram mode is disabled, while still
+ * running from ROM, the console buffer in the cache as RAM area becomes
+ * unavailable.
+ *
+ * By this time the console log buffer is already available in
+ * CBMEM. The location at 0x600 is used as the redirect pointer allowing to
+ * find out where the actual console log buffer is.
+ */
+#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600))
+#else
+
+/*
+ * When running from RAM, a lot of console output is generated before CBMEM is
+ * reinitialized. This static buffer is used to store that output temporarily,
+ * to be concatenated with the CBMEM console buffer contents accumulated
+ * during the ROM stage, once CBMEM becomes avaiklable at RAM stage.
+ */
+static u8 static_console[40000];
+static struct cbmem_console *cbmem_console_p;
+#endif
+
+void cbmemc_init(void)
+{
+#ifdef __PRE_RAM__
+	cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+#else
+	/*
+	 * Initializing before CBMEM is available, use static buffer to store
+	 * the log.
+	 */
+	cbmem_console_p = (struct cbmem_console *) static_console;
+	cbmem_console_p->buffer_size = sizeof(static_console) -
+		sizeof(struct cbmem_console);
+#endif
+	cbmem_console_p->buffer_cursor = 0;
+}
+
+void cbmemc_tx_byte(unsigned char data)
+{
+	struct cbmem_console *cbm_cons_p = cbmem_console_p;
+	u32 cursor;
+#ifdef __PRE_RAM__
+	/*
+	 * This check allows to tell if the cache as RAM mode has been exited
+	 * or not. If it has been exited, the real memory is being used
+	 * (resulting in the variable on the stack located below
+	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
+	 * actual console buffer is.
+	 */
+	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
+#endif
+	if (!cbm_cons_p)
+		return;
+
+	cursor = cbm_cons_p->buffer_cursor++;
+	if (cursor < cbm_cons_p->buffer_size)
+		cbm_cons_p->buffer_body[cursor] = data;
+}
+
+/*
+ * Copy the current console buffer (either from the cache as RAM area, or from
+ * the static buffer, pointed at by cbmem_console_p) into the CBMEM console
+ * buffer space (pointed at by new_cons_p), concatenating the copied data with
+ * the CBMEM console buffer contents.
+ *
+ * If there is overflow - add to the destination area a string, reporting the
+ * overflow and the number of dropped charactes.
+ */
+static void copy_console_buffer(struct cbmem_console *new_cons_p)
+{
+	u32 copy_size;
+	u32 cursor = new_cons_p->buffer_cursor;
+	int overflow = cbmem_console_p->buffer_cursor >
+		cbmem_console_p->buffer_size;
+
+	copy_size = overflow ?
+		cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor;
+
+	memcpy(new_cons_p->buffer_body + cursor,
+	       cbmem_console_p->buffer_body,
+	       copy_size);
+
+	cursor += copy_size;
+
+	if (overflow) {
+		const char loss_str1[] = "\n\n*** Log truncated, ";
+		const char loss_str2[] = " characters dropped. ***\n\n";
+		u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size;
+
+		/*
+		 * When running from ROM sprintf is not available, a simple
+		 * itoa implementation is used instead.
+		 */
+		int got_first_digit = 0;
+
+		/* Way more than possible number of dropped characters. */
+		u32 mult = 100000;
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1);
+		cursor += sizeof(loss_str1) - 1;
+
+		while (mult) {
+			int digit = dropped_chars / mult;
+			if (got_first_digit || digit) {
+				new_cons_p->buffer_body[cursor++] = digit + '0';
+				dropped_chars %= mult;
+				/* Excessive, but keeps it simple */
+				got_first_digit = 1;
+			}
+			mult /= 10;
+		}
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2);
+		cursor += sizeof(loss_str2) - 1;
+	}
+	new_cons_p->buffer_cursor = cursor;
+}
+
+void cbmemc_reinit(void)
+{
+	struct cbmem_console *cbm_cons_p;
+
+#ifdef __PRE_RAM__
+	cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE,
+			       CONFIG_CONSOLE_CBMEM_BUFFER_SIZE);
+	if (!cbm_cons_p) {
+		CBMEM_CONSOLE_REDIRECT = NULL;
+		return;
+	}
+
+	cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+
+	cbm_cons_p->buffer_cursor = 0;
+
+	copy_console_buffer(cbm_cons_p);
+
+	CBMEM_CONSOLE_REDIRECT = cbm_cons_p;
+#else
+	cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (!cbm_cons_p)
+		return;
+
+	copy_console_buffer(cbm_cons_p);
+
+	cbmem_console_p = cbm_cons_p;
+#endif
+}



From gerrit at coreboot.org  Wed Mar  7 20:22:55 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:55 +0100
Subject: [coreboot] Patch set updated for coreboot: 05b3eee CBMEM CONSOLE:
	Add config option for CBMEM stored console log.
References: <I209603f516244ae136631e6281ba21ebc6fb1710+0@gerrit.coreboot.org>
Message-ID: <I209603f516244ae136631e6281ba21ebc6fb1710+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/718

-gerrit

commit 05b3eeef8c098f761f4c7a61fbd27cc7b7175ec6
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Wed Sep 28 13:51:30 2011 -0700

    CBMEM CONSOLE: Add config option for CBMEM stored console log.
    
    Some experiments have demonstrated that total amount of text
    generated by coreboot console when BIOS_SPEW level is enabled
    exceeds 40KB.
    
    Console output generated before DRAM is initialized can exceed
    2KB. This patch introduces the new configuration option and
    assigns adequate default values to cache based and DRAM based
    console buffers.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
     . run the following commands in the root directory
    
       cp config.stumpy .config
       make menuconfig
    
     . enable the new option (Console->Send console output to a CBMEM buffer)
     . save the configuration
    
    Observe the following settings added to the config:
    +CONFIG_CONSOLE_CBMEM=y
    +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
    +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
    
    Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5855
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index dbd11f6..fefbe2e 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -190,6 +190,33 @@ config CONSOLE_NE2K_IO_PORT
 	  32 bytes of IO spaces will be used (and align on 32 bytes
 	  boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+	depends on EARLY_CBMEM_INIT
+	bool "Send console output to a CBMEM buffer"
+	default n
+	help
+	  Enable this to save the console output in a CBMEM buffer. This would
+	  allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in CBMEM"
+	default 0xae00
+	help
+	  Space allocated for console output storage in CBMEM. The default
+	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+	  even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in cash as RAM"
+	default 0xc00
+	help
+	  Console is used before RAM is initialized. This is the room reserved
+	  in the DCACHE based RAM to keep console output before it can be
+	  saved in a CBMEM buffer. 3K bytes should be enough even for the
+	  BIOS_SPEW level.
+
 
 choice
 	prompt "Maximum console log level"



From gerrit at coreboot.org  Wed Mar  7 20:22:56 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:22:56 +0100
Subject: [coreboot] Patch set updated for coreboot: f39995e Detect whether
	the OXPCIE card is really present while in the ROM stage.
References: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+0@gerrit.coreboot.org>
Message-ID: <I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/728

-gerrit

commit f39995ec5b90cc5c0fa7ad5247a68e3938f4fba1
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:52:08 2011 -0700

    Detect whether the OXPCIE card is really present while in the ROM stage.
    
    Use an int in CAR global data to store whether or not the OXPCIE serial card
    is actually there. Also, time out if the card doesn't show up quickly enough,
    don't continue initialization if it's not there, and don't make the
    initialization routine default to a card if none is found.
    
    Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/lib/romstage_console.c      |    5 ++++-
 src/drivers/oxford/oxpcie/oxpcie_early.c |   20 +++++++++++++++++---
 src/include/uart8250.h                   |    5 +++++
 3 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 0f22727..25eda9b 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -35,7 +35,10 @@ static void console_tx_byte(unsigned char byte)
 		console_tx_byte('\r');
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
-	uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	if (oxford_oxpcie_present) {
+		uart8250_mem_tx_byte(
+			CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	}
 #endif
 #if CONFIG_CONSOLE_SERIAL8250
 	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 2c7767e..4f7a3cb 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -34,9 +36,13 @@
 #define OXPCIE_DEVICE_3 \
 	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
 
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
+
 void oxford_init(void)
 {
 	u16 reg16;
+	oxford_oxpcie_present = 1;
 
 	/* First we reset the secondary bus */
 	reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -69,11 +75,14 @@ void oxford_init(void)
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if
-	// no device is in the slot.
+	u32 timeout = 20000; // Timeout in 10s of microseconds.
 	u32 id = 0;
-	while ((id == 0) || (id == 0xffffffff))
+	for (;;) {
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+		if (!timeout-- || (id != 0 && id != 0xffffffff))
+			break;
+		udelay(10);
+	}
 
 	u32 device = OXPCIE_DEVICE; /* unknown default */
 	switch (id) {
@@ -90,6 +99,10 @@ void oxford_init(void)
 	case 0xc1581415: /* e.g. Startech MPEX2S952 */
 		device = OXPCIE_DEVICE;
 		break;
+	default:
+		/* No UART here. */
+		oxford_oxpcie_present = 0;
+		return;
 	}
 
 	/* Setup base address on device */
@@ -107,3 +120,4 @@ void oxford_init(void)
 	uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index aa510e5..71b9a5f 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -135,8 +135,13 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
 u32 uartmem_getbaseaddr(void);
 
+#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
+	CONFIG_CONSOLE_SERIAL8250MEM
 /* and special init for OXPCIe based cards */
+extern int oxford_oxpcie_present;
+
 void oxford_init(void);
+#endif
 
 #endif /* __ROMCC__ */
 



From gerrit at coreboot.org  Wed Mar  7 20:23:00 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:00 +0100
Subject: [coreboot] Patch set updated for coreboot: ce5ca60 If the memory
	mapped UART isn't present, leave it out of the cb tables.
References: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+0@gerrit.coreboot.org>
Message-ID: <I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/729

-gerrit

commit ce5ca6042e1e71c331e9ef68e9fbabc60980e112
Author: Gabe Black <gabeblack at google.com>
Date:   Wed Oct 5 01:57:03 2011 -0700

    If the memory mapped UART isn't present, leave it out of the cb tables.
    
    This way u-boot won't try to use a UART that isn't plugged in.
    
    Change-Id: I9a3a0d074dd03add8afbd4dad836c4c6a05abe6f
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/boot/coreboot_table.c |   24 ++++++++++++++----------
 1 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f29481b..d24d7c4 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -118,16 +118,20 @@ static struct lb_serial *lb_serial(struct lb_header *header)
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
 #elif CONFIG_CONSOLE_SERIAL8250MEM
-	struct lb_record *rec;
-	struct lb_serial *serial;
-	rec = lb_new_record(header);
-	serial = (struct lb_serial *)rec;
-	serial->tag = LB_TAG_SERIAL;
-	serial->size = sizeof(*serial);
-	serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial->baseaddr = uartmem_getbaseaddr();
-	serial->baud = CONFIG_TTYS0_BAUD;
-	return serial;
+	if (uartmem_getbaseaddr()) {
+		struct lb_record *rec;
+		struct lb_serial *serial;
+		rec = lb_new_record(header);
+		serial = (struct lb_serial *)rec;
+		serial->tag = LB_TAG_SERIAL;
+		serial->size = sizeof(*serial);
+		serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+		serial->baseaddr = uartmem_getbaseaddr();
+		serial->baud = CONFIG_TTYS0_BAUD;
+		return serial;
+	} else {
+		return NULL;
+	}
 #else
 	return NULL;
 #endif



From gerrit at coreboot.org  Wed Mar  7 20:23:01 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:01 +0100
Subject: [coreboot] Patch set updated for coreboot: bb711d3 Don't run any
	option roms stored outside of the system flash
References: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+0@gerrit.coreboot.org>
Message-ID: <I485291c06ec5cd1f875357401831fe32ccfc5f2f+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/730

-gerrit

commit bb711d3f6dbde4db589fefb0cc10d49a62a944ba
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Thu Oct 6 16:47:51 2011 -0700

    Don't run any option roms stored outside of the system flash
    
    Right now coreboot only executes vga option roms. However, this is not
    good enough. For security reasons we want to execute only option roms
    stored in our RO CBFS.
    
    This patch adds a new option to disable execution of arbitrary option
    ROMs and enables it for all our boards.
    
    Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/devices/Kconfig   |   13 +++++++++++++
 src/devices/pci_rom.c |    6 ++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 572addc..98e8d9f 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -49,6 +49,19 @@ config PCI_ROM_RUN
 	  Examples include IDE/SATA controller option ROMs and option ROMs
 	  for network cards (NICs).
 
+config ON_DEVICE_ROM_RUN
+	bool "Run option ROMs on PCI devices"
+	default y
+	help
+	  Execute option ROMs that are stored on PCI/PCIe/AGP devices.
+
+	  If disabled, only option ROMs stored in CBFS will be executed. If
+	  you are concerned about security, you might want to disable this
+	  option, but it might leave your system in a state of degraded
+	  functionality.
+
+	  If unsure, say Y
+
 choice
 	prompt "Option ROM execution type"
 	default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 471c7e2..1b6f1da 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -71,9 +71,15 @@ struct rom_header *pci_rom_probe(struct device *dev)
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
+#if CONFIG_ON_DEVICE_ROM_RUN
 		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+#else
+		printk(BIOS_DEBUG, "On card option ROM execution disabled "
+			"for %s\n", dev_path(dev));
+		return NULL;
+#endif
 	}
 
 	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "



From gerrit at coreboot.org  Wed Mar  7 20:23:10 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:10 +0100
Subject: [coreboot] Patch set updated for coreboot: f91f4dc Add TPM support
	to coreboot
References: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+0@gerrit.coreboot.org>
Message-ID: <I000d4322ef313e931e23c56defaa17e3a4d7f8cf+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/731

-gerrit

commit f91f4dc2549767500e0f7d069f7c913767298ce8
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 11 14:46:25 2011 -0700

    Add TPM support to coreboot
    
    and initialize the TPM on S3 resume
    
    This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
    resume without including any other parts of vboot.
    
    We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
    (that are incompatible with coreboot's) and it does a lot more than we
    want it to do.
    
    Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/Kconfig                            |    4 +
 src/arch/x86/boot/acpi.c               |    8 +
 src/include/pc80/tpm.h                 |   29 ++
 src/pc80/Makefile.inc                  |    1 +
 src/pc80/tpm.c                         |  554 ++++++++++++++++++++++++++++++++
 src/vendorcode/google/chromeos/vboot.c |  201 ++++++++++++
 6 files changed, 797 insertions(+), 0 deletions(-)

diff --git a/src/Kconfig b/src/Kconfig
index 573868f..26e6dde 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -262,6 +262,10 @@ config IOAPIC
 	bool
 	default n
 
+config TPM
+	bool
+	default n
+
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
 	int
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index f1be034..eb2e4e1 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -525,6 +528,11 @@ void *acpi_find_wakeup_vector(void)
 	if (!acpi_is_wakeup())
 		return NULL;
 
+#ifdef CONFIG_CHROMEOS
+	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+	init_vboot();
+#endif
+
 	printk(BIOS_DEBUG, "Trying to find the wakeup vector...\n");
 
 	/* Find RSDP. */
diff --git a/src/include/pc80/tpm.h b/src/include/pc80/tpm.h
new file mode 100644
index 0000000..2eff15a
--- /dev/null
+++ b/src/include/pc80/tpm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef TPM_H_
+#define TPM_H_
+
+int tis_init(void);
+int tis_open(void);
+int tis_close(void);
+int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
+			size_t *recv_len);
+
+#endif /* TPM_H_ */
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 2c8a80e..cd6ea33 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -4,6 +4,7 @@ ramstage-y += i8254.c
 ramstage-y += i8259.c
 ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
 ramstage-y += keyboard.c
+ramstage-$(CONFIG_TPM) += tpm.c
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 subdirs-y += vga
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
new file mode 100644
index 0000000..1cbf800
--- /dev/null
+++ b/src/pc80/tpm.c
@@ -0,0 +1,554 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The code in this file has been heavily based on the article "Writing a TPM
+ * Device Driver" published on http://ptgmedia.pearsoncmg.com and the
+ * submission by Stefan Berger on Qemu-devel mailing list.
+ *
+ * One principal difference is that in the simplest config the other than 0
+ * TPM localities do not get mapped by some devices (for instance, by
+ * Infineon slb9635), so this driver provides access to locality 0 only.
+ */
+
+/* #define DEBUG */
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/byteorder.h>
+#include <console/console.h>
+#include <pc80/tpm.h>
+
+#ifdef DEBUG
+#define TPM_DEBUG_ON	1
+#else
+#define TPM_DEBUG_ON	0
+#endif
+
+#define PREFIX "lpc_tpm: "
+
+/* coreboot wrapper for TPM driver (start) */
+#define	TPM_DEBUG(fmt, args...)		\
+	if (TPM_DEBUG_ON) {		\
+		printk(BIOS_DEBUG, PREFIX);		\
+		printk(BIOS_DEBUG, fmt , ##args);	\
+	}
+#define printf(x...) printk(BIOS_ERR, x)
+
+#define min(a,b) MIN(a,b)
+#define max(a,b) MAX(a,b)
+#define readb(_a) (*(volatile unsigned char *) (_a))
+#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v))
+#define readl(_a) (*(volatile unsigned long *) (_a))
+#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v))
+/* coreboot wrapper for TPM driver (end) */
+
+#ifndef CONFIG_TPM_TIS_BASE_ADDRESS
+/* Base TPM address standard for x86 systems */
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+#endif
+
+/* the macro accepts the locality value, but only locality 0 is operational */
+#define TIS_REG(LOCALITY, REG) \
+    (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+
+/* hardware registers' offsets */
+#define TIS_REG_ACCESS                 0x0
+#define TIS_REG_INT_ENABLE             0x8
+#define TIS_REG_INT_VECTOR             0xc
+#define TIS_REG_INT_STATUS             0x10
+#define TIS_REG_INTF_CAPABILITY        0x14
+#define TIS_REG_STS                    0x18
+#define TIS_REG_DATA_FIFO              0x24
+#define TIS_REG_DID_VID                0xf00
+#define TIS_REG_RID                    0xf04
+
+/* Some registers' bit field definitions */
+#define TIS_STS_VALID                  (1 << 7) /* 0x80 */
+#define TIS_STS_COMMAND_READY          (1 << 6) /* 0x40 */
+#define TIS_STS_TPM_GO                 (1 << 5) /* 0x20 */
+#define TIS_STS_DATA_AVAILABLE         (1 << 4) /* 0x10 */
+#define TIS_STS_EXPECT                 (1 << 3) /* 0x08 */
+#define TIS_STS_RESPONSE_RETRY         (1 << 1) /* 0x02 */
+
+#define TIS_ACCESS_TPM_REG_VALID_STS   (1 << 7) /* 0x80 */
+#define TIS_ACCESS_ACTIVE_LOCALITY     (1 << 5) /* 0x20 */
+#define TIS_ACCESS_BEEN_SEIZED         (1 << 4) /* 0x10 */
+#define TIS_ACCESS_SEIZE               (1 << 3) /* 0x08 */
+#define TIS_ACCESS_PENDING_REQUEST     (1 << 2) /* 0x04 */
+#define TIS_ACCESS_REQUEST_USE         (1 << 1) /* 0x02 */
+#define TIS_ACCESS_TPM_ESTABLISHMENT   (1 << 0) /* 0x01 */
+
+#define TIS_STS_BURST_COUNT_MASK       (0xffff)
+#define TIS_STS_BURST_COUNT_SHIFT      (8)
+
+/*
+ * Error value returned if a tpm register does not enter the expected state
+ * after continuous polling. No actual TPM register reading ever returns ~0,
+ * so this value is a safe error indication to be mixed with possible status
+ * register values.
+ */
+#define TPM_TIMEOUT_ERR			(~0)
+
+/* Error value returned on various TPM driver errors */
+#define TPM_DRIVER_ERR		(~0)
+
+ /* 1 second is plenty for anything TPM does.*/
+#define MAX_DELAY_US	(1000 * 1000)
+
+/* Retrieve burst count value out of the status register contents. */
+#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \
+				   TIS_STS_BURST_COUNT_MASK))
+
+/*
+ * Structures defined below allow creating descriptions of TPM vendor/device
+ * ID information for run time discovery. The only device the system knows
+ * about at this time is Infineon slb9635
+ */
+struct device_name {
+	u16 dev_id;
+	const char * const dev_name;
+};
+
+struct vendor_name {
+	u16 vendor_id;
+	const char * vendor_name;
+	struct device_name* dev_names;
+};
+
+static struct device_name infineon_devices[] = {
+	{0xb, "SLB9635 TT 1.2"},
+	{0}
+};
+
+static const struct vendor_name vendor_names[] = {
+	{0x15d1, "Infineon", infineon_devices},
+};
+
+/*
+ * Cached vendor/device ID pair to indicate that the device has been already
+ * discovered
+ */
+static u32 vendor_dev_id;
+
+static int is_byte_reg(u32 reg)
+{
+	/*
+	 * These TPM registers are 8 bits wide and as such require byte access
+	 * on writes and truncated value on reads.
+	 */
+	return ((reg == TIS_REG_ACCESS)	||
+		(reg == TIS_REG_INT_VECTOR) ||
+		(reg == TIS_REG_DATA_FIFO));
+}
+
+/* TPM access functions are carved out to make tracing easier. */
+static u32 tpm_read(int locality, u32 reg)
+{
+	u32 value;
+	/*
+	 * Data FIFO register must be read and written in byte access mode,
+	 * otherwise the FIFO values are returned 4 bytes at a time.
+	 */
+	if (is_byte_reg(reg))
+		value = readb(TIS_REG(locality, reg));
+	else
+		value = readl(TIS_REG(locality, reg));
+
+	TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value);
+	return value;
+}
+
+static void tpm_write(u32 value, int locality,  u32 reg)
+{
+	TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value);
+
+	if (is_byte_reg(reg))
+		writeb(value & 0xff, TIS_REG(locality, reg));
+	else
+		writel(value, TIS_REG(locality, reg));
+}
+
+/*
+ * tis_wait_reg()
+ *
+ * Wait for at least a second for a register to change its state to match the
+ * expected state. Normally the transition happens within microseconds.
+ *
+ * @reg - the TPM register offset
+ * @locality - locality
+ * @mask - bitmask for the bitfield(s) to watch
+ * @expected - value the field(s) are supposed to be set to
+ *
+ * Returns the register contents in case the expected value was found in the
+ * appropriate register bits, or TPM_TIMEOUT_ERR on timeout.
+ */
+static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
+{
+	u32 time_us = MAX_DELAY_US;
+	while (time_us > 0) {
+		u32 value = tpm_read(locality, reg);
+		if ((value & mask) == expected)
+			return value;
+		udelay(1); /* 1 us */
+		time_us--;
+	}
+	return TPM_TIMEOUT_ERR;
+}
+
+/*
+ * Probe the TPM device and try determining its manufacturer/device name.
+ *
+ * Returns 0 on success (the device is found or was found during an earlier
+ * invocation) or TPM_DRIVER_ERR if the device is not found.
+ */
+static u32 tis_probe(void)
+{
+	u32 didvid = tpm_read(0, TIS_REG_DID_VID);
+	int i;
+	const char *device_name = "unknown";
+	const char *vendor_name = device_name;
+	u16 vid, did;
+
+	if (vendor_dev_id)
+		return 0;  /* Already probed. */
+
+	if (!didvid || (didvid == 0xffffffff)) {
+		printf("%s: No TPM device found\n", __FUNCTION__);
+		return TPM_DRIVER_ERR;
+	}
+
+	vendor_dev_id = didvid;
+
+	vid = didvid & 0xffff;
+	did = (didvid >> 16) & 0xffff;
+	for (i = 0; i < ARRAY_SIZE(vendor_names); i++) {
+		int j = 0;
+		u16 known_did;
+		if (vid == vendor_names[i].vendor_id) {
+			vendor_name = vendor_names[i].vendor_name;
+		}
+		while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+			if (known_did == did) {
+				device_name =
+					vendor_names[i].dev_names[j].dev_name;
+				break;
+			}
+			j++;
+		}
+		break;
+	}
+	/* this will have to be converted into debug printout */
+	TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name);
+	return 0;
+}
+
+/*
+ * tis_senddata()
+ *
+ * send the passed in data to the TPM device.
+ *
+ * @data - address of the data to send, byte by byte
+ * @len - length of the data to send
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
+ * not accept the entire command).
+ */
+static u32 tis_senddata(const u8 * const data, u32 len)
+{
+	u32 offset = 0;
+	u16 burst = 0;
+	u32 max_cycles = 0;
+	u8 locality = 0;
+	u32 value;
+
+	value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY,
+			     TIS_STS_COMMAND_READY);
+	if (value == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to get 'command_ready' status\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+	burst = BURST_COUNT(value);
+
+	while (1) {
+		unsigned count;
+
+		/* Wait till the device is ready to accept more data. */
+		while (!burst) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d failed to feed %d bytes of %d\n",
+				       __FILE__, __LINE__, len - offset, len);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS));
+		}
+
+		max_cycles = 0;
+
+		/*
+		 * Calculate number of bytes the TPM is ready to accept in one
+		 * shot.
+		 *
+		 * We want to send the last byte outside of the loop (hence
+		 * the -1 below) to make sure that the 'expected' status bit
+		 * changes to zero exactly after the last byte is fed into the
+		 * FIFO.
+		 */
+		count = min(burst, len - offset - 1);
+		while (count--)
+			tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+		value = tis_wait_reg(TIS_REG_STS, locality,
+				     TIS_STS_VALID, TIS_STS_VALID);
+
+		if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) {
+			printf("%s:%d TPM command feed overflow\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		burst = BURST_COUNT(value);
+		if ((offset == (len - 1)) && burst)
+			/*
+			 * We need to be able to send the last byte to the
+			 * device, so burst size must be nonzero before we
+			 * break out.
+			 */
+			break;
+	}
+
+	/* Send the last byte. */
+	tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+	/*
+	 * Verify that TPM does not expect any more data as part of this
+	 * command.
+	 */
+	value = tis_wait_reg(TIS_REG_STS, locality,
+			     TIS_STS_VALID, TIS_STS_VALID);
+	if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) {
+		printf("%s:%d unexpected TPM status 0x%x\n",
+		       __FILE__, __LINE__, value);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* OK, sitting pretty, let's start the command execution. */
+	tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_readresponse()
+ *
+ * read the TPM device response after a command was issued.
+ *
+ * @buffer - address where to read the response, byte by byte.
+ * @len - pointer to the size of buffer
+ *
+ * On success stores the number of received bytes to len and returns 0. On
+ * errors (misformatted TPM data or synchronization problems) returns
+ * TPM_DRIVER_ERR.
+ */
+static u32 tis_readresponse(u8 *buffer, size_t *len)
+{
+	u16 burst_count;
+	u32 status;
+	u32 offset = 0;
+	u8 locality = 0;
+	const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+	u32 expected_count = *len;
+	int max_cycles = 0;
+
+	/* Wait for the TPM to process the command */
+	status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data);
+	if (status == TPM_TIMEOUT_ERR) {
+		printf("%s:%d failed processing command\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	do {
+		while ((burst_count = BURST_COUNT(status)) == 0) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d TPM stuck on read\n",
+				       __FILE__, __LINE__);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			status = tpm_read(locality, TIS_REG_STS);
+		}
+
+		max_cycles = 0;
+
+		while (burst_count-- && (offset < expected_count)) {
+			buffer[offset++] = (u8) tpm_read(locality,
+							 TIS_REG_DATA_FIFO);
+			if (offset == 6) {
+				/*
+				 * We got the first six bytes of the reply,
+				 * let's figure out how many bytes to expect
+				 * total - it is stored as a 4 byte number in
+				 * network order, starting with offset 2 into
+				 * the body of the reply.
+				 */
+				u32 real_length;
+				memcpy(&real_length,
+				       buffer + 2,
+				       sizeof(real_length));
+				expected_count = be32_to_cpu(real_length);
+
+				if ((expected_count < offset) ||
+				    (expected_count > *len)) {
+					printf("%s:%d bad response size %d\n",
+					       __FILE__, __LINE__,
+					       expected_count);
+					return TPM_DRIVER_ERR;
+				}
+			}
+		}
+
+		/* Wait for the next portion */
+		status = tis_wait_reg(TIS_REG_STS, locality,
+				      TIS_STS_VALID, TIS_STS_VALID);
+		if (status == TPM_TIMEOUT_ERR) {
+			printf("%s:%d failed to read response\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		if (offset == expected_count)
+			break;	/* We got all we need */
+
+	} while ((status & has_data) == has_data);
+
+	/*
+	 * Make sure we indeed read all there was. The TIS_STS_VALID bit is
+	 * known to be set.
+	 */
+	if (status & TIS_STS_DATA_AVAILABLE) {
+		printf("%s:%d wrong receive status %x\n",
+		       __FILE__, __LINE__, status);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* Tell the TPM that we are done. */
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	*len = offset;
+	return 0;
+}
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void)
+{
+	if (tis_probe())
+		return TPM_DRIVER_ERR;
+	return 0;
+}
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on failure.
+ */
+int tis_open(void)
+{
+	u8 locality = 0; /* we use locality zero for everything */
+
+	if (tis_close())
+		return TPM_DRIVER_ERR;
+
+	/* now request access to locality */
+	tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS);
+
+	/* did we get a lock? */
+	if (tis_wait_reg(TIS_REG_ACCESS, locality,
+			 TIS_ACCESS_ACTIVE_LOCALITY,
+			 TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to lock locality %d\n",
+		       __FILE__, __LINE__, locality);
+		return TPM_DRIVER_ERR;
+	}
+
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void)
+{
+	u8 locality = 0;
+	if (tpm_read(locality, TIS_REG_ACCESS) &
+	    TIS_ACCESS_ACTIVE_LOCALITY) {
+		tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS);
+
+		if (tis_wait_reg(TIS_REG_ACCESS, locality,
+				 TIS_ACCESS_ACTIVE_LOCALITY, 0) ==
+		    TPM_TIMEOUT_ERR) {
+			printf("%s:%d - failed to release locality %d\n",
+			       __FILE__, __LINE__, locality);
+			return TPM_DRIVER_ERR;
+		}
+	}
+	return 0;
+}
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or TPM_DRIVER_ERR on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size,
+		 uint8_t *recvbuf, size_t *recv_len)
+{
+	if (tis_senddata(sendbuf, send_size)) {
+		printf("%s:%d failed sending data to TPM\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	return tis_readresponse(recvbuf, recv_len);
+}
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
new file mode 100644
index 0000000..e0a8c9b
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <pc80/tpm.h>
+#include "chromeos.h"
+
+//#define EXTRA_LOGGING
+
+#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
+
+#define TPM_SUCCESS               ((u32)0x00000000)
+
+#define TPM_E_IOERROR             ((u32)0x0000001f)
+#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004)
+#define TPM_E_NON_FATAL           ((u32)0x00000800)
+#define TPM_E_INVALID_POSTINIT    ((u32)0x00000026)
+
+#define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
+#define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
+
+static const struct {
+	u8 buffer[12];
+} tpm_resume_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 }
+};
+
+static const struct {
+	u8 buffer[10];
+} tpm_continueselftest_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 }
+};
+
+static inline void FromTpmUint32(const u8 * buffer, u32 * x)
+{
+	*x = ((buffer[0] << 24) |
+	      (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]);
+}
+
+static inline int TpmCommandSize(const u8 * buffer)
+{
+	u32 size;
+	FromTpmUint32(buffer + sizeof(u16), &size);
+	return (int)size;
+}
+
+/* Gets the code field of a TPM command. */
+static inline int TpmCommandCode(const u8 * buffer)
+{
+	u32 code;
+	FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code);
+	return code;
+}
+
+/* Gets the return code field of a TPM result. */
+static inline int TpmReturnCode(const u8 * buffer)
+{
+	return TpmCommandCode(buffer);
+}
+
+/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or
+ * DOING_SELFTEST errors are returned.
+ */
+static u32 TlclSendReceiveNoRetry(const u8 * request,
+				  u8 * response, int max_length)
+{
+	size_t response_length = max_length;
+	u32 result;
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n",
+	       request[0], request[1],
+	       request[2], request[3], request[4], request[5],
+	       request[6], request[7], request[8], request[9]);
+#endif
+
+	result = TPM_SUCCESS;
+	if (tis_sendrecv
+	    (request, TpmCommandSize(request), response, &response_length))
+		result = TPM_E_IOERROR;
+
+	if (0 != result) {
+		/* Communication with TPM failed, so response is garbage */
+		printk(BIOS_DEBUG,
+		       "TPM: command 0x%x send/receive failed: 0x%x\n",
+		       TpmCommandCode(request), result);
+		return TPM_E_COMMUNICATION_ERROR;
+	}
+	/* Otherwise, use the result code from the response */
+	result = TpmReturnCode(response);
+
+/* TODO: add paranoia about returned response_length vs. max_length
+ * (and possibly expected length from the response header).  See
+ * crosbug.com/17017 */
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n",
+	       response[0], response[1],
+	       response[2], response[3], response[4], response[5],
+	       response[6], response[7], response[8], response[9]);
+#endif
+
+	printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n",
+	       TpmCommandCode(request), result);
+
+	return result;
+}
+
+static inline u32 TlclContinueSelfTest(void)
+{
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+	printk(BIOS_DEBUG, "TPM: Continue self test\n");
+	/* Call the No Retry version of SendReceive to avoid recursion. */
+	return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer,
+				      response, sizeof(response));
+}
+
+/* Sends a TPM command and gets a response.  Returns 0 if success or the TPM
+ * error code if error. In the firmware, waits for the self test to complete
+ * if needed. In the host, reports the first error without retries. */
+static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
+{
+	u32 result = TlclSendReceiveNoRetry(request, response, max_length);
+	/* When compiling for the firmware, hide command failures due to the self
+	 * test not having run or completed. */
+	/* If the command fails because the self test has not completed, try it
+	 * again after attempting to ensure that the self test has completed. */
+	if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) {
+		result = TlclContinueSelfTest();
+		if (result != TPM_SUCCESS) {
+			return result;
+		}
+#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE)
+		/* Retry only once */
+		result = TlclSendReceiveNoRetry(request, response, max_length);
+#else
+		/* This needs serious testing.  The TPM specification says:
+		 * "iii. The caller MUST wait for the actions of
+		 * TPM_ContinueSelfTest to complete before reissuing the
+		 * command C1."  But, if ContinueSelfTest is non-blocking, how
+		 * do we know that the actions have completed other than trying
+		 * again? */
+		do {
+			result =
+			    TlclSendReceiveNoRetry(request, response,
+						   max_length);
+		} while (result == TPM_E_DOING_SELFTEST);
+#endif
+	}
+
+	return result;
+}
+
+void init_vboot(void)
+{
+	u32 result;
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+
+	printk(BIOS_DEBUG, "TPM: Init\n");
+	if (tis_init())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Open\n");
+	if (tis_open())
+		return;
+
+	printk(BIOS_DEBUG, "TPM: Resume\n");
+
+	result =
+	    TlclSendReceive(tpm_resume_cmd.buffer, response, sizeof(response));
+
+	if (result == TPM_E_INVALID_POSTINIT) {
+		/* We're on a platform where the TPM maintains power in S3, so
+		 * it's already initialized. */
+		printk(BIOS_DEBUG, "TPM: Already initialized.\n");
+		return;
+	}
+	if (result == TPM_SUCCESS) {
+		printk(BIOS_DEBUG, "TPM: OK.\n");
+		return;
+	}
+	// TODO(reinauer) hard reboot?
+}



From gerrit at coreboot.org  Wed Mar  7 20:23:12 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:12 +0100
Subject: [coreboot] Patch set updated for coreboot: b7e70b3 selfboot: Allow
	loading SeaBIOS into a reserved region in the lower 1MB This
	fixes loading SeaBIOS when lower memory is reserved.
References: <Idbdcaf95f3307f97307f304d6d677406d059927d+0@gerrit.coreboot.org>
Message-ID: <Idbdcaf95f3307f97307f304d6d677406d059927d+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/732

-gerrit

commit b7e70b33f24510c3ec513def4ef210e2dbee6f5c
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 18 15:11:04 2011 -0700

    selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB
    This fixes loading SeaBIOS when lower memory is reserved.
    
    Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/boot/selfboot.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index fe56653..bbf160e 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -148,6 +148,11 @@ static int valid_area(struct lb_memory *mem, unsigned long buffer,
 		}
 	}
 	if (i == mem_entries) {
+		if (start < (1024*1024) && end <=(1024*1024)) {
+			printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded"
+				" into a reserved area in the lower 1MB\n");
+			return 1;
+		}
 		printk(BIOS_ERR, "No matching ram area found for range:\n");
 		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
 		printk(BIOS_ERR, "Ram areas\n");



From gerrit at coreboot.org  Wed Mar  7 20:23:13 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:13 +0100
Subject: [coreboot] Patch set updated for coreboot: b7fd05a Add timestamps
	for selfboot and acpi wake
References: <I28224867610b947739d940d25c98399d219f10f4+0@gerrit.coreboot.org>
Message-ID: <I28224867610b947739d940d25c98399d219f10f4+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/733

-gerrit

commit b7fd05a98d451fa9d98886025cc30cdcd8799551
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Oct 19 15:32:39 2011 -0700

    Add timestamps for selfboot and acpi wake
    
    Change-Id: I28224867610b947739d940d25c98399d219f10f4
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/arch/x86/boot/acpi.c |    7 +++++++
 src/boot/selfboot.c      |    7 +++++++
 src/include/timestamp.h  |    2 ++
 3 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index eb2e4e1..d4d554c 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -31,6 +31,9 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 #if CONFIG_CHROMEOS
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
@@ -611,6 +614,10 @@ void acpi_jump_to_wakeup(void *vector)
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
 }
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index bbf160e..d4ab8c8 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -29,6 +29,9 @@
 #include <string.h>
 #include <cbfs.h>
 #include <lib.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 
 /* Maximum physical address we can use for the coreboot bounce buffer. */
 #ifndef MAX_ADDR
@@ -529,6 +532,10 @@ static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
 	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(POST_ENTER_ELF_BOOT);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_SELFBOOT_JUMP);
+#endif
+
 	/* Jump to kernel */
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
index cfa06e2..8b9a89a 100644
--- a/src/include/timestamp.h
+++ b/src/include/timestamp.h
@@ -37,6 +37,8 @@ struct timestamp_table {
 enum timestamp_id {
 	TS_BEFORE_INITRAM = 1,
 	TS_AFTER_INITRAM = 2,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
 };
 
 void timestamp_init(tsc_t base);



From gerrit at coreboot.org  Wed Mar  7 20:23:13 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:13 +0100
Subject: [coreboot] Patch set updated for coreboot: df4b21e tell superiotool
	about the ITE 8772
References: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+0@gerrit.coreboot.org>
Message-ID: <I4e687ca816c8d6d1c95255b0abf6a19513e23f86+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/734

-gerrit

commit df4b21edd01fae57bcb8ee5026693e8198100bb9
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 25 17:12:53 2011 +0000

    tell superiotool about the ITE 8772
    
    no dumping yet
    
    Change-Id: I4e687ca816c8d6d1c95255b0abf6a19513e23f86
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 util/superiotool/ite.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index c83d788..e186e10 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -708,6 +708,8 @@ static const struct superio_registers reg_table[] = {
 		{EOT}}},
 	{0x8761, "IT8761E", {
 		{EOT}}},
+	{0x8772, "IT8772F", {
+		{EOT}}},
 	{0x8780, "IT8780F", {
 		{EOT}}},
 	{EOT}



From gerrit at coreboot.org  Wed Mar  7 20:23:15 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:15 +0100
Subject: [coreboot] Patch set updated for coreboot: 7861a33 Add support for
	enabling PCIe Common Clock and ASPM
References: <I3fe46282eada67629e9eeeed07e487dff54f2729+0@gerrit.coreboot.org>
Message-ID: <I3fe46282eada67629e9eeeed07e487dff54f2729+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/735

-gerrit

commit 7861a33f83e654439c3ba4e3c4191534264e28fc
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Oct 25 14:15:11 2011 -0700

    Add support for enabling PCIe Common Clock and ASPM
    
    These are guarded by individual Kconfig entries. The deprecated
    CONFIG_PCIE_TUNING defines have been removed in favor of using specific
    config options.
    
    This is the generic half, there is board-specific pieces
    still to come that tune before and after ASPM is enabled.
    
    Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/devices/Kconfig          |   14 +++
 src/devices/pciexp_device.c  |  188 +++++++++++++++++++++++++++++++++++++++---
 src/include/device/pci_def.h |    7 ++
 src/include/device/pciexp.h  |    7 ++
 4 files changed, 205 insertions(+), 11 deletions(-)

diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 98e8d9f..7429bda 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -163,3 +163,17 @@ config AGP_PLUGIN_SUPPORT
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	default y
+
+config PCIEXP_COMMON_CLOCK
+	prompt "Enable PCIe Common Clock"
+	bool
+	default n
+	help
+	  Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+	prompt "Enable PCIe ASPM"
+	bool
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 5d33942..36f3e6a 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -19,31 +19,197 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
+#if CONFIG_PCIEXP_COMMON_CLOCK
+/*
+ * Re-train a PCIe link
+ */
+#define PCIE_TRAIN_RETRY 10000
+static int pciexp_retrain_link(device_t dev, unsigned cap)
+{
+	unsigned try = PCIE_TRAIN_RETRY;
+	u16 lnk;
+
+	/* Start link retraining */
+	lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
+	lnk |= PCI_EXP_LNKCTL_RL;
+	pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
+
+	/* Wait for training to complete */
+	while (try--) {
+		lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+		if (!(lnk & PCI_EXP_LNKSTA_LT))
+			return 0;
+		udelay(100);
+	}
+
+	printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+	return -1;
+}
+
+/*
+ * Check the Slot Clock Configuration for root port and endpoint
+ * and enable Common Clock Configuration if possible.  If CCC is
+ * enabled the link must be retrained.
+ */
+static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
+				       device_t endp, unsigned endp_cap)
+{
+	u16 root_scc, endp_scc, lnkctl;
+
+	/* Get Slot Clock Configuration for root port */
+	root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
+	root_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Get Slot Clock Configuration for endpoint */
+	endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
+	endp_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Enable Common Clock Configuration and retrain */
+	if (root_scc && endp_scc) {
+		printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
+
+		/* Set in endpoint */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set in root port */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Retrain link if CCC was enabled */
+		pciexp_retrain_link(root, root_cap);
+	}
+}
+#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
+
+#if CONFIG_PCIEXP_ASPM
+/*
+ * Determine the ASPM L0s or L1 exit latency for a link
+ * by checking both root port and endpoint and returning
+ * the highest latency value.
+ */
+static int pciexp_aspm_latency(device_t root, unsigned root_cap,
+			       device_t endp, unsigned endp_cap,
+			       enum aspm_type type)
+{
+	int root_lat = 0, endp_lat = 0;
+	u32 root_lnkcap, endp_lnkcap;
+
+	root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+	endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
+
+	/* Make sure the link supports this ASPM type by checking
+	 * capability bits 11:10 with aspm_type offset by 1 */
+	if (!(root_lnkcap & (1 << (type + 9))) ||
+	    !(endp_lnkcap & (1 << (type + 9))))
+		return -1;
+
+	/* Find the one with higher latency */
+	switch (type) {
+	case PCIE_ASPM_L0S:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		break;
+	case PCIE_ASPM_L1:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		break;
+	default:
+		return -1;
+	}
+
+	return (endp_lat > root_lat) ? endp_lat : root_lat;
+}
+
+/*
+ * Enable ASPM on PCIe root port and endpoint.
+ *
+ * Returns APMC value:
+ *   -1 = Error
+ *    0 = no ASPM
+ *    1 = L0s Enabled
+ *    2 = L1 Enabled
+ *    3 = L0s and L1 Enabled
+ */
+static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
+					 device_t endp, unsigned endp_cap)
+{
+	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	int exit_latency, ok_latency;
+	u16 lnkctl;
+	u32 devcap;
+
+	/* Get endpoint device capabilities for acceptable limits */
+	devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
+
+	/* Enable L0s if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L0S);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L0S;
+
+	/* Enable L1 if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L1);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L1;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set APMC in root port first */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set APMC in endpoint device next */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+	}
+
+	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
+	return apmc;
+}
+#endif /* CONFIG_PCIEXP_ASPM */
+
 static void pciexp_tune_dev(device_t dev)
 {
-	unsigned int cap;
-#if CONFIG_PCIE_TUNING
-	u32 reg32;
-#endif
+	device_t root = dev->bus->dev;
+	unsigned int root_cap, cap;
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
 		return;
 
-#if CONFIG_PCIE_TUNING
-	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
+	root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+	if (!root_cap)
+		return;
+
+#if CONFIG_PCIEXP_COMMON_CLOCK
+	/* Check for and enable Common Clock */
+	pciexp_enable_common_clock(root, root_cap, dev, cap);
+#endif
 
-	// TODO make this depending on ASPM.
+#if CONFIG_PCIEXP_ASPM
+	/* Check for and enable ASPM */
+	enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
 
-	/* Enable ASPM role based error reporting. */
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Enable ASPM role based error reporting. */
+		u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+		reg32 |= PCI_EXP_DEVCAP_RBER;
+		pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	}
 #endif
 }
 
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1..58a7321 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
 #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
+#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
+#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
 #define PCI_EXP_SLTCTL		24	/* Slot Control */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211..87a5002 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
 #define DEVICE_PCIEXP_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+enum aspm_type {
+	PCIE_ASPM_NONE = 0,
+	PCIE_ASPM_L0S  = 1,
+	PCIE_ASPM_L1   = 2,
+	PCIE_ASPM_BOTH = 3,
+};
+
 unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn, unsigned int max);
 unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);



From gerrit at coreboot.org  Wed Mar  7 20:23:16 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:16 +0100
Subject: [coreboot] Patch set updated for coreboot: 1017143 CBMEM CONSOLE:
	Add CBMEM type for console buffer.
References: <I02757c06d71e46af77b02b90b0e6018a37b62406+0@gerrit.coreboot.org>
Message-ID: <I02757c06d71e46af77b02b90b0e6018a37b62406+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/720

-gerrit

commit 1017143d7c8c2b58c11027279f7d0b9b62dbc55f
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:13:06 2011 -0700

    CBMEM CONSOLE: Add CBMEM type for console buffer.
    
    Add CBMEM type for the console buffer section.
    
    Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    1 +
 src/lib/cbmem.c     |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index c3f10ef..a19ec5a 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -42,6 +42,7 @@ extern uint64_t high_tables_base, high_tables_size;
 #define CBMEM_ID_RESUME		0x5245534d
 #define CBMEM_ID_SMBIOS         0x534d4254
 #define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_CONSOLE	0x434f4e53
 #define CBMEM_ID_NONE		0x00000000
 
 int cbmem_initialize(void);
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index f800b04..b09b070 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -256,6 +256,7 @@ void cbmem_list(void)
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
 		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
 		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
+		case CBMEM_ID_CONSOLE:   printk(BIOS_DEBUG, "CONSOLE    "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);



From gerrit at coreboot.org  Wed Mar  7 20:23:18 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:18 +0100
Subject: [coreboot] Patch set updated for coreboot: 91462b5 CBMEM CONSOLE:
	Add code using the new console driver.
References: <Ifd1f492ce6321412a014333babbc5b3f14635988+0@gerrit.coreboot.org>
Message-ID: <Ifd1f492ce6321412a014333babbc5b3f14635988+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/721

-gerrit

commit 91462b57c5a5a6e8475241d028d58b4a84970ec8
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 11:16:49 2011 -0700

    CBMEM CONSOLE: Add code using the new console driver.
    
    The new added code is compiled in when the CBMEM_CONSOLE config
    flag is enabled.
    
    Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/lib/romcc_console.c    |    3 +++
 src/arch/x86/lib/romstage_console.c |    3 +++
 src/boot/hardwaremain.c             |    3 +++
 src/console/console.c               |    5 ++++-
 4 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 13ee1f0..0e1f4e6 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -46,6 +46,9 @@ static void __console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void __console_tx_nibble(unsigned nibble)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 8adb3ba..0f22727 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -46,6 +46,9 @@ static void console_tx_byte(unsigned char byte)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void console_tx_flush(void)
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 3d15b55..9b293c0 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -92,6 +92,9 @@ void hardwaremain(int boot_complete)
 
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
diff --git a/src/console/console.c b/src/console/console.c
index d933668..8f60f04 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -87,7 +87,7 @@ int console_tst_byte(void)
 	return 0;
 }
 
-#else
+#else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
 void console_init(void)
 {
@@ -104,6 +104,9 @@ void console_init(void)
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_init();
+#endif
 	static const char console_test[] =
 		"\n\ncoreboot-"
 		COREBOOT_VERSION



From gerrit at coreboot.org  Wed Mar  7 20:23:20 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:20 +0100
Subject: [coreboot] Patch set updated for coreboot: be71426 CBMEM CONSOLE:
	Enable coreboot CBMEM console.
References: <I91842b1ba0f89d611d3249b63c020a2713a9124f+0@gerrit.coreboot.org>
Message-ID: <I91842b1ba0f89d611d3249b63c020a2713a9124f+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/722

-gerrit

commit be714260ace953f3f5f438a14054030ddb8a0c2e
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 12:02:18 2011 -0700

    CBMEM CONSOLE: Enable coreboot CBMEM console.
    
    The appropriate Makefiles are modified to include the required
    source code in compilation.
    
    Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/console/Makefile.inc |    2 ++
 src/lib/Makefile.inc     |    2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..f3b8758 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -18,6 +18,8 @@ driver-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
+driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
 $(obj)/console/console.romstage.o : $(obj)/build.h
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index db640dc..45cb788 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -11,6 +11,7 @@ romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
@@ -34,6 +35,7 @@ ramstage-y += clog2.c
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
 ramstage-$(CONFIG_TRACE) += trace.c



From gerrit at coreboot.org  Wed Mar  7 20:23:25 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:25 +0100
Subject: [coreboot] Patch set updated for coreboot: 149337f Introduce
	utility for parsing CBMEM contents.
References: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+0@gerrit.coreboot.org>
Message-ID: <Id863a8598eaadc2d20d728f9186843e65cbe6f37+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/723

-gerrit

commit 149337fe6571b33b248f05bd72a21e4c7f715e49
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Fri Sep 30 14:21:03 2011 -0700

    Introduce utility for parsing CBMEM contents.
    
    This is a python script which is supposed to run on a target
    which is controlled by coreboot. The script examines top of
    memory looking for the CBMEM signature at addresses aligned at
    128K boundary. Once the script finds the CBMEM, it iterates
    through the CBMEM table of contents and parses two entries: the
    timestamps and the console log.
    
    This submission is just a template to build upon to create a
    utility for displaying CBMEM information while running Linux on
    the target.
    
    BUG=chrome-os-partner:4200
    TEST=manual
    
    See test description of d81e6b8c8d41f2d6 for test procedure.
    
    Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
    Reviewed-on: https://gerrit-int.chromium.org/5942
    Tested-by: Vadim Bendebury <vbendeb at google.com>
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 util/cbmem/cbmem.py |  204 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 204 insertions(+), 0 deletions(-)

diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
new file mode 100755
index 0000000..3e8476d
--- /dev/null
+++ b/util/cbmem/cbmem.py
@@ -0,0 +1,204 @@
+#!/usr/bin/python
+#
+# cbmem.py - Linux space CBMEM contents parser
+#
+# Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+'''
+Parse and display CBMEM contents.
+
+This module is meant to run on systems with coreboot based firmware.
+
+When started, it determines the amount of DRAM installed on the system, and
+then scans the top area of DRAM (right above the available memory size)
+looking for the CBMEM base signature at locations aligned at 0x20000
+boundaries.
+
+Once it finds the CBMEM signature, the utility parses the contents, reporting
+the section IDs/sizes and also reporting the contents of the tiemstamp and
+console sections.
+'''
+
+import mmap
+import re
+import struct
+import sys
+import time
+
+# These definitions follow src/include/cbmem.h
+CBMEM_MAGIC = 0x434f5245
+CBMEM_MAX_ENTRIES = 16
+
+CBMEM_ENTRY_FORMAT = '@LLQQ'
+CONSOLE_HEADER_FORMAT = '@LL'
+TIMESTAMP_HEADER_FORMAT = '@QLL'
+TIMESTAMP_ENTRY_FORMAT = '@LQ'
+
+mf_fileno = 0  # File number of the file providing access to memory.
+
+def align_up(base, alignment):
+    '''Increment to the alignment boundary.
+
+    Return the next integer larger than 'base' and divisible by 'alignment'.
+    '''
+
+    return base + alignment - base % alignment
+
+def normalize_timer(value, freq):
+    '''Convert timer reading into microseconds.
+
+    Get the free running clock counter value, divide it by the clock frequency
+    and multiply by 1 million to get reading in microseconds.
+
+    Then convert the value into an ASCII string with groups of three digits
+    separated by commas.
+
+    Inputs:
+      value: int, the clock reading
+      freq: float, the clock frequency
+
+    Returns:
+      A string presenting 'value' in microseconds.
+    '''
+
+    result = []
+    value = int(value * 1000000.0 / freq)
+    svalue = '%d' % value
+    vlength = len(svalue)
+    remainder = vlength % 3
+    if remainder:
+        result.append(svalue[0:remainder])
+    while remainder < vlength:
+        result.append(svalue[remainder:remainder+3])
+        remainder = remainder + 3
+    return ','.join(result)
+
+def get_cpu_freq():
+    '''Retrieve CPU frequency from sysfs.
+
+    Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source.
+    '''
+    freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq'
+                    ).read()
+    # Convert reading into Hertz
+    return float(freq_str) * 1000.0
+
+def get_mem_size():
+    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
+    mult = {
+        'kB': 1024
+        }
+    meminfo = open('/proc/meminfo').read()
+    m = re.search('MemTotal:.*\n', meminfo)
+    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
+    (_, size, mult_name) = mem_string.split()
+    return int(size) * mult[mult_name]
+
+def parse_mem_at(addr, format):
+    '''Read and parse a memory location.
+
+    This function reads memory at the passed in address, parses it according
+    to the passed in format specification and returns a list of values.
+
+    The first value in the list is the size of data matching the format
+    expression, and the rest of the elements of the list are the actual values
+    retrieved using the format.
+    '''
+
+    size = struct.calcsize(format)
+    delta = addr % 4096   # mmap requires the offset to be page size aligned.
+    mm = mmap.mmap(mf_fileno, size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mm.close()
+    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
+    return rv
+
+def dprint(text):
+    '''Debug print function.
+
+    Edit it to get the debug output.
+    '''
+
+    if False:
+        print text
+
+def process_timers(base):
+    '''Scan the array of timestamps found in CBMEM at address base.
+
+    For each timestamp print the timer ID and the value in microseconds.
+    '''
+
+    (step, base_time, max_entr, entr) = parse_mem_at(
+        base, TIMESTAMP_HEADER_FORMAT)
+
+    print('\ntime base %d, total entries %d' % (base_time, entr))
+    clock_freq = get_cpu_freq()
+    base = base + step
+    for i in range(entr):
+        (step, timer_id, timer_value) = parse_mem_at(
+            base, TIMESTAMP_ENTRY_FORMAT)
+        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
+        base = base + step
+    print
+
+def process_console(base):
+    '''Dump the console log buffer contents found at address base.'''
+
+    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
+    print 'cursor at %d\n' % cursor
+
+    cons_string_format = '%ds' % min(cursor, size)
+    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    print cons_text
+    print '\n'
+
+mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
+table_alignment = 128 * 1024
+
+mem_size = get_mem_size()
+
+# start at memory address aligned at 128K.
+offset = align_up(mem_size, table_alignment)
+
+dprint('mem_size %x offset %x' %(mem_size, offset))
+mf = open("/dev/mem")
+mf_fileno = mf.fileno()
+
+while offset % mem_alignment: # do not cross the 1G boundary while searching
+    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if magic == CBMEM_MAGIC:
+        offset = offset + step
+        break
+    offset += table_alignment
+else:
+    print 'Did not find the CBMEM'
+    sys.exit(0)
+
+for i in (range(1, CBMEM_MAX_ENTRIES)):
+    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if mid == 0:
+        break
+
+    print '%x, %x, %x' % (mid, base, size)
+    if mid == 0x54494d45:
+        process_timers(base)
+    if mid == 0x434f4e53:
+        process_console(base)
+
+    offset = offset + step
+
+mf.close()



From gerrit at coreboot.org  Wed Mar  7 20:23:26 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:26 +0100
Subject: [coreboot] Patch set updated for coreboot: 2b91139 Refactor
	publishing CBMEM addresses through coreboot table.
References: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+0@gerrit.coreboot.org>
Message-ID: <I63adb67093b8b50ee61b0deb0b56ebb2c4856895+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/724

-gerrit

commit 2b91139bc6554adf37436bbe9cb3526aca3af587
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Mon Oct 3 14:58:57 2011 -0700

    Refactor publishing CBMEM addresses through coreboot table.
    
    We need to provide u-boot access to several different CBMEM
    sections. To do that, a common coreboot table structure is used,
    just different tags match different coreboot table sections.
    
    Also, the code is added to export CBMEM console and MRC cache
    addresses through the same mechanism.
    
    Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/arch/x86/boot/coreboot_table.c |   59 +++++++++++++++++++++++++++++-------
 src/include/boot/coreboot_tables.h |    6 ++-
 2 files changed, 52 insertions(+), 13 deletions(-)

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index f189e76..f29481b 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -175,22 +175,40 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
-#if CONFIG_COLLECT_TIMESTAMPS
-static void lb_tsamp(struct lb_header *header)
+static void add_cbmem_pointers(struct lb_header *header)
 {
-	struct lb_tstamp *tstamp;
-	void *tstamp_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+	/*
+	 * These CBMEM sections' addresses are included in the coreboot table
+	 * with the appropriate tags.
+	 */
+	const struct section_id {
+		int cbmem_id;
+		int table_tag;
+	} section_ids[] = {
+		{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+		{CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE},
+		{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+	};
+	int i;
 
-	if (!tstamp_table)
-		return;
+	for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+		const struct section_id *sid = section_ids + i;
+		struct lb_cbmem_ref *cbmem_ref;
+		void *cbmem_addr = cbmem_find(sid->cbmem_id);
 
-	tstamp = (struct lb_tstamp *)lb_new_record(header);
-	tstamp->tag = LB_TAG_TIMESTAMPS;
-	tstamp->size = sizeof(*tstamp);
-	tstamp->tstamp_tab = tstamp_table;
+		if (!cbmem_addr)
+			continue;  /* This section is not present */
 
+		cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+		if (!cbmem_ref) {
+			printk(BIOS_ERR, "No more room in coreboot table!\n");
+			break;
+		}
+		cbmem_ref->tag = sid->table_tag;
+		cbmem_ref->size = sizeof(*cbmem_ref);
+		cbmem_ref->cbmem_addr = cbmem_addr;
+	}
 }
-#endif
 
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
@@ -633,9 +651,28 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+<<<<<<< HEAD
 #if CONFIG_COLLECT_TIMESTAMPS
 	lb_tsamp(head);
 #endif
+=======
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+#endif
+#if CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head, serial);
+#endif
+	add_cbmem_pointers(head);
+
+>>>>>>> 3fc47a1... Refactor publishing CBMEM addresses through coreboot table.
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 46d6489..5535a38 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -196,11 +196,13 @@ struct lb_framebuffer {
 };
 
 #define LB_TAG_TIMESTAMPS	0x0016
-struct lb_tstamp {
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+struct lb_cbmem_ref {
 	uint32_t tag;
 	uint32_t size;
 
-	void	*tstamp_tab;
+	void	*cbmem_addr;
 };
 
 /* The following structures are for the cmos definitions table */



From gerrit at coreboot.org  Wed Mar  7 20:23:27 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:27 +0100
Subject: [coreboot] Patch set updated for coreboot: 3f5e2ae Increase CBMEM
	to accommodate larger console.
References: <If583013dfb210de5028d69577675095c6fe2f3ab+0@gerrit.coreboot.org>
Message-ID: <If583013dfb210de5028d69577675095c6fe2f3ab+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/725

-gerrit

commit 3f5e2ae69ac3c76349d7d65e5d4d380b1ecfb1d2
Author: Vadim Bendebury <vbendeb at chromium.org>
Date:   Tue Oct 4 10:44:16 2011 -0700

    Increase CBMEM to accommodate larger console.
    
    This change adds 128K to the memory amount set aside for CBMEM in
    case the CBMEM console is enabled (to keep the CBMEM 128K byte
    aligned). The console buffer size is being set to 64K, which is
    enough to accommodate the most verbose coreboot console and
    u-boot console.
    
    Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
    Signed-off-by: Vadim Bendebury <vbendeb at chromium.org>
---
 src/include/cbmem.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a19ec5a..6a48dd2 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -21,7 +21,12 @@
 #define _CBMEM_H_
 
 /* Reserve 128k for ACPI and other tables */
+#if CONFIG_CONSOLE_CBMEM
+#define HIGH_MEMORY_DEF_SIZE	( 256 * 1024 )
+#else
 #define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#endif
+
 #ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
 #endif



From gerrit at coreboot.org  Wed Mar  7 20:23:31 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:31 +0100
Subject: [coreboot] Patch set updated for coreboot: 9f8dda7 Fix typos in
	src/console/Kconfig
References: <Ia906077257e93622ad56bc54a42f8184ade78b29+0@gerrit.coreboot.org>
Message-ID: <Ia906077257e93622ad56bc54a42f8184ade78b29+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/726

-gerrit

commit 9f8dda7328a023fb7ad0bb2960db589714c69ff2
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Oct 4 16:21:17 2011 -0700

    Fix typos in src/console/Kconfig
    
    - cash -> Cache
    - make the new size of the cbmem console buffer the default
    
    Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
 src/console/Kconfig |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/console/Kconfig b/src/console/Kconfig
index fefbe2e..2cfc4db 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -201,7 +201,7 @@ config CONSOLE_CBMEM
 config CONSOLE_CBMEM_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
 	hex "Room allocated for console output in CBMEM"
-	default 0xae00
+	default 0x10000
 	help
 	  Space allocated for console output storage in CBMEM. The default
 	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
@@ -209,7 +209,7 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 
 config CONSOLE_CAR_BUFFER_SIZE
 	depends on CONSOLE_CBMEM
-	hex "Room allocated for console output in cash as RAM"
+	hex "Room allocated for console output in Cache as RAM"
 	default 0xc00
 	help
 	  Console is used before RAM is initialized. This is the room reserved



From gerrit at coreboot.org  Wed Mar  7 20:23:32 2012
From: gerrit at coreboot.org (Stefan Reinauer (stefan.reinauer@coreboot.org))
Date: Wed, 7 Mar 2012 20:23:32 +0100
Subject: [coreboot] Patch set updated for coreboot: 27f1d38 Add
	infrastructure for global data in the CAR phase of boot.
References: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+0@gerrit.coreboot.org>
Message-ID: <Iccfb99b128d59c5b7d6164796d21ba46d2a674e0+3@gerrit.coreboot.org>

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/727

-gerrit

commit 27f1d389c5d3e80e402ff637a48f4f7f6a156998
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Oct 1 04:27:32 2011 -0700

    Add infrastructure for global data in the CAR phase of boot.
    
    The cbmem console structure and car global data are put in their own section,
    with the cbmem console coming after the global data. These areas are linked
    to be where CAR is available and at the very bottom of the stack.
    
    There is one shortcoming of this change:
    The section created by this change needs to be stripped out by the Makefile
    since leaving it in confuses cbfstool when it installs the stage in the image.
    I would like to make the tools link those symbols at the right location but
    leave allocation of that space out of the ELF.
    
    Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
    Signed-off-by: Gabe Black <gabeblack at google.com>
---
 src/arch/x86/Makefile.inc      |    2 +-
 src/arch/x86/init/bootblock.ld |    7 +++++++
 src/include/cpu/x86/car.h      |   31 +++++++++++++++++++++++++++++++
 src/lib/cbmem_console.c        |    7 +++++--
 4 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 624b510..aeb4875 100755
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -272,7 +272,7 @@ $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	rm -f $@
 	cp $(obj)/coreboot.pre1 $@
 	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf \
-            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	    $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index bde0430..6f8ade8 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -51,5 +51,12 @@ SECTIONS
 		*(.eh_frame);
 	}
 
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h
new file mode 100644
index 0000000..2d2af03
--- /dev/null
+++ b/src/include/cpu/x86/car.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef CPU_X86_CAR_H
+#define CPU_X86_CAR_H
+
+#ifdef __PRE_RAM__
+#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\", at nobits#")))
+#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\", at nobits#")))
+#else
+#define CAR_GLOBAL
+#define CAR_CBMEM
+#endif
+
+#endif
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
index b58de48..431ea1f 100644
--- a/src/lib/cbmem_console.c
+++ b/src/lib/cbmem_console.c
@@ -19,6 +19,7 @@
 
 #include <console/console.h>
 #include <cbmem.h>
+#include <cpu/x86/car.h>
 #include <string.h>
 
 /*
@@ -39,7 +40,9 @@ struct cbmem_console {
  * ram space is used for the console buffer storage. The size and location of
  * the area are defined in the config.
  */
-#define cbmem_console_p ((struct cbmem_console *)CONFIG_DCACHE_RAM_BASE)
+
+static struct cbmem_console car_cbmem_console CAR_CBMEM;
+#define cbmem_console_p (&car_cbmem_console)
 
 /*
  * Once DRAM is initialized and the cache as ram mode is disabled, while still
@@ -92,7 +95,7 @@ void cbmemc_tx_byte(unsigned char data)
 	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
 	 * actual console buffer is.
 	 */
-	if ((u32)&cursor < (u32)CONFIG_DCACHE_RAM_BASE)
+	if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console)
 		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
 #endif
 	if (!cbm_cons_p)



From christian.suehs at online.de  Wed Mar  7 20:57:11 2012
From: christian.suehs at online.de (Christian)
Date: Wed, 07 Mar 2012 20:57:11 +0100
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <20120306004733.7814.qmail@stuge.se>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
	<20120306004733.7814.qmail@stuge.se>
Message-ID: <1331150231.2467.6.camel@dance-or-die3.athome.de>


> What CPU do you have? Is CN700 usable exclusively with C7? What

Yes it is a Via C7

vendor_id	:	CentaurHauls
cpu family	:	6
model	:	13
model name	:	VIA Eden Processor 600MHz
stepping	:	0

> generation C7 do you have? Does VIA have updated setup code for
> your model CPU?

I don`t know

> > qemu: fatal: Trying to execute code outside RAM or ROM at 0x000a0000
> > 
> > EAX=00000004 EBX=00000000 ECX=00000000 EDX=00000001
> > ESI=00000000 EDI=00000000 EBP=ffef7fe8 ESP=ffef7fb8
> > EIP=0009ff66
> 
> So code at 9ff66 is trying to jump to a0000. This is all sorts of
> wrong. Start by looking at what is going on at 9ff66. Obviously make
> sure that your toolchain is working. I believe VIA startup has some
> assembly. Verify that your disassembled binaries have 1:1 of the
> source. All basic bringup.

I will check this.

> > There are hints for Rev. 3566 code for the southbridge? Is this
> > important.
> 
> A more precise reference to the code you have in mind would allow
> more efficient collaboration.
> 

In the Wiki
Status for BCOM/Winnetp680 and
Status for Jetway/J7F2

> 
> Thanks.
> 
> //Peter
> 





From christian.suehs at online.de  Wed Mar  7 21:54:37 2012
From: christian.suehs at online.de (Christian)
Date: Wed, 07 Mar 2012 21:54:37 +0100
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <1331150231.2467.6.camel@dance-or-die3.athome.de>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
	<20120306004733.7814.qmail@stuge.se>
	<1331150231.2467.6.camel@dance-or-die3.athome.de>
Message-ID: <1331153677.2467.13.camel@dance-or-die3.athome.de>


> > > EAX=00000004 EBX=00000000 ECX=00000000 EDX=00000001
> > > ESI=00000000 EDI=00000000 EBP=ffef7fe8 ESP=ffef7fb8
> > > EIP=0009ff66
> > 
> > So code at 9ff66 is trying to jump to a0000. This is all sorts of
> > wrong. Start by looking at what is going on at 9ff66. Obviously make
> > sure that your toolchain is working. I believe VIA startup has some
> > assembly. Verify that your disassembled binaries have 1:1 of the
> > source. All basic bringup.
> 
> I will check this.

It could be something wrong in

src/cpu/via/car/cache_as_ram.inc

Here are my bases and sizes, always default

CONFIG_DCACHE_RAM_BASE=0xffef0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_XIP_ROM_SIZE=0x100000
CONFIG_XIP_ROM_BASE=0xfff00000
CONFIG_RAMTOP=0x200000
CONFIG_RAMBASE=0x100000

In this file are many calculations, but my assembler lessons are ten
years ago :)

thanks chris




From kyosti.malkki at gmail.com  Wed Mar  7 22:19:01 2012
From: kyosti.malkki at gmail.com (=?ISO-8859-1?Q?Ky=F6sti_M=E4lkki?=)
Date: Wed, 07 Mar 2012 23:19:01 +0200
Subject: [coreboot] VIA CN700 / VT8237R support in V4 broken?
In-Reply-To: <1331153677.2467.13.camel@dance-or-die3.athome.de>
References: <1330887701.6905.17.camel@dance-or-die3.athome.de>
	<20120306004733.7814.qmail@stuge.se>
	<1331150231.2467.6.camel@dance-or-die3.athome.de>
	<1331153677.2467.13.camel@dance-or-die3.athome.de>
Message-ID: <1331155141.19415.69.camel@obelix>

On Wed, 2012-03-07 at 21:54 +0100, Christian wrote:
> Here are my bases and sizes, always default
> 
> CONFIG_DCACHE_RAM_BASE=0xffef0000
> CONFIG_DCACHE_RAM_SIZE=0x8000
> CONFIG_XIP_ROM_SIZE=0x100000
> CONFIG_XIP_ROM_BASE=0xfff00000
> CONFIG_RAMTOP=0x200000
> CONFIG_RAMBASE=0x100000
> 

XIP_ROM_SIZE should be 64k and _BASE is obsolete.

I think AMD Agesa leaks it's Kconfig, try with the attached patch.

KM

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From gerrit at coreboot.org  Thu Mar  8 00:08:26 2012
From: gerrit at coreboot.org (Kyösti Mälkki (kyosti.malkki@gmail.com))
Date: Thu, 8 Mar 2012 00:08:26 +0100
Subject: [coreboot] New patch to review for coreboot: 55312ae Fix AMD Agesa
	leaking Kconfig
References: <Ic7891012220e1bef758a5a39002b66971d5206e3+0@gerrit.coreboot.org>
Message-ID: <Ic7891012220e1bef758a5a39002b66971d5206e3+1@gerrit.coreboot.org>

Ky?sti M?lkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/773

-gerrit

commit 55312ae0554da57c7becaef099ef240b4904ee5b
Author: Ky?sti M?lkki <kyosti.malkki at gmail.com>
Date:   Wed Mar 7 23:21:35 2012 +0200

    Fix AMD Agesa leaking Kconfig
    
    Kconfig leaked XIP_ROM_SIZE to other platforms and also
    defined obsolete option XIP_ROM_BASE.
    
    Rename AMD_AGESA to CPU_AMD_AGESA.
    Also alias CPU_AMD_AGESA as NORTHBRIDGE_AMD_AGESA.
    
    Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3
    Signed-off-by: Ky?sti M?lkki <kyosti.malkki at gmail.com>
---
 src/arch/x86/init/bootblock.ld              |    2 +-
 src/cpu/amd/Makefile.inc                    |    2 +-
 src/cpu/amd/agesa/Kconfig                   |   10 ++++++----
 src/cpu/amd/agesa/family15/Kconfig          |    5 -----
 src/mainboard/advansus/a785e-i/Makefile.inc |    2 +-
 src/mainboard/amd/inagua/Kconfig            |    5 +----
 src/mainboard/amd/persimmon/Kconfig         |    5 +----
 src/mainboard/amd/south_station/Kconfig     |    5 +----
 src/mainboard/amd/torpedo/Kconfig           |    5 +----
 src/mainboard/amd/union_station/Kconfig     |    5 +----
 src/mainboard/asrock/e350m1/Kconfig         |    5 +----
 src/mainboard/asus/m5a88-v/Makefile.inc     |    2 +-
 src/mainboard/avalue/eax-785e/Makefile.inc  |    2 +-
 src/northbridge/amd/Makefile.inc            |    2 +-
 src/northbridge/amd/agesa/Kconfig           |    7 +++++++
 15 files changed, 25 insertions(+), 39 deletions(-)

diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index bde0430..fd4d3db 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -51,5 +51,5 @@ SECTIONS
 		*(.eh_frame);
 	}
 
-	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
+	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc
index 2ea376a..6663d14 100644
--- a/src/cpu/amd/Makefile.inc
+++ b/src/cpu/amd/Makefile.inc
@@ -14,4 +14,4 @@ subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
 subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
 subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1
 
-subdirs-$(CONFIG_AMD_AGESA) += agesa
+subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 631724b..214aca3 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -17,13 +17,12 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-config AMD_AGESA
+config CPU_AMD_AGESA
         bool
+        default y if CPU_AMD_AGESA_FAMILY15
         default n
 
-config XIP_ROM_BASE
-	hex
-	default 0xfff00000
+if CPU_AMD_AGESA
 
 config XIP_ROM_SIZE
 	hex
@@ -40,3 +39,6 @@ source src/cpu/amd/agesa/family10/Kconfig
 source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig
 source src/cpu/amd/agesa/family15/Kconfig
+
+endif # CPU_AMD_AGESA
+
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
index 0f2f920..c1528f6 100644
--- a/src/cpu/amd/agesa/family15/Kconfig
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -20,7 +20,6 @@
 config CPU_AMD_AGESA_FAMILY15
 	bool
 	select PCI_IO_CFG_EXT
-	select AMD_AGESA
 
 if CPU_AMD_AGESA_FAMILY15
 
@@ -58,10 +57,6 @@ config CDB
 	hex
 	default 0x18
 
-config XIP_ROM_BASE
-	hex
-	default 0xfff80000
-
 config XIP_ROM_SIZE
 	hex
 	default 0x80000
diff --git a/src/mainboard/advansus/a785e-i/Makefile.inc b/src/mainboard/advansus/a785e-i/Makefile.inc
index 737bb1c..d69a9bf 100755
--- a/src/mainboard/advansus/a785e-i/Makefile.inc
+++ b/src/mainboard/advansus/a785e-i/Makefile.inc
@@ -3,7 +3,7 @@
 ramstage-y += reset.c
 
 #SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
  AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
  romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
  ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig
index a5920af..acc9e45 100644
--- a/src/mainboard/amd/inagua/Kconfig
+++ b/src/mainboard/amd/inagua/Kconfig
@@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select ENABLE_APIC_EXT_ID
 	select GFXUMA
-
-config AMD_AGESA
-	bool
-	default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/amd/persimmon/Kconfig b/src/mainboard/amd/persimmon/Kconfig
index e01e101..7cb5c16 100644
--- a/src/mainboard/amd/persimmon/Kconfig
+++ b/src/mainboard/amd/persimmon/Kconfig
@@ -41,10 +41,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_ACPI_TABLES
 	select BOARD_ROMSIZE_KB_4096
 	select GFXUMA
-
-config AMD_AGESA
-	bool
-	default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig
index fb41cec..69c4874 100644
--- a/src/mainboard/amd/south_station/Kconfig
+++ b/src/mainboard/amd/south_station/Kconfig
@@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_4096
 	select GFXUMA
 	select UDELAY_LAPIC
-
-config AMD_AGESA
-	bool
-	default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/amd/torpedo/Kconfig b/src/mainboard/amd/torpedo/Kconfig
index f368279..1a45724 100755
--- a/src/mainboard/amd/torpedo/Kconfig
+++ b/src/mainboard/amd/torpedo/Kconfig
@@ -44,10 +44,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
   select BOARD_ROMSIZE_KB_2048
   select ENABLE_APIC_EXT_ID
         select GFXUMA
-
-config AMD_AGESA
-        bool
-        default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
         string
diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig
index 194a39d..9c1a779 100644
--- a/src/mainboard/amd/union_station/Kconfig
+++ b/src/mainboard/amd/union_station/Kconfig
@@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select BOARD_ROMSIZE_KB_2048
 	select GFXUMA
 	select UDELAY_LAPIC
-
-config AMD_AGESA
-	bool
-	default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig
index 8324fa4..c8d5218 100644
--- a/src/mainboard/asrock/e350m1/Kconfig
+++ b/src/mainboard/asrock/e350m1/Kconfig
@@ -42,10 +42,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
         select HAVE_ACPI_TABLES
   select BOARD_ROMSIZE_KB_4096
         select GFXUMA
-
-config AMD_AGESA
-        bool
-        default y
+	select CPU_AMD_AGESA
 
 config MAINBOARD_DIR
         string
diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc
index b55a0c7..35b2043 100644
--- a/src/mainboard/asus/m5a88-v/Makefile.inc
+++ b/src/mainboard/asus/m5a88-v/Makefile.inc
@@ -1,7 +1,7 @@
 ramstage-y += reset.c
 
 #SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
  AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
  romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
  ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
diff --git a/src/mainboard/avalue/eax-785e/Makefile.inc b/src/mainboard/avalue/eax-785e/Makefile.inc
index 737bb1c..d69a9bf 100644
--- a/src/mainboard/avalue/eax-785e/Makefile.inc
+++ b/src/mainboard/avalue/eax-785e/Makefile.inc
@@ -3,7 +3,7 @@
 ramstage-y += reset.c
 
 #SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_AMD_AGESA),y)
+ifneq ($(CONFIG_CPU_AMD_AGESA),y)
  AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
  romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
  ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c
diff --git a/src/northbridge/amd/Makefile.inc b/src/northbridge/amd/Makefile.inc
index c438473..7e85d08 100644
--- a/src/northbridge/amd/Makefile.inc
+++ b/src/northbridge/amd/Makefile.inc
@@ -3,6 +3,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa
 
-subdirs-$(CONFIG_AMD_AGESA) += agesa
 subdirs-$(CONFIG_AMD_NB_CIMX) += cimx
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index 2ed9fd5..2ee921b 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -17,6 +17,12 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
+config NORTHBRIDGE_AMD_AGESA
+        bool
+        default CPU_AMD_AGESA
+
+if NORTHBRIDGE_AMD_AGESA
+
 config CONSOLE_VGA_MULTI
 	bool
 	default n
@@ -26,3 +32,4 @@ source src/northbridge/amd/agesa/family12/Kconfig
 source src/northbridge/amd/agesa/family14/Kconfig
 source src/northbridge/amd/agesa/family15/Kconfig
 
+endif # NORTHBRIDGE_AMD_AGESA



From kevin at koconnor.net  Thu Mar  8 03:27:19 2012
From: kevin at koconnor.net (Kevin O'Connor)
Date: Wed, 7 Mar 2012 21:27:19 -0500
Subject: [coreboot] Bug when I