[coreboot] Dual SPI Flash

[Oliver Schinagl]

Pin 1, 'chip select enable' is an inverted? pin. enables and
disables device operation. When chip select is high, the device is
de-selected and the serial data pins are at 'high impedance'.

 When
chip select is brought low, the device will be selected and instructions
can be written to and data read from the device.

 After power-up, Chip
Select must transition from high to low before a new instruction will be
accepted.

 So if I understand all this correctly, the chip can be
connected in parallel with the exception of the Chip Select Enable. A
simple switch to either connect it directly to the board/socket/other
end and toggle it to connect to ground (via 'some' resistor').

 I tried
to make a simple schematic in ascii, but failed horribly so i've
attached it to this message as monochrome BMP (only format that I could
quickly think of to be smallest in size). I don't know what value those
resistors need to be (and if the schematic can be even more simplified,
with a single resistor), but I belive this is the schematic used for the
dual-SPI flash 'module' 

This seems sensible to me, but my knowledge in
this field is very limited. 

On 06-03-12 10:42, Peter Stuge wrote: 

>
Oliver Schinagl wrote:
> 
>>> I guess whoever made the PCB can publish
source and gerbers so that
>>> others can order the same board if they
want.
>> 
>> That would be probably the best idea to start with. I've
been staring at 
>> the foto of the pvb for a while, and did notice as
you said, only one pin 
>> is being diverted.
> 
> So check which one
and compare with the flash chip data sheet.
> 
> //Peter

  
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