[coreboot] New patch to review for coreboot: 9bf656b Fix SATA port map to only enable port 0

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/977

-gerrit

commit 9bf656b94d245b89d388fc63ff5512f32ad7b4ee
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Mon Apr 30 16:42:07 2012 -0700

    Fix SATA port map to only enable port 0
    
    The sata controller comes up in legacy/normal mode and
    is currently put into AHCI mode in romstage.
    
    If that is removed and the controller is left alone until the
    ramstage driver (like we do on Stumpy/Lumpy) then the resource
    allocator will have configured the device for IDE mode with an
    IO address in BAR5.  Then when the ramstage driver puts the
    controller into AHCI mode it will not have the correct resources
    to do the rest of the AHCI setup.
    
    So the controller mode needs to be changed in the enable stage
    rather than in the init phase.  This same register contains
    the port map and it is a R/WO (write once) field so the configured
    port map must be written at the same time.  For non-AHCI mode
    the devicetree map was ignored before but it is used now.
    
    Since the port map register is now written at enable step it
    does not need to be written again during init.
    
    With this change the sata port map can be reduced to just port 0
    and then U-boot does not have to probe all available ports.
    
    Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/bd82x6x/sata.c |   29 ++++++++++++++++++++++-------
 1 files changed, 22 insertions(+), 7 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index ce5aea9..93dff91 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -48,8 +48,6 @@ static void sata_init(struct device *dev)
 
 	if (config->ide_legacy_combined) {
 		printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
-		/* Combine IDE - SATA configuration */
-		pci_write_config16(dev, 0x90, 0x0000);
 
 		/* No AHCI: clear AHCI base */
 		pci_write_config32(dev, 0x24, 0x00000000);
@@ -88,9 +86,6 @@ static void sata_init(struct device *dev)
 		u32 abar;
 
 		printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
-		/* Set Sata Controller Mode. */
-		pci_write_config16(dev, 0x90, 0x0060 |
-				   ((config->sata_port_map ^ 0x3f) << 8));
 
 		/* Set Interrupt Line */
 		/* Interrupt Pin is set by D31IP.PIP */
@@ -143,8 +138,6 @@ static void sata_init(struct device *dev)
 		write32(abar + 0xa0, reg32);
 	} else {
 		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
-		/* Set Sata Controller Mode. No Mapping(?) */
-		pci_write_config16(dev, 0x90, 0x0000);
 
 		/* No AHCI: clear AHCI base */
 		pci_write_config32(dev, 0x24, 0x00000000);
@@ -191,6 +184,27 @@ static void sata_init(struct device *dev)
 	}
 }
 
+static void sata_enable(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+	u16 map = 0;
+
+	if (!config)
+		return;
+
+	/*
+	 * Set SATA controller mode early so the resource allocator can
+	 * properly assign IO/Memory resources for the controller.
+	 */
+	if (config->sata_ahci)
+		map = 0x0060;
+
+	map |= (config->sata_port_map ^ 0x3f) << 8;
+
+	pci_write_config16(dev, 0x90, map);
+}
+
 static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
@@ -211,6 +225,7 @@ static struct device_operations sata_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= sata_init,
+	.enable			= sata_enable,
 	.scan_bus		= 0,
 	.ops_pci		= &sata_pci_ops,
 };