[coreboot] Patch merged into coreboot/master: 84981fe Update PCIe Root Port _PRT to handle re-mapped functions

gerrit at coreboot.org gerrit at coreboot.org
Tue May 1 21:21:21 CEST 2012


the following patch was just integrated into master:
commit 84981fe4c4542eecf8e834e19ba38f505515a3c0
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Apr 27 09:55:45 2012 -0700

    Update PCIe Root Port _PRT to handle re-mapped functions
    
    The chipset enforces static-defined interrupt swizzling on PCIe root
    ports so if a port is remapped to a different function it needs to
    still report the proper interrupt map to the OS instead of assuming
    that function number is equivalent to root port number.
    
    This change also includes an update to the PCH function disable
    register which was incorrect for CPT/PPT and would cause unpredictable
    behavior if used.
    
    The kernel command line was changed to add 'nomsi' in order to force
    PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
    that the mapping is correct.
    
    LUMPY current:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      16:   41518   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
      19:     720   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0
    
    LUMPY with PCIe port coalesce enabled:
    
      00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
      00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
    
      16:   38988   0   0   0   IO-APIC-fasteoi   i915, ahci, ath9k
      19:     347   0   0   0   IO-APIC-fasteoi   ehci_hcd:usb2, eth0
    
    Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>

Build-Tested: build bot (Jenkins) at Tue May  1 06:13:23 2012, giving +1
See http://review.coreboot.org/978 for details.

-gerrit




More information about the coreboot mailing list