[coreboot] New patch to review for coreboot: ef6dfc1 Fix register corruption during Intel Microcode update
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Thu May 3 01:47:57 CEST 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/996
-gerrit
commit ef6dfc1d0656f34331519fb97e5ec87784c4686d
Author: Stefan Reinauer <reinauer at chromium.org>
Date: Wed May 2 16:41:55 2012 -0700
Fix register corruption during Intel Microcode update
Another bug in the Intel microcode update code that existed since we switched
to LinuxBIOSv2 in 2004:
The inline assembly code that reads the CPU revision from an MSR after running
cpuid(1) trashes registers EBX and ECX. Only ECX was mentioned in the clobber
list. C code running after this function could silently access completely wrong
data, which resulted in the wrong date being printed on microcode updates (and
potentially other issues happening until the C code writes to EBX again)
Change-Id: Ida733fa1747565ec9824d3a37d08b1a73cd8355f
Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
src/cpu/intel/microcode/microcode.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index ae1c26a..ec42fb9 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -63,7 +63,7 @@ static inline u32 read_microcode_rev(void)
"=a" (msr.lo), "=d" (msr.hi)
: /* inputs */
: /* trashed */
- "ecx"
+ "ebx", "ecx"
);
return msr.hi;
}
More information about the coreboot
mailing list