[coreboot] New patch to review for coreboot: a683bce Clean up #ifs
Patrick Georgi (patrick@georgi-clan.de)
gerrit at coreboot.org
Sat May 5 15:41:04 CEST 2012
Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1004
-gerrit
commit a683bce1f9db7f5fc57daf613572a73d80412cc3
Author: Patrick Georgi <patrick at georgi-clan.de>
Date: Sat May 5 15:29:32 2012 +0200
Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +
Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +
Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +
Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +
Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick at georgi-clan.de>
---
src/arch/x86/boot/acpi.c | 2 +-
src/arch/x86/boot/coreboot_table.c | 2 +-
src/arch/x86/boot/tables.c | 6 +-
src/arch/x86/include/arch/acpi.h | 2 +-
src/arch/x86/include/arch/pci_ops.h | 2 +-
src/arch/x86/include/arch/pciconf.h | 2 +-
src/arch/x86/include/arch/pirq_routing.h | 4 +-
src/arch/x86/include/arch/romcc_io.h | 12 ++--
src/arch/x86/lib/cbfs_and_run.c | 2 +-
src/arch/x86/lib/exception.c | 2 +-
src/arch/x86/lib/pci_ops_conf1.c | 2 +-
src/boot/hardwaremain.c | 4 +-
src/cpu/amd/agesa/family10/model_10_init.c | 4 +-
src/cpu/amd/agesa/family12/model_12_init.c | 4 +-
src/cpu/amd/agesa/family14/model_14_init.c | 6 +-
src/cpu/amd/agesa/family15/model_15_init.c | 4 +-
src/cpu/amd/car/post_cache_as_ram.c | 12 ++--
src/cpu/amd/dualcore/dualcore.c | 2 +-
src/cpu/amd/model_10xxx/init_cpus.c | 10 ++--
src/cpu/amd/model_10xxx/model_10xxx_init.c | 4 +-
src/cpu/amd/model_fxx/init_cpus.c | 16 +++---
src/cpu/amd/model_fxx/model_fxx_init.c | 22 ++++----
src/cpu/amd/model_fxx/model_fxx_update_microcode.c | 8 ++--
src/cpu/amd/model_fxx/powernow_acpi.c | 2 +-
src/cpu/amd/model_fxx/processor_name.c | 12 ++--
src/cpu/amd/mtrr/amd_mtrr.c | 4 +-
src/cpu/intel/hyperthreading/intel_sibling.c | 2 +-
src/cpu/x86/lapic/lapic_cpu_init.c | 26 +++++-----
src/devices/device.c | 8 ++--
src/devices/hypertransport.c | 6 +-
src/devices/pci_device.c | 26 +++++-----
src/devices/pci_rom.c | 2 +-
src/drivers/ati/ragexl/atyfb.h | 6 +-
src/drivers/ati/ragexl/mach64_ct.c | 2 +-
src/drivers/ati/ragexl/xlinit.c | 18 +++---
src/include/cpu/amd/model_fxx_rev.h | 4 +-
src/include/cpu/x86/lapic.h | 2 +-
src/include/delay.h | 2 +-
src/include/reset.h | 2 +-
src/include/smp/atomic.h | 2 +-
src/include/smp/spinlock.h | 2 +-
src/include/watchdog.h | 2 +-
src/mainboard/advansus/a785e-i/acpi_tables.c | 2 +-
src/mainboard/advansus/a785e-i/get_bus_conf.c | 4 +-
src/mainboard/advansus/a785e-i/mainboard.c | 4 +-
src/mainboard/advansus/a785e-i/mptable.c | 2 +-
src/mainboard/advansus/a785e-i/platform_cfg.h | 2 +-
src/mainboard/advansus/a785e-i/romstage.c | 4 +-
src/mainboard/amd/bimini_fam10/get_bus_conf.c | 4 +-
src/mainboard/amd/bimini_fam10/mainboard.c | 4 +-
src/mainboard/amd/bimini_fam10/mptable.c | 2 +-
src/mainboard/amd/bimini_fam10/romstage.c | 2 +-
src/mainboard/amd/dbm690t/get_bus_conf.c | 4 +-
src/mainboard/amd/dbm690t/mainboard.c | 4 +-
src/mainboard/amd/dbm690t/mptable.c | 2 +-
src/mainboard/amd/dbm690t/romstage.c | 2 +-
src/mainboard/amd/dinar/mainboard.c | 4 +-
src/mainboard/amd/dinar/rd890_cfg.h | 4 +-
src/mainboard/amd/dinar/sb700_cfg.h | 2 +-
src/mainboard/amd/inagua/mainboard.c | 4 +-
src/mainboard/amd/inagua/mptable.c | 2 +-
src/mainboard/amd/inagua/platform_cfg.h | 2 +-
src/mainboard/amd/mahogany/get_bus_conf.c | 4 +-
src/mainboard/amd/mahogany/mainboard.c | 4 +-
src/mainboard/amd/mahogany/mptable.c | 2 +-
src/mainboard/amd/mahogany/romstage.c | 2 +-
src/mainboard/amd/mahogany_fam10/get_bus_conf.c | 4 +-
src/mainboard/amd/mahogany_fam10/mainboard.c | 4 +-
src/mainboard/amd/mahogany_fam10/mptable.c | 2 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 2 +-
src/mainboard/amd/persimmon/agesawrapper.c | 2 +-
src/mainboard/amd/persimmon/get_bus_conf.c | 4 +-
src/mainboard/amd/persimmon/mainboard.c | 6 +-
src/mainboard/amd/persimmon/mptable.c | 2 +-
src/mainboard/amd/persimmon/platform_cfg.h | 2 +-
src/mainboard/amd/persimmon/romstage.c | 6 +-
src/mainboard/amd/pistachio/get_bus_conf.c | 4 +-
src/mainboard/amd/pistachio/mainboard.c | 4 +-
src/mainboard/amd/pistachio/mptable.c | 2 +-
src/mainboard/amd/pistachio/romstage.c | 2 +-
src/mainboard/amd/serengeti_cheetah/get_bus_conf.c | 4 +-
src/mainboard/amd/serengeti_cheetah/mptable.c | 2 +-
src/mainboard/amd/serengeti_cheetah/romstage.c | 6 +-
.../amd/serengeti_cheetah_fam10/get_bus_conf.c | 2 +-
.../amd/serengeti_cheetah_fam10/mptable.c | 2 +-
.../amd/serengeti_cheetah_fam10/romstage.c | 2 +-
src/mainboard/amd/south_station/mainboard.c | 4 +-
src/mainboard/amd/south_station/mptable.c | 2 +-
src/mainboard/amd/south_station/platform_cfg.h | 2 +-
src/mainboard/amd/tilapia_fam10/get_bus_conf.c | 4 +-
src/mainboard/amd/tilapia_fam10/mainboard.c | 4 +-
src/mainboard/amd/tilapia_fam10/mptable.c | 2 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 2 +-
src/mainboard/amd/torpedo/Oem.h | 2 +-
src/mainboard/amd/torpedo/mainboard.c | 4 +-
src/mainboard/amd/torpedo/mptable.c | 2 +-
src/mainboard/amd/torpedo/platform_cfg.h | 6 +-
src/mainboard/amd/union_station/mainboard.c | 4 +-
src/mainboard/amd/union_station/mptable.c | 2 +-
src/mainboard/amd/union_station/platform_cfg.h | 2 +-
src/mainboard/arima/hdama/romstage.c | 2 +-
src/mainboard/asrock/939a785gmh/get_bus_conf.c | 4 +-
src/mainboard/asrock/939a785gmh/mainboard.c | 4 +-
src/mainboard/asrock/939a785gmh/mptable.c | 2 +-
src/mainboard/asrock/939a785gmh/romstage.c | 2 +-
src/mainboard/asrock/e350m1/mainboard.c | 4 +-
src/mainboard/asrock/e350m1/mptable.c | 2 +-
src/mainboard/asrock/e350m1/platform_cfg.h | 2 +-
src/mainboard/asus/a8n_e/get_bus_conf.c | 4 +-
src/mainboard/asus/a8n_e/romstage.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +-
src/mainboard/asus/a8v-e_se/romstage.c | 2 +-
src/mainboard/asus/k8v-x/romstage.c | 2 +-
src/mainboard/asus/m2n-e/get_bus_conf.c | 4 +-
src/mainboard/asus/m2n-e/romstage.c | 6 +-
src/mainboard/asus/m2v-mx_se/mainboard.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 4 +-
src/mainboard/asus/m2v/romstage.c | 4 +-
src/mainboard/asus/m4a78-em/get_bus_conf.c | 4 +-
src/mainboard/asus/m4a78-em/mainboard.c | 2 +-
src/mainboard/asus/m4a78-em/mptable.c | 2 +-
src/mainboard/asus/m4a78-em/romstage.c | 2 +-
src/mainboard/asus/m4a785-m/get_bus_conf.c | 4 +-
src/mainboard/asus/m4a785-m/mainboard.c | 2 +-
src/mainboard/asus/m4a785-m/mptable.c | 2 +-
src/mainboard/asus/m4a785-m/romstage.c | 2 +-
src/mainboard/asus/m5a88-v/acpi_tables.c | 2 +-
src/mainboard/asus/m5a88-v/get_bus_conf.c | 4 +-
src/mainboard/asus/m5a88-v/mainboard.c | 4 +-
src/mainboard/asus/m5a88-v/mptable.c | 2 +-
src/mainboard/asus/m5a88-v/platform_cfg.h | 2 +-
src/mainboard/asus/m5a88-v/romstage.c | 4 +-
src/mainboard/avalue/eax-785e/acpi_tables.c | 2 +-
src/mainboard/avalue/eax-785e/get_bus_conf.c | 8 ++--
src/mainboard/avalue/eax-785e/mainboard.c | 4 +-
src/mainboard/avalue/eax-785e/mptable.c | 2 +-
src/mainboard/avalue/eax-785e/platform_cfg.h | 2 +-
src/mainboard/avalue/eax-785e/romstage.c | 4 +-
src/mainboard/broadcom/blast/get_bus_conf.c | 4 +-
src/mainboard/broadcom/blast/mptable.c | 2 +-
src/mainboard/broadcom/blast/romstage.c | 2 +-
src/mainboard/emulation/qemu-x86/northbridge.c | 4 +-
src/mainboard/getac/p470/romstage.c | 2 +-
src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 4 +-
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 6 +-
src/mainboard/gigabyte/m57sli/get_bus_conf.c | 4 +-
src/mainboard/gigabyte/m57sli/romstage.c | 6 +-
src/mainboard/gigabyte/ma785gm/get_bus_conf.c | 4 +-
src/mainboard/gigabyte/ma785gm/mainboard.c | 4 +-
src/mainboard/gigabyte/ma785gm/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gm/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gmt/get_bus_conf.c | 4 +-
src/mainboard/gigabyte/ma785gmt/mainboard.c | 4 +-
src/mainboard/gigabyte/ma785gmt/mptable.c | 2 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +-
src/mainboard/gigabyte/ma78gm/get_bus_conf.c | 4 +-
src/mainboard/gigabyte/ma78gm/mainboard.c | 4 +-
src/mainboard/gigabyte/ma78gm/mptable.c | 2 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 2 +-
src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 +-
src/mainboard/hp/dl145_g1/romstage.c | 4 +-
src/mainboard/hp/dl145_g3/get_bus_conf.c | 4 +-
src/mainboard/hp/dl145_g3/mptable.c | 2 +-
src/mainboard/hp/dl145_g3/romstage.c | 6 +-
src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 2 +-
src/mainboard/hp/dl165_g6_fam10/mptable.c | 2 +-
src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +-
src/mainboard/ibm/e325/romstage.c | 2 +-
src/mainboard/ibm/e326/romstage.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c | 4 +-
src/mainboard/iei/kino-780am2-fam10/mainboard.c | 4 +-
src/mainboard/iei/kino-780am2-fam10/mptable.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +-
src/mainboard/intel/eagleheights/fadt.c | 2 +-
src/mainboard/iwill/dk8_htx/get_bus_conf.c | 4 +-
src/mainboard/iwill/dk8_htx/mptable.c | 2 +-
src/mainboard/iwill/dk8_htx/romstage.c | 6 +-
src/mainboard/iwill/dk8s2/romstage.c | 6 +-
src/mainboard/iwill/dk8x/romstage.c | 6 +-
src/mainboard/jetway/pa78vm5/get_bus_conf.c | 4 +-
src/mainboard/jetway/pa78vm5/mainboard.c | 4 +-
src/mainboard/jetway/pa78vm5/mptable.c | 2 +-
src/mainboard/jetway/pa78vm5/romstage.c | 2 +-
src/mainboard/kontron/kt690/get_bus_conf.c | 4 +-
src/mainboard/kontron/kt690/mainboard.c | 4 +-
src/mainboard/kontron/kt690/mptable.c | 2 +-
src/mainboard/kontron/kt690/romstage.c | 2 +-
src/mainboard/msi/ms7135/get_bus_conf.c | 4 +-
src/mainboard/msi/ms7135/romstage.c | 2 +-
src/mainboard/msi/ms7260/get_bus_conf.c | 4 +-
src/mainboard/msi/ms7260/romstage.c | 6 +-
src/mainboard/msi/ms9185/get_bus_conf.c | 4 +-
src/mainboard/msi/ms9185/mptable.c | 2 +-
src/mainboard/msi/ms9185/romstage.c | 2 +-
src/mainboard/msi/ms9282/get_bus_conf.c | 4 +-
src/mainboard/msi/ms9282/romstage.c | 2 +-
src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 4 +-
src/mainboard/msi/ms9652_fam10/romstage.c | 2 +-
src/mainboard/newisys/khepri/romstage.c | 2 +-
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c | 4 +-
src/mainboard/nvidia/l1_2pvv/romstage.c | 6 +-
src/mainboard/siemens/sitemp_g1p1/acpi_tables.c | 2 +-
src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c | 4 +-
src/mainboard/siemens/sitemp_g1p1/mainboard.c | 8 ++--
src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +-
src/mainboard/sunw/ultra40/get_bus_conf.c | 4 +-
src/mainboard/sunw/ultra40/romstage.c | 2 +-
src/mainboard/supermicro/h8dme/get_bus_conf.c | 4 +-
src/mainboard/supermicro/h8dme/romstage.c | 6 +-
src/mainboard/supermicro/h8dmr/get_bus_conf.c | 4 +-
src/mainboard/supermicro/h8dmr/romstage.c | 6 +-
.../supermicro/h8dmr_fam10/get_bus_conf.c | 4 +-
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +-
src/mainboard/supermicro/h8qgi/buildOpts.c | 6 +-
src/mainboard/supermicro/h8qgi/mainboard.c | 2 +-
src/mainboard/supermicro/h8qgi/rd890_cfg.h | 4 +-
src/mainboard/supermicro/h8qgi/sb700_cfg.h | 2 +-
.../supermicro/h8qme_fam10/get_bus_conf.c | 4 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +-
.../supermicro/h8scm_fam10/get_bus_conf.c | 4 +-
src/mainboard/supermicro/h8scm_fam10/mainboard.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/mptable.c | 2 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +-
src/mainboard/technexion/tim5690/get_bus_conf.c | 4 +-
src/mainboard/technexion/tim5690/mainboard.c | 4 +-
src/mainboard/technexion/tim5690/mptable.c | 2 +-
src/mainboard/technexion/tim5690/romstage.c | 2 +-
src/mainboard/technexion/tim8690/get_bus_conf.c | 4 +-
src/mainboard/technexion/tim8690/mainboard.c | 4 +-
src/mainboard/technexion/tim8690/mptable.c | 2 +-
src/mainboard/technexion/tim8690/romstage.c | 2 +-
src/mainboard/tyan/s2850/mptable.c | 4 +-
src/mainboard/tyan/s2850/romstage.c | 2 +-
src/mainboard/tyan/s2875/mptable.c | 4 +-
src/mainboard/tyan/s2875/romstage.c | 2 +-
src/mainboard/tyan/s2880/mptable.c | 4 +-
src/mainboard/tyan/s2880/romstage.c | 2 +-
src/mainboard/tyan/s2881/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2881/romstage.c | 2 +-
src/mainboard/tyan/s2882/mptable.c | 4 +-
src/mainboard/tyan/s2882/romstage.c | 2 +-
src/mainboard/tyan/s2885/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2885/romstage.c | 2 +-
src/mainboard/tyan/s2891/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2891/romstage.c | 2 +-
src/mainboard/tyan/s2892/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2892/romstage.c | 2 +-
src/mainboard/tyan/s2895/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2912/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2912/romstage.c | 6 +-
src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 4 +-
src/mainboard/tyan/s2912_fam10/romstage.c | 2 +-
src/mainboard/tyan/s4880/mptable.c | 4 +-
src/mainboard/tyan/s4880/romstage.c | 2 +-
src/mainboard/tyan/s4882/mptable.c | 4 +-
src/mainboard/tyan/s4882/romstage.c | 2 +-
src/mainboard/via/epia-n/mainboard.c | 2 +-
src/northbridge/amd/agesa/family10/northbridge.c | 38 +++++++-------
src/northbridge/amd/agesa/family12/northbridge.c | 24 ++++----
src/northbridge/amd/agesa/family14/northbridge.c | 24 ++++----
src/northbridge/amd/agesa/family15/northbridge.c | 24 ++++----
src/northbridge/amd/amdfam10/amdfam10.h | 8 ++--
src/northbridge/amd/amdfam10/conf.c | 10 ++--
src/northbridge/amd/amdfam10/debug.c | 2 +-
src/northbridge/amd/amdfam10/early_ht.c | 4 +-
src/northbridge/amd/amdfam10/northbridge.c | 54 ++++++++++----------
src/northbridge/amd/amdfam10/reset_test.c | 2 +-
src/northbridge/amd/amdht/ht_wrapper.c | 2 +-
src/northbridge/amd/amdk8/amdk8.h | 2 +-
src/northbridge/amd/amdk8/coherent_ht.c | 24 ++++----
src/northbridge/amd/amdk8/debug.c | 2 +-
src/northbridge/amd/amdk8/incoherent_ht.c | 12 ++--
src/northbridge/amd/amdk8/misc_control.c | 2 +-
src/northbridge/amd/amdk8/northbridge.c | 42 ++++++++--------
src/northbridge/amd/amdk8/raminit.c | 4 +-
src/northbridge/amd/amdk8/raminit_f.c | 10 ++--
src/northbridge/amd/amdk8/raminit_f_dqs.c | 22 ++++----
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 10 ++--
src/northbridge/amd/gx1/northbridge.c | 4 +-
src/northbridge/amd/gx2/northbridge.c | 4 +-
src/northbridge/amd/lx/northbridge.c | 4 +-
src/northbridge/intel/e7501/northbridge.c | 4 +-
src/northbridge/intel/e7505/northbridge.c | 4 +-
src/northbridge/intel/e7520/northbridge.c | 4 +-
src/northbridge/intel/e7525/northbridge.c | 4 +-
src/northbridge/intel/i3100/northbridge.c | 4 +-
src/northbridge/intel/i3100/raminit.c | 2 +-
src/northbridge/intel/i440bx/northbridge.c | 4 +-
src/northbridge/intel/i440lx/northbridge.c | 4 +-
src/northbridge/intel/i82810/northbridge.c | 4 +-
src/northbridge/intel/i82830/northbridge.c | 4 +-
src/northbridge/intel/i855/northbridge.c | 4 +-
src/northbridge/intel/i945/northbridge.c | 4 +-
src/northbridge/intel/sandybridge/northbridge.c | 4 +-
src/northbridge/intel/sch/northbridge.c | 4 +-
src/northbridge/rdc/r8610/northbridge.c | 4 +-
src/northbridge/via/cn400/northbridge.c | 4 +-
src/northbridge/via/cn700/northbridge.c | 4 +-
src/northbridge/via/cx700/northbridge.c | 4 +-
src/northbridge/via/vt8601/northbridge.c | 4 +-
src/northbridge/via/vt8623/northbridge.c | 4 +-
src/northbridge/via/vx800/examples/chipset_init.c | 4 +-
src/southbridge/amd/amd8111/acpi.c | 4 +-
src/southbridge/amd/cimx/sb700/bootblock.c | 2 +-
src/southbridge/amd/cimx/sb700/early.c | 2 +-
src/southbridge/amd/cimx/sb700/sb_cimx.h | 2 +-
src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +-
src/southbridge/amd/cimx/sb800/cfg.c | 4 +-
src/southbridge/amd/cimx/sb800/early.c | 4 +-
src/southbridge/amd/cimx/sb800/late.c | 4 +-
src/southbridge/amd/cimx/sb800/sb_cimx.h | 2 +-
src/southbridge/amd/cimx/sb900/bootblock.c | 2 +-
src/southbridge/amd/cs5530/vga.c | 4 +-
src/southbridge/amd/rs690/ht.c | 6 +-
src/southbridge/amd/rs780/early_setup.c | 2 +-
src/southbridge/amd/rs780/gfx.c | 6 +-
src/southbridge/amd/rs780/rs780.c | 2 +-
src/southbridge/amd/sb600/ide.c | 2 +-
src/southbridge/amd/sb700/early_setup.c | 2 +-
src/southbridge/amd/sb700/ide.c | 2 +-
src/southbridge/amd/sb700/lpc.c | 2 +-
src/southbridge/amd/sb700/sb700.h | 2 +-
src/southbridge/amd/sb800/early_setup.c | 2 +-
src/southbridge/amd/sb800/ide.c | 2 +-
src/southbridge/broadcom/bcm5780/nic.c | 2 +-
src/southbridge/intel/i82371eb/smbus.c | 4 +-
src/southbridge/nvidia/ck804/early_setup.c | 2 +-
src/southbridge/nvidia/ck804/early_setup_car.c | 2 +-
src/southbridge/nvidia/ck804/ide.c | 2 +-
src/southbridge/nvidia/ck804/nic.c | 2 +-
src/southbridge/nvidia/mcp55/ide.c | 2 +-
src/southbridge/nvidia/mcp55/nic.c | 2 +-
src/southbridge/nvidia/mcp55/smbus.c | 4 +-
src/southbridge/sis/sis966/ide.c | 2 +-
src/southbridge/via/vt8237r/early_smbus.c | 2 +-
src/southbridge/via/vt8237r/lpc.c | 2 +-
src/superio/via/vt1211/vt1211.c | 2 +-
337 files changed, 729 insertions(+), 729 deletions(-)
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 010ba9f..6932208 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -550,7 +550,7 @@ void acpi_write_hest(acpi_hest_t *hest)
header->checksum = acpi_checksum((void *)hest, header->length);
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
void suspend_resume(void)
{
void *wake_vec;
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index 9ceca45..5b5834a 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -324,7 +324,7 @@ static void lb_strings(struct lb_header *header)
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 4fefc7d..72aa979 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -71,7 +71,7 @@ struct lb_memory *write_tables(void)
low_table_start = 0;
low_table_end = 0x500;
-#if CONFIG_GENERATE_PIRQ_TABLE == 1
+#if CONFIG_GENERATE_PIRQ_TABLE
#define MAX_PIRQ_TABLE_SIZE (4 * 1024)
post_code(0x9a);
@@ -97,7 +97,7 @@ struct lb_memory *write_tables(void)
#endif
-#if CONFIG_GENERATE_MP_TABLE == 1
+#if CONFIG_GENERATE_MP_TABLE
#define MAX_MP_TABLE_SIZE (4 * 1024)
post_code(0x9b);
@@ -120,7 +120,7 @@ struct lb_memory *write_tables(void)
}
#endif /* CONFIG_GENERATE_MP_TABLE */
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
#define MAX_ACPI_SIZE (45 * 1024)
post_code(0x9c);
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index be62008..9f790cc 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -27,7 +27,7 @@
#ifndef __ASM_ACPI_H
#define __ASM_ACPI_H
-#if CONFIG_GENERATE_ACPI_TABLES==1
+#if CONFIG_GENERATE_ACPI_TABLES
#include <stdint.h>
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index 9c4e029..955ccd3 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -4,7 +4,7 @@
extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_cf8_conf2;
-#if CONFIG_MMCONF_SUPPORT==1
+#if CONFIG_MMCONF_SUPPORT
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
diff --git a/src/arch/x86/include/arch/pciconf.h b/src/arch/x86/include/arch/pciconf.h
index a356935..df21817 100644
--- a/src/arch/x86/include/arch/pciconf.h
+++ b/src/arch/x86/include/arch/pciconf.h
@@ -5,7 +5,7 @@
#define PCI_CONF_REG_INDEX 0xcf8
#define PCI_CONF_REG_DATA 0xcfc
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where))
#else
#define CONFIG_ADDR(bus,devfn,where) (((bus) << 16) | ((devfn) << 8) | (where & 0xff) | ((where & 0xf00)<<16) )
diff --git a/src/arch/x86/include/arch/pirq_routing.h b/src/arch/x86/include/arch/pirq_routing.h
index 0b65eac..08ba535 100644
--- a/src/arch/x86/include/arch/pirq_routing.h
+++ b/src/arch/x86/include/arch/pirq_routing.h
@@ -1,7 +1,7 @@
#ifndef ARCH_PIRQ_ROUTING_H
#define ARCH_PIRQ_ROUTING_H
-#if CONFIG_GENERATE_PIRQ_TABLE==1
+#if CONFIG_GENERATE_PIRQ_TABLE
#include <stdint.h>
#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
@@ -39,7 +39,7 @@ extern const struct irq_routing_table intel_irq_routing_table;
unsigned long copy_pirq_routing_table(unsigned long start);
unsigned long write_pirq_routing_table(unsigned long start);
-#if CONFIG_PIRQ_ROUTE==1
+#if CONFIG_PIRQ_ROUTE
void pirq_routing_irqs(unsigned long start);
void pirq_assign_irqs(const unsigned char pIntAtoD[4]);
#else
diff --git a/src/arch/x86/include/arch/romcc_io.h b/src/arch/x86/include/arch/romcc_io.h
index b0c8f65..37fb7ab 100644
--- a/src/arch/x86/include/arch/romcc_io.h
+++ b/src/arch/x86/include/arch/romcc_io.h
@@ -65,7 +65,7 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha
static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0
@@ -94,7 +94,7 @@ static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t d
static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -125,7 +125,7 @@ static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t
static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -155,7 +155,7 @@ static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t
static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -186,7 +186,7 @@ static inline __attribute__((always_inline)) void pci_write_config8(device_t dev
static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
@@ -217,7 +217,7 @@ static inline __attribute__((always_inline)) void pci_write_config16(device_t de
static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value)
{
unsigned addr;
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
addr = (dev>>4) | where;
#else
addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16);
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 53f06ee..62b2789 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -50,7 +50,7 @@ void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset)
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset);
}
-#if CONFIG_AP_CODE_IN_CAR == 1
+#if CONFIG_AP_CODE_IN_CAR
void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr);
diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c
index 91525d5..4721bc8 100644
--- a/src/arch/x86/lib/exception.c
+++ b/src/arch/x86/lib/exception.c
@@ -365,7 +365,7 @@ void x86_exception(struct eregs *info);
void x86_exception(struct eregs *info)
{
-#if CONFIG_GDB_STUB == 1
+#if CONFIG_GDB_STUB
int signo;
memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
gdb_stub_registers[PC] = info->eip;
diff --git a/src/arch/x86/lib/pci_ops_conf1.c b/src/arch/x86/lib/pci_ops_conf1.c
index 266a9cc..77df4b3 100644
--- a/src/arch/x86/lib/pci_ops_conf1.c
+++ b/src/arch/x86/lib/pci_ops_conf1.c
@@ -8,7 +8,7 @@
* Functions for accessing PCI configuration space with type 1 accesses
*/
-#if CONFIG_PCI_IO_CFG_EXT == 0
+#if !CONFIG_PCI_IO_CFG_EXT
#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | \
(devfn << 8) | (where & ~3))
#else
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 532135f..f0853ec 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -113,13 +113,13 @@ void hardwaremain(int boot_complete)
timestamps[5] = rdtsc();
#endif
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
cbmem_initialize();
#if CONFIG_CONSOLE_CBMEM
cbmemc_reinit();
#endif
#endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
suspend_resume();
post_code(0x8a);
#endif
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c
index 8c1cfad..c216a81 100644
--- a/src/cpu/amd/agesa/family10/model_10_init.c
+++ b/src/cpu/amd/agesa/family10/model_10_init.c
@@ -61,7 +61,7 @@ static void model_10_init(device_t dev)
u8 i;
msr_t msr;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -88,7 +88,7 @@ static void model_10_init(device_t dev)
// init_processor_name();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c
index 3a12db3..4ed477c 100644
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -63,7 +63,7 @@ static void model_12_init(device_t dev)
u8 i;
msr_t msr;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -94,7 +94,7 @@ static void model_12_init(device_t dev)
// init_processor_name();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
index d90695a..9cc36e2 100644
--- a/src/cpu/amd/agesa/family14/model_14_init.c
+++ b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -61,7 +61,7 @@ static void model_14_init(device_t dev)
{
u32 i;
msr_t msr;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
@@ -94,7 +94,7 @@ static void model_14_init(device_t dev)
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type == 3)
restore_mtrr();
#endif
@@ -112,7 +112,7 @@ static void model_14_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c
index d100338..39775ba 100644
--- a/src/cpu/amd/agesa/family15/model_15_init.c
+++ b/src/cpu/amd/agesa/family15/model_15_init.c
@@ -59,7 +59,7 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -95,7 +95,7 @@ static void model_15_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 270c542..d99be48 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -29,7 +29,7 @@ static void inline __attribute__((always_inline)) memcopy(void *dest, const voi
: "memory", "cc");
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
static inline void *backup_resume(void) {
unsigned long high_ram_base;
@@ -83,7 +83,7 @@ static void vErrata343(void)
static void post_cache_as_ram(void)
{
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
#if 1
@@ -108,7 +108,7 @@ static void post_cache_as_ram(void)
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
resume_backup_memory = backup_resume();
#endif
@@ -142,7 +142,7 @@ static void post_cache_as_ram(void)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
/* now copy the rest of the area, using the WB method because we already
run normal RAM */
if (resume_backup_memory) {
@@ -154,7 +154,7 @@ static void post_cache_as_ram(void)
print_debug("Clearing initial memory region: ");
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
/* clear only coreboot used region of memory. Note: this may break ECC enabled boards */
memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE);
#else
@@ -164,7 +164,7 @@ static void post_cache_as_ram(void)
set_sysinfo_in_ram(1); // So other core0 could start to train mem
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
// struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
diff --git a/src/cpu/amd/dualcore/dualcore.c b/src/cpu/amd/dualcore/dualcore.c
index 9c2583f..69ce56a 100644
--- a/src/cpu/amd/dualcore/dualcore.c
+++ b/src/cpu/amd/dualcore/dualcore.c
@@ -17,7 +17,7 @@ static inline unsigned get_core_num_in_bsp(unsigned nodeid)
static inline uint8_t set_apicid_cpuid_lo(void)
{
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
#endif
diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index e0538af..edc016a 100644
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -33,7 +33,7 @@ static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void);
-#if CONFIG_PCI_IO_CFG_EXT == 1
+#if CONFIG_PCI_IO_CFG_EXT
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG[46]=1;
@@ -112,7 +112,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
j * (nb_cfg_54 ? 1 : 64);
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
-#if CONFIG_LIFT_BSP_APIC_ID == 0
+#if !CONFIG_LIFT_BSP_APIC_ID
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@@ -267,7 +267,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
set_EnableCf8ExtCfg(); /* only set it on core0 */
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_ENABLE_APIC_EXT_ID
enable_apic_ext_id(id.nodeid);
#endif
}
@@ -277,7 +277,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();
-#if CONFIG_LIFT_BSP_APIC_ID == 0
+#if !CONFIG_LIFT_BSP_APIC_ID
if (initial_apicid != 0) // other than bsp
#endif
{
@@ -289,7 +289,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
lapic_write(LAPIC_ID, dword);
}
-#if CONFIG_LIFT_BSP_APIC_ID == 1
+#if CONFIG_LIFT_BSP_APIC_ID
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index cf11135..27f56c2 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -63,7 +63,7 @@ static void model_10xxx_init(device_t dev)
u8 i;
msr_t msr;
struct node_core_id id;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -92,7 +92,7 @@ static void model_10xxx_init(device_t dev)
/* Set the processor name string */
init_processor_name();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c
index 0036277..ed1c830 100644
--- a/src/cpu/amd/model_fxx/init_cpus.c
+++ b/src/cpu/amd/model_fxx/init_cpus.c
@@ -40,7 +40,7 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
3);
if (nb_cfg_54) {
if (j == 0) { // if it is single core, we need to increase siblings for apic calculation
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
@@ -72,8 +72,8 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
i * (nb_cfg_54 ? (siblings + 1) : 1) +
j * (nb_cfg_54 ? 1 : 8);
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
-#if CONFIG_LIFT_BSP_APIC_ID == 0
+#if CONFIG_ENABLE_APIC_EXT_ID
+#if !CONFIG_LIFT_BSP_APIC_ID
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
@@ -215,7 +215,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
core0 is done at first --- use wait_all_core0_started */
if (id.coreid == 0) {
set_apicid_cpuid_lo(); /* only set it on core0 */
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_ENABLE_APIC_EXT_ID
enable_apic_ext_id(id.nodeid);
#endif
}
@@ -223,10 +223,10 @@ static u32 init_cpus(u32 cpu_init_detectedx)
enable_lapic();
// init_timer(); // We need TMICT to pass msg for FID/VID change
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_ENABLE_APIC_EXT_ID
u32 initial_apicid = get_initial_apicid();
-#if CONFIG_LIFT_BSP_APIC_ID == 0
+#if !CONFIG_LIFT_BSP_APIC_ID
if (initial_apicid != 0) // other than bsp
#endif
{
@@ -238,7 +238,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
lapic_write(LAPIC_ID, dword);
}
-#if CONFIG_LIFT_BSP_APIC_ID == 1
+#if CONFIG_LIFT_BSP_APIC_ID
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif
@@ -293,7 +293,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
}
lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
train_ram_on_node(id.nodeid, id.coreid, sysinfo,
(unsigned)STOP_CAR_AND_CPU);
#endif
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c
index ae5429d..7084606 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -31,7 +31,7 @@
#if CONFIG_WAIT_BEFORE_CPUS_INIT
void cpus_ready_for_init(void)
{
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox);
@@ -39,7 +39,7 @@ void cpus_ready_for_init(void)
}
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@@ -67,7 +67,7 @@ int is_e0_later_in_bsp(int nodeid)
}
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
@@ -298,7 +298,7 @@ static void init_ecc_memory(unsigned node_id)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
unsigned long hole_startk = 0;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0()) {
#endif
@@ -307,7 +307,7 @@ static void init_ecc_memory(unsigned node_id)
if (val & 1) {
hole_startk = ((val & (0xff << 24)) >> 10);
}
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
}
#endif
#endif
@@ -370,7 +370,7 @@ static void init_ecc_memory(unsigned node_id)
static inline void k8_errata(void)
{
msr_t msr;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
@@ -437,14 +437,14 @@ static inline void k8_errata(void)
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
/* I can't touch this msr on early buggy cpus */
if (!is_cpu_pre_b3())
#endif
{
msr = rdmsr(NB_CFG_MSR);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
/* Erratum 86 Disable data masking on C0 and
@@ -523,7 +523,7 @@ static void model_fxx_init(device_t dev)
/* Enable the local cpu apics */
setup_lapic();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
u32 siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
@@ -570,7 +570,7 @@ static struct device_operations cpu_dev_ops = {
};
static struct cpu_device_id cpu_table[] = {
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
{ X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
{ X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
{ X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
@@ -612,7 +612,7 @@ static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
/*
* AMD F0 support.
*
diff --git a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
index 5cc0fba..69769c9 100644
--- a/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
+++ b/src/cpu/amd/model_fxx/model_fxx_update_microcode.c
@@ -27,13 +27,13 @@
static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
#include "microcode_rev_c.h"
#include "microcode_rev_d.h"
#include "microcode_rev_e.h"
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
// #include "microcode_rev_f.h"
#endif
/* Dummy terminator */
@@ -45,7 +45,7 @@ static uint8_t microcode_updates[] __attribute__ ((aligned(16))) = {
static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
static unsigned id_mapping_table[] = {
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
0x0f48, 0x0048,
0x0f58, 0x0048,
@@ -68,7 +68,7 @@ static unsigned get_equivalent_processor_rev_id(unsigned orig_id) {
0x20fb1, 0x0210,
#endif
- #if CONFIG_K8_REV_F_SUPPORT == 1
+ #if CONFIG_K8_REV_F_SUPPORT
#endif
diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index 83d34f1..81b1067 100644
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -632,7 +632,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
return 0;
}
-#if CONFIG_MAX_PHYSICAL_CPUS==1
+#if CONFIG_MAX_PHYSICAL_CPUS
/* IRT 80us RVO = 50mV PLL_LOCK_TIME 2us, MVS 25mv, VST 100us */
control = (3 << 30) | (2 << 28) | (2 << 20) | (0 << 18) | (5 << 11);
#else
diff --git a/src/cpu/amd/model_fxx/processor_name.c b/src/cpu/amd/model_fxx/processor_name.c
index 3f3d973..6f45b0f 100644
--- a/src/cpu/amd/model_fxx/processor_name.c
+++ b/src/cpu/amd/model_fxx/processor_name.c
@@ -42,7 +42,7 @@
* your mainboard will not be posted on the AMD Recommended Motherboard Website
*/
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
static const char *processor_names[]={
/* 0x00 */ "AMD Engineering Sample",
/* 0x01-0x03 */ NULL, NULL, NULL,
@@ -113,7 +113,7 @@ static inline void wrmsr_amd(unsigned index, msr_t msr)
int init_processor_name(void)
{
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
u32 EightBitBrandId;
#endif
u32 BrandId;
@@ -127,7 +127,7 @@ int init_processor_name(void)
char program_string[48];
unsigned int *program_values = (unsigned int *)program_string;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
/* Find out which CPU brand it is */
EightBitBrandId = cpuid_ebx(0x00000001) & 0xff;
BrandId = cpuid_ebx(0x80000001) & 0xffff;
@@ -151,7 +151,7 @@ int init_processor_name(void)
processor_name_string = "AMD Processor model unknown";
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
u32 Socket;
u32 CmpCap;
u32 PwrLmt;
@@ -407,7 +407,7 @@ int init_processor_name(void)
for (i=0; i<47; i++) { // 48 -1
if(program_string[i] == program_string[i+1]) {
switch (program_string[i]) {
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
case 'X': ModelNumber = 22+ NN; break;
case 'Y': ModelNumber = 38 + (2*NN); break;
case 'Z':
@@ -416,7 +416,7 @@ int init_processor_name(void)
case 'V': ModelNumber = 9 + NN; break;
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
case 'R': ModelNumber = NN - 1; break;
case 'P': ModelNumber = 26 + NN; break;
case 'T': ModelNumber = 15 + (CmpCap * 10) + NN; break;
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 54a70e2..5c48cfd 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -6,7 +6,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_size;
#endif
@@ -163,7 +163,7 @@ void amd_setup_mtrrs(void)
* has been deducted from the size of memory below 4GB.
* When setting TOM, include UMA DRAM
*/
- #if CONFIG_GFXUMA == 1
+ #if CONFIG_GFXUMA
msr.lo += uma_memory_size;
#endif
wrmsr(TOP_MEM, msr);
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c
index e988664..2d2e105 100644
--- a/src/cpu/intel/hyperthreading/intel_sibling.c
+++ b/src/cpu/intel/hyperthreading/intel_sibling.c
@@ -7,7 +7,7 @@
#include <smp/spinlock.h>
#include <assert.h>
-#if CONFIG_SERIAL_CPU_INIT==0
+#if !CONFIG_SERIAL_CPU_INIT
#error Intel hyper-threading requires serialized cpu init
#endif
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index f823981..e491d46 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -16,7 +16,7 @@
#include <cpu/cpu.h>
#include <cpu/intel/speedstep.h>
-#if CONFIG_SMP == 1
+#if CONFIG_SMP
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -29,7 +29,7 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
char *lowmem_backup;
char *lowmem_backup_ptr;
int lowmem_backup_size;
@@ -49,7 +49,7 @@ static void copy_secondary_start_to_1m_below(void)
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
@@ -277,7 +277,7 @@ int start_cpu(device_t cpu)
return result;
}
-#if CONFIG_AP_IN_SIPI_WAIT == 1
+#if CONFIG_AP_IN_SIPI_WAIT
/**
* Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay.
@@ -384,7 +384,7 @@ static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Dat
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
-#if CONFIG_SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT
spin_lock(&start_cpu_lock);
#endif
@@ -399,7 +399,7 @@ void secondary_cpu_init(void)
writecr4(cr4_val);
#endif
cpu_initialize();
-#if CONFIG_SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT
spin_unlock(&start_cpu_lock);
#endif
@@ -417,7 +417,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
- #if CONFIG_SERIAL_CPU_INIT == 0
+ #if !CONFIG_SERIAL_CPU_INIT
if(cpu==bsp_cpu) {
continue;
}
@@ -436,7 +436,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
-#if CONFIG_SERIAL_CPU_INIT == 1
+#if CONFIG_SERIAL_CPU_INIT
udelay(10);
#endif
}
@@ -502,7 +502,7 @@ void initialize_cpus(struct bus *cpu_bus)
/* Find the device structure for the boot cpu */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
-#if CONFIG_SMP == 1
+#if CONFIG_SMP
copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
#endif
@@ -512,8 +512,8 @@ void initialize_cpus(struct bus *cpu_bus)
cpus_ready_for_init();
-#if CONFIG_SMP == 1
- #if CONFIG_SERIAL_CPU_INIT == 0
+#if CONFIG_SMP
+ #if !CONFIG_SERIAL_CPU_INIT
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
#endif
@@ -522,8 +522,8 @@ void initialize_cpus(struct bus *cpu_bus)
/* Initialize the bootstrap processor */
cpu_initialize();
-#if CONFIG_SMP == 1
- #if CONFIG_SERIAL_CPU_INIT == 1
+#if CONFIG_SMP
+ #if CONFIG_SERIAL_CPU_INIT
start_other_cpus(cpu_bus, info->cpu);
#endif
diff --git a/src/devices/device.c b/src/devices/device.c
index 0e9c39e..ebac1a0 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -536,7 +536,7 @@ static void allocate_resources(struct bus *bus, struct resource *bridge,
}
}
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#else
#define MEM_MASK (IORESOURCE_MEM)
@@ -676,7 +676,7 @@ static void avoid_fixed_resources(struct device *dev)
}
}
-#if CONFIG_VGA_BRIDGE_SETUP == 1
+#if CONFIG_VGA_BRIDGE_SETUP
device_t vga_pri = 0;
static void set_vga_bridge_bits(void)
{
@@ -725,7 +725,7 @@ static void set_vga_bridge_bits(void)
if (!vga)
vga = vga_first;
-#if CONFIG_ONBOARD_VGA_IS_PRIMARY == 1
+#if CONFIG_ONBOARD_VGA_IS_PRIMARY
if (vga_onboard) /* Will use onboard VGA as primary. */
#else
if (!vga) /* Will use last add-on adapter as primary. */
@@ -935,7 +935,7 @@ void dev_configure(void)
struct device *root;
struct device *child;
-#if CONFIG_VGA_BRIDGE_SETUP == 1
+#if CONFIG_VGA_BRIDGE_SETUP
set_vga_bridge_bits();
#endif
diff --git a/src/devices/hypertransport.c b/src/devices/hypertransport.c
index 9267291..420054e 100644
--- a/src/devices/hypertransport.c
+++ b/src/devices/hypertransport.c
@@ -103,9 +103,9 @@ static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
/* AMD K8 unsupported 1GHz? */
if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
-#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
/* Only e0 later suupport 1GHz HT. */
if (is_cpu_pre_e0())
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
@@ -351,7 +351,7 @@ static void ht_collapse_early_enumeration(struct bus *bus,
} while ((ctrl & (1 << 5)) == 0);
/* Actually, only for one HT device HT chain, and unitid is 0. */
-#if CONFIG_HT_CHAIN_UNITID_BASE == 0
+#if !CONFIG_HT_CHAIN_UNITID_BASE
if (offset_unitid)
return;
#endif
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index c9af7c4..7fa7384 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -33,22 +33,22 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <delay.h>
-#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
+#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
#include <device/hypertransport.h>
#endif
-#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
+#if CONFIG_PCIX_PLUGIN_SUPPORT
#include <device/pcix.h>
#endif
-#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
+#if CONFIG_PCIEXP_PLUGIN_SUPPORT
#include <device/pciexp.h>
#endif
-#if CONFIG_AGP_PLUGIN_SUPPORT == 1
+#if CONFIG_AGP_PLUGIN_SUPPORT
#include <device/agp.h>
#endif
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
+#if CONFIG_CARDBUS_PLUGIN_SUPPORT
#include <device/cardbus.h>
#endif
-#if CONFIG_PC80_SYSTEM == 1
+#if CONFIG_PC80_SYSTEM
#include <pc80/i8259.h>
#endif
#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
@@ -748,17 +748,17 @@ static struct device_operations *get_pci_bridge_ops(device_t dev)
{
unsigned int pos;
-#if CONFIG_PCIX_PLUGIN_SUPPORT == 1
+#if CONFIG_PCIX_PLUGIN_SUPPORT
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (pos) {
printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
return &default_pcix_ops_bus;
}
#endif
-#if CONFIG_AGP_PLUGIN_SUPPORT == 1
+#if CONFIG_AGP_PLUGIN_SUPPORT
/* How do I detect a PCI to AGP bridge? */
#endif
-#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
+#if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
pos = 0;
while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
u16 flags;
@@ -771,7 +771,7 @@ static struct device_operations *get_pci_bridge_ops(device_t dev)
}
}
#endif
-#if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
+#if CONFIG_PCIEXP_PLUGIN_SUPPORT
pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
if (pos) {
u16 flags;
@@ -860,7 +860,7 @@ static void set_pci_ops(struct device *dev)
goto bad;
dev->ops = get_pci_bridge_ops(dev);
break;
-#if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
+#if CONFIG_CARDBUS_PLUGIN_SUPPORT
case PCI_HEADER_TYPE_CARDBUS:
dev->ops = &default_cardbus_ops_bus;
break;
@@ -1256,7 +1256,7 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
return max;
}
-#if CONFIG_PC80_SYSTEM == 1
+#if CONFIG_PC80_SYSTEM
/**
* Assign IRQ numbers.
*
@@ -1305,7 +1305,7 @@ void pci_assign_irqs(unsigned bus, unsigned slot,
printk(BIOS_DEBUG, " Readback = %d\n", irq);
#endif
-#if CONFIG_PC80_SYSTEM == 1
+#if CONFIG_PC80_SYSTEM
/* Change to level triggered. */
i8259_configure_irq_trigger(pIntAtoD[line - 1],
IRQ_LEVEL_TRIGGERED);
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index e7933eb..fe67515 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -151,7 +151,7 @@ struct rom_header *pci_rom_load(struct device *dev,
* devices have a mismatch between the hardware and the ROM.
*/
if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 0
+#if !CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; /* Primary VGA device (device.c). */
if (dev != vga_pri) return NULL; /* Only one VGA supported. */
#endif
diff --git a/src/drivers/ati/ragexl/atyfb.h b/src/drivers/ati/ragexl/atyfb.h
index 99a87b3..557ead7 100644
--- a/src/drivers/ati/ragexl/atyfb.h
+++ b/src/drivers/ati/ragexl/atyfb.h
@@ -8,7 +8,7 @@
#define max(x,y) (x>=y)?x:y
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
/*
* Elements of the hardware specific atyfb_par structure
*/
@@ -73,7 +73,7 @@ union aty_pll {
* The hardware parameters for each card
*/
struct atyfb_par {
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
struct crtc crtc;
#endif
union aty_pll pll;
@@ -97,7 +97,7 @@ struct aty_cursor {
};
#endif
struct fb_info_aty {
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
#if PLL_CRTC_DECODE==1
struct fb_info fb_info;
#endif
diff --git a/src/drivers/ati/ragexl/mach64_ct.c b/src/drivers/ati/ragexl/mach64_ct.c
index b34be82..9b45f2a 100644
--- a/src/drivers/ati/ragexl/mach64_ct.c
+++ b/src/drivers/ati/ragexl/mach64_ct.c
@@ -284,7 +284,7 @@ int aty_var_to_pll_ct(const struct fb_info_aty *info, u32 vclk_per,
aty_calc_pll_ct(info, &pll->ct);
return 0;
}
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
#if PLL_CRTC_DECODE==1
u32 aty_pll_ct_to_var(const struct fb_info_aty *info,
const union aty_pll *pll)
diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c
index 747b343..36a0619 100644
--- a/src/drivers/ati/ragexl/xlinit.c
+++ b/src/drivers/ati/ragexl/xlinit.c
@@ -28,7 +28,7 @@
// Hence do only remove this if you fix the code.
#define CONFIG_CONSOLE_BTEXT 0
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
#define PLL_CRTC_DECODE 0
#define SUPPORT_8_BPP_ABOVE 0
@@ -393,7 +393,7 @@ static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
static void aty_set_crtc(const struct fb_info_aty *info,
const struct crtc *crtc);
static int aty_var_to_crtc(const struct fb_info_aty *info,
@@ -455,7 +455,7 @@ static struct {
/* 3D RAGE XL PCI-33/BGA */
{ 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
};
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
{
int i, size;
@@ -502,7 +502,7 @@ static void ati_ragexl_init(device_t dev)
#endif
int pll, mclk, xclk;
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
#if 0
int gtb_memsize, k;
@@ -532,7 +532,7 @@ static void ati_ragexl_init(device_t dev)
res = res->next;
}
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
info->frame_buffer = res->base;
#endif /* CONFIG_CONSOLE_BTEXT */
@@ -548,7 +548,7 @@ static void ati_ragexl_init(device_t dev)
#endif
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
#endif
@@ -581,7 +581,7 @@ found:
mclk = 63;
}
#endif
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
aty_calc_mem_refresh(info, type, xclk);
#endif /* CONFIG_CONSOLE_BTEXT */
@@ -596,7 +596,7 @@ found:
atyfb_xl_init(info);
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
@@ -803,7 +803,7 @@ found:
}
-#if CONFIG_CONSOLE_BTEXT==1
+#if CONFIG_CONSOLE_BTEXT
static int atyfb_decode_var(const struct fb_var_screeninfo *var,
struct atyfb_par *par,
diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h
index 56381e3..1e85596 100644
--- a/src/include/cpu/amd/model_fxx_rev.h
+++ b/src/include/cpu/amd/model_fxx_rev.h
@@ -2,7 +2,7 @@
int init_processor_name(void);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@@ -79,7 +79,7 @@ int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
//AMD_F0_SUPPORT
static inline int is_cpu_pre_f0(void)
{
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 2215ec7..078f2a7 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -147,7 +147,7 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
void setup_lapic(void);
-#if CONFIG_SMP == 1
+#if CONFIG_SMP
struct device;
int start_cpu(struct device *cpu);
#endif /* CONFIG_SMP */
diff --git a/src/include/delay.h b/src/include/delay.h
index 5d0dc01..0333879 100644
--- a/src/include/delay.h
+++ b/src/include/delay.h
@@ -3,7 +3,7 @@
#if !defined( __ROMCC__)
-#if CONFIG_HAVE_INIT_TIMER == 1
+#if CONFIG_HAVE_INIT_TIMER
void init_timer(void);
#else
#define init_timer() do{} while(0)
diff --git a/src/include/reset.h b/src/include/reset.h
index 3d72a8c..79bf6d5 100644
--- a/src/include/reset.h
+++ b/src/include/reset.h
@@ -4,7 +4,7 @@
#if !defined( __ROMCC__ )
/* ROMCC can't do function prototypes... */
-#if CONFIG_HAVE_HARD_RESET == 1
+#if CONFIG_HAVE_HARD_RESET
void hard_reset(void);
#else
#define hard_reset() do {} while(0)
diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h
index 8da08a2..44be4c5 100644
--- a/src/include/smp/atomic.h
+++ b/src/include/smp/atomic.h
@@ -1,7 +1,7 @@
#ifndef SMP_ATOMIC_H
#define SMP_ATOMIC_H
-#if CONFIG_SMP == 1
+#if CONFIG_SMP
#include <arch/smp/atomic.h>
#else
diff --git a/src/include/smp/spinlock.h b/src/include/smp/spinlock.h
index 1b0b4fd..87298b1 100644
--- a/src/include/smp/spinlock.h
+++ b/src/include/smp/spinlock.h
@@ -1,7 +1,7 @@
#ifndef SMP_SPINLOCK_H
#define SMP_SPINLOCK_H
-#if CONFIG_SMP == 1
+#if CONFIG_SMP
#include <arch/smp/spinlock.h>
#else /* !CONFIG_SMP */
diff --git a/src/include/watchdog.h b/src/include/watchdog.h
index 98d6d51..d626737 100644
--- a/src/include/watchdog.h
+++ b/src/include/watchdog.h
@@ -1,7 +1,7 @@
#ifndef WATCHDOG_H
#define WATCHDOG_H
-#if CONFIG_USE_WATCHDOG_ON_BOOT == 1
+#if CONFIG_USE_WATCHDOG_ON_BOOT
void watchdog_off(void);
#else
#define watchdog_off()
diff --git a/src/mainboard/advansus/a785e-i/acpi_tables.c b/src/mainboard/advansus/a785e-i/acpi_tables.c
index 9642bb4..fa93842 100644
--- a/src/mainboard/advansus/a785e-i/acpi_tables.c
+++ b/src/mainboard/advansus/a785e-i/acpi_tables.c
@@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_create_facs(facs);
/* FDAT */
-#if CONFIG_BOARD_HAS_FADT == 1
+#if CONFIG_BOARD_HAS_FADT
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
diff --git a/src/mainboard/advansus/a785e-i/get_bus_conf.c b/src/mainboard/advansus/a785e-i/get_bus_conf.c
index 5c21e09..fcf0bd9 100644
--- a/src/mainboard/advansus/a785e-i/get_bus_conf.c
+++ b/src/mainboard/advansus/a785e-i/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
@@ -141,7 +141,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index ff2d395..afa82f3 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -84,7 +84,7 @@ static void a785e_i_enable(device_t dev)
printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/advansus/a785e-i/mptable.c b/src/mainboard/advansus/a785e-i/mptable.c
index 8643320..818d4be 100644
--- a/src/mainboard/advansus/a785e-i/mptable.c
+++ b/src/mainboard/advansus/a785e-i/mptable.c
@@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h
index 5fd49d6..98e2c94 100644
--- a/src/mainboard/advansus/a785e-i/platform_cfg.h
+++ b/src/mainboard/advansus/a785e-i/platform_cfg.h
@@ -36,7 +36,7 @@
* bigger than 1M you have to set the ROM size outside CIMx module and
* before AGESA module get call.
*/
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 3a33b5f..dcc3ba5 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
-#if CONFIG_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/amd/bimini_fam10/get_bus_conf.c b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
index e53aef5..41a2fe7 100644
--- a/src/mainboard/amd/bimini_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/bimini_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
@@ -138,7 +138,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 1fd0eeb..241d905 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -134,7 +134,7 @@ static void bimini_enable(device_t dev)
printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -184,7 +184,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/bimini_fam10/mptable.c b/src/mainboard/amd/bimini_fam10/mptable.c
index ae81411..ec60b35 100644
--- a/src/mainboard/amd/bimini_fam10/mptable.c
+++ b/src/mainboard/amd/bimini_fam10/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 732e033..5980ca2 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/amd/dbm690t/get_bus_conf.c b/src/mainboard/amd/dbm690t/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/amd/dbm690t/get_bus_conf.c
+++ b/src/mainboard/amd/dbm690t/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index 2f54bfd..8841291 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -187,7 +187,7 @@ static void dbm690t_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/amd/dbm690t/mptable.c b/src/mainboard/amd/dbm690t/mptable.c
index cf98ae3..f34918f 100644
--- a/src/mainboard/amd/dbm690t/mptable.c
+++ b/src/mainboard/amd/dbm690t/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index 66637a8..459aa47 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 9d10390..360e1df 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -75,7 +75,7 @@ uint64_t uma_memory_base, uma_memory_size;
static void dinar_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Dinar Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -124,7 +124,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h
index a4f4e1a..aaab1f3 100644
--- a/src/mainboard/amd/dinar/rd890_cfg.h
+++ b/src/mainboard/amd/dinar/rd890_cfg.h
@@ -32,10 +32,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif
diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h
index b405f0e..038e7e7 100644
--- a/src/mainboard/amd/dinar/sb700_cfg.h
+++ b/src/mainboard/amd/dinar/sb700_cfg.h
@@ -40,7 +40,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index 17c985d..d35b175 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -80,7 +80,7 @@ static void inagua_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c
index b5a507f..393eb9e 100644
--- a/src/mainboard/amd/inagua/mptable.c
+++ b/src/mainboard/amd/inagua/mptable.c
@@ -87,7 +87,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h
index 2a3342c..dd0251f 100644
--- a/src/mainboard/amd/inagua/platform_cfg.h
+++ b/src/mainboard/amd/inagua/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c
index bed7606..149e163 100644
--- a/src/mainboard/amd/mahogany/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 0ccef10..989070c 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -105,7 +105,7 @@ static void mahogany_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -154,7 +154,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/mahogany/mptable.c b/src/mainboard/amd/mahogany/mptable.c
index dabd2ed..376e043 100644
--- a/src/mainboard/amd/mahogany/mptable.c
+++ b/src/mainboard/amd/mahogany/mptable.c
@@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 104652a..9d913e9 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 2cbeaf1..1f1941b 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -106,7 +106,7 @@ static void mahogany_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -155,7 +155,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index c56952e..d69c7b7 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index dce9baa..d48b69d 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/amd/persimmon/agesawrapper.c b/src/mainboard/amd/persimmon/agesawrapper.c
index e60673e..0d63abb 100644
--- a/src/mainboard/amd/persimmon/agesawrapper.c
+++ b/src/mainboard/amd/persimmon/agesawrapper.c
@@ -515,7 +515,7 @@ agesawrapper_amdinitlate (
return (UINT32)Status;
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
UINT32
agesawrapper_amdinitresume (
VOID
diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c
index 4c094ae..1d5842a 100644
--- a/src/mainboard/amd/persimmon/get_bus_conf.c
+++ b/src/mainboard/amd/persimmon/get_bus_conf.c
@@ -51,7 +51,7 @@ u32 sbdn_sb800;
static u32 get_bus_conf_done = 0;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
@@ -83,7 +83,7 @@ void get_bus_conf(void)
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
if(status)
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 9a8428e..76a9ae6 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -63,11 +63,11 @@ static void persimmon_enable(device_t dev)
* The mainboard is the first place that we get control in ramstage. Check
* for S3 resume and call the approriate AGESA/CIMx resume functions.
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
#endif
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -113,7 +113,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c
index 61ddef1..d0c31f0 100644
--- a/src/mainboard/amd/persimmon/mptable.c
+++ b/src/mainboard/amd/persimmon/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h
index 97aa47e..db3fc15 100644
--- a/src/mainboard/amd/persimmon/platform_cfg.h
+++ b/src/mainboard/amd/persimmon/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 55d0516..56a6788 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -51,7 +51,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
@@ -107,7 +107,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
else
printk(BIOS_DEBUG, "passed.\n");
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (!acpi_is_wakeup_early()) { /* Check for S3 resume */
#endif
post_code(0x40);
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
else
printk(BIOS_DEBUG, "passed.\n");
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
diff --git a/src/mainboard/amd/pistachio/get_bus_conf.c b/src/mainboard/amd/pistachio/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/amd/pistachio/get_bus_conf.c
+++ b/src/mainboard/amd/pistachio/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index d1d9a84..e5d0efa 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -257,7 +257,7 @@ static void pistachio_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -308,7 +308,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/amd/pistachio/mptable.c b/src/mainboard/amd/pistachio/mptable.c
index cf98ae3..f34918f 100644
--- a/src/mainboard/amd/pistachio/mptable.c
+++ b/src/mainboard/amd/pistachio/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 5d6e7a8..45c94c8 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -101,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
index 36b5776..d4f44c0 100644
--- a/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -192,7 +192,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c
index 4214408..866875d 100644
--- a/src/mainboard/amd/serengeti_cheetah/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 8378ca4..7378130 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -1,4 +1,4 @@
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -139,13 +139,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index b595473..da7efe6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -22,7 +22,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
index e90b348..d19b3c6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c
@@ -23,7 +23,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 29b00b2..09447a6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -255,7 +255,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index 990c8b9..ed65b34 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -82,7 +82,7 @@ static void southstation_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -129,7 +129,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c
index 99004b3..ba73ce0 100644
--- a/src/mainboard/amd/south_station/mptable.c
+++ b/src/mainboard/amd/south_station/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h
index 66aab8b..1c8506b 100644
--- a/src/mainboard/amd/south_station/platform_cfg.h
+++ b/src/mainboard/amd/south_station/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index 357bdac..e2ef3f9 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -281,7 +281,7 @@ static void tilapia_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard TILAPIA Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -331,7 +331,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index f316395..9919cce 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h
index 037ce94..4acc136 100644
--- a/src/mainboard/amd/torpedo/Oem.h
+++ b/src/mainboard/amd/torpedo/Oem.h
@@ -20,7 +20,7 @@
#define BIOS_SIZE 0x04 //04 - 1MB
#endif
#define LEGACY_FREE 0x00
-#if CONFIG_ONBOARD_USB30 == 0
+#if !CONFIG_ONBOARD_USB30
#define XHCI_SUPPORT 0x01
#endif
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 2152153..7248bfb 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -58,7 +58,7 @@ uint64_t uma_memory_base, uma_memory_size;
static void torpedo_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -107,7 +107,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c
index 936a417..9513741 100644
--- a/src/mainboard/amd/torpedo/mptable.c
+++ b/src/mainboard/amd/torpedo/mptable.c
@@ -164,7 +164,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb900, (pin))
#else
diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h
index cf31c6a..a6d02e8 100644
--- a/src/mainboard/amd/torpedo/platform_cfg.h
+++ b/src/mainboard/amd/torpedo/platform_cfg.h
@@ -39,7 +39,7 @@
#define BIOS_SIZE_4M 3
#define BIOS_SIZE_8M 7
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
@@ -311,7 +311,7 @@
#define INCHIP_USB_CINFIG 0x7F
#define INCHIP_USB_OHCI1_CINFIG 0x01
#define INCHIP_USB_OHCI2_CINFIG 0x01
-#if CONFIG_ONBOARD_USB30 == 1
+#if CONFIG_ONBOARD_USB30
#define INCHIP_USB_OHCI3_CINFIG 0x00
#else
#define INCHIP_USB_OHCI3_CINFIG 0x01
@@ -985,7 +985,7 @@
* @li <b>0</b> - Disable
* @li <b>1</b> - Enable
*/
-#if CONFIG_ONBOARD_USB30 == 1
+#if CONFIG_ONBOARD_USB30
#define SB_XHCI_SWITCH 0
#else
#define SB_XHCI_SWITCH 1
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index 800d64d..c5b481d 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -56,7 +56,7 @@ static void unionstation_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -103,7 +103,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c
index 99004b3..ba73ce0 100644
--- a/src/mainboard/amd/union_station/mptable.c
+++ b/src/mainboard/amd/union_station/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h
index 66aab8b..1c8506b 100644
--- a/src/mainboard/amd/union_station/platform_cfg.h
+++ b/src/mainboard/amd/union_station/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index c334fa5..cd08389 100644
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asrock/939a785gmh/get_bus_conf.c b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
index bed7606..149e163 100644
--- a/src/mainboard/asrock/939a785gmh/get_bus_conf.c
+++ b/src/mainboard/asrock/939a785gmh/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 945a19f..0b566e4 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -103,7 +103,7 @@ static void mb_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard 939A785GMH/128M Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -152,7 +152,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/asrock/939a785gmh/mptable.c b/src/mainboard/asrock/939a785gmh/mptable.c
index c0ca550..5b73b20 100644
--- a/src/mainboard/asrock/939a785gmh/mptable.c
+++ b/src/mainboard/asrock/939a785gmh/mptable.c
@@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 4a1b1c3..51b7519 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -169,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index 4e58324..8642e28 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -54,7 +54,7 @@ uint64_t uma_memory_base, uma_memory_size;
static void e350m1_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
uint32_t sys_mem;
@@ -101,7 +101,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c
index 7e8c947..81fe0bd 100644
--- a/src/mainboard/asrock/e350m1/mptable.c
+++ b/src/mainboard/asrock/e350m1/mptable.c
@@ -83,7 +83,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h
index 6aa31d2..7fa9c23 100644
--- a/src/mainboard/asrock/e350m1/platform_cfg.h
+++ b/src/mainboard/asrock/e350m1/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
- #if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
index 75741fd..ce1448d 100644
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ b/src/mainboard/asus/a8n_e/get_bus_conf.c
@@ -27,7 +27,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
@@ -114,7 +114,7 @@ void get_bus_conf(void)
}
}
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index b3e85b7..fcbe86d 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 47a0e65..53a1fbc 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_info("now booting... Core0 started\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 4193452..7539a80 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_info("now booting... Core0 started\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index f24c4d4..82b0636 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_info("now booting... Core0 started\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
index a39ac22..031b673 100644
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ b/src/mainboard/asus/m2n-e/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
@@ -112,7 +112,7 @@ void get_bus_conf(void)
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
}
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index e820a79..8f9089d 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -20,7 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
#endif
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
/*
* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index 614af39..c936fa9 100644
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -30,7 +30,7 @@ uint64_t uma_memory_base, uma_memory_size;
int add_mainboard_resources(struct lb_memory *mem)
{
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 9825e2b..ac88f6a 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -24,7 +24,7 @@
unsigned int get_sbdn(unsigned bus);
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... All core 0 started\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 53a3fc3..367ef3b 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -24,7 +24,7 @@
unsigned int get_sbdn(unsigned bus);
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -256,7 +256,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_INFO, "now booting... All core 0 started\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 4854208..10ecb64 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -125,7 +125,7 @@ static void m4a78em_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index a96592d..50bbfca 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index d152f71..3b68143 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -197,7 +197,7 @@ static void m4a785m_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 870af70..f0be2f7 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c
index 9642bb4..fa93842 100644
--- a/src/mainboard/asus/m5a88-v/acpi_tables.c
+++ b/src/mainboard/asus/m5a88-v/acpi_tables.c
@@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_create_facs(facs);
/* FDAT */
-#if CONFIG_BOARD_HAS_FADT == 1
+#if CONFIG_BOARD_HAS_FADT
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index 5c21e09..fcf0bd9 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
@@ -141,7 +141,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 7fa4ee7..38b9648 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -81,7 +81,7 @@ static void m5a88pm_v_enable(device_t dev)
printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -130,7 +130,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index ac8ed5e..7daa5d1 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h
index 43573f1..00f9695 100644
--- a/src/mainboard/asus/m5a88-v/platform_cfg.h
+++ b/src/mainboard/asus/m5a88-v/platform_cfg.h
@@ -36,7 +36,7 @@
* bigger than 1M you have to set the ROM size outside CIMx module and
* before AGESA module get call.
*/
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 9d8e08a..22d87b3 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -159,7 +159,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
-#if CONFIG_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/avalue/eax-785e/acpi_tables.c b/src/mainboard/avalue/eax-785e/acpi_tables.c
index 9642bb4..fa93842 100644
--- a/src/mainboard/avalue/eax-785e/acpi_tables.c
+++ b/src/mainboard/avalue/eax-785e/acpi_tables.c
@@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_create_facs(facs);
/* FDAT */
-#if CONFIG_BOARD_HAS_FADT == 1
+#if CONFIG_BOARD_HAS_FADT
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * FADT at %lx\n", current);
fadt = (acpi_fadt_t *) current;
diff --git a/src/mainboard/avalue/eax-785e/get_bus_conf.c b/src/mainboard/avalue/eax-785e/get_bus_conf.c
index 20a856e..fcf0bd9 100644
--- a/src/mainboard/avalue/eax-785e/get_bus_conf.c
+++ b/src/mainboard/avalue/eax-785e/get_bus_conf.c
@@ -23,11 +23,11 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
-#if CONFIG_AMD_SB_CIMX == 1
+#if CONFIG_AMD_SB_CIMX
#include <sb_cimx.h>
#endif
@@ -141,14 +141,14 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
apicid_sb800 = apicid_base + 0;
-#if CONFIG_AMD_SB_CIMX == 1
+#if CONFIG_AMD_SB_CIMX
sb_Late_Post();
#endif
}
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 7f55c03..52befa5 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -84,7 +84,7 @@ static void eax_785e(device_t dev)
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -133,7 +133,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/avalue/eax-785e/mptable.c b/src/mainboard/avalue/eax-785e/mptable.c
index 6f541a0..bf5a684 100644
--- a/src/mainboard/avalue/eax-785e/mptable.c
+++ b/src/mainboard/avalue/eax-785e/mptable.c
@@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
#else
diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h
index e503585..1ce1c51 100644
--- a/src/mainboard/avalue/eax-785e/platform_cfg.h
+++ b/src/mainboard/avalue/eax-785e/platform_cfg.h
@@ -37,7 +37,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index beea992..3667235 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* run _early_setup before soft-reset. */
rs780_early_setup();
-#if CONFIG_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
post_code(0x39);
diff --git a/src/mainboard/broadcom/blast/get_bus_conf.c b/src/mainboard/broadcom/blast/get_bus_conf.c
index 869f049..36959a4 100644
--- a/src/mainboard/broadcom/blast/get_bus_conf.c
+++ b/src/mainboard/broadcom/blast/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -101,7 +101,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/broadcom/blast/mptable.c b/src/mainboard/broadcom/blast/mptable.c
index 5a1bf28..d7ae6b7 100644
--- a/src/mainboard/broadcom/blast/mptable.c
+++ b/src/mainboard/broadcom/blast/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index 4dee763..df7b615 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -105,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index b961e8b..f1669bb 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -12,7 +12,7 @@
#include <delay.h>
#include <smbios.h>
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -54,7 +54,7 @@ static void cpu_pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index afad4bc..90fc25f 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -341,7 +341,7 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization();
-#if CONFIG_HAVE_ACPI_RESUME == 0
+#if !CONFIG_HAVE_ACPI_RESUME
/* When doing resume, we must not overwrite RAM */
#if CONFIG_DEBUG_RAM_SETUP
sdram_dump_mchbar_registers();
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
index 2fda606..c27dd23 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
@@ -26,7 +26,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -119,7 +119,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 0ba4c59..9c7ae9c 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -21,7 +21,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -150,13 +150,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
index 0df65c7..b264170 100644
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -117,7 +117,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 16d2453..281c768 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -153,13 +153,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gm/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 989dfb5..254df00 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -142,7 +142,7 @@ static void ma785gm_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -191,7 +191,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 68f3dcc..f118c3c 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 5747e62..8d669ba 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -252,7 +252,7 @@ static void ma785gmt_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -302,7 +302,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 68f3dcc..f118c3c 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index 1a00af6..ee353ed 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -79,7 +79,7 @@ static void ma78gm_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -128,7 +128,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 4a276fb..d7951cf 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 6c25a9e..4f90823 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index b7bbaad..9ca5792 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -100,7 +100,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 6b8972b..88b2133 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -121,12 +121,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_dl145g1_resource_map();
//setup_default_resource_map();
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
index 36852f1..b1d1b22 100644
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c
@@ -26,7 +26,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -127,7 +127,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 609432a..0b6095f 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -33,7 +33,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index a46218a..4945709 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -25,7 +25,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -163,13 +163,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index 7f4112b..f313ced 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 00234a3..5f77d03 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -33,7 +33,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 32a94d4..8235f9c 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index 5208790..b10f693 100644
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 0cb0cce..93afa39 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
+++ b/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index 4d0cd09..ef02c89 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -61,7 +61,7 @@ static void kino_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard Kino Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -110,7 +110,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index a26fbde..b007969 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index f51b3ec..4318831 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/intel/eagleheights/fadt.c b/src/mainboard/intel/eagleheights/fadt.c
index 40be3ea..c584c62 100644
--- a/src/mainboard/intel/eagleheights/fadt.c
+++ b/src/mainboard/intel/eagleheights/fadt.c
@@ -67,7 +67,7 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
fadt->dsdt = (unsigned long) dsdt;
fadt->preferred_pm_profile = 7; /* Performance Server */
fadt->sci_int = 0x9;
-#if CONFIG_HAVE_SMI_HANDLER == 1
+#if CONFIG_HAVE_SMI_HANDLER
fadt->smi_cmd = APM_CNT;
#else
fadt->smi_cmd = 0x00;
diff --git a/src/mainboard/iwill/dk8_htx/get_bus_conf.c b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
index aa6d21f..4f63ff5 100644
--- a/src/mainboard/iwill/dk8_htx/get_bus_conf.c
+++ b/src/mainboard/iwill/dk8_htx/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -191,7 +191,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/iwill/dk8_htx/mptable.c b/src/mainboard/iwill/dk8_htx/mptable.c
index 3977673..ff6e582 100644
--- a/src/mainboard/iwill/dk8_htx/mptable.c
+++ b/src/mainboard/iwill/dk8_htx/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index 5a24447..e75eb8c 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -1,4 +1,4 @@
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -103,13 +103,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index 4125c66..b8cf14f 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -1,4 +1,4 @@
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -104,13 +104,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 765114c..b0fb299 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -1,4 +1,4 @@
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -104,13 +104,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/jetway/pa78vm5/get_bus_conf.c b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
index b169775..563a87e 100644
--- a/src/mainboard/jetway/pa78vm5/get_bus_conf.c
+++ b/src/mainboard/jetway/pa78vm5/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 6d0ceba..e992f74 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -108,7 +108,7 @@ static void pa78vm5_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard PA78VM5 Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -157,7 +157,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index b8caa23..40d2d6b 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -101,7 +101,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
#else
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index ba3b208..338c7f3 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/kontron/kt690/get_bus_conf.c b/src/mainboard/kontron/kt690/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/kontron/kt690/get_bus_conf.c
+++ b/src/mainboard/kontron/kt690/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index 2e0c8e7..c2a401e 100644
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -187,7 +187,7 @@ static void kt690_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -238,7 +238,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/kontron/kt690/mptable.c b/src/mainboard/kontron/kt690/mptable.c
index 4ffba6f..bb3232a 100644
--- a/src/mainboard/kontron/kt690/mptable.c
+++ b/src/mainboard/kontron/kt690/mptable.c
@@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 621c27f..ee17208 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/msi/ms7135/get_bus_conf.c b/src/mainboard/msi/ms7135/get_bus_conf.c
index cfcce2f..fe75f78 100644
--- a/src/mainboard/msi/ms7135/get_bus_conf.c
+++ b/src/mainboard/msi/ms7135/get_bus_conf.c
@@ -27,7 +27,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -98,7 +98,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 773d93e..515f7d7 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/msi/ms7260/get_bus_conf.c b/src/mainboard/msi/ms7260/get_bus_conf.c
index fadc3fe..0f053cd 100644
--- a/src/mainboard/msi/ms7260/get_bus_conf.c
+++ b/src/mainboard/msi/ms7260/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
@@ -117,7 +117,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index b384119..1e05619 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -20,7 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -144,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
#endif
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
* setup_coherent_ht_domain, so here need to make sure last core0 is
diff --git a/src/mainboard/msi/ms9185/get_bus_conf.c b/src/mainboard/msi/ms9185/get_bus_conf.c
index 0e97de6..b20288b 100644
--- a/src/mainboard/msi/ms9185/get_bus_conf.c
+++ b/src/mainboard/msi/ms9185/get_bus_conf.c
@@ -26,7 +26,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -124,7 +124,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/msi/ms9185/mptable.c b/src/mainboard/msi/ms9185/mptable.c
index fe65d7d..c28074c 100644
--- a/src/mainboard/msi/ms9185/mptable.c
+++ b/src/mainboard/msi/ms9185/mptable.c
@@ -30,7 +30,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index a2505d6..1a72ae0 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/msi/ms9282/get_bus_conf.c b/src/mainboard/msi/ms9282/get_bus_conf.c
index 833b29b..7ce44ab 100644
--- a/src/mainboard/msi/ms9282/get_bus_conf.c
+++ b/src/mainboard/msi/ms9282/get_bus_conf.c
@@ -27,7 +27,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -118,7 +118,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index e73e5d7..46492a2 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
//wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index 746abc8..605b70e 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -116,7 +116,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS==1: apicid_base: %08x\n", apicid_base);
#else
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 0bf6d11..3bb436a 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index 83acd52..1098275 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
index 99f8431..b06f758 100644
--- a/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
+++ b/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -134,7 +134,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(2);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index 94aa14a..266e7ac 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -142,13 +142,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
index bae2782..9cdaa64 100644
--- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
+++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c
@@ -148,7 +148,7 @@ unsigned long acpi_fill_madt(unsigned long current)
/* Write SB600 IOAPIC, only one */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2,
IO_APIC_ADDR, 0);
-#if CONFIG_LINT01_CONVERSION == 0
+#if !CONFIG_LINT01_CONVERSION
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
diff --git a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
+++ b/src/mainboard/siemens/sitemp_g1p1/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 76397ab..0d7b8da 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -816,14 +816,14 @@ static void smm_lock( void )
static void init(device_t dev)
{
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
+#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
INT15_function_extensions int15_func;
#endif
printk(BIOS_DEBUG, "%s %s[%x/%x] %s\n",
dev->chip_ops->name, dev_path(dev), dev->subsystem_vendor, dev->subsystem_device, __func__);
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL == 0
+#if !CONFIG_PCI_OPTION_ROM_RUN_YABEL
if( get_option(&int15_func.regs.func00_LCD_panel_id, "lcd_panel_id") < 0 )
int15_func.regs.func00_LCD_panel_id = PANEL_TABLE_ID_NO;
int15_func.regs.func05_TV_standard = TV_MODE_NO;
@@ -853,7 +853,7 @@ static void enable_dev(device_t dev)
detect_hw_variant(dev);
update_subsystemid(dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
{
msr_t msr, msr2;
@@ -921,7 +921,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size);
diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c
index b570d45..0c61e5d 100644
--- a/src/mainboard/siemens/sitemp_g1p1/romstage.c
+++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c
@@ -258,7 +258,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/sunw/ultra40/get_bus_conf.c b/src/mainboard/sunw/ultra40/get_bus_conf.c
index bd57def..af4d6f0 100644
--- a/src/mainboard/sunw/ultra40/get_bus_conf.c
+++ b/src/mainboard/sunw/ultra40/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <stdlib.h>
@@ -254,7 +254,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(4);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 0bc8de2..1f0a395 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/supermicro/h8dme/get_bus_conf.c b/src/mainboard/supermicro/h8dme/get_bus_conf.c
index 42c4c46..53dcd72 100644
--- a/src/mainboard/supermicro/h8dme/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dme/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -141,7 +141,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 2cdc4c9..53bd7b1 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -16,7 +16,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -210,14 +210,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug_hex8(bsp_apicid);
print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
/* dump_smbus_registers(); */
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/supermicro/h8dmr/get_bus_conf.c b/src/mainboard/supermicro/h8dmr/get_bus_conf.c
index 42c4c46..53dcd72 100644
--- a/src/mainboard/supermicro/h8dmr/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -141,7 +141,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 38aef5e..bda4ed0 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -137,13 +137,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index 07350e3..0cb580c 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -115,7 +115,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 4e243c2..ddd0920 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c
index 5837349..d73e8ad 100644
--- a/src/mainboard/supermicro/h8qgi/buildOpts.c
+++ b/src/mainboard/supermicro/h8qgi/buildOpts.c
@@ -202,7 +202,7 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA h8qgi_manual_swaplist[2] =
}
};
-#if CONFIG_HT3_SUPPORT == 1
+#if CONFIG_HT3_SUPPORT
/**
* The socket and link match values are platform specific
*
@@ -439,10 +439,10 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] =
#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
/*
-#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1)
+#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
-#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1)
+#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index 675c87f..f6d437e 100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -72,7 +72,7 @@ static void h8qgi_enable(device_t dev)
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
}
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
int add_mainboard_resources(struct lb_memory *mem)
{
return 0;
diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.h b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
index 8f45019..3ba25d5 100644
--- a/src/mainboard/supermicro/h8qgi/rd890_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.h
@@ -31,10 +31,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY10
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#if CONFIG_CPU_AMD_AGESA_FAMILY15
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif
diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
index aac61ec..42cd363 100644
--- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h
+++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h
@@ -40,7 +40,7 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
#define BIOS_SIZE BIOS_SIZE_1M
#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
#define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index f03fb64..a92bf42 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -132,7 +132,7 @@ void get_bus_conf(void)
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index d9d5218..2f5be99 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -226,7 +226,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
index 6a1fd77..fe5fcde 100644
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -128,7 +128,7 @@ void get_bus_conf(void)
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index 90b5335..d0fb541 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -97,7 +97,7 @@ static void h8scm_enable(device_t dev)
/* get_ide_dma66(); */
}
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
int add_mainboard_resources(struct lb_memory *mem)
{
return 0;
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index 0c75d1a..2e50b84 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sp5100, (pin))
#else
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 70b3a04..6ad1484 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/technexion/tim5690/get_bus_conf.c b/src/mainboard/technexion/tim5690/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/technexion/tim5690/get_bus_conf.c
+++ b/src/mainboard/technexion/tim5690/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 924d09e..6350230 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -241,7 +241,7 @@ static void tim5690_enable(device_t dev)
vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO;
vgabios_init(&vbios_regs);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -290,7 +290,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/technexion/tim5690/mptable.c b/src/mainboard/technexion/tim5690/mptable.c
index 4ffba6f..bb3232a 100644
--- a/src/mainboard/technexion/tim5690/mptable.c
+++ b/src/mainboard/technexion/tim5690/mptable.c
@@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 5934938..c24e891 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -108,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/technexion/tim8690/get_bus_conf.c b/src/mainboard/technexion/tim8690/get_bus_conf.c
index 2b0fca7..d4152a1 100644
--- a/src/mainboard/technexion/tim8690/get_bus_conf.c
+++ b/src/mainboard/technexion/tim8690/get_bus_conf.c
@@ -23,7 +23,7 @@
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ void get_bus_conf(void)
}
/* I/O APICs: APIC ID Version State Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 664372d..18abbc9 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -147,7 +147,7 @@ static void tim8690_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
msr_t msr, msr2;
/* TOP_MEM: the top of DRAM below 4G */
@@ -197,7 +197,7 @@ int add_mainboard_resources(struct lb_memory *mem)
/* UMA is removed from system memory in the northbridge code, but
* in some circumstances we want the memory mentioned as reserved.
*/
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
uma_memory_base, uma_memory_size);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/mainboard/technexion/tim8690/mptable.c b/src/mainboard/technexion/tim8690/mptable.c
index 4ffba6f..bb3232a 100644
--- a/src/mainboard/technexion/tim8690/mptable.c
+++ b/src/mainboard/technexion/tim8690/mptable.c
@@ -99,7 +99,7 @@ static void *smp_write_config_table(void *v)
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
#define PCI_INT(bus, dev, fn, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin))
#else
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 97bc4e1..875321e 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched */
wait_all_core0_started();
start_other_cores();
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 08027f4..371d9a3 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index e990f4e..567b4f1 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -89,7 +89,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index c3765f2..90299a7 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -98,7 +98,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 832255c..4b52cd3 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 2d34c8b..32fc639 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 6bdb3d0..6dc62af 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c
index e4721ce..c7b62c7 100644
--- a/src/mainboard/tyan/s2881/get_bus_conf.c
+++ b/src/mainboard/tyan/s2881/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -106,7 +106,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index bba4c7e..07ac12b 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -92,7 +92,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 47c39a7..6c07965 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -5,7 +5,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -107,7 +107,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 6bdb3d0..6dc62af 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/tyan/s2885/get_bus_conf.c b/src/mainboard/tyan/s2885/get_bus_conf.c
index 5cb760d..e390f7c 100644
--- a/src/mainboard/tyan/s2885/get_bus_conf.c
+++ b/src/mainboard/tyan/s2885/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -119,7 +119,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index d6552ac..5aede1c 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -92,7 +92,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/tyan/s2891/get_bus_conf.c b/src/mainboard/tyan/s2891/get_bus_conf.c
index bbb02e9..6be68ad 100644
--- a/src/mainboard/tyan/s2891/get_bus_conf.c
+++ b/src/mainboard/tyan/s2891/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -153,7 +153,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 8cdeb85..0936481 100644
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -113,7 +113,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/tyan/s2892/get_bus_conf.c b/src/mainboard/tyan/s2892/get_bus_conf.c
index 3a45cfa..174632f 100644
--- a/src/mainboard/tyan/s2892/get_bus_conf.c
+++ b/src/mainboard/tyan/s2892/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -146,7 +146,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index 2b2d6fa..9124b99 100644
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/tyan/s2895/get_bus_conf.c b/src/mainboard/tyan/s2895/get_bus_conf.c
index 9de1629..abd6297 100644
--- a/src/mainboard/tyan/s2895/get_bus_conf.c
+++ b/src/mainboard/tyan/s2895/get_bus_conf.c
@@ -3,7 +3,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -157,7 +157,7 @@ void get_bus_conf(void)
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(4);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2912/get_bus_conf.c b/src/mainboard/tyan/s2912/get_bus_conf.c
index d16f4e6..d807358 100644
--- a/src/mainboard/tyan/s2912/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
#include <cpu/amd/amdk8_sysconf.h>
@@ -112,7 +112,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 67ce286..926521d 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -19,7 +19,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
#endif
@@ -140,13 +140,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index da0ed54..4137908 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -114,7 +114,7 @@ void get_bus_conf(void)
}
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(1);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index df571a0..c3017e5 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
diff --git a/src/mainboard/tyan/s4880/mptable.c b/src/mainboard/tyan/s4880/mptable.c
index 9111a63..dcc0fd8 100644
--- a/src/mainboard/tyan/s4880/mptable.c
+++ b/src/mainboard/tyan/s4880/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 9348f39..c697670 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -145,7 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
#endif
diff --git a/src/mainboard/tyan/s4882/mptable.c b/src/mainboard/tyan/s4882/mptable.c
index bca26a0..350b55c 100644
--- a/src/mainboard/tyan/s4882/mptable.c
+++ b/src/mainboard/tyan/s4882/mptable.c
@@ -4,7 +4,7 @@
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#endif
@@ -109,7 +109,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
apicid_base = get_apicid_base(3);
#else
apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index c916e4c..56b6325 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = setup_coherent_ht_domain();
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c
index 6e11a00..cf5ae96 100644
--- a/src/mainboard/via/epia-n/mainboard.c
+++ b/src/mainboard/via/epia-n/mainboard.c
@@ -30,7 +30,7 @@
int add_mainboard_resources(struct lb_memory *mem)
{
-#if CONFIG_IOAPIC == 1
+#if CONFIG_IOAPIC
lb_add_memory_range(mem, LB_MEM_RESERVED,
IO_APIC_ADDR, 0x1000);
lb_add_memory_range(mem, LB_MEM_RESERVED,
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index ee02f0d..7b73987 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -31,7 +31,7 @@
#include <cpu/x86/lapic.h>
#include <cbmem.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <pc80/mc146818rtc.h>
#endif
@@ -70,7 +70,7 @@ static dram_base_mask_t get_dram_base_mask(u32 nodeid)
dram_base_mask_t d;
dev = __f1_dev[0];
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
/* I will use ext space only for simple */
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
@@ -551,7 +551,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -577,7 +577,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -594,7 +594,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -677,7 +677,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -806,7 +806,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -908,7 +908,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -926,7 +926,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -939,7 +939,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -1054,10 +1054,10 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1079,19 +1079,19 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1101,7 +1101,7 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1121,7 +1121,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
for (reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// all nodes
for (i = 0; i< sysconf.nodes; i++) {
int index;
@@ -1270,7 +1270,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1376,7 +1376,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index a3afecb..efc0a48 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -222,7 +222,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam12_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -248,7 +248,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -265,7 +265,7 @@ static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -338,7 +338,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -525,7 +525,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
//- pci_domain_read_resources(dev);
struct resource *resource;
@@ -574,7 +574,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " amsr - incoming dev = %08lx\n",dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -587,7 +587,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for(link = dev->link_list; link; link = link->next) {
@@ -711,10 +711,10 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
ram_resource(dev, idx, basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -740,12 +740,12 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
0, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %x.\n",uma_memory_base);
#else
@@ -758,7 +758,7 @@ printk(BIOS_DEBUG, "adsr: mmio_basek=%08x, basek=%08x, limitk=%08x\n", mmio_bas
printk(BIOS_DEBUG, " adsr - mmio_basek = %x.\n",mmio_basek);
printk(BIOS_DEBUG, " adsr - high_tables_size = %x.\n",high_tables_size);
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
add_uma_resource(dev, 7);
#endif
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 2647814..f7c3b8e 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -210,7 +210,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam14_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
} else
@@ -235,7 +235,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -252,7 +252,7 @@ static void amdfam14_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if ((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -326,7 +326,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -508,7 +508,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -538,7 +538,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, "\nFam14h - domain_set_resources.\n");
printk(BIOS_DEBUG, " amsr - incoming dev = %08x\n", (u32) dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -551,7 +551,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
printk(BIOS_DEBUG, "adsr - CONFIG_PCI_64BIT_PREF_MEM is true.\n");
for (link = dev->link_list; link; link = link->next) {
@@ -685,10 +685,10 @@ static void domain_set_resources(device_t dev)
pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -712,13 +712,13 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | 0), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,
mmio_basek, basek, limitk);
if (high_tables_base == 0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, " adsr - uma_memory_base = %llx.\n", uma_memory_base);
#else
@@ -732,7 +732,7 @@ static void domain_set_resources(device_t dev)
printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n",
high_tables_size);
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "adsr - adding uma resource.\n");
add_uma_resource(dev, 7);
#endif
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index d1a322c..130086e 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -406,7 +406,7 @@ static void create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -540,7 +540,7 @@ static void domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
@@ -626,7 +626,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
}
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
{
@@ -644,7 +644,7 @@ static void add_uma_resource(struct device *dev, int index)
static void domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -657,7 +657,7 @@ static void domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for (link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -773,10 +773,10 @@ static void domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -798,19 +798,19 @@ static void domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -820,7 +820,7 @@ static void domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1022,7 +1022,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index 9951806..2bd0411 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -976,7 +976,7 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07
#include "raminit.h"
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
//struct definitions
@@ -1034,12 +1034,12 @@ struct nodes_info_t {
} __attribute__((packed));
/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
//#define MEM_CS_COPY 1
#define MEM_CS_COPY NODE_NUMS
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if !CONFIG_MEM_TRAIN_SEQ
#define DQS_DELAY_COPY NODE_NUMS
#else
// #define DQS_DELAY_COPY 1
@@ -1102,7 +1102,7 @@ struct sys_info {
device_t get_node_pci(u32 nodeid, u32 fn);
#endif
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
#ifdef __PRE_RAM__
static void soft_reset(void);
diff --git a/src/northbridge/amd/amdfam10/conf.c b/src/northbridge/amd/amdfam10/conf.c
index adfff0f..d8c161f 100644
--- a/src/northbridge/amd/amdfam10/conf.c
+++ b/src/northbridge/amd/amdfam10/conf.c
@@ -38,7 +38,7 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
dev = __f1_dev[0];
#endif
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8]
d.mask = pci_read_config32(dev, 0x114); // enable is bit 0
@@ -61,12 +61,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
return d;
}
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
{
u32 i;
device_t dev;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
u32 d_base_i, d_base_d, d_mask_i, d_mask_d;
d_base_i = nodeid | (0<<28);
@@ -95,7 +95,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
dev = __f1_dev[i];
#endif
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// I will use ext space only for simple
pci_write_config32(dev, 0x110, d_base_i);
pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8];
@@ -120,7 +120,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes)
}
#endif
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
{
device_t dev;
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 2dc5427..c6f7c78 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -33,7 +33,7 @@ static inline void print_debug_addr(const char *str, void *val)
static void print_debug_pci_dev(u32 dev)
{
-#if CONFIG_PCI_BUS_SEGN_BITS==0
+#if !CONFIG_PCI_BUS_SEGN_BITS
printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
#else
printk(BIOS_DEBUG, "PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7);
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index 58f2cdd..bbf6b86 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -21,7 +21,7 @@
// mmconf is not ready yet
static void set_bsp_node_CHtExtNodeCfgEn(void)
{
-#if CONFIG_EXT_RT_TBL_SUPPORT == 1
+#if CONFIG_EXT_RT_TBL_SUPPORT
u32 dword;
dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68);
dword |= (1<<27) | (1<<25);
@@ -112,7 +112,7 @@ static void enumerate_ht_chain(void)
real_last_pos = pos;
ht_dev_num++ ;
#endif
- #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0
+ #if !CONFIG_HT_CHAIN_END_UNITID_BASE
if (!next_unitid)
goto out;
#endif
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 89bd673..0e80c71 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -31,7 +31,7 @@
#include <cpu/x86/lapic.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <cpu/amd/multicore.h>
#include <pc80/mc146818rtc.h>
#endif
@@ -161,7 +161,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
#endif
u32 max_devfn;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
if(is_sublink1) {
u32 regpos;
u32 reg;
@@ -192,7 +192,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 l
*/
ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
-#if CONFIG_EXT_CONF_SUPPORT == 0
+#if !CONFIG_EXT_CONF_SUPPORT
if(ht_c_index>=4) return max;
#endif
@@ -316,7 +316,7 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max)
#endif
offset_unitid = 0;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if((nodeid == 0) && (sblink == link->link_num))
#endif
offset_unitid = 1;
@@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource = amdfam10_find_iopair(dev, nodeid, link);
if (resource) {
u32 align;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
align = 8;
}
@@ -460,7 +460,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -477,7 +477,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
if((resource->index & 0x1fff) == 0x1110) { // ext
normalize_resource(resource);
}
@@ -560,7 +560,7 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -664,7 +664,7 @@ static void amdfam10_domain_read_resources(device_t dev)
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
-#if CONFIG_PCI_64BIT_PREF_MEM == 0
+#if !CONFIG_PCI_64BIT_PREF_MEM
pci_domain_read_resources(dev);
#else
struct bus *link;
@@ -762,7 +762,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
// Does it make sense not to?
-#if CONFIG_AMDMCT == 0
+#if !CONFIG_AMDMCT
static void disable_hoist_memory(unsigned long hole_startk, int node_id)
{
int i;
@@ -843,11 +843,11 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -865,7 +865,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdfam10_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -878,7 +878,7 @@ static void amdfam10_domain_set_resources(device_t dev)
u32 reset_memhole = 1;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
for(link = dev->link_list; link; link = link->next) {
/* Now reallocate the pci resources memory with the
@@ -960,7 +960,7 @@ static void amdfam10_domain_set_resources(device_t dev)
reset_memhole = 0;
}
- #if CONFIG_AMDMCT == 0
+ #if !CONFIG_AMDMCT
//mmio_basek = 3*1024*1024; // for debug to meet boundary
if(reset_memhole) {
@@ -975,7 +975,7 @@ static void amdfam10_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
- #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
// We need to double check if the mmio_basek is valid for hole
// setting, if it is equal to basek, we need to decrease it some
resource_t basek_pri;
@@ -1031,10 +1031,10 @@ static void amdfam10_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1045,7 +1045,7 @@ static void amdfam10_domain_set_resources(device_t dev)
}
#endif
}
- #if CONFIG_AMDMCT == 0
+ #if !CONFIG_AMDMCT
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole) {
struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
@@ -1067,19 +1067,19 @@ static void amdfam10_domain_set_resources(device_t dev)
}
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1089,7 +1089,7 @@ static void amdfam10_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
@@ -1109,7 +1109,7 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// all nodes
for(i = 0; i< sysconf.nodes; i++) {
int index;
@@ -1187,7 +1187,7 @@ static void sysconf_init(device_t dev) // first node
sysconf.bsp_apicid = lapicid();
sysconf.apicid_offset = sysconf.bsp_apicid;
-#if (CONFIG_ENABLE_APIC_EXT_ID == 1)
+#if CONFIG_ENABLE_APIC_EXT_ID
if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
{
sysconf.enabled_apic_ext_id = 1;
@@ -1265,7 +1265,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
}
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1371,7 +1371,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
* otherwise the device under it will not be scanned
*/
int linknum;
-#if CONFIG_HT3_SUPPORT==1
+#if CONFIG_HT3_SUPPORT
linknum = 8;
#else
linknum = 4;
diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c
index c48fca6..f1f22cb 100644
--- a/src/northbridge/amd/amdfam10/reset_test.c
+++ b/src/northbridge/amd/amdfam10/reset_test.c
@@ -127,7 +127,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b
}
}
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
// let's check that in extend space
// use the nodeid extend space to find out the bus for the linkn
u32 tempreg;
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index 32908c4..ff444d5 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -28,7 +28,7 @@
*/
/* Single CPU system? */
-#if (CONFIG_MAX_PHYSICAL_CPUS == 1)
+#if CONFIG_MAX_PHYSICAL_CPUS
#define HT_BUILD_NC_ONLY 1
#endif
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index e353edc..5aa3b31 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -2,7 +2,7 @@
#define AMDK8_H
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
#include "f.h"
#else
#include "pre_f.h"
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index a262686..636114d 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -160,7 +160,7 @@ static void disable_probes(void)
#if 0
static void enable_apic_ext_id(u8 node)
{
-#if CONFIG_ENABLE_APIC_EXT_ID==1
+#if CONFIG_ENABLE_APIC_EXT_ID
#warning "FIXME Is the right place to enable apic ext id here?"
u32 val;
@@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos)
freq_cap = pci_read_config16(dev, pos);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
-#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
- #if CONFIG_K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_HT_FREQ_1G_SUPPORT
+ #if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0())
#endif
{
@@ -665,7 +665,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
print_spew("Enabling UP settings\n");
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
#endif
@@ -1574,7 +1574,7 @@ static void clear_dead_routes(unsigned nodes)
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
static unsigned verify_dualcore(unsigned nodes)
{
unsigned node, totalcpus, tmp;
@@ -1593,10 +1593,10 @@ static unsigned verify_dualcore(unsigned nodes)
static void coherent_ht_finalize(unsigned nodes)
{
unsigned node;
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
int rev_a0;
#endif
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
unsigned total_cpus;
if (read_option(multi_core, 0) == 0) { /* multi_core */
@@ -1614,7 +1614,7 @@ static void coherent_ht_finalize(unsigned nodes)
*/
print_spew("coherent_ht_finalize\n");
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
rev_a0 = is_cpu_rev_a0();
#endif
for (node = 0; node < nodes; node++) {
@@ -1625,7 +1625,7 @@ static void coherent_ht_finalize(unsigned nodes)
/* Set the Total CPU and Node count in the system */
val = pci_read_config32(dev, 0x60);
val &= (~0x000F0070);
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
#else
val |= ((nodes-1)<<16)|((nodes-1)<<4);
@@ -1645,7 +1645,7 @@ static void coherent_ht_finalize(unsigned nodes)
(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (rev_a0) {
pci_write_config32(dev, 0x94, 0);
pci_write_config32(dev, 0xb4, 0);
@@ -1665,7 +1665,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
device_t dev;
uint32_t cmd;
dev = NODE_MC(node);
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Errata 66
@@ -1710,7 +1710,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
#endif
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
/* I can't touch this msr on early buggy cpus, and cannot apply either 169 or 131 */
if (!is_cpu_pre_b3())
#endif
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index fd9fe60..4f9d8ca 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -57,7 +57,7 @@ static void dump_pci_device(unsigned dev)
print_debug("\n");
}
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index);
static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index f57eb5b..ee1945a 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -67,7 +67,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid
device_t dev;
//actually, only for one HT device HT chain, and unitid is 0
-#if CONFIG_HT_CHAIN_UNITID_BASE == 0
+#if !CONFIG_HT_CHAIN_UNITID_BASE
if(offset_unitid) {
return;
}
@@ -136,8 +136,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
/* AMD K8 Unsupported 1Ghz? */
if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
- #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if CONFIG_K8_HT_FREQ_1G_SUPPORT
+ #if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_e0()) { // only E0 later support 1GHz
freq_cap &= ~(1 << HT_FREQ_1000Mhz);
}
@@ -149,7 +149,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
-#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 == 1
+#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
freq_cap &= 0x3f;
printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
#endif
@@ -539,7 +539,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
unsigned devn = 1;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if(i==0) // to check if it is sb ht chain
#endif
devn = CONFIG_HT_CHAIN_UNITID_BASE;
@@ -671,7 +671,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if(i==0) // to check if it is sb ht chain
#endif
offset_unitid = 1;
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 7ba2b90..cc69883 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -124,7 +124,7 @@ static void misc_control_init(struct device *dev)
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd );
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
/* Errata 58
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 90b4ebf..5eeeda2 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -20,7 +20,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/amd/multicore.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
#include <pc80/mc146818rtc.h>
#endif
@@ -256,7 +256,7 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max)
#endif
offset_unitid = 0;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
- #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+ #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
if((nodeid == 0) && (sblink == link->link_num))
#endif
offset_unitid = 1;
@@ -494,7 +494,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS
extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
@@ -635,7 +635,7 @@ static void amdk8_domain_read_resources(device_t dev)
pci_domain_read_resources(dev);
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
/* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL;
@@ -818,11 +818,11 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
}
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
static void add_uma_resource(struct device *dev, int index)
@@ -840,7 +840,7 @@ static void add_uma_resource(struct device *dev, int index)
static void amdk8_domain_set_resources(device_t dev)
{
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
struct resource *io, *mem1, *mem2;
struct resource *res;
#endif
@@ -857,7 +857,7 @@ static void amdk8_domain_set_resources(device_t dev)
io = find_resource(dev, 0);
io->base = DEVICE_IO_START;
#endif
-#if CONFIG_PCI_64BIT_PREF_MEM == 1
+#if CONFIG_PCI_64BIT_PREF_MEM
/* Now reallocate the pci resources memory with the
* highest addresses I can manage.
*/
@@ -927,7 +927,7 @@ static void amdk8_domain_set_resources(device_t dev)
* if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole.
* otherwise We reset the hole to the mmio_basek
*/
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
if (!is_cpu_pre_e0()) {
#endif
@@ -947,7 +947,7 @@ static void amdk8_domain_set_resources(device_t dev)
disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id);
}
- #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+ #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
u32 basek_pri;
for (i = 0; i < fx_devs; i++) {
@@ -968,7 +968,7 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_K8_REV_F_SUPPORT == 0
+#if !CONFIG_K8_REV_F_SUPPORT
} // is_cpu_pre_e0
#endif
@@ -997,7 +997,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
if ((uma_memory_base >> 10) < mmio_basek)
printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
@@ -1014,10 +1014,10 @@ static void amdk8_domain_set_resources(device_t dev)
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
@@ -1030,7 +1030,7 @@ static void amdk8_domain_set_resources(device_t dev)
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if(reset_memhole)
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
if(!is_cpu_pre_e0() )
#endif
sizek += hoist_memory(mmio_basek,i);
@@ -1049,7 +1049,7 @@ static void amdk8_domain_set_resources(device_t dev)
/* If sizek == 0, it was split at mmio_basek without a hole.
* Don't create an empty ram_resource.
*/
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
/* Deduct uma memory before reporting because
* this is what the mtrr code expects */
sizek -= uma_memory_size / 1024;
@@ -1057,12 +1057,12 @@ static void amdk8_domain_set_resources(device_t dev)
if (sizek)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
#else
high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
@@ -1072,7 +1072,7 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
}
-#if CONFIG_GFXUMA == 1
+#if CONFIG_GFXUMA
add_uma_resource(dev, 7);
#endif
assign_resources(dev->link_list);
@@ -1179,7 +1179,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
sysconf.apicid_offset = bsp_apicid;
disable_siblings = !CONFIG_LOGICAL_CPUS;
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
get_option(&disable_siblings, "multi_core");
#endif
@@ -1248,7 +1248,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
// That is the typical case
if(j == 0 ){
- #if CONFIG_K8_REV_F_SUPPORT == 0
+ #if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 9cb7c60..7db338b 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -2289,7 +2289,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk(BIOS_SPEW, "Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
* we need to decrease it.
@@ -2348,7 +2348,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
u32 whatWait = 0;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 33df485..af3a324 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -2965,7 +2965,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK;
printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk);
-#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
+#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;
@@ -3009,7 +3009,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
}
#endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include "exit_from_self.c"
#endif
@@ -3017,7 +3017,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
int i;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int suspend = acpi_is_wakeup_early();
#else
int suspend = 0;
@@ -3190,7 +3190,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
}
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if !CONFIG_MEM_TRAIN_SEQ
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
dqs_timing(controllers, ctrl, tsc0, sysinfo);
#else
@@ -3210,7 +3210,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
dqs_timing(i, &ctrl[i], sysinfo, 1);
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
break; // only train the first node with ram
#endif
}
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 8ddd44f..c7f9e3e 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -1717,7 +1717,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
return reg;
}
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
{
msr_t msr;
@@ -1804,7 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
}
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
static unsigned get_htic_bit(unsigned i, unsigned bit)
{
uint32_t dword;
@@ -1826,9 +1826,9 @@ static void set_sysinfo_in_ram(unsigned val)
set_htic_bit(0, val, 9);
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if !CONFIG_MEM_TRAIN_SEQ
static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
{
u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
@@ -1865,7 +1865,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
return pos;
}
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if !CONFIG_MEM_TRAIN_SEQ
static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
{
/* 30 bytes per channel */
@@ -1914,7 +1914,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev)
}
#endif
-#if CONFIG_MEM_TRAIN_SEQ == 0
+#if !CONFIG_MEM_TRAIN_SEQ
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo)
#else
@@ -1981,7 +1981,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
printk(BIOS_DEBUG, " done\n");
sysinfo->mem_trained[i]=1;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
dqs_save_MC_NVRAM((ctrl+i)->f2);
#endif
}
@@ -2013,7 +2013,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
if(sysinfo->mem_trained[i] != 0x80) return;
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
//need to enable mtrr, so dqs training could access the test address
setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k);
#endif
@@ -2059,7 +2059,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
}
out:
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
clear_mtrr_dqs(sysinfo->tom2_k);
#endif
@@ -2076,7 +2076,7 @@ out:
}
#endif
-#if CONFIG_MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ
static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox)
{
dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy
@@ -2103,7 +2103,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
#endif
set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
- #if CONFIG_AP_CODE_IN_CAR == 0
+ #if !CONFIG_AP_CODE_IN_CAR
printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
train_ram(nodeid, sysinfo, sysinfox);
#else
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 4af75fd..00b1555 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -64,14 +64,14 @@ static u16 mctGet_NVbits(u8 index)
//val = 2; /* S4 (Unbuffered SO-DIMMS) */
break;
case NV_BYPMAX:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 4;
#elif (CONFIG_GFXUMA == 1)
val = 7;
#endif
break;
case NV_RDWRQBYP:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 2;
#elif (CONFIG_GFXUMA == 1)
val = 3;
@@ -113,7 +113,7 @@ static u16 mctGet_NVbits(u8 index)
//val = 1; /* Enable */
break;
case NV_BurstLen32:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0; /* 64 byte mode */
#elif (CONFIG_GFXUMA == 1)
val = 1; /* 32 byte mode */
@@ -132,14 +132,14 @@ static u16 mctGet_NVbits(u8 index)
//val = 1; /* enable */
break;
case NV_BottomIO:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
#elif (CONFIG_GFXUMA == 1)
val = 0xC0; /* address bits [31:24] */
#endif
break;
case NV_BottomUMA:
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
val = 0xE0; /* address bits [31:24] */
#elif (CONFIG_GFXUMA == 1)
val = 0xC0; /* address bits [31:24] */
diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index abbc855..5c59f73 100644
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -66,7 +66,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -113,7 +113,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c
index f567766..8da37b4 100644
--- a/src/northbridge/amd/gx2/northbridge.c
+++ b/src/northbridge/amd/gx2/northbridge.c
@@ -273,7 +273,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -294,7 +294,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 61f3afe..9ceceb8 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -372,7 +372,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_AMD_LXBRIDGE,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -393,7 +393,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index e6e955f..1fa77d7 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -9,7 +9,7 @@
#include <bitops.h>
#include "chip.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 6a533cd..9046f43 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -10,7 +10,7 @@
#include "chip.h"
#include "e7505.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -90,7 +90,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c
index 49c8ba3..3b92aa8 100644
--- a/src/northbridge/intel/e7520/northbridge.c
+++ b/src/northbridge/intel/e7520/northbridge.c
@@ -16,7 +16,7 @@
static unsigned int max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c
index 5e9f9c5..ab88899 100644
--- a/src/northbridge/intel/e7525/northbridge.c
+++ b/src/northbridge/intel/e7525/northbridge.c
@@ -16,7 +16,7 @@
static unsigned int max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -108,7 +108,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index acd4c3c..db35b85 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -37,7 +37,7 @@
static u32 max_bus;
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -129,7 +129,7 @@ static void pci_domain_set_resources(device_t dev)
(remaplimitk + 64*1024) - remapbasek);
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 926d5b3..050df95 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1197,7 +1197,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
-#if CONFIG_CACHE_AS_RAM == 0
+#if !CONFIG_CACHE_AS_RAM
cache_lbmem(MTRR_TYPE_WRBACK);
#endif
}
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 136755e..18e5716 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -33,7 +33,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7190,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -72,7 +72,7 @@ static void i440bx_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c
index 73be101..f34b5ab 100644
--- a/src/northbridge/intel/i440lx/northbridge.c
+++ b/src/northbridge/intel/i440lx/northbridge.c
@@ -62,7 +62,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7180,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -101,7 +101,7 @@ static void i440lx_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c
index 3434c6d..78e3728 100644
--- a/src/northbridge/intel/i82810/northbridge.c
+++ b/src/northbridge/intel/i82810/northbridge.c
@@ -83,7 +83,7 @@ static int translate_i82810_to_mb[] = {
/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
index dea05db..93bdc28 100644
--- a/src/northbridge/intel/i82830/northbridge.c
+++ b/src/northbridge/intel/i82830/northbridge.c
@@ -64,7 +64,7 @@ int add_northbridge_resources(struct lb_memory *mem)
return 0;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
@@ -116,7 +116,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index 53f5997..b59ba50 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -53,7 +53,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x3580,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
@@ -109,7 +109,7 @@ static void pci_domain_set_resources(device_t dev)
/* ram_resource(dev, idx++, 1024, tolmk - 1024); */
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index a10bb4a..40b1aaa 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -93,7 +93,7 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -181,7 +181,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index b1f7c72..b2baaa3 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -143,7 +143,7 @@ static void add_fixed_resources(struct device *dev, int index)
}
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -267,7 +267,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index 7b7c67b..57245b6 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -105,7 +105,7 @@ static void add_fixed_resources(struct device *dev, int index)
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -192,7 +192,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables. */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c
index 48d830c..250ace0 100644
--- a/src/northbridge/rdc/r8610/northbridge.c
+++ b/src/northbridge/rdc/r8610/northbridge.c
@@ -32,7 +32,7 @@
#include <smbios.h>
#include "chip.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -69,7 +69,7 @@ static void cpu_pci_domain_set_resources(device_t dev)
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI, PIRQ and MP tables */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c
index 2cc331b..74e0edf 100644
--- a/src/northbridge/via/cn400/northbridge.c
+++ b/src/northbridge/via/cn400/northbridge.c
@@ -177,7 +177,7 @@ static void ram_reservation(device_t dev, unsigned long index,
}
#endif
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -207,7 +207,7 @@ static void cn400_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
/* Locate the High Tables at the Top of Low Memory below the Video RAM */
high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c
index 6400e22..ced4c2f 100644
--- a/src/northbridge/via/cn700/northbridge.c
+++ b/src/northbridge/via/cn700/northbridge.c
@@ -97,7 +97,7 @@ static const struct pci_driver memctrl_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -138,7 +138,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c
index 9e30298..4fca723 100644
--- a/src/northbridge/via/cx700/northbridge.c
+++ b/src/northbridge/via/cx700/northbridge.c
@@ -32,7 +32,7 @@
#include "chip.h"
#include "northbridge.h"
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -74,7 +74,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk -= 1024; // TOP 1M SM Memory
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c
index 3a7ada5..92adf32 100644
--- a/src/northbridge/via/vt8601/northbridge.c
+++ b/src/northbridge/via/vt8601/northbridge.c
@@ -45,7 +45,7 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x0601, /* 0x8601 is the AGP bridge? */
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -89,7 +89,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c
index 19f14d5..5ea2212 100644
--- a/src/northbridge/via/vt8623/northbridge.c
+++ b/src/northbridge/via/vt8623/northbridge.c
@@ -105,7 +105,7 @@ static const struct pci_driver agp_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_8633_1,
};
-#if CONFIG_WRITE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES
#include <cbmem.h>
#endif
@@ -149,7 +149,7 @@ static void pci_domain_set_resources(device_t dev)
tolmk = tomk;
}
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n",
diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c
index 5e82262..f4798c9 100644
--- a/src/northbridge/via/vx800/examples/chipset_init.c
+++ b/src/northbridge/via/vx800/examples/chipset_init.c
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include <arch/acpi.h>
#endif
#include "../vx800.h"
@@ -607,7 +607,7 @@ void init_VIA_chipset(void)
void hardwaremain(int boot_complete)
{
struct lb_memory *lb_mem;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
void *wake_vec;
#endif
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index d5b1c18..df57a7e 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -89,7 +89,7 @@ static int lsmbus_block_write(device_t dev, uint8_t cmd, u8 bytes, const u8 *buf
}
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
unsigned pm_base;
#endif
@@ -162,7 +162,7 @@ static void acpi_init(struct device *dev)
(on*12)+(on>>1),(on&1)*5);
}
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
#endif
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
index 401c039..ce7707b 100644
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ b/src/southbridge/amd/cimx/sb700/bootblock.c
@@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
/* Data */
#define UART_RBR 0x00
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index c899320..3f647c8 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -31,7 +31,7 @@
#include "smbus.h"
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
index 632e4cd..8e62048 100644
--- a/src/southbridge/amd/cimx/sb700/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h
@@ -40,7 +40,7 @@ void sb_Late_Post(void);
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
void sb7xx_51xx_disable_wideio(u8 wio_index);
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number, called by finalize_node_setup()
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
index 7dc752a..22d7724 100644
--- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h
@@ -158,7 +158,7 @@ typedef union _PCI_ADDR {
#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h"
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
#include "spi.h"
#endif
diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c
index 2b73155..71fea67 100644
--- a/src/southbridge/amd/cimx/sb800/cfg.c
+++ b/src/southbridge/amd/cimx/sb800/cfg.c
@@ -26,7 +26,7 @@
#include <arch/io.h>
#include <arch/acpi.h>
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_get_sleep_type(void)
{
u16 tmp = inw(PM1_CNT_BLK_ADDRESS);
@@ -75,7 +75,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config)
if (!sb_config)
return;
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_get_sleep_type() == 3)
sb_config->S3Resume = 1;
#endif
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index f692897..c0f8533 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -30,7 +30,7 @@
#include "cbmem.h"
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
@@ -82,7 +82,7 @@ void sb800_clk_output_48Mhz(void)
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void)
{
return (acpi_get_sleep_type() == 3);
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c69782b..0ce82b3 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -161,7 +161,7 @@ static const struct pci_driver raid5_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5,
};
-#if CONFIG_USBDEBUG == 1
+#if CONFIG_USBDEBUG
static void usb_set_resources(struct device *dev)
{
struct resource *res;
@@ -480,7 +480,7 @@ static void sb800_enable(device_t dev)
/* call the CIMX entry at the last sb800 device,
* so make sure the mainboard devicetree is complete
*/
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3)
sb_Before_Pci_Init();
else
diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h
index 5e510de..9916c81 100644
--- a/src/southbridge/amd/cimx/sb800/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h
@@ -40,7 +40,7 @@ int acpi_is_wakeup_early(void);
*/
void sb800_clk_output_48Mhz(void);
-#if CONFIG_RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
/**
* @brief Get SouthBridge device number, called by finalize_node_setup()
* @param[in] bus target bus number
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index e84743b..61c3c3e 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -22,7 +22,7 @@
#include <arch/romcc_io.h>
-#if CONFIG_CONSOLE_POST == 1
+#if CONFIG_CONSOLE_POST
/* Data */
#define UART_RBR 0x00
diff --git a/src/southbridge/amd/cs5530/vga.c b/src/southbridge/amd/cs5530/vga.c
index 4a26251..56bea45 100644
--- a/src/southbridge/amd/cs5530/vga.c
+++ b/src/southbridge/amd/cs5530/vga.c
@@ -41,7 +41,7 @@
#include <cpu/amd/gx1def.h>
#include <delay.h>
-#if CONFIG_GX1_VIDEO == 1
+#if CONFIG_GX1_VIDEO
/*
* Some register descriptions that are no listed in cpu/amd/gx1def.h
*/
@@ -397,7 +397,7 @@ static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
}
-#if CONFIG_SPLASH_GRAPHIC == 1
+#if CONFIG_SPLASH_GRAPHIC
/*
* This bitmap file must provide:
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index 5d816e5..9eb47bb 100644
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -27,7 +27,7 @@
static void ht_dev_set_resources(device_t dev)
{
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
unsigned reg;
device_t k8_f1;
resource_t rbase, rend;
@@ -86,7 +86,7 @@ static void ht_dev_set_resources(device_t dev)
static void ht_dev_read_resources(device_t dev)
{
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
struct resource *res;
printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
@@ -95,7 +95,7 @@ static void ht_dev_read_resources(device_t dev)
pci_dev_read_resources(dev);
-#if CONFIG_EXT_CONF_SUPPORT == 1
+#if CONFIG_EXT_CONF_SUPPORT
/* Add an MMCONFIG resource. */
res = new_resource(dev, 0x1C);
res->base = EXT_CONF_BASE_ADDRESS;
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 8adf1f6..0540823 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -101,7 +101,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
}
}
/* family 10 only, for reg > 0xFF */
-#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
+#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val)
{
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 29a6394..e8d4596 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -659,7 +659,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
pointer = (u32 *)&vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
{
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
*GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i;
@@ -775,7 +775,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t nb_dev = dev_find_slot(0, 0);
msr_t sysmem;
-#if (CONFIG_GFXUMA == 0)
+#if !CONFIG_GFXUMA
u32 FB_Start, FB_End;
#endif
@@ -818,7 +818,7 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x25, 0xffffffff, 0x111f111f);
set_htiu_enable_bits(nb_dev, 0x37, 1<<24, 1<<24);
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
/* GFX_InitUMA. */
/* Copy CPU DDR Controller to NB MC. */
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c
index 717aeab..9b153aa 100644
--- a/src/southbridge/amd/rs780/rs780.c
+++ b/src/southbridge/amd/rs780/rs780.c
@@ -220,7 +220,7 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
/* Program Straps. */
romstrap2 = 1 << 26; // enables audio function
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
extern uint64_t uma_memory_size;
// bits 7-9: aperture size
// 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
diff --git a/src/southbridge/amd/sb600/ide.c b/src/southbridge/amd/sb600/ide.c
index e38e83f..3fa31ea 100644
--- a/src/southbridge/amd/sb600/ide.c
+++ b/src/southbridge/amd/sb600/ide.c
@@ -45,7 +45,7 @@ static void ide_init(struct device *dev)
dword |= 1 << 2;
pci_write_config16(dev, 0x4, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 2dc84d8..c890ad9 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -715,7 +715,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void)
{
u16 tmp;
diff --git a/src/southbridge/amd/sb700/ide.c b/src/southbridge/amd/sb700/ide.c
index 5f415fb..19d4ed5 100644
--- a/src/southbridge/amd/sb700/ide.c
+++ b/src/southbridge/amd/sb700/ide.c
@@ -60,7 +60,7 @@ static void ide_init(struct device *dev)
pci_write_config8(sm_dev, 0xAD, byte);
}
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 5dd7d69..c968927 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -73,7 +73,7 @@ static void lpc_init(device_t dev)
/* hack, but the whole sb700 startup lacks any device which
is doing the acpi init */
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
{
extern u8 acpi_slp_type;
u16 tmp = inw(ACPI_PM1_CNT_BLK);
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 165c72d..d358ee8 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,7 +75,7 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev);
#endif
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
int acpi_is_wakeup_early(void);
#endif
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 50f4ff7..a85f490 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -665,7 +665,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
return nvram_pos;
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
static int acpi_is_wakeup_early(void)
{
u16 tmp;
diff --git a/src/southbridge/amd/sb800/ide.c b/src/southbridge/amd/sb800/ide.c
index eb287f2..a63878b 100644
--- a/src/southbridge/amd/sb800/ide.c
+++ b/src/southbridge/amd/sb800/ide.c
@@ -58,7 +58,7 @@ static void ide_init(struct device *dev)
pci_write_config8(dev, 0xAD, byte);
}
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index 387c402..0fa9a4e 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -26,7 +26,7 @@
static void nic_init(struct device *dev)
{
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);// it will init option rom
#endif
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 65af02a..b4d9493 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -31,7 +31,7 @@
#include "i82371eb.h"
#include "smbus.h"
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
int acpi_get_sleep_type(void);
#endif
@@ -92,7 +92,7 @@ static void pwrmgt_enable(struct device *dev)
outw(0xffff, DEFAULT_PMBASE + GLBSTS);
outl(0xffffffff, DEFAULT_PMBASE + DEVSTS);
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
/* this reads PMCNTRL, so we have to call it before writing the
* default value */
acpi_slp_type = acpi_get_sleep_type();
diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c
index dfe9ff2..505d059 100644
--- a/src/southbridge/nvidia/ck804/early_setup.c
+++ b/src/southbridge/nvidia/ck804/early_setup.c
@@ -82,7 +82,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index bb0fd13..efe1b99 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -72,7 +72,7 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control,
#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
#endif
-#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
+#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
#define CK804B_DEVN_BASE 1
#else
#define CK804B_DEVN_BASE CK804_DEVN_BASE
diff --git a/src/southbridge/nvidia/ck804/ide.c b/src/southbridge/nvidia/ck804/ide.c
index ac94acb..c7236ec 100644
--- a/src/southbridge/nvidia/ck804/ide.c
+++ b/src/southbridge/nvidia/ck804/ide.c
@@ -60,7 +60,7 @@ static void ide_init(struct device *dev)
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c
index ca6cd94..c62728a 100644
--- a/src/southbridge/nvidia/ck804/nic.c
+++ b/src/southbridge/nvidia/ck804/nic.c
@@ -108,7 +108,7 @@ static void nic_init(struct device *dev)
nic_index++;
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev); /* It will init Option ROM. */
#endif
}
diff --git a/src/southbridge/nvidia/mcp55/ide.c b/src/southbridge/nvidia/mcp55/ide.c
index 0677a75..6d0cebf 100644
--- a/src/southbridge/nvidia/mcp55/ide.c
+++ b/src/southbridge/nvidia/mcp55/ide.c
@@ -61,7 +61,7 @@ static void ide_init(struct device *dev)
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
}
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index d74f10d..0521b89 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -180,7 +180,7 @@ static void nic_init(struct device *dev)
nic_index++;
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);// it will init option rom
#endif
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 3b11dd3..a945f23 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -94,7 +94,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
unsigned pm_base;
#endif
@@ -113,7 +113,7 @@ static void mcp55_sm_read_resources(device_t dev)
static void mcp55_sm_init(device_t dev)
{
-#if CONFIG_GENERATE_ACPI_TABLES == 1
+#if CONFIG_GENERATE_ACPI_TABLES
struct resource *res;
res = find_resource(dev, 0x60);
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index 90ea002..d067b5c 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -144,7 +144,7 @@ print_debug("IDE_INIT:---------->\n");
dword = pci_read_config32(dev, 0xf8);
dword |= 12;
pci_write_config32(dev, 0xf8, dword);
-#if CONFIG_PCI_ROM_RUN == 1
+#if CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index e25535b..0c820c0 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -327,7 +327,7 @@ void enable_rom_decode(void)
pci_write_config8(dev, 0x41, 0x7f);
}
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
static int acpi_is_wakeup_early(void) {
device_t dev;
u16 tmp;
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 7fc5b52..a47ab38 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -244,7 +244,7 @@ static void setup_pm(device_t dev)
/* SCI is generated for RTC/pwrBtn/slpBtn. */
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
-#if CONFIG_HAVE_ACPI_RESUME == 1
+#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
#endif
diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c
index 1afa57e..e681d6e 100644
--- a/src/superio/via/vt1211/vt1211.c
+++ b/src/superio/via/vt1211/vt1211.c
@@ -131,7 +131,7 @@ static void vt1211_pnp_set_resources(struct device *dev)
{
struct resource *res;
-#if CONFIG_CONSOLE_SERIAL8250 == 1
+#if CONFIG_CONSOLE_SERIAL8250
/* TODO: Do the same for SP2? */
if (dev->path.pnp.device == VT1211_SP1) {
for (res = dev->resource_list; res; res = res->next) {
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