[coreboot] Patch merged into coreboot/master: 6f05c2e AMD rd890 late.c: Don't enable PCIe ports after PCIe init.

gerrit at coreboot.org gerrit at coreboot.org
Wed Nov 7 02:03:36 CET 2012

the following patch was just integrated into master:
commit 6f05c2eb5963069977fcb4adce26ebbd5f1123bf
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date:   Sun Oct 28 18:16:19 2012 +0800

    AMD rd890 late.c: Don't enable PCIe ports after PCIe init.
    PCIE devices are detected and initialized by the AMD PCIe init functions,
    which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init.
    Now, all bridges and devices are trained on the device 0.0 enable.
    After PCIe init, the PCIe ports with devices are on and the PCIe ports
    without devices are off. so resources may be allocated correctly
    during the rest of the PCI scan.
    But if the devicetree was being used to enable/disable devices after initialization,
    the problems would arise. Take a look at the serial log:
    do_pci_scan_bridge for PCI: 00:02.0
    PCI: pci_scan_bus for bus 01
    PCI: pci_scan_bus returning with max=001
    do_pci_scan_bridge returns max 1
    do_pci_scan_bridge for PCI: 00:03.0
    PCI: pci_scan_bus for bus 02
    PCI: pci_scan_bus returning with max=002
    do_pci_scan_bridge returns max 2
    do_pci_scan_bridge for PCI: 00:04.0
    PCI: pci_scan_bus for bus 03
    PCI: pci_scan_bus returning with max=003
    do_pci_scan_bridge returns max 3
    PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges
    are still scanned. This is not correct.
    Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395
    Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
    Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
    Reviewed-on: http://review.coreboot.org/1640
    Tested-by: build bot (Jenkins)
    Reviewed-by: Marc Jones <marcj303 at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Nov  6 12:51:42 2012, giving +1
Reviewed-By: Marc Jones <marcj303 at gmail.com> at Wed Nov  7 02:03:36 2012, giving +2
See http://review.coreboot.org/1640 for details.


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