[coreboot] Patch set updated for coreboot: 939777f SPI: Fix and enable Fast Read support
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Wed Nov 7 20:19:15 CET 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1775
-gerrit
commit 939777fa369c6edc5332efc8ce9a2c15419e95bc
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Wed Oct 10 14:21:23 2012 -0700
SPI: Fix and enable Fast Read support
- Fix handling of 5-byte Fast Read command in the ICH SPI
driver. This fix is ported from the U-boot driver.
- Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
defining a name for the bool in Kconfig and removing the
forced select in southbridge config
- Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
to use #if instead of #ifdef
- Relocate flash functions in SMM so they are usable.
This really only needs to happen for read function pointer
since it uses a global function rather than a static one from
the chip, but it is good to ensure the rest are set up
correctly as well.
Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/drivers/spi/Kconfig | 2 +-
src/drivers/spi/gigadevice.c | 4 ++--
src/drivers/spi/macronix.c | 2 +-
src/drivers/spi/spi_flash.c | 10 +++++++++-
src/drivers/spi/winbond.c | 2 +-
src/include/spi.h | 1 +
src/southbridge/intel/bd82x6x/Kconfig | 1 -
src/southbridge/intel/bd82x6x/spi.c | 6 ++++++
8 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index 334ee95..8e6191e 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -80,7 +80,7 @@ config SPI_FLASH_WINBOND
data in the SPI flash and your SPI flash is made by Winbond.
config SPI_FLASH_NO_FAST_READ
- bool
+ bool "Disable Fast Read command"
default n
depends on SPI_FLASH
help
diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c
index 8454705..0647baf 100644
--- a/src/drivers/spi/gigadevice.c
+++ b/src/drivers/spi/gigadevice.c
@@ -154,7 +154,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset,
cmd[3] = offset & 0xff;
#if CONFIG_DEBUG_SPI_FLASH
printk(BIOS_SPEW,
- "PP gigadevice.c: %#p => cmd = { %#02x %#02x%02x%02x }"
+ "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
" chunk_len = %zu\n", buf + actual,
cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
#endif
@@ -226,7 +226,7 @@ struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
stm->flash.write = gigadevice_write;
stm->flash.erase = gigadevice_erase;
-#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+#if CONFIG_SPI_FLASH_NO_FAST_READ
stm->flash.read = spi_flash_cmd_read_slow;
#else
stm->flash.read = spi_flash_cmd_read_fast;
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 148527d..f9138e1 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -210,7 +210,7 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode)
mcx->flash.write = macronix_write;
mcx->flash.erase = macronix_erase;
-#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+#if CONFIG_SPI_FLASH_NO_FAST_READ
mcx->flash.read = spi_flash_cmd_read_slow;
#else
mcx->flash.read = spi_flash_cmd_read_fast;
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 4757486..7116cbf 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -281,7 +281,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
/* search the table for matches in shift and id */
for (i = 0; i < ARRAY_SIZE(flashes); ++i)
if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
-#ifdef __SMM__
+#if CONFIG_SMM_TSEG && defined(__SMM__)
/* Need to relocate this function */
tseg_relocate((void **)&flashes[i].probe);
#endif
@@ -296,6 +296,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
goto err_manufacturer_probe;
}
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
flash->name, flash->sector_size, flash->size);
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index 0e50843..50c2ed4 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
@@ -205,7 +205,7 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode)
stm->flash.write = winbond_write;
stm->flash.erase = winbond_erase;
-#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+#if CONFIG_SPI_FLASH_NO_FAST_READ
stm->flash.read = spi_flash_cmd_read_slow;
#else
stm->flash.read = spi_flash_cmd_read_fast;
diff --git a/src/include/spi.h b/src/include/spi.h
index 7d195d0..5fbe51e 100644
--- a/src/include/spi.h
+++ b/src/include/spi.h
@@ -46,6 +46,7 @@
/* SPI opcodes */
#define SPI_OPCODE_WREN 0x06
+#define SPI_OPCODE_FAST_READ 0x0b
/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 75858c2..7634b80 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -34,7 +34,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
- select SPI_FLASH_NO_FAST_READ
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 53b9982..05649fc 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -484,6 +484,12 @@ static void spi_setup_type(spi_transaction *trans)
if (trans->bytesout == 4) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
}
+
+ /* Fast read command is called with 5 bytes instead of 4 */
+ if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ --trans->bytesout;
+ }
}
static int spi_setup_opcode(spi_transaction *trans)
More information about the coreboot
mailing list