[coreboot] Patch set updated for coreboot: a180293 SPI: Add Fast Read to the OPMENU for locked down SPI

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1772

-gerrit

commit a180293343110ba6a8b75473d7a75a836f44f685
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Oct 8 14:30:06 2012 -0700

    SPI: Add Fast Read to the OPMENU for locked down SPI
    
    The chips we are using do not use BE52 (block erase 0x52)
    so we can use that opcode menu location to enable fast read.
    
    Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
    Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
 src/southbridge/intel/bd82x6x/pch.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 8481554..40c97fd 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -524,8 +524,8 @@ int smbus_read_byte(unsigned device, unsigned address);
 #define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
 #define SPI_OPTYPE_6 0x03 /* Write, address required */
 
-#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */
-#define SPI_OPTYPE_7 0x03 /* Write, address required */
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
 
 #define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
 			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)