[coreboot] Patch merged into coreboot/master: d4bc067 SPI: Add early romstage SPI driver using hardware sequencing

gerrit at coreboot.org gerrit at coreboot.org
Mon Nov 12 17:10:00 CET 2012

the following patch was just integrated into master:
commit d4bc0679540842d78712b41707c2da9f3d7ae204
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Oct 11 13:04:14 2012 -0700

    SPI: Add early romstage SPI driver using hardware sequencing
    This is a basic romstage driver that can be used for the
    MRC cache code on systems where we do not have the MRC cache
    stored in a flash region that is memory mapped.
    It uses the hardware sequencing interface to avoid having
    to know anything about the flash chip itself.
    TEST=manual: this was tested with debug code added to romstage
    that attempted to read the MRC cache at offset 0x3e0000.
    SPI READ offset=003e0000 size=64 buffer=ff7fba00
    SPI ADDR 0x003e0000
    SPI HSFC 0x3f00
    SPI READ: 0=4443524d
    SPI READ: 1=00000bb0
    SPI READ: 2=00008e24
    SPI READ: 3=00000000
    SPI READ: 4=001c8bbb
    SPI READ: 5=0c206466
    SPI READ: 6=0a043220
    SPI READ: 7=000058b4
    SPI READ: 8=00000000
    SPI READ: 9=00000000
    SPI READ: 10=00100000
    SPI READ: 11=00100005
    SPI READ: 12=20202025
    SPI READ: 13=000e0001
    SPI READ: 14=00000000
    SPI READ: 15=00000000
    Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/1777
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Mon Nov 12 09:22:53 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Mon Nov 12 16:42:41 2012, giving +2
See http://review.coreboot.org/1777 for details.


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