[coreboot] Patch set updated for coreboot: 6e138b7 SMM: Pass the ACPI GNVS pointer via state save map

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1766

-gerrit

commit 6e138b7c5222511e40df15ccd96678a6a8b56a03
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Oct 3 19:11:26 2012 -0700

    SMM: Pass the ACPI GNVS pointer via state save map
    
    Instead of hijacking some random memory addresses to
    relay the GNVS pointer to SMM we can use EBX register
    during the write to APM_CNT register when the SMI is
    triggered.
    
    Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/southbridge/intel/bd82x6x/smi.c        | 20 ++++++++++++++------
 src/southbridge/intel/bd82x6x/smihandler.c | 12 ++++++++----
 2 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index bd88df2..c89ae18 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -398,11 +398,19 @@ void smm_lock(void)
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 {
-	/* The GDT or coreboot table is going to live here. But a long time
-	 * after we relocated the GNVS, so this is not troublesome.
+	/*
+	 * Issue SMI to set the gnvs pointer in SMM.
+	 * tcg and smi1 are unused.
+	 *
+	 * EAX = APM_CNT_GNVS_UPDATE
+	 * EBX = gnvs pointer
+	 * EDX = APM_CNT
 	 */
-	*(u32 *)0x500 = (u32)gnvs;
-	*(u32 *)0x504 = (u32)tcg;
-	*(u32 *)0x508 = (u32)smi1;
-	outb(0xea, 0xb2);
+	asm volatile (
+		"outb %%al, %%dx\n\t"
+		: /* ignore result */
+		: "a" (APM_CNT_GNVS_UPDATE),
+		  "b" ((u32)gnvs),
+		  "d" (APM_CNT)
+	);
 }
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 8fea33f..4cad88b 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -424,7 +424,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 	}
 }
 
-#if CONFIG_ELOG_GSMI
 /*
  * Look for Synchronous IO SMI and use save state from that
  * core in case we are not running on the same core that
@@ -462,7 +461,6 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u64 cmd)
 
 	return NULL;
 }
-#endif
 
 #if CONFIG_ELOG_GSMI
 static void southbridge_smi_gsmi(void)
@@ -492,6 +490,7 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 	u32 pmctrl;
 	u8 reg8;
 	int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
+	em64t101_smm_state_save_area_t *state;
 
 	/* Emulate B2 register as the FADT / Linux expects it */
 
@@ -528,8 +527,13 @@ static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state
 			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
 			return;
 		}
-		gnvs = *(global_nvs_t **)0x500;
-		smm_initialized = 1;
+		state = smi_apmc_find_state_save(reg8);
+		if (state) {
+			/* EBX in the state save contains the GNVS pointer */
+			gnvs = (global_nvs_t *)((u32)state->rbx);
+			smm_initialized = 1;
+			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
+		}
 		break;
 #if CONFIG_ELOG_GSMI
 	case ELOG_GSMI_APM_CNT: