[coreboot] New patch to review for coreboot: 89a5394 Sandybridge: Set PEG clock gating
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Tue Nov 13 02:41:19 CET 2012
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1827
-gerrit
commit 89a53943e16def986ea8b715d6edb9c0e5ae0f4b
Author: Marc Jones <marc.jones at se-eng.com>
Date: Fri Nov 2 14:26:44 2012 -0600
Sandybridge: Set PEG clock gating
If the PEI System Agent doesn't run PCIe initialization, the PEG
clock gating will not be setup. Add the PEG clock gating when
pei_data->pcie_init is 0.
Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/northbridge/intel/sandybridge/raminit.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2b46873..b5a1c23 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -205,6 +205,13 @@ static void report_memory_config(void)
}
}
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
+}
+
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@@ -289,6 +296,7 @@ void sdram_initialize(struct pei_data *pei_data)
else
intel_early_me_status();
+ post_system_agent_init(pei_data);
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */
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