[coreboot] Patch merged into coreboot/master: e8179b5 Add ddr3lv_support flag to pei_data structure

gerrit at coreboot.org gerrit at coreboot.org
Wed Nov 14 05:38:19 CET 2012

the following patch was just integrated into master:
commit e8179b51380cf0922466c33a9a0998a65f246a84
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Wed Jul 11 10:40:45 2012 -0700

    Add ddr3lv_support flag to pei_data structure
    This will enable DDR3 1.35V support for memory training in
    the reference code.  It requires the board to be setup for
    1.35V with whatever board-specific GPIOs are available.
    Change-Id: I14e4686c20f9610f90678e6e3bece8ba80d8621a
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: http://review.coreboot.org/1825
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martin at se-eng.com>
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Tue Nov 13 20:22:49 2012, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Wed Nov 14 05:38:16 2012, giving +2
See http://review.coreboot.org/1825 for details.


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