[coreboot] New patch to review for coreboot: c229589 Persimmon: Disable the unused GPP PCIe clocks

Dave Frodin (dave.frodin@se-eng.com) gerrit at coreboot.org
Fri Nov 16 23:16:19 CET 2012


Dave Frodin (dave.frodin at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1876

-gerrit

commit c229589289506e6978677f7c6bd48cfdcd681e92
Author: Dave Frodin <dave.frodin at se-eng.com>
Date:   Fri Nov 16 14:16:33 2012 -0700

    Persimmon: Disable the unused GPP PCIe clocks
    
    Change-Id: I4128af7912bec090bbd48acc1b20d0452e7a4a28
    Signed-off-by: Dave Frodin <dave.frodin at se-eng.com>
---
 src/mainboard/amd/persimmon/mainboard.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 4c52dc3..6949ce7 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -28,6 +28,7 @@
 #include "BiosCallOuts.h"
 #include <cpu/amd/agesa/s3_resume.h>
 #include <cpu/amd/mtrr.h>
+#include "SBPLATFORM.h"
 
 void set_pcie_reset(void);
 void set_pcie_dereset(void);
@@ -63,6 +64,16 @@ static void persimmon_enable(device_t dev)
 #if CONFIG_HAVE_ACPI_RESUME
 	acpi_slp_type = acpi_get_sleep_type();
 #endif
+
+u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+
+	/* enable GPP CLK0 thru CLK1 */
+	/* disable GPP CLK2 thru SLT_GFX_CLK */
+	*(misc_mem_clk_cntrl + 0) = 0xFF;
+	*(misc_mem_clk_cntrl + 1) = 0x00;
+	*(misc_mem_clk_cntrl + 2) = 0x00;
+	*(misc_mem_clk_cntrl + 3) = 0x00;
+	*(misc_mem_clk_cntrl + 4) = 0x00;
 }
 
 struct chip_operations mainboard_ops = {




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