[coreboot] Patch merged into coreboot/master: b8117b0 SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)

gerrit at coreboot.org gerrit at coreboot.org
Tue Nov 27 11:03:53 CET 2012

the following patch was just integrated into master:
commit b8117b062266eda6b8ac9a8b60881a99f0323a48
Author: Zheng Bao <fishbaozi at gmail.com>
Date:   Tue Nov 27 18:08:53 2012 +0800

    SPI/SST: Add OpCode Enable-Write-Status-Register (EWSR)
    For SST chips, the Write-Status-Register instruction must be
    executed immediately after the execution of the
    Enable-Write-Status-Register instruction, instead of Write-Enable.
    Change-Id: I4b3473cd671829def3bd1641ececcf8d9dad4a56
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
    Reviewed-on: http://review.coreboot.org/1919
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Patrick Georgi <patrick at georgi-clan.de>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Tue Nov 27 11:03:52 2012, giving +2
See http://review.coreboot.org/1919 for details.


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