[coreboot] Patch set updated for coreboot: b068a07 AMD SB800: PCI(E) slots on Persimmon

Zheng Bao (zheng.bao@amd.com) gerrit at coreboot.org
Thu Oct 18 10:54:07 CEST 2012


Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1098

-gerrit

commit b068a0753e63f8ddbeaaa2bc265a456655904b5e
Author: Zheng Bao <fishbaozi at gmail.com>
Date:   Fri Oct 12 11:17:20 2012 +0800

    AMD SB800: PCI(E) slots on Persimmon
    
    (routine.asl):Set the correct device number in the pcie interrupt routine in ACPI asl.
    The device number is decided by which address pin is connected to IDSEL.
    Table 3-1: IDSEL Generation
    Primary Address AD[15::11]     Secondary Address AD[31::16]
    0 0000                          0000 0000 0000 0001
    0 0001                          0000 0000 0000 0010
    0 0010                          0000 0000 0000 0100
    0 0011                          0000 0000 0000 1000
    0 0100                          0000 0000 0001 0000
    0 0101                          0000 0000 0010 0000
    0 0110                          0000 0000 0100 0000
    0 0111                          0000 0000 1000 0000
    0 1000                          0000 0001 0000 0000
    0 1001                          0000 0010 0000 0000
    0 1010                          0000 0100 0000 0000
    0 1011                          0000 1000 0000 0000
    0 1100                          0001 0000 0000 0000
    0 1101                          0010 0000 0000 0000
    0 1110                          0100 0000 0000 0000
    0 1111                          1000 0000 0000 0000
    1 xxxx                          0000 0000 0000 0000
    On persimmon, PCI slot 0's IDSEL is connected to AD19, so the device number is 3.
    Slot 1's IDSEL is connected to AD20, so the device number is 4.
    
    (devicetree.cb): Enable the PCIE bridge which is connected to the PCIE slot.
    
    Change-Id: I1b3fb59990e06d7bc7cf19639f2b93dbb7bf9b3e
    Signed-off-by: Zheng Bao <zheng.bao at amd.com>
    Signed-off-by: zbao <fishbaozi at gmail.com>
---
 src/mainboard/amd/persimmon/acpi/routing.asl | 24 ++++++++++++------------
 src/mainboard/amd/persimmon/devicetree.cb    | 10 +++++-----
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/amd/persimmon/acpi/routing.asl b/src/mainboard/amd/persimmon/acpi/routing.asl
index d7e4687..24bc809 100644
--- a/src/mainboard/amd/persimmon/acpi/routing.asl
+++ b/src/mainboard/amd/persimmon/acpi/routing.asl
@@ -391,17 +391,17 @@ Scope(\_SB) {
 
 	Name(PCIB, Package(){
 		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-		Package(){0x0007FFFF, 0, 0, 0x16 },
-		Package(){0x0007FFFF, 1, 0, 0x17 },
-		Package(){0x0007FFFF, 2, 0, 0x14 },
-		Package(){0x0007FFFF, 3, 0, 0x15 },
+		Package(){0x0003FFFF, 0, 0, 0x14 },
+		Package(){0x0003FFFF, 1, 0, 0x15 },
+		Package(){0x0003FFFF, 2, 0, 0x16 },
+		Package(){0x0003FFFF, 3, 0, 0x17 },
+		Package(){0x0004FFFF, 0, 0, 0x15 },
+		Package(){0x0004FFFF, 1, 0, 0x16 },
+		Package(){0x0004FFFF, 2, 0, 0x17 },
+		Package(){0x0004FFFF, 3, 0, 0x14 },
+		Package(){0x0005FFFF, 0, 0, 0x16 },
+		Package(){0x0005FFFF, 1, 0, 0x17 },
+		Package(){0x0005FFFF, 2, 0, 0x14 },
+		Package(){0x0005FFFF, 3, 0, 0x15 },
 	})
 }
diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb
index e5bbca2..da81dc3 100644
--- a/src/mainboard/amd/persimmon/devicetree.cb
+++ b/src/mainboard/amd/persimmon/devicetree.cb
@@ -28,12 +28,12 @@ chip northbridge/amd/agesa/family14/root_complex
 #					device pci 18.0 on #  northbridge
 					chip northbridge/amd/agesa/family14 # PCI side of HT root complex
 						device pci 0.0 on end # Root Complex
-						device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
+						device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456]
 						device pci 1.1 on end # Internal Multimedia
-						device pci 4.0 on end # PCIE P2P bridge 0x9604
-						device pci 5.0 off end # PCIE P2P bridge 0x9605
-						device pci 6.0 off end # PCIE P2P bridge 0x9606
-						device pci 7.0 off end # PCIE P2P bridge 0x9607
+						device pci 4.0 on end # PCIE P2P bridge on-board NIC
+						device pci 5.0 off end # PCIE P2P bridge
+						device pci 6.0 on end # PCIE P2P bridge PCIe slot
+						device pci 7.0 off end # PCIE P2P bridge
 						device pci 8.0 off end # NB/SB Link P2P bridge
 					end # agesa northbridge
 




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