[coreboot] Generic AMD E350 Support
c-d.hailfinger.devel.2006 at gmx.net
Fri Oct 19 12:53:47 CEST 2012
Am 18.10.2012 01:32 schrieb Peter Stuge:
> Graeme Russ wrote:
>>> Unsure. You would then be powering one of the 3v3 rails (where the
>>> flash chip is connected) from the programmer, without powering any
>>> other rail on the board. The southbridge may not like it at all
>>> when your programmer drives the SPI pins in that state.
>> Hmmm, I wonder what the potential for permanent damage is?
> I also don't know. It depends on what the IO drivers are like in the
I wouldn't fear permanent damage on the mainboard, but it's entirely
possible that the southbridge and other devices sink too much current on
the 3.3V rail and you either damage the programmer or the voltage on the
3.3V rail isn't high enough to drive the chip due to programmer power
>> So to be safe:
>> - Jumper the front panel reset pins
>> - Power-on the motherboard
>> - Do a current test from VCC to each of the CS#, HOLD#, WP#, SCLK,
>> SI, and SO pins
> To be really safe test both from VCC to pin, as well as from pin to GND.
> HOLD# and WP# are never really used, and you don't even have to
> connect them to the programmer.
HOLD# is used by IT87* LPC->SPI translation to achieve page (256 byte)
programming. Otherwise it's rare.
WP# might be pulled down by the chipset/superio, it really depends on
the board designer. If it defaults to high, there is no reason to
connect it to the programmer. If it defaults to low, you have to make
sure you won't burn out the GPIO driving it while you pull it high from
>> - Connect the programmer without connecting the programmers VCC
>> - Program the chip
> Yep, that's it.
Indeed, that looks like a good idea.
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