[coreboot] New patch to review for coreboot: 9ca468c northbridge/sch: Read the GPU memory from the correct PCI device
Sebastian Andrzej Siewior (sebastian@breakpoint.cc)
gerrit at coreboot.org
Fri Oct 26 19:16:34 CEST 2012
Sebastian Andrzej Siewior (sebastian at breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1628
-gerrit
commit 9ca468c393884f342b167d4c2d4028b8d976e60b
Author: Sebastian Andrzej Siewior <bigeasy at linutronix.de>
Date: Fri Oct 26 19:01:17 2012 +0200
northbridge/sch: Read the GPU memory from the correct PCI device
The GGC register which contains the size of memory that is used for GPU
is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
src/mainboard/iwave/iWRainbowG6/romstage.c.
Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
Signed-off-by: Sebastian Andrzej Siewior <bigeasy at linutronix.de>
---
src/northbridge/intel/sch/northbridge.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index fb3bff8..4ca1248 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -144,7 +144,7 @@ static void pci_domain_set_resources(device_t dev)
tseg_memory_size = tseg_size * 1024ULL;
}
- reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(2, 0)), GGC);
if (!(reg16 & 2)) {
int uma_size = 0;
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
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