[coreboot] Patch merged into coreboot/master: 9ca468c northbridge/sch: Read the GPU memory from the correct PCI device

gerrit at coreboot.org gerrit at coreboot.org
Fri Oct 26 21:54:50 CEST 2012


the following patch was just integrated into master:
commit 9ca468c393884f342b167d4c2d4028b8d976e60b
Author: Sebastian Andrzej Siewior <bigeasy at linutronix.de>
Date:   Fri Oct 26 19:01:17 2012 +0200

    northbridge/sch: Read the GPU memory from the correct PCI device
    
    The GGC register which contains the size of memory that is used for GPU
    is in PCI device 2,0 and not 0,0. It is set to to 4MiB in
    src/mainboard/iwave/iWRainbowG6/romstage.c.
    
    Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4
    Signed-off-by: Sebastian Andrzej Siewior <bigeasy at linutronix.de>

Reviewed-By: Patrick Georgi <patrick at georgi-clan.de> at Fri Oct 26 19:23:20 2012, giving +2
Build-Tested: build bot (Jenkins) at Fri Oct 26 19:54:08 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer at coreboot.org> at Fri Oct 26 19:27:40 2012, giving +2
See http://review.coreboot.org/1628 for details.

-gerrit




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