[coreboot] New patch to review for coreboot: 065fde7 Merge cpu/intel/acpi.h into cpu/intel/speedstep.h

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Tue Oct 30 14:50:10 CET 2012


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1655

-gerrit

commit 065fde704df295308e25c100cd622e4b55bbe2d8
Author: Nico Huber <nico.huber at secunet.com>
Date:   Mon Oct 1 15:53:14 2012 +0200

    Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
    
    We had only some MSR definitions in there, which are used in speedstep
    related code. I think speedstep.h is the better and less confusing place
    for these.
    
    Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/cpu/intel/model_206ax/acpi.c            |  1 -
 src/cpu/intel/model_6ex/model_6ex_init.c    |  1 -
 src/cpu/intel/model_6fx/model_6fx_init.c    |  1 -
 src/cpu/intel/speedstep/acpi.c              |  1 -
 src/include/cpu/intel/acpi.h                | 24 ------------------------
 src/include/cpu/intel/speedstep.h           |  7 +++++++
 src/mainboard/intel/eagleheights/romstage.c |  2 +-
 7 files changed, 8 insertions(+), 29 deletions(-)

diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index c8c30a4..80ed4ba 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -26,7 +26,6 @@
 #include <arch/acpigen.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/intel/acpi.h>
 #include <cpu/intel/speedstep.h>
 #include <cpu/intel/turbo.h>
 #include <device/device.h>
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 1c8c72b..9dbb137 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -30,7 +30,6 @@
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/intel/acpi.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <usbdebug.h>
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 106719e..3cdfdc4 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -29,7 +29,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
 #include <cpu/intel/speedstep.h>
-#include <cpu/intel/acpi.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 5cc4c1d..249d9e4 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -25,7 +25,6 @@
 #include <arch/acpigen.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
-#include <cpu/intel/acpi.h>
 #include <cpu/intel/speedstep.h>
 #include <device/device.h>
 
diff --git a/src/include/cpu/intel/acpi.h b/src/include/cpu/intel/acpi.h
deleted file mode 100644
index aac4592..0000000
--- a/src/include/cpu/intel/acpi.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Patrick Georgi <patrick at georgi-clan.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define IA32_PLATFORM_ID  0x017
-#define IA32_PERF_STS     0x198
-#define IA32_PERF_CTL     0x199
-#define MSR_THERM2_CTL    0x19D
-#define IA32_MISC_ENABLES 0x1A0
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index 00a5b9b..c3cd2d2 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -32,3 +32,10 @@
  */
 #define PMB1_BASE 0x800
 
+
+/* Speedstep related MSRs */
+#define IA32_PLATFORM_ID  0x017
+#define IA32_PERF_STS     0x198
+#define IA32_PERF_CTL     0x199
+#define MSR_THERM2_CTL    0x19D
+#define IA32_MISC_ENABLES 0x1A0
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index a250c05..1e906ef 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -30,7 +30,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
 #include "reset.c"




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