[coreboot] AMD SB800 AHCI: How to enable Staggered Spin-up?
paulepanter at users.sourceforge.net
Fri Apr 12 14:35:01 CEST 2013
Dear coreboot folks,
investigating, why GRUB is not able to find my SATA drive when the SATA
controller is in AHCI mode , Vladimir pointed out that the controller
does not advertise support of staggered spin-up as described in section
10.10 of the AHCI specification .
Looking at the SeaBIOS serial log with the debug level set to 8, the
flags are printed as follows.
AHCI: cap 0xf332ff05, ports_impl 0x3f
With the following SeaBIOS code
$ nl -ba src/ahci.h
97 /* global controller registers */
98 #define HOST_CAP 0x00 /* host capabilities */
109 /* HOST_CAP bits */
110 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */
111 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */
112 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */
113 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
$ nl -ba src/ahci.c
601 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
602 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
603 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
604 ctrl->caps, ctrl->ports);
this means, that for `HOST_CAP_SSS` we have to look at the 7th digit
from the right of the hex number 0xf332ff05, which is 3, which is in
0011b, and now at the fourth digit from the right which is 0. So this is
disabled. (SeaBIOS does not seem to care about the flag though.)
Reading the code in `src/vendorcode/amd/cimx/sb800/SATA.c`  I do not
find where this bit might be set.
So any idea, why the CIMx code does not allow to enable staggered
spin-up? Are there known problems with the hardware or is it just not
implemented in CIMx yet and should simply be added?
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