[coreboot] Question regarding two registers on the LPC bridge in AMD Hudson
wei at aristanetworks.com
Sat Aug 3 10:09:40 CEST 2013
I see hudson_enable_rom() in southbridge/amd/agesa/hudson/bootblock.c
enables LPC ROM decoding and sets up ROM address range 2 to be
identical to ROM size. In particular I'm referring to the two
registers at 0x48 and 0x6c.
However, when I boot into Linux I found the LPC ROM Range Port Enable
bits were cleared, which is fine I suppose since the boot rom is off
SPI instead of LPC? And the ROM Address Range 2 was set to start from
0xff00_0000. I think it should start from 0xffc0_0000 instead since
the flash size is 4MB.
I'm curious what else would bother to write to those registers? Also,
what register on AMD chip is used to cancel the legacy BIOS mapping at
1MB? On Intel northbridge there are the PAM (programmable attribute
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