[coreboot] New patch to review for coreboot: c2ba5f8 armv7: unify stage hand-off routines

David Hendricks (dhendrix@chromium.org) gerrit at coreboot.org
Fri Feb 1 02:19:59 CET 2013


David Hendricks (dhendrix at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2254

-gerrit

commit c2ba5f86d00ad43ed2d7828c3b840f79751938a7
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Jan 31 17:05:50 2013 -0800

    armv7: unify stage hand-off routines
    
    This replaces the current stage-specific exit/entry functions with
    generic versions. Now all stages compile with stage_entry(), which
    is placed at .text.stage_entry.armv7, and stage_exit().
    
    Snow is also updated to avoid breakage.
    
    Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
---
 src/arch/armv7/Makefile.inc            | 40 ++++++++---------
 src/arch/armv7/bootblock_simple.c      |  8 ++--
 src/arch/armv7/coreboot_ram.ld         |  1 +
 src/arch/armv7/include/arch/stages.h   | 28 ++++++++++++
 src/arch/armv7/lib/Makefile.inc        |  2 -
 src/arch/armv7/lib/c_start.S           |  9 ----
 src/arch/armv7/romstage.ld             |  2 +-
 src/arch/armv7/romstage_main.c         | 29 -------------
 src/arch/armv7/stages.c                | 45 ++++++++++++++++++++
 src/mainboard/google/snow/Makefile.inc |  1 +
 src/mainboard/google/snow/mainboard.c  |  2 +-
 src/mainboard/google/snow/ramstage.c   | 32 ++++++++++++++
 src/mainboard/google/snow/romstage.c   | 78 +++++++++++++++++++++++++++++++---
 13 files changed, 203 insertions(+), 74 deletions(-)

diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index ba734a6..78fa671 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -104,6 +104,14 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	$(OBJCOPY) --add-gnu-debuglink=$< $@.tmp
 	mv $@.tmp $@
 
+stages_c = $(src)/arch/armv7/stages.c
+stages_o = $(obj)/arch/armv7/stages.o
+
+$(stages_o): $(stages_c)
+	@printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm
+
+
 ################################################################################
 # Build the coreboot_ram (stage 2)
 
@@ -115,12 +123,12 @@ else
 	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $<
 endif
 
-$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME)
+$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --wrap __do_div64 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group
 else
-	$(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 ################################################################################
@@ -239,18 +247,11 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc)
 	@printf "    GEN        $(subst $(obj)/,,$(@))\n"
 	printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@
 
-bootblock_exit_c = $(src)/arch/armv7/bootblock_exit.c
-bootblock_exit_o = $(obj)/arch/armv7/bootblock_exit.o
-
-$(bootblock_exit_o): $(bootblock_exit_c)
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm
-
 $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -Wa,-acdlns -c -o $@ $<  > $(basename $@).disasm
 
-BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o)
+#BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o)
 
 $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
@@ -262,39 +263,32 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ",,$(CONFIG_BOOTBLOCK_S
 		$< > $(objgenerated)/bootblock.inc.d
 	$(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $< -o $@
 
-$(objcbfs)/bootblock.debug: $(BOOTBLOCK_OBJS) $(objgenerated)/bootblock.ld
+$(objcbfs)/bootblock.debug:  $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $< -T $(objgenerated)/bootblock.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(BOOTBLOCK_OBJS) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group  $(objgenerated)/bootblock.o $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 ################################################################################
 # Build the romstage
 
-romstage_main_c = $(src)/arch/armv7/romstage_main.c
-romstage_main_o = $(obj)/arch/armv7/romstage_main.o
-
-$(romstage_main_o): $(romstage_main_c)
-	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -nostdlib -nostartfiles -static -c -o $@ $< -marm
-
 # FIXME(dhendrix): added debug printfs
-$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(romstage_main_o) $(objgenerated)/romstage_null.ld
+$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage_null.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(romstage_main_o) -T $(objgenerated)/romstage_xip.ld
+	$(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(stages_o) -T $(objgenerated)/romstage_xip.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(romstage_main_o) $(LIBGCC_FILE_NAME) -Wl,--end-group
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group
 endif
 
 $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions
diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/armv7/bootblock_simple.c
index d97075e..8df7e6a 100644
--- a/src/arch/armv7/bootblock_simple.c
+++ b/src/arch/armv7/bootblock_simple.c
@@ -20,9 +20,11 @@
  */
 
 #include <bootblock_common.h>
-#include <arch/bootblock_exit.h>
 #include <arch/cbfs.h>
 #include <arch/hlt.h>
+#include <arch/stages.h>
+
+#include "stages.c"
 
 static int boot_cpu(void)
 {
@@ -34,7 +36,7 @@ static int boot_cpu(void)
 	return 1;
 }
 
-void main(unsigned long bist)
+void main(void)
 {
 	const char *target1 = "fallback/romstage";
 	unsigned long romstage_entry;
@@ -49,6 +51,6 @@ void main(unsigned long bist)
 			CBFS_DEFAULT_MEDIA, target1);
 
 	printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
-	if (romstage_entry) bootblock_exit(romstage_entry);
+	if (romstage_entry) stage_exit(romstage_entry);
 	hlt();
 }
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index 329bce4..2f08d14 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -32,6 +32,7 @@ SECTIONS
 	 */
 	.text : {
 		_text = .;
+		*(.text.stage_entry.armv7);
 		*(.text);
 		*(.text.*);
 		. = ALIGN(16);
diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h
new file mode 100644
index 0000000..215aaa8
--- /dev/null
+++ b/src/arch/armv7/include/arch/stages.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 The ChromiumOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_STAGES_H
+#define __ARCH_STAGES_H
+
+extern void main(void);
+
+void stage_entry(void) __attribute__((section(".text.stage_entry.armv7")));
+void stage_exit(unsigned long);
+
+#endif
diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc
index d911341..e52bc54 100644
--- a/src/arch/armv7/lib/Makefile.inc
+++ b/src/arch/armv7/lib/Makefile.inc
@@ -9,8 +9,6 @@ romstage-y += syslib.c
 #ramstage-y += printk_init.c
 #romstage-y += walkcbfs.S
 
-ramstage-y += c_start.S
-
 ramstage-y += div0.c
 ramstage-y += div64.S
 ramstage-y += hang_spl.c
diff --git a/src/arch/armv7/lib/c_start.S b/src/arch/armv7/lib/c_start.S
deleted file mode 100644
index b6e7462..0000000
--- a/src/arch/armv7/lib/c_start.S
+++ /dev/null
@@ -1,9 +0,0 @@
-.section ".text"
-.globl _start
-_start:
-	bl	_hardwaremain
-
-_hardwaremain: .word hardwaremain
-@ .word hardwaremain
-
-
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index b4bc29d..6728fb1 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -38,7 +38,7 @@ SECTIONS
 	.romtext . : {
 		_rom = .;
 		_start = .;
-		*(.text.entry.armv7);
+		*(.text.stage_entry.armv7);
 		*(.text.startup);
 		*(.text);
 	}
diff --git a/src/arch/armv7/romstage_main.c b/src/arch/armv7/romstage_main.c
deleted file mode 100644
index 0b463b8..0000000
--- a/src/arch/armv7/romstage_main.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-void main(void);
-
-/* romstage_main is simply a stub to invoke main(), to handle ARM mode switching
- * (ARM/Thumb) properly. */
-
-void romstage_main(void) __attribute__((section(".text.entry.armv7")));
-void romstage_main(void)
-{
-	main();
-}
diff --git a/src/arch/armv7/stages.c b/src/arch/armv7/stages.c
new file mode 100644
index 0000000..fd4374f
--- /dev/null
+++ b/src/arch/armv7/stages.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * This file contains entry/exit functions for each stage during coreboot
+ * execution (bootblock entry and ramstage exit will depend on external
+ * loading.
+ *
+ * Unlike other files, this one should be compiled with a -m option to
+ * specify a pre-determined instruction set. The is to ensure consistency
+ * in the CPU operating mode (ARM or Thumb) when hand-off between stages
+ * occurs.
+ *
+ * Entry points must be placed at the location the previous stage jumps
+ * to (the lowest address in the stage image). This is done by giving
+ * stage_entry() its own section in .text and placing it first in the
+ * linker script.
+ */
+
+#include <arch/stages.h>
+
+void stage_entry(void)
+{
+	main();
+}
+
+void stage_exit(unsigned long addr)
+{
+	__attribute__((noreturn)) void (*doit)(void) = (void *)addr;
+	doit();
+}
diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc
index 26378db..a43bcbc 100644
--- a/src/mainboard/google/snow/Makefile.inc
+++ b/src/mainboard/google/snow/Makefile.inc
@@ -28,6 +28,7 @@ romstage-y += romstage.c
 romstage-y += smdk5250_spl.c
 ramstage-y += smdk5250_spl.c
 #ramstage-y += mainboard.c
+ramstage-y += ramstage.c
 
 # romstage-$(CONFIG_CHROMEOS) += chromeos.c
 
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 00b3e93..f11f1fa 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -18,6 +18,7 @@
  */
 
 #include <device/device.h>
+#include <console/console.h>
 
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
@@ -31,4 +32,3 @@ struct chip_operations mainboard_ops = {
 	.name	= "Samsung/Google ARM ChromeBook",
 	.enable_dev = mainboard_enable,
 };
-
diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c
new file mode 100644
index 0000000..50050d3
--- /dev/null
+++ b/src/mainboard/google/snow/ramstage.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2013 The ChromeOS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <console/console.h>
+
+void main(void)
+{
+//	volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+//	*pshold &= ~0x100;	/* shut down */
+
+	/* FIXME: console_init() seems to cause things to die... Maybe
+	   we need to reset our stack pointer? */
+//	console_init();
+	printk(BIOS_INFO, "hello from ramstage\n");
+	while (1);
+}
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 3f3f3ec..d496366 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -30,24 +30,90 @@
 #include <device/i2c.h>
 
 #include <cpu/samsung/s5p-common/s3c24x0_i2c.h>
-#include "cpu/samsung/exynos5250/dmc.h"
 #include <cpu/samsung/exynos5250/power.h>
-#include <cpu/samsung/exynos5250/clock_init.h>
 #include <cpu/samsung/exynos5-common/uart.h>
 #endif
+#include <cbfs.h>
+#include <common.h>
+#include <cpu/samsung/exynos5250/setup.h>
+#include <cpu/samsung/exynos5250/dmc.h>
+#include <cpu/samsung/exynos5250/clock_init.h>
 #include <console/console.h>
+#include <arch/bootblock_exit.h>
+#include <arch/stages.h>
 
-void main(void);
 void main(void)
 {
-//	volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+	struct cbfs_media cbfs;
 //	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 //	power_init();
 //	clock_init();
 //	exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
 	console_init();
 	printk(BIOS_INFO, "hello from romstage\n");
+	struct mem_timings *mem;
+	int ret;
+
+	mem = clock_get_mem_timings();
+	printk(BIOS_SPEW, "clock_get_mem_timings returns 0x%p\n", mem);
+	printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
+		mem->mem_manuf,
+		mem->mem_type,
+		mem->mpll_mdiv,
+		mem->frequency_mhz);
+
+       ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
+       if (ret) {
+               printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
+                      ret);
+               while(1);
+       }
+
+       printk(BIOS_INFO, "ddr3_init done\n");
+       /* wow, did it work? */
+	int i;
+	u32 *c = (void *)CONFIG_RAMBASE;
+
+//	mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+//      printk(BIOS_INFO, "mmu_setup done\n");
+	for(i = 0; i < 16384; i++)
+		c[i] = i+32768;
+	for(i = 0; i < 16384; i++)
+		if (c[i] != i+32768)
+			printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]);
+	for(i = 0; i < 1048576; i++)
+		c[i] = 0;
+	ret = init_default_cbfs_media(&cbfs);
+	if (ret){
+		printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n",
+		       ret);
+		while (1);
+	}
+
+	struct cbfs_stage *stage = (struct cbfs_stage *)
+		cbfs_get_file_content(&cbfs, "fallback/coreboot_ram",
+				      CBFS_TYPE_STAGE);
+	printk(BIOS_ERR, "Stage: %p\n", stage);
+	printk(BIOS_ERR, "loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n",
+	       "ram stage",
+	       (uint32_t) stage->load, stage->memlen,
+	       (void *)(u32)stage->entry);
+
+#if 0
+	/* for reference and testing ... we should be able to remove soon */
+//	c = (void *)(u32)(stage->load + stage->len);
+	c = (void *)(u32)(stage->load);
+	printk(BIOS_ERR, "memzero 0x%x words starting at %p\n",
+	       (stage->memlen /*- stage->len*/)/4, c);
+	for(i = 0; i < (stage->memlen /*- stage->len*/)/4; i++){
+		printk(BIOS_INFO, "%p, ", &c[i]);
+		c[i] = 0;
+	}
+#endif
+
+	void *entry = cbfs_load_stage(&cbfs, "fallback/coreboot_ram");
+	printk(BIOS_INFO, "entry is %p\n", entry);
 
-//	*pshold &= ~0x100;	/* shut down */
-	mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+	printk(BIOS_INFO, "sayonara, romstage!\n");
+	stage_exit((unsigned long)entry);
 }



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