[coreboot] New patch to review for coreboot: 2a29e77 AMD Fam14 - Fix warnings
Martin Roth (martin.roth@se-eng.com)
gerrit at coreboot.org
Wed Feb 6 05:21:22 CET 2013
Martin Roth (martin.roth at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2293
-gerrit
commit 2a29e779732b0e8f9672bfc5fc44e69a8208ace2
Author: Martin Roth <martin.roth at se-eng.com>
Date: Tue Feb 5 21:06:21 2013 -0700
AMD Fam14 - Fix warnings
Added casts and a couple of #ifdefs to fix the warnings in the
vendorcode/amd/agesa/f14 codebase. This will allow us to re-enable
'all warnings being treated as errors' in boards such as Persimmon
that are using this code. That change will follow.
Verified on persimmon.
Change-Id: I1671b191c72dfc1d63ada41126ae3418bc8f86ae
Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
src/vendorcode/amd/agesa/f14/AGESA.h | 4 ++++
.../amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++---
.../amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 4 ++--
.../amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c | 2 +-
src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 19 ++++++++++---------
5 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h
index 511be69..5eaa638 100644
--- a/src/vendorcode/amd/agesa/f14/AGESA.h
+++ b/src/vendorcode/amd/agesa/f14/AGESA.h
@@ -1129,8 +1129,12 @@ typedef enum {
///< CPU MSR Register definitions ------------------------------------------
#define SYS_CFG 0xC0010010
+#ifndef TOP_MEM
#define TOP_MEM 0xC001001A
+#endif
+#ifndef TOP_MEM2
#define TOP_MEM2 0xC001001D
+#endif
#define HWCR 0xC0010015
#define NB_CFG 0xC001001F
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
index d3987fb..bb23204 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
@@ -216,7 +216,7 @@ CopyHeapToTempRamAtPost (
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
- BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress);
+ BaseAddressInTempMem = (UINT8 *) (intptr_t) (UserOptions.CfgHeapDramAddress);
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
@@ -369,7 +369,7 @@ CopyHeapToMainRamAtPost (
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
- if (StdHeader->HeapBasePtr >= 0x100000) {
+ if (StdHeader->HeapBasePtr >= (void *) 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
@@ -378,7 +378,7 @@ CopyHeapToMainRamAtPost (
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
- if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
+ if ((VariableMtrrBase == ((UINT64) (intptr_t) (StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
break;
}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
index 40c395d..0b9b9c6 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c
@@ -860,7 +860,7 @@ ApUtilSetupIdtForHlt (
DescSize = 8;
}
- HandlerOffset = (UINT64)&NmiHandler;
+ HandlerOffset = (UINT64) (intptr_t) &NmiHandler;
NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF);
NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF);
GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);
@@ -869,7 +869,7 @@ ApUtilSetupIdtForHlt (
NmiIdtDescPtr->Offset64 = (UINT32) (HandlerOffset >> 32);
NmiIdtDescPtr->Rsvd64 = 0;
IdtInfo.Limit = (UINT16) ((DescSize * 3) - 1);
- IdtInfo.Base = (UINT64) NmiIdtDescPtr - (DescSize * 2);
+ IdtInfo.Base = (UINT64) (intptr_t) NmiIdtDescPtr - (DescSize * 2);
SetIdtr (&IdtInfo , StdHeader);
}
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
index 4116a6e..bc15447 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
@@ -208,7 +208,7 @@ LoadMicrocode (
PATCH_LOADER PatchLoaderMsr;
// Load microcode patch into CPU
- PatchLoaderMsr.RawData = (UINT64) MicrocodePatchPtr;
+ PatchLoaderMsr.RawData = (UINT64) (intptr_t) MicrocodePatchPtr;
PatchLoaderMsr.BitFields.SBZ = 0;
LibAmdMsrWrite (MSR_PATCH_LOADER, &PatchLoaderMsr.RawData, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
index 57e1838..f6b409f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c
@@ -164,7 +164,8 @@ HeapManagerInit (
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_MASK, &MsrData, StdHeader);
if (MsrData == (CacheInfoPtr->VariableMtrrMask & AMD_HEAP_MTRR_MASK)) {
LibAmdMsrRead (AMD_MTRR_VARIABLE_HEAP_BASE, &MsrData, StdHeader);
- if ((MsrData & CacheInfoPtr->HeapBaseMask) == ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
+ if (((UINT64) (intptr_t) MsrData & CacheInfoPtr->HeapBaseMask) ==
+ ((UINT64) (intptr_t) HeapBufferPtr & CacheInfoPtr->HeapBaseMask)) {
if (((HEAP_MANAGER *) HeapBufferPtr)->Signature == HEAP_SIGNATURE_VALID) {
// This is not a bug, there are multiple premem basic entry points,
// and each will call heap init to make sure create struct will succeed.
@@ -180,7 +181,7 @@ HeapManagerInit (
}
// Set variable MTRR base and mask
- MsrData = ((UINT64) HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
+ MsrData = ((UINT64) (intptr_t)HeapBufferPtr & CacheInfoPtr->HeapBaseMask);
MsrMask = CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK;
MsrData |= 0x06;
@@ -666,34 +667,34 @@ VOID
// Firstly, we try to see if heap is in cache
BaseAddress = HeapGetCurrentBase (StdHeader);
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if ((HeapManager->Signature != HEAP_SIGNATURE_VALID) &&
(StdHeader->HeapStatus != HEAP_DO_NOT_EXIST_YET) &&
(StdHeader->HeapStatus != HEAP_LOCAL_CACHE)) {
// Secondly, we try to see if heap is in temp memory
BaseAddress = UserOptions.CfgHeapDramAddress;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
// Thirdly, we try to see if heap in main memory
// by locating with external buffer manager (IBV)
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
if (AgesaLocateBuffer (0, &AgesaBuffer) == AGESA_SUCCESS) {
- BaseAddress = (UINT64) AgesaBuffer.BufferPointer;
- HeapManager = (HEAP_MANAGER *) BaseAddress;
+ BaseAddress = (UINT64) (intptr_t) AgesaBuffer.BufferPointer;
+ HeapManager = (HEAP_MANAGER *) (intptr_t) BaseAddress;
if (HeapManager->Signature != HEAP_SIGNATURE_VALID) {
// No valid heap signature ever found, return a NULL pointer
- BaseAddress = NULL;
+ BaseAddress = (UINT64) (intptr_t) NULL;
}
} else {
// No heap buffer is allocated by external manager (IBV), return a NULL pointer
- BaseAddress = NULL;
+ BaseAddress = (UINT64) (intptr_t) NULL;
}
}
}
- return BaseAddress;
+ return (void *) (intptr_t) BaseAddress;
}
/*---------------------------------------------------------------------------------------
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