[coreboot] New patch to review for coreboot: 6a81b32 console: Support EARLY_CONSOLE correctly.
Hung-Te Lin (hungte@chromium.org)
gerrit at coreboot.org
Wed Feb 6 15:07:11 CET 2013
Hung-Te Lin (hungte at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2300
-gerrit
commit 6a81b32519a778849a597da79c347dc017da61ea
Author: Hung-Te Lin <hungte at chromium.org>
Date: Wed Feb 6 21:51:15 2013 +0800
console: Support EARLY_CONSOLE correctly.
Refines console source file dependency (especially for EARLY_CONSOLE), and
interprets printk/console_init according to EARLY_CONSOLE setting (no-ops if
EARLY_CONSOLE is not defined).
Change-Id: Idbbd3a26bc1135c9d3ae282aad486961fb60e0ea
Signed-off-by: Hung-Te Lin <hungte at chromium.org>
---
src/console/Makefile.inc | 8 ++++----
src/console/console.c | 8 +++++---
src/include/console/console.h | 16 ++++++++++++++--
src/include/uart.h | 4 ++--
4 files changed, 25 insertions(+), 11 deletions(-)
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 938dee3..9ce3474 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -9,13 +9,13 @@ smm-y += printk.c
smm-y += vtxprintf.c
smm-$(CONFIG_SMM_TSEG) += die.c
-romstage-y += vtxprintf.c
-romstage-$(CONFIG_EARLY_CONSOLE) += console.c
+romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c
+romstage-y += console.c
romstage-y += post.c
romstage-y += die.c
-bootblock-y += vtxprintf.c
-bootblock-$(CONFIG_EARLY_CONSOLE) += console.c
+bootblock-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c
+bootblock-y += console.c
bootblock-y += post.c
bootblock-y += die.c
diff --git a/src/console/console.c b/src/console/console.c
index d4b4b88..fc77df7 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -99,10 +99,10 @@ int console_tst_byte(void)
#else // __PRE_RAM__ ^^^ NOT defined vvv defined
-#include <uart.h>
-
void console_init(void)
{
+#if CONFIG_EARLY_CONSOLE
+
#if CONFIG_USBDEBUG
enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
early_usbdebug_init();
@@ -127,5 +127,7 @@ void console_init(void)
COREBOOT_BUILD
" starting...\n";
print_info(console_test);
+
+#endif /* CONFIG_EARLY_CONSOLE */
}
-#endif
+#endif /* __PRE_RAM__ */
diff --git a/src/include/console/console.h b/src/include/console/console.h
index edd49e0..497a517 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -74,6 +74,15 @@ void mainboard_post(u8 value);
void __attribute__ ((noreturn)) die(const char *msg);
int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
+#if defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE
+
+static inline void printk(int LEVEL, const char *fmt, ...);
+static inline void printk(int LEVEL, const char *fmt, ...) {
+ /* Do nothing. */
+}
+
+#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */
+
#undef WE_CLEANED_UP_ALL_SIDE_EFFECTS
/* We saw some strange effects in the past like coreboot crashing while
* disabling cache as ram for a maximum console log level of 6 and above while
@@ -97,7 +106,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
} \
} while(0)
-#else
+#else /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */
#define printk(LEVEL, fmt, args...) \
do { \
@@ -107,7 +116,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
do_printk(BIOS_NEVER, fmt, ##args); \
} \
} while(0)
-#endif
+
+#endif /* WE_CLEANED_UP_ALL_SIDE_EFFECTS */
+
+#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */
#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR))
#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR))
diff --git a/src/include/uart.h b/src/include/uart.h
index 2a72575..e424496 100644
--- a/src/include/uart.h
+++ b/src/include/uart.h
@@ -26,7 +26,7 @@
#ifndef UART_H
#define UART_H
-#if CONFIG_CONSOLE_SERIAL8250
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
#include <uart8250.h>
#endif
@@ -34,7 +34,7 @@
#include <cpu/samsung/exynos5-common/uart.h>
#endif
-#ifndef __ROMCC__
+#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART
unsigned char uart_rx_byte(void);
void uart_tx_byte(unsigned char data);
void uart_tx_flush(void);
More information about the coreboot
mailing list