[coreboot] Patch set updated for coreboot: 615a10b AMD/Persimmon: Add RTC init to CIMX SB800

[Mike Loptien (mike.loptien@se-eng.com)]

Mike Loptien (mike.loptien at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2444

-gerrit

commit 615a10be4efd0213cd6383506e4c63adf309031d
Author: Mike Loptien <mike.loptien at se-eng.com>
Date:   Fri Feb 22 13:18:31 2013 -0700

    AMD/Persimmon: Add RTC init to CIMX SB800
    
    Adding RTC init code to the Southbridge initialization
    code in 'late.c'.  This initializes the RTC so that the
    Date Alarm register is set to a valid value (0x00) at
    startup.  By setting the Date Alarm register to 0x00,
    it does not get evaluated along with the seconds,
    minutes, and hours when running fwts s3.
    
    This was tested on a Persimmon but will apply to
    other mainboards as well.
    
    Change-Id: Ica01572c23efa6d1c0fc422b5b2abf1b0f6eba71
    Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
---
 src/southbridge/amd/cimx/sb800/late.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index ef3a34b..0d9b5ef 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -128,6 +128,13 @@ static void lpc_init(device_t dev)
 
 	rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
 
+	/* Initialize the real time clock.
+	 * The 0 argument tells rtc_init not to
+	 * update CMOS unless it is invalid.
+	 * 1 tells rtc_init to always initialize the CMOS.
+	 */
+	rtc_init(0);
+
 	printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
 }