[coreboot] Patch set updated for coreboot: c4d3d45 AMD/Persimmon: Add RTC init to CIMX SB800
Mike Loptien (mike.loptien@se-eng.com)
gerrit at coreboot.org
Fri Feb 22 23:27:37 CET 2013
Mike Loptien (mike.loptien at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2488
-gerrit
commit c4d3d4517331a5fa735cfa05c43265f260dbd5d6
Author: Mike Loptien <mike.loptien at se-eng.com>
Date: Fri Feb 22 13:18:31 2013 -0700
AMD/Persimmon: Add RTC init to CIMX SB800
Adding RTC init code to the Southbridge initialization
code in 'late.c'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This was tested on a Persimmon but will apply to
other mainboards as well.
Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
---
src/southbridge/amd/cimx/sb800/late.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index ef3a34b..0d9b5ef 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -128,6 +128,13 @@ static void lpc_init(device_t dev)
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
+
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n");
}
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