[coreboot] Patch set updated for coreboot: cea84a1 Use defines for some i82801ex/gx registers
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Wed Feb 27 21:15:06 CET 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2530
-gerrit
commit cea84a104165c36e1b2d9f19539e04d59e4c9dda
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Tue Feb 26 19:21:39 2013 +0200
Use defines for some i82801ex/gx registers
Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/intel/i82801ex/i82801ex.h | 7 +++++++
src/southbridge/intel/i82801ex/lpc.c | 8 +++-----
src/southbridge/intel/i82801gx/i82801gx.h | 1 +
src/southbridge/intel/i82801gx/lpc.c | 2 +-
4 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h
index 67fecdd..3c7321a 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.h
+++ b/src/southbridge/intel/i82801ex/i82801ex.h
@@ -12,4 +12,11 @@ extern void i82801ex_enable(device_t dev);
#define RTC_CONF 0xd8
#define GEN_PMCON_3 0xa4
+#define PMBASE 0x40
+#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 4)
+#define GPIO_BASE 0x58
+#define GPIO_CNTL 0x5C
+#define GPIO_EN (1 << 4)
+
#endif /* I82801EX_H */
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 998360c..d0d5978 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -12,8 +12,6 @@
#include <arch/ioapic.h>
#include "i82801ex.h"
-#define ACPI_BAR 0x40
-#define GPIO_BAR 0x58
#define NMI_OFF 0
#define MAINBOARD_POWER_OFF 0
@@ -193,7 +191,7 @@ static void i82801ex_gpio_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
/* Find the GPIO bar */
- res = find_resource(dev, GPIO_BAR);
+ res = find_resource(dev, GPIO_BASE);
if (!res) {
return;
}
@@ -295,10 +293,10 @@ static void i82801ex_lpc_read_resources(device_t dev)
pci_dev_read_resources(dev);
/* Add the ACPI BAR */
- res = pci_get_resource(dev, ACPI_BAR);
+ res = pci_get_resource(dev, PMBASE);
/* Add the GPIO BAR */
- res = pci_get_resource(dev, GPIO_BAR);
+ res = pci_get_resource(dev, GPIO_BASE);
/* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 566311f..6561399 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address);
#define PMBASE 0x40
#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 7)
#define BIOS_CNTL 0xDC
#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index c6b76d3..45d5c12 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev)
/* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
- pci_write_config8(dev, ACPI_CNTL, 0x80);
+ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
*ioapic_index = 0;
*ioapic_data = (1 << 25);
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