[coreboot] New patch to review for coreboot: 85ffe9c Unify setting i82801g IOAPIC ID

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2546

-gerrit

commit 85ffe9cf809497193417109c290505af48d68f89
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Tue Feb 26 17:24:41 2013 +0200

    Unify setting i82801g IOAPIC ID
    
    Remove obscure local copy of writing the ioapic registers.
    
    Change-Id: Ia703eb394991bc97aacd872ae211eefbd03e68c3
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/i82801gx/lpc.c | 35 ++++++-----------------------------
 1 file changed, 6 insertions(+), 29 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 45d5c12..1033449 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -39,37 +39,12 @@
 
 typedef struct southbridge_intel_i82801gx_config config_t;
 
-static void i82801gx_enable_apic(struct device *dev)
+static void i82801gx_enable_acpi(struct device *dev)
 {
-	int i;
-	u32 reg32;
-	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
-	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
-
-	/* Enable ACPI I/O and power management.
-	 * Set SCI IRQ to IRQ9
+	/* Enable ACPI I/O range decode and ACPI power management.
+	 * Select SCI IRQ as IRQ9.
 	 */
 	pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-
-	*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
-
-	*ioapic_index = 0;
-	reg32 = *ioapic_data;
-	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
-	if (reg32 != (1 << 25))
-		die("APIC Error\n");
-
-	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
-	for (i=0; i<3; i++) {
-		*ioapic_index = i;
-		printk(BIOS_SPEW, "  reg 0x%04x:", i);
-		reg32 = *ioapic_data;
-		printk(BIOS_SPEW, " 0x%08x\n", reg32);
-	}
-
-	*ioapic_index = 3; /* Select Boot Configuration register. */
-	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
 }
 
 static void i82801gx_enable_serial_irqs(struct device *dev)
@@ -421,8 +396,10 @@ static void lpc_init(struct device *dev)
 	/* Set the value for PCI command register. */
 	pci_write_config16(dev, PCI_COMMAND, 0x000f);
 
+	i82801gx_enable_acpi(dev);
+
 	/* IO APIC initialization. */
-	i82801gx_enable_apic(dev);
+	set_ioapic_id(IO_APIC_ADDR, 0x02);
 
 	i82801gx_enable_serial_irqs(dev);