[coreboot] Patch merged into coreboot/master: fba42a7 Snow bootblock (bloated/debug version)

gerrit at coreboot.org gerrit at coreboot.org
Fri Jan 18 00:26:54 CET 2013

the following patch was just integrated into master:
commit fba42a793a67d8910b4ab7fdfb386bcda9896d13
Author: David Hendricks <dhendrix at chromium.org>
Date:   Thu Jan 17 15:07:35 2013 -0800

    Snow bootblock (bloated/debug version)
    This is the bloated Snow bootblock which includes:
    - SPI driver
    - UART, including requisite I2C, Maxim PMIC, and clock config code.
    - Adjustments for magic offsets (id section, stack pointer address)
    This is just a temporary solution until we have romstage loading.
    Once that happens, we'll rip out all but the code necessary for
    copying SPI ROM content into SRAM.
    Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be
    Signed-off-by: David Hendricks <dhendrix at chromium.org>
    Reviewed-on: http://review.coreboot.org/2170
    Tested-by: build bot (Jenkins)
    Reviewed-by: Ronald G. Minnich <rminnich at gmail.com>

Build-Tested: build bot (Jenkins) at Fri Jan 18 00:23:12 2013, giving +1
Reviewed-By: Ronald G. Minnich <rminnich at gmail.com> at Fri Jan 18 00:26:53 2013, giving +2
See http://review.coreboot.org/2170 for details.


More information about the coreboot mailing list