[coreboot] Re : Re: Big picture of recent ARM patches?
echelon at free.fr
echelon at free.fr
Fri Jan 18 23:18:20 CET 2013
You said :
> - we don't own the first two stages of firmware, they are binary blobs
> and one of them is in the mask rom but we have to deal with it, this is how things are going to be on
> most CPUs in coming years.
My questions : MOST or ALL? Will this be true for x86 too?
----- Mail d'origine -----
De: ron minnich <rminnich at gmail.com>
À: Paul Menzel <paulepanter at users.sourceforge.net>
Cc: coreboot at coreboot.org
Envoyé: Fri, 18 Jan 2013 18:08:24 +0100 (CET)
Objet: Re: [coreboot] Big picture of recent ARM patches?
I'm delighted that you are interested!
This is our first multi-arch port in 10 years. The platform we are
porting to is not without its difficulties:
- rom is not memory addressed
- we don't own the first two stages of firmware, they are binary blobs
and one of them is in the mask rom
but we have to deal with it, this is how things are going to be on
most CPUs in coming years.
- we don't have a convenient serial port
- no really good jtag path
This is one of the harder platforms we've worked with.
The guiding principle is to make the ARM port match how we do things
in coreboot today:bootblock, romstage, ramstage. But to get here we
have to pollute things a bit at first. You see this in the serial port
in the bootblock, which we hope to remove sometime next week.
I like committing these intermediate targets. This is a good case
study of how to do a part, which you can refer to in coming years for
new ports. I'd be even happier if we got you folks interested in
taking a look at the code too. Just be aware that some of this is
pretty kludgy, and will change, but I really want people to see the
ugly parts of a port. Just showing a final version would not be as
I doubt we've got time to do a full roadmap, but I have time to answer
And maybe you can take your -1 off my firmware CL :-)
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