[coreboot] New patch to review for coreboot: 16b2edf AGESA: Fix CR0_PE bit define

[Aladyshev Konstantin (kostr@list.ru)]

Aladyshev Konstantin (kostr at list.ru) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2591

-gerrit

commit 16b2edf6b25b92243be5669afa4dc3dacd1a0f4d
Author: Konstantin Aladyshev <aladyshev at nicevt.ru>
Date:   Wed Mar 6 22:13:42 2013 +0400

    AGESA: Fix CR0_PE bit define
    
    AGESA code has wrong definition of CR0_PE bit (1 instead of 0).
    
    PE [Protected Mode Enable] is 0 bit in CR0 register
    (If PE=1, system is in protected mode, else system is in real mode)
    
    Bit 1 is MP [Monitor co-processor]
    (Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)
    
    System uses CR0_PE define, but I didn't expect any consequences because of this bug.
    
    Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
    Signed-off-by: Konstantin Aladyshev <aladyshev at nicevt.ru>
---
 src/vendorcode/amd/agesa/f10/gcccar.inc | 2 +-
 src/vendorcode/amd/agesa/f12/gcccar.inc | 2 +-
 src/vendorcode/amd/agesa/f14/cpcar.inc  | 2 +-
 src/vendorcode/amd/agesa/f14/gcccar.inc | 2 +-
 src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc
index a24c0b7..47909e1 100755
--- a/src/vendorcode/amd/agesa/f10/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f10/gcccar.inc
@@ -100,7 +100,7 @@ CU_CFG3                  =      0x0C001102B      /* Combined Unit Configuration
     COMBINE_CR0_CD       =      49               /*   Combine CR0.CD for both cores of a compute unit */                  
                                                                                                              
                                                                                                              
-CR0_PE                  = 1           # Protection Enable
+CR0_PE                  = 0           # Protection Enable
 CR0_NW                  = 29          # Not Write-through
 CR0_CD                  = 30          # Cache Disable
 CR0_PG                  = 31          # Paging Enable
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 63f3ea9..0b7b289 100755
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -100,7 +100,7 @@ CU_CFG3                  =      0x0C001102B      /* Combined Unit Configuration
     COMBINE_CR0_CD       =      49               /*   Combine CR0.CD for both cores of a compute unit */                  
                                                                                                              
                                                                                                              
-CR0_PE                  = 1           # Protection Enable
+CR0_PE                  = 0           # Protection Enable
 CR0_NW                  = 29          # Not Write-through
 CR0_CD                  = 30          # Cache Disable
 CR0_PG                  = 31          # Paging Enable
diff --git a/src/vendorcode/amd/agesa/f14/cpcar.inc b/src/vendorcode/amd/agesa/f14/cpcar.inc
index b9aaa91..ce33f62 100644
--- a/src/vendorcode/amd/agesa/f14/cpcar.inc
+++ b/src/vendorcode/amd/agesa/f14/cpcar.inc
@@ -97,7 +97,7 @@ CU_CFG3                 EQU 0C001102Bh  ; Combined Unit Configuration 3
     COMBINE_CR0_CD          EQU 49      ;   Combine CR0.CD for both cores of a compute unit
 
 
-CR0_PE                  EQU 1           ; Protection Enable
+CR0_PE                  EQU 0           ; Protection Enable
 CR0_NW                  EQU 29          ; Not Write-through
 CR0_CD                  EQU 30          ; Cache Disable
 CR0_PG                  EQU 31          ; Paging Enable
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index d81b6af..b977f4f 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -114,7 +114,7 @@ CU_CFG3                  =      0x0C001102B      /* Combined Unit Configuration
     COMBINE_CR0_CD       =      49               /*   Combine CR0.CD for both cores of a compute unit */
 
 
-CR0_PE                  = 1           # Protection Enable
+CR0_PE                  = 0           # Protection Enable
 CR0_NW                  = 29          # Not Write-through
 CR0_CD                  = 30          # Cache Disable
 CR0_PG                  = 31          # Paging Enable
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index 423d404..dda35e9 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -115,7 +115,7 @@ CU_CFG3                  =      0x0C001102B      /* Combined Unit Configuration
     COMBINE_CR0_CD       =      49               /*   Combine CR0.CD for both cores of a compute unit */
 
 
-CR0_PE                  = 1           # Protection Enable
+CR0_PE                  = 0           # Protection Enable
 CR0_NW                  = 29          # Not Write-through
 CR0_CD                  = 30          # Cache Disable
 CR0_PG                  = 31          # Paging Enable